AD9913 [ADI]
Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer; 低功耗250 MSPS 10位DAC 1.8 V CMOS直接数字频率合成器
| 型号： | AD9913 |
| 厂家： | 
ADI |
| 描述： | Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| 文件： | 总32页 (文件大小：687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power 250 MSPS 10-Bit DAC 1.8 V
CMOS Direct Digital Synthesizer
AD9913
FEATURES
GENERAL DESCRIPTION
50 mW at up to 250 MSPS internal clock speed
100 MHz analog output
Integrated 10-bit DAC
0.058 Hz or better frequency resolution
0.022° phase tuning resolution
Programmable modulus in frequency equation
The AD9913 is a complete direct digital synthesizer (DDS)
designed to meet the stringent power consumption limits of
portable, handheld, and battery-powered equipment. The
AD9913 features a 10-bit digital-to-analog converter (DAC)
operating up to 250 MSPS. The AD9913 uses advanced DDS
technology, coupled with an internal high speed, high
Phase noise ≤ –135 dBc per Hz @ 1 kHz offset (DAC output)
(<115 dBc per Hz when using on-board PLL multiplier)
Excellent dynamic performance
>80 dB SFDR @ 100 MHz ( 100 kHz offset) AOUT
Automatic linear frequency sweeping capability
8 frequency or phase offset profiles
performance DAC to form a complete, digitally-program-
mable, high frequency synthesizer capable of generating a
frequency agile analog output sinusoidal waveform at up to
100 MHz.
The AD9913 provides fast frequency hopping and fine tuning
resolution. The AD9913 also offers fine resolution phase offset
control. Control words are loaded into the AD9913 through the
serial or parallel I/O port. The AD9913 also supports a user-
defined linear sweep mode of operation for generating highly
linearized swept waveforms of frequency. To support various
methods of generating a system clock, the AD9913 includes an
oscillator, allowing a simple crystal to be used as the frequency
reference, as well as a high speed clock multiplier to convert the
reference clock frequency up to the full system clock rate. For
power saving considerations, many of the individual blocks of
the AD9913 can be powered down when not in use.
1.8 V power supply
Software and hardware controlled power-down
Parallel and serial programming options
32-lead LFCSP package
Optional PLL REF_CLK multiplier
Internal oscillator (can be driven by a single crystal)
Phase modulation capability
APPLICATIONS
Portable and handheld equipment
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
The AD9913 operates over the extended industrial temperature
range of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
AD9913
10-BIT
DAC
DDS
REF_CLK INPUT
CIRCUITRY
TIMING AND
CONTROL LOGIC
USER INTERFACE
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD9913
TABLE OF CONTENTS
Features .............................................................................................. 1
I/O Port........................................................................................ 13
Profile Selections ........................................................................ 13
Modes of Operation ....................................................................... 14
Single Tone Mode....................................................................... 14
Direct Switch Mode ................................................................... 14
Programmable Modulus Mode ................................................ 14
Linear Sweep Mode.................................................................... 14
Clock Input (REF_CLK)................................................................ 18
Power-Down Features................................................................ 21
I/O Programming........................................................................... 22
Serial programming ................................................................... 22
Parallel I/O Programming......................................................... 23
Register Map and Bit Descriptions .............................................. 25
Register Map ............................................................................... 25
Register Bit Descriptions........................................................... 27
Outline Dimensions....................................................................... 31
Ordering Guide .......................................................................... 31
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Equivalent Circuits....................................................................... 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 8
Applications Circuits...................................................................... 11
Theory of Operation ...................................................................... 12
DDS Core..................................................................................... 12
Auxiliary Accumulator .............................................................. 13
10-Bit DAC.................................................................................. 13
REVISION HISTORY
10/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD9913
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD (1.8 V), DVDD (1.8 V), and DVDD_I/O = 1.8 V 5ꢀ, T = 25°C, RSET = 4.64 kΩ, DAC full-scale current = 2 mA, external
reference clock frequency = 250 MHz with REF_CLK multiplier disabled, unless otherwise noted.
Table 1.
Parameter
Conditions/Comments
Min
Typ
Max
Unit
REF_CLK INPUT CHARACTERISTICS
Frequency Range
REF_CLK Multiplier
Disabled
Enabled
Full temperature range
VCO1
250
250
83
250
250
MHz
MHz
MHz
MHz
MHz
μs
MHz
V
V
REF_CLK Input Divider Frequency
VCO Oscillation Frequency
16
100
VCO2
PLL Lock Time
External Crystal Mode
CMOS Mode
25 MHz reference clock, 10× PLL
60
25
VIH
VIL
0.9
0.65
Input Capacitance
3
pF
Input Impedance (Differential)
Input Impedance (Single-Ended)
Duty Cycle
2.7
1.35
kΩ
kΩ
%
45
55
REF_CLK Input Level
355
1000
mV p-p
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
AC Voltage Compliance Range
SPURIOUS-FREE DYNAMIC RANGE
SERIAL PORT TIMING CHARACTERISTICS
SCLK Frequency
4.6
−6
+0.1
+0.4
+0.5
mA
%FS
μA
LSB
LSB
mV
−14
−0.4
−0.5
±400
Refer to Figure 6
32
2
MHz
ns
ns
SCLK Pulse Width
Low
High
17.5
3.5
SCLK Rise/Fall Time
ns
Data Setup Time to SCLK
Data Hold Time to SCLK
Data Valid Time in Read Mode
PARALLEL PORT TIMING CHARACTERISTICS
PCLK Frequency
5.5
0
ns
ns
ns
22
33
MHz
ns
ns
PCLK Pulse Width
Low
High
10
20
PCLK Rise/Fall Time
2
8
ns
ns
ns
ns
Address/Data Setup Time to PCLK
Address/Data Hold Time to PCLK
Data Valid Time in Read Mode
IO_UPDATE/PROFILE(2:0) TIMING
Setup Time to SYNC_CLK
3.0
0.3
0.5
1
ns
Hold Time to SYNC_CLK
SYNC_CLK cycles
Rev. 0 | Page 3 of 32
AD9913
Parameter
Conditions/Comments
Min
Typ
Max
Unit
MISCELLANEOUS TIMING CHARACTERISTICS
Wake-Up Time1
Fast Recovery Mode
Full Sleep Mode
1
60
SYSCLK cycles2
ꢀs
Reset Pulse Width High
DATA LATENCY (PIPELINE DELAY)
Frequency, Phase-to-DAC Output
Frequency-to-DAC Output
Phase-to-DAC Output
5
SYSCLK cycles
Matched latency enabled
Matched latency disabled
Matched latency disabled
11
11
10
14
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
Delta Tuning Word-to-DAC Output (Linear Sweep)
CMOS LOGIC INPUTS
Logic 1 Voltage
1.2
V
Logic 0 Voltage
0.4
V
Logic 1 Current
Logic 0 Current
Input Capacitance
−700
−700
+700
+700
nA
nA
pF
3
CMOS LOGIC OUTPUTS
Logic 1 Voltage
Logic 0 Voltage
1 mA load
1.5
V
V
0.125
POWER SUPPLY CURRENT
DVDD (1.8 V) Pin Current Consumption
DAC_CLK_AVDD (1.8 V)
DAC_AVDD (1.8 V) Pin Current Consumption
PLL_AVDD (1.8 V)
CLK_AVDD (1.8 V) Pin Current Consumption
POWER CONSUMPTION
Single Tone Mode
46.5
4.7
6.2
1.8
4.3
mA
mA
mA
mA
mA
PLL enabled, CMOS input
PLL disabled, differential input
PLL enabled, XTAL input
PLL disabled
50
57
52
66.5
70.5
68.5
94.6
98.4
mW
mW
mW
mW
mW
Modulus Mode
Linear Sweep Mode
Power-Down
Full
PLL disabled
15
44.8
mW
mW
Safe
PLL enabled
PLL Modes
VCO 1
Differential Input Mode
CMOS Input Mode
Crystal Mode
VCO 2
11
7.5
5.4
mW
mW
mW
Differential Input Mode
CMOS Input Mode
Crystal Mode
15
11.5
9.4
mW
mW
mW
1 Refer to the Power-Down Features section.
2 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not used, the
SYSCLK frequency is the same as the external reference clock frequency.
Rev. 0 | Page 4 of 32
AD9913
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Maximum Junction Temperature
AVDD, DVDD
150°C
2 V
Digital Output Current
Storage Temperature
Operating Temperature
Lead Temperature (Soldering, 10 sec)
θJA
5 mA
–65°C to +150°C
–40°C to +105°C
300°C
ESD CAUTION
36.1°C/W
4.2°C/W
θJC
EQUIVALENT CIRCUITS
DIGITAL INPUTS
DVDD_I/O
DAC OUTPUTS
AVDD
INPUT
IOUT
IOUT
AVOID OVERDRIVING DIGITAL INPUTS.
FORWARD BIASING ESD DIODES MAY
COUPLE DIGITAL NOISE ONTO POWER
PINS.
MUST TERMINATE OUTPUTS TO AGND
FOR CURRENT FLOW. DO NOT EXCEED
THE OUTPUT VOLTAGE COMPLIANCE
RATING.
Figure 2. Equivalent Input and Output Circuits
Rev. 0 | Page 5 of 32
AD9913
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PS2/ADR5/D5
PS1/ADR4/D4
PS0/ADR3/D3
DVDD
1
2
3
4
5
6
7
8
24 RSET
23 AGND
22 AVDD
21 AGND
20 IOUT
19 IOUT
18 AGND
17 AVDD
PIN 1
INDICATOR
AD9913
TOP VIEW
(Not to Scale)
DGND
ADR2/D2
ADR1/D1
ADR0/D0
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
I/O Description
1
PS2/ADR5/D5
I/O Multipurpose pin: Profile Select Pin (PS2) in Direct Switch Mode, Parallel Port Address Line (ADR5), and
Data Line (D5) to program registers.
2
3
PS1/ADR4/D4
PS0/ADR3/D3
I/O Multipurpose pin: Profile Select Pin (PS1) in Direct Switch Mode or Linear Sweeping Mode, Parallel Port
Address Line (ADR4), and Data Line (D4) to program registers.
I/O Multipurpose pin: Profile Select Pin (PS0) in Direct Switch Mode or Linear Sweeping Mode, Parallel Port
Address Line (ADR3), and Data Line (D3) to program registers.
4
5
6
7
8
9
DVDD
DGND
ADR2/D2
ADR1/D1
ADR0/D0
SYNC_CLK
I
I
Digital Power Supply (1.8 V).
Digital Ground.
I/O Parallel Port Address Line 2 and Data Line 2.
I/O Parallel Port Address Line 1and Data Line 1.
I/O Parallel Port Address Line 0 and Data Line 0.
O
Clock Out. The profile pins [PS0:PS2] and the IO_UPDATE pin (Pin 27) should be set up to the rising
edge of this signal to maintain constant pipe line delay through the device.
10
SER/PAR
AGND
I
I
Serial Port and Parallel Port Selection. Logic low = serial mode; logic high = parallel mode.
Analog Ground.
11, 15,
18, 21,
23
12, 16,
17, 22
AVDD
I
Analog Power Supply (1.8 V).
13
14
19
20
24
REF_CLK
REF_CLK
IOUT
I
I
Reference Clock Input. See the REF_CLK Overview section for more details.
Complementary Reference Clock Input. See the REF_CLK Overview section for more details.
Open Source DAC Complementary Output Source. Current mode. Connect through 50 Ω to AGND.
Open Source DAC Output Source. Current mode. Connect through 50 Ω to AGND.
Analog Reference. This pin programs the DAC output full-scale reference current. Attach a 4.64 kΩ
resistor to AGND.
O
O
I
IOUT
RSET
25
MASTER_RESET
I
Master Reset, Digital Input (Active High). This pin clears all memory elements and reprograms registers
to default values.
Rev. 0 | Page 6 of 32
AD9913
Pin No.
Mnemonic
I/O Description
26
PWR_DWN_CTL
I
External Power-Down, Digital Input (Active High). A high level on this pin initiates the currently
programmed power-down mode. See the Power-Down Features section for further details. If unused,
tie to ground.
27
28
IO_UPDATE
CS
I
I
I/O Update; Digital Input. A high on this pin indicates a transfer of the contents of the I/O buffers to the
corresponding internal registers.
Chip Select for Serial and Parallel Port. Digital input (active low). Bringing this pin low enables the
AD9913 to detect serial (SCLK) or parallel (PCLK) clock rising/falling edges. Bringing this pin high
causes the AD9913 to ignore input on the data pins.
29
30
31
32
SDIO(WR/RD)
SCLK/PCLK
ADR7/D7
I/O Bidirectional Data Line for Serial Port Operation and Write/Read Enable for Parallel Port Operation.
Input Clock for Serial and Parallel Port.
I/O Parallel Port Address Line 7 and Data Line 7.
I/O Parallel Port Address Line 6 and Data Line 6.
I
ADR6/D6
Rev. 0 | Page 7 of 32
AD9913
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
−20
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−40
−60
−80
−100
−120
0
20
40
60
80
100
120
99.758381 99.763381 99.768381 99.773381 99.778381 99.783381
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. Wideband SFDR @ 99.76 MHz fOUT
Figure 7. Narrow-Band SFDR @ 99.76 MHz fOUT
(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)
(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
−20
−40
−60
−80
−100
−120
0
20
40
60
80
100
120
25.124918 25.134918 25.144918 25.154918 25.164918 25.174918
25.129918 25.139918 25.149918 25.159918 25.169918
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. Wideband SFDR @ 25.14 MHz fOUT
(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)
Figure 8. Narrow-Band SFDR @ 25.14 MHz fOUT
(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)
–50
–55
–60
–65
–70
–75
–80
–85
–90
–50
–55
1.7V
1.8V
+85ºC
–60
–40°C
+25°C
–65
–70
–75
–80
–85
–90
1.9V
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
fOUT (% of System Clock)
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
fOUT (% of System Clock)
Figure 6. SFDR vs. Supply Variation
Figure 9. SFDR vs. Temperature
(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)
(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)
Rev. 0 | Page 8 of 32
AD9913
–50
–55
–60
–65
–70
–75
–80
–85
–90
−50
−60
−70
−80
−90
39.88%
99MHz
49MHz
−100
−110
−120
−130
−140
−150
26.58%
10.21%
25MHz
12.5MHz
0
50
100
150
200
250
100
1k
10k
100k
1M
10M
100M
SYSTEM CLOCK (MHz)
FREQUENCY (MHz)
Figure 12. Absolute Phase Noise vs. fOUT Using the Internal PLL
(REF_CLK 25 MHz × 10 = 250 MHz Using PLL)
Figure 10. SFDR vs. System Clock Frequency (PLL Bypassed)
–100
–50
92.3MHz
48.9MHz
23.1MHz
6.1MHz
PLL ×10
REFSPUR
BYPASS
–55
–60
–65
–70
–75
–80
–85
–90
–110
–120
–130
–140
–150
–160
–170
10
100
1k
10k
100k
1M
10M
100M
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
fOUT (% of System Clock)
FREQUENCY (MHz)
Figure 11. Residual Phase Noise vs. fOUT (PLL Bypassed)
Figure 13. SFDR Without the Internal PLL
(REF_CLK = 25 MHz × 10 = 250 MHz Using PLL, 4 mA DAC Full-Scale Current)
Rev. 0 | Page 9 of 32
AD9913
80
70
60
50
40
30
20
10
0
−60
−80
DIFF INPUT LINEAR SWEEP
CMOS INPUT LINEAR SWEEP
VCO 1
VCO 2
−100
−120
−140
DIFF INPUT SINGLE TONE
CMOS INPUT SINGLE TONE
−160
50
70
90
110 130 150 170 190 210 230 250
100
1k
10k
100k
1M
10M
100M
SYSTEM CLOCK FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. Power Dissipation vs. System Clock Frequency
vs. Clock Input Mode
Figure 14. Absolute Phase Noise, VCO1 vs. VCO2
40
35
30
25
20
15
10
5
DVDD
AVDD (PLL)
AVDD (CLK)
AVDD (DAC)
AVDD (DAC CLK)
0
50
70
90
110 130 150 170 190 210 230 250
SYSTEM CLOCK FREQUENCY (MHz)
Figure 15. Power Supply Current Domains
(CMOS Input Mode, 4 mA DAC Full-Scale Current, Single Tone)
Rev. 0 | Page 10 of 32
AD9913
APPLICATIONS CIRCUITS
LO
+
–
+
–
SPLITTER
–
+
SIDEBAND
SELECTION
FILTER
AD9913
–
ADC
Figure 17. RFID Block Diagram (Only I-Channel of Receiver Shown)
INPUT
LOW-PASS
FILTER
SIGNAL
BAND-PASS
FILTER
VGA
+
–
VIDEO
FILTER
INPUT
ATTENUATOR
LOCAL
OSCILLATOR
AD9913 AS
SWEEP
GENERATOR
CRT DISPLAY
Figure 18. Handheld Spectrum Analyzer
Rev. 0 | Page 11 of 32
AD9913
THEORY OF OPERATION
The FTW required to generate a desired value of fOUT is found
by solving Equation 1 for FTW as given in Equation 2
DDS CORE
The DDS block generates a reference signal (sine or cosine
based on the selected DDS sine output bit). The parameters of
the reference signal (frequency and phase), are applied to the
DDS at its frequency and phase offset control inputs, as shown
in Figure 19.
⎛
⎜
⎝
⎞
⎟
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
fOUT
fSYSCLK
32
⎜
FTW = round 2
(2)
⎟
⎠
where the round(x) function rounds the argument (the value of
x) to the nearest integer. This is required because the FTW is
constrained to be an integer value.
DDS SIGNAL CONTROL PARAMETERS
PHASE
OFFSET
CONTROL
14
For applications where rounding to the nearest available fre-
quency is not acceptable, programmable modulus mode enables
additional options.
MSB ALIGNED
32-BIT
ACCUMULATOR
32
ANGLE
TO
AMPLITUDE
CONVERSION
(SINE OR
COSINE)
The relative phase of the DDS signal can be digitally controlled
by means of a 14-bit phase offset word (POW). The phase offset
is applied prior to the angle-to-amplitude conversion block
internal to the DDS core. The relative phase offset (Δθ) is given by
32
32
10
32 15
15
MSBs
FREQUENCY
CONTROL
D Q
R
TO DAC
SYSTEM
CLOCK
ACCUMULATOR
RESET
POW
⎛
⎜
⎝
⎞
⎟
⎠
Figure 19. DDS Block Diagram
2π
214
Δθ =
The output frequency (fOUT) of the AD9913 is controlled by the
frequency tuning word (FTW) at the frequency control input to
the DDS. In all modes except for programmable modulus, the
relationship between fOUT, FTW, and fSYSCLK is:
POW
⎛
⎜
⎝
⎞
⎟
⎠
360
214
where the upper quantity is for the phase offset expressed as
radian units and the lower quantity as degrees. To find the
POW value necessary to develop an arbitrary Δθ, solve the
above equation for POW and round the result (in a manner
similar to that described for finding an arbitrary FTW in
Equation 1 and Equation 2).
FTW
⎛
⎜
⎝
⎞
⎟
⎠
fOUT
=
f
(1)
SYSCLK
232
where FTW is a 32-bit integer ranging in value from 0 to
2,147,483,647 (231 − 1), which represents the lower half of the
full 32-bit range. This range constitutes frequencies from dc to
Nyquist (that is, ½ fSYSCLK).
PHASE
ACCUMULATOR
PHASE
OFFSET
DDS CORE
32
AUXILIARY
ACCUMULATOR
IOUT
IOUT
0
1
0
1
ANGLE TO
AMPLITUDE
–1
DAC
Z
32
14
14
RSET
32
32
32
10
EXTERNAL
2
0
1
PROFILE
SELECTIONS
INTERNAL
FTW
POW
REGISTER MAP AND TIMING CONTROL
PLL
MULTIPLIER
CLOCK
I/O PORT
CLOCK PORT
SELECTION
Figure 20. Detailed Block Diagram
Rev. 0 | Page 12 of 32
AD9913
5
4
3
2
1
0
AUXILIARY ACCUMULATOR
In addition to the phase accumulator of the DDS, the AD9913
has an auxiliary accumulator. This accumulator can be con-
figured to support either an automatic sweep of one of the
programmable characteristics of the DDS output (frequency or
phase), or it can be configured to implement a change in the
denominator of the frequency equation given in the DDS Core
section. For further details, refer to the Programmable Modulus
Mode section.
10-BIT DAC
The AD9913 incorporates an integrated 10-bit, current output
DAC. The output current is delivered as a balanced signal using
two outputs. The use of balanced outputs reduces the potential
amount of common-mode noise present at the DAC output,
offering the advantage of an increased signal-to-noise ratio. An
external resistor (RSET) connected between the RSET pin and
AGND establishes the reference current. The full-scale output
current of the DAC (IOUT) is produced as a scaled version of the
reference current. The recommended value of RSET is 4.62 kΩ.
0
200
400
600
800
1000
1200
DAC CODE
Figure 21. DAC Output Current vs. DAC FS Bits
Pay careful attention to the load termination to ensure that the
output voltage remains within the specified compliance range;
voltages developed beyond this range cause excessive distortion
and can damage the DAC output circuitry.
I/O PORT
The following equation computes the typical full-scale current
with respect to the Rset resistor value and the gain control
setting:
The AD9913 I/O port can be configured as a synchronous serial
communications port that allows easy interface to many industry-
standard microcontrollers and microprocessors. The serial I/O port
is compatible with most synchronous transfer formats, including
both the Motorola 6905/11 SPI and Intel 8051 SSR protocols. For
faster programming requirements, a parallel mode is also provided.
0.0206
RSET
I
OUT(x,RSET ) =
× 1+ x
( )
The DAC is designed to operate with full-scale current values
up to 4.58 mA. Based on the equation and assuming a 4.62 kΩ
resistor value for RSET, and x = 0x1FF, the nominal output
current for the DAC is 2.28 mA.
PROFILE SELECTIONS
The AD9913 supports the use of profiles, which consist of a group
of eight registers containing pertinent operating parameters for
a particular operating mode. Profiles enable rapid switching
between parameter sets. Profile parameters are programmed via
the I/O port. Once programmed, a specific profile is activated
by means of Register CFR1 Bits [22:20], or three external profile
select pins. The external profile pins option is only available in
serial mode.
Figure 17 shows the range of DAC output current vs. the DAC
FS value assuming an RSET value of 4.62 kΩ.
Rev. 0 | Page 13 of 32
AD9913
PROGRAMMABLE MODULUS MODE
MODES OF OPERATION
In programmable modulus mode, the auxiliary accumulator is
used to alter the frequency equation of the DDS core, making it
possible to implement fractions which are not restricted to a
power of 2 in the denominator.
The AD9913 operates in four modes:
•
•
•
•
Single tone
Direct switch
Programmable modulus
Linear sweep
A standard DDS is restricted to powers of 2 as a denominator
because the phase accumulator is a set of bits as wide as the
frequency tuning word. When in programmable modulus
mode, the frequency equation becomes
f0 = (FTW)(fS)/x with 0 ≤ FTW ≤ 231
f0 = fS × (1 − (FTW/x)) with 231 < FTW < 232 − 1
where 0 ≤ x ≤ 232.
The modes relate to the data source used to supply the DDS
with its signal control parameters: frequency, phase, or ampli-
tude. The partitioning of the data into different combinations
of frequency, phase, and amplitude is handled automatically
based on the mode and/or specific control bits.
SINGLE TONE MODE
When in programmable modulus mode, the auxiliary accumu-
lator is set up to roll over before it reaches full capacity. Every
time it rolls over, an extra LSB value is added to the phase
accumulator. In order to determine the values that must be
programmed in the registers, the user must define the desired
output to sampling clock frequency as a ratio of integers (M/N,
where N must not exceed 232). N should be programmed into
Register 0x06 [63:32].
Single tone mode is the default operational mode and is active
when both the direct switch mode bit and the auxiliary
accumulator enable bit are not set. This mode outputs a single
frequency as programmed by the user in the frequency tuning
word (FTW) register. A phase offset value is also available in
single tone mode via the POW register.
DIRECT SWITCH MODE
Register 0x06 [31:0] must be programmed with the FTW which
Direct switch mode enables FSK or PSK modulation. This mode
simply selects the frequency or phase value programmed into
the profile registers. Frequency or phase is determined by the
destination bits in CFR1 [13:12]. Direct switch mode is enabled
using the direct switch mode active bit in register CFR1 [16].
is the integer portion of ((232 × f0)/fS).
Finally, Register 0x07 [31:0] must be programmed with the
modulus step which is the remainder of ((232 × f0)/fS).
LINEAR SWEEP MODE
Two approaches are designed for switching between profile
registers. The first is programming the internal profile control
bits, CFR1 [22:20], to the desired value and issuing an
IO_UPDATE. The second approach, with higher data
throughput, is achieved by changing the profile control pins
[2:0]. Control bit CFR1 [27] is for selection between the two
approaches. The default state uses the profile pins.
One purpose of linear sweep mode is to provide better
bandwidth containment compared to direct switch mode by
enabling more gradual, user-defined changes between a starting
point (S0) to an endpoint (E0). The auxiliary accumulator
enable bit is located in Register CFR1 [11]. Linear sweep uses
the auxiliary accumulator to sweep frequency or phase from S0
to E0. A frequency or phase sweep is determined by the
destination bits in CFR1 [13:12]. The trigger to initiate the
sweep can be edge or level triggered. This is determined by
Register CFR1 [9]. Note that, in level triggered mode, the sweep
automatically repeats as long as the appropriate profile pin is
held high.
To perform 8-tone FSK or PSK, program the FTW word or
phase offset word in each profile. The internal profile control
bits or the profile pins are used for the FSK or PSK data.
Table 4 shows the relationship between the profile selection pin
or bit approach.
In linear sweep mode, S0 and E0 (upper and lower limits) are
loaded into the linear sweep parameter register (Register 0x06).
If configured for frequency sweep, the resolution is 32-bits. For
phase sweep, the resolution is 14 bits. When sweeping the
phase, the word value must be MSB-aligned; unused bits are
ignored. The profile pins or the internal profile bits trigger and
control the direction (up/down) of the linear sweep for
Table 4. Profile Selection
Profile Pins PS [2:0] or CFR1 Bits [22:20] Profile Selection
000
001
010
011
100
101
110
111
Profile 0
Profile 1
Profile 2
Profile 3
Profile 4
Profile 5
Profile 6
Profile 7
frequency or phase. Table 5 depicts the direction of the sweep.
Rev. 0 | Page 14 of 32
AD9913
Table 5. Determining the Direction of the Linear Sweep
For a piecemeal or a nonlinear transition between S0 and E0,
the delta tuning words and ramp rate words can be reprogram-
med during the transition.
Profile Pins [2:0] or CFR1 Bits [22:20]
Linear Sweep Mode
x001
Sweep off
Ramp up
Ramp down
Bidirectional ramp
x011
The formulas for calculating the step size of RDW or FDW are
x101
RDW
x111
⎛
⎜
⎝
⎞
⎟
⎠
FrequencyStep =
f
(MHz)
SYSCLK
232
1 x = don’t care.
πRDW
Note that if the part is used in parallel port programming mode,
the sweep mode is only determined by the internal profile
control bits, CFR1 [22:20]. If the part is used in serial port
programming mode, either the internal profile control bits or
the external profile select pins can work as the sweep control.
CFR1 [27] selects between these two approaches.
⎛
⎜
⎝
⎞
⎟
⎠
PhaseStep =
PhaseStep =
(radians)
(degrees)
213
45RDW
⎛
⎜
⎝
⎞
⎟
⎠
211
The formula for calculating delta time from RSRR or FSRR is
Δt = RSRR / fSYSCLK (Hz)
(
)
Setting the Slope of the Linear Sweep
The slope of the linear sweep is set by the intermediate step size
(delta tuning word) between S0 and E0 (see Figure 22) and the
time spent (sweep ramp rate word) at each step. The resolution
of the delta tuning word is 32 bits for frequency and 14 bits for
phase. The resolution for the delta ramp rate word is 16 bits.
At 250 MSPS operation, (fSYSCLK =250 MHz). The minimum time
interval between steps is 1/250 MHz × 1 = 4 ns. The maximum
time interval is (1/250 MHz) × 65,535= 262 μs.
Frequency Linear Sweep Example
In linear sweep mode, when sweeping from low to high, the
RDW is applied to the input of the auxiliary accumulator and
the RSRR register is loaded into the sweep rate timer.
In linear sweep mode, the user programs a rising delta word
(RDW, Register 0x07) and a rising sweep ramp rate (RSRR,
Register 0x08). These settings apply when sweeping from S0 to
E0. The falling delta word (FDW, Register 0x07) and falling
sweep ramp rate (FSRR, Register 0x08) apply when sweeping
from E0 to S0.
The RDW accumulates at the rate given by the ramp rate
(RSRR) until the output equals the upper limit in the linear
sweep parameter register (Register 0x06). The sweep is then
complete.
Note that if the auxiliary accumulator is allowed to overflow, an
uncontrolled, continuous sweep operation occurs. To avoid this,
the magnitude of the rising or falling delta word should be
smaller than the difference between full-scale and the E0 value
(full-scale − E0). For a frequency sweep, full-scale is 232 − 1. For
a phase sweep, full-scale is 214 − 1.
When sweeping from high to low, the FDW is applied to the
input of the auxiliary accumulator and the FSRR register is
loaded into the sweep rate timer.
The FDW accumulates at the rate given by the ramp rate
(FSRR) until the output equals the lower limit in the linear
sweep parameter register value (Register 0x06). The sweep is
then complete. A phase sweep works in the same manner with
fewer bits.
Figure 22 displays a linear sweep up and then down. This
depicts the dwell mode (see CRF1 [8]). If the no-dwell bit,
CFR1 [8], is set, the sweep accumulator returns to 0 upon
reaching E0.
To view sweep capabilities using the profile pins and the no-
dwell bit, refer to Figure 23, Figure 24, and Figure 25.
E0
RDW
Δf, p
FDW
Δf, p
RSRR
FSRR
Δt
Δt
S0
TIME
Figure 22. Linear Sweep Mode
Rev. 0 | Page 15 of 32
AD9913
RAMP-DOWN MODE (EDGE TRIGGERED)
NO-DWELL BIT = 0
RAMP-UP MODE (EDGE TRIGGERED)
E0
S0
E0
S0
NO-DWELL BIT = 0
PS[0]
PS[1]
PS[0]
PS[1]
E0
S0
E0
S0
NO-DWELL BIT = 1
NO-DWELL BIT = 1
PS[0]
PS[1]
PS[0]
PS[1]
RAMP-UP MODE (LEVEL TRIGGERED)
RAMP-DOWN MODE (LEVEL TRIGGERED)
NO-DWELL BIT = 0
E0
S0
E0
S0
NO-DWELL
BIT = 0
PS[0]
PS[1]
PS[0]
PS[1]
E0
S0
E0
S0
NO-DWELL BIT = 1
NO-DWELL
BIT = 1
PS[0]
PS[1]
PS[0]
PS[1]
Figure 23. Display of Ramp-Up and Ramp-Down Capability Using the External Profile Pins
Rev. 0 | Page 16 of 32
AD9913
BIDIRECTIONAL MODE (EDGE TRIGGERED)
COMBINATION OF MODES (EDGE TRIGGERED)
RAMP DOWN
MODE
E0
S0
E0
S0
NO-DWELL BIT = x
RAMP UP
MODE
BIDIRECTIONAL RAMP UP
MODE MODE
PS[0]
PS[1]
PS[0]
PS[1]
Figure 25. Combination of Sweep Modes Using the External Profile Pins
BIDIRECTIONAL MODE (LEVEL TRIGGERED)
E0
S0
Clear Functions
The AD9913 allows for a programmable continuous zeroing of
the sweep logic and the phase accumulator as well as clear-and-
release, or automatic zeroing function. Each feature is
individually controlled via bits in the control registers.
NO-DWELL BIT = 0
PS[0]
PS[1]
Continuous Clear Bits
The continuous clear bits are simply static control signals that
hold the respective accumulator (and associated logic) at zero
for the entire time the bit is active.
E0
S0
NO-DWELL BIT = 1
Clear-and-Release Function
PS[0]
PS[1]
The auto clear auxiliary accumulator bit, when active, clears and
releases the auxiliary accumulator upon receiving an
I/O_UPDATE or change in profile bits.
Figure 24. Display of Bidirectional Ramp Capability
Using the External Profile Pins
The auto clear phase accumulator, when active, clears and
releases the phase accumulator upon receiving a I/O_UPDATE
or a change in profile bits.
The automatic clearing function is repeated for every
subsequent I/O_UPDATE or change in profile bits until the
control bit is cleared.
These bits are programmed independently and do not have to
be active at the same time. For example, one accumulator may
be using the clear and release function while the other is
continuously cleared.
Rev. 0 | Page 17 of 32
AD9913
CLOCK INPUT (REF_CLK)
REF_CLK OVERVIEW
pins to avoid disturbing the internal dc bias voltage of ~1.35 V.
See Figure 28 for more details.
The AD9913 supports a number of options for producing the
internal SYSCLK signal (that is, the DAC sample clock) via the
REF_CLK input pins. The REF_CLK input can be driven
directly from a differential or single-ended source, or it can
accept a crystal connected across the two input pins. There is
also an internal phase-locked loop (PLL) multiplier that can be
independently enabled. The various input configurations are
controlled by means of the control bits in the CFR2 [7:5]
register.
The REF_CLK input resistance is ~2.7 kΩ differential (~1.35 kΩ
single-ended). Most signal sources have relatively low output
impedances. The REF_CLK input resistance is relatively high,
therefore, its effect on the termination impedance is negligible
and can usually be chosen to be the same as the output imped-
ance of the signal source. The bottom two examples in Figure 28
assume a signal source with a 50 Ω output impedance.
0.1µF
13 REF_CLK
LVPECL,
DIFFERENTIAL SOURCE,
DIFFERENTIAL INPUT
OR
Table 6. Clock Input Mode Configuration
TERMINATION
LVDS
DRIVER
CFR2 [7:5]
Mode Configuration
14
REF_CLK
000
Differential Input, PLL Enabled
Differential Input, PLL Disabled (Default)
XTAL Input, PLL Enabled
0.1µF
001
x101
0.1µF
BALUN
(1:1)
x111
XTAL Input, PLL Disabled
REF_CLK
REF_CLK
13
14
100
101
CMOS Input, PLL Enabled
CMOS Input PLL Disabled
SINGLE-ENDED SOURCE,
DIFFERENTIAL INPUT
50Ω
1 x = don’t care.
0.1µF
CFR2[5]
CFR2[6]
CFR2[7:6]
0.1µF
1
13
14
REF_CLK
REF_CLK
1
0
0
XTAL
SYSTEM
CLOCK
CFR2[3]
0
13
14
REF_CLK
REF_CLK
CFR2[15]
0
PLL
SINGLE-ENDED SOURCE,
SINGLE-ENDED INPUT
50Ω
00
10
DIFFERENTIAL/
SINGLE
÷2
1
÷2
1
0.1µF
Figure 28. Direct Connection Diagram
CMOS
CFR2[14:9] CFR2[5:0]
CMOS-DRIVEN REF_CLK
Figure 26. Internal Clock Path Functional Block Diagram
This mode is enabled by writing CFR2 [7] to be true. In this
state, the AD9913 must be driven at Pin 13 with the reference
clock source. Additionally, it is recommended that Pin 14 in
CMOS mode be tied to ground through a 10 kΩ resistor.
CRYSTAL-DRIVEN REF_CLK
When using a crystal at the REF_CLK input, the resonant
frequency should be approximately 25 MHz. Figure 27 shows
the recommended circuit configuration.
13
REF_CLK
REF_CLK
CMOS
DRIVER
13
REFCLK
REFCLK
14
10kΩ
XTAL
39pF
14
39pF
Figure 29. CMOS-Driven Diagram
PHASE-LOCKED LOOP (PLL) MULTIPLIER
Figure 27. Crystal Connection Diagram
An internal phase-locked loop (PLL) provides users of the
AD9913 the option to use a reference clock frequency that is
lower than the system clock frequency. The PLL supports a wide
range of programmable frequency multiplication factors (1× to
64×). See Table 7 for details on configuring the PLL multipli-
cation factor. The PLL is also equipped with a PLL_LOCK bit.
DIRECT-DRIVEN REF_CLK
When driving the REF_CLK inputs directly from a signal
source, either single-ended or differential signals can be used.
With a differential signal source, the REF_CLK pins are driven
with complementary signals and ac-coupled with 0.1 μF
capacitors. With a single-ended signal source, either a single-
ended-to-differential conversion can be employed or the
REF_CLK input can be driven single-ended directly. In either
case, 0.1 μF capacitors are used to ac couple both REF_CLK
CFR2 [15:8] and CFR2 [5:1] control the PLL operation. Upon
power-up, the PLL is off. To initialize the PLL, CFR2 [5] must
be cleared and CFR2 [1] must be set. The function of CFR2 [1]
Rev. 0 | Page 18 of 32
AD9913
is to reset digital logic in the PLL circuit with an active low
signal. The function of CFR2 [5] is to power up or power down
the PLL.
PLL. The bits CFR [14:9] control the feedback divider. The
feedback divider is composed of two stages: ÷ N (1:31) selected
by CFR2 [13:9]; ÷1 or ÷2 selected by CFR2 [14].
CFR2 [4] is the PLL LO range bit. When operating the AD9913
with the PLL enabled, CFR2 [4] adjusts PLL loop filter
components to allow low frequency reference clock inputs.
Note that the same system clock frequency can be obtained with
different combinations of CFR2 [15:9] and CFR2 [3]. One
combination may work better in a given application either to
run at lower power or to satisfy the VCOs minimum oscillation
frequency
CFR2 [3] enables a divide-by-two circuit at the input of the PLL
phase detector. If this bit is enabled the reference clock signal is
divided by 2 prior to multiplication in the PLL. Refer to the
electrical specifications for the maximum reference clock input
frequency when utilizing the PLL with the divide by 2 circuit
enabled. If the divide by 2 circuit is disabled and the PLL is
enabled, then the maximum reference clock input frequency is
one-half the maximum rate indicated in the electrical
Note that the AD9913 maximum system clock frequency is
250 MHz. If the user intends to use high values for the PLL
feedback divider ratio, then care should be taken that the
system clock frequency does not exceed 250 MHz.
PLL LOCK INDICATION
CFR2 [0] is a read-only bit that displays the status of the PLL
lock signal.
specifications table for the maximum input divider frequency.
The AD9913 PLL uses one of two VCOs for producing the
system clock signal. CFR2 Bit 2 is a select bit that enables an
alternative VCO in the PLL. The basic operation of the PLL is
not affected by the state of this bit. The purpose of offering two
VCOs is to provide performance options. The two VCOs have
approximately the same gain characteristics, but differ in other
aspects. The overall spurious performance, phase noise, and
power consumption may change based on the setting of CFR2
Bit 2. It is important to consider that for either VCO, the
minimum oscillation frequency must be satisfied, and that
minimum oscillation frequency is significantly different
between the two oscillators.
When the AD9913 is programmed to use the PLL, there is some
amount of time required for the loop to lock. While the loop is
not locked, the chip system clock operates at the reference clock
frequency presented to the part at the pins. Once the PLL lock
signal goes high, the system clock frequency switches
asynchronously to operate at the PLL output frequency. To
maintain a system clock frequency with or without a locked
loop if the PLL lock signal transistions low, the chip reverts to
the reference clock signal while the loop attempts to acquire
lock once again.
Table 7 describes how to configure the PLL multiplication
factor using the appropriated register bits.
CFR2 [15:9], along with CFR2 [3], determine the multiplication
of the PLL. CFR2 [15] enables a divider at the output of the
Rev. 0 | Page 19 of 32
AD9913
Table 7. PLL Multiplication Factor Configuration
CFR2 [15:14], CFR2 [3]
CFR2 [13:9]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
= 000
32
1
2
3
4
5
6
7
= 001
16
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
= 100
16
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
= 101
8
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
4.25
4.5
4.75
5
5.25
5.5
5.75
6
6.25
6.5
6.75
7
= 010
64
2
4
6
= 011
32
1
2
3
4
5
6
7
= 110
32
1
2
3
4
5
6
7
= 111
16
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
8
9
8
9
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
129
30
31
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
129
30
31
8.5
9
8.5
9
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
7.25
7.5
7.75
Rev. 0 | Page 20 of 32
AD9913
POWER-DOWN FEATURES
The AD9913 supports an externally controlled power-down
feature as well as software programmable power-down bits
consistent with other Analog Devices, Inc. DDS products.
Table 8. Power-Down Controls
Control
Mode Active
Description
PWR_DWN_CTL = 0 Software
Digital power-down = CFR1 [6]
DAC power-down = CFR1 [5]
Input clock power-down =
CFR1 [4]
CFR1 [7] = don’t
care
Control
The external PWR_DWN_CTL pin determines the power-
down scheme. A low on this pin allows the user to power down
DAC, PLL, input clock circuitry, and the digital section of the
chip individually via the unique control bits, CFR1 [6:4]. In this
mode, CFR1 [7] is inactive.
PWRDWNCTL = 1
CFR1 [7] = 0
External
Control,
N/A
Fast recovery
power-down
mode
When the PWR_DWN_CTL is set, CFR1 [6:4] lose their
meaning. At the same time, the AD9913 provides two different
power-down modes based on the value of CFR1 [7]: a fast
recovery power-down mode in which only the digital logic and
the DAC digital logic are powered down, and a full power-down
mode in which all functions are powered down. A significant
amount of time is required to recover from power-down mode.
PWRDWNCTL = 1
CFR1 [7] = 1
External
Control,
N/A
Full power-
down mode
Table 11 indicates the logic level for each power-down bit that
drives out of the AD9913 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
Rev. 0 | Page 21 of 32
AD9913
eight SCLK rising edges. The instruction byte provides the
AD9913 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write and the serial address of
the register being accessed.
I/O PROGRAMMING
SERIAL PROGRAMMING
The AD9913 serial port is a flexible, synchronous serial
communications port allowing an easy interface to many
industry standard microcontrollers and microprocessors. The
serial I/O is compatible with most synchronous transfer
formats, including both the Motorola 6905/11 SPI and Intel
8051 SSR protocols.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9913. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9913
and the system controller. The number of bytes transferred
during Phase 2 of the communication cycle is a function of the
register accessed. For example, when accessing the Control
Function Register 2, which is two bytes wide, Phase 2 requires
that two bytes be transferred. If accessing one of the profile
registers, which are six bytes wide, Phase 2 requires that six
bytes be transferred. After transferring all data bytes per the
instruction, the communication cycle is completed.
The interface allows read/write access to all registers that
configure the AD9913. MSB first or LSB first transfer formats
are supported. The AD9913 serial interface port is configured
as a single pin I/O (SDIO), which allows a two-wire interface.
The AD9913 does not have a SDO pin for 3-wire operation.
With the AD9913, the instruction byte specifies read/write
operation and the register address. Serial operations on the
AD9913 occur only at the register level, not the byte level.
For the AD9913, the serial port controller recognizes the
instruction byte register address and automatically generates
the proper register byte address. In addition, the controller
expects that all bytes of that register are accessed. It is a
requirement that all bytes of a register be accessed during
serial I/O operations.
At the completion of any communication cycle, the AD9913
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle.
All data input to the AD9913 is registered on the rising edge
of SCLK. All data is driven out of the AD9913 on the falling
edge of SCLK. Figure 30 through Figure 32 illustrate the general
operation of serial ports.
There are two phases to a communication cycle with the
AD9913. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9913, coincident with the first
INSTRUCTION CYCLE
CS
DATA TRANSFER CYCLE
SCLK
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
SDIO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Figure 30. Serial Port Writing Timing—Clock Stall Low
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Figure 31. Serial Port Write Timing—Clock Stall High
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
O0
7
6
5
4
3
2
1
0
O7
O6
O5
O4
O3
O2
O1
Figure 32. Two-Wire Serial Port Read Timing—Clock Stall High
Rev. 0 | Page 22 of 32
AD9913
For MSB first operation, the serial port controller generates the
most significant byte (of the specified register) address first
followed by the next less significant byte addresses until the I/O
operation is complete. All data written to (read from) the
AD9913 must be in MSB first order.
Instruction Byte
The instruction byte contains the following information as
shown in the instruction byte bit map.
Instruction Byte Information Bit Map
MSB
LSB
D0
A0
If the LSB mode is active, the serial port controller generates the
least significant byte address first followed by the next greater
significant byte addresses until the I/O operation is complete.
All data written to (read from) the AD9913 must be in LSB
first order.
D7
D6
D5
D4
D3
D2
D1
R/W
X
X
A4
A3
A2
A1
W
R/ —Bit 7 of the instruction byte determines whether a read
or write data transfer occurs after the instruction byte write.
Logic high indicates read operation. Logic 0 indicates a write
operation.
Notes on Serial Port Operation
The LSB first bit resides in CFR1 [23]. Note that the
configuration changes immediately upon writing to the byte
containing the LSB first bit. Therefore, care must be taken to
compensate for this new configuration for the remainder of the
current communication cycle.
X, X—Bit 6 and Bit 5 of the instruction byte are don’t care.
A4, A3, A2, A1, A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte determine which register is accessed during the
data transfer portion of the communications cycle.
Reading profile registers requires that the external profile select
pins (PS[2:0]) be configured to select the corresponding
register.
Serial Interface Port Pin Description
SCLK—Serial Port Clock
The serial clock pin is used to synchronize data to and from the
AD9913 and to run the internal state machines.
PARALLEL I/O PROGRAMMING
Parallel Port Interface Pin Description
CS
—Chip Select
CS
—Chip Select
Active low input that allows more than one device on the same
serial communications line. The SDIO pin goes to a high
impedance state when this input is high. If driven high during
any communications cycle, that cycle is suspended until chip
select is reactivated low. Chip select can be tied low in systems
that maintain control of SCLK.
An active low on this pin indicates that a read/write operation is
about to be performed. If this pin goes high during an access,
the parallel port is reset to its initial condition.
W
R/ —Read/Write
CS
A high on Pin 29 combined with
active low indicates a read
operation. A low on this pin indicates a write operation.
SDIO—Serial Data I/O.
PCLK—Parallel Port Clock
Data is always written into and read from the AD9913 on
this pin.
The parallel clock pin is used to synchronize data to and from
the AD9913 and to run the internal state machines.
MSB/LSB Transfers
ADDR/DATA [7:0]
The AD9913 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the CFR1 [23]. The default value
is MSB first. The instruction byte must be written in the format
indicated by Control Register 0x00 Bit 8. That is, if the AD9913
is in LSB first mode, the instruction byte must be written from
least significant bit to most significant bit.
The 8-bit address/data bus. It works in a bidirectional fashion to
support both read and write operations.
Notes on Parallel Port Operation
Each operation works in a 3-PCLK cycle with the first clock
cycle for addressing, the second for reading or writing, and the
third for re-initialization. In parallel port operation, each byte is
programmed individually.
Rev. 0 | Page 23 of 32
AD9913
Data Write Operation
Data Read Operation
Write operations work in a similar fashion as read operations
except that the user drives the bus for both PCLK cycles. A
typical write access follows the steps shown in Figure 34.
A typical read operation follows the steps shown in Figure 33.
CS
W
1. The user supplies PCLK, , R/ , and the parallel address
of the register using the address pins (ADR0 through
ADR7) for the read operation.
CS
W
1. The user supplies the PCLK, , R/ , and the parallel
address of the register and using the address pins
(ADR0/D0 through ADR7/D7).
CS
W
2.
, R/ , and the address lines must meet the setup and
hold times relative to the 1st PCLK rising edge.
CS
W
2.
, R/ , and the address lines must meet the set up and
3. The user releases the bus to read.
hold times relative to the 1st PCLK rising edge.
4. The AD9913 drives data onto the bus after the second
3. Data lines must meet the set up and hold times relative to
PCLK rising edge.
the 2nd PCLK rising edge.
rd
CS
5.
must meet the set up and hold times to the 3 PCLK
rd
CS
4.
must meet the set up and hold times relative to the 3
PCK rising edge.
rising edge.
READ OPERATION
PCLK
CS
R/W
ADDR/DATA
ADDR0
DATA0
ADDR1
DATA1
3ns 0.3ns
8ns 3ns 0.3ns
tASU tAHD
tDVLD tCSU tCHD
Figure 33. Parallel Port Read Timing
WRITE OPERATION
PCLK
CS
R/W
ADDR/DATA
ADDR0
DATA0
ADDR1
DATA1
3ns 0.3ns 3ns 0.3ns 3ns 0.3ns
tASU tAHD tDSU tDHD tCSU tCHD
Figure 34. Parallel Port Write Timing
Rev. 0 | Page 24 of 32
AD9913
REGISTER MAP AND BIT DESCRIPTIONS
REGISTER MAP
Note that the highest number found in the Serial Bit Range column for each register in the following tables is the MSB and the lowest
number is the LSB for that register.
Table 9. Control Registers
Register
Name
(Serial
[Serial Bit
Range]/
Parallel
MSB
Bit 7
LSB
Bit 0
Default
Value
Address)
Address
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CFR1—
Control
Function
Register 1
(0x00)
[7:0]/0x00
External
Power-
Down
Digital
Power-
Down
DAC
Power-
Down
Clock
Input
Power-
Down
Load SRR @
IO_UPDATE
Autoclear
Auxiliary
Accum.
Autoclear
Phase
Accum.
Enable
Sine
Output
0x00
Mode
[15:8]/0x01
Clear
Auxiliary
Accum.
Clear
Phase
Accum.
Destination [1:0]
00: Frequency Word
01: Phase Word
Auxiliary
Accumulator Output
Enable
DC
Linear
Sweep
State
Trigger
Active
Linear
0x00
Sweep
No-Dwell
Active
Active
[23:16]/0x02
[31:24]/0x03
LSB First
Open
Internal Profile Control [2:0]
Sync Clock
Disable
Open
Open
Direct
Switch
Mode
Active
0x00
0x00
Open
Open
Modulus
Enable
Use Internal
Profile
Match
Pipe
Open
Open
Delays
Active
CFR2—
Control
Function
Register 2
(0x01)
[7:0]/0x04
CMOS
Clock
Mode
Crystal
Clock
Mode
PLL
Power-
Down
PLL LO
Range
PLL Input
Div by 2
VCO2 Sel
PLL Reset
PLL Lock
Open
0x32
0x14
[15:8]/0x05
PLL
Output
Div by 2
PLL Multiplication Factor [5:0]
DAC Control
Register
(0x02)
[7:0]/0x06
FS C [7:0]
0xFF
0x13
0x7F
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
[15:8]/0x07
[23:16]/0x08
[31:24]/0x09
[7:0]/0x0A
Open
Open
Reserved
Reserved
Open
FSC [9:8]
Reserved
FTW
(0x03)
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
[15:8]/0x0B
[23:16]/0x0C
[31:24]/0x0D
[7:0]/0x0E
POW
(0x04)
[15:8]/0x0F
[7:0]/0x12
Open [1:0]
Phase Offset Word [13:8]
Linear Sweep
Parameter
Register
Sweep Parameter Word 0 [7:0]
Sweep Parameter Word 0 [15:8]
Sweep Parameter Word 0 [23:16]
Sweep Parameter Word 0 [31:24]
Sweep Parameter Word 1 [7:0]
Sweep Parameter Word 1 [15:8]
Sweep Parameter Word 1 [23:16]
Sweep Parameter Word 1 [31:24]
Rising Delta Word [7:0]
[15:8]/0x13
[23:16]/0x14
[31:24]/0x15
[39:32]/0x16
[47:40]/0x17
[55:48]/0x18
[63:56]/0x19
[7:0]/0x1A
(0x06)
Linear Sweep
Delta
Parameter
Register
(0x07)
[15:8]/0x1B
[23:16]/0x1C
[31:24]/0x1D
[39:32]/0x1E
[47:40]/0x1F
[55:48]/0x20
[63:56]/0x21
Rising Delta Word [15:8]
Rising Delta Word [23:16]
Rising Delta Word [31:24]
Falling Delta Word [7:0]
Falling Delta Word [15:8]
Falling Delta Word [23:16]
Falling Delta Word [31:24]
Rev. 0 | Page 25 of 32
AD9913
Register
Name
(Serial
[Serial Bit
Range]/
Parallel
MSB
Bit 7
LSB
Bit 0
Default
Value
Address)
Address
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
[7:0]/0x22
Rising Sweep Ramp Rate Word [7:0]
Rising Sweep Ramp Rate Word [15:8]
Falling Sweep Ramp Rate Word [7:0]
Falling Sweep Ramp Rate Word [15:8]
Frequency Tuning Word [7:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Linear Sweep
Ramp Rate
Register
[15:8]/0x23
[23:16]/0x24
[31:24]/0x25
[7:0]/0x26
(0x08)
Profile 0
(0x09)
[15:8]/0x27
[23:16]/0x28
[31:24]/0x29
[39:32]/0x2A
[47:40]/0x2B
[7:0]/0x2C
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
Open [1:0]
Phase Offset Word [13:8]
Profile 1
(0x0A)
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
[15:8]/0x2D
[23:16]/0x2E
[31:24]/0x2F
[39:32]/0x30
[47:40]/0x31
[7:0]/0x32
Open [1:0]
Open [1:0]
Open [1:0]
Open [1:0]
Open [1:0]
Phase Offset Word [13:8]
Profile 2
(0x0B)
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
[15:8]/0x33
[23:16]/0x34
[31:24]/0x35
[39:32]/0x36
[47:40]/0x37
[7:0]/0x38
Phase Offset Word [13:8]
Profile 3
(0x0C)
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
[15:8]/0x39
[23:16]/0x3A
[31:24]/0x3B
[39:32]/0x3C
[47:40]/0x3D
[7:0]/0x3E
Phase Offset Word [13:8]
Profile 4
(0x0D)
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
[15:8]/0x3F
[23:16]/0x40
[31:24]/0x41
[39:32]/0x42
[47:40]/0x43
[7:0]/0x44
Phase Offset Word [13:8]
Profile 5
(0x0E)
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
[15:8]/0x45
[23:16]/0x46
[31:24]/0x47
[39:32]/0x48
[47:40]/0x49
[7:0]/0x4A
Phase Offset Word [13:8]
Profile 6
(0x0F)
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
[15:8]/0x4B
[23:16]/0x4C
[31:24]/0x4D
[39:32]/0x4E
[47:40]/0x4F
[7:0]/0x50
Open
Open
Open
Phase Offset Word [13:8]
Profile 7
(0x10)
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
[15:8]/0x51
[23:16]/0x52
[31:24]/0x53
[39:32]/0x54
[47:40]/0x55
Open
Phase Offset Word [13:8]
Rev. 0 | Page 26 of 32
AD9913
REGISTER BIT DESCRIPTIONS
This section is organized in sequential order of the serial
addresses of the registers. Each subheading includes the register
name and optional register mnemonic (in parentheses). Also
given is the serial address in hexadecimal format and the
number of bytes assigned to the register.
The serial I/O port registers span an address range of 0 to 16
(0x00 to 0x10 in hexadecimal notation). This represents a total
of 17 registers. However, one of these registers (0x05) is unused,
yielding a total of 16 available registers.
Following each subheading is a table containing the individual
bit descriptions for that particular register. The location of the
bit(s) in the register are indicated by a single number or a pair
of numbers separated by a colon. A pair of numbers (A:B)
indicates a range of bits from the most significant (A) to the
least significant (B). For example, 5:2 implies Bit Position 5
down to Bit Position 2, inclusive, with Bit 0 identifying the LSB
of the register.
The registers are not of uniform depth; each contains the
number of bytes necessary for its particular function.
Additionally, the registers are assigned names according to their
functionality. In some cases, a register is given a mnemonic
descriptor. For example, the register at Serial Address 0x00 is
named Control Function Register 1 and is assigned the
mnemonic CFR1.
The following section provides a detailed description of each bit
in the AD9913 register map. For cases in which a group of bits
serve a specific function, the entire group is considered as a
binary word and described in aggregate.
Unless otherwise stated, programmed bits are not transferred to
their internal destinations until the assertion of the I/O_UPDATE
pin or a profile change.
Control Function Register 1 (CFR1)
Address 0x00; 4 bytes are assigned to this register.
Table 10. Bit Description for CFR1
Bit(s)
31:29
28
Bit Name
Description
Open
Leave these bits at their default values.
Modulus Enable
This bit is ignored if linear sweep is disabled.
0 = the auxiliary accumulator is used for linear sweep generation.
1 = the auxiliary accumulator is used for programmable modulus.
27
26
Use Internal Profile
0 = profiles are controlled by profile pins; only valid in serial mode.
1 = profiles are controlled by CFR1 [22:20].
Match Pipeline Delays Active
0 = the latency across the auxiliary accumulator, the phase offset word, and phase
accumulator are matched.
1 = the latency across the auxiliary accumulator, the phase offset word, and phase
accumulator are not matched.
25:24
23
Open
Leave these bits at the default values.
0 = MSB first format is used.
LSB First
1 = LSB first format is used.
22:20
19
Internal Profile Control
Sync Clock Disable
Ineffective unless Bit 27 = 1. Default is 0002. Refer to the Linear Sweep Mode section for
details on how to program these registers during linear sweep, and refer to the Direct
Switch Mode section for details on how to program these registers in direct switch mode.
0 = the SYNC_CLK pin is active.
1 = the SYNC_CLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive
logic is shut down, minimizing the noise generated by the digital circuitry.
18:17
16
Open
Leave these bits in their default values.
0 = direct switch mode is disabled.
Direct Switch Mode Active
1 = direct switch mode is enabled.
15
Clear Auxiliary Accumulator
Clear Phase Accumulator
0 = normal operation of the auxiliary accumulator (default).
1 = asynchronous, static reset of the auxiliary accumulator. The ramp accumulator remains
reset as long as this bit remains set. This bit is synchronized with either an I/O update or a
profile change and the next rising edge of SYNC_CLK.
14
0 = normal operation of the DDS phase accumulator (default).
1 = asynchronous, static reset of the DDS phase accumulator.
Rev. 0 | Page 27 of 32
AD9913
Bit(s)
Bit Name
Description
13:12
Destination
00 = In direct switch mode, use this setting for FSK.
In linear sweep mode, the auxiliary accumulator is used for frequency sweeping.
In programmable modulus mode, these bits must be 00.
01 = In direct switch mode, use this setting for PSK.
In linear sweep mode, the auxiliary accumulator is used for phase sweeping.
11
10
Auxiliary Accumulator Enable 0 = auxiliary accumulator is inactive.
1 = auxiliary accumulator is active.
DC Output Active
This bit is ignored if linear sweep is disabled (see CFR1 [11]).
0 = normal operating state.
1 = the output of the DAC is driven to full-scale and the DDS output is disabled.
9
8
Linear Sweep State Trigger
Active
0 = edge triggered mode active.
1 = state triggered mode active.
Linear Sweep No-Dwell Active This bit is ignored if linear sweep is disabled (see CFR1[11]).
0 = when a sweep is completed, the device holds at the final state.
1 = when a sweep is completed, the device reverts to the initial state.
7
External Power-Down Mode
0 = the external power-down mode selected is the fast recovery power-down mode. In this
mode, when the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital
logic are powered down. The DAC bias circuitry, comparator, PLL, oscillator, and clock input
circuitry are not powered down.
1 = the external power-down mode selected is the full power-down mode. In this mode,
when the PWR_DWN_CTL pin is high, all functions are powered down. This includes the
DAC and PLL, which take a significant amount of time to power up.
6
5
4
Digital Power-Down
DAC Power-Down
0 = the digital core is enabled for operation.
1 = the digital core is disabled and is in a low power dissipation state.
0 = the DAC is enabled for operation.
1 = the DAC is disabled and is in its lowest power dissipation state.
0 = normal operation.
Clock Input Power-Down
1 = shut down all clock generation including the system clock signal going into the digital
section.
3
LOAD SRR @ IO_UPDATE
0 = every time the linear sweep rate register is updated, the ramp rate timer keeps its
operation until it times out and then loads the update value into the timer.
1 = the timer is interrupted immediately upon the assertion of IO_UPDATE and the value is
loaded.
2
1
0
Autoclear Auxiliary
Accumulator
0 = normal operation.
1 = the auxiliary accumulator is synchronously cleared (zero is loaded) for one cycle upon
receipt of the IO_UPDATE sequence indicator.
Autoclear Phase Accumulator 0 = normal operation.
1 = the phase accumulator is synchronously cleared for one cycle upon receipt of the
IO_UPDATE sequence indicator.
Enable Sine Output
0 = the angle-to-amplitude conversion logic employs a cosine function.
1 = the angle-to-amplitude conversion logic employs a sine function.
Rev. 0 | Page 28 of 32
AD9913
Control Function Register 2 (CFR2)
Address 0x01; 2 bytes are assigned to this register.
Table 11. Bit Descriptions for CFR2
Bit(s)
Bit Name
Description
15
14:9
8
PLL Output Div by 2
PLL Multiplication Factor
Open
See Table 7 for details on multiplication factor configuration.
Leave this bit at the default state.
7
CMOS Clock Mode
Crystal Clock Mode
PLL Power-Down
See Table 6 for directions on programming this bit.
See Table 6 for directions on programming this bit.
6
5
0 = PLL is active
1 = PLL is inactive and in its lowest power state
4
3
2
PLL LO Range
PLL Input Div by 2
VCO2 Sel
0 = use this setting for PLL if the PLL reference frequency is >5 MHz.
1 = use this setting for PLL if the PLL reference frequency is <5 MHz.
0 = the PLL reference frequency = the REF_CLK input frequency.
1 = the PLL reference frequency = ½ the REF_CLK input frequency.
0 = use this setting for VCO frequencies below 100 MHz and/or to optimize for power rather
than performance.
1 = use this setting to optimize for performance; this setting results in slightly higher power
consumption. Note: When setting this bit, an IO_UPDATE must occur within 40 μs of the PLL
power-down bit (CFR2 [5]) going low.
1
0
PLL Reset
PLL Lock
0 = the PLL logic is reset and non-operational until this bit is set.
1 = the PLL logic operates normally.
This read-only bit is set when the REF_CLK PLL is locked.
DAC Control Register
Address 0x02; 4 bytes are assigned to this register.
Table 12. Bit Descriptions for DAC Control Register
Bit(s)
Bit Name
Description
15:14, 10
9:0
Open
Leave these bits at their default state.
This 10-bit number controls the full-scale output current of the DAC.
Leave these bits at their default state.
FSC
31:16,13:11
Reserved
Frequency Tuning Word Register (FTW)
Address 0x03, 4 bytes are assigned to this register.
Table 13. Bit Descriptions for FTW Register
Bit(s)
Bit Name
Description
31:0
Frequency Tuning Word
32-bit frequency tuning word.
Phase Offset Word Register (POW)
Address 0x04, 2 bytes are assigned to this register.
Table 14. Bit Descriptions for POW Register
Bit(s)
15:14
13:0
Bit Name
Description
Open
Leave these bits at their default state.
14-bit phase offset word.
Phase Offset Word
Rev. 0 | Page 29 of 32
AD9913
Linear Sweep Parameter Register
Address 0x06, 8 bytes are assigned to this register. This register is only effective if CFR1 [11] or CFR1 [28] are set. See the Auxiliary
Accumulator section.
Table 15. Bit Descriptions for Linear Sweep Limit Register
Bit(s)
Bit Name
Description
63:32
Sweep Parameter Word 0
32-bit linear sweep upper limit value. In modulus mode, these bits set the auxiliary
accumulator capacity
31:0
Sweep Parameter Word 1
32-bit linear sweep lower limit value. In modulus mode, these bits set the base FTW.
Linear Sweep Delta Parameter Register
Address 0x07, 8 bytes are assigned to this register. This register is only effective if CFR1 [11] or CFR1 [28] are set. See the Auxiliary
Accumulator section.
Table 16. Bit Descriptions for Linear Sweep Step Size Register
Bit(s)
63:32
31:0
Bit Name
Description
Falling Delta Word
Rising Delta Word
32-bit linear sweep decrement step size value.
32-bit linear sweep increment step size value. In modulus mode, these bits set the auxiliary
accumulator seed value.
Linear Sweep Ramp Rate Register
Address 0x08, 4 bytes are assigned to this register. This register is only effective if CFR1 [11] or CFR1 [28] are set. See the Auxiliary
Accumulator section.
Table 17. Bit Descriptions for Linear Sweep Rate Register
Bit(s)
Bit Name
Description
31:16
Falling Sweep Ramp Rate
16-bit linear sweep negative slope value that defines the time interval between decrement
values.
15:0
Rising Sweep Ramp Rate
16-bit linear sweep positive slope value that defines the time interval between increment
values.
Profile Registers
There are eight consecutive serial I/O addresses dedicated to device profiles. In normal operation, the active profile register is selected
using the external profile select pins.
Profile 0 to Profile 7—Single Tone Register
Address 0x09 to Address 0x10, 6 bytes are assigned to these registers.
Table 18. Bit Descriptions for Profile 0 to Profile 7 Single Tone Register
Bit(s)
47:46
45:32
31:0
Bit Name
Description
Open
Leave these bits at their default state.
This 14-bit number controls the DDS phase offset.
This 32-bit number controls the DDS frequency.
Phase Offset Word
Frequency Tuning Word
Rev. 0 | Page 30 of 32
AD9913
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 35. 32-Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
CP-32-2
CP-32-2
AD9913BCPZ1
32-Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
AD9913BCPZ-REEL71
AD9913/PCBZ1
1 Z = RoHS Compliant Part.
AD9913
NOTES
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D07002-0-10/07(0)
Rev. 0 | Page 32 of 32
相关型号：
AD9913BCPZ
PARALLEL, WORD INPUT LOADING, 10-BIT DAC, QCC32, 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32
ROCHESTER
AD9913BCPZ-REEL7
PARALLEL, WORD INPUT LOADING, 10-BIT DAC, QCC32, 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32
ROCHESTER
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