AD9914_技术文档

3.5 GSPS Direct Digital Synthesizer

with 12-Bit DAC

Data Sheet

AD9914

1.8 V/3.3 V power supplies

FEATURES

Software and hardware controlled power-down

88-lead LFCSP package

PLL REF CLK multiplier

Phase modulation capability

Amplitude modulation capability

3.5 GSPS internal clock speed

Integrated 12-bit DAC

Frequency tuning resolution to 190 pHz

16-bit phase tuning resolution

12-bit amplitude scaling

Programmable modulus

Automatic linear and nonlinear frequency sweeping

capability

32-bit parallel datapath interface

8 frequency/phase offset profiles

Phase noise: −128 dBc/Hz (1 kHz offset at 1396 MHz)

Wideband SFDR < −50 dBc

APPLICATIONS

Agile LO frequency synthesis

Programmable clock generator

FM chirp source for radar and scanning systems

Test and measurement equipment

Acousto-optic device drivers

Polar modulator

Serial or parallel I/O control

Fast frequency hopping

FUNCTIONAL BLOCK DIAGRAM

AD9914

HIGH SPEED PARALLEL

MODULATION

PORT

LINEAR

SWEEP

BLOCK

3.5GSPS DDS CORE

12-BIT DAC

REF CLK

MULTIPLIER

TIMING AND CONTROL

SERIAL OR PARALLEL

DATA PORT

Figure 1.

Rev. C

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AD9914

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

DDS Core .................................................................................... 19

12-Bit DAC Output.................................................................... 20

DAC Calibration Output........................................................... 20

Reconstruction Filter................................................................. 20

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Absolute Maximum Ratings............................................................ 8

Thermal Performance.................................................................. 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 12

Equivalent Circuits......................................................................... 16

Theory of Operation ...................................................................... 17

Single Tone Mode....................................................................... 17

Profile Modulation Mode.......................................................... 17

Digital Ramp Modulation Mode.............................................. 17

Parallel Data Port Modulation Mode....................................... 17

Programmable Modulus Mode................................................. 17

Mode Priority.............................................................................. 18

Functional Block Detail ................................................................. 19

REF_CLK

Clock Input (REF_CLK/

)........................................ 21

PLL Lock Indication .................................................................. 22

Output Shift Keying (OSK)....................................................... 22

Digital Ramp Generator (DRG)............................................... 23

Power-Down Control ................................................................ 27

Programming and Function Pins................................................. 28

Serial Programming ....................................................................... 31

Control Interface—Serial I/O................................................... 31

General Serial I/O Operation ................................................... 31

Instruction Byte.......................................................................... 31

Serial I/O Port Pin Descriptions .............................................. 31

Serial I/O Timing Diagrams ..................................................... 32

MSB/LSB Transfers .................................................................... 32

Parallel Programming (8-/16-Bit)................................................ 33

Register Map and Bit Descriptions .............................................. 34

Register Bit Descriptions........................................................... 39

Outline Dimensions....................................................................... 45

Ordering Guide .......................................................................... 45

REVISION HISTORY

11/13—Rev. B to Rev. C

8/12—Rev. 0 to Rev. A

Changes to Table 2.............................................................................5

Change to Programming and Function Pins Section.................30

Changes to Features Section ............................................................1

Changed Differential Input Voltage Unit from mV p-p to V p-p .... 4

Changes to Table 14 ....................................................................... 34

Changes to Table 16 ....................................................................... 40

Changes to Table 28 ....................................................................... 44

Updated Outline Dimensions....................................................... 45

7/13—Rev. A to Rev. B

Change to CMOS Logic Outputs Parameter, Table 1 ...................4

Changes to Table 2.............................................................................7

Changes to DDS Core Section.......................................................19

Changes to Phase-Locked Loop (PLL) Multiplier Section ........21

Changed PLL Charge Pump Section to PLL Charge Pump/

Total Feedback Divider Section; Changes to Table 8, PLL

7/12—Revision 0: Initial Version

Loop Filter Components Section, and Figure 34 ........................22

Change to Table 14 ..........................................................................34

Changes to Bits [15:8], Table 17.....................................................42

Rev. C | Page 2 of 48

Data Sheet

AD9914

GENERAL DESCRIPTION

The AD9914 is a direct digital synthesizer (DDS) featuring a

12-bit DAC. The AD9914 uses advanced DDS technology,

coupled with an internal high speed, high performance DAC

to form a digitally programmable, complete high frequency

synthesizer capable of generating a frequency-agile analog

output sinusoidal waveform at up to 1.4 GHz. The AD9914

enables fast frequency hopping and fine tuning resolution

(64-bit capable using programmable modulus mode). The

AD9914 also offers fast phase and amplitude hopping capability.

The frequency tuning and control words are loaded into the

AD9914 via a serial or parallel I/O port. The AD9914 also

supports a user defined linear sweep mode of operation for

generating linear swept waveforms of frequency, phase, or

amplitude. A high speed, 32-bit parallel data input port is

included, enabling high data rates for polar modulation

schemes and fast reprogramming of the phase, frequency,

and amplitude tuning words.

The AD9914 is specified to operate over the extended industrial

temperature range (see the Absolute Maximum Ratings section).

AD9914

OUTPUT

DDS

SHIFT

OSK

DAC_RSET

KEYING

AMPLITUDE (A)

PHASE (θ)

2

Acos (ωt + θ)

Asin (ωt + θ)

A

DRCTL

DRHOLD

DIGITAL

RAMP

GENERATOR

AOUT

DAC

12-BIT

DATA

ROUTE

θ

FREQUENCY (ω)

DROVER

AND

ω

PARTITION

CONTROL

CLOCK

3

INTERNAL

PROGRAMMING

REGISTERS

PS[2:0]

SYSCLK

I/O_UPDATE

REF_CLK

INTERNAL CLOCK TIMING

AND CONTROL

32

4

PLL

D0 TO D31

POWER-

DOWN

CONTROL

F0 TO F3

MULTICHIP

SYNCHRONIZATION

SYNC_CLK

Figure 2. Detailed Block Diagram

Rev. C | Page 3 of 48

AD9914

Data Sheet

SPECIFICATIONS

DC SPECIFICATIONS

AVDD (1.8V) and DVDD (1.8V) = 1.8 V 5%, AVDD (3.3V) and DVDD_I/O (3.3V) = 3.3 V 5%, T_A= 25°C, R_SET= 3.3 kΩ,

_OUT= 20 mA, external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.

I

Table 1.

Parameter

SUPPLY VOLTAGE

DVDD_I/O

DVDD

Min

Typ

Max

Unit

Test Conditions/Comments

3.135 3.30

1.71 1.80

3.135 3.30

3.465

1.89

3.465

V

Pin 16, Pin 83

Pin 6, Pin 23, Pin 73

Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,

Pin 53, Pin 60

AVDD (3.3V)

AVDD (1.8V)

SUPPLY CURRENT

I_{DVDD_I/O}

I_DVDD

I_AVDD(3.3V)

1.71

1.80

1.89

V

Pin 32, Pin 56, Pin 57

See also the total power dissipation specifications

Pin 16, Pin 83

Pin 6, Pin 23, Pin 73

Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,

Pin 53, Pin 60

20

433

640

mA

I_AVDD(1.8V)

178

mA

Pin 32, Pin 56, Pin 57

TOTAL POWER DISSIPATION

Base DDS Power, PLL Disabled

2392 3091

2237 2627

mW

3.5 GHz, single-tone mode, modules disabled, linear

sweep disabled, amplitude scaler disabled

2.5 GHz, single-tone mode, modules disabled, linear

sweep disabled, amplitude scaler disabled

Base DDS Power, PLL Enabled

Linear Sweep Additional Power

Modulus Additional Power

Amplitude Scaler Additional

Power

28

20

138

mW

Manual or automatic

Full Power-Down Mode

400

616

mW

Using either the power-down and enable register or the

EXT_PWR_DWN pin

CMOS LOGIC INPUTS

Input High Voltage (V_IH)

Input Low Voltage (V_IL)

Input Current (I_INH, I_INL)

Maximum Input Capacitance (C_IN)

CMOS LOGIC OUTPUTS

Output High Voltage (V_OH)

Output Low Voltage (V_OL)

REF CLK INPUT CHARACTERISTICS

2.0

2.7

DVDD_I/O

0.8

200

V

µA

pF

60

3

At V_IN= 0 V and V_IN= DVDD_I/O

DVDD_I/O

0.4

V

I_OH= 1 mA

I_OL= 1 mA

REF CLK inputs should always be ac-coupled (both single-

ended and differential)

REF CLK Multiplier Bypassed

Input Capacitance

Input Resistance

Internally Generated DC Bias

Voltage

1

1.4

2

pF

kΩ

V

Single-ended, each pin

Differential

Differential Input Voltage

REF CLK Multiplier Enabled

Input Capacitance

Input Resistance

Internally Generated DC Bias

Voltage

0.8

1.5

V p-p

1

1.4

2

pF

kΩ

V

Single-ended, each pin

Differential

Differential Input Voltage

0.8

V p-p

Rev. C | Page 4 of 48

Data Sheet

AD9914

AC SPECIFICATIONS

AVDD (1.8V) and DVDD (1.8V) = 1.8 V 5%, AVDD3 (3.3V) and DVDD_I/O (3.3V) = 3.3 V 5%, T_A= 25°C, R_SET= 3.3 kΩ, I_OUT

20 mA, external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.

=

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REF CLK INPUT

Input frequency range

REF CLK Multiplier Bypassed

Input Frequency Range

Duty Cycle

500

45

3500

55

MHz

%

Maximum f_OUTis 0.4 × f_SYSCLK

Minimum Differential Input Level

System Clock (SYSCLK) PLL Enabled

VCO Frequency Range

VCO Gain (K_V)

Maximum PFD Rate

CLOCK DRIVERS

632

mV p-p

Equivalent to 316 mV swing on each leg

2400

2500

125

MHz

MHz/V

MHz

60

SYNC_CLK Output Driver

Frequency Range

Duty Cycle

Rise Time/Fall Time (20% to 80%)

SYNC_OUT Output Driver

Frequency Range

146

55

MHz

%

ps

45

33

0

50

650

10 pF load

9.1

66

MHz

%

ps

Duty Cycle

CFR2 register, Bit 9 = 1

10 pF load

Rise Time (20% to 80%)

Fall Time (20% to 80%)

DAC OUTPUT CHARACTERISTICS

Output Frequency Range (1^stNyquist

Zone)

1350

1670

ps

1750

MHz

Ω

Output Resistance

50

1

Single-ended (each pin internally terminated to

AVDD (3.3V))

Output Capacitance

Full-Scale Output Current

Gain Error

Output Offset

Voltage Compliance Range

pF

20.48

+10

0.6

AVDD +

0.50

mA

% FS

μA

V

Range depends on DAC R_SETresistor

−10

AVDD −

0.50

Wideband SFDR

See the Typical Performance Characteristics

section

101.1 MHz Output

427.5 MHz Output

696.5 MHz Output

1396.5 MHz Output

Narrow-Band SFDR

−66

−65

−57

−52

dBc

0 MHz to 1750 MHz

See the Typical Performance Characteristics

section

100.5 MHz Output

427.5 MHz Output

696.5 MHz Output

−95

−92

dBc

500 kHz

1396.5 MHz Output

DIGITAL TIMING SPECIFICATIONS

Time Required to Enter Power-Down

45

ns

Power-down mode loses DAC/PLL calibration

settings

Time Required to Leave Power-Down

Minimum Master Reset time

250

ns

Must recalibrate DAC/PLL

24

SYSCLK cycles

µs

Maximum DAC Calibration Time (t_CAL

)

152

f_CAL= f_SYSCLK/384 USR0 register, Bit 6 = 0; see the

DAC Calibration Output section for formula

Maximum PLL Calibration Time (t_{REF_CLK}

)

16

8

ms

PFD rate = 25 MHz

PFD rate = 50 MHz

Maximum Profile Toggle Rate

2

SYNC_CLK period

Rev. C | Page 5 of 48

AD9914

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PARALLEL PORT TIMING

Write Timing

1

ns

Address Setup Time to WR Active

0

Address Hold Time to WR Inactive

Data Setup Time to WR Inactive

Data Hold Time to WR Inactive

WR Minimum Low Time

3.8

0

2.1

3.8

10.5

WR Minimum High Time

Minimum WR Time

Read Timing

Address to Data Valid

Address Hold to RD Inactive

92

0

ns

69

50

69

50

ns

RD Active to Data Valid

RD Inactive to Data Tristate

RD Minimum Low Time

RD Minimum High Time

SERIAL PORT TIMING

SCLK Clock Rate (1/t_CLK

)

80

MHz

ns

SCLK duty cycle = 50%

SCLK Pulse Width High, t_HIGH

SCLK Pulse Width Low, t_LOW

SDIO to SCLK Setup Time, t_DS

SDIO to SCLK Hold Time, t_DH

1.5

5.1

4.9

0

SCLK Falling Edge to Valid Data on

SDIO/SDO, t_DV

78

ns

4

ns

CS to SCLK Setup Time, t_S

0

CS to SCLK Hold Time, t_H

CS Minimum Pulse Width High, t_PWH

DATA PORT TIMING

D[31:0] Setup Time to SYNC_CLK

D[31:0] Hold Time to SYNC_CLK

F[3:0] Setup Time to SYNC_CLK

F[3:0] Hold Time to SYNC_CLK

IO_UPDATE Pin Setup Time to

SYNC_CLK

2

ns

0

IO_UPDATE Pin Hold Time to

SYNC_CLK

Profile Pin Setup Time to SYNC_CLK

Profile Pin Hold Time to SYNC_CLK

DR_CTL/DR_HOLD Setup Time to

SYNC_CLK

DR_CTL/DR_HOLD Hold Time to

SYNC_CLK

0

ns

2

ns

Rev. C | Page 6 of 48

Data Sheet

AD9914

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DATA LATENCY (PIPELINE DELAY)

SYSCLK cycles = f_S= system clock frequency

in GHz

Single Tone Mode or Profile Mode

(Matched Latency Disabled)

Frequency

318

342

294

318

102

SYSCLK cycles

OSK disabled

OSK enabled

OSK disabled

OSK enabled

Phase

Amplitude

Single Tone Mode or Profile Mode

(Matched Latency Enabled)

Frequency

318

342

318

342

SYSCLK cycles

OSK disabled

OSK enabled

OSK disabled

OSK enabled

Phase

Amplitude

Modulation Mode with 32-Bit Parallel

Port (Matched Latency Disabled)

Frequency

318

342

294

318

102

SYSCLK cycles

OSK disabled

OSK enabled

OSK disabled

OSK enabled

Phase

Amplitude

Modulation Mode with 32-Bit Parallel

Port (Matched Latency Enabled)

Frequency

318

342

318

342

SYSCLK cycles

OSK disabled

OSK enabled

OSK disabled

OSK enabled

Phase

Amplitude

Sweep Mode (Match Latency Disabled)

Frequency

342

366

318

342

126

SYSCLK cycles

OSK disabled

OSK enabled

OSK disabled

OSK enabled

Phase

Amplitude

Sweep Mode (Match Latency Enabled)

Frequency

342

366

342

366

SYSCLK cycles

OSK disabled

OSK enabled

OSK disabled

OSK enabled

Phase

Amplitude

Rev. C | Page 7 of 48

AD9914

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL PERFORMANCE

Table 3.

Parameter

Rating

Table 4.

Symbol Description

AVDD (1.8 V), DVDD (1.8 V) Supplies

AVDD (3.3 V), DVDD_I/O (3.3 V) Supplies

Digital Input Voltage

2 V

4 V

Value¹Unit

Junction-to-ambient thermal

resistance (still air) per JEDEC

JESD51-2

24.1

21.3

20.0

13.3

12.8

°C/W

_JA

−0.7 V to +4 V

5 mA

Digital Output Current

Storage Temperature Range

Operating Temperature Range

Maximum Junction Temperature

Lead Temperature (10 sec Soldering)

−65°C to +150°C

−40°C to +85°C

150°C

Junction-to-ambient thermal

resistance (1.0 m/sec airflow)

per JEDEC JESD51-6

Junction-to-ambient thermal

resistance (2.0 m/sec air flow)

per JEDEC JESD51-6

Junction-to-board thermal

resistance (still air) per JEDEC

JESD51-8

Junction-to-board characterization

parameter (still air) per JEDEC

JESD51-6

_JMA

_JB

300°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

_JB

Junction-to-case thermal resistance 2.21

°C/W

_JC

Junction-to-top-of-package

characterization parameter (still air)

per JEDEC JESD51-2

0.23

_JT

¹Results are from simulations. PCB is JEDEC multilayer. Thermal performance

for actual applications requires careful inspection of the conditions in the

application to determine if they are similar to those assumed in these

calculations.

ESD CAUTION

Rev. C | Page 8 of 48

Data Sheet

AD9914

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

D17

D16

D15/A7

D14/A6

D13/A5

DVDD (1.8V)

DGND

1

2

3

4

5

6

7

8

9

66 OSK

65 DROVER

64 DRHOLD

63 DRCTL

62 SYNC_IN

61 SYNC_OUT

60 AVDD (3.3V)

59 REF

58 LOOP_FILTER

57 AVDD (1.8V)

56 AVDD (1.8V)

55 REF CLK

D12/A4

D11/A3

D10/A2 10

D9/A1 11

D8/A0 12

AD9914

TOP VIEW

(Not to Scale)

D7 13

D6 14

D5 15

54

REF CLK

53 AVDD (3.3V)

52 AVDD (3.3V)

51 AGND

DVDD_I/O (3.3V) 16

DGND 17

50 AVDD (3.3V)

49 AGND

48 DAC_RSET

47 AVDD (3.3V)

46 AGND

D4/SYNCIO 18

D3/SDO 19

D2/SDIO/WR 20

D1/SCLK/RD 21

D0/CS/PWD 22

45 DAC_BP

NOTES

1. THE EPAD MUST BE SOLDERED TO GROUND.

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic

1, 2, 13 to 15, 68 D5 to D7, D16 to

I/O¹Description

I/O

Parallel Port Pins. The 32-bit parallel port offers the option for serial or parallel programming

of the internal registers. In addition, the parallel port can be configured to provide direct FSK,

PSK, or ASK (or combinations thereof) modulation data. The 32-bit parallel port configuration

is set by the state of the four function pins (F0 to F3).

to 72, 75 to 81,

87, 88

D31, D27 to D31

3

D15/A7

I/O

Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin

acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the

internal registers.

Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin

acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the

internal registers.

Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin

acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the

internal registers.

Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin

acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the

internal registers.

Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin

acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the

internal registers.

Parallel Port Pin/Address Line. Multipurpose pin depending on the state of the function pins

(F0 to F3). The state of the F0 to F3 function pins determines if this pin acts as a line for direct

FSK, PSK, or ASK data or as an address line for programming the internal registers.

Parallel Port Pin/Address Line. Multipurpose pin depending on the state of the function pins

(F0 to F3). The state of the F0 to F3 function pins determines if this pin acts as a line for direct

FSK, PSK, or ASK data or as an address line for programming the internal registers.

4

D14/A6

5

D13/A5

8

D12/A4

9

D11/A3

10

11

D10/A2

D9/A1

Rev. C | Page 9 of 48

AD9914

Data Sheet

Pin No.

Mnemonic

I/O¹Description

12

D8/A0

I/O

Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin

acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the

internal registers.

18

19

20

D4/SYNCIO

D3/SDO

I

Parallel Port Pin/Serial Port Synchronization Pin. This pin is D4 for direct FSK, PSK, or ASK data.

If serial mode is invoked via F0 to F3, this pin is used to reset the serial port.

Parallel Port Pin/Serial Data Output. This pin is D3 for direct FSK, PSK, or ASK data. If serial

mode is invoked via F0 to F3, this pin is used for readback mode for serial operation.

Parallel Port Pin/Serial Data Input and Output/Write Input. This pin is D2 for direct FSK, PSK,

or ASK data. If serial mode is invoked via F0 to F3, this pin is used for the SDIO for serial

operation. If parallel mode is enabled, this pin is used to write to change the values of the

internal registers.

I/O

D2/SDIO/WR

21

22

D1/SCLK/RD

D0/CS/PWD

I

Parallel Port Pin/Serial Clock/Read Input. This pin is D1 for direct FSK, PSK, or ASK data. If

serial mode is invoked via F0 to F3, this pin is used for SCLK for serial operation. If parallel

mode is enabled, this pin is used to read back the value of the internal registers.

Parallel Port Pin/Chip Select/Parallel Width. This pin is D0 for direct FSK, PSK, or ASK data. If

serial mode is invoked via F0 to F3, this pin is used for the chip select for serial operation. If

parallel mode is enabled, this pin is used to set either 8-bit data or16-bit data.

6, 23, 73

7, 17, 24, 74, 84

16, 83

32, 56, 57

33, 35, 37, 38,

44, 46, 49, 51

DVDD (1.8V)

DGND

DVDD_I/O (3.3V)

AVDD (1.8V)

AGND

I

Digital Core Supplies (1.8 V).

Digital Ground.

Digital Input/Output Supplies (3.3 V).

Analog Core Supplies (1.8 V).

Analog Ground.

34, 36, 39, 40,

43, 47, 50, 52,

53, 60

AVDD (3.3V)

PS0 to PS2

I

Analog DAC Supplies (3.3 V).

25, 26, 27

Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight

phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the

current contents of all I/O buffers to the corresponding registers. State changes should be set

up on the SYNC_CLK pin (Pin 82).

28, 29, 30, 31

F0 to F3

I

Function Pins. Digital inputs. The state of these pins determines if a serial or parallel interface

is used. In addition, the function pins determine how the 32-bit parallel data-word is

partitioned for FSK, PSK, or ASK modulation mode.

41

42

45

AOUT

O

I

DAC Complementary Output Source. Analog output (voltage mode). Internally connected

through a 50 Ω resistor to AVDD (3.3V).

DAC Output Source. Analog output (voltage mode). Internally connected through a 50 Ω

resistor to AVDD (3.3V).

DAC Bypass Pin. Provides access to the common control node of the DAC current sources.

Connecting a capacitor between this pin and ground can improve noise performance at the

DAC output.

AOUT

DAC_BP

48

DAC_RSET

O

Analog Reference. This pin programs the DAC output full-scale reference current. Connect a

3.3 kΩ resistor to AGND.

54

55

58

59

61

62

63

64

65

REF_CLK

LOOP_FILTER

REF

SYNC_OUT

SYNC_IN

DRCTL

I

Complementary Reference Clock Input. Analog input.

Reference Clock Input. Analog input.

External PLL Loop Filter Node.

I

O

I

Local PLL Reference Supply. Typically at 2.05 V.

Digital Synchronization Output. Used to synchronize multiple chips.

Digital Synchronization Input. Used to synchronize multiple chips.

Ramp Control. Digital input (active high). This pin controls the sweep direction (up/down).

Ramp Hold. Digital input (active high). Pauses the sweep when active.

Ramp Over. Digital output (active high). This pin switches to Logic 1 when the digital ramp

generator reaches its programmed upper or lower limit.

DRHOLD

DROVER

O

66

OSK

I

Output Shift Keying. Digital input (active high). When the OSK features are placed in either

manual or automatic mode, this pin controls the OSK function. In manual mode, it toggles

the multiplier between 0 (low) and the programmed amplitude scale factor (high). In

automatic mode, a low sweeps the amplitude down to zero and a high sweeps the

amplitude up to the amplitude scale factor.

Rev. C | Page 10 of 48

Data Sheet

AD9914

Pin No.

Mnemonic

I/O¹Description

67

EXT_PWR_DWN

I

External Power-Down. Digital input (active high). A high level on this pin initiates the

currently programmed power-down mode.

82

SYNC_CLK

O

Clock Output. Digital output. Many of the digital inputs on the chip, such as I/O_UPDATE,

PS[2:0], and the parallel data port (D0 to D31), must be set up on the rising edge of

this signal.

85

86

MASTER_RESET

I/O_UPDATE

EPAD

I

Master Reset. Digital input (active high). Clears all memory elements and sets registers to

default values.

Input/Output Update. Digital input (active high). A high on this pin transfers the contents of

the I/O buffers to the corresponding internal registers.

Exposed Pad. The EPAD must be soldered to ground.

¹I = input, O = output.

Rev. C | Page 11 of 48

AD9914

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

Nominal supply voltage; DAC R_SET= 3.3 kΩ, T_A= 25°C, unless otherwise noted.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz

175MHz/DIV

STOP 1.75GHz

CENTER 171.5MHz

50kHz/DIV

SPAN 500kHz

Figure 4. Wideband SFDR at 171.5 MHz

SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed)

Figure 7. Narrow-Band SFDR at 171.5 MHz,

SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 427.5MHz

50kHz/DIV

SPAN 500kHz

START 0Hz

175MHz/DIV

STOP 1.75GHz

Figure 8. Narrow-Band SFDR at 427.5 MHz,

SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed)

Figure 5. Wideband SFDR at 427.5 MHz

SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 696.5MHz

50kHz/DIV

SPAN 500kHz

START 0Hz

175MHz/DIV

STOP 1.75GHz

Figure 6. Wideband SFDR at 696.5 MHz,

SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed)

Figure 9. Narrow-Band SFDR at 696.5 MHz,

SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed)

Rev. C | Page 12 of 48

Data Sheet

AD9914

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 1396.5MHz

50kHz/DIV

SPAN 500kHz

START 0Hz

175MHz/DIV

STOP 1.75GHz

Figure 13. Narrow-Band SFDR at 1396.5 MHz,

SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed)

Figure 10. Wideband SFDR at 1396.5 MHz,

SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed)

–70

–80

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

SMA AND

ADCLK925

SMA

1M

10

100

1k

10k

100k

10M

100M

0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

FREQUENCY OFFSET (Hz)

f_C/f_S

Figure 14. Absolute Phase Noise of REF CLK Source Driving AD9914

Rohde & Schwarz SMA100 Signal Generator at 3.5 GHz Buffered by Series

ADCLK925

Figure 11. Wideband SFDR vs. Normalized f_OUT

SYSCLK = 3.5 GHz

–70

–80

0

–10

–20

–30

–40

–50

–60

–70

–80

SYSCLK = 1.5GHz

SYSCLK = 1.6GHz

SYSCLK = 1.7GHz

SYSCLK = 1.8GHz

SYSCLK = 1.9GHz

SYSCLK = 2.0GHz

SYSCLK = 2.1GHz

SYSCLK = 2.2GHz

SYSCLK = 2.3GHz

SYSCLK = 2.4GHz

SYSCLK = 2.5GHz

SYSCLK = 2.6GHz

SYSCLK = 2.7GHz

SYSCLK = 2.8GHz

SYSCLK = 2.9GHz

SYSCLK = 3.0GHz

SYSCLK = 3.1GHz

SYSCLK = 3.2GHz

SYSCLK = 3.3GHz

SYSCLK = 3.4GHz

SYSCLK = 3.5GHz

–90

–100

–110

1396MHz

–120

696MHz

–130

–140

–150

427MHz

–160

–170

171MHz

10

100

1k

10k

100k

1M

10M

100M

0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

FREQUENCY OFFSET (Hz)

f_C/f_S

Figure 15. Absolute Phase Noise Curves of DDS Output at 3.5 GHz Operation

Figure 12. Wideband SFDR vs. Normalized f_OUT

,

SYSCLK = 2.5 GHz to 3.5 GHz

Rev. C | Page 13 of 48

AD9914

Data Sheet

–70

–80

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

–90

–100

–110

–120

–130

–140

–150

–160

–170

978MHz

1396MHz

497MHz

305MHz

NORMALIZED

REF CLK SOURCE

123MHz

–170

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET (Hz)

Figure 16. Absolute Phase Noise Curves of Normalized REF CLK Source to

DDS Output at 1396 MHz (SYSCLK = 3.5 GHz)

Figure 19. Absolute Phase Noise Curves of DDS Output Using Internal PLL at

2.5 GHz Operation

–60

–70

–60

–70

–80

–90

–80

–90

–100

–110

–100

–120

–110

1396MHz

1396MHz ABSOLUTE

–130

–120

–130

–140

696MHz

–140

–150

–160

–170

–180

427MHz

10k

1396MHz RESIDUAL

–150

171MHz

1M

–160

10

100

1k

100k

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET (Hz)

Figure 17. Residual Phase Noise Curves

Figure 20. Residual PN vs. Absolute PN Measurement Curves at 1396 MHz

0.5

0.4

0.3

0.2

0.1

–60

–70

3.3V ANALOG

–80

–90

–100

–110

1396MHz ABSOLUTE

–120

1.8V DIGITAL

1.8V ANALOG

–130

–140

–150

–160

–170

–180

1396MHz RESIDUAL

3.3V DIGITAL

0

500

1000

1500

2000

2500

3000

3500

4000

10

100

1k

10k

100k

1M

10M

100M

SYSTEM CLOCK (MHz)

FREQUENCY OFFSET (Hz)

Figure 18. Power Supply Current vs. SYSCLK

Figure 21. Residual Phase Noise vs. Normalized Absolute REF CLK Source

Phase Noise at 1396 MHz

Rev. C | Page 14 of 48

Data Sheet

AD9914

930

920

910

900

890

880

870

1

CH2 1.0V Ω

M20.00ms

CH2

IT 40.0ps/pt

–6

–4

–2

0

2

4

6

A

1.64V

TIME (ms)

Figure 24. Measured Rising Linear Frequency Sweep

Figure 22. SYNC_OUT (f_SYSCLK/384)

930

920

910

900

890

880

870

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–6

–4

–2

0

2

4

6

500

1000

1500

2000

2500

3000

3500

TIME (ms)

SYSTEM CLOCK RATE (MHz)

Figure 25. Measured Falling Linear Frequency Sweep

Figure 23. DAC Calibration Time vs. SYSCLK Rate. See the DAC Calibration

Output Section for Formula.

Rev. C | Page 15 of 48

AD9914

Data Sheet

EQUIVALENT CIRCUITS

AGND

I

FS

CURRENT

SWITCH

ARRAY

CURRENT

SWITCH

ARRAY

SWITCH

CONTROL

DVDD (3.3V)

I

/2 + I

I

/2 – I

FS CODE

FS

CODE

42

AOUT

41

AOUT

INTERNAL

50Ω

INTERNAL

50Ω

AVDD (3.3V)

Figure 28. CMOS Input

Figure 26. DAC Output

AVDD (3.3V)

DVDD (3.3V)

REF_CLK

Figure 27. REF CLK input

Figure 29. CMOS Output

Rev. C | Page 16 of 48

Data Sheet

AD9914

THEORY OF OPERATION

The AD9914 has five modes of operation.

DIGITAL RAMP MODULATION MODE

•

Single tone

Profile modulation

Digital ramp modulation (linear sweep)

Parallel data port modulation

Programmable modulus mode

In digital ramp modulation mode, the modulated DDS signal

control parameter is supplied directly from the digital ramp

generator (DRG). The ramp generation parameters are

controlled through the serial or parallel I/O port.

The ramp generation parameters allow the user to control both

the rising and falling slopes of the ramp. The upper and lower

boundaries of the ramp, the step size and step rate of the rising

portion of the ramp, and the step size and step rate of the falling

portion of the ramp are all programmable.

The modes define the data source used to supply the DDS with

its signal control parameters: frequency, phase, or amplitude.

The partitioning of the data into different combinations of

frequency, phase, and amplitude is established based on the

mode and/or specific control bits and function pins.

The ramp is digitally generated with 32-bit output resolution.

The 32-bit output of the DRG can be programmed to affect

frequency, phase, or amplitude. When programmed for frequency,

all 32 bits are used. However, when programmed for phase or

amplitude, only the 16 MSBs or 12 MSBs, respectively, are used.

Although the various modes are described independently, they can

be enabled simultaneously. This provides an unprecedented level

of flexibility for generating complex modulation schemes. However,

to avoid multiple data sources from driving the same DDS signal

control parameter, the device has a built-in priority protocol.

The ramp direction (rising or falling) is externally controlled by

the DRCTL pin. An additional pin (DRHOLD) allows the user

to suspend the ramp generator in its present state. Note that

amplitude control must also be enabled using the OSK enable

bit in Register CFR1.

In single tone mode, the DDS signal control parameters come

directly from the profile programming registers. In digital ramp

modulation mode, the DDS signal control parameters are delivered

by a digital ramp generator. In parallel data port modulation mode,

the DDS signal control parameters are driven directly into the

parallel port.

PARALLEL DATA PORT MODULATION MODE

In parallel data port modulation mode, the modulated DDS signal

control parameter(s) are supplied directly from the 32-bit parallel

data port. The function pins define how the 32-bit data-word is

applied to the DDS signal control parameters. Formatting of the

32-bit data-word is unsigned binary, regardless of the destination.

The various modulation modes generally operate on only one of

the DDS signal control parameters (two in the case of the polar

modulation format via the parallel data port). The unmodulated

DDS signal control parameters are stored in programming registers

and automatically routed to the DDS based on the selected mode.

Parallel Data Clock (SYNC_CLK)

A separate output shift keying (OSK) function is also available.

This function employs a separate digital linear ramp generator

that affects only the amplitude parameter of the DDS. The OSK

function has priority over the other data sources that can drive

the DDS amplitude parameter. As such, no other data source

can drive the DDS amplitude when the OSK function is enabled.

The AD9914 generates a clock signal on the SYNC_CLK pin

that runs at 1/24 of the DAC sample rate (the sample rate of the

parallel data port). SYNC_CLK serves as a data clock for the

parallel port.

PROGRAMMABLE MODULUS MODE

In programmable modulus mode, the DRG is used as an

auxiliary accumulator to alter the frequency equation of the

DDS core, making it possible to implement fractions that are

not restricted to a power of 2 in the denominator. A standard

DDS is restricted to powers of 2 as a denominator because the

phase accumulator is a set of bits as wide as the frequency

tuning word (FTW).

SINGLE TONE MODE

In single tone mode, the DDS signal control parameters are

supplied directly from the profile programming registers. A

profile is an independent register that contains the DDS signal

control parameters. Eight profile registers are available. Note

that the profile pins must be used to select the desired register.

PROFILE MODULATION MODE

When in programmable modulus mode, however, the

frequency equation is:

f₀= (f_S)(FTW + A/B)/2³²

where f₀/f_S< ½, 0 ≤ FTW < 2³¹, 2 ≤ B ≤ 2³²– 1, and A < B.

This equation implies a modulus of B × 2³²(rather than 2³², in

the case of a standard DDS). Furthermore, because B is

programmable, the result is a DDS with a programmable

modulus.

Each profile is independently accessible. For FSK, PSK, or ASK

modulation, use the three external profile pins (PS[2:0]) to select

the desired profile. A change in the state of the profile pins with

the next rising edge on SYNC_CLK updates the DDS with the

parameters specified by the selected profile. Therefore, the profile

change must meet the setup and hold times to the SYNC_CLK

rising edge. Note that amplitude control must also be enabled

using the OSK enable bit in the CFR1 register (0x00[8]).

Rev. C | Page 17 of 48

AD9914

Data Sheet

When in programmable modulus mode, the 32-bit auxiliary

accumulator operates in a way that allows it to roll over at a

value other than its full capacity of 2³². That is, it operates with a

modified modulus based on the programmable value of B. With

each roll over of the auxiliary accumulator, a value of 1 LSB

adds to the current accumulated value of the 32-bit phase

accumulator. This behavior changes the modulus of the phase

accumulator to B × 2³²(instead of 2³²), allowing it to synthesize

the desired f₀.

Reducing this fraction to lowest terms yields 3/10; therefore,

M = 3 and N = 10. FTW is the integer part of (M × 2³²)/N, or

(3 × 2³²)/10, which is 1,288,490,188 (0x4CCCCCCC in 32-bit

hexadecimal notation). The remainder, Y, of (3 × 2³²)/10, is (2³²

× 3) − (1,288,490,188 × 10), which is 8. Therefore, Y/N is 8/10,

which reduces to 4/5. Therefore, A = 4 and B = 5 (0x00000004

and 0x00000005 in 32-bit hexadecimal notation, respectively).

Programming the AD9914 with these values of FTW, A, and B

results in an output frequency that is exactly 3/10 of the system

clock frequency.

To determine the programmable modulus mode register values

for FTW, A, and B, the user must first define f₀/f_Sas a ratio of

relatively prime integers, M/N. That is, having converted f₀and

f_Sto integers, M and N, reduce the fraction, M/N, to its lowest

terms. Then, divide M × 232 by N. The integer part of this division

operation is the value of FTW (Register 0x04[31:0]). The

remainder, Y, of this division operation is

MODE PRIORITY

The ability to activate each mode independently makes it

possible to have multiple data sources attempting to drive the

same DDS signal control parameter (frequency, phase, and

amplitude). To avoid contention, the AD9914 has a built-in

priority system. Table 6 summarizes the priority for each of the

DDS modes. The data source column in Table 6 lists data sources

for a particular DDS signal control parameter in descending

order of precedence. For example, if the profile mode enable bit

and the parallel data port enable bit (0x01[23:22]) are set to

Logic 1 and both are programmed to source the frequency

tuning word to DDS output, the profile modulation mode has

priority over the parallel data port modulation mode.

Y = (2³²× M) – (FTW × N)

The value of Y facilitates the determination of A and B by taking

the fraction, Y/N, and reducing it to its lowest terms. Then, the

numerator of the reduced fraction is A (Register 0x06[31:0])

and the denominator is the B (Register 0x05[31:0]).

For example, synthesizing precisely 300 MHz with a 1 GHz

system clock is not possible with a standard DDS. It is possible,

however, using programmable modulus as follows.

First, express f₀/f_Sas a ratio of integers:

300,000,000/1,000,000,000

Table 6. Data Source Priority

DDS Signal Control Parameters

Priority

Data Source

Conditions

Highest

Priority

Programmable If programmable modulus mode is used to output frequency only, no other data source can be used to

modulus

control the output frequency in this mode. Note that the DRG is used in conjunction with programmable

modulus mode; therefore, the DRG cannot be used to sweep phase or amplitude in programmable

modulus mode.

If output phase offset control is desired, enable profile mode and use the profile registers and profile

pins accordingly to control output phase adjustment.

If output amplitude control is desired, enable profile mode and use the profile registers and profile pins

accordingly to control output amplitude adjustment. Note that the OSK enable bit must be set to control

the output amplitude.

DRG

The digital ramp modulation mode is the next highest priority mode. If the DRG is enabled to sweep

output frequency, phase, or amplitude, the two parameters not being swept can be controlled

independently via the profile mode.

Profiles

The profile modulation mode is the next highest priority mode. Profile mode can be used to control all

three parameters independently, if desired.

Lowest

Priority

Parallel port

Parallel data port modulation has the lowest priority but the most flexibility as far as changing any

parameter at the high rate. See the Programming and Function Pins section.

Rev. C | Page 18 of 48

Data Sheet

AD9914

FUNCTIONAL BLOCK DETAIL

DDS CORE

POW













2π

2¹⁴

The direct digital synthesizer (DDS) block generates a reference

signal (sine or cosine based on 0x00[16], the enable sine output

bit). The parameters of the reference signal (frequency, phase,

and amplitude) are applied to the DDS at its frequency, phase

offset, and amplitude control inputs, as shown in Figure 30.

∆θ =

POW









360



2¹⁴



where the upper quantity is for the phase offset expressed as

radian units and the lower quantity as degrees.

The output frequency (f_OUT) of the AD9914 is controlled by the

frequency tuning word (FTW) at the frequency control input to

the DDS. The relationship among f_OUT, FTW, and f_SYSCLKis given by

To find the POW value necessary to develop an arbitrary Δθ,

solve the preceding equation for POW and round the result (in

a manner similar to that described previously for finding an

arbitrary FTW).

FTW













f_OUT

=

f

SYSCLK

(1)

2³²

The relative amplitude of the DDS signal can be digitally scaled

(relative to full scale) by means of a 12-bit amplitude scale factor

(ASF). The amplitude scale value is applied at the output of the

angle-to-amplitude conversion block internal to the DDS core.

The amplitude scale is given by

where FTW is a 32-bit integer ranging in value from 0 to

2,147,483,647 (2³¹− 1), which represents the lower half of the

full 32-bit range. This range constitutes frequencies from dc to

Nyquist (that is, ½ f_SYSCLK).

The FTW required to generate a desired value of f_OUTis found

by solving Equation 1 for FTW, as given in Equation 2.

ASF

2¹²

Amplitude Scale =

(3)

ASF



























³²









f_OUT

f_SYSCLK

20log



2¹²

(2)

FTW = round 2



where the upper quantity is amplitude expressed as a fraction of

full scale and the lower quantity is expressed in decibels relative

to full scale.

where the round(x) function rounds the argument (the value of

x) to the nearest integer. This is required because the FTW is

constrained to be an integer value. For example, for f_OUT

=

To find the ASF value necessary for a particular scale factor, solve

Equation 3 for ASF and round the result (in a manner similar

to that described previously for finding an arbitrary FTW).

41 MHz and f_SYSCLK= 122.88 MHz, FTW = 1,433,053,867

(0x556AAAAB).

Programming an FTW greater than 2³¹produces an aliased

image that appears at a frequency given by

When the AD9914 is programmed to modulate any of the DDS

signal control parameters, the maximum modulation sample

rate is 1/24 f_SYSCLK. This means that the modulation signal exhibits

images at multiples of 1/24 f_SYSCLK. The impact of these images

must be considered when using the device as a modulator.

FTW











(for FTW ≥ 2³¹)

f_OUT= 1−

f

SYSCLK



2³²

The relative phase of the DDS signal can be digitally controlled

by means of a 16-bit phase offset word (POW). The phase offset

is applied prior to the angle-to-amplitude conversion block internal

to the DDS core. The relative phase offset (Δθ) is given by

DDS SIGNAL CONTROL PARAMETERS

12

AMPLITUDE

CONTROL

PHASE

16

OFFSET

CONTROL

MSB ALIGNED

32-BIT

12

ACCUMULATOR

32

14

ANGLE-TO-

AMPLITUDE

CONVERSION

(SINE OR

17

(MSBs)

12

32

32 17

FREQUENCY

CONTROL

D Q

R

COSINE)

TO DAC

DDS_CLK

ACCUMULATOR

RESET

Figure 30. DDS Block Diagram

Rev. C | Page 19 of 48

AD9914

Data Sheet

output is typically passed through an external reconstruction

filter that serves to remove the artifacts of the sampling process

and other spurs outside the filter bandwidth.

12-BIT DAC OUTPUT

The AD9914 incorporates an integrated 12-bit, current output

DAC. The output current is delivered as a balanced signal using

two outputs. The use of balanced outputs reduces the potential

amount of common-mode noise present at the DAC output,

offering the advantage of an increased signal-to-noise ratio. An

external resistor (R_SET) connected between the DAC_RSET pin

and AGND establishes the reference current. The recommended

value of R_SETis 3.3 kΩ.

Because the DAC constitutes a sampled system, its output must

be filtered so that the analog waveform accurately represents the

digital samples supplied to the DAC input. The unfiltered DAC

output contains the desired baseband signal, which extends from

dc to the Nyquist frequency (f_S/2). It also contains images of the

baseband signal that theoretically extend to infinity. Notice that

the odd numbered images (shown in Figure 31) are mirror

images of the baseband signal. Furthermore, the entire DAC

output spectrum is affected by a sin(x)/x response, which is

caused by the sample-and-hold nature of the DAC output signal.

Attention should be paid to the load termination to keep the

output voltage within the specified compliance range; voltages

developed beyond this range cause excessive distortion and can

damage the DAC output circuitry.

For applications using the fundamental frequency of the DAC

output, the response of the reconstruction filter should preserve

the baseband signal (Image 0), while completely rejecting all

other images. However, a practical filter implementation

typically exhibits a relatively flat pass band that covers the

desired output frequency plus 20%, rolls off as steeply as

possible, and then maintains significant (though not complete)

rejection of the remaining images. Depending on how close

unwanted spurs are to the desired signal, a third-, fifth-, or

seventh-order elliptic low-pass filter is common.

DAC CALIBRATION OUTPUT

The DAC CAL enable bit in the CFR4 control register (0x03[24])

must be manually set and then cleared after each power-up and

every time the REF CLK or internal system clock is changed.

This initiates an internal calibration routine to optimize the

setup and hold times for internal DAC timing. Failure to

calibrate may degrade performance and even result in loss of

functionality. The length of time to calibrate the DAC clock is

calculated from the following equation:

531,840

Some applications operate from an image above the Nyquist

frequency, and those applications use a band-pass filter instead

of a low-pass filter. The design of the reconstruction filter has a

significant impact on the overall signal performance. Therefore,

good filter design and implementation techniques are important

for obtaining the best possible jitter results.

t

_CAL( f_S) =

f_S

RECONSTRUCTION FILTER

The DAC output signal appears as a sinusoid sampled at f_S. The

frequency of the sinusoid is determined by the frequency tuning

word (FTW) that appears at the input to the DDS. The DAC

MAGNITUDE

(dB)

IMAGE 0

IMAGE 1

IMAGE 2

IMAGE 3

IMAGE 4

0

–20

PRIMARY

SIGNAL

FILTER

RESPONSE

–40

SIN(x)/x

ENVELOPE

–60

–80

SPURS

f

–100

f_s/2

f_s

3f_s/2

2

f_s

5f_s/2

BASE BAND

Figure 31. DAC Spectrum vs. Reconstruction Filter Response

Rev. C | Page 20 of 48

Data Sheet

AD9914

is relatively high; therefore, its effect on the termination impedance

is negligible and can usually be chosen to be the same as the output

impedance of the signal source. The bottom two examples in

Figure 33 assume a signal source with a 50 Ω output impedance.

0.1µF

CLOCK INPUT (REF_CLK/REF_CLK)

REF_CLK

REF_CLK/

Overview

The AD9914 supports a number of options for producing the

internal SYSCLK signal (that is, the DAC sample clock) via the

REF_CLK

REF_CLK/

input pins. The REF_CLK input can be

55 REF_CLK

PECL,

LVPECL,

DIFFERENTIAL SOURCE,

DIFFERENTIAL INPUT

driven directly from a differential or single-ended source. There

is also an internal phase-locked loop (PLL) multiplier that can

be independently enabled. However, the PLL limits the SYSCLK

signal between 2.4 GHz and 2.5 GHz operation. A differential

signal is recommended when the PLL is bypassed. A block

diagram of the REF_CLK functionality is shown in Figure 32.

Figure 32 also shows how the CFR3 control bits are associated

with specific functional blocks.

OR

TERMINATION

0.1µF

LVDS

DRIVER

54

REF_CLK

0.1µF

BALUN

(1:1)

55

54

REF_CLK

SINGLE-ENDED SOURCE,

DIFFERENTIAL INPUT

50Ω

LOOP_FILTER

0.1µF

58

PLL ENABLE

0.1µF

DOUBLER ENABLE

CFR3[18]

CFR3[19]

55

54

REF_CLK

SINGLE-ENDED SOURCE,

SINGLE-ENDED INPUT

DOUBLER

CLOCK EDGE

CFR3[16]

50Ω

LOOP

ENABLE

IN

FILTER

0.1µF

1

0

×2

PLL

OUT

SYSCLK

1

0

Figure 33. Direct Connection Diagram

÷ 1, 2, 4, 8

CHARGE

PUMP

DIVIDE

Phase-Locked Loop (PLL) Multiplier

2

INPUT DIVIDER

RESET CFR3[22]

REF_CLK

2

7

An internal phase-locked loop (PLL) provides the option to use

a reference clock frequency that is significantly lower than the

system clock frequency. The PLL supports a wide range of

programmable even frequency multiplication factors (20× to

510×) as well as a programmable charge pump current and

external loop filter components (connected via the PLL

LOOP_FILTER pin). These features add an extra layer of

flexibility to the PLL, allowing optimization of phase noise

performance and flexibility in frequency plan development. The

PLL is also equipped with a PLL lock bit indicator (0x1B[24]).

N

55

54

I

INPUT DIVIDER RATIO

CFR3[21:20]

CFR3[15:8]

CP

CFR3[5:3]

Figure 32. REF_CLK Block Diagram

The PLL enable bit is used to choose between the PLL path or

the direct input path. When the direct input path is selected,

REF_CLK

the REF_CLK/

pins must be driven by an external

signal source (single-ended or differential). Input frequencies

up to 3.5 GHz are supported.

The PLL output frequency range (f_SYSCLK) is constrained to the

range of 2.4 GHz ≤ f_SYSCLK≤ 2.5 GHz by the internal VCO.

REF_CLK

Direct Driven REF_CLK/

REF_CLK

With a differential signal source, the REF_CLK/

pins

VCO Calibration

are driven with complementary signals and ac-coupled with 0.1 µF

capacitors. With a single-ended signal source, either a single-

ended-to-differential conversion can be employed or the

REF_CLK input can be driven single-ended directly. In either

case, 0.1 µF capacitors are used to ac couple both

When using the PLL to generate the system clock, VCO calibration

is required to tune the VCO appropriately and achieve good

performance. When the reference input signal is stable, the

VCO cal enable bit in the CFR1 register, 0x00[24], must be

asserted. Subsequent VCO calibrations require that the VCO

calibration bit be cleared prior to initiating another VCO

calibration. VCO calibration must occur before DAC calibration

to ensure optimal performance and functionality.

REF_CLK

REF_CLK/

bias voltage of ~1.35 V. See Figure 33 for more details.

REF_CLK

pins to avoid disturbing the internal dc

The REF_CLK/

(~1.2 kΩ single-ended). Most signal sources have relatively low

REF_CLK

input resistance is ~2.5 kΩ differential

output impedances. The REF_CLK/

input resistance

Rev. C | Page 21 of 48

AD9914

Data Sheet

PLL Charge Pump/Total Feedback Divider

C

= 560pF (RECOMMENDED)

Z

0.47µF

The charge pump current (I_CP) value is automatically chosen via

the VCO calibration process and N value (N = 10 to 255) stored

in Feedback Divider N[7:0] in the CFR3 register (0x02[15:8]). N

values below 10 should be avoided.

REF

LOOP_FILTER

59

58

C

P

50pF

R

(3.5kΩ)

PZ

Note that the total PLL multiplication value for the PLL is always

2N due to the fixed divide by 2 element in the feedback path.

This is shown in Figure 34. This fixed divide by 2 element forces

only even PLL multiplication.

REFCLK PLL

PFD CP

PLL IN

VCO

PLL OUT

÷N

÷2

To manually override the charge pump current value, the manual

Figure 34. REF CLK PLL External Loop Filter

I_CPselection bit in CFR3 (0x02[6]) must be set to Logic 1. This

provides the user with additional flexibility to optimize the PLL

performance. Table 7 lists the bit settings vs. the nominal charge

pump current.

PLL LOCK INDICATION

When the PLL is in use, the PLL lock bit (0x1B[24])provides an

active high indication that the PLL has locked to the REF CLK

input signal.

Table 7. PLL Charge Pump Current

I_CPBits (CFR3[5:3])

Charge Pump Current, I_CP(μA)

OUTPUT SHIFT KEYING (OSK)

000

001

010

011

100

101

110

111

125

250

375

500 (default)

625

750

875

1000

The OSK function (see Figure 35) allows the user to control the

output signal amplitude of the DDS. The amplitude data generated

by the OSK block has priority over any other functional block

that is programmed to deliver amplitude data to the DDS.

Therefore, the OSK data source, when enabled, overrides all

other amplitude data sources.

The operation of the OSK function is governed by two CFR1

register bits, OSK enable (0x00[8]) and external OSK enable

(0x00[9]), the external OSK pin, the profile pins, and the 12 bits

of amplitude scale factor found in one of eight profile registers.

The profile pins are used to select the profile register containing

the desired amplitude scale factor.

Table 8. N divider vs. Charge Pump Current

Recommended Charge Pump

Current, I_CP(μA)

N Divider Range

10 to 15

16 to 23

24 to 35

36 to 43

44 to 55

56 to 63

64 to 79

80 to 100

125

250

375

500

625

750

875

1000

The primary control for the OSK block is the OSK enable bit

(0x00[8]). When the OSK function is disabled, the OSK input

controls and OSK pin are ignored.

The OSK pin functionality depends on the state of the external

OSK enable bit and the OSK enable bit. When both bits are set

to Logic 1 and the OSK pin is Logic 0, the output amplitude is

forced to 0; otherwise, if the OSK pin is Logic 1, the output

amplitude is set by the amplitude scale factor value in one of

eight profile registers depending on the profile pin selection.

PLL Loop Filter Components

The loop filter is mostly internal to the device, as shown in

Figure 34. The recommended external capacitor value is 560 pF.

Because C_Pand R_PZare integrated, it is not recommended to

adjust the loop bandwidth via the external capacitor value. The

better option is to adjust the charge pump current even though

it is a coarse adjustment.

PS0 PS1 PS2

25 26 27

OSK

66

OSK ENABLE

EXTERNAL

OSK ENABLE

TO DDS

AMPLITUDE

CONTROL

OSK

CONTROLLER

12

For example, suppose the PLL is manually programmed such

that I_CP= 375 μA, K_V= 60 MHz/V, and N = 25. This produces a

loop bandwidth of approximately 250 kHz.

AMPLITUDE SCALE

FACTOR (1 OF 8

SELECTED PROFILE

REGISTERS [27:16])

12

PARAMETER

DDS CLOCK

Figure 35. OSK Block Diagram

Rev. C | Page 22 of 48

Data Sheet

AD9914

The output of the DRG is a 32-bit unsigned data bus that can be

routed to any one of the three DDS signal control parameters, as

controlled by the two digital ramp destination bits in Control

Function Register 2 according to Table 9. The 32-bit output bus

is MSB-aligned with the 32-bit frequency parameter, the 16-bit

phase parameter, or the 12-bit amplitude parameter, as defined

by the destination bits. When the destination is phase or amplitude,

the unused LSBs are ignored.

DIGITAL RAMP GENERATOR (DRG)

DRG Overview

To sweep phase, frequency, or amplitude from a defined start

point to a defined endpoint, a completely digital ramp generator

is included in the AD9914. The DRG makes use of eight control

register bits, three external pins, and five 32-bit registers (see

Figure 36).

Table 9. Digital Ramp Destination

Digital Ramp

Destination Bits

(CFR2[21:20])

DDS Signal

Control

Parameter

63

64

65

Bits Assigned to

DDS Parameter

DIGITAL RAMP ENABLE

00

01

1x¹

Frequency

Phase

Amplitude

31:0

31:18

31:20

2

DIGITAL RAMP DESTINATION

DIGITAL RAMP NO-DWELL

LOAD LRR AT I/O_UPDATE

¹x = don’t care.

CLEAR DIGITAL

RAMP ACCUMULATOR

The ramp characteristics of the DRG are fully programmable. This

includes the upper and lower ramp limits, and independent control

of the step size and step rate for both the positive and negative slope

characteristics of the ramp. A detailed block diagram of the DRG is

shown in Figure 37.

AUTOCLEAR DIGITAL

RAMP ACCUMULATOR

32

DIGITAL RAMP LOWER LIMIT REGISTER

32

DIGITAL

RAMP

GENERATOR

TO DDS

SIGNAL

CONTROL

PARAMETER

DIGITAL RAMP UPPER LIMIT REGISTER

32

The direction of the ramping function is controlled by the

DRCTL pin. Logic 0 on this pin causes the DRG to ramp with a

negative slope, whereas Logic 1 causes the DRG to ramp with a

positive slope.

RISING DIGITAL RAMP STEP

SIZE REGISTER

FALLING DIGITAL RAMP STEP

SIZE REGISTER

DIGITAL RAMP RATE REGISTER

The DRG also supports a hold feature controlled via the DRHOLD

pin. When this pin is set to Logic 1, the DRG is stalled at its last

state; otherwise, the DRG operates normally. The DDS signal

control parameters that are not the destination of the DRG are

taken from the active profile.

DDS CLOCK

Figure 36. Digital Ramp Block Diagram

The primary control for the DRG is the digital ramp enable bit

(0x01[19]). When disabled, the other DRG input controls are

ignored and the internal clocks are shut down to conserve power.

DIGITAL RAMP ACCUMULATOR

32

0

1

DECREMENT STEP SIZE

INCREMENT STEP SIZE

32

TO DDS

32

SIGNAL

D

Q

LIMIT CONTROL

32

CONTROL

PARAMETER

63

DRCTL

32

R

UPPER

LIMIT

LOWER

LIMIT

16

0

1

NEGATIVE SLOPE RATE

POSITIVE SLOPE RATE

16

2

NO-DWELL

CONTROL

NO DWELL

ACCUMULATOR

RESET

CONTROL

LOGIC

CLEAR DIGITAL RAMP ACCUMULATOR

AUTOCLEAR DIGITAL RAMP ACC

PRESET

LOAD

.

LOAD

CONTROL

LOGIC

LOAD LRR AT I/O_UPDATE

Q

DIGITAL

RAMP

TIMER

64

DRHOLD

DDS CLOCK

Figure 37. Digital Ramp Generator Detail

Rev. C | Page 23 of 48

AD9914

Data Sheet

DRG Slope Control

Note that the frequency units are the same as those used to

represent f_SYSCLK(MHz, for example). The amplitude units are

the same as those used to represent I_FS, the full-scale output

current of the DAC (mA, for example).

The core of the DRG is a 32-bit accumulator clocked by a

programmable timer. The time base for the timer is the DDS

clock, which operates at 1/24 f_SYSCLK. The timer establishes the

interval between successive updates of the accumulator. The

positive (+Δt) and negative (−Δt) slope step intervals are

independently programmable as given by

The phase and amplitude step size equations yield the average

step size. Although the step size accumulates with 32-bit precision,

the phase or amplitude destination exhibits only 16 bits or 12 bits,

respectively. Therefore, at the destination, the actual phase or

amplitude step is the accumulated 32-bit value truncated to

16 bits or 12 bits, respectively.

24P

f_SYSCLK

+ ∆t =

24N

− ∆t =

As described previously, the step interval is controlled by a

16-bit programmable timer. There are three events that can

cause this timer to be reloaded prior to its expiration. One event

occurs when the digital ramp enable bit transitions from cleared

to set, followed by an I/O update. A second event is a change of

state in the DRCTL pin. The third event is enabled using the load

LRR at I/O update bit (0x00[15]).

f_SYSCLK

where P and N are the two 16-bit values stored in the 32-bit digital

ramp rate register and control the step interval. N defines the step

interval of the negative slope portion of the ramp. P defines the step

interval of the positive slope portion of the ramp.

The step size of the positive (STEP_P) and negative (STEP_N) slope

portions of the ramp are 32-bit values programmed into the 32-bit

rising and falling digital ramp step size registers (0x06 and 0x07).

Program each of the step sizes as an unsigned integer (the hardware

automatically interprets STEP_Nas a negative value). The

relationship between the 32-bit step size values and actual units

of frequency, phase, or amplitude depend on the digital ramp

destination bits. Calculate the actual frequency, phase, or amplitude

step size by substituting STEP_Nor STEP_Pfor M in the following

equations as required:

DRG Limit Control

The ramp accumulator is followed by limit control logic that

enforces an upper and lower boundary on the output of the

ramp generator. Under no circumstances does the output of the

DRG exceed the programmed limit values while the DRG is

enabled. The limits are set through the 64-bit digital ramp limit

register. Note that the upper limit value must be greater than the

lower limit value to ensure normal operation.

DRG Accumulator Clear

M













The ramp accumulator can be cleared (that is, reset to 0) under

program control. When the ramp accumulator is cleared, it forces

the DRG output to the lower limit programmed into the digital

ramp limit register.

FrequencyStep =

f

SYSCLK

2³²

πM

PhaseStep =

2³¹

(radians)

(degrees)

With the limit control block embedded in the feedback path of the

accumulator, resetting the accumulator is equivalent to presetting

it to the lower limit value.

45M

PhaseStep =

2²⁹

M









AmplitudeStep =

I





FS

2³²

Rev. C | Page 24 of 48

Data Sheet

AD9914

P DDS CLOCK CYCLES

N DDS CLOCK CYCLES

NEGATIVE

1 DDS CLOCK CYCLE

STEP SIZE

POSITIVE

STEP SIZE

+Δ

t

–Δt

UPPER LIMIT

DRG OUTPUT

LOWER LIMIT

DROVER

DIGITAL RAMP ENABLE

DRCTL

DRHOLD

CLEAR DIGITAL

RAMP ACCUMULATOR

AUTOCLEAR DIGITAL

RAMP ACCUMULATOR

I/O_UPDATE

1

2

3

4

5

6

7

8

9

11

13

10

12

Figure 38. Normal Ramp Generation

Event 4—DRCTL transitions to Logic 0 to initiate a negative

slope at the DRG output. In this example, the DRCTL pin is

held long enough to cause the DRG to reach its programmed

lower limit. The DRG remains at the lower limit until DRCTL = 1,

or until the lower limit is reprogrammed to a lower value. In the

latter case, the DRG immediately resumes its previous negative

slope profile.

Normal Ramp Generation

Normal ramp generation implies that both no-dwell bits are

cleared (see the No-Dwell Ramp Generation section for details).

In Figure 38, a sample ramp waveform is depicted with the

required control signals. The top trace is the DRG output. The

next trace down is the status of the DROVER output pin (assuming

that the DRG over output enable bit is set). The remaining traces

are control bits and control pins. The pertinent ramp parameters

are also identified (upper and lower limits plus step size and Δt

for the positive and negative slopes). Along the bottom, circled

numbers identify specific events. These events are referred to by

number (Event 1 and so on) in the following paragraphs.

Event 5—DRCTL transitions to Logic 1 for the second time,

initiating a second positive slope.

Event 6—The positive slope profile is interrupted by DRHOLD

transitioning to Logic 1. This stalls the ramp accumulator and

freezes the DRG output at its last value.

In this example, the positive and negative slopes of the ramp are

different to demonstrate the flexibility of the DRG. The parameters

of both slopes can be programmed to make the positive and

negative slopes the same.

Event 7—DRHOLD transitions to Logic 0, releasing the ramp

accumulator and reinstating the previous positive slope profile.

Event 8—The clear digital ramp accumulator bit is set, which

has no effect on the DRG because the bit is not effective until an

I/O update is issued.

Event 1—The digital ramp enable bit is set, which has no effect

on the DRG output because the bit is not effective until an I/O

update occurs.

Event 9—An I/O update registers that the clear digital ramp

accumulator bit is set, resetting the ramp accumulator and forcing

the DRG output to the programmed lower limit. The DRG output

remains at the lower limit until the clear condition is removed.

Event 2—An I/O update registers the digital ramp enable bit. If

DRCTL = 1 is in effect (the gray portion of the DRCTL trace),

the DRG output immediately begins a positive slope (the gray

portion of the DRG output trace). Otherwise, if DRCTL = 0, the

DRG output is initialized to the lower limit.

Event 10—The clear digital ramp accumulator bit is cleared,

which has no effect on the DRG output because the bit is not

effective until an I/O update is issued.

Event 3—DRCTL transitions to Logic 1 to initiate a positive

slope at the DRG output. In this example, the DRCTL pin is

held long enough to cause the DRG to reach its programmed

upper limit. The DRG remains at the upper limit until the ramp

accumulator is cleared (DRCTL = 0) or the upper limit is

reprogrammed to a higher value. In the latter case, the DRG

immediately resumes its previous positive slope profile.

Event 11—An I/O update registers that the clear digital ramp

accumulator bit is cleared, releasing the ramp accumulator; and

the previous positive slope profile restarts.

Event 12—The autoclear digital ramp accumulator bit is set,

which has no effect on the DRG output because the bit is not

effective until an I/O update is issued.

Rev. C | Page 25 of 48

AD9914

Data Sheet

Event 13—An I/O update registers that the autoclear digital

ramp accumulator bit is set, resetting the ramp accumulator.

However, with an automatic clear, the ramp accumulator is held

in reset for only a single DDS clock cycle. This forces the DRG

output to the lower limit, but the ramp accumulator is immedi-

ately made available for normal operation. In this example, the

DRCTL pin remains Logic 1; therefore, the DRG output restarts

the previous positive ramp profile.

tion between the limits. Likewise, if the DRG output is in the

midst of a negative slope and the DRCTL pin transitions from

Logic 0 to Logic 1, the DRG immediately switches to the positive

slope parameters and resumes oscillation between the limits.

When both no-dwell bits are set, the DROVER signal produces

a positive pulse (two cycles of the DDS clock) each time the DRG

output reaches either of the programmed limits (assuming that

the DRG over output enable bit (0x01[13]) is set).

No-Dwell Ramp Generation

A no-dwell high DRG output waveform is shown in Figure 39.

The waveform diagram assumes that the digital ramp no-dwell

high bit is set and has been registered by an I/O update. The

status of the DROVER pin is also shown with the assumption

that the DRG over output enable bit has been set.

The two no-dwell high and no-dwell low bits (0x01[18:17]) in

CFR2 add to the flexibility of the DRG capabilities. During normal

ramp generation, when the DRG output reaches the programmed

upper or lower limit, it simply remains at the limit until the

operating parameters dictate otherwise. However, during no-dwell

operation, the DRG output does not necessarily remain at the limit.

For example, if the digital ramp no-dwell high bit is set when the

DRG reaches the upper limit, it automatically (and immediately)

snaps to the lower limit (that is, it does not ramp back to the lower

limit; it jumps to the lower limit). Likewise, when the digital ramp

no-dwell low bit is set, and the DRG reaches the lower limit, it

automatically (and immediately) snaps to the upper limit.

The circled numbers in Figure 39 indicate specific events, which

are explained as follows:

Event 1—Indicates the instant that an I/O update registers that the

digital ramp enable bit is set.

Event 2—DRCTL transitions to Logic 1, initiating a positive

slope at the DRG output.

Event 3—DRCTL transitions to Logic 0, which has no effect on

the DRG output.

During no-dwell operation, the DRCTL pin is monitored for state

transitions only; that is, the static logic level is immaterial.

Event 4—Because the digital ramp no-dwell high bit is set, the

moment that the DRG output reaches the upper limit, it imme-

diately switches to the lower limit, where it remains until the

next Logic 0 to Logic 1 transition of DRCTL.

During no-dwell high operation, a positive transition of the

DRCTL pin initiates a positive slope ramp, which continues

uninterrupted (regardless of any further activity on the DRCTL

pin) until the upper limit is reached.

Event 5—DRCTL transitions from Logic 0 to Logic 1, which

restarts a positive slope ramp.

During no-dwell low operation, a negative transition of the DRCTL

pin initiates a negative slope ramp, which continues uninterrupted

(regardless of any further activity on the DRCTL pin) until the

lower limit is reached.

Event 6 and Event 7—DRCTL transitions are ignored until the

DRG output reaches the programmed upper limit.

Event 8—Because the digital ramp no-dwell high bit is set, the

moment that the DRG output reaches the upper limit, it immedi-

ately switches to the lower limit, where it remains until the next

Logic 0 to Logic 1 transition of DRCTL.

Setting both no-dwell bits invokes a continuous ramping mode

of operation; that is, the DRG output automatically oscillates

between the two limits using the programmed slope parameters.

Furthermore, the function of the DRCTL pin is slightly different.

Instead of controlling the initiation of the ramp sequence, it

only serves to change the direction of the ramp; that is, if the

DRG output is in the midst of a positive slope and the DRCTL

pin transitions from Logic 1 to Logic 0, the DRG immediately

switches to the negative slope parameters and resumes oscilla-

Operation with the digital ramp no-dwell low bit set (instead of

the digital ramp no-dwell high bit) is similar, except that the DRG

output ramps in the negative direction on a Logic 1 to Logic 0

transition of DRCTL and jumps to the upper limit upon

reaching the lower limit.

P DDS CLOCK CYCLES

POSITIVE

STEP SIZE

+Δ

t

UPPER LIMIT

DRG OUTPUT

LOWER LIMIT

DROVER

DRCTL

1

2

3

4

5

6

7

8

Figure 39. No-Dwell High Ramp Generation

Rev. C | Page 26 of 48

Data Sheet

AD9914

DROVER Pin

POWER-DOWN CONTROL

The DROVER pin provides an external signal to indicate the status

of the DRG. Specifically, when the DRG output is at either of

the programmed limits, the DROVER pin is Logic 1; otherwise,

it is Logic 0. In the special case of both no-dwell bits set, the

DROVER pin pulses positive for two DDS clock cycles each

time the DRG output reaches either of the programmed limits.

The AD9914 offers the ability to independently power down

three specific sections of the device. Power-down functionality

applies to the following:

•

Digital core

DAC

Input REF CLK clock circuitry

Frequency Jumping Capability in DRG Mode

A power-down of the digital core disables the ability to update

the serial/parallel I/O port. However, the digital power-down

bit (0x00[7]) can still be cleared to prevent the possibility of a

nonrecoverable state.

Another feature of the AD9914 allows the user to skip a predefined

range of frequencies during a normal sweep. The frequency jump

enable bit in CFR2 (0x01[14]) enables this functionality. When

this bit is set, the sweeping logic monitors the instantaneous

frequency. When it reaches the frequency point defined in the

lower frequency jump register (0x09) on the next accumulation

cycle, instead of accumulating a delta tuning word as in normal

sweeping, it skips directly to the frequency value set in the upper

frequency jump register (0x0A), and vice versa. Figure 40 shows

how this feature works.

Software power-down is controlled via three independent

power-down bits in CFR1. Software control requires that the

EXT_PWR_DWN pin be forced to a Logic 0 state. In this case,

setting the desired power-down bits (0x00[7:5]) via the serial

I/O port powers down the associated functional block, whereas

clearing the bits restores the function.

Alternatively, all three functions can be simultaneously powered

down via external hardware control through the EXT_PWR_DWN

pin. When this pin is forced to Logic 1, all four circuit blocks are

powered down regardless of the state of the power-down bits;

that is, the independent power-down bits in CFR1 are ignored

and overridden when EXT_PWR_DWN is Logic 1.

A second frequency jump can also be allowed if the frequency

jump registers are reprogrammed before the sweeping is complete.

The following rules apply when this feature is enabled.

•

The frequency jump values must lie between the lower

limit and upper limit of the frequency sweep range.

The lower frequency jump register value must be lower

than that of the upper frequency jump register value.

•

Based on the state of the external power-down control bit, the

EXT_PWR_DWN pin produces either a full power-down or a

fast recovery power-down. The fast recovery power-down mode

maintains power to the DAC bias circuitry and the PLL, VCO,

and input clock circuitry. Although the fast recovery power-down

does not conserve as much power as the full power-down, it allows

the device to awaken very quickly from the power-down state.

FREQUENCY

UPPER LIMIT

0x09

0x0A

LOWER LIMIT

t

Figure 40. Frequency vs. Time

Rev. C | Page 27 of 48

AD9914

Data Sheet

PROGRAMMING AND FUNCTION PINS

The AD9914 is equipped with a 32-bit parallel port. The 32-bit

port is for programming the internal registers of the device in

either serial mode or parallel mode as well as allowing for direct

modulation control of frequency (FTW), phase (POW), and

amplitude (AMP). The state of the external function pins (F0

to F3) determines how the 32-bit parallel port is configured.

Pin 28 to Pin 31 are the function pins. Refer to Table 10 for

possible configurations.

Note that the OSK enable bit, CFR1[8], must be set to enable

amplitude control, as shown in Table 10.

Table 10. Parallel Port Configurations

Function Pins,

F[3:0]¹

32-Bit Parallel Port Pin Assignment

Mode Description

Bits[31:24]²

Bits[23:16]³Bits[15:8]⁴

Bits[7:0]⁵

0000

Parallel programming mode

Data[15:8]

(optional)

Data[7:0]

Address[7:0] Used to control writes, reads, and

8-bit or 16-bit data-word. See the

Parallel Programming section for

details.

0001

Serial programming mode

Not used

Used to control SCLK, SDIO,

SDO, CS, and SYNCIO. See the

Serial Programming section for

details.

0010

0011

0100

0101

Full 32 bits of direct frequency

tuning word control. MSB and LSB

aligned to parallel port pins

Full 32 bits of direct frequency

tuning word control with different

parallel port pin assignments

Full 16 bits of direct phase offset

control and full 12 bits of direct

amplitude control

Full 12 bits of direct amplitude

control and full 16 bits of direct

phase offset control

FTW[31:24]

FTW[15:8]

POW[15:8]

AMP[11:8]

FTW[23:16]

FTW[7:0]

POW[7:0]

AMP[7:0]

FTW[15:8]

FTW[31:24]

AMP[11:8]

POW[15:8]

FTW[7:0]

FTW[23:16]

AMP[7:0]

POW[7:0]

0110

0111

1000

1001

1010

1011

1100

1101