AD9937KCPRL [ADI]
CCD Signal Processor with Precision Timing⑩ Generator; CCD信号处理器具有精密Timing⑩发生器
| 型号： | AD9937KCPRL |
| 厂家： | 
ADI |
| 描述： | CCD Signal Processor with Precision Timing⑩ Generator |
| 文件： | 总44页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CCD Signal Processor with
Precision Timing™ Generator
AD9937
FEATURES
GENERAL DESCRIPTION
12 MSPS Correlated Double Sampler (CDS)
10-Bit 12 MHz A/D Converter
No Missing Codes Guaranteed
6 dB to 40 dB Variable Gain Amplifier (VGA)
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Generator
Precision Timing Core with 1.7 ns Resolution
On-Chip: 6-Channel Horizontal and 1-Channel RS Drivers
4-Phase Vertical Transfer Clocks
The AD9937 is a highly integrated CCD signal processor. It
includes a complete analog front end with A/D conversion,
combined with a full-function programmable timing generator.
A Precision Timing core allows adjustment of high speed clocks
with 1.7 ns resolution at 12 MHz operation.
The AD9937 is specified at pixel rates of up to 12 MHz. The
analog front end includes black level clamping, CDS, VGA, and
a 10-bit A/D converter. The timing generator provides all the
necessary CCD clocks: RS, H-clocks, V-clocks, sensor gate pulses,
and substrate charge reset pulse. Operation is programmed using a
3-wire serial interface.
Electronic and Mechanical Shutter Modes
On-Chip Sync Generator with External Sync Option
APPLICATIONS
Digital Still Cameras
Industrial Imaging
The AD9937 is packaged in a 56-lead LFCSP and specified over
an operating temperature range of –25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9937
6dBTO 40dB
VGA
VREF
10
ADC
CDS
DOUT
VCLK
CLAMP
INTERNAL CLOCKS
RS
HORIZONTAL
DRIVERS
PRECISION
TIMING
GENERATOR
6
4
4
H1 A–D
H2 A, B
V1 A/B
V2
V3 A/B
V4
V-H
CONTROL
SYNC
GENERATOR
INTERNAL
REGISTERS
TG1A
TG1B
TG3A
TG3B
LM
OFD
HD VD
VCKM
SLD SCK SDA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD9937
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3
ANALOG SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTION MAXIMUM RATINGS . . . . . . . . . . . . . . . 5
PACKAGE THERMAL CHARACTERISTICS . . . . . . . . . 5
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Peak Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Total Output Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
EQUIVALENT CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . 7
TYPICAL PERFORMANCE CHARACTERISTICS . . . . . 8
REGISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SERIAL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . 18
Control Register Serial Interface . . . . . . . . . . . . . . . . . . . 18
System and Mode Register Serial Interface . . . . . . . . . . . 18
Page/Burst Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Random Access Option . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Internal Power-On Reset Circuitry . . . . . . . . . . . . . . . . . . 19
VD Synchronous and Asynchronous Register Operation . 19
Asynchronous Register Operation . . . . . . . . . . . . . . . . . . 19
VD Synchronous Register Operation . . . . . . . . . . . . . . . . 19
SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ANALOG FRONT END DESCRIPTION AND
HORIZONTAL AND VERTICAL TIMING . . . . . . . . . . . 25
Individual HMASK Sequence . . . . . . . . . . . . . . . . . . . . . 25
Individual PBLK Sequences . . . . . . . . . . . . . . . . . . . . . . 25
Controlling CLPOB Clamp Pulse Timing . . . . . . . . . . . . 28
Vertical Sensor Transfer Gate Timing . . . . . . . . . . . . . . . 29
SHUTTER TIMING CONTROL . . . . . . . . . . . . . . . . . . . 29
Normal Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
High Precision Shutter Mode . . . . . . . . . . . . . . . . . . . . . . 29
Controlling LM Pulse Timing . . . . . . . . . . . . . . . . . . . . . 31
SPECIAL HORIZONTAL PATTERN TIMING . . . . . . . . 32
MASKING H1 AND H2 OUTPUTS . . . . . . . . . . . . . . . . . 33
Horizontal Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Vertical Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
VERTICAL TIMING GENERATION . . . . . . . . . . . . . . . 35
CCD REGIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
POWER-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STANDBY SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . 40
POWER-DOWN SEQUENCE . . . . . . . . . . . . . . . . . . . . . . 41
CIRCUIT LAYOUT INFORMATION . . . . . . . . . . . . . . . 42
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44
TABLES
Table I. Control Register Map . . . . . . . . . . . . . . . . . . . . . . . . 9
Table II. VTP Sequence System Register Map . . . . . . . . . . 10
Table III. H/LM System Register Map . . . . . . . . . . . . . . . . 12
Table IV. Shutter System Register Map . . . . . . . . . . . . . . . . 13
Table V. Mode_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table VI. Mode_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table VII. Serial Interface Registers . . . . . . . . . . . . . . . . . . 18
Table VIII. RS, H1, SHP, SHD, and DOUTPHASE
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table IX. Precision Timing Edge Locations for RS, H1,
SHP, SHD, and DOUTPHASE . . . . . . . . . . . . . . . . . . . . . 23
Table X. HD and VD Registers . . . . . . . . . . . . . . . . . . . . . . 25
Table XI. PBLK Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table XII. CLPOB Registers . . . . . . . . . . . . . . . . . . . . . . . . 28
Table XIII. TG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table XIV. OFD Registers . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table XV. LM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table XVI. Special H Pattern Registers . . . . . . . . . . . . . . . . 33
Table XVII. Sequence Change Positions Registers . . . . . . . 35
Table XVIII. Start-Up Polarities . . . . . . . . . . . . . . . . . . . . . 39
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Correlated Double Sampler . . . . . . . . . . . . . . . . . . . . . . . 21
PRECISION TIMING HIGH SPEED TIMING
GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Timing Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
High Speed Clock Programmability . . . . . . . . . . . . . . . . . 22
H-Driver and RS Outputs . . . . . . . . . . . . . . . . . . . . . . . . 22
MASTER AND SLAVE MODE OPERATION . . . . . . . . . 25
–2–
REV. 0
AD9937–SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
–25
–65
+85
+150
°C
°C
POWER SUPPLY VOLTAGE
AVDD (AFE Analog Supply)
TCVDD (Timing Core Analog Supply)
RSVDD (RS Driver)
HVDD1 (H1A, H2A, and H1C Drivers)
HVDD2 (H1B, H2B, and H1D Drivers)
DRVDD (Data Output Drivers)
DVDD (Digital)
2.7
2.7
2.7
2.7
2.7
2.7
2.7
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
V
V
V
V
V
V
POWER CONSUMPTION @ 10 MHz
Power from (AVDD + TCVDD + DRVDD + DVDD)
Power from (HVDD1 + HVDD2)1
100
25
3
mW
mW
mW
mW
Power from (RSVDD)2
Standby Mode (AFE_STBY and DIG_STBY = 0)
1.5
VCKM MAX CLOCK RATE
12
MHz
NOTES
H1A
H2A
H1B
H2B
H1C
H1D
30ꢁ
30ꢁ
30ꢁ
30ꢁ
30ꢁ
30ꢁ
10pF
30pF
10pF
50pF
10pF
30pF
10pF
50pF
10pF 10pF
30pF
10pF
30pF
RS
30ꢁ
10pF
10pF
2RS Load
1H1 (A–D) and H2 (A, B) Loads
(RSVDD = HVDD = 2.7 V to 3.6 V, –25ꢀC to +85ꢀC, unless otherwise noted.)
DIGITAL SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS (VCKM, SLD, SDA, and SCK)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
VIH
VIL
IIH
IIL
CIN
2.1
V
V
µA
µA
pF
0.6
40
40
Input Capacitance
10
LOGIC OUTPUTS (Except H1(A–D), H2(A, B), and RS)
High Level Output Voltage @ IOH = 2 mA
Low Level Output Voltage @ IOL = 2 mA
VOH
VOL
DRVDD – 0.5
DVDD – 0.5
V
V
0.5
0.5
H-DRIVER OUTPUTS (H1(A–D), H2(A, B))
High Level Output Voltage @ Max Current
Low Level Output Voltage @ Max Current
H1(A–D) Maximum Output Current (Programmable)
H2(A, B) Maximum Output Current (Programmable)
Maximum Load Current
VOH
VOL
V
V
mA
mA
pF
12.25
12.25
100
RS-DRIVER OUTPUTS
High Level Output Voltage @ Max Current
Low Level Output Voltage @ Max Current
RS Maximum Output Current (Programmable)
Maximum Load Current
VOH
VOL
RSVDD – 0.5
V
V
mA
pF
0.5
12.25
100
Specifications subject to change without notice.
REV. 0
–3–
AD9937
ANALOG SPECIFICATIONS (AVDD = 3 V, fCLI = 12 MHz, –25ꢀC to +85ꢀC, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Notes
CDS
Allowable CCD Reset Transient
Max Input Range before Saturation
Max CCD Black Pixel Amplitude
500
mV
V p-p
mV
Input signal characteristics.*
1.0
100
VARIABLE GAIN AMPLIFIER (VGA)
Max Output Range
Gain Control Resolution
Gain Monotonicity
2.0
V p-p
Bits
10
Guaranteed
Gain Range
Low Gain (VGA Code 0)
Max Gain (VGA Code 1023)
5.3
41.1
dB
dB
40
10
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
255
Steps
LSB measured at ADC output.
Min Clamp Level
Max Clamp Level
0
LSB
LSB
63.75
A/D CONVERTER
Resolution
Bits
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
0.4
Guaranteed
2.0
1.0
LSB
V
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
2.0
1.0
V
V
SYSTEM PERFORMANCE
Gain Accuracy
Includes entire signal chain.
Low Gain (VGA Code 17)
Max Gain (VGA Code 1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
5
40.2
6
7
42.2
dB
dB
%
LSB rms
dB
Gain = (0.035 × Code) + 5.4 dB
41.2
0.1
0.3
40
12 dB gain applied.
AC ground input, 6 dB gain applied.
Measured with step change on supply.
Power Supply Rejection (PSR)
*Input signal characteristics defined as follows:
500mV TYP
RESET
TRANSIENT
1V MAX
INPUT
SIGNAL RANGE
100mV MAX
OPTICAL
BLACK PIXEL
Specifications subject to change without notice.
–4–
REV. 0
AD9937
TIMING SPECIFICATIONS (CL = 20 pF, AVDD = DVDD = DRVDD = 3 V, fCLI = 12 MHz, unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
MASTER CLOCK, VCKM
VCKM Clock Period
VCKM High/Low Pulsewidth
Delay from VCKM Rising Edge to Internal Pixel Position 0
tCONV
83.33
ns
ns
ns
41.67
9
tVCKMDLY
AFE CLAMP PULSES1
CLPOB Pulsewidth2
AFE SAMPLE LOCATION1 (See Figure 13)
SHP Sample Edge to SHD Sample Edge
2
20
Pixels
ns
tS1
33.34
41.67
DATA OUTPUTS
Output Delay from VCLK Rising Edge
Pipeline Delay from SHP/SHD Sampling (See Figure 40)
tOD
9
9
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SLD to SCK Setup Time
SCK to SLD Hold Time
SDA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDA Valid Hold
SCK Falling Edge to SDA Valid Read
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
NOTES
1Parameter is programmable.
2Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
With
Respect
JA = 24.9°C/W
Parameter
To
Min Max
Unit
AVDD
TCVDD
HVDD
RSVDD
DVDD
DRVDD
RS Output
AVSS
–0.3 +3.9
V
V
V
V
V
V
TCVSS –0.3 +3.9
HVSS –0.3 +3.9
RSVSS –0.3 +3.9
DVSS –0.3 +3.9
DRVSS –0.3 +3.9
ORDERING GUIDE
Temperature
Range
Package
Description Option
Package
Model
AD9937KCP
–25°C to +85°C Lead Frame CP-56
RSVSS –0.3 RSVDD + 0.3 V
Chip Scale
Package
H1(A–D), H2(A, B)Output HVSS
–0.3 HVDD + 0.3
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
150
V
V
V
V
V
V
°C
°C
Digital Outputs
Digital Inputs
SCK, SLD, SDA
VRT, VRB
DVSS
DVSS
DVSS
AVSS
AVSS
(LFCSP)
AD9937KCPRL –25°C to +85°C Lead Frame CP-56
Chip Scale
Package
(LFCSP)
CCDIN
Junction Temperature
Lead Temperature, 10 sec
350
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9937 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–5–
AD9937
PIN CONFIGURATION
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1
2
NC
NC
42
41
40
39
38
TG1B
V1A/B
TG1A
REFB
REFT
PIN 1
IDENTIFIER
3
D0
4
D1
5
D2
6
D3
37 AVSS
AD9937
7
DRVSS
DRVDD
D4
36
CCDIN
8
35
34
33
32
31
30
AVDD
VCKM
TCVDD
TCVSS
NC
TOP VIEW
(Not to Scale)
9
10
11
12
13
14
D5
D6
D7
D8
NC
D9
29 NC
15 16 17 18 19 20 21 22 23 24 25 26 27 28
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS1
Pin
Pin
No. Mnemonic Type2 Description
No. Mnemonic Type2 Description
1
2
3
4
5
6
7
8
NC
NC
D0
D1
D2
D3
DRVSS
DRVDD
D4
D5
D6
D7
D8
D9
VCLK
HVDD2
NC
NC
DO
DO
DO
DO
P
No Connect
No Connect
Data Output
Data Output
Data Output
Data Output
Data Output Driver Ground
Data Output Driver Supply
Data Output
Data Output
Data Output
Data Output
Data Output
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
NC
NC
P
No Connect
TCVSS
TCVDD
VCKM
AVDD
CCDIN
AVSS
REFT
REFB
TG1A
V1A/B
TG1B
V2
Analog Ground for Timing Core
Analog Supply for Timing Core
Reference Clock Input
Analog Supply for AFE
CCD Input Signal
P
DI3
P
AI
P
Analog Ground for AFE
Voltage Reference Top Bypass
Voltage Reference Bottom Bypass
CCD Sensor Gate Pulse 1
CCD Vertical Transfer Clock 1
CCD Sensor Gate Pulse 2
CCD Vertical Transfer Clock 2
CCD Sensor Gate Pulse 3
CCD Vertical Transfer Clock 3
CCD Sensor Gate Pulse 4
CCD Vertical Transfer Clock 4
Line Memory Control Pulse
Digital Supply
Digital Ground
CCD Substrate Reset Pulse
Horizontal Sync Pulse
Vertical Sync Pulse
3-Wire Serial Load Pulse
3-Wire Serial Data
P
AO
AO
DO
DO
DO
DO
DO
DO
DO
DO
DO
P
9
DO
DO
DO
DO
DO
DO
DO
P
10
11
12
13
14
15
16
Data Output
TG3A
V3A/B
TG3B
V4
Data Output Clock
Horizontal Driver Supply 2
for H1D, H2B, and H1B
Horizontal Driver Ground 2
CCD Horizontal Clock 4
CCD Horizontal Clock 6
CCD Horizontal Clock 2
Horizontal Driver Supply 1
for H1C, H2A, and H1A
Horizontal Driver Ground 1
CCD Horizontal Clock 3
CCD Horizontal Clock 5
CCD Horizontal Clock 1
RS Driver Ground
CCD Reset Gate Clock
RS Driver Supply
17
18
19
20
21
HVSS2
H1D
H2B
H1B
HVDD1
P
LM
DO
DO
DO
P
DVDD
DVSS
OFD
HD
VD
SLD
SDA
SCK
P
DO
DO
DO
DI3
DI3
DI3
22
23
24
25
26
27
28
29
30
HVSS1
H1C
H2A
H1A
RSVSS
RS
RSVDD
NC
NC
P
DO
DO
DO
P
DO
P
3-Wire Serial Clock
NOTES
1See Figure 41 for circuit configuration.
2AI = Analog Input, AO = Analog Output, DI = Digital Input,
DO = Digital Output, DIO = Digital Input/Output, P = Power,
NC = No Connection.
NC
NC
No Connect
No Connect
3Schmitt trigger type input.
–6–
REV. 0
AD9937
TERMINOLOGY
Total Output Noise
Differential Nonlinearity (DNL)
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
10-bit resolution indicates that all 1024 codes must be present
over all operating conditions.
1LSB = ADC Full Scale 2N codes
(
)
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9937 from a true straight
line. The point used as zero scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2 LSB
beyond the last code transition. The deviation is measured from
the middle of each particular output code to the true straight line.
The error is then expressed as a percentage of the 2 V ADC full-
scale signal. The input signal is always appropriately gained up
to fill the ADC’s full-scale range.
where N is the bit resolution of the ADC. For the AD9937, 1 LSB
is 1.95 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9937’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
EQUIVALENT CIRCUITS
DVDD
AVDD
330ꢁ
R
AVSS
AVSS
DVSS
Figure 1. CCDIN
Figure 3. Digital Inputs
HVDD1, HVDD2,
OR RSVDD
DRVDD
DVDD
RS,
H1 (A–D),
H2 (A, B)
DATA
ENABLE
OUTPUT
DOUT
TRISTATEOUT
HVSS1, HVSS2,
OR RSVSS
DVSS
DRVSS
Figure 2. Digital Data Outputs
Figure 4. H1(A–D), H2(A, B), and RS Drivers
REV. 0
–7–
AD9937–Typical Performance Characteristics
0.50
0.25
160
150
V
= 3.3V
DD
140
130
120
110
100
V = 3.0V
DD
V
= 3.0V
= 2.7V
0
–0.25
–0.50
DD
V
DD
0
200
400
600
800
1000
8
10
12
CODE
SAMPLE RATE – MHz
TPC 2. Typical DNL Performance
TPC 1. Power vs. Sample Rate
–8–
REV. 0
AD9937
Table I. Control Register Map
Register
Bit
Bit
Addr Breakdown Width Default
Name
Function
0
1
(23:0)
0
24
1
0
0
SW_RESET
Software Reset = 000000 (Reset All Registers to Default).
OUTCONT_REG Internal OUTCONT Signal Control (0 = Digital Outputs held
at fixed dc level, 1 = Normal Operation).
Unused
(23:1)
(1:0)
23
2
2
3
0
0
AFE_STBY
AFE Standby (0 = Full Standby, 1 = Normal Operation,
2/3 = Reference Standby).
2
1
21
DIG_STBY
Unused
Digital Standby (0 = Full Standby, 1 = Normal Operation).
(23:3)
(7:0)
8
9
10
11
12
13
14
(16:15)
17
8
1
1
1
1
1
1
1
2
1
1
5
0x80
REFBLACK
BC_EN
TESTMODE
TESTMODE
PBLK_LEVEL
TRISTATEOUT
Black Clamp Level.
1 = Black Clamp Enable.
This register should always be set to 0.
This register should always be set to 0.
0 = Blank to 0, 1 = Blank to Clamp Level (REFBLACK).
0 = Data Outputs are Driven, 1 = Data Outputs are Three-Stated.
1
0
0
0
0
0
0
0
0
1
RETIMEOUT_BAR 0 = Retime Data Outputs, 1 = Do Not Retime Data Outputs.
GRAY_ENCODE
TESTMODE
TESTMODE
TESTMODE
Unused
1 = Gray Encode ADC Outputs.
This register should always be set to 0.
This register should always be set to 0.
This register should always be set to 1.
18
(23:19)
4
0
1
2
3
1
1
1
1
0
0
0
0
VCKM_DIVIDE
H1BLKRETIME
LM_INVERT
VCKM Input Clock Divider (0 = VCKM, 1 = VCKM/2).
Retimes the H1 HBLK to Internal Clock.
LM Inversion Control (1 = Invert Programmed LM).
TGOFD_INVERT TG and OFD Inversion Control (1 = Invert Programmed TG
and ODF).
4
1
0
0
VDHD_INVERT
VD and HD Inversion Control (1 = Invert Programmed VD
and HD; Note that Internal VD/HD Are HI Active).
Operating Mode (0 = Slave Mode, 1 = Master Mode).
5
1
18
MASTER
Unused
(23:6)
5
(5:0)
6
6
6
2
0x00
0x24
0x00
0x00
SHDLOC
SHPLOC
DOUTPHASE
DOUT_DELAY
SHD Sample Location.
SHP Sample Location.
Data Output [9:0] and VCLK Phase Adjustment.
Data Output Clock Selection (0 = No Delay, 1 = ~4 ns, 2 = ~8 ns,
3 = ~12 ns).
(11:6)
(17:12)
(19:18)
20
21
22
23
1
1
1
1
0
1
0
–
VCLKMASK
VCLK_INVERT
DTEST
VCLK Masking Control (1 = Mask).
1 = Invert VCLK.
1 = Internal Digital Signal Test Mode.
Unused
6
7
(5:0)
6
6
6
6
0x00
0x20
0x00
0x10
H1POSLOC
H1NEGLOC
RSPOSLOC
RSNEGLOC
H1 Positive Edge Location.
H1 Negative Edge Location.
RS Positive Edge Location.
RS Negative Edge Location.
(11:6)
(17:12)
(23:18)
(2:0)
3
4
H1DRV
H1A/B/C/D Drive Strength (0 = OFF, 1 = 1.75 mA, 2 = 3.5 mA,
3 = 5.25 mA, 4 = 7 mA, 5 = 8.75 mA, 6 = 10.5 mA, 7 = 12.25 mA).
H2A/B Drive Strength (see H1DRV).
(5:3)
(8:6)
(23:9)
(23:1)
3
3
15
23
4
4
H2DRV
RSDRV
Unused
Unused
RS Drive Strength (see H1DRV).
REV. 0
–9–
AD9937
Table I. Control Register Map (continued)
Register
Bit
Bit
Addr Breakdown Width Default
Name
Function
8
0
1
23
0
MODE
Unused
Mode Control Bit. (0 = Mode A, 1 = Mode B)
(23:1)
9
0
1
4
19
1
0x9
SPEN
SPLOGIC
Unused
Single Pulse (SP) Output Enable.
Single Pulse Logic Setting (0 = OR, 1 = AND).
(4:1)
(23:5)
10
0
1
11
1
1
OFDEN
OFDNUM
TGEN
OFD Output Enable Control (0 = Disable, 1 = Enable).
Total Number of OFD Pulses per Field.
TG Output Enable Control (0 = Disable, 1 = Enable).
(11:1)
12
0x7FF
1
(23:13)
11
Unused
11
12
(11:0)
(23:12)
12
12
4095
4095
OFDHPTOG1
OFDHPTOG2
High Precision OFD Toggle Position 1.
High Precision OFD Toggle Position 2.
(9:0)
(23:10)
10
14
0x000
VGAGAIN
Unused
VGA Gain Control.
Denotes VD synchronous registers (control addresses 8, 9, 10, 11, and 12).
Table II. VTP Sequence System Register Map (Addr 0x14)
Bit
Bit
Register
Name
Addr
Breakdown Width
Default
Function
VTP_Reg(0)
(11:0)
(23:12)
(31:24)
12
12
8
ENDADDRESS
STARTADDRESS
VTP_Reg_Addr
Sub Word End Address
Sub Word Start Address
System Register Address 0x14
VTP_Reg(1)
(8:0)
(17:9)
(26:18)
27
28
29
9
9
9
1
1
1
1
1
279
75
250
1
0
0
VTPLEN_0
V1TOG1_0
V1TOG2_0
V1POL_0
V2POL_0
V3POL_0
V4POL_0
Unused
VTP0: Length between Repetitions
VTP0: V1 Toggle Position 1
VTP0: V1 Toggle Position 2
VTP0: V1 Start Polarity
VTP0: V2 Start Polarity
VTP0: V3 Start Polarity
30
31
1
VTP0: V4 Start Polarity
VTP_Reg(2)
VTP_Reg(3)
VTP_Reg(4)
(8:0)
9
9
9
5
40
145
110
V2TOG1_0
V2TOG2_0
V3TOG1_0
Unused
VTP0: V2 Toggle Position 1
VTP0: V2 Toggle Position 2
VTP0: V3 Toggle Position 1
(17:9)
(26:18)
(31:27)
(8:0)
9
9
9
5
215
5
180
V3TOG2_0
V4TOG1_0
V4TOG2_0
Unused
VTP0: V3 Toggle Position 2
VTP0: V4 Toggle Position 1
VTP0: V4 Toggle Position 2
(17:9)
(26:18)
(31:27)
(8:0)
(17:9)
(26:18)
27
28
29
9
9
9
1
1
1
1
1
99
29
99
1
0
0
VTPLEN_1
V1TOG1_1
V1TOG2_1
V1POL_1
V2POL_1
V3POL_1
V4POL_1
Unused
VTP1: Length between Repetitions
VTP1: V1 Toggle Position 1
VTP1: V1 Toggle Position 2
VTP1: V1 Start Polarity
VTP1: V2 Start Polarity
VTP1: V3 Start Polarity
30
31
1
VTP1: V4 Start Polarity
VTP_Reg(5)
(8:0)
9
9
9
5
15
57
43
V2TOG1_1
V2TOG2_1
V3TOG1_1
Unused
VTP1: V2 Toggle Position 1
VTP1: V2 Toggle Position 2
VTP1: V3 Toggle Position 1
(17:9)
(26:18)
(31:27)
–10–
REV. 0
AD9937
Table II. VTP Sequence System Register Map (Addr 0x14) (continued)
Bit
Bit
Register
Name
Addr
Breakdown Width
Default
Function
VTP_Reg(6)
(8:0)
9
9
9
5
85
1
71
V3TOG2_1
V4TOG1_1
V4TOG2_1
Unused
VTP1: V3 Toggle Position 2
VTP1: V4 Toggle Position 1
VTP1: V4 Toggle Position 2
(17:9)
(26:18)
(31:27)
VTP_Reg(7)
(8:0)
(17:9)
(26:18)
27
28
29
9
9
9
1
1
1
1
1
99
29
99
1
0
0
VTPLEN_2
V1TOG1_2
V1TOG2_2
V1POL_2
V2POL_2
V3POL_2
V4POL_2
Unused
VTP2: Length between Repetitions
VTP2: V1 Toggle Position 1
VTP2: V1 Toggle Position 2
VTP2: V1 Start Polarity
VTP2: V2 Start Polarity
VTP2: V3 Start Polarity
30
31
1
VTP2: V4 Start Polarity
VTP_Reg(8)
VTP_Reg(9)
(8:0)
9
9
9
5
15
57
43
V2TOG1_2
V2TOG2_2
V3TOG1_2
Unused
VTP2: V2 Toggle Position 1
VTP2: V2 Toggle Position 2
VTP2: V3 Toggle Position 1
(17:9)
(26:18)
(31:27)
(8:0)
9
9
9
5
85
1
71
V3TOG2_2
V4TOG1_2
V4TOG2_2
Unused
VTP2: V3 Toggle Position 2
VTP2: V4 Toggle Position 1
VTP2: V4 Toggle Position 2
(17:9)
(26:18)
(31:27)
VTP_Reg(10) (11:0)
(23:12)
12
12
8
40
410
SP1TOG1
SP1TOG2
Unused
SP1 Toggle Position 1 (V1A/V1B)
SP1 Toggle Position 2 (V1A/V1B)
(31:24)
VTP_Reg(11) (11:0)
(23:12)
12
12
8
490
780
SP2TOG1
SP2TOG2
Unused
SP2 Toggle Position 1 (V2)
SP2 Toggle Position 2 (V2)
(31:24)
VTP_Reg(12) (11:0)
(23:12)
12
12
8
80
360
SP3TOG1
SP3TOG2
Unused
SP3 Toggle Position 1 (V3A/V3B)
SP3 Toggle Position 2 (V3A/V3B)
(31:24)
VTP_Reg(13) (11:0)
(23:12)
12
12
8
450
820
SP4TOG1
SP4TOG2
Unused
SP4 Toggle Position 1 (V4)
SP4 Toggle Position 2 (V4)
(31:24)
REV. 0
–11–
AD9937
Table III. H/LM System Register Map (Addr 0x15)
Register
Bit
Bit
Addr
Breakdown Width
Default
Name
Function
HLM_Reg(0) (11:0)
(23:12)
12
12
8
ENDADDRESS
STARTADDRESS Sub Word Start Address
HLM_Reg_Addr
Sub Word End Address
(31:24)
System Register Address 0x15
HLM_Reg(1)
0
1
2
3
4
5
1
1
1
1
1
1
26
0
0
1
1
0
0
H1APOL
H1BPOL
H1CPOL
H1DPOL
H2APOL
H2BPOL
Unused
H1A Special H-Pattern Start Polarity
H1B Special H-Pattern Start Polarity
H1C Special H-Pattern Start Polarity
H1D Special H-Pattern Start Polarity
H2A Special H-Pattern Start Polarity
H2B Special H-Pattern Start Polarity
(31:6)
HLM_Reg(2) (5:0)
(11:6)
6
6
6
14
0x00
0x04
0x01
SPH1A1
SPH1B1
SPH1C1
Unused
H1A Special H-Pattern during LM Repetition 1
H1B Special H-Pattern during LM Repetition 1
H1C Special H-Pattern during LM Repetition 1
(17:12)
(31:18)
HLM_Reg(3) (5:0)
(11:6)
6
6
6
14
0x07
0x08
0x22
SPH1D1
SPH2A1
SPH2B1
Unused
H1D Special H-Pattern during LM Repetition 1
H2A Special H-Pattern during LM Repetition 1
H2B Special H-Pattern during LM Repetition 1
(17:12)
(31:18)
HLM_Reg(4) (5:0)
(11:6)
6
6
6
14
0x34
0x34
0x04
SPH1A2
SPH1B2
SPH1C2
Unused
H1A Special H-Pattern during LM Repetition 2
H1B Special H-Pattern during LM Repetition 2
H1C Special H-Pattern during LM Repetition 2
(17:12)
(31:18)
HLM_Reg(5) (5:0)
(11:6)
6
6
6
14
0x04
0x3A
0x0B
SPH1D2
SPH2A2
SPH2B2
Unused
H1D Special H-Pattern during LM Repetition 2
H2A Special H-Pattern during LM Repetition 2
H2B Special H-Pattern during LM Repetition 2
(17:12)
(31:18)
HLM_Reg(6) (5:0)
(11:6)
6
6
6
14
0x3D
0x3F
0x3C
SPH1A3
SPH1B3
SPH1C3
Unused
H1A Special H-Pattern during LM Repetition 3
H1B Special H-Pattern during LM Repetition 3
H1C Special H-Pattern during LM Repetition 3
(17:12)
(31:18)
HLM_Reg(7) (5:0)
(11:6)
6
6
6
14
0x3C
0x03
0x02
SPH1D3
SPH2A2
SPH2B3
Unused
H1D Special H-Pattern during LM Repetition 3
H2A Special H-Pattern during LM Repetition 3
H2B Special H-Pattern during LM Repetition 3
(17:12)
(31:18)
HLM_Reg(8) (7:0)
(15:8)
8
8
8
8
99
5
55
87
LMLEN0
LM Pattern 0 (LM0): LM Counter Length
LM Pattern 0 (LM0): Toggle Position 1
LM Pattern 0 (LM0): Toggle Position 2
LM Pattern 0 (LM0): Special H Pulse Start Position
LMTOG1_0
LMTOG2_0
SPHSTART0
(23:16)
(31:24)
HLM_Reg(9) (7:0)
(15:8)
8
8
8
8
29
2
26
0
LMLEN1
LM Pattern 1 (LM1): LM Counter Length
LM Pattern 1 (LM1): Toggle Position 1
LM Pattern 1 (LM1): Toggle Position 2
LM Pattern 1 (LM1): Special H Pulse Start Position
LMTOG1_1
LMTOG2_1
SPHSTART1
(23:16)
(31:24)
–12–
REV. 0
AD9937
Table IV. Shutter System Register Map (Addr 0x16)
Register
Bit
Bit
Addr
Breakdown Width
Default
Name
Function
Shut_Reg(0)
(11:0)
(23:12)
(31:24)
12
12
8
ENDADDRESS
STARTADDRESS Sub Word Start Address
SHUT_Reg_Addr System Register Address 0x16
Sub Word End Address
Shut_Reg(1)
Shut_Reg(2)
Shut_Reg(3)
Shut_Reg(4)
(11:0)
(23:12)
(31:24)
12
12
8
80
370
TGTOG1_0
TGTOG2_0
Unused
TG0 Pulse Toggle Position 1
TG0 Pulse Toggle Position 2
(11:0)
(23:12)
(31:24)
12
12
8
490
780
TGTOG1_1
TGTOG2_1
Unused
TG1 Pulse Toggle Position 1
TG1 Pulse Toggle Position 2
(11:0)
(23:12)
(31:24)
12
12
8
540
720
OFDTOG1_0
OFDTOG2_0
Unused
OFD0 Pulse Toggle Position 1
OFD0 Pulse Toggle Position 2
(11:0)
(23:12)
(31:24)
12
12
8
830
860
OFDTOG1_1
OFDTOG2_1
Unused
OFD1 Pulse Toggle Position 1
OFD1 Pulse Toggle Position 2
REV. 0
–13–
AD9937
Table V. Mode_A (Addr 0x17)
Register
Bit
Bit
Addr
Breakdown Width
Default Name
Function
Mode_Reg(0) (11:0)
(23:12)
12
12
8
ENDADDRESS
STARTADDRESS
MODE_Reg_Addr
Sub Word End Address
Sub Word Start Address
Mode Register Address (Mode A = Addr 0x17)
(31:24)
Mode_Reg(1) (6:0)
7
1
1
4
1
18
0
0
1
0xA
0
TGACTLINE
TGPATSEL0
TGPATSEL1
TGMASK
OFDPATSEL
Unused
TG Active Line
7
8
TG1A/B Pattern Selector (0 = TG0, 1 = TG1)
TG3A/B Pattern Selector (0 = TG0, 1 = TG1)
TG Masking Control (1 = Mask)
(12:9)
13
(31:14)
OFD Pattern Selection (0 = OFD0, 1 = OFD1)
Mode_Reg(2) (11:0)
(23:12)
12
12
8
831
866
HDTOG1
HDTOG2
Unused
HD Toggle Position 1
HD Toggle Position 2
(31:24)
Mode_Reg(3) (11:0)
(23:12)
12
12
8
4095
4095
HDTOG3
HDTOG4
Unused
HD Toggle Position 3
HD Toggle Position 4
(31:24)
Mode_Reg(4) (11:0)
12
11
4
4
1
2339
262
0
HDLASTLEN
VDLEN
VDTOG1
VDTOG2
Unused
HD Last Line Length
VD Field Length
VD Toggle Position 1
VD Toggle Position 2
(22:12)
(26:23)
(30:27)
31
4
Mode_Reg(5) (11:0)
(23:12)
12
12
8
1543
1557
CLPOBTOG1
CLPOBTOG2
Unused
CLPOB Toggle Position 1
CLPOB Toggle Position 2
(31:24)
Mode_Reg(6) (11:0)
(23:12)
12
12
8
4095
4095
CLPOBTOG3
CLPOBTOG4
Unused
CLPOB Toggle Position 3
CLPOB Toggle Position 4
(31:24)
Mode_Reg(7) (11:0)
12
12
1
0
869
0
HBLKTOG1
HBLKTOG2
H1TOG12POL
Unused
HBLK Toggle Position 1
HBLK Toggle Position 2
H1 Polarity between Toggle Positions 1 and 2
(23:12)
24
(31:25)
7
Mode_Reg(8) (11:0)
12
12
1
4095
4095
0
HBLKTOG3
HBLKTOG4
H1TOG34POL
Unused
HBLK Toggle Position 3
HBLK Toggle Position 4
H1 Polarity between Toggle Positions 3 and 4
(23:12)
24
(31:25)
7
Mode_Reg(9) (11:0)
(23:12)
12
12
8
6
878
PBLKTOG1
PBLKTOG2
Unused
PBLK Toggle Position 1
PBLK Toggle Position 2
(31:24)
Mode_Reg(10) (11:0)
(23:12)
12
12
8
4095
4095
PBLKTOG3
PBLKTOG4
Unused
PBLK Toggle Position 3
PBLK Toggle Position 4
(31:24)
Mode_Reg(11) (10:0)
(21:11)
11
11
10
255
3
PBLKSTART
PBLKSTOP
Unused
PBLK Start Position
PBLK Stop Position
(31:22)
Mode_Reg(12) (10:0)
11
11
1
0
1
0
HMASKSTART
HMASKSTOP
H1MASKPOL
Unused
Vertical H Masking Start Position
Vertical H Masking Stop Position
Masking Polarity for H1 during Vertical Blanking Period
(21:11)
22
(31:23)
9
Mode_Reg(13) (11:0)
(23:12)
12
12
8
550
4095
LMSTART0
LMSTART1
Unused
LM Counter Start Position 1
LM Counter Start Position 2
(31:24)
–14–
REV. 0
AD9937
Table V. Mode_A (Addr 0x17) (continued)
Register
Bit
Bit
Addr
Breakdown Width
Default
Name
Function
Mode_Reg(14) (7:0)
(15:8)
8
8
8
8
1
0
0
0
SCP1
SCP2
SCP3
SCP4
Sequence Change Position 1
Sequence Change Position 2
Sequence Change Position 3
Sequence Change Position 4
(23:16)
(31:24)
Mode_Reg(15) (11:0)
12
2
3
1
2
1
1
10
1559
HDLEN0
HD Counter Length Value for Region 0
VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2)
VTP Pulse Repetition Number in Region 0
LM Pattern Select for Region 0 (0 = LM0, 1 = LM1)
LM Repetition Number in Region 0
Special H-Pattern Enable in Region 0
CLPOB Enable in Region 0
(13:12)
(16:14)
17
(19:18)
20
0
0
0
0
0
1
VTPPATSEL0
VTPREP0
LMPATSEL0
LMREP0
SPHEN0
CLPOBEN0
Unused
21
(31:22)
Mode_Reg(16) (11:0)
12
2
3
1
2
1
1
10
1559
HDLEN1
HD Counter Length Value for Region 1
VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2)
VTP Pulse Repetition Number in Region 1
LM Pattern Select for Region 1 (0 = LM0, 1 = LM1)
LM Repetition Number in Region 1
Special H-Pattern Enable in Region 1
CLPOB Enable in Region 1
(13:12)
(16:14)
17
(19:18)
20
0
2
0
3
1
1
VTPPATSEL1
VTPREP1
LMPATSEL1
LMREP1
SPHEN1
CLPOBEN1
Unused
21
(31:22)
Mode_Reg(17) (11:0)
12
2
3
1
2
1
1
10
1559
HDLEN2
HD Counter Length Value for Region 2
VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2)
VTP Pulse Repetition Number in Region 2
LM Pattern Select for Region 2 (0 = LM0, 1 = LM1)
LM Repetition Number in Region 2
(13:12)
(16:14)
17
(19:18)
20
21
(31:22)
0
2
0
3
1
1
VTPPATSEL2
VTPREP2
LMPATSEL2
LMREP2
SPHEN2
CLPOBEN2
Unused
Special H-Pattern Enable in Region 2
CLPOB Enable in Region 2
Mode_Reg(18) (11:0)
12
2
3
1
2
1
1
10
1559
HDLEN3
HD Counter Length Value for Region 3
VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2)
VTP Pulse Repetition Number in Region 3
LM Pattern Select for Region 3 (0 = LM0, 1 = LM1)
LM Repetition Number in Region 3
(13:12)
(16:14)
17
(19:18)
20
0
2
0
3
1
1
VTPPATSEL3
VTPREP3
LMPATSEL3
LMREP3
SPHEN3
CLPOBEN3
Unused
Special H-Pattern Enable in Region 3
CLPOB Enable in Region 3
21
(31:22)
Mode_Reg(19) (11:0)
12
2
3
1
2
1
1
10
1559
HDLEN4
HD Counter Length Value for Region 4
VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2)
VTP Pulse Repetition Number in Region 4
LM Pattern Select for Region 4 (0 = LM0, 1 = LM1)
LM Repetition Number in Region 4
(13:12)
(16:14)
17
(19:18)
20
0
2
0
3
1
1
VTPPATSEL4
VTPREP4
LMPATSEL4
LMREP4
SPHEN4
CLPOBEN4
Unused
Special H-Pattern Enable in Region 4
CLPOB Enable in Region 4
21
(31:22)
REV. 0
–15–
AD9937
Table VI. Mode_B (Addr 0x18)
Register
Bit
Bit
Addr
Breakdown Width
Default Name
Function
Mode_Reg(0) (11:0)
(23:12)
12
12
8
ENDADDRESS
STARTADDRESS Sub Word Start Address
MODE_Reg_Addr Mode Register Address (Mode B = Addr 0x18)
Sub Word End Address
(31:24)
Mode_Reg(1) (6:0)
7
1
1
4
1
18
0
0
1
0x0
1
TGACTLINE
TGPATSEL0
TGPATSEL1
TGMASK
OFDPATSEL
Unused
TG Active Line
7
8
TG1A/B Pattern Selector (0 = TG0, 1 = TG1)
TG3A/B Pattern Selector (0 = TG0, 1 = TG1)
TG Masking Control (1 = Mask)
(12:9)
13
(31:14)
OFD Pattern Selection (0 = OFD0, 1 = OFD1)
Mode_Reg(2) (11:0)
(23:12)
12
12
8
95
130
HDTOG1
HDTOG2
Unused
HD Toggle Position 1
HD Toggle Position 2
(31:24)
Mode_Reg(3) (11:0)
(23:12)
12
12
8
830
865
HDTOG3
HDTOG4
Unused
HD Toggle Position 3
HD Toggle Position 4
(31:24)
Mode_Reg(4) (11:0)
12
11
4
4
1
1559
525
0
HDLASTLEN
VDLEN
VDTOG1
VDTOG2
Unused
HD Last Line Length
VD Field Length
VD Toggle Position 1
VD Toggle Position 2
(22:12)
(26:23)
(30:27)
31
4
Mode_Reg(5) (11:0)
(23:12)
12
12
8
808
822
CLPOBTOG1
CLPOBTOG2
Unused
CLPOB Toggle Position 1
CLPOB Toggle Position 2
(31:24)
Mode_Reg(6) (11:0)
(23:12)
12
12
8
1543
1557
CLPOBTOG3
CLPOBTOG4
Unused
CLPOB Toggle Position 3
CLPOB Toggle Position 4
(31:24)
Mode_Reg(7) (11:0)
12
12
1
1
133
1
HBLKTOG1
HBLKTOG2
H1TOG12POL
Unused
HBLK Toggle Position 1
HBLK Toggle Position 2
H1 Polarity between Toggle Positions 1 and 2
(23:12)
24
(31:25)
7
Mode_Reg(8) (11:0)
12
12
1
825
868
0
HBLKTOG3
HBLKTOG4
H1TOG34POL
Unused
HBLK Toggle Position 3
HBLK Toggle Position 4
H1 Polarity between Toggle Positions 3 and 4
(23:12)
24
(31:25)
7
Mode_Reg(9) (11:0)
(23:12)
12
12
8
6
143
PBLKTOG1
PBLKTOG2
Unused
PBLK Toggle Position 1
PBLK Toggle Position 2
(31:24)
Mode_Reg(10) (11:0)
(23:12)
12
12
8
831
878
PBLKTOG3
PBLKTOG4
Unused
PBLK Toggle Position 3
PBLK Toggle Position 4
(31:24)
Mode_Reg(11) (10:0)
(21:11)
11
11
10
510
6
PBLKSTART
PBLKSTOP
Unused
PBLK Start Position
PBLK Stop Position
(31:22)
Mode_Reg(12) (10:0)
11
11
1
0
1
0
HMASKSTART
HMASKSTOP
H1MASKPOL
Unused
Vertical H Masking Start Position
Vertical H Masking Stop Position
Masking Polarity for H1 during Vertical Blanking Period
(21:11)
22
(31:23)
9
Mode_Reg(13) (11:0)
(23:12)
12
12
8
99
830
LMSTART0
LMSTART1
Unused
LM Counter Start Position 1
LM Counter Start Position 2
(31:24)
–16–
REV. 0
AD9937
Table VI. Mode_B (Addr 0x18) (continued)
Register
Bit
Bit
Addr
Breakdown Width
Default Name
Function
Mode_Reg(14) (7:0)
(15:8)
8
8
8
8
1
0
0
0
SCP1
SCP2
SCP3
SCP4
Sequence Change Position 1
Sequence Change Position 2
Sequence Change Position 3
Sequence Change Position 4
(23:16)
(31:24)
Mode_Reg(15) (11:0)
12
2
3
1
2
1
1
10
1559
HDLEN0
HD Counter Length Value for Region 0
(13:12)
(16:14)
17
(19:18)
20
0
0
0
0
0
1
VTPPATSEL0
VTPREP0
LMPATSEL0
LMREP0
SPHEN0
CLPOBEN0
Unused
VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2)
VTP Pulse Repetition Number in Region 0
LM Pattern Select for Region 0 (0 = LM0, 1 = LM1)
LM Repetition Number in Region 0
Special H-Pattern Enable in Region 0
CLPOB Enable in Region 0
21
(31:22)
Mode_Reg(16) (11:0)
12
2
3
1
2
1
1
10
1559
HDLEN1
HD Counter Length Value for Region 1
VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2)
VTP Pulse Repetition Number in Region 1
LM Pattern Select for Region 1 (0 = LM0, 1 = LM1)
LM Repetition Number in Region 1
Special H-Pattern Enable in Region 1
CLPOB Enable in Region 1
(13:12)
(16:14)
17
(19:18)
20
1
1
1
1
0
1
VTPPATSEL1
VTPREP1
LMPATSEL1
LMREP1
SPHEN1
CLPOBEN1
Unused
21
(31:22)
Mode_Reg(17) (11:0)
12
2
3
1
2
1
1
10
1559
HDLEN2
HD Counter Length Value for Region 2
VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2)
VTP Pulse Repetition Number in Region 2
LM Pattern Select for Region 2 (0 = LM0, 1 = LM1)
LM Repetition Number in Region 2
(13:12)
(16:14)
17
(19:18)
20
21
(31:22)
1
1
1
1
0
1
VTPPATSEL2
VTPREP2
LMPATSEL2
LMREP2
SPHEN2
CLPOBEN2
Unused
Special H-Pattern Enable in Region 2
CLPOB Enable in Region 2
Mode_Reg(18) (11:0)
12
2
3
1
2
1
1
10
1559
HDLEN3
HD Counter Length Value for Region 3
VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2)
VTP Pulse Repetition Number in Region 3
LM Pattern Select for Region 3 (0 = LM0, 1 = LM1)
LM Repetition Number in Region 3
(13:12)
(16:14)
17
(19:18)
20
1
1
1
1
0
1
VTPPATSEL3
VTPREP3
LMPATSEL3
LMREP3
SPHEN3
CLPOBEN3
Unused
Special H-Pattern Enable in Region 3
CLPOB Enable in Region 3
21
(31:22)
Mode_Reg(19) (11:0)
12
2
3
1
2
1
1
10
1559
HDLEN4
HD Counter Length Value for Region 4
VTP Pattern Select (0 = VTP0, 1 = VTP1, 2 = VTP2)
VTP Pulse Repetition Number in Region 4
LM Pattern Select for Region 4 (0 = LM0, 1 = LM1)
LM Repetition Number in Region 4
(13:12)
(16:14)
17
(19:18)
20
1
1
1
1
0
1
VTPPATSEL4
VTPREP4
LMPATSEL4
LMREP4
SPHEN4
CLPOBEN4
Unused
Special H-Pattern Enable in Region 4
CLPOB Enable in Region 4
21
(31:22)
REV. 0
–17–
AD9937
SERIAL INTERFACE TIMING
System and Mode Register Serial Interface
All of the internal registers of the AD9937 are accessed through
a 3-wire serial interface. The 3-wire interface consists of a clock
(SCK), serial load (SLD), and serial data (SDA).
The AD9937 provides two options for writing to system and
mode registers. The Page/Burst write option is used when all the
registers are going to be written to, whereas the Random Access
option is used when only one or a small contiguous sequence of
registers is going to be written to. As shown in Figure 6, the
protocol for writing to system and mode registers requires eight
bits for the address data, 12 bits for the start location, 12 bits
for the end location, and 32 bits for the register data.
The AD9937 has three different register types that are configured
by the 3-wire serial interface pins. As described in Table VII,
the three register types are control registers, system registers,
and mode registers.
Table VII. Serial Interface Registers
Page/Burst Option
The AD9937 is automatically configured for Page/Burst mode if
both 12-bit STARTADDRESS and ENDADDRESS fields
equal 0. In this configuration, the AD9937 expects all registers
to be written to, therefore all register data must be clocked in
before the SLD pulse is asserted high. The SLD pulse is ignored
until all register data is clocked in. The Page/Burst option is
preferred when initially programming the system and mode
registers at startup.
Register
Address
No. of Registers
Control Registers
0x00 to
0x12
24-Bit Register at Each
Address. See Table I.
VTP Sequence
System Registers
0x14
0x15
0x16
0x17
0x18
Fourteen 32-Bit System
Registers at Address
0x14. See Table II.
H/LM System
Registers
Ten 32-Bit System
Registers at Address
0x15. See Table III.
Random Access Option
With the Random Access option, the 12-bit STARTADDRESS
and ENDADDRESS fields are typically used when writing to
one system or mode register or a small sequential number of
system or mode registers. In this mode, the address data selects
the system or mode register bank that is going to be accessed,
the 12-bit STARTADDRESS determines the first register to be
accessed, and the 12-bit ENDADDRESS determines the last
register to be accessed. Two examples of Random Access are
provided below (refer to Figure 6).
Shutter System
Registers
Five 32-Bit System
Registers at Address
0x16. See Table IV.
Mode_A
Mode_B
Twenty 32-Bit Mode_A
Registers at Address
0x17. See Table V.
Twenty 32-Bit Mode_B
Registers at Address
0x18. See Table VI.
Example 1: Accessing Only One Register, HLM_Reg(6)
HLM_Reg_addr[A7:A0] = 0x15
STARTADDRESS[S11:S0] = 0x0006
ENDADDRESS[E11:E0] = 0x0006
Control Register Serial Interface
The control register 3-wire interface timing requirements are
shown in Figure 5. Writing to control registers requires eight bits of
address data followed by 24 bits of configuration data between
each active low period of SLD for each address. The SLD signal
must be kept high for at least one full SCK cycle between suc-
cessive writes to control registers.
Example 2: Accessing HLM_Reg(2), HLM_Reg(3), and
HLM_Reg(4) Sequentially
HLM_Reg_addr[A7:A0] = 0x15
STARTADDRESS[S11:S0] = 0x0002
ENDADDRESS[E11:E0] = 0x0004
....
....
SDA
SCK
A7
A6
tDH
A5
A4
A3
A2
A1
A0
D23
D22
D21
D3
D2
D1
D0
tDS
1
2
3
4
5
6
7
8
9
10
11
29
30
31
tLH
32
tLS
SLD
1. SDA BITS ARE INTERNALLY LATCHED ONTHE RISING EDGES OF SCK.
2. THISTIMING PATTERN MUST BEWRITTEN FOR EACH REGISTERWRITEWITH SLD REMAINING HIGH FOR AT
LEAST ONE FULL SCK PERIOD BEFORE ASSERTING SLD LOW AGAIN FORTHE NEXT REGISTERWRITE.
Figure 5. 3-Wire Serial Interface Timing for Control Registers
–18–
REV. 0
AD9937
8-BIT REG
ADDRESS [7:0]
12-BIT START
ADDRESS [11:0]
12-BIT END
ADDRESS[11:0]
32-BIT DATA 0 [31:0]
32-BIT DATA N [31:0]
SDA
8 BIT
ADDRESS
START LOCATION
ADDRESS
END LOCATION
ADDRESS
DATA 0 [31:0]
DATA N [31:0]
SCK
SLD
1
1
2
1
1. ALL SLD PULSES ARE IGNORED UNTILTHE LAST BIT OFTHE LAST DATA NWORD IS CLOCKED IN.
2.THE SLD PULSE MUST BE ASSERTED HIGHWHEN ALL SDA DATATRANSMISSIONS HAVE BEEN COMPLETED.
Figure 6. System and Mode Register Writes
Internal Power-On Reset Circuitry
Asynchronous Register Operation
After power-on, the AD9937 automatically resets all internal
registers and performs internal calibration procedures. This
takes approximately 1 ms to complete. During this time, normal
clock signals and serial write operations may occur. However,
serial register writes are ignored until the internal reset opera-
tion is completed.
For asynchronous register writes, SDA data is stored directly
into the serial register at the rising edge of SLK. As a result,
register operation begins immediately after the register LSB has
been latched in on the rising edge of SCK.
VD Synchronous Register Operation
For VD synchronous type registers, SDA data is temporarily
stored in a buffer register upon completion of clocking in the
last register LSB. This data is held in the temporary buffer
register until the next rising edge of VD is applied. Once the
next rising edge of VD occurs, the buffered register data is
loaded into the serial register, and register operation begins.
See Figure 7.
VD Synchronous and Asynchronous Register Operation
There are two types of control registers, VD synchronous and
VD asynchronous, as indicated in the Address column of Table I.
Register writes to synchronous and asynchronous type registers
operate differently as described in the following sections. All
writes to system, Mode_A, and Mode_B registers occur
asynchronously.
Control registers at addresses 0x08, 0x09, 0x10, 0x11, and 0x12
are VD synchronous type registers.
OPERATION OF VD SYNCHRONOUS TYPE
REGISTER WRITES BEGIN AT THE NEXT VD
RISING EDGE.
VD
HD
VCKM
PROGRAMMING VD SYNCHRONOUS
TYPE REGISTERS MUST BE COMPLETED
AT LEAST FOUR VCKM CYCLES BEFORE
THE RISING EDGE OF VD.
Figure 7. VD Synchronous Type Register Writes
REV. 0
–19–
AD9937
SYSTEM OVERVIEW
The H-drivers for H1(A–D) and H2(A,B), and RS are included
in the AD9937, allowing these clocks to be directly connected
to the CCD. H-drive voltage of up to 3.6 V is supported. An
external V-driver is required for the vertical transfer clocks and
sensor gate pulses.
Figure 8 shows the typical system block diagram for the AD9937.
The CCD output is processed by the AD9937’s AFE circuitry,
which consists of a CDS, VGA, black level clamp, and A/D
converter. The digitized pixel information is sent to the digital
image processor chip, which performs the postprocessing and
compression. To operate the CCD, all CCD timing parameters
are programmed into the AD9937 from the system micropro-
cessor, through the 3-wire serial interface. From the system
master clock, VCKM provided by the image processor or exter-
nal crystal, the AD9937 generates all of the CCD’s horizontal
and vertical clocks and all internal AFE clocks.
Figure 9 shows the horizontal and vertical counter dimensions
for the AD9937. All internal horizontal and vertical clocking is
programmed using these dimensions to specify line and pixel
locations.
MAXIMUM FIELD DIMENSIONS
12-BIT HORIZONTALCOUNTER = 4096 PIXELS MAX
CCD
AD9937
DIGITAL
OUTPUTS
V
OUT
ADC
OUT
0.1ꢂF
DIGITAL IMAGE
PROCESSING
ASIC
CCDIN
C
SERIAL
INTERFACE
IN
REGISTER
DATA
BUFFER
V-DRIVE
CCD
TIMING
TIMING
GENERATOR
Figure 8. Typical System Block Diagram, Master Mode
Figure 9. Horizontal and Vertical Counters
MAX VD LENGTH IS 2048 LINES
VD
MAX HD LENGTH IS 4095 PIXELS
HD
VCKM
Figure 10. Maximum VD/HD Dimensions
–20–
REV. 0
AD9937
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9937 AFE signal processing chain is shown in Figure 11.
Each processing step is essential in achieving a high quality image
from the raw CCD pixel data.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
diagram in Figure 13 illustrates how the two internally gener-
ated CDS clocks, SHP and SHD, are used to sample the
reference level and the data level, respectively, of the CCD
signal. The placement of the SHP and SHD sampling edges is
determined by the setting of the SHPLOC (addr 0x05) and
SHDLOC (addr 0x05) control registers. Placement of these two
clock edges is critical in achieving the best performance from
the CCD.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to approxi-
mately 1.5 V to be compatible with the 3 V analog supply of
the AD9937.
1.0ꢂF
REFT
2.0V
1.0ꢂF
REFB
1.0V
DC RESTORE
AD9937
INTERNAL
VREF
1.5V
DOUT
PHASE
SHP
SHD
2V FULL
SCALE
6dB TO 40dB
0.1ꢂF
OUTPUT
DATA
LATCH
10
CCDIN
ADC
CDS
VGA
DOUT
10
OPTICAL BLACK
CLAMP
8-BIT
DAC
VGA GAIN
REGISTER
CLPOB
DIGITAL
FILTER
8
DOUT
PHASE
SHD
CLPOB
SHP
CLAMP LEVEL
REGISTER
V-H
PRECISION
TIMING
TIMING
GENERATION
GENERATION
Figure 11. AFE Block Diagram
REV. 0
–21–
AD9937
PRECISION TIMING HIGH SPEED TIMING
GENERATION
High Speed Clock Programmability
Figure 13 shows how the high speed clocks RS, H1–H2, SHP, and
SHD are generated. The RS and H1 pulse have positive and nega-
tive edge programmability by using control registers (addr 0x06).
The H2 clock is always the inverse of H1. Table VIII summarizes
the high speed timing registers and the parameters for the high
speed clocks. Each register is six bits wide with the 2 MSB
used to select the quadrant region as outlined in Table IX.
Figure 14 shows the range and default locations of the high
speed clock signals.
The AD9937 generates flexible high speed timing signals using
the precision timing core. This core is the foundation for gener-
ating the timing used for both the CCD and the AFE: the
reset gate RS, horizontal drivers H1(A–D) and H2(A, B), and
the CDS sample clocks. A unique architecture makes it routine
for the system designer to optimize image quality by providing
precise control over the horizontal CCD readout and the AFE
correlated double sampling.
Timing Resolution
H-Driver and RS Outputs
The precision timing core uses a 13 master clock input
(VCKM) as a reference. This clock should be the same as
the CCD pixel clock frequency. Figure 12 illustrates how
the internal timing core divides the master clock period into
48 steps or edge positions. Using a 12 MHz VCKM fre-
quency, the edge resolution of the precision timing core is
1.7 ns. A 24 MHz VCKM frequency can be applied to the
AD9937 where the AD9937 will internally divide the VCKM
frequency by 2. VCKM frequency division by 2 is controlled
by using the VCKM_DIVIDE control (addr 0x04) register.
In addition to the programmable timing positions, the AD9937
features on-chip output drivers for the RS and H1–H2 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver current can be adjusted for optimum rise/
fall time into a particular load by using the H1DRV and H2DRV
control registers (addr 0x07). The RS drive current is adjustable
using the RSDRV control register (addr 0x07). The H1DRV,
H2DRV, and RSDRV registers are adjustable in 1.75 mA incre-
ments. All DRV registers have setting of 0 equal to OFF or
three-state, and the maximum setting of 7.
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
POSITION
VCKM
tVCKMDLY
1 PIXEL
PERIOD
PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
THERE IS A FIXED DELAY FROMTHE VCKM INPUTTOTHE INTERNAL PIXEL PERIOD POSITIONS (tVCKMDLY = 6ns TYP).
Figure 12. High Speed Clock Resolution from VCKM Master Clock
3
CCD
SIGNAL
4
(INTERNAL)
CDS
1
5
2
RS
6
H1
H2
PROGRAMMABLE CLOCK INFORMATION
1. RG RISING EDGE (PROGRAMMABLE AT CONTROL REGISTER RSPOSLOC (ADDR 0x06))
2. RG FALLING EDGE (PROGRAMMABLE AT CONTROL REGISTER RSNEGLOC (ADDR 0x06))
3. SHP SAMPLE LOCATION (PROGRAMMABLE AT CONTROL REGISTER SHPLOC (ADDR 0x05))
4. SHD SAMPLE LOCATION (PROGRAMMABLE AT CONTROL REGISTER SHDLOC (ADDR 0x05))
5. H1 RISING EDGE LOCATION (PROGRAMMABLE AT CONTROL REGISTER H1POSLOC (ADDR 0x06))
6. H1 NEGATIVE EDGE LOCATION (PROGRAMMABLE AT CONTROL REGISTER H1NEGLOC (ADDR 0x06))
7. H2 IS ALWAYS THE INVERSE OF H1.
Figure 13. High Speed Clock Programmable Locations
–22–
REV. 0
AD9937
Table VIII. RS, H1, SHP, SHD, and DOUTPHASE Timing Parameters
Bit Width
Register Name*
(Bits)
Register Type
Range
Description
RSPOSLOC
RSNEGLOC
H1POSLOC
H1NEGLOC
SHPLOC
6
6
6
6
6
6
6
Control (Addr 0x06)
Control (Addr 0x06)
Control (Addr 0x06)
Control (Addr 0x06)
Control (Addr 0x05)
Control (Addr 0x05)
Control (Addr 0x05)
0–47 Edge Location
0–47 Edge Location
0–47 Edge Location
0–47 Edge Location
0–47 Edge Location
0–47 Edge Location
0–47 Edge Location
Falling Edge Location for RS
Falling Edge Location for RS
Positive Edge Location for H1
Negative Edge Location for H1
Sample Location for SHP
SHDLOC
DOUTPHASE
Sample Location for SHD
Phase Location of Data Output [9:0]
*The 2 MSB bits are used to select the quadrant.
Table IX. Precision Timing Edge Locations for RS, H1, SHP, SHD, and DOUTPHASE
Quadrant
(Range)
RS Rising Edge
RSPOSLOC
RS Falling Edge
RSNEGLOC
Signal Name
RS
I
II
III
IV
P[0] to P[11]
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
Quadrant
(Range)
H1 Rising Edge
H1POSLOC
H1 Falling Edge
H1NEGLOC
Signal Name
H1
I
II
III
IV
P[0] to P[11]
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
Quadrant
(Range)
CDS (SHP) Rising Edge
SHPLOC
CDS (SHD) Falling Edge
SHDLOC
Signal Name
CDS (Internal)
I
II
III
IV
P[0] to P[11]
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
Quadrant
(Range)
DOUT Rising Edge
DOUTPHASE
DOUT Falling Edge
(Not Programmable)
Signal Name
Data Output[9:0]
I
II
III
IV
P[0] to P[11]
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
DOUTPHASE + 24 Steps
DOUTPHASE + 24 Steps
DOUTPHASE + 24 Steps
DOUTPHASE + 24 Steps
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
REV. 0
–23–
AD9937
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
POSITION
PIXEL
PERIOD
RSr[0]
Hr[0]
RSf[12]
RS
H1
Hf[24]
CDS
(INTERNAL)
SHP[24]
tS1
CCD
SIGNAL
SHD[48]
Figure 14. High Speed Clock Default and Programmable Locations
tRISE
H1
H2
tPD < tRISE
tPD
H2
H1
FIXED CROSSOVER VOLTAGE
Figure 15. H-Clock Inverse Phase Relationship
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
PIXEL
PERIOD
VCLK
tOD
DOUT
1. DOUTPHASE REGISTER (ADDR 0x05) CAN BE USEDTO SHIFTTHE PHASE OF VCLK AND DOUTTOGETHERWITH RESPECTTO P[0].
2. DOUT[9:0] CAN BE INDEPENDENTLY DELAYEDWITH RESPECTTO VCLK BY USING DOUT_DELAY REGISTER (ADDR 0x05).
Figure 16. Digital Output Phase Adjustment
–24–
REV. 0
AD9937
MASTER AND SLAVE MODE OPERATION
The AD9937 defaults at power up into slave mode operation.
During slave mode operation, the VD and HD pins are config-
ured as inputs for external VD and HD signals. The AD9937
can be configured into master mode operation to output the
VD and HD signals by programming MASTER = 1 (control
addr 0x05).
Individual HMASK Sequence
The HMASK programmable timing shown in Figure 18 pro-
vides two HMASK toggle positions and an H1MASK polarity
setting. These registers can be used to disable the horizontal
H1 and H2 outputs during the vertical transfer period. As shown
in Figure 18, the H2(A, B) outputs are always the opposite
polarity of the H1(A–D) outputs. The H1MASKSTART and
H1MASKSTOP registers reference the 11-bit VD counter.
HORIZONTAL AND VERTICAL TIMING
Individual PBLK Sequences
The internal VD and HD synchronization timing is configured
by using the registers in Table X. As shown in Figure 17, the
HD and VD clock positions are referenced to the 12-bit
H-counter and 11-bit V-counter, respectively. This allows for
a maximum of 4096 horizontal pixels by 2048 vertical
line resolution.
Up to two individual PBLK pulses can be programmed per line
using the registers in Table XI. During the time PBLK is active,
the DOUT[9:0] data is fixed at the level set in the PBLK_LEVEL
(control addr 0x03) register. Figures 19, 20, and 21 provide
examples of PBLK registers described in Table XI.
The AD9937 provides programmability for two HD pulses per
line with the ability to independently set the last line length by
using the HDLASTLEN register (Mode_Reg(4)). Additionally,
the HDLENx (where x = 0, 1, 2, 3, 4 representing CCD regions)
registers can be used to set different line lengths for each CCD
region. As shown in Figure 31, up to five unique CCD regions
may be specified.
Table X. HD and VD Registers
Length
(Bits)
Register Name
Register Type
Range
Description
VDLEN
11
4
4
Mode_Reg(4)
Mode_Reg(4)
Mode_Reg(4)
Mode_Reg(2)
Mode_Reg(2)
Mode_Reg(3)
Mode_Reg(3)
Mode_Reg(4)
Mode_Reg(15)
Mode_Reg(16)
Mode_Reg(17)
Mode_Reg(18)
Mode_Reg(19)
Control 0x04
0–2047 Line Number
0–15 Pixel Location
0–15 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
HIGH/LOW
11-Bit VD Counter Length
VD Toggle Position 1. See Figure 17.
VD Toggle Position 2. See Figure 17.
HD Toggle Position 1. See Figure 17.
HD Toggle Position 2. See Figure 17.
HD Toggle Position 3. See Figure 17.
HD Toggle Position 4. See Figure 17.
HD Last Line Length. See Figure 17.
12-Bit HD Counter Length Value for CCD Region 0
12-Bit HD Counter Length Value for CCD Region 1
12-Bit HD Counter Length Value for CCD Region 2
12-Bit HD Counter Length Value for CCD Region 3
12-Bit HD Counter Length Value for CCD Region 4
VD and HD Inversion Control
VDTOG1
VDTOG2
HDTOG1
HDTOG2
HDTOG3
HDTOG4
HDLASTLEN
HDLEN0
HDLEN1
HDLEN2
HDLEN3
HDLEN4
VDHD_INVERT
12
12
12
12
12
12
12
12
12
12
1
REV. 0
–25–
AD9937
VDLEN
11-BIT
VD COUNTER
000
001
000
001
002
003
N – 1
N
2048
12-BIT
HD COUNTER
*
HDLENx
HDLASTLEN
1
2
3
VD
HD
4
5
6
7
OPTIONAL SECOND HD PULSE PER LINE
X = 0, 1, 2, 3, 4 REPRESENTING CCD REGIONS
*
PROGRAMMABLE CLOCK POSITIONS
1. VDHD_INVERT (PROGRAMMABLE AT CONTROL 0x04)
2. VDTOG1 (PROGRAMMABLE AT MODE_REG(4))
3. VDTOG2 (PROGRAMMABLE AT MODE_REG(4))
4. HDTOG1 (PROGRAMMABLE AT MODE_REG(2))
5. HDTOG2 (PROGRAMMABLE AT MODE_REG(2))
6. HDTOG3 (PROGRAMMABLE AT MODE_REG(3))
7. HDTOG4 (PROGRAMMABLE AT MODE_REG(3))
Figure 17. VD and HD Programmable Locations
11-BIT
VD COUNTER
VD
HMASK
H1(A–D)
1
2
3
H1(A–D)
H1(A, B)
PROGRAMMABLE CLOCK POSITIONS
1. HMASKSTART (PROGRAMMABLE AT MODE_REG(12))
2. HMASKSTOP (PROGRAMMABLE AT MODE_REG(12))
3. H1MASKPOL (PROGRAMMABLE AT MODE_REG(12))
THE POLARITY OF H1(A–D) DURING BLANKING IS PROGRAMMABLE
(H2(A, B) IS ALWAYSTHE OPPOSITE POLARITY OF H1 (A–D))
Figure 18. Programmable Clock Positions for HMASK
Table XI. PBLK Registers
Register
Length
(Bits)
Register Name
Type
Range
Description
PBLK_LEVEL
1
Control 0x03
HIGH/LOW
0 = Blank Output Data to Zero,
1 = Blank Output Data to REFBLACK
PBLKTOG1
PBLKTOG2
PBLKTOG3
PBLKTOG4
PBLKSTART
PBLKSTOP
12
12
12
12
11
11
Mode_Reg(9)
Mode_Reg(9)
Mode_Reg(10)
Mode_Reg(10)
Mode_Reg(11)
Mode_Reg(11)
0–4095 Pixel Locations
0–4095 Pixel Locations
0–4095 Pixel Locations
0–4095 Pixel Locations
0–2047 Line Number
0–2047 Line Number
Sets PBLK Toggle Position 1 within the Line
Sets PBLK Toggle Position 2 within the Line
Sets PBLK Toggle Position 3 within the Line
Sets PBLK Toggle Position 4 within the Line
Sets the Line Number the PBLK Pulse Will Start In
Sets the Line Number the PBLK Pulse Will Stop In
–26–
REV. 0
AD9937
12-BIT
HD COUNTER
PBLK
1
3
2
4
PROGRAMMABLE CLOCK POSITIONS
1. PBLKTOG1 (PROGRAMMABLE AT MODE_REG(9))
2. PBLKTOG2 (PROGRAMMABLE AT MODE_REG(9))
3. PBLKTOG3 (PROGRAMMABLE AT MODE_REG(10))
4. PBLKTOG4 (PROGRAMMABLE AT MODE_REG(10))
Figure 19. PBLK Timing
HDLEN = 1500
PBLKTOG2 = 785
PBLKTOG1 = 500
12-BIT
HD COUNTER
PBLK
1. PBLKTOG1 = 500
2. PBLKTOG2 = 785
3. PBLKTOG3 = 4095
4. PBLKTOG4 = 4095
5.THIS PBLK PULSE SEQUENCE IS USED INTHE EXAMPLE BELOW.
11-BIT
VD COUNTER
N – 4
N – 3
N – 2
N – 1
N
000
001
002
003
VD
500 785
500 785
500
500 785
500 785
500 785
12-BIT
HD COUNTER
PBLKSTART
PBLKSTOP
1. PBLKSTART = N – 2
2. PBLKSTOP = 001
3.THIS EXAMPLE SHOWS HOW PBLK IS LOW INTHEVERTICAL BLANKING REGION FROM PBLKTOG1 IN LINE PBLKSTART UNTIL PBLKTOG2 IN LINE PBLKSTOP.
AS SHOWN INTHE ABOVE FIGURE, PBLK REMAINS LOW FROM PBLKTOG1TO PBLKTOG2.
Figure 20. Example of PBLK Applied in Vertical Blanking Region Using PBLKSTART and PBLKSTOP Registers
REV. 0
–27–
AD9937
11-BIT
VD COUNTER
000
001
002
003
004
N – 1
N
12-BIT
HD COUNTER
VD
HD
PBLK
Figure 21. Example with PBLKSTOP = PBLKSTART = 2048
Controlling CLPOB Clamp Pulse Timing
provided that allow for independently enabling and disabling
the CLPOB pulse in each region of the CCD. Figure 23 shows
an example of disabling the CLPOB pulse while operating in
CCD region 1.
Up to two individual CLPOB pulses can be programmed per line
using the CLPOBTOGx (x = 1, 2, 3, 4) registers in Table XII.
As shown in Figure 19, these registers reference the 12-bit HD
counter. Additional CLPOBENn (n = 0, 1, 2, 3, 4) registers are
Table XII. CLPOB Registers
Length
(Bits)
Register
Type
Register Name
Range
Description
CLPOBTOG1
CLPOBTOG2
CLPOBTOG3
CLPOBTOG4
CLPOBEN0
CLPOBEN1
CLPOBEN2
CLPOBEN3
CLPOBEN4
12
12
12
12
1
1
1
1
1
Mode_Reg(5)
Mode_Reg(5)
Mode_Reg(6)
Mode_Reg(6)
Mode_Reg(15)
Mode_Reg(16)
Mode_Reg(17)
Mode_Reg(18)
Mode_Reg(19)
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
First Toggle Position for CLPOB
First Toggle Position for CLPOB
First Toggle Position for CLPOB
First Toggle Position for CLPOB
CCD Region 0 CLPOB Enable Disable Control
CCD Region 1 CLPOB Enable Disable Control
CCD Region 2 CLPOB Enable Disable Control
CCD Region 3 CLPOB Enable Disable Control
CCD Region 4 CLPOB Enable Disable Control
12-BIT
HD COUNTER
HD
CLPOB
1
2
3
4
PROGRAMMABLE CLOCK POSITIONS
1. CLPOBTOG1 (PROGRAMMABLE AT MODE_REG(5))
2. CLPOBTOG2 (PROGRAMMABLE AT MODE_REG(5))
3. CLPOBTOG3 (PROGRAMMABLE AT MODE_REG(6))
4. CLPOBTOG4 (PROGRAMMABLE AT MODE_REG(6))
Figure 22. CLPOB Toggle Positions
–28–
REV. 0
AD9937
CCD REGION 2
CCD REGION 0
CCD REGION 1
VD
HD
CLPOB
Figure 23. Example with CLPOBEN1 = 0
Vertical Sensor Transfer Gate Timing
SHUTTER TIMING CONTROL
The vertical transfer sensor gate (TG) pulses are used to trans-
fer the pixel charges from the light-sensitive image area into the
light-shielded vertical registers. When a mechanical shutter is
not being used, this transfer effectively ends the exposure
period during the image acquisition. From the light-shield
vertical registers, the image is then read out line by line using
the vertical transfer pulses in conjunction with the high speed
horizontal clocks.
CCD image exposure is controlled through use of the substrate
clock signal (OFD), which pulses the CCD substrate to clear
out accumulated charge. The AD9937 supports two types of
OFD shutter timing: normal shutter mode and high precision
shutter mode. The registers used for OFD programming are
described in Table XIV.
Normal Shutter Mode
Figure 24 shows the VD and OFD output for normal shutter
mode. Programming the OFD outputs is similar to program-
ming the TG pulse whereas two unique OFD pulses can be
preprogrammed using the OFDTOG_x (x = 0, 1) registers. The
OFDTOG_x registers reference the 12-bit HD counter as shown
in Figure 24. Once the toggle positions have been programmed,
the OFDPATSEL register is used to select which of the two
preprogrammed OFD pulses will be output. The OFD will pulse
once per line for as many lines set in the OFDNUM register.
The AD9937 provides four programmable vertical transfer gate
pulses (TG1A, TG1B, TG3A, and TG3B). Table XIII lists the
TG registers. Two unique TG pulses can be preprogrammed
using the TGTOG_x (x = 0, 1) registers. As shown in Figure 24,
these toggle registers reference the 12-bit H counter for resolu-
tion control at the pixel level. Once the toggle positions have
been programmed, the TGPATSELx (x = 0, 1) can be used to
select which of the two TG pulses will be output on the TG1A/
B and TG3A/B pins. The TG1A/B and TG3A/B outputs are
selected as a group. As a result, the TG1A and TG1B outputs
will always be the same. This also applies for the TG3A and
TG3B outputs. For example, if TGPATSEL0 = 0, TG1A and
TG1B will have the outputs provided by the TGTOG1_0 and
TGTOG2_0 registers.
High Precision Shutter Mode
High precision shuttering is controlled in the same way as nor-
mal shuttering but requires a second set of shutter registers. In
this mode, the OFD still pulses once per line, but the last OFD
in the field will have an additional OFD pulse whose location is
determined by the OFDHPTOG1 and OFDHPTOG2 registers.
An example of this is shown in Figure 25. Finer resolution of
the exposure time is possible using this mode. Leaving both
OFDHPTOG registers set to 4095 disables the high precision
shutter mode (default setting).
The TGMASK register can be used to individually mask (disable)
any one of the TG outputs. For example, if TGMASK = 1, the
TG1A will not be output. All TG outputs can be disabled by
setting TGEN = 0.
Table XIII. TG Registers
Length Register
Register Name
(Bits)
Type
Range
Description
TGEN
1
Control 0x10
Shut_Reg(1)
Shut_Reg(1)
Shut_Reg(2)
Shut_Reg(2)
Mode_Reg(1)
Mode_Reg(1)
Mode_Reg(1)
Mode_Reg(1)
High/Low
TG Output Enable Control (0 = Disable, 1 = Enable)
TG0 Pulse Toggle Position 1
TG0 Pulse Toggle Position 2
TG1 Pulse Toggle Position 1
TGTOG1_0
TGTOG2_0
TGTOG1_1
TGTOG2_1
TGACTLINE
TGPATSEL0
TGPATSEL1
TGMASK
12
12
12
12
7
1
1
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–127 Pixel Location
High/Low
TG1 Pulse Toggle Position 2
Line in Field where TG Outputs are Active
TG1 A/B Pattern Selector (0 = TG0, 1 = TG1)
TG3 A/B Pattern Selector (0 = TG0, 1 = TG1)
TG Masking Control (0 = No Masking, 1 = Mask TG1A,
2 = Mask TG1B, 3 = Mask TG3A, 4 = Mask TG3B)
High/Low
4 Individual Bits
4
REV. 0
–29–
AD9937
Table XIV. OFD Registers
Length Register
Register Name
(Bits)
Type
Range
Description
OFDEN
OFDNUM
1
Control 0x10
Control 0x10
Control 0x11
Control 0x11
Shut_Reg(3)
Shut_Reg(3)
Shut_Reg(4)
Shut_Reg(4)
Mode_Reg(1)
High/Low
0–2048 Pulses
OFD Output Enable Control (0 = Disable, 1 = Enable)
Total Number of OFD Pulses per Field
11
12
12
12
12
12
12
1
OFDHPTOG1
OFDHPTOG2
OFDTOG1_0
OFDTOG2_0
OFDTOG1_1
OFDTOG2_1
OFDPATSEL
0–4095 Pixel Locations High Precision Toggle Position 1. See Figure 24.
0–4095 Pixel Locations High Precision Toggle Position 2. See Figure 24.
0–4095 Pixel Locations OFD0 Pulse Toggle Position 1
0–4095 Pixel Locations OFD0 Pulse Toggle Position 2
0–4095 Pixel Locations OFD1 Pulse Toggle Position 1
0–4095 Pixel Locations OFD1 Pulse Toggle Position 2
High/Low
OFD Pattern Selector (0 = OFD0, 1 = OFD1)
11-BIT
VD COUNTER
000
001
002
003
N – 1
N
2048
000
001
12-BIT
HD COUNTER
LAST LINE
VD
HD
1
2
TG1A
TG1B
3
TG3A
TG3B
4
5
tEXP
OFD
6
7
PROGRAMMABLE CLOCK POSITIONS
1. TGACTLINE (PROGRAMMABLE AT MODE_REG(1)) 5. TGTOG2_1 (PROGRAMMABLE AT SHUT_REG(2))
6. OFDTOG1_0 (PROGRAMMABLE AT SHUT_REG(3))
7. OFDTOG2_0 (PROGRAMMABLE AT SHUT_REG(3))
2. TGTOG1_0 (PROGRAMMABLE AT SHUT_REG(1))
3. TGTOG2_0 (PROGRAMMABLE AT SHUT_REG(1))
4. TGTOG1_1 (PROGRAMMABLE AT SHUT_REG(2))
Figure 24. Horizontal Timing Example with TGACTLINE = 1 and OFDNUM = 2
VD
HD
LAST LINE
TG1A
TG1B
TG3A
TG3B
tEXP
OFD
1
2
PROGRAMMABLE CLOCK POSITIONS
1. OFDHPTOG1 (PROGRAMMABLE AT CONTROL REGISTER 0x11)
2. OFDHPTOG2 (PROGRAMMABLE AT CONTROL REGISTER 0x11)
SECOND OFD PULSE ADDED INTHE
LAST LINE FOR GREATER EXPOSURE
CONTROL PRECISION
Figure 25. High Precision
–30–
REV. 0
AD9937
Controlling LM Pulse Timing
the 12-bit H counter resets to 0 set by the HDLEN register.
The LMSTART0 and LMSTART1 positions reference the 12-
bit H counter value zero. The 8-bit LM counter begins counting
when LMSTART0 is reached; it counts up to the value set in
the LMLENx register, as shown in Figure 26. The LM pulse
toggle positions reference the 8-bit LM counter.
The AD9937 provides an LM output pulse that is fully program-
mable by using the registers in Table XV. Two unique sets of LM
pulses can be preprogrammed using the LMLENx, LMTOG1_x,
and LMTOG2_x (x = 0, 1) registers. Once these pulses are
preprogrammed, they can be individually selected to be output
in any of the five CCD regions by using the LMPATSELn
register (n = 0, 1, 2, 3, 4). The number of repetitions can also be
individually programmed for each CCD region by using the
LMREPn register (n = 0, 1, 2, 3, 4).
Figures 26 and 27 provide examples of programming the LM
pulses. Figure 26 shows an example when LMSTART1 is less
than HDLEN. In this case, multiple sets of LM pulses can be
output between the HDLEN lengths. The number of sets is
determined by the value of HDLEN and LMSTART1. Figure 27
shows that only one set of LM pulses will be output when
LMSTART1 is greater than HDLEN.
The 12-bit H counter and 8-bit LM counters are used for con-
figuring the LM pulse. The 8-bit LM counter resets to 0 when
Table XV. LM Registers
Length
(Bits)
Register
Type
Register Name
Range
Description
LM_INVERT
LMSTART0*
LMSTART1*
1
12
12
Control 0x04
Mode_Reg(13)
Mode_Reg(13)
High/Low
0–4095 Pixels
0–4095 Pixels
LM Inversion Control (1 = Invert Programmed LM)
LM Counter Start Position 1
LM Counter Start Position 2
LMLEN0
8
8
8
8
8
8
HLM_Reg(8)
HLM_Reg(8)
HLM_Reg(8)
HLM_Reg(9)
HLM_Reg(9)
HLM_Reg(9)
0–255 Pixels
0–255 Pixels
0–255 Pixels
0–255 Pixels
0–255 Pixels
0–255 Pixels
LM Counter Length for LM0
LM0 Toggle Position 1
LM0 Toggle Position 2
LM Counter Length for LM1
LM1 Toggle Position 1
LM1 Toggle Position 2
LMTOG1_0
LMTOG2_0
LMLEN1
LMTOG1_1
LMTOG2_1
LMPATSEL0
LMREP0
LMPATSEL1
LMREP1
LMPATSEL2
LMREP2
LMPATSEL3
LMREP3
1
2
1
2
1
2
1
2
1
2
Mode_Reg(15)
Mode_Reg(15)
Mode_Reg(16)
Mode_Reg(16)
Mode_Reg(17)
Mode_Reg(17)
Mode_Reg(18)
Mode_Reg(18)
Mode_Reg(19)
Mode_Reg(19)
High/Low
0–3 LM Repetitions
High/Low
0–3 LM Repetitions
High/Low
0–3 LM Repetitions
High/Low
0–3 LM Repetitions
High/Low
0–3 LM Repetitions
Selects CCD Region 0 LM Pattern (0 = LM0, 1 = LM1)
LM Repetition Number in CCD Region 0
Selects CCD Region 1 LM Pattern (0 = LM0, 1 = LM1)
LM Repetition Number in CCD Region 1
Selects CCD Region 2 LM Pattern (0 = LM0, 1 = LM1)
LM Repetition Number in CCD Region 2
Selects CCD Region 3 LM Pattern (0 = LM0, 1 = LM1)
LM Repetition Number in CCD Region 3
LMPATSEL4
LMREP4
Selects CCD Region 4 LM Pattern (0 = LM0, 1 = LM1)
LM Repetition Number in CCD Region 4
*LMSTART0 and LMSTART1 reference the 12-bit HD counter.
REV. 0
–31–
AD9937
12-BIT
HD COUNTER
1
LMLENx
8-BIT
LM COUNTER
2
LMREPn = 3
1
1
2
3
LMx
LM PULSE SET 1
LM PULSE SET 2
LMSTART0
LMSTART1
NOTES
1
PROGRAMMABLE CLOCK POSITIONS
1. LM_INVERT (PROGRAMMABLE AT CONTROL 0x04)
2. LMTOG1_x (PROGRAMMABLE AT HLM_REG(8))
3. LMTOG2_x (PROGRAMMABLE AT HLM_REG(8))
x = 0, 1 (TWO UNIQUE SETS OF LM OUTPUTS CAN BE PROGRAMMED)
n = 0, 1, 2, 3, 4 (INDIVIDUAL REPETITION CONTROL FOR EACH CCD REGION)
2
Figure 26. Example of LM Pulse with LMSTART1 < HDLEN
12-BIT
HD COUNTER
LMLENx
8-BIT
LM COUNTER
LMREPn = 3
LMx
LM PULSE SET 1
LMSTART0
Figure 27. Example of LM Pulse with LMSTART1 > HDLEN
SPECIAL HORIZONTAL PATTERN TIMING
the H1A output is shown, the same special H timing can be
independently configured on the remaining horizontal outputs
by using the registers described in Table XVI. As shown in
Figure 28, the special H1A output begins when SPHSTARTx
is reached. It is important to note that there are two SPHSTART
registers. If SPHPATSEL = 0, the SPHSTART0 register will
be used, whereas if SPHPATSEL = 1, the SPHSTART1 regis-
ter will be used. The special H patterns can be enabled and
disabled for each of the five CCD regions by using the SPHENx
(x = 0, 1, 2, 3, 4).
The AD9937 provides the ability to interrupt the normal hori-
zontal H1(A–D) and H2(A, B) clocking in order to apply a
special pattern on these outputs. This special horizontal pattern
timing occurs during the period when the LM outputs are active.
Table XVI lists the registers used to program the special H
patterns. Figure 28 provides an example of a special H pattern
being applied to the H1A output.
The timing diagram shown in Figure 28 identifies the registers
associated with outputting the special H patterns. Although only
–32–
REV. 0
AD9937
MASKING H1 AND H2 OUTPUTS
The H1 and H2 outputs can be masked during the horizontal
and vertical transfers as shown in Figures 29 and 30.
will be masked during the entire last line. It is recommended to
always program HBLKTOG3 and HBLKTOG4 to 4095 when
only one H-blanking in a line is required. It is also recommended
to program HBLKTOG1 < HBLKTOG2 < HBLKTOG3 <
HBLKTOG4.
Horizontal Masking
The H1 clocks are masked with the polarity set by the
H1MASKPOL register as shown in Figure 29. The H2 outputs
will always be the opposite polarity of H1. The H1 and H2 out-
puts are masked from HDLEN + 1 to HBLKTOG1 position
when HDLASTLEN is the same as HDLEN. In the case when
HDLASTLEN is greater than HDLEN, the H1 and H2 outputs
Vertical Masking
As shown in Figure 30, the H1 and H2 outputs remain masked
if the horizontal HMASK is followed by the vertical HMASK
region or if the vertical HMASK region is followed by the hori-
zontal HMASK region.
Table XVI. Special H Pattern Registers
Length Register
Register Name
(Bits)
Type
Range
Description
HBLKTOG11
HBLKTOG21
HBLKTOG31
HBLKTOG41
H1APOL
H1BPOL
H1CPOL
H1DPOL
H2APOL
H2BPOL
SPHSTART02
SPHSTART12
SPH1A1
SPH1B1
SPH1C1
SPH1D1
SPH2A1
SPH2B1
SPH1A2
SPH1B2
SPH1C2
12
12
12
12
1
1
1
1
1
1
8
8
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
1
1
1
Mode_Reg(7)
Mode_Reg(7)
Mode_Reg(8)
Mode_Reg(8)
HLM_Reg(1)
HLM_Reg(1)
HLM_Reg(1)
HLM_Reg(1)
HLM_Reg(1)
HLM_Reg(1)
HLM_Reg(8)
HLM_Reg(9)
HLM_Reg(2)
HLM_Reg(2)
HLM_Reg(2)
HLM_Reg(3)
HLM_Reg(3)
HLM_Reg(3)
HLM_Reg(4)
HLM_Reg(4)
HLM_Reg(4)
HLM_Reg(5)
HLM_Reg(5)
HLM_Reg(5)
HLM_Reg(6)
HLM_Reg(6)
HLM_Reg(6)
HLM_Reg(7)
HLM_Reg(7)
HLM_Reg(7)
0–4095 Pixel Locations
0–4095 Pixel Locations
0–4095 Pixel Locations
0–4095 Pixel Locations
High/Low
High/Low
High/Low
High/Low
High/Low
HBLK Toggle Position 1
HBLK Toggle Position 2
HBLK Toggle Position 3
HBLK Toggle Position 4
H1A Special H Pattern Start Polarity
H1B Special H Pattern Start Polarity
H1C Special H Pattern Start Polarity
H1D Special H Pattern Start Polarity
H2A Special H Pattern Start Polarity
H2B Special H Pattern Start Polarity
High/Low
0–255 Pixel Locations
0–255 Pixel Locations
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
LM Pattern #0 (LM0) Special H Pulse Start Position
LM Pattern #1 (LM1) Special H Pulse Start Position
H1A Special H Pattern during LM Repetition 1
H1B Special H Pattern during LM Repetition 1
H1C Special H Pattern during LM Repetition 1
H1D Special H Pattern during LM Repetition 1
H2A Special H Pattern during LM Repetition 1
H2B Special H Pattern during LM Repetition 1
H1A Special H Pattern during LM Repetition 2
H1B Special H Pattern during LM Repetition 2
H1C Special H Pattern during LM Repetition 2
H1D Special H Pattern during LM Repetition 2
H2A Special H Pattern during LM Repetition 2
H2B Special H Pattern during LM Repetition 2
H1A Special H Pattern during LM Repetition 3
H1B Special H Pattern during LM Repetition 3
H1C Special H Pattern during LM Repetition 3
H1D Special H Pattern during LM Repetition 3
H2A Special H Pattern during LM Repetition 3
H2B Special H Pattern during LM Repetition 3
Special H Pattern Enable in CCD Region 0
Special H Pattern Enable in CCD Region 1
Special H Pattern Enable in CCD Region 2
Special H Pattern Enable in CCD Region 3
Special H Pattern Enable in CCD Region 4
SPH1D2
SPH2A2
SPH2B2
SPH1A3
SPH1B3
SPH1C3
SPH1D3
SPH2A3
SPH2B3
SPHEN0
SPHEN1
SPHEN2
SPHEN3
SPHEN4
Mode_Reg(15) High/Low
Mode_Reg(16) High/Low
Mode_Reg(17) High/Low
Mode_Reg(18) High/Low
Mode_Reg(19) High/Low
1
1
NOTES
1The HBLKTOGx toggle positions reference the 12-bit HD counter.
2The SPHSTART0 and SPHSTART1 toggle positions reference the 8-bit LM counter.
REV. 0
–33–
AD9937
12-BIT
HD COUNTER
LMSTART0
8-BIT
LM COUNTER
HBLKTOG1
SPHSTARTx
H1A
2
3
4
5
6
HBLKTOG2
HBLKTOG3
LMSTART1
HBLKTOG3
PROGRAMMING NOTES
1. THERE ARE TWO SPHSTART REGISTERS. THEY ARE SPHSTART0 AND SPHSTART1.
SPHSTART0 IS USED WHEN THE LM0 PULSE IS SELECTED BY SETTING LMPATSEL = 0.
SPHSTART1 IS USED WHEN THE LM1 PULSE IS SELECTED BY SETTING LMPATSEL = 1.
2.THIS REGION REPRESENTS NORMAL H1A OUTPUTS.
3.THIS REGION REPRESENTS SPECIAL H1A PATTERN BEING OUTPUT DURINGTHE LM REP 1.
THE SPH1A1 REGISTER IS USEDTO SETTHE SPECIAL H1A PATTERN INTHIS REGION.
4.THIS REGION REPRESENTS SPECIAL H1A PATTERN BEING OUTPUT DURINGTHE LM REP 2.
THE SPH1A2 REGISTER IS USEDTO SETTHE SPECIAL H1A PATTERN INTHIS REGION.
5.THIS REGION REPRESENTS SPECIAL H1A PATTERN BEING OUTPUT DURINGTHE LM REP 3.
THE SPH1A3 REGISTER IS USEDTO SETTHE SPECIAL H1A PATTERN INTHIS REGION.
6.THIS REGION REPRESENTS NORMAL H1A OUTPUTS.
8-BIT
LM COUNTER
SPHSTARTx
PIXEL
CLOCK
SPH1A1
1
1
0
1
0
1
SPECIAL
H1A
PROGRAMMING NOTES
1.THIS EXAMPLE SHOWS H1A OUTPUT FOR REGION 3 ABOVE.
INTHIS EXAMPLE: SPH1A1 = 110101.
2.THE SPECIAL H PATTERN STARTING POLARITY CAN BE INDEPENDENTLY SET FOR EACH H OUTPUT
USINGTHE POL REGISTERS LISTED INTABLE XVI. NOTE: THE SPECIAL H STARTING POLARITYWILL
OCCUR ATTHE START OF SPHSTARTx. (ABOVE: H1APOL = 0)
Figure 28. Example of Programming the Special H-Output Patterns
HMASK
HBLK
HBLK
HBLK
3
0
131
132
133
134
135
823
824
825
868
1559 1560
1
2
4
H1TOG34POL
H1MASKPOL
H1
H2
H1TOG12POL
HBLKTOG2
HBLKTOG3
HBLKTOG4
HBLKTOG1
Figure 29. Example of Horizontal HMASK Masking
–34–
REV. 0
AD9937
HMASK
HBLK
HMASK
VERTICAL HMASK
HBLK
0
234
0
131
132
133
134
135
154
155
156
233
1
2
1559 1560
1
2
3
4
H1TOG34POL
H1MASKPOL
H1
H2
H1TOG12POL
HBLKTOG2
HDLEN
HDLASTLEN
HBLKTOG1
Figure 30. Example of Vertical HMASK Masking with HDLASTLEN > HDLEN with HMASTKSTART = 0 and HMASKSTOP = 1560
VERTICAL TIMING GENERATION
CCD REGIONS
The AD9937 provides a very flexible solution for generating
vertical CCD timing, and can support multiple CCDs and differ-
ent system architectures. The 4-phase vertical transfer clocks
V1–V4 are used to shift each line of pixels into the horizontal
output register of the CCD. The AD9937 allows these outputs
to be individually programmed into different pulse patterns.
Vertical sequence control registers then organize the individual
vertical pulses into the desired CCD vertical timing arrangement.
Up to five unique CCD regions can be preprogrammed using the
sequence change position registers as described in Table XVII.
The SCPx (x = 0, 1, 2, 3, 4) registers determine when the set-
tings in Mode_Reg(15–19) are active. For example, the SCP1
register activates the registers at Mode_Reg(16) for CCD region 1.
Note that SCP0 is not programmable. The SCP0 position always
starts at Line 0, as shown in Figure 31.
SCP0
(FIXED AT LINE 0)
The AD9937 can preprogram three unique sets of vertical transfer
pulses known as VTP0, VTP1, and VTP2. Each VTP set consists
of the four vertical clocks (V1A/B, V2, V3A/B, and V4), as shown
in Figure 32. Once preprogrammed, any one of the three unique
VTP sets can then be selected to be output in any one of the
five CCD regions by using the VTPPATSELx (x = 0, 1, 2, 3, 4)
registers. The VTP_Reg(1–9) registers listed in Table II are used
for generating the VTP pulse sets.
CCD REGION 0
REGISTERS LOCATED AT MODE_REG(15)
ARE ACTIVE WHILE
OPERATING IN CCD REGION 0
SCP1 [7:0]
CCD REGION 1
REGISTERS LOCATED AT MODE_REG(16)
ARE ACTIVE WHILE
OPERATING IN CCD REGION 1
SCP2 [7:0]
CCD REGION 2
Figure 32 shows an example of programming one VTPx (x = 0, 1, 2)
pulse set. Once a VTP pulse set has been configured, multiple
repetitions of this set can be repeated to create an entire VTP
sequence. This is accomplished by using the VTPREPn
(n = 0, 1, 2, 3, 4) registers where n represents the five CCD regions.
An example of repeating a VTP set is shown in Figure 33.
REGISTERS LOCATED AT MODE_REG(17)
ARE ACTIVE WHILE
OPERATING IN CCD REGION 2
SCP3 [7:0]
CCD REGION 3
REGISTERS LOCATED AT MODE_REG(18)
ARE ACTIVE WHILE
OPERATING IN CCD REGION 3
SCP4 [7:0]
CCD REGION 4
REGISTERS LOCATED AT MODE_REG(19)
ARE ACTIVE WHILE
OPERATING IN CCD REGION 4
Figure 31. Sequence Change Positions
Table XVII. Sequence Change Positions Registers
Register
Length
(Bits)
Register Name*
Type
Range
Description
SCP1
SCP2
SCP3
SCP4
8
8
8
8
Mode_Reg(14)
Mode_Reg(14)
Mode_Reg(14)
Mode_Reg(14)
0–255 Line Positions
0–255 Line Positions
0–255 Line Positions
0–255 Line Positions
Sequence Change Position 1
Sequence Change Position 2
Sequence Change Position 3
Sequence Change Position 4
*There is no SCP0 register. The SCP0 position is always fixed at Line 0.
REV. 0
–35–
AD9937
12-BIT
HD COUNTER
V1A/B
6
1
2
5
7
8
V2
V3A/B
V4
3
4
10
9
11
12
VTPLEN_x*
PROGRAMMING NOTES
*(x = 0, 1, 2)THE x REPRESENTSTHETHREE SEPARATE REGISTERS FOR VTP0, VTP1, AND VTP2 SETS.THIS ALSO APPLIESTOTHE x
USED INTHE PROGRAMMABLE CLOCK POSITIONS BELOW.
PROGRAMMABLE CLOCK POSITIONS
1. V1POL_x (PROGRAMMABLE AT VTP_REG(x))
2. V2POL_x (PROGRAMMABLE AT VTP_REG(x))
3. V3POL_x (PROGRAMMABLE AT VTP_REG(x))
4. V4POL_x (PROGRAMMABLE AT VTP_REG(x))
5. V1TOG1_x (PROGRAMMABLE AT VTP_REG(x))
6. V1TOG2_x (PROGRAMMABLE AT VTP_REG(x))
7. V2TOG1_x (PROGRAMMABLE AT VTP_REG(x))
8. V2TOG2_x (PROGRAMMABLE AT VTP_REG(x))
9. V3TOG1_x (PROGRAMMABLE AT VTP_REG(x))
10. V3TOG2_x (PROGRAMMABLE AT VTP_REG(x))
11. V4TOG1_x (PROGRAMMABLE AT VTP_REG(x))
12. V4TOG2_x (PROGRAMMABLE AT VTP_REG(x))
Figure 32. Example of Programming One VTP Pulse
VTPREPn* = 2
12-BIT
HD COUNTER
V1A/B
V2
75
250
355
530
40
145
320
425
110
215
390
495
V3A/B
V4
5
180
285
460
VTPLEN_x
*(n = 0, 1, 2, 3, 4) n REPRESENTSTHE NUMBER OF PROGRAMMABLE CCD REGIONS.THE NUMBER OF REPETITIONS IN EACH
CCD REGION CAN BE INDEPENDENTLY SET USINGTHE VTPREP REGISTER FORTHAT REGION.
Figure 33. Example of Creating a Sequence of VTP Pulses by Using the VTPREP Register
–36–
REV. 0
AD9937
12-BIT
HD COUNTER
VTPLEN_0
VTPLEN_1
VTPLEN_2
V1A/B
V2
V3A/B
V4
VTP0
VTP1
VTP2
Figure 34. Example of Three Preprogrammed VTP Pulses
SCP0
(FIXED AT LINE 0)
SCP1 = 1
11-BIT
VD COUNTER
000
001
002
N
12-BIT
HD COUNTER
VD
HD
V1A/B
V2
V3A/B
V4
VTPPATSEL0 = 1
VREP0 = 1
VTPPATSEL1 = 0
VREP1 = 1
Figure 35. Example of Applying VTP Pulse Sequences to CCD Regions
REV. 0
–37–
AD9937
SCP0
(FIXED AT LINE 0)
SCP1 = 1
11-BIT
VD COUNTER
000
001
002
N
12-BIT
HD COUNTER
VD
HD
V1A/B
V2
V3A/B
V4
VTPPATSEL0 = 1
VREP0 = 1
VTPPATSEL1 = 0
VREP1 = 2
Figure 36. Example of VTP Pulse Sequence with VREP = 2 in CCD Region 1
–38–
REV. 0
AD9937
VDD
(INPUT)
1
1
tPWR
INTERNAL
POWER-ON
AUTO-RESET
(LO-ACTIVE)
2
VCKM
4
5
6
7
SERIAL
WRITES
OUTCONT
(REGISTER
CONTROLLED)
1V
VD
(OUTPUT)
ODD FIELD
EVEN FIELD
ODD FIELD
1H
HD
(OUTPUT)
V1A/B, V2, V3A/B, V4, TG1A, TG1B, TG3A, TG3B,
OFD, H1(A, B, C, D)
DIGITAL
OUTPUTS
RS, H2(A, B), LM
2
3
tSETTINGS
tDELAY
VCLK
NOTES
1
THE INTERNAL POWER-ON AUTO RESET TIME tPWR = 1.0ms REGARDLESS OF THE VCLK CLOCK FREQUENCY.
2
IT TAKES 500ꢂs FOR VCLK TO SETTLE ONCE THE DIG_STBY REGISTER HAS BEEN PROGRAMMED.
3
IT TAKES FOUR VCKM CLOCK CYCLES FROM WHEN OUTCONT IS ASSERTED HIGH UNTIL THE VD, HD, AND DIGITAL OUTPUT DATA IS VALID.
Figure 37. Recommended Power-Up Sequence
Table XVIII. Start-Up Polarities
(While OUTCONT = LO)
POWER-UP FOR MASTER MODE
When the AD9937 is powered up, the following sequence is
recommended. (Refer to Figure 37 for each step.)
Output
OUTCONT = LO
1. Turn on power supplies for AD9937.
V1A/B
V2
V3A/B
V4
TG1A
TG1B
TG3A
TG3B
OFD
H1(A–D)
H2(A, B)
LM
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
LO
2. The internal power-on auto-reset circuit will deassert
1.0 ms after VDD settles. (All internal registers are reset to
the default values.)
3. The VCKM clock can be applied as soon as VDD settles.
4. Reset the internal AD9937 registers: write a 0x000000 to
the SW_RESET register (addr 0x00). This will set all inter-
nal register values to their default values. (This step is optional
because the internal power-on reset circuit is applied at
power-up.)
5. Write a 1 to the DIG_STBY and AFE_STBY registers
(addr 0x02). This will put the digital and analog circuits into
the normal operating mode.
6. Program all control, system, and mode registers.
7. Write a 1 to the OUTCONT_REG (addr 0x01). This will put
the digital outputs into the normal operating mode. The inter-
nal OUTCONT will be asserted high on the rising edge of the
32nd SCK clock when writing to the OUTCONT_REG.
RS
REV. 0
–39–
AD9937
VDD
(INPUT)
3
VCKM
1
2
5
6
7
SERIAL
WRITES
OUTCONT
(INTERNAL
SIGNAL)
VD
(OUTPUT)
HD
(OUTPUT)
V1A/B, V2, V3A/B, V4, TG1A, TG1B, TG3A, TG3B,
OFD, H1(A, B, C, D)
DIGITAL
OUTPUTS
RS, H2(A, B), LM
tDELAY
*
AFE_STBY
(REGISTER)
DIG_STBY
(REGISTER)
*IT TAKES 4 VCKM CLOCK CYCLES FROM WHEN OUTCONT GOES HIGH UNTIL VD, HD AND DIGITAL
OUTPUT DATA IS VALID.
Figure 38. Recommended Standby Sequence
STANDBY SEQUENCE
3. Stop VCKM clock. (This is optional.)
The following sequence is recommended when the AD9937 is
put into standby operation. (Refer to Figure 38 for each step.)
4. Apply VCKM when ready to come out of standby operation.
5. Write a 1 to the DIG_STBY and AFE_STBY registers
(addr 0x02). This will put the digital and analog circuits into
the normal operating mode.
6. Program any necessary control, system, or mode registers.
7. Write a 1 to the OUTCONT_REG register (addr 0x01) to
begin operation.
1. Write a 0 to the OUTCONT_REG register (addr 0x01).
2. Write a 0 to the DIG_STBY and AFE_STBY registers
(addr 0x02). This will put the digital and analog circuits into
the standby operating mode.
–40–
REV. 0
AD9937
POWER-DOWN SEQUENCE
The following sequence is recommended when AD9937 is being
powered down. (Refer to Figure 39 for each step.)
2. Write a 0 to the DIG_STBY and AFE_STBY registers
(addr 0x02). This will put the digital and analog circuits into
the standby operating mode.
3. Stop VCKM clock.
4. Turn off power supplies to AD9937.
1. Write a 0 to the OUTCONT_REG register (addr 0x01).
4
VDD
(INPUT)
3
VCKM
SERIAL
WRITES
OUTCONT
(INTERNAL)
VD
(OUTPUT)
ODD FIELD
EVEN FIELD
ODD FIELD
HD
(OUTPUT)
V1A/B, V2, V3A/B, V4, TG1A, TG1B, TG3A, TG3B,
OFD, H1(A, B, C, D)
DIGITAL
OUTPUTS
RS, H2(A, B), LM
VCLK
AFE_STBY
(REGISTER)
DIG_STBY
(REGISTER)
Figure 39. Recommended Power-Down Sequence
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 9
CCD
SIGNAL
N
N + 7
N + 8
N + 10
N + 11
tID
tID
SHP
SHD
tS2
tS1
tCP
CYCLE 1
CYCLE 2
CYCLE 3
CYCLE 4
CYCLE 5
CYCLE 6
CYCLE 7
CYCLE 8
CYCLE 9
VCKM
tOD
OUTPUT
DATA
N – 10
N – 9
N – 8
N – 7
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
NOTES
1. RECOMMENDED PLACEMENT FOR VCKM RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
3. OUTPUT DATA LATENCY IS NINE VCKM CYCLES.
Figure 40. Pipeline Latency
–41–
REV. 0
AD9937
CIRCUIT LAYOUT INFORMATION
The analog bypass pins (REFB, REFT) should also be carefully
decoupled to ground as close as possible to their respective pins.
The analog input (CCDIN) capacitor should also be located
close to the pin.
The AD9937 typical circuit connection is shown in Figure 41.
The PCB layout is critical in achieving good image quality from
the AD9937 product. All of the supply pins, particularly the
AVDD, DVDD, TCVDD, RSVDD, HVDD1, and HVDD2
supplies, must be decoupled to ground with good quality high
frequency chip capacitors. The decoupling capacitors should be
located as close as possible to the supply pins, and should have
a very low impedance path to a continuous ground plane. There
should also be a 4.7 µF or larger value bypass capacitor for each
main supply although this is not necessary for each individual pin.
The H1(A–D), H2(A, B), and RS printed circuit board traces
should be designed to have low inductance to avoid excessive distor-
tion of the signals. Heavier traces are recommended, because of
the large transient current demand on H1(A–D) and H2(A, B) by
the CCD. If possible, physically locate the AD9937 closer to the
CCD to reduce the inductance on these lines. As always, the rout-
ing path should be as direct as possible from the AD9937 to the
CCD. Careful trace impedance considerations must also be made
with applications using a flex printed circuit (FPC) connecting the
CCD to the AD9937. FPC trace impedances can be controlled
by applying a solid uniform ground plane under the H1(A–D),
H2(A, B), and RS traces. This helps minimize the amount of
overshoot and ringing on these signals at the CCD inputs.
In most applications, it is easier and recommended to share the
same supply for AVDD, DVDD, TCVDD, RSVDD, HVDD1,
and HVDD2, which may be done as long as the individual supply
pins are separately bypassed at each supply pin. A separate 3 V
supply should be used for DRVDD with this supply pin decoupled
to the same ground plane as the rest of the chip. A separate
ground for DRVSS is not recommended.
0.1ꢂF
3V
ANALOG SUPPLY
2
VD, HD
OFD, LM, V4, TG3B, V3A/B,
TG3A, V2, TG1B, V1A/B, TG1A,
TO V-DRIVER
8
3
SERIAL
INTERFACE
56 55 54 53 52 51 50 49 48 47 46 45 44 43
TG1B
V1A/B
TG1A
REFB
REFT 1.0ꢂF
AVSS
NC
NC
42
41
40
1
2
PIN 1
IDENTIFIER
D0
D1
3
1.0ꢂF
39
38
37
36
35
34
33
32
31
4
D2
5
D3
AD9937
6
0.1ꢂF
CCDIN
AVDD
VCKM
TCVDD
DRVSS
DRVDD
D4
CCD SIGNAL
7
3V
DRIVER
SUPPLY
TOP VIEW
(Not to Scale)
4.7ꢂF
0.1ꢂF
3V ANALOG SUPPLY
8
REF CLOCK INPUT
9
0.1ꢂF
D5
10
11
12
13
14
0.1ꢂF
TCVSS
D6
NC
NC
NC
D7
3V ANALOG SUPPLY
D8
30
29
4.7ꢂF
D9
10
DATA
OUTPUTS
15 16 17 18 19 20 21 22 23 24 25 26 27 28
RS
H1D, H2B, H1B, H1C, H2A, H1A
6
DATA OUTPUT CLOCK
0.1ꢂF
0.1ꢂF
0.1ꢂF
3V ANALOG SUPPLY
Figure 41. Typical Circuit Configuration
–42–
REV. 0
AD9937
Figures 42 and 43 show the recommended AD9937 supply group-
ing. Figure 42 shows how the supplies should be tied together when
there are only two available supply sources, whereas Figure 43
shows how the supplies can be tied together when there are three
available supply sources. In either case, all grounds should be
tied together as shown.
Also as shown in Figures 42 and 43 is that the AD9937 DRVDD
supply can be shared with the system ASIC/DSP.
AD9937
3V ANALOG
SUPPLY
AVDD
AVSS
TCVSS
HVSS1
HVSS2
RSVSS
DVSS
TCVDD
HVDD1
HVDD2
RSVDD
DVDD
3V DRIVER
SUPPLY
DRVDD
DRVSS
ASIC/DSP
Figure 42. Recommended Supply Grouping with Two Available Supply Sources
3V ANALOG
SUPPLY 1
AD9937
AVDD
AVSS
TCVSS
DVSS
HVSS1
HVSS2
RSVSS
TCVDD
DVDD
HVDD1
HVDD2
RSVDD
3V ANALOG
SUPPLY 2
3V DRIVER
SUPPLY
DRVDD
DRVSS
ASIC/DSP
Figure 43. Recommended Supply Grouping with Three Available Supply Sources
REV. 0
–43–
AD9937
OUTLINE DIMENSIONS
56-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-56)
Dimensions shown in millimeters
0.30
8.00
BSC SQ
0.23
0.18
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
43
56
1
42
PIN 1
INDICATOR
6.25
6.10 SQ
5.95
7.75
BSC SQ
BOTTOM
VIEW
TOP
VIEW
0.50
0.40
0.30
29
28
14
15
0.25 MIN
6.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12ꢀ MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
–44–
REV. 0
相关型号：
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