AD9941BSTZRL [ADI]
Complete 14-Bit, 56 MSPS Imaging Signal Processor;
| 型号： | AD9941BSTZRL |
| 厂家： | 
ADI |
| 描述： | Complete 14-Bit, 56 MSPS Imaging Signal Processor 商用集成电路 |
| 文件： | 总16页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete 14-Bit, 56 MSPS
Imaging Signal Processor
AD9941
FEATURES
GENERAL DESCRIPTION
Differential sensor input with 1 V p-p input range
0 dB/6 dB variable gain amplifier (VGA)
Low noise optical black clamp circuit
14-bit, 56 MSPS analog-to-digital converter (ADC)
No missing codes guaranteed
3-wire serial digital interface
3 V single-supply operation
Low power CMOS: 145 mW @ 3.0 V, 56 MHz
48-lead LQFP package
The AD9941 is a complete analog signal processor for imaging
applications that do not require correlated double sampling
(CDS). It is also suitable for processing the output signal from
the AD9940 CDS front end product. It features a 56 MHz, single-
channel architecture designed to sample and condition the output
of CMOS imagers and CCD arrays already containing on-chip
CDS. The AD9941 signal chain consists of a differential input
sample-and-hold amplifier (SHA), a digitally controlled variable
gain amplifier (VGA), a black level clamp, and a 14-bit ADC.
The internal registers are programmed through a 3-wire serial
digital interface.
APPLICATIONS
Digital still cameras using CMOS imagers
Professional HDTV camcorders
Professional/high-end digital cameras
Broadcast cameras
The AD9941 operates from a single 3 V supply, typically
dissipates 145 mW, and is packaged in a 48-lead LQFP.
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS
REFT REFB
PBLK
AD9941
DRVDD
DRVSS
BAND GAP
REFERENCE
0dB, 6dB
VGA
VIN+
VIN–
14
14-BIT
ADC
DOUT
SHA
CLP
CLPOB
8
INTERNAL
REGISTERS
BLK CLAMP
LEVEL
DVDD
DVSS
DIGITAL
INTERFACE
SL
SCK
SDATA
ADCLK
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD9941
TABLE OF CONTENTS
Specifications .....................................................................................3
Equivalent Input/Output Circuits...................................................9
Serial Interface Timing...................................................................10
Circuit Description and Operation ..............................................12
Differential Input SHA...............................................................12
Variable Gain Amplifier.............................................................13
ADC..............................................................................................13
Optical Black Clamp...................................................................13
Applications Information...............................................................14
Outline Dimensions........................................................................16
Ordering Guide ...........................................................................16
Digital Specifications....................................................................3
Analog Specifications ...................................................................4
Timing Specifications...................................................................5
Timing Diagrams ..........................................................................5
Absolute Maximum Ratings ............................................................6
Thermal Characteristics...............................................................6
ESD Caution ..................................................................................6
Pin Configuration and Function Descriptions .............................7
Terminology .......................................................................................8
REVISION HISTORY
7/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD9941
SPECIFICATIONS
Table 1.
Parameter
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
−25
−65
+85
+150
°C
°C
POWER SUPPLY VOLTAGE
AVDD, DVDD, DRVDD
POWER DISSIPATION
Normal Operation—56 MHz, AVDD = DVDD = DRVDD = 3.0 V
Standby Mode
2.9
3.0
3.6
V
145
2
mW
mW
MHz
MAXIMUM CLOCK RATE
56
DIGITAL SPECIFICATIONS
DRVDD = 2.9 V, CL = 20 pF, unless otherwise noted.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.1
V
V
μA
μA
pF
0.6
10
10
10
LOGIC OUTPUTS
High Level Output Voltage , IOH = 2 mA
Low Level Output Voltage , IOL = 2 mA
VOH
VOL
2.2
V
V
0.5
Rev. 0 | Page 3 of 16
AD9941
ANALOG SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD, fADCLK = 56 MHz, unless otherwise noted.
Table 3.
Parameter
Min
Typ
Max
Unit
Notes
ANALOG INPUTS (VIN+, VIN−)
Input Common-Mode Range1
Maximum Input Amplitude1
Maximum Differential Input Amplitude1
OB Correction Range
Gain 1 (6 dB)1
1.1
1.0
2.0
2.3
V
V p-p
V p-p
Linear operating range for VIN+, VIN−
VIN+ and VIN− signal swing
Defined as VIN+ − VIN−
OB offset shown in Note 1
90
180
mV
mV
Gain 2 (0 dB)1
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Range
2
Steps
CCD Mode Gain 1
CCD Mode Gain 2
5.0
−0.5
5.5
0
6.0
+0.5
dB
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
256
Steps
Clamp level = 4 × REFBLK
Minimum Clamp Level (Code 0)
Maximum Clamp Level (Code 255)
A/D CONVERTER
0
1020
LSB
LSB
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
14
Bits
LSB
0.5
Guaranteed
Integral Nonlinearity
0.3
2.0
% FS
V p-p
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
2.0
1.0
V
V
1 Input signal characteristics defined as
2.3V
VIN–
1V p-p MAX INPUT SIGNAL SWING, VIN+ AND VIN–
2V p-p MAX DIFFERENTIAL SIGNAL, VIN+ – VIN–
BLACK
LEVEL
WHITE
LEVEL
VIN+
GND
1.1V
MAX OB OFFSET
Rev. 0 | Page 4 of 16
AD9941
TIMING SPECIFICATIONS
CL = 20 pF, fADCLK = 56 MHz, refer to Figure 2 and Figure 8.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
SAMPLE CLOCKS
ADCLK Clock Period
ADCLK High/Low Pulse Width
CLPOB Pulse Width
Internal Clock Delay
DATA OUTPUTS
18
ns
ns
Pixels
ns
8
20
3
TID
Output Delay
Output Hold Time
TOD
TH
20
ns
ns
5
Pipeline Delay
9
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Rising Edge to SDATA Valid Hold
fSCLK
tLS
tLH
tDS
tDH
10
10
10
10
10
MHz
ns
ns
ns
ns
TIMING DIAGRAMS
N + 9
N
N + 1
VIN–
N + 2
N + 8
VIN+
tID
tCONV
ADCLK
tOD
tH
OUTPUT
DATA
N – 10
N – 9
N – 8
N – 1
N
NOTES
1. VIN+ AND VIN– SIGNALS ARE SAMPLED AT ADCLK RISING EDGES (CAN BE INVERTED USING THE ADCPOL REGISTER).
2. INTERNAL SAMPLING DELAY (APERTURE) t IS TYPICALLY 3ns.
ID
3. OUTPUT DATA LATENCY IS NINE ADCLK CYCLES.
Figure 2. Input/Output Data Timing
HORIZONTAL
BLANKING
EFFECTIVE PIXELS
OPTICAL BLACK PIXELS
EFFECTIVE PIXELS
IMAGER
SIGNAL
CLPOB
PBLK
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
EFFECTIVE DATA
NOTES
1. CLPOB OVERWRITES PBLK. PBLK DOES NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUPUT DATA IS ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE ADCLK CYCLES.
Figure 3. Typical Imager Timing
Rev. 0 | Page 5 of 16
AD9941
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Stresses above those listed under Absolute Maximum Ratings
Rating
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
REFT, REFB
VIN+, VIN−
ADCLK, RST, SL, SDI, SCK
AVDD to AVSS
DVDD and DRVDD to DVSS
and DRVSS
AVSS − 0.3 V to AVDD + 0.3 V
AVSS − 0.3 V to AVDD + 0.3 V
DVSS − 0.3 V to DVDD + 0.3 V
−0.3 V to + 3.9 V
−0.3 V to +3.9 V
Any VSS to Any VSS
Digital Outputs to DRVSS
CLPOB/PBLK to DVSS
−0.3 V to +0.3 V
THERMAL CHARACTERISTICS
−0.3 V to DRVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
Thermal resistance for the 48-lead LQFP package:
SCK, SL, and SDATA to DVSS
θJA = 92°C/W1
1
θJA is measured using a 4-layer PCB.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 16
AD9941
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
D2
NC
PIN 1
2
3
D3
D4
AVSS
NC
4
D5
AVDD
NC
5
D6
AD9941
TOP VIEW
(Not to Scale)
6
D7
VIN–
VIN+
NC
7
D8
8
D9
9
D10
D11
D12
D13
NC
10
11
12
NC
NC
NC
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1 to 12
13
14
15
Mnemonic
D2 to D13
DRVDD
DRVSS
DVSS
Type
DO
P
P
P
Description
Digital Data Outputs
Digital Output Driver Supply
Digital Output Ground
Digital Ground
16
17
ADCLK
DVDD
DI
P
Digital Data Output Clock
Digital Supply
18, 21 to 29, 32,
34, 36, 40, 41
NC
NC
No Connection (tie to VDD or GND)
19
20
30
31
33
35
37
38
39
42
43
44
45
46
47
48
PBLK
CLPOB
VIN+
VIN−
AVDD
AVSS
DVSS
REFT
REFB
DVSS
RST
SDATA
SCK
SL
D0
D1
DI
DI
AI
AI
P
Preblanking Clock Input (internal 50 kΩ pull-up)
Black Level Clamp Clock Input
Positive Data Input
Negative Data Input
Analog Supply
P
P
Analog Ground (GND)
Digital Ground
AO
AO
P
DI
DI
DI
DI
DO
DO
ADC Reference Voltage Top (bypass to GND with a 0.1 μF capacitor)
ADC Reference Voltage Bottom (bypass to GND with a 0.1 μF capacitor)
Digital Ground
Reset Control for Internal Registers (active low)
Serial Data Input Signal
Serial Clock
Serial Load Enable
Digital Data Output
Digital Data Output
Rev. 0 | Page 7 of 16
AD9941
TERMINOLOGY
Differential Nonlinearity (DNL)
Total Output Noise
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value; therefore, every
code must have a finite width. No missing codes guaranteed to
14-bit resolution indicates that all 16,384 codes must be present
over all operating conditions.
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
Peak Nonlinearity
1 LSB = (ADC full scale/2n codes)
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9941 from a true straight
line. The point used as zero scale occurs 0.5 LSB before the first
code transition. Positive full scale is defined as a level 1 LSB and
0.5 LSB beyond the last code transition. The deviation is measured
from the middle of each output code to the true straight line. The
error is then expressed as a percentage of the 2 V ADC full-scale
signal. The input signal is always appropriately gained up to fill
the ADC’s full-scale range.
where n is the bit resolution of the ADC, and 1 LSB is
approximately 122 μV.
Internal Delay for SHA
The internal delay, or aperture delay, is the time delay from
when the sampling edge is applied to the AD9941 to when the
actual sample of the input signal is held. The ADCLK samples
the input signal during the transition from low to high; therefore,
the internal delay is measured from each clock’s rising edge to
the instant the actual sample is taken.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
Rev. 0 | Page 8 of 16
AD9941
EQUIVALENT INPUT/OUTPUT CIRCUITS
DVDD
AVDD
330Ω
60Ω
DVSS
AVSS
AVSS
Figure 5. Digital Inputs—ADCLK, CLPOB, PBLK, SCK, SDATA, SL, RST
Figure 7. VIN+, VIN−
DVSS
DRVDD
DATA
THREE-STATE
DOUT
DVSS
DRVSS
Figure 6. Data Outputs—D0 to D13
Rev. 0 | Page 9 of 16
AD9941
SERIAL INTERFACE TIMING
All of the internal registers of the AD9941 are accessed through
a 3-wire serial interface. Each register consists of an 8-bit data
byte, starting with the LSB bit. As shown in Figure 8, the data
bits are clocked in on the rising edge of SCK after SL is asserted
low, and the entire 8-bit word is latched in on the rising edge of
SL after the last MSB bit. Consecutive serial writes are performed
starting with Address 00 and ending with an address MSB bit
prior to asserting SL high.
Note that Address 00 must be written at the start of any write
operation to specify the PARTSEL bit. The LSB of Address 00
(PARTSEL) must be set high to write to the AD9941 registers.
A hard reset is recommended after power-up to reset the
AD9941 prior to performing a serial interface write. A hard
reset is performed by asserting the RST pin low for a minimum
of 10 μs. The serial interface pins SCK, SL, and SDI must be in a
known state after the RST has been applied.
ADDR 00
ADDR 01
ADDR N
ADDR N + 1
...
...
...
...
SDATA
D7 D0 D1
D3
D7
D1 D2 D3
D3
D7 D0 D1
D3
D7
D0
D2
D0
D2
D2
D1
tDS
tDH
...
...
...
...
SCK
SL
tLS
tLH
...
NOTES
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWER ADDRESS 00.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED
FOR EACH REGISTER.
3. ALL LOADED REGISTERS ARE SIMULTANEOUSLY UPDATED ON THE RISING EDGE OF SL.
Figure 8. Consecutive Serial Write Interface Timing
Rev. 0 | Page 10 of 16
AD9941
Table 7. Serial Interface Registers
Address
Data Bit Content
Default Value
Name
Description
00
[0]
[2:1]
1
1
PARTSEL
OPERATION MODE
1 = select AD9941, 0 = select AD9940
0 = standby mode
1 = 6 dB VGA gain mode
2 = test mode
3 = 0 dB VGA gain mode
Always set to 0
0 = ADCLK rising edge update
1 = ADCLK falling edge update
0 = fast clamp off
[3]
[4]
0
0
TESTMODE
ADCPOL
[5]
0
CLPMODE
1 = fast clamp on (the OB loop time constant is reduced by half)
Always set to 0
0 = normal operation, 1 = data outputs are three-state
Always set to 0
0 = OB clamp enabled, 1= OB clamp disabled
Always set to 0
[6]
[7]
0
0
0
TESTMODE
DOUT DISABLE
TESTMODE
CLPDISABLE
TESTMODE
01
[5:0]
[6]
[7]
02
03
04
05
[7:0]
[7:0]
[7:0]
[0]
0
0
0
0
TESTMODE
Always set to 72
TESTMODE
Always set to 99
TESTMODE
Always set to 16
CLPLEVEL ENABLE
0 = disable CLAMPLEVEL register, clamp level fixed at 492 LSB
1 = enable CLAMPLEVEL register, clamp level is set to value in
Register Value 06 CLAMPLEVEL
[1]
0
CLPUPDATE
0 = ignore new value in CLAMPLEVEL register
1 = update new clamp level value with CLAMPLEVEL register
Always set to 0
[7:2]
[7:0]
0
0
TESTMODE
06
CLAMPLEVEL
OB clamp level (0 = 0 LSB, 123 = 492, 255 = 1020 LSB)
Clamp level (LSB) = 4 × REFBLK
Rev. 0 | Page 11 of 16
AD9941
CIRCUIT DESCRIPTION AND OPERATION
both VIN+ and VIN− signals simultaneously. The imager’s
The AD9941 signal processing chain is shown in Figure 9. Each
processing step is essential in achieving a high quality image
from the raw data of the imager.
signal is sampled on the rising edge of ADCLK. Placement of
this clock signal is critical in achieving the best performance
from the imager. An internal ADCLK delay (tID) of 3 ns is caused
by internal propagation delays.
DIFFERENTIAL INPUT SHA
The differential input SHA circuit is designed to accommodate
a variety of image sensor output voltages. The timing shown in
Figure 2 illustrates how the ADCLK signal is used to sample
0.1μF 0.1μF
ADCLK
REFB
REFT
1.0V 2.0V
AD9941
INTERNAL
V
REF
PBLK
0dB, 6dB
VIN+
VIN–
14
14-BIT
ADC
SHA
VGA
DOUT
OPTICAL BLACK
CLAMP
CLPOB
8-BIT
DAC
OPERATION
MODE
REGISTER
DIGITAL
FILTER
8
CLAMP LEVEL
REGISTER
Figure 9. Internal Block Diagram
Rev. 0 | Page 12 of 16
AD9941
VARIABLE GAIN AMPLIFIER
OPTICAL BLACK CLAMP
The VGA stage can be programmed to either 0 dB or 6 dB using
the OPERATION MODE register. The 6 dB gain setting is needed
to match a 1 V input signal with the ADC full-scale range of 2 V.
The 0 dB gain setting can be used with the AD9940 CDS front
end component, which has a 2 V differential output range. Note
that the OB correction range is different for each gain setting, as
outlined in Table 3.
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
imager’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the CLAMPLEVEL
register. The value can be programmed between 0 LSB and
1020 LSB in 256 steps. The resulting error signal is filtered to
reduce noise, and the correction value is applied to the ADC
input through a digital-to-analog converter. Normally, the
optical black clamp loop is turned on once per horizontal line,
but this loop can be updated more slowly to suit a particular
application. If external digital clamping is used during the
postprocessing, the AD9941 optical black clamping can be
disabled using the CLPDISABLE register.
ADC
The AD9941 uses a high performance ADC architecture,
optimized for high speed and low power. Differential
nonlinearity (DNL) performance is typically better than
0.5 LSB. The ADC uses a 2 V input range.
The CLPOB pulse should be placed during the imager’s optical
black pixels. It is recommended that the CLPOB pulse duration
be at least 20 pixels wide to minimize clamp noise. Shorter pulse
widths can be used, but clamp noise may increase and the
ability to track low frequency variations in the black level will
be reduced.
Rev. 0 | Page 13 of 16
AD9941
APPLICATIONS INFORMATION
Careful placement of a split in the ground plane on the board
All signals should be carefully routed on the PCB to maintain
low noise performance. The clock inputs are located on the
package side opposite the analog pins and should be connected
to the digital ASIC. A single ground plane is recommended for
the AD9941. This ground plane should be as continuous as
possible, particularly where analog pins are concentrated. This
ensures that all analog decoupling capacitors provide the lowest
possible impedance path between the power and bypass pins
and their respective ground pins. All decoupling capacitors
should be located as close as possible to the package pins.
can help prevent the return current of the horizontal driver
from flowing into the analog ground, thereby reducing digital-
to-analog coupling noise. Power supply decoupling is very
important for achieving low noise performance. Figure 11
shows the local high frequency decoupling capacitors, but
additional capacitance is recommended for lower frequencies.
Additional capacitors and ferrite beads can further reduce noise.
CMOS
OR
CCD
AD9941
DIGITAL
OUTPUTS
OUT+
OUT–
VIN+
VIN–
DIGITAL IMAGE
PROCESSING
ASIC
ADC
OUT
IMAGER
SERIAL
INTERFACE
REGISTER-
DATA
(MAY ALSO
INCLUDE TG)
BUFFER
OR
LEVEL SHIFT
ADCLK/CLAMP
TIMING
V-DRIVER
(CCD)
IMAGER
TIMING
TIMING
GENERATOR
Figure 10. System Application Diagram
Rev. 0 | Page 14 of 16
AD9941
RST
3
SERIAL
INTERFACE
0.1μF
0.1μF
48 47 46 45 44 43 42 41 40 39 38 37
NC
D2
D3
D4
D5
D6
D7
D8
D9
1
36
35
34
33
32
31
30
29
28
27
26
25
AVSS
NC
PIN 1
2
3
0.1μF
3V
AVDD
NC
4
ANALOG
SUPPLY
5
AD9941
TOP VIEW
(Not to Scale)
VIN–
VIN+
NC
6
VIN– INPUT
VIN+ INPUT
7
8
NC
D10
D11
D12
D13
9
NC
10
11
12
NC
NC
14
DATA
OUTPUTS
13 14 15 16 17 18 19 20 21 22 23 24
3
CLOCK
INPUTS
3V
3V
DRIVER
SUPPLY
ANALOG
SUPPLY
0.1μF
0.1μF
Figure 11. Recommended Circuit Configuration
Rev. 0 | Page 15 of 16
AD9941
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.00
BSC SQ
1.60
MAX
37
48
36
1
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
12
0.15
0.05
13
24
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 12. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9941BSTZ1
AD9941BSTZRL1
−25°C to +85°C
−25°C to +85°C
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
ST-48
ST-48
1 Z = Pb-free part.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05504–0–7/05(0)
Rev. 0 | Page 16 of 16
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