AD9944KCPZRL [ADI]
Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors; 完整的10位和12位， 25 MHz的CCD信号处理器
| 型号： | AD9944KCPZRL |
| 厂家： | 
ADI |
| 描述： | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| 文件： | 总20页 (文件大小：672K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete 10-Bit and 12-Bit, 25 MHz
CCD Signal Processors
AD9943/AD9944
FEATURES
GENERAL DESCRIPTION
25 MSPS correlated double sampler (CDS)
6 dB to 40 dB 10-bit variable gain amplifier (VGA)
Low noise optical black clamp circuit
Preblanking function
10-bit (AD9943), 12-bit (AD9944) 25 MSPS A/D converter
No missing codes guaranteed
The AD9943/AD9944 are complete analog signal processors
for CCD applications. They feature a 25 MHz single-channel
architecture designed to sample and condition the outputs of
interlaced and progressive scan area CCD arrays. The signal
chain for the AD9943/AD9944 consists of a correlated double
sampler (CDS), a digitally controlled variable gain amplifier
(VGA), and a black level clamp. The AD9943 offers 10-bit
ADC resolution, while the AD9944 contains a true 12-bit ADC.
3-wire serial digital interface
3 V single-supply operation
Space-saving 32-lead 5 mm × 5 mm LFCSP package
The internal registers are programmed through a 3-wire
serial digital interface. Programmable features include gain
adjustment, black level adjustment, input clock polarity, and
power-down modes. The AD9943/AD9944 operate from a
single 3 V power supply, typically dissipate 79 mW, and are
packaged in space-saving 32-lead LFCSP packages.
APPLICATIONS
Digital still cameras
Digital video camcorders
PC cameras
Portable CCD imaging devices
CCTV cameras
FUNCTIONAL BLOCK DIAGRAM
REFT
REFB
PBLK
AD9943/AD9944
DRVDD
DRVSS
BAND GAP
REFERENCE
6dB–40dB
10/12
10-/12-BIT
ADC
CCDIN
DOUT
VGA
CDS
CLP
10
AVDD
AVSS
CLPOB
CONTROL
REGISTERS
DVDD
DVSS
DIGITAL
INTERFACE
INTERNAL
TIMING
SL
SCK
SDATA
SHP
SHD DATACLK
Figure 1. Functional Block Diagram
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD9943/AD9944
TABLE OF CONTENTS
AD9943/AD9944 Specifications..................................................... 3
Internal Register Map .................................................................... 13
Serial Interface ................................................................................ 14
Circuit Description and Operation.............................................. 15
DC Restore .................................................................................. 15
Correlated Double Sampler ...................................................... 15
Optical Black Clamp .................................................................. 15
A/D Converter............................................................................ 16
Variable Gain Amplifier ............................................................ 16
CCD Mode Timing ........................................................................ 17
Applications Information.............................................................. 18
Internal Power-On Reset Circuitry.......................................... 19
Grounding and Decoupling Recommendations.................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
General Specifications ................................................................. 3
Digital Specifications ................................................................... 3
AD9943 System Specifications ....................................................... 4
AD9944 System Specifications ....................................................... 5
Timing Specifications....................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Characteristics .............................................................. 7
ESD Caution.................................................................................. 7
AD9943 Pin Configuration and Function Descriptions ............. 8
AD9944 Pin Configuration and Function Descriptions ............. 9
Terminology .................................................................................... 10
Equivalent Input Circuits .............................................................. 11
Typical Performance Characteristics ........................................... 12
REVISION HISTORY
5/04—Data Sheet Changed from Rev. A to Rev. B
Updated Format..................................................................Universal
Updated Outline Dimensions....................................................... 20
Changes to Ordering Guide .......................................................... 20
5/03—Data Sheet changed from Rev. 0 to Rev. A
Added AD9944....................................................................Universal
Changes to Features Section............................................................ 1
Updated Ordering Guide................................................................. 5
Replaced TPC 3................................................................................. 9
Added Figure 12.............................................................................. 15
Updated Outline Dimensions....................................................... 16
Rev. B | Page 2 of 20
AD9943/AD9944
AD9943/AD9944 SPECIFICATIONS
GENERAL SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 25 MHz, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
−20
−65
+85
+150
°C
°C
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver
POWER CONSUMPTION
Normal Operation
Power-Down Mode
MAXIMUM CLOCK RATE
2.7
3.6
V
79
150
mW
µW
25
MHz
DIGITAL SPECIFICATIONS
DRVDD = DVDD = 2.7 V, CL = 20 pF, unless otherwise noted.
Table 2.
Parameter
Symbol
Min
2.1
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
VIH
VIL
IIH
V
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
0.6
V
10
10
10
µA
µA
pF
IIL
CIN
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA
Low Level Output Voltage, IOL = 2 mA
VOH
VOL
2.2
V
V
0.5
Rev. B | Page 3 of 20
AD9943/AD9944
AD9943 SYSTEM SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 25 MHz, unless otherwise noted.
Table 3.
Parameter
Min Typ
Max Unit
Conditions
CDS
Maximum Input Range before Saturation1
1.0
500
100
V p-p
mV
mV
1
Allowable CCD Reset Transient
See input waveform in footnote.
1
Maximum CCD Black Pixel Amplitude
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
1024
Guaranteed
Steps
Minimum Gain
Maximum Gain
5.3
41.5
dB
dB
See Figure 13 for VGA gain curve.
See Variable Gain Amplifier section for VGA
gain equation.
40
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
256
Steps
Measured at ADC output.
Minimum Clamp Level
Maximum Clamp Level
A/D CONVERTER
0
LSB
LSB
63.75
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
10
Bits
LSB
0.3
Guaranteed
Straight binary
2.0
Data Output Coding
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
SYSTEM PERFORMANCE
Gain Range
V
2.0
1.0
V
V
Specifications include entire signal chain.
Low Gain (VGA Code = 0)
Maximum Gain (VGA Code = 1023)
Gain Accuracy
Peak Nonlinearity 500 mV Input Signal
Total Output Noise
5.3
41.5
1
0.1
0.3
50
dB
dB
dB
%
LSB rms
dB
40
12 dB gain applied.
AC grounded input, 6 dB gain applied.
Measured with step change on supply.
Power Supply Rejection (PSR)
1 Input signal characteristics defined as follows:
500mV TYP
RESET TRANSIENT
100mV TYP
1V TYP
INPUT SIGNAL RANGE
OPTICAL BLACK PIXEL
Rev. B | Page 4 of 20
AD9943/AD9944
AD9944 SYSTEM SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 25 MHz, unless otherwise noted.
Table 4.
Parameter
Min Typ
Max Unit
Conditions
CDS
Maximum Input Range before Saturation1
1.0
500
100
V p-p
mV
mV
1
Allowable CCD Reset Transient
See input waveform in footnote.
1
Maximum CCD Black Pixel Amplitude
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
1024
Guaranteed
Steps
Minimum Gain
Maximum Gain
5.3
41.5
dB
dB
See Figure 13 for VGA gain curve.
See Variable Gain Amplifier section for VGA
gain equation.
40
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
256
Steps
Measured at ADC output.
Minimum Clamp Level
Maximum Clamp Level
A/D CONVERTER
0
255
LSB
LSB
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
12
Bits
LSB
0.4
Guaranteed
Straight binary
2.0
Data Output Coding
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
SYSTEM PERFORMANCE
Gain Range
V
2.0
1.0
V
V
Specifications include entire signal chain.
Low Gain (VGA Code = 0)
Maximum Gain (VGA Code = 1023)
Gain Accuracy
Peak Nonlinearity 500 mV Input Signal
Total Output Noise
5.3
41.5
1
0.1
0.9
50
dB
dB
dB
%
40
12 dB gain applied.
LSB rms AC grounded input, 6 dB gain applied.
dB Measured with step change on supply.
Power Supply Rejection (PSR)
1 Input signal characteristics defined as follows:
500mV TYP
RESET TRANSIENT
100mV TYP
1V TYP
INPUT SIGNAL RANGE
OPTICAL BLACK PIXEL
Rev. B | Page 5 of 20
AD9943/AD9944
TIMING SPECIFICATIONS
CL = 20 pF, fSAMP = 25 MHz. See CCD-mode timing in Figure 14 and Figure 15, and serial timing in Figure 10 and Figure 11.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
DATACLK High/Low Pulse Width
SHP Pulse Width
SHD Pulse Width
CLPOB Pulse Width1
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
tCONV
tADC
tSHP
tSHD
tCOB
tS1
40
16
ns
ns
ns
ns
Pixels
ns
ns
20
10
10
20
10
20
3.0
2
tS2
tID
16
ns
DATA OUTPUTS
Output Delay
Pipeline Delay
tOD
9.5
9
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
fSCLK
tLS
tLH
tDS
tDH
10
10
10
10
10
MHz
ns
ns
ns
ns
1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Rev. B | Page 6 of 20
AD9943/AD9944
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter (With Respect To) Min
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Max
Unit
V
V
V
V
V
V
V
V
AVDD (AVSS)
DVDD (DVSS)
DRVDD (DRVSS)
Digital Outputs (DRVSS)
SHP, SHD, DATACLK (DVSS)
CLPOB, PBLK (DVSS)
SCK, SL, SDATA DVSS (AVSS)
REFT, REFB, CCDIN
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
+3.9
+3.9
+3.9
DRVDD + 0.3
DVDD + 0.3
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
150
THERMAL CHARACTERISTICS
The thermal resistance of a 32-Lead LFCSP package
(with the exposed bottom pad soldered to the board GND)
is θJA = 27.7°C/W.
Junction Temperature
Lead Temperature (10 sec)
°C
°C
300
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 20
AD9943/AD9944
AD9943 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
24 REFB
23 REFT
22 CCDIN
21 AVSS
20 AVDD
19 SHD
PIN 1
INDICATOR
AD9943
TOP VIEW
18 SHP
17 CLPOB
NC = NO CONNECT
Figure 2. AD9943 Pin Configuration
Table 7. AD9943 Pin Function Descriptions
Pin No.
1 to 10
11
12
13
14
15
16
17
18
19
20
21
Mnemonic
D0 to D9
DRVDD
DRVSS
DVDD
DATACLK
DVSS
PBLK
CLPOB
SHP
SHD
AVDD
AVSS
Type1
DO
P
P
P
Description
Digital Data Outputs.
Digital Output Driver Supply.
Digital Output Driver Ground.
Digital Supply.
Digital Data Output Latch Clock.
Digital Supply Ground.
DI
P
DI
DI
DI
DI
P
Preblanking Clock Input.
Black Level Clamp Clock Input.
CDS Sampling Clock for CCD Reference Level.
CDS Sampling Clock for CCD Data Level.
Analog Supply.
P
Analog Ground.
22
23
24
25
26
27
28 to 30
31 to 32
CCDIN
REFT
REFB
SL
SDATA
SCK
AI
Analog Input for CCD Signal.
AO
AO
DI
DI
DI
NC
NC
A/D Converter Top Reference Voltage Decoupling.
A/D Converter Bottom Reference Voltage Decoupling.
Serial Digital Interface Load Pulse.
Serial Digital Interface Data Input.
Serial Digital Interface Clock Input.
Internally pulled down. Float or connect to GND.
Internally not nonnected.
NC
NC
1 Type: AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
Rev. B | Page 8 of 20
AD9943/AD9944
AD9944 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D2 1
D3 2
D4 3
D5 4
D6 5
D7 6
D8 7
D9 8
24 REFB
23 REFT
22 CCDIN
21 AVSS
20 AVDD
19 SHD
PIN 1
INDICATOR
AD9944
TOP VIEW
18 SHP
17 CLPOB
NC = NO CONNECT
Figure 3. AD9944 Pin Configuration
Table 8. AD9944 Pin Function Descriptions
Pin No.
1 to 10
11
12
13
14
15
16
17
18
19
20
21
Mnemonic
D2 to D11
DRVDD
DRVSS
DVDD
DATACLK
DVSS
PBLK
CLPOB
SHP
SHD
AVDD
AVSS
Type1
DO
P
P
P
Description
Digital Data Outputs.
Digital Output Driver Supply.
Digital Output Driver Ground.
Digital Supply.
Digital Data Output Latch Clock.
Digital Supply Ground.
DI
P
DI
DI
DI
DI
P
Preblanking Clock Input.
Black Level Clamp Clock Input.
CDS Sampling Clock for CCD Reference Level.
CDS Sampling Clock for CCD Data Level.
Analog Supply.
P
Analog Ground.
22
23
24
25
26
27
28 to 30
31
32
CCDIN
REFT
REFB
SL
SDATA
SCK
NC
D0
D1
AI
Analog Input for CCD Signal.
A/D Converter Top Reference Voltage Decoupling.
A/D Converter Bottom Reference Voltage Decoupling.
Serial Digital Interface Load Pulse.
Serial Digital Interface Data Input.
Serial Digital Interface Clock Input.
Internally pulled down. Float or connect to GND.
Digital Data Output.
AO
AO
DI
DI
DI
NC
DO
DO
Digital Data Output.
1 Type: AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
Rev. B | Page 9 of 20
AD9943/AD9944
TERMINOLOGY
Differential Nonlinearity (DNL)
Power Supply Rejection (PSR)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Therefore
every code must have a finite width. No missing codes
guaranteed to 10-bit resolution indicates that all 1024 codes,
respectively, must be present over all operating conditions.
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9943/AD9944’s power supply. The PSR specification is
calculated from the change in the data outputs for a given
step change in the supply voltage.
Peak Nonlinearity
Internal Delay for SHP/SHD
Peak nonlinearity, a full-signal chain specification, refers to the
peak deviation of the output of the AD9943/AD9944 from a
true straight line. The point used as zero scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of
the 2 V ADC full-scale signal. The input signal is always
appropriately gained up to fill the ADC’s full-scale range.
The internal delay (also called aperture delay) is the time delay
that occurs from the time a sampling edge is applied to the
AD9943/AD9944 until the actual sample of the input signal is
held. Both SHP and SHD sample the input signal during the
transition from low to high, so the internal delay is measured
from each clock’s rising edge to the instant the actual internal
sample is taken.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
1LSB =
(
ADC Full Scale 2N codes
)
where N is the bit resolution of the ADC. For example, 1 LSB of
the AD9943 is 1.95 mV.
Rev. B | Page 10 of 20
AD9943/AD9944
EQUIVALENT INPUT CIRCUITS
AVDD
DVDD
60Ω
330Ω
INPUT
AVSS
AVSS
DVSS
Figure 4. Digital Inputs—SHP, SHD, DATACLK, CLOB, PBLK, SCK, SL
Figure 6. CCDIN (Pin 22)
DRVDD
DVDD
DATA
THREE-
STATE
DOUT
DVSS
DRVSS
Figure 5. Data Outputs
Rev. B | Page 11 of 20
AD9943/AD9944
TYPICAL PERFORMANCE CHARACTERISTICS
0.50
0.25
0
100
90
V
= 3.3V
DD
80
70
V
= 3.0V
= 2.7V
DD
V
DD
60
50
40
–0.25
–0.50
10
15
25
20
0
800
1600
2400
3200
4000
SAMPLE RATE (MHz)
Figure 9. AD9944 Typical DNL Performance
Figure 7. AD9943/AD9944 Power vs. Sample Rate
0.50
0.25
0
–0.25
–0.50
0
200
400
600
800
1000
Figure 8. AD9943 Typical DNL Performance
Rev. B | Page 12 of 20
AD9943/AD9944
INTERNAL REGISTER MAP
All register values default to 0x000 at power-up except clamp level, which defaults to 128 decimal (AD9943 = 32 LSB clamp level, and
AD9944 = 128 LSB clamp level).
Table 9.
Address Bits
Register Name
A2 A1 A0 Data Bits
Function
Operation
0
0
0
D0
D2, D1
D3
Software Reset (0 = normal operation, 1 = reset all registers to default).
Power-Down Modes (00 = normal power, 01 = standby, 10 = total shutdown).
OB Clamp Disable (0 = clamp on, 1 = clamp off).
D5, D4
D6
D8, D7
D11 to D9
D0
D1
D2
D3
D4
D5
D6
D11 to D7
D7 to D0
Test Mode. Should always be set to 00.
PBLK Blanking Level (0 = blank output to zero, 1 = blank to ob clamp level).
Test Mode 1. Should always be set to 00.
Test Mode 2. Should always be set to 000.
Control
0
0
1
SHP/SHD Input Polarity (0 = active low, 1 = active high).
DATACLK Input Polarity (0 = active low, 1 = active high).
CLPOB Input Polarity (0 = active low, 1 = active high).
PBLK Input Polarity (0 = active low, 1 = active high).
Three-State Data Outputs (0 = outputs active, 1 = outputs three-stated).
Data Output Latching (0 = latched by DATACLK, 1 = latch is transparent).
Data Output Coding (0 = binary output, 1 = gray code output).
Test Mode. Should always be set to 00000.
Clamp Level
VGA Gain
0
0
1
1
0
1
OB Clamp Level (AD9943: 0 = 0 LSB, 255 = 63.75 LSB,
AD9944: 0 = 0 LSB, 255 = 255 LSB).
D9 to D0
VGA Gain (0 = 6 dB, 1023 = 40 dB).
Rev. B | Page 13 of 20
AD9943/AD9944
SERIAL INTERFACE
TEST BIT
0
SDATA
SCK
A0
A1
tDH
A2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
tDS
tLS
tLH
SL
NOTES
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
3. ALL 12 DATA BITS D0–D11 MUST BE WRITTEN. IF THE REGISTER CONTAINS FEWER THAN 12 BITS, ZEROS SHOULD BE USED
FOR THE UNDEFINED BITS.
4. TEST BIT IS FOR INTERNAL USE ONLY AND MUST BE SET LOW.
Figure 10. Serial Write Operation
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
TEST
BIT
...
SDATA
A0
A1
A2
D0
D1
D2
D3
D4
D5
D10 D11 D0
D1
0
D2
31 ...
...
SCK
SL
30
17
18
27
28
29
15
16
1
2
3
4
5
6
7
8
9
10
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 12-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 12-BIT DATA-WORD. (ALL 12 BITS MUST BE WRITTEN.)
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED AT THE NEXT SL RISING EDGE.
Figure 11. Continuous Serial Write Operation to All Registers
Rev. B | Page 14 of 20
AD9943/AD9944
CIRCUIT DESCRIPTION AND OPERATION
DC RESTORE
INTERNAL
V
REF
6dB TO 40dB
VGA
2V FULL SCALE
0.1µF
CCDIN
10/12
10-/12-BIT
ADC
DOUT
CDS
CLPOB
OPTICAL BLACK
CLAMP
8-BIT
DAC
10
DIGITAL
FILTERING
VGA GAIN
REGISTER
8
CLAMP LEVEL
REGISTER
Figure 12. CCD Mode Block Diagram
The AD9943/AD9944 signal processing chain is shown in
OPTICAL BLACK CLAMP
Figure 12. Each processing step is essential for achieving a high
quality image from the raw CCD pixel data.
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with the
fixed black level reference selected by the user in the clamp level
register. The resulting error signal is filtered to reduce noise, and
the correction value is applied to the ADC input through a D/A
converter. Normally, the optical black clamp loop is turned on
once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital
clamping is used during the post processing, the optical black
clamping for the AD9943/AD9944 may be disabled using
Bit D3 in the operation register. Refer to Table 9 and Figure 10
and Figure 11.
DC RESTORE
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V, which is compatible with the 3 V single
supply of the AD9943/AD9944.
CORRELATED DOUBLE SAMPLER
The CDS circuit samples each CCD pixel twice to extract video
information and reject low frequency noise. The timing shown
in Figure 14 illustrates how the two CDS clocks, SHP and SHD,
are used, respectively, to sample the reference level and data
level of the CCD signal. The CCD signal is sampled on the
rising edges of SHP and SHD. Placement of these two clock
signals is critical for achieving the best performance from the
CCD. An internal SHP/SHD delay (tID) of 3 ns is caused by
internal propagation delays.
When the loop is disabled, the clamp level register may still be
used to provide programmable offset adjustment. Horizontal
timing is shown in Figure 15. The CLPOB pulse should be
placed during the CCD’s optical black pixels. It is recommended
that the CLPOB pulse be used during valid CCD dark pixels.
The CLPOB pulse should be a minimum of 20 pixels wide to
minimize clamp noise. Shorter pulse widths may be used, but
clamp noise may increase and the loop’s ability to track low
frequency variations in the black level is reduced.
Rev. B | Page 15 of 20
AD9943/AD9944
42
36
30
34
A/D CONVERTER
The ADC uses a 2 V input range. Better noise performance
results from using a larger ADC full-scale range. The ADC uses
a pipelined architecture with a 2 V full-scale input for low noise
performance.
VARIABLE GAIN AMPLIFIER
The VGA stage provides a gain range of 6 dB to 40 dB,
programmable with 10-bit resolution through the serial digital
interface. The minimum gain of 6 dB is needed to match a 1 V
input signal with the ADC full-scale range of 2 V. A plot of the
VGA gain curve is shown in Figure 13.
18
12
6
0
127
383
511
639
767
895
1023
255
VGA GAIN REGISTER MODE
VGA Gain
(
dB
)
=
VGA Code × 0.035 dB + 5.3 dB
Figure 13. VGA Gain Curve
Rev. B | Page 16 of 20
AD9943/AD9944
CCD MODE TIMING
CCD
SIGNAL
N
N + 1
N + 2
N + 9
N + 10
tID
tID
SHP
tS1
tS2
tCP
SHD
DATACLK
tOD
N – 10
OUTPUT
DATA
N – 9
N – 8
N – 1
N
NOTES
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
Figure 14. CCD Mode Timing
HORIZONTAL
BLANKING
EFFECTIVE PIXELS
OPTICAL BLACK PIXELS
DUMMY PIXELS
EFFECTIVE PIXELS
CCD
SIGNAL
CLPOB
PBLK
OUTPUT
DATA
OB PIXEL DATA
DUMMY BLACK
EFFECTIVE DATA
EFFECTIVE PIXEL DATA
NOTES
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
Figure 15. Typical CCD Mode Line Clamp Timing
Rev. B | Page 17 of 20
AD9943/AD9944
APPLICATIONS INFORMATION
The AD9943/AD9944 are complete analog front end (AFE)
products for digital still camera and camcorder applications. As
shown in Figure 12, the CCD image (pixel) data is buffered and
sent to the AD9943/AD9944 analog input through a series input
capacitor. The AD9943/AD9944 perform the dc restoration,
CDS, gain adjustment, black level correction, and analog-to-
digital conversion. The AD9943/AD9944’s digital output data is
then processed by the image processing ASIC. The internal
registers of the AD9943/AD9944—used to control gain, offset
level, and other functions—are programmed by the ASIC or
microprocessor through a 3-wire serial digital interface. A
system timing generator provides the clock signals for both the
CCD and the AFE.
DIGITAL
OUTPUTS
AD9943/AD9944
CCD
V
OUT
ADC
OUT
0.1µF
DIGITAL IMAGE
PROCESSING
ASIC
CCDIN
SERIAL
INTERFACE
REGISTER
DATA
BUFFER
CDS/CLAMP
TIMING
V-DRIVE
CCD
TIMING
TIMING
GENERATOR
Figure 16. System Applications Diagram
3
SERIAL
INTERFACE
32 31 30 29 28 27 26 25
1.0µF
1.0µF
24 REFB
23 REFT
22 CCDIN
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
PIN 1
IDENTIFIER
0.1µF
CCDIN
21 AVSS
20 AVDD
AD9943
3V
ANALOG
SUPPLY
19 SHD
0.1µF
TOP VIEW
18 SHP
17 CLPOB
(Not to Scale)
9
10 11 12 13 14 15 16
10
5
CLOCK
INPUTS
DATA
OUTPUTS
3V
3V
DRIVER
SUPPLY
ANALOG
SUPPLY
0.1µF
0.1µF
NC = NO CONNECT
Figure 17. AD9943 Recommended Circuit Configuration for CCD Mode
Rev. B | Page 18 of 20
AD9943/AD9944
3
SERIAL
INTERFACE
D0
D1
32 31 30 29 28 27 26 25
1.0µF
1.0µF
24 REFB
23 REFT
22 CCDIN
D2
D3
D4
D5
D6
D7
D8
D9
1
2
3
4
5
6
7
8
PIN 1
IDENTIFIER
0.1µF
CCDIN
21 AVSS
20 AVDD
AD9944
3V
ANALOG
SUPPLY
19 SHD
0.1µF
TOP VIEW
18 SHP
17 CLPOB
(Not to Scale)
9
10 11 12 13 14 15 16
12
5
CLOCK
INPUTS
DATA
OUTPUTS
3V
3V
DRIVER
SUPPLY
ANALOG
SUPPLY
0.1µF
0.1µF
NC = NO CONNECT
Figure 18. AD9944 Recommended Circuit Configuration for CCD Mode
INTERNAL POWER-ON RESET CIRCUITRY
After power-on, the AD9943/AD9944 automatically reset all
internal registers and perform internal calibration procedures.
This takes approximately 1 ms to complete. During this time,
normal clock signals and serial write operations may occur.
However, serial register writes are ignored until the internal
reset operation is completed.
close as possible to the package pins. A single clean power
supply is recommended for the AD9943 and AD9944, but a
separate digital driver supply may be used for DRVDD (Pin 11).
DRVDD should always be decoupled to DRVSS (Pin 12), which
should be connected to the analog ground plane. Advantages of
using a separate digital driver supply include using a lower
voltage (2.7 V) to match levels with a 2.7 V ASIC, and reducing
digital power dissipation and potential noise coupling. If the
digital outputs must drive a load larger than 20 pF, buffering
is the recommended method to reduce digital code transition
noise. Alternatively, placing series resistors close to the digital
output pins may also help reduce noise.
GROUNDING AND DECOUPLING
RECOMMENDATIONS
As shown in Figure 17 and Figure 18, a single ground plane is
recommended for the AD9943/AD9944. This ground plane
should be as continuous as possible. This ensures that all analog
decoupling capacitors provide the lowest possible impedance
path between the power and bypass pins and their respective
ground pins. All decoupling capacitors should be located as
Note: The exposed pad on the bottom of the AD9943/AD9944
should be soldered to the GND plane of the printed circuit
board.
Rev. B | Page 19 of 20
AD9943/AD9944
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
3.25
3.10 SQ
2.95
TOP
VIEW
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 19. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body
(CP-32)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9943KCP
Temperature Range
−20°C to +85°C
−20°C to +85°C
−20°C to +85°C
−20°C to +85°C
−20°C to +85°C
−20°C to +85°C
−20°C to +85°C
−20°C to +85°C
Package Description
Package Option
CP-32
Lead Frame Chip Scale (LFCSP)
Lead Frame Chip Scale (LFCSP)
Lead Frame Chip Scale (LFCSP)
Lead Frame Chip Scale (LFCSP)
Lead Frame Chip Scale (LFCSP)
Lead Frame Chip Scale (LFCSP)
Lead Frame Chip Scale (LFCSP)
Lead Frame Chip Scale (LFCSP)
AD9943KCPRL
AD9943KCPZ1
AD9943KCPZRL1
AD9944KCP
CP-32
CP-32
CP-32
CP-32
AD9944KCPRL
AD9944KCPZ1
AD9944KCPZRL1
CP-32
CP-32
CP-32
1 Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02905–0–5/04(B)
Rev. B | Page 20 of 20
相关型号：
AD9945KCPZRL
IC SPECIALTY CONSUMER CIRCUIT, QCC32, 5 X 5 MM, MO-220-VHHD-2, LFCSP-32, Consumer IC:Other
ADI
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