AD9954YSVZ_技术文档

400 MSPS 14-Bit, 1.8 V CMOS

Direct Digital Synthesizer

AD9954

Support for 5 V input levels on most digital inputs

PLL REFCLK multiplier (4× to 20×)

Internal oscillator, can be driven by a single crystal

Phase modulation capability

FEATURES

400 MSPS internal clock speed

Integrated 14-bit DAC

Programmable phase/amplitude dithering

32-bit tuning word

Multichip synchronization

Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)

Excellent dynamic performance

>80 dB SFDR @ 160 MHz ( 100 kHz offset) A_OUT

Serial I/O control

Ultrahigh speed analog comparator

Automatic linear and nonlinear frequency sweeping

capability

APPLICATIONS

Agile LO frequency synthesis

Programmable clock generator

FM chirp source for radar and scanning systems

Automotive radar

Test and measurement equipment

Acousto-optic device drivers

4 frequency/phase offset profiles

1.8 V power supply

Software and hardware controlled power-down

48-lead TQFP/EP package

Integrated 1024 word × 32-bit RAM

FUNCTIONAL BLOCK DIAGRAM

FREQUENCY

DDS CORE

AD9954

ACCUMULATOR

32

PHASE

M

U

X

ACCUMULATOR

RAM

DAC_R

PHASE

OFFSET

SET

DATA

–1

Z

STATIC RAM

1024 × 32

IOUT

32

19

14

32

COS(X)

DAC

14

SYSTEM

CLOCK

14

–1

Z

DDS

CLOCK

32

MUX

SYNC_IN

3

32

10

14

RAM DATA

<31:18>

θ

OSK

TIMING AND CONTROL LOGIC

I/O UPDATE

SYNC_CLK

PWRDWNCTL

0

M

U

X

SYNC

CONTROL REGISTERS

÷ 4

COMPARATOR

OSCILLATOR/BUFFER

COMP_IN

M

U

X

SYSTEM

CLOCK

4×–20×

CLOCK

MULTIPLIER

REFCLK

COMP_OUT

ENABLE

CRYSTAL OUT

PS<1:0> I/O PORT

RESET

Figure 1. 48-LeadTQFP/EP

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

AD9954

TABLE OF CONTENTS

General Description......................................................................... 3

Serial Port Operation................................................................. 30

Instruction Byte.......................................................................... 32

Serial Interface Port Pin Description....................................... 32

MSB/LSB Transfers .................................................................... 32

RAM I/O Via Serial Port ........................................................... 32

Suggested Application Circuits..................................................... 35

Outline Dimensions....................................................................... 36

ESD Caution................................................................................ 36

Ordering Guide .......................................................................... 36

AD9954—Electrical Specifications ................................................ 4

Absolute Maximum Ratings............................................................ 7

Pin Configurations ........................................................................... 8

Pin Function Descriptions .............................................................. 9

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 13

Component Blocks..................................................................... 13

Modes of Operation ................................................................... 22

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 2 of 36

AD9954

GENERAL DESCRIPTION

the AD9954 via a serial I/O port. The AD9954 includes an

The AD9954 is a direct digital synthesizer (DDS) featuring a

14-bit DAC operating up to 400 MSPS. The AD9954 uses

advanced DDS technology, coupled with an internal high speed,

high performance DAC to form a digitally programmable,

complete high frequency synthesizer capable of generating a

frequency-agile analog output sinusoidal waveform at up to

200 MHz. The AD9954 is designed to provide fast frequency

hopping and fine tuning resolution (32-bit frequency tuning

word). The frequency tuning and control words are loaded into

integrated 1024 × 32 static RAM to support flexible frequency

sweep capability in several modes. The AD9954 also supports a

user defined linear sweep mode of operation. The device

includes an on-chip high speed comparator for applications

requiring a square wave output.

The AD9954 is specified to operate over the extended industrial

temperature range of –40°C to +105°C.

Rev. 0 | Page 3 of 36

AD9954

AD9954—ELECTRICAL SPECIFICATIONS

Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V 5%, DVDD_I/O = 3.3 V 5%, R_SET= 3.92 kΩ, External Reference Clock

Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.

Test

Parameter

Temp Level Min

Typ

Max

Unit

REF CLOCK INPUT CHARACTERISTICS

Frequency Range

REFCLK Multiplier Disabled

REFCLK Multiplier Enabled at 4×

REFCLK Multiplier Enabled at 20×

Input Capacitance

Input Impedance

Duty Cycle

FULL

25°C

FULL

VI

V

1

20

4

400

100

20

MHz

pF

kΩ

%

3

1.5

50

Duty Cycle with REFCLK Multiplier Enabled

REFCLK Input Power¹

V

IV

35

–15

65

+3

%

dBm

0

DAC OUTPUT CHARACTERISTICS

Resolution

Full Scale Output Current

Gain Error

Output Offset

Differential Nonlinearity

14

10

Bits

mA

%FS

µA

LSB

pF

25°C

5

–10

15

+10

0.6

I

V

1

2

5

Integral Nonlinearity

Output Capacitance

Residual Phase Noise @ 1 kHz Offset, 40 MHz A_OUT

REFCLK Multiplier Enabled @ 20×

REFCLK Multiplier Enabled @ 4×

REFCLK Multiplier Disabled

Voltage Compliance Range

Wideband SFDR

25°C

V

I

–105

–115

–132

dBc/Hz

V

AVDD – 0.5

AVDD + 0.5

1 MHz to 10 MHz Analog Out

10 MHz to 40 MHz Analog Out

40 MHz to 80 MHz Analog Out

80 MHz to 120 MHz Analog Out

120 MHz to 160 MHz Analog Out

Narrow Band SFDR

25°C

V

73

67

62

58

52

dBc

40 MHz Analog Out ( 1 MHz)

40 MHz Analog Out ( 250 kHz)

40 MHz Analog Out ( 50 kHz)

40 MHz Analog Out ( 10 kHz)

80 MHz Analog Out ( 1 MHz)

80 MHz Analog Out ( 250 kHz)

80 MHz Analog Out ( 50 kHz)

80 MHz Analog Out ( 10 kHz)

120 MHz Analog Out ( 1 MHz)

120 MHz Analog Out ( 250 kHz)

120 MHz Analog Out ( 50 kHz)

120 MHz Analog Out ( 10 kHz)

160 MHz Analog Out ( 1 MHz)

160 MHz Analog Out ( 250 kHz)

160 MHz Analog Out ( 50 kHz)

160 MHz Analog Out ( 10 kHz)

25°C

V

87

89

91

93

85

87

89

91

83

85

87

89

81

83

85

87

dBc

Rev. 0 | Page 4 of 36

AD9954

Test

Parameter

Temp Level Min

Typ

Max

Unit

COMPARATOR INPUT CHARACTERISTICS

Input Capacitance

Input Resistance

Input Current

Hysteresis

25°C

V

IV

I

3

500

12

pF

kΩ

µA

mV

IV

30

45

COMPARATOR OUTPUT CHARACTERISTICS

Logic 1 Voltage, High Z Load

Logic 0 Voltage, High Z Load

Propagation Delay

Output Duty Cycle Error

Rise/Fall Time, 5 pF Load

Toggle Rate, High Z Load

Output Jitter²

FULL

25°C

VI

IV

1.6

V

ns

%

0.4

3

5

1

ns

200

MHz

ps RMS

dBc

COMPARATOR NARROWBAND SFDR

10 MHz (1 MHz)

10 MHz (250 kHz)

10 MHz (50 kHz)

10 MHz (10 kHz)

70 MHz (1 MHz)

70 MHz (250 kHz)

70 MHz (50 kHz)

70 MHz (10 kHz)

110 MHz (1 MHz)

110 MHz (250 kHz)

110 MHz (50 kHz)

110 MHz (10 kHz)

140 MHz (1 MHz)

140 MHz (250 kHz)

140 MHz (50 kHz)

140 MHz (10 kHz)

25°C

V

80

85

90

95

80

85

90

95

80

85

90

95

80

85

90

95

80

85

90

95

160 MHz (1 MHz)

160 MHz (250 kHz)

160 MHz (50 kHz)

160 MHz (10 kHz)

CLOCK GENERATOR OUTPUT JITTER³

5 MHz A_OUT

10 MHz A_OUT

40 MHz A_OUT

80 MHz A_OUT

120 MHz A_OUT

140 MHz A_OUT

160 MHz A_OUT

25°C

V

100

60

50

ps RMS

TIMING CHARACTERISTICS

Serial Control Bus

FULL

IV

Maximum Frequency

Minimum Clock Pulse Width Low

Minimum Clock Pulse Width High

Maximum Clock Rise/Fall Time

Minimum Data Setup Time DVDD_I/O = 3.3 V

Minimum Data Setup Time DVDD_I/O = 1.8 V

Minimum Data Hold Time

25

2

Mbps

ns

7

ns

3

5

0

ns

Rev. 0 | Page 5 of 36

AD9954

Test

Parameter

Temp Level Min

Typ

Max

Unit

Maximum Data Valid Time

FULL

IV

I

25

1

ns

ms

Wake-Up Time⁴

Minimum Reset Pulse Width High

5

4

6

0

SYSCLK Cycles⁵

I/O UPDATE, PS0, PS1 to SYNCCLK Setup Time DVDD_I/O = 3.3 V

I/O UPDATE, PS0, PS1 to SYNCCLK Hold Time

ns

Latency

I/O UPDATE to Frequency Change Prop Delay

I/O UPDATE to Phase Offset Change Prop Delay

I/O UPDATE to Amplitude Change Prop Delay

PS0, PS1 to RAM Driven Frequency Change Prop Delay

PS0, PS1 to RAM Driven Phase Change Prop Delay

PS0 to Linear Frequency Sweep Prop Delay

CMOS LOGIC INPUTS

25°C

IV

24

16

28

SYSCLK Cycles

Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V

Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V

Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V

Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V

Logic 1 Current

25°C

I

1.25

2.2

V

µA

pF

0.6

0.8

12

V

3

2

Logic 0 Current

Input Capacitance

CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V

Logic 1 Voltage

Logic 0 Voltage

CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V

Logic 1 Voltage

Logic 0 Voltage

25°C

I

1.35

2.8

V

0.4

25°C

I

V

POWER CONSUMPTION (AVDD = DVDD = 1.8 V)

Single Tone Mode (Comparator Off)

With RAM or Linear Sweep Enabled

With Comparator Enabled

With RAM and Comparator Enabled

Rapid Power-Down Mode

25°C

I

162

175

180

198

150

20

171

190

220

160

27

mW

Full-Sleep Mode

SYNCHRONIZATION FUNCTION⁶

Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V)

Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V)

SYNC_CLK Alignment Resolution⁷

25°C

VI

V

62.5

100

MHz

SYSCLK Cycles

1

¹To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise per-

formance of the device.

²Represents the cycle-to-cycle residual jitter from the comparator alone.

³Represents the cycle-to-cycle residual jitter from the DDS core driving the comparator.

⁴Wake-up time refers to the recovery from analog power-down modes (see section on Power-Down Modes of Operation). The longest time required is for the reference

clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DAC_BP and that the recommended PLL loop filter values are used.

⁵SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,

the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK fre-

quency is the same as the external reference clock frequency.

⁶SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.

⁷This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock

edges are aligned, the synchronization function should not increase the skew between the two edges.

Rev. 0 | Page 6 of 36

AD9954

ABSOLUTE MAXIMUM RATINGS

Table 2.

Table 3. Explanation of Test Levels

I

100% Production Tested.

Parameter

Rating

II

100% Production Tested at 25°C and sample Tested at

Specified Temperatures.

Maximum Junction Temperature

DVDD_I/O (Pin 43)

AVDD, DVDD

150°C

4 V

2 V

III Sample Tested Only.

IV Parameter is guaranteed by design and characterization

testing.

Digital Input Voltage (DVDD_I/O = 3.3 V)

Digital Input Voltage (DVDD_I/O = 1.8 V)

Digital Output Current

Storage Temperature

Operating Temperature

Lead Temperature (10 sec Soldering)

θ_JA

–0.7 V to +5.25 V

–0.7 V to +2.2 V

5 mA

–65°C to +150°C

–40°C to +105°C

300°C

V

Parameter is a typical value only.

VI Devices are 100% production tested at 25°C and

guaranteed by design and characterization testing for

industrial operating temperature range.

38°C/W

θ_JC

15°C/W

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at these or any

other conditions above those indicated in the operational sec-

tion of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

DIGITAL

COMPARATOR

INPUTS

COMPARATOR

OUTPUT

DAC OUTPUTS

INPUTS

AVDD

DVDD_I/O

IOUT

AVDD

IOUT

INPUT

COMP IN

MUST TERMINATE

OUTPUTS TO AVDD FOR

CURRENT FLOW. DO

NOT EXCEED THE

OUTPUT VOLTAGE

COMPLIANCE RATING.

AVOID OVERDRIVING

DIGITAL INPUTS.

FORWARD BIASING

ESD DIODES MAY

COUPLE DIGITAL NOISE

ONTO POWER PINS.

Figure 2. Equivalent Input and Output Circuits

Rev. 0 | Page 7 of 36

AD9954

PIN CONFIGURATIONS

48 47 46 45 44

42

40 39 38 37

43

41

I/O UPDATE

DVDD

1

2

3

4

5

6

7

8

9

RESET

36

35

34

PWRDWNCTL

DVDD

DGND

AVDD

DGND

33

32

31

30

29

AGND

AVDD

COMP_IN

AVDD

AD9954

AGND

TOP VIEW

(Not to Scale)

OSC/REFCLK

COMP_OUT

AVDD

28

27

26

CRYSTAL OUT 10

CLKMODESELECT 11

AGND

LOOP_FILTER

AVDD

12

25

13 14 15 16 17 18 19 20 21 22 23 24

Figure 3. 48-Lead EP_TQFP

Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to

analog ground. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or 3.3 V. The DVDD pins (Pin 2 and Pin 34) can only be

powered to 1.8 V.

Rev. 0 | Page 8 of 36

AD9954

PIN FUNCTION DESCRIPTIONS

Table 4. Pin Function Descriptions—48-Lead TQFP/EP

Pin No.

Mnemonic

I/O Description

1

I/O UPDATE

I

The rising edge transfers the contents of the internal buffer memory to the I/O registers. This pin

must be set up and held around the SYNC_CLK output signal.

2, 34

3, 33, 42

4, 6, 13, 16,

18, 19, 25,

27, 29

DVDD

DGND

AVDD

I

Digital Power Supply Pins (1.8 V).

Digital Power Ground Pins.

Analog Power Supply Pins (1.8 V).

5, 7, 14, 15,

17, 22, 26,

32

AGND

I

Analog Power Ground Pins.

8

OSC/REFCLK

I

Complementary Reference Clock/Oscillator Input. When the REFCLK port is operated in single-

ended mode, REFCLKB should be decoupled to AVDD with a 0.1 µF capacitor.

Reference Clock/Oscillator Input. See Clock Input section for details on the OSCILLATOR/REFCLK

operation.

9

10

11

CRYSTAL OUT

CLKMODESELECT

O

I

Output of the Oscillator Section.

Control Pin for the Oscillator Section. When high, the oscillator section is enabled. When low, the

oscillator section is bypassed.

12

LOOP_FILTER

I

This pin provides the connection for the external zero compensation network of the REFCLK

multiplier’s PLL loop filter. The network consists of a 1 kΩ resistor in series with a 0.1 µF capacitor

tied to AVDD.

20

21

23

24

IOUT

O

I

Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.

DAC Output. Should be biased through a resistor to AVDD, not AGND.

DAC Biasline Decoupling Pin.

A resistor (3.92 kΩ nominal) connected from AGND to DAC_R_SETestablishes the reference current

for the DAC.

IOUT

DACBP

DAC_R_SET

I

28

30

31

35

36

COMP_OUT

COMP_IN

PWRDWNCTL

RESET

O

I

Comparator Output.

Comparator Input.

Comparator Complementary Input.

Input Pin Used as an External Power-Down Control (see Table 13 for details).

Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9954 to the initial state,

as described in the I/O port register map.

I

37

38

IOSYNC

SDO

I

Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O

operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC is

returned low. If unused, ground this pin; do not allow this pin to float.

When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output. When

operated as a 2-wire serial port, this pin is unused and can be left unconnected.

O

39

40

41

CS

I

This pin functions as an active low chip select that allows multiple devices to share the I/O bus.

This pin functions as the serial data clock for I/O operations.

SCLK

SDIO

I/O When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input, only.

When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.

43

44

DVDD_I/O

SYNC_IN

I

Digital Power Supply (for I/O Cells Only, 3.3 V).

Input signal used to synchronize multiple AD9954s. This input is connected to the SYNC_CLK

output of a master AD9954.

45

46

SYNC_CLK

OSK

O

I

Clock Output Pin that Serves as a Synchronizer for External Hardware.

Input pin used to control the direction of the shaped on-off keying function when programmed

for operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not programmed, this pin

should be tied to DGND.

47, 48

<49>

PS0, PS1

AGND

I

Input pin used to select one of the four internal profiles. Profile <1:0> are synchronous to the

SYNC_CLK pin. Any change in these inputs transfers the contents of the internal buffer memory

to the I/O registers (sends an internal I/O UPDATE).

The exposed paddle on the bottom of the package is a ground connection for the DAC and must

be attached to AGND in any board layout.

Rev. 0 | Page 9 of 36

AD9954

TYPICAL PERFORMANCE CHARACTERISTICS

MKR1 98.0MHz

MKR1 80.0MHz

–61.55dB

REF 0dBm

ATTEN 10dB

–70.68dB

ATTEN 10dB

0

PEAK

LOG

10dB/

PEAK

LOG

10dB/

1R

–10

–20

–30

–20

–30

–40

MARKER

–40

MARKER

100.000000MHz

–70.68dB

80.000000MHz

–61.55dB

–50

–60

–70

–80

–90

–50

–60

–70

–80

–90

1

W1 S2

S3 FC

AA

W1 S2

S3 FC

AA

1

–100

CENTER 100MHz

#RES BW 3kHz

SPAN 200MHz

SWEEP 55.56 s (401 PTS)

CENTER 100MHz

#RES BW 3kHz

SPAN 200MHz

SWEEP 55.56 s (401 PTS)

VBW 3kHz

Figure 4. F_OUT= 1 MHz FCLK = 400 MSPS, WBSFDR

Figure 7. F_OUT= 80 MHz FCLK = 400 MSPS, WBSFDR

MKR1 80.0MHz

–69.12dB

MKR1 40.0MHz

–56.2dB

REF 0dBm

ATTEN 10dB

0

PEAK

LOG

PEAK

LOG

1R

–10

10dB/

–20

–30

–20

–30

–40

MARKER

–40

MARKER

80.000000MHz

–69.12dB

40.000000MHz

–56.2dB

–50

–60

–70

–80

–90

–50

–60

–70

–80

–90

1

W1 S2

S3 FC

AA

W1 S2

S3 FC

AA

1

–100

CENTER 100MHz

#RES BW 3kHz

SPAN 200MHz

SWEEP 55.56 s (401 PTS)

CENTER 100MHz

#RES BW 3kHz

SPAN 200MHz

SWEEP 55.56 s (401 PTS)

VBW 3kHz

Figure 5. F_OUT= 10 MHz, FCLK = 400 MSPS, WBSFDR

Figure 8 F_OUT= 120 MHz, FCLK = 400 MSPS, WBSFDR

MKR1 0Hz

–68.44dB

MKR1 0Hz

–53.17dB

REF 0dBm

ATTEN 10dB

1R

ATTEN 10dB

0

PEAK

LOG

PEAK

LOG

1R

–10

10dB/

–20

–30

–20

–30

–40

MARKER

–40

MARKER

40.000000MHz

–68.44dB

80.000000MHz

–53.17dB

–50

–60

–70

–80

–90

–50

–60

–70

–80

–90

1

W1 S2

S3 FC

AA

W1 S2

S3 FC

AA

1

–100

CENTER 100MHz

#RES BW 3kHz

SPAN 200MHz

SWEEP 55.56 s (401 PTS)

CENTER 100MHz

#RES BW 3kHz

SPAN 200MHz

SWEEP 55.56 s (401 PTS)

VBW 3kHz

Figure 6. F_OUT= 40 MHz, FCLK = 400 MSPS, WBSFDR

Figure 9. F_OUT= 160 MHz, FCLK = 400 MSPS, WBSFDR

Rev. 0 | Page 10 of 36

AD9954

MKR1 1.105MHz

–5.679dBm

MKR1 80.301MHz

REF –4dBm

ATTEN 10dB

–6.318dBm

1

0

PEAK

LOG

PEAK

LOG

–10

10dB/

–20

–30

–20

–30

–40

MARKER

–40

MARKER

1.105000MHz

–5.679dBm

80.301000MHz

–6.318dBm

–50

–60

–70

–80

–90

–50

–60

–70

–80

–90

W1 S2

S3 FC

AA

W1 S2

S3 FC

AA

ST

–100

ST

–100

CENTER 1.105MHz

#RES BW 30Hz

SPAN 2MHz

SWEEP 199.2 s (401 PTS)

CENTER 80.25MHz

#RES BW 30Hz

SPAN 2MHz

SWEEP 199.2 s (401 PTS)

VBW 30Hz

Figure 10. F_OUT= 1.1 MHz, FCLK = 400 MSPS, NBSFDR, 1 MHz

Figure 13. F_OUT= 80.3 MHz, FCLK = 400 MSPS, NBSFDR, 1 MHz

MKR1 85kHz

MKR1 120.205MHz

REF 0dBm

REF –4dBm

ATTEN 10dB

–93.01dB

ATTEN 10dB

–6.825dBm

1

0

PEAK

LOG

10dB/

PEAK

LOG

10dB/

1R

–10

–20

–30

–20

–30

–40

MARKER

–40

MARKER

40.000000MHz

–56.2dB

120.205000MHz

–6.825dBm

–50

–60

–70

–80

–90

–50

–60

–70

–80

–90

W1 S2

S3 FC

AA

W1 S2

S3 FC

AA

1

ST

–100

CENTER 10MHz

#RES BW 30Hz

SPAN 2MHz

SWEEP 199.2 s (401 PTS)

CENTER 120.2MHz

#RES BW 30Hz

SPAN 2MHz

SWEEP 199.2 s (401 PTS)

VBW 30Hz

Figure 11. F_OUT= 10 MHz, FCLK = 400 MSPS, NBSFDR, 1 MHz

Figure 14. F_OUT= 120.2 MHz, FCLK = 400 MSPS, NBSFDR, 1 MHz

MKR1 39.905MHz

MKR1 600kHz

REF 0dBm

REF –4dBm

ATTEN 10dB

–5.347dBm

ATTEN 10dB

–0.911dB

1

0

PEAK

LOG

PEAK

LOG

–10

10dB/

–20

–30

–20

–30

–40

MARKER

–40

CENTER

39.905000MHz

–5.347dBm

160.5000000MHz

–50

–60

–70

–80

–90

–50

–60

–70

–80

–90

W1 S2

S3 FC

AA

W1 S2

S3 FC

AA

ST

–100

CENTER 39.9MHz

#RES BW 30Hz

SPAN 2MHz

SWEEP 199.2 s (401 PTS)

CENTER 160.5MHz

#RES BW 30Hz

SPAN 2MHz

SWEEP 199.2 s (401 PTS)

VBW 30Hz

Figure 12. F_OUT= 39.9 MHz, FCLK = 400 MSPS, NBSFDR, 1 MHz

Figure 15. F_OUT= 160 MHz, FCLK = 400 MSPS, NBSFDR, 1 MHz

Rev. 0 | Page 11 of 36

AD9954

t

= 3.156ns

= 3.04ns

1

2

∆

t = –116.0PS

1/∆t = –8.621GHz

1

CH1 200mV

Ω

M 200PS 20.0GS/S IT 4.0PS/PT 3.1ns

A CH1

708mV

Figure 16. Residual Phase Noise with F_OUT= 159.5 MHz. F_CLK= 400 MSPS

(Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue)

Figure 19. Residual Peak-to-Peak Jitter of DDS

and Comparator Operating Together at 160 MHz

Figure 17. Residual Phase Noise with F_OUT= 9.5 MHz; F_CLK= 400 MSPS (Green),

4 ×100 MSPS (Red), and 20 × 20 MSPS (Blue)

FALL (R1) = 396.4PS

RISE(R2) = 464.3PS

R1

R2

REF2 200mV 500ns M 500PS 20.0GS/S IT 10.0PS/PT –100PS

A CH1

708mV

Figure 18. Comparator Rise and Fall Time at 160 MHz

Rev. 0 | Page 12 of 36

AD9954

THEORY OF OPERATION

COMPONENT BLOCKS

DDS Core

Clock Input

The output frequency (f_O) of the DDS is a function of the fre-

quency of system clock (SYSCLK), the value of the frequency

tuning word (FTW), and the capacity of the accumulator (2³², in

this case). The exact relationship is given below with f_Sdefined

as the frequency of SYSCLK.

The AD9954 supports various clock methodologies. Support for

differential or single-ended input clocks, and enabling of an on-

chip oscillator, and/or a phase-locked loop (PLL) multiplier are

all controlled via user programmable bits. The AD9954 may be

configured in one of six operating modes to generate the system

clock. The modes are configured using the CLKMODESELECT

pin, CFR1<4> and CFR2<7:3>. Connecting the external pin

CLKMODESELECT to Logic High enables the on-chip crystal

oscillator circuit. With the on-chip oscillator enabled, users of

the AD9954 connect an external crystal to the REFCLK and

REFCLKB inputs to produce a low frequency reference clock in

the range of 20 MHz to 30 MHz. The signal generated by the

oscillator is buffered before it is delivered to the rest of the chip.

This buffered signal is available via the CRYSTAL OUT pin. Bit

CFR1<4> can be used to enable or disable the buffer, turning on

or off the system clock. The oscillator itself is not powered

down in order to avoid long startup times associated with turn-

ing on a crystal oscillator. Writing CFR2<9> to Logic High

enables the crystal oscillator output buffer. Logic Low at

CFR2<9> disables the oscillator output buffer.

f_O

=

(

FTW

)(

f_S

)

/2³²with 0 ≤ FTW ≤ 2³¹

f_O= f_S×

(

1–

(

FTW /2³²

))

with 2³¹< FTW < 2³²–1

The value at the output of the phase accumulator is translated to

an amplitude value via the COS(x) functional block and routed

to the DAC.

In certain applications it is desirable to force the output signal to

zero phase. Simply setting the FTW to 0 does not accomplish

this; it only results in the DDS core holding its current phase

value. Thus, a control bit is required to force the phase accumu-

lator output to zero.

At power-up, the clear phase accumulator bit is set to Logic 1,

but the buffer memory for this bit is cleared (Logic 0). There-

fore, upon power-up, the phase accumulator will remain clear

until the first I/O UPDATE is issued.

Connecting CLKMODESELECT to Logic Low disables the on-

chip oscillator and the oscillator output buffer. With the oscilla-

tor disabled, an external oscillator must provide the REFCLK

and/or REFCLKB signals. For differential operation, these pins

are driven with complementary signals. For single-ended opera-

tion, a 0.1 µF capacitor should be connected between the

unused pin and the analog power supply. With the capacitor in

place, the clock input pin bias voltage is 1.35 V. In addition, the

PLL may be used to multiply the reference frequency by an

integer value in the range of 4 to 20. Table 5 summarizes the

clock modes of operation. Note the PLL multiplier is controlled

via the CFR2<7:3> bits, independent of the CFR1<4> bit.

Phase-Locked Loop (PLL)

The PLL allows multiplication of the REFCLK frequency. Con-

trol of the PLL is accomplished by programming the 5-bit

REFCLK multiplier portion of Control Function Register No. 2,

Bits <7:3>.

When programmed for values ranging from 0x04 to 0x14

(4 decimal to 20 decimal), the PLL multiplies the REFCLK input

frequency by the corresponding decimal value. However, the

maximum output frequency of the PLL is restricted to

400 MHz. Whenever the PLL value is changed, the user should

be aware that time must be allocated to allow the PLL to lock

(approximately 1 ms).

The PLL is bypassed by programming a value outside the range

of 4 to 20 (decimal). When bypassed, the PLL is shut down to

conserve power.

Table 5.Clock Input Modes of Operation

CFR1<4>

CLKMODESELECT

CFR2<7:3>

3 < M < 21

M < 4 or M > 20

3 < M < 21

M < 4 or M > 20

X

Oscillator Enabled?

System Clock

F_CLK= F_OSC× M

F_CLK= F_OSC

F_CLK= F_OSC× M

F_CLK= F_OSC

Frequency Range (MHz)

80 < F_CLK< 400

20 < F_CLK< 30

80 < F_CLK< 400

10 < F_CLK< 400

N/A

Low

High

Low

X

Yes

No

High

F_CLK= 0

Rev. 0 | Page 13 of 36

AD9954

DAC Output

addition, the linear sweep no dwell bit controls the linear sweep

block’s behavior upon reaching the terminal frequency in a

sweep. The actual method for programming a frequency sweep

is covered in the Modes of Operation section.

The AD9954 incorporates an integrated 14-bit current output

DAC. Unlike most DACs, this output is referenced to AVDD,

not AGND.

Serial IO Port

Two complementary outputs provide a combined full-scale

output current (I_OUT). Differential outputs reduce the amount of

common-mode noise that might be present at the DAC output,

offering the advantage of an increased signal-to-noise ratio. The

full-scale current is controlled by means of an external resistor

(R_SET) connected between the DAC_R_SETpin and the DAC

ground (AGND_DAC). The full-scale current is proportional to

the resistor value as follows

The AD9954 serial port is a flexible, synchronous serial communi-

cations port that allows easy interface to many industry-standard

microcontrollers and microprocessors. The serial I/O port is com-

patible with most synchronous transfer formats, including both the

Motorola 6905/11 SPI and Intel 8051 SSR protocols.

The interface allows read/write access to all registers that configure

the AD9954. MSB first or LSB first transfer formats are supported.

In addition, the AD9954’s serial interface port can be configured as

a single pin I/O (SDIO), which allows a 2-wire interface or two

unidirectional pins for in/out (SDIO/SDO), which enables a 3-wire

interface. Two optional pins, IOSYNC and , enable greater flexi-

bility for system design in the AD9954.

R_SET= 39.19/I_OUT

The maximum full-scale output current of the combined DAC

outputs is 15 mA, but limiting the output to 10 mA provides the

best spurious-free dynamic range (SFDR) performance. The DAC

output compliance range is AVDD + 0.5 V to AVDD – 0.5 V.Volt-

ages developed beyond this range will cause excessive DAC distor-

tion and could potentially damage the DAC output circuitry.

Proper attention should be paid to the load termination to keep the

output voltage within this compliance range.

CS

Register Maps and Descriptions

The register maps are listed in Table 7 and Table 8. The appro-

priate register map depends on the state of the linear sweep

enable bit because certain registers are remapped depending

on which mode the part is operating in. Specifically, Registers

0x07, 0x08, 0x09, and 0x0A act as the RAM segment control

words for each of the RAM profile slices when the linear sweep

enable bit is false. When the linear sweep enable bit is true, 0x07

becomes the negative linear sweep control word and 0x08

becomes the positive linear sweep control word. The 0x09 and

0x0A registers are not used in linear sweep mode. Because the

linear sweep operation takes precedence over RAM operations,

ADI recommends that the RAM enable bit CFR1<31> be set to

zero when the linear sweep enable bit CFR1<21> is true to

conserve power. The serial address numbers associated with

each of the registers are shown in hexadecimal format. Angle

brackets <> are used to reference specific bits or ranges of bits.

For example, <3> designates Bit 3, while <7:3> designates the

range of bits from 7 down to 3, inclusive.

Comparator

Many applications require a square wave signal rather than a

sine wave. For example, in most clocking applications a high

slew rate helps to reduce phase noise and jitter. To support these

applications, the AD9954 includes an on-chip comparator. The

comparator has a bandwidth greater than 200 MHz and a

common-mode input range of 1.3 V to 1.8 V. By setting the

comparator power-down bit, CFR1<6>, the comparator can be

turned off to save on power consumption.

Linear Sweep Block

Linear sweep is a mode of operation whereby changes from a

start frequency (F0) to a terminal frequency (F1) are not instan-

taneous but instead are accomplished in a sweep or ramped

fashion. Frequency ramping, whether linear or nonlinear, neces-

sitates that many intermediate frequencies between F0 and F1

will be output in addition to the primary F0 and F1 frequencies.

Table 6. Register Mapping Based on Linear Sweep Enable Bit

Linear Sweep Enable Bit Register Map

False (CFR1 <21> = 0)

True (CFR1 <21> = 1)

RAM Segment Control Words Active

Linear Sweep Control Words Active

The linear sweep block is comprised of the falling and rising

delta frequency tuning words, the falling and rising delta fre-

quency ramp rates, and the frequency accumulator. The linear

sweep enable bit CFR1 <21> enables the linear sweep block. In

Rev. 0 | Page 14 of 36

AD9954

Table 7. Register Map—When Linear Sweep Enable Bit Is False (CFR1<21> = 0).

Note that the RAM enable Bit CFR1<31> only activates the RAM itself not the RAM segment control words.

Register

Name

(Serial

Default

Value

OR

Bit

Range

(MSB)

Bit 7

(LSB)

Bit 0

Address)

Bit 6

Comp

Power-

Down

Bit 5

DAC

Power-

Down

Bit 4

Bit 3

Bit 2

Linear

Sweep No

Dwell

Bit 1

Profile

External

Power-

Down

0x00

Digital

Power-

Down

Clock Input

Power-

SYNC_CLK

Out

Disable

Not

Used

<7:0>

Down

Mode

AutoClr

Freq.

Accum

AutoClr

Phase

Accum

Enable

SINE

Output

Clear

Freq

Accum.

Clear

Phase

Accum.

SDIO

Input

Only

0x00

Control

Function

Register

No.1

(CFR1)

(0x00)

Load SRR

@ I/O UD

<15:8>

LSB First

Automatic

Sync

Enable

Software

Manual

Sync

Linear

Sweep

Enable

0x00

Not

Used

<23:16>

Not Used

RAM

Dest. Is

Phase

Word

Auto

OSK

Keying

RAM

Enable

Load ARR

@ I/O UD

OSK

Enable

<31:24>

<7:0>

Internal Profile Control <2:0>

REFCLK Multiplier

0x00 or 0x01, or 0x02 or 0x03: Bypass Multiplier

0x04 to 0x14: 4× to 20× Multiplication

0x00

Charge Pump Current

<1:0>

VCO Range

Control

Function

Register No.

2 (CFR2)

(0x01)

High

Speed

Sync

Hardware

Manual

Sync

CRYSTAL

Not

<15:8>

Not Used

OUT Pin

Used

Active

Enable

<23:16>

<7:0>

Not Used

Amplitude Scale Factor Register <7:0>

0x00

Amplitude

Scale Factor

(ASF)

Auto Ramp Rate Speed

Control <1:0>

<15:8>

Amplitude Scale Factor Register <13:8>

(0x02)

Amplitude

Ramp Rate

(ARR)

0x00

<7:0>

Amplitude Ramp Rate Register <7:0>

(0x03)

Frequency

Tuning

Word

(FTW0)

(0x04)

<7:0>

<15:8>

<23:16>

<31:24>

Frequency Tuning Word No. 0 <7:0>

Frequency Tuning Word No. 0 <15:8>

Frequency Tuning Word No. 0 <23:16>

Frequency Tuning Word No. 0 <31:24>

0x00

Phase

Offset Word

(POW0)

<7:0>

Phase Offset Word No. 0 <7:0>

0x00

<15:8>

Not Used<1:0>

Phase Offset Word No. 0 <13:8>

(0x05)

Frequency

Tuning

Word

(FTW1)

(0x06)

<7:0>

<15:8>

<23:16>

Frequency Tuning Word No. 1 <7:0>

Frequency Tuning Word No. 1 <15:8>

Frequency Tuning Word No. 1 <23:16>

Frequency Tuning Word No. 1 <31:24>

0x00

<31:24>

Rev. 0 | Page 15 of 36

AD9954

Register

Name

(Serial

Default

Value

OR

Bit

Range

(MSB)

Bit 7

(LSB)

Bit 0

Address)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Profile

RAM Segment 0 Mode Control <2:0> No Dwell

Active

RAM Segment 0 Beginning Address <9:6>

PS0 = 0

PS1 = 0

<7:0>

<15:8>

<23:16>

<31:24>

<39:32>

<7:0>

RAM Segment 0 Beginning Address <5:0>

RAM Segment 0 Final Address <9:8>

PS0 = 0

PS1 = 0

RAM

Segment

Control

Word No. 0

(RSCW0)

(0x07)

RAM Segment 0 Final Address <7:0>

PS0 = 0

PS1 = 0

RAM Segment 0 Address Ramp Rate <15:8>

RAM Segment 0 Address Ramp Rate <7:0>

PS0 = 0

PS1 = 0

PS0 = 0

PS1 = 0

RAM Segment 1 Mode Control

<2:0>

No Dwell

Active

RAM Segment 1 Beginning Address <9:6>

PS0 = 0

PS1 = 1

RAM Segment 1 Beginning Address <5:0>

RAM Segment 1 Final Address <9:8> PS0 = 0

PS1 = 1

RAM

Segment

Control

Word No. 1

(RSCW1)

(0x08)

<15:8>

<23:16>

<31:24>

<39:32>

<7:0>

RAM Segment 1 Final Address <7:0>

PS0 = 0

PS1 = 1

RAM Segment 1 Address Ramp Rate <15:8>

PS0 = 0

PS1 = 1

RAM Segment 1 Address Ramp Rate <7:0>

No Dwell Active

PS0 = 0

PS1 = 1

RAM Segment 2 Mode Control

<2:0>

RAM Segment 2 Beginning

Address <9:6>

PS0 = 1

PS1 = 0

RAM Segment 2 Beginning Address <5:0>

RAM Segment 2 Final Address <9:8>

PS0 = 1

PS1 = 0

RAM

Segment

Control

Word No. 2

(RSCW2)

(0x09)

<15:8>

<23:16>

<31:24>

<39:32>

<7:0>

RAM Segment 2 Final Address <7:0>

PS0 = 1

PS1 = 0

RAM Segment 2 Address Ramp Rate <15:8>

RAM Segment 2 Address Ramp Rate <7:0>

PS0 = 1

PS1 = 0

PS0 = 1

PS1 = 0

RAM Segment 3 Mode Control

<2:0>

RAM Segment 3 Beginning Address <5:0>

No Dwell Active

RAM Segment 3 Beginning

Address <9:6>

PS0 = 1

PS1 = 1

RAM Segment 3 Final Address <9:8>

PS0 = 1

PS1 = 1

RAM

Segment

Control

Word No. 3

(RSCW3)

(0x0A)

<15:8>

<23:16>

<31:24>

<39:32>

RAM Segment 3 Final Address <7:0>

PS0 = 1

PS1 = 1

RAM Segment 3 Address Ramp Rate <15:8>

RAM Segment 3 Address Ramp Rate <7:0>

PS0 = 1

PS1 = 1

PS0 = 1

PS1 = 1

RAM (0x0B)

RAM [1023:0] <31:0> (Read Instructions Write Out RAM Signature Register Data)

Rev. 0 | Page 16 of 36

AD9954

Table 8. Register Map–When Linear Sweep Enable Bit Is True (CFR1<21> = 1).

Note that the RAM enable Bit CFR1<31> only activates the RAM itself not the RAM segment control words.

Register

Name

(Serial

Default

Value

OR

(MSB)

Bit Range Bit 7

(LSB)

Bit 0

Address)

Bit 6

Comp

Power-

Down

Bit 5

DAC

Power-

Down

Bit 4

Clock

Input

Power

Dwn

Bit 3

Bit 2

Bit 1

Profile

External

Power-

Down

0x00

Digital

Power-

Down

CRYSTAL

OUT Pin

Active

SYNC_CLK

Out

Disable

Not

Used

<7:0>

Mode

AutoClr

Freq.

Accum

AutoClr

Phase

Accum

Enable

SINE

Output

Clear

Freq

Accum.

Clear

Phase

Accum.

SDIO

Input

Only

0x00

Load SRR

@ I/O UD

Control

Function

Register No.

1 (CFR1)

<15:8>

LSB First

Automatic Software

Linear

Sweep

Enable

0x00

Not

Used

Not

Used

<23:16>

Sync

Enable

Manual

Sync

Not Used

(0x00)

RAM

Dest. Is

Phase

Word

Output

Shaped

Keying

Enable

Auto

RAM

Enable

Load ARR

@ I/O UD

Output

Shaped

Keying

<31:24>

<7:0>

Internal Profile Control <2:0>

REFCLK Multiplier

0x00 or 0x1 or 0x02 or 0x03: Bypass Multiplier

0x04 to 0x14: 4× to 20× Multiplication

0x00

VCO

Range

Charge Pump Current

<1:0>

Control

Function

Register No.

2 (CFR2)

High

Speed

Sync

Hardware

Manual

Sync

CRYSTAL

Not

<15:8>

Not Used

OUT Pin

Used

(0x01)

Active

Enable

<23:16>

Not Used

0x00

<7:0>

(0x07)

Amplitude Scale Factor Register <7:0>

Amplitude

Scale Factor

(ASF) (0x02)

Auto Ramp Rate

Speed Control <1:0>

<15:8>

Amplitude Scale Factor Register <13:8>

Amplitude

Ramp Rate

(ARR) (0x03)

<7:0>

Amplitude Ramp Rate Register <7:0>

Frequency

Tuning

Word

(FTW0)

(0x04)

<7:0>

<15:8>

<23:16>

<31:24>

Frequency Tuning Word No. 0 <7:0>

Frequency Tuning Word No. 0 <15:8>

Frequency Tuning Word No. 0 <23:16>

Frequency Tuning Word No. 0 <31:24>

0x00

Phase Offset

Word

(POW0)

(0x05)

<7:0>

Phase Offset Word No. 0 <7:0>

0x00

<15:8>

Open<1:0>

Phase Offset Word No. 0 <13:8>

Frequency

Tuning

Word

(FTW1)

(0x06)

<7:0>

<15:8>

<23:16>

<31:24>

Frequency Tuning Word No. 1 <7:0>

Frequency Tuning Word No. 1 <15:8>

Frequency Tuning Word No. 1 <23:16>

Frequency Tuning Word No. 1 <31:24>

Negative

Linear

Sweep

Control

Word

(NLSCW)

(0x07)

<7:0>

<15:8>

<23:16>

<31:24>

Falling Delta Frequency Tuning Word <7:0>

Falling Delta Frequency Tuning Word <15:8>

Falling Delta Frequency Tuning Word <23:16>

Falling Delta Frequency Tuning Word <31:24>

PS0 = 0

<39:32>

Falling Sweep Ramp Rate Word <7:0>

Rev. 0 | Page 17 of 36

AD9954

Register

Name

(Serial

Default

Value

OR

(MSB)

Bit Range Bit 7

(LSB)

Bit 0

Address)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Profile

Positive

Linear

Sweep

Control

Word

<7:0>

<15:8>

<23:16>

<31:24>

Rising Delta Frequency Tuning Word <7:0>

Rising Delta Frequency Tuning Word <15:8>

Rising Delta Frequency Tuning Word <23:16>

Rising Delta Frequency Tuning Word <31:24>

PS0 = 1

(PLSCW)

(0x08)

<39:32>

Rising Sweep Ramp Rate Word <7:0>

Control Register Bit Descriptions

Control Function Register No.1 (CFR1)

CFR1<25>: Shaped On-Off Keying Enable Bit

The CFR1 is used to control the various functions, features,

and modes of the AD9954. The functionality of each bit is

detailed below.

CFR1<25> = 0 (default) Shaped on-off keying is

bypassed.

CFR1<25> = 1. Shaped on-off keying is enabled. When enabled,

CFR1<24> controls the mode of operation for this function.

CFR1<31>: RAM Enable Bit

CFR1<31> = 0 (default). When CFR1<31> is inactive, the RAM

is disabled for operation. Either single-tone mode of

operation or linear sweep mode of operation is enabled.

CFR1<24>: Auto Shaped On-Off Keying Enable Bit (Only Valid

When CFR1<25> Is Active High)

CFR1<24> = 0 (default). When CFR1<25> is active, a Logic 0

on CFR1<24> enables the manual shaped on-off keying opera-

tion. Each amplitude sample sent to the DAC is multiplied by

the amplitude scale factor. See the Shaped On-Off Keying sec-

tion for details.

CFR1<31> = 1. If CFR1<31> is active, the RAM is

enabled for operation. Access control for normal operation is

controlled via the mode control bits of the RSCW for the cur-

rent profile.

CFR1<30>: RAM Destination Bit

CFR1<24> = 1. When CFR1<25> is active, a Logic 1 on

CFR1<24> enables the auto shaped on-off keying operation.

Toggling the OSK pin high will cause the output scalar to ramp

up from zero scale to the amplitude scale factor at a rate deter-

mined by the amplitude ramp rate. Toggling the OSK pin low

will cause the output to ramp down from the amplitude scale

factor to zero scale at the amplitude ramp rate. See the Shaped

On-Off Keying section for details.

CFR1<30> = 0 (default). If CFR1<31> is active, a Logic 0 on the

RAM destination bit (CFR1<30> = 0) configures the AD9954

such that the RAM output drives the phase accumulator (i.e.,

the frequency tuning word). If CFR1<31> is inactive,

CFR1<30> is a Don’t Care.

CFR1<30> = 1. If CFR1<31> is active, a Logic 1 on the RAM

destination bit (CFR1<30> = 1) configures the AD9954 such

that the RAM output drives the phase-offset adder (i.e., sets the

phase offset of the DDS core).

CFR1<23>: Automatic Synchronization Enable Bit

CFR1<23> = 0 (default). The automatic synchronization feature

of multiple AD9954s is inactive.

CFR1<29:27>: Internal Profile Control Bits

CFR1<23> = 1. The automatic synchronization feature of mul-

tiple AD9954s is active. The device will synchronize its internal

synchronization clock (SYNC_CLK) to align to the signal pre-

sent on the sync-in input. See the Synchronizing Multiple

AD9954s section for details.

These bits cause the profile bits to be ignored when the RAM is

being used and puts the AD9954 into an automatic profile loop

sequence that allows the user to implement a frequency/phase

composite sweep that runs without external inputs. See the

Internal Profile Control section for more details.

CFR1<22>: Software Manual Synchronization of Multiple

AD9954

CFR1<26>: Amplitude Ramp Rate Load Control Bit

CFR1<26> = 0 (default). The amplitude ramp rate timer is

loaded only upon timeout (timer == 1) and is not loaded due to

an I/O UPDATE input signal.

CFR1<22> = 0 (default). The manual synchronization feature is

inactive.

CFR1<26> = 1. The amplitude ramp rate timer is loaded upon

timeout (timer == 1) or at the time of an I/O UPDATE input signal.

Rev. 0 | Page 18 of 36

AD9954

CFR1<22> = 1. The software controlled manual synchroniza-

tion feature is executed. The SYNC_CLK rising edge is

advanced by one SYNC_CLK cycle and this bit is cleared. To

advance the rising edge multiple times, this bit needs to be set

for each advance. See the Synchronizing Multiple AD9954s sec-

tion for details.

CFR1<11>: Clear Frequency Accumulator

CFR1<11> = 0 (default). The frequency accumulator functions

as normal.

CFR1<11> = 1. The frequency accumulator memory elements

are cleared and held clear until this bit is cleared.

CFR1<21>: Linear Frequency Sweep Enable

CFR1<10>: Clear Phase Accumulator

CFR1<21> = 0 (default). The linear frequency sweep capability

of the AD9954 is inactive.

CFR1<10> = 0 (default). The phase accumulator functions as

normal.

CFR1<21> = 1, the linear frequency sweep capability of the

AD9954 is enabled. When enabled, either the rising or falling

delta frequency tuning word is applied to the frequency accu-

mulator at the programmed ramp rate, causing the output fre-

quency to ramp up or ramp down, controlled by the Profile 0

input. See the Linear Sweep Mode section for details.

CFR1<10> = 1. The phase accumulator memory elements are

cleared and held clear until this bit is cleared.

CFR1<9>: SDIO Input Only

CFR1<9> = 0 (default). The SDIO pin has bidirectional opera-

tion (2-wire serial programming mode).

CFR1<20:16>: Not Used

CFR1<9> = 1. The serial data I/O pin (SDIO) is configured as

an input only pin (3-wire serial programming mode).

CFR1<15>: Linear Sweep Ramp Rate Load Control Bit

CFR1<8>: LSB First

CFR1<15> = 0 (default). The linear sweep ramp rate timer is

loaded only upon timeout (timer = 1) and is not loaded due to

an I/O UPDATE input signal.

CFR1<8> = 0 (default). MSB first format is active.

CFR1<8> = 1.The serial interface accepts serial data in LSB first

format.

CFR1<15> = 1. The linear sweep ramp rate timer is loaded

upon timeout (timer == 1) or at the time of an I/O UPDATE

input signal.

CFR1<7>: Digital Power-Down Bit

CFR1<14>: Auto Clear Frequency Accumulator Bit

CFR1<7> = 0 (default). All digital functions and clocks are ac-

tive.

CFR1<14> = 0 (default). The current state of the frequency

accumulator remains unchanged when the delta frequency

word is changed.

CFR1<7> = 1. All non-IO digital functionality is suspended,

lowering the power significantly.

CFR1<14> = 1. This bit automatically synchronously clears

(loads 0s into) the frequency accumulator for one cycle upon

reception of an I/O UPDATE signal.

CFR1<6>: Comparator Power-Down Bit

CFR1<6> = 0 (default). The comparator is enabled for opera-

tion.

CFR1<13>: Auto-Clear Phase Accumulator Bit

CFR1<6> = 1. The comparator is disabled and is in its lowest

power dissipation state.

CFR1<13> = 0 (default), the current state of the phase accumu-

lator remains unchanged when the frequency tuning word is

applied.

CFR1<5>: DAC Power-Down Bit

CFR1<5> = 0 (default). The DAC is enabled for operation.

CFR1<13> = 1. This bit automatically synchronously clears

(loads 0s into) the phase accumulator for one cycle upon recep-

tion of an I/O UPDATE signal.

CFR1<5> = 1. The DAC is disabled and is in its lowest power

dissipation state.

CFR1<12>: Sine/Cosine Select Bit

CFR1<4>: Clock Input Power-Down Bit

CFR1<12> = 0 (default). The angle-to-amplitude conversion

logic employs a COSINE function.

CFR1<4> = 0 (default). The clock input circuitry is enabled for

operation.

CFR1<12> = 1. The angle-to-amplitude conversion logic

employs a SINE function.

CFR1<4> = 1. The clock input circuitry is disabled and the

device is in its lowest power dissipation state.

Rev. 0 | Page 19 of 36

AD9954

CFR1<3>: External Power-Down Mode

CFR2<10> = 1. The hardware manual sync function is enabled.

While this bit is set, a rising edge on the SYNC_IN pin will

cause the device to advance the SYNC_CLK rising edge by one

REFCLK cycle. Unlike the software manual sync enable bit, this

bit does not self-clear. Once the hardware manual sync mode is

enabled, it will stay enabled until this bit is cleared. See the

Synchronizing Multiple AD9954s section for details.

CFR1<3> = 0 (default). The external power-down mode

selected is the rapid recovery power-down mode. In this mode,

when the PWRDWNCTL input pin is high, the digital logic and

the DAC digital logic are powered down. The DAC bias cir-

cuitry, comparator, PLL, oscillator, and clock input circuitry are

not powered down.

CFR2<9>: CRYSTAL OUT Enable Bit

CFR1<3> = 1. The external power-down mode selected is the

full power-down mode. In this mode, when the PWRDWNCTL

input pin is high, all functions are powered down. This includes

the DAC and PLL, which take a significant amount of time to

power up.

CFR2<9> = 0 (default). The CRYSTAL OUT pin is inactive.

CFR2<9> = 1. The CRYSTAL OUT pin is active. When active,

the crystal oscillator circuitry output drives the CRYSTAL OUT

pin, which can be connected to other devices to produce a refer-

ence frequency. The oscillator will respond to crystals in the

range of 20 MHz to 30 MHz.

CFR1<2>: Linear Sweep No Dwell Bit

CFR1<2> = 0 (default). The linear sweep no dwell function is

inactive.

CFR2<8>: Not Used

CFR1<2> = 1. The linear sweep no dwell function is active. If

CFR1<21>, the linear sweep enable bit, is active and CFR1<2> is

active, the linear sweep no dwell function is activated. See the

Linear Sweep Mode section for details. If CFR1<21> is clear,

this bit is a Don’t Care.

CFR2<7:3>: Reference Clock Multiplier Control Bits

This 5-bit word controls the multiplier value out of the clock-

multiplier (PLL) block. Valid values are decimal 4 to 20 (0×04 to

0×14). Values entered outside this range will bypass the clock

multiplier. See the Phase-Locked Loop (PLL) section for details.

CFR1<1>: SYNC_CLK Disable Bit

CFR2<2>: VCO Range Control Bit

CFR1<1> = 0 (default). The SYNC_CLK pin is active.

This bit is used to control the range setting on the VCO.

When CFR2<2> == 0 (default), the VCO operates in a range of

100 MHz to 250 MHz. When CFR2<2> == 1, the VCO operates

in a range of 250 MHz to 400 MHz.

CFR1<1> = 1. The SYNC_CLK pin assumes a static Logic 0

state to keep noise generated by the digital circuitry at a mini-

mum. However, the synchronization circuitry remains active

(internally) to maintain normal device timing.

CFR2<1:0>: Charge Pump Current Control Bits

CFR1<0>: Not Used, Leave at 0

These bits are used to control the current setting on the charge

pump. The default setting, CFR2<1:0>, sets the charge pump

current to the default value of 75 µA. For each bit added (01, 10,

11) 25 µA of current is added to the charge pump current:

100 µA, 125 µA, and 150 µA.

Control Function Register No.2 (CFR2)

The CFR2 is used to control the various functions, features, and

modes of the AD9954, primarily related to the analog sections

of the chip.

Other Register Descriptions

Amplitude Scale Factor (ASF)

CFR2<15:12>: Not Used

CFR2<11>: High Speed Sync Enable Bit

The ASF register stores the 2-bit auto ramp rate speed value and

the 14-bit amplitude scale factor used in the output shaped key-

ing (OSK) operation. In auto OSK operation, ASF <15:14> tells

the OSK block how many amplitude steps to take for each

increment or decrement. ASF<13:0> sets the maximum value

achievable by the OSK internal multiplier. In manual OSK

mode, ASF<15:14> has no effect. ASF <13:0> provide the output

scale factor directly. If the OSK enable bit is cleared, CFR1<25>

= 0, this register has no effect on device operation.

CFR2<11> = 0 (default). The high speed sync enhancement is

off.

CFR2<11> = 1. The high speed sync enhancement is on. This

bit should be set when attempting to use the auto-

synchronization feature for SYNC_CLK inputs beyond 50 MHz,

(200 MSPS SYSCLK). See the Synchronizing Multiple AD9954s

section for details.

CFR2<10>: Hardware Manual Sync Enable Bit

CFR2<10> = 0 (default). The hardware manual sync function is

off.

Rev. 0 | Page 20 of 36

AD9954

Amplitude Ramp Rate (ARR)

RAM Segment Address Ramp Rate, RSCW<39:24>

The ARR register stores the 8-bit amplitude ramp rate used in

the auto OSK mode. This register programs the rate at which

the amplitude scale factor counter increments or decrements. If

the OSK is set to manual mode, or if OSK enable is cleared, this

register has no effect on device operation.

For RAM modes that step through address values, such as

ramping, this 16-bit word defines the number of SYNC_CLK

cycles the RAM controller dwells at each address. A value of 0 is

invalid. Any other value from 1 to 65535 may be used.

RAM Segment Final Address RSCW<9:8>, RSCW<23:16>

Frequency Tuning Word 0 (FTW0)

This discontinuous 10-bit sequence defines the final address

value for the given RAM segment. The order in which the bits

are listed is the order in which the bits must be written.

RSCW<23>, even though during the write operation is more

significant than RSCW<9>, is only the third MSB of the final

address value. RSCW<9>, even though it comes later in the

RSCW than RSCW<23>, is the MSB of the final address value.

The frequency tuning word is a 32-bit register that controls the

rate of accumulation in the phase accumulator of the DDS core.

Its specific role is dependent on the device mode of operation.

Phase Offset Word (POW)

The phase offset word is a 14-bit register that stores a phase

offset value. This offset value is added to the output of the phase

accumulator to offset the current phase of the output signal.

The exact value of phase offset is given by the following formula

RAM Segment Beginning Address RSCW<3:0>, <15:10>

This discontinuous 10-bit sequence defines the final address

value for the given RAM segment. The order in which the bits

are listed is the order in which the bits must be written.

RSCW<15>, even though during the write operation is more

significant than RSCW<3>, is only the fifth MSB of the final

address value. RSCW<3>, even though it comes later in the

RSCW than RSCW<15>, is the MSB of the final address value.

POW

⎛

⎜

⎝

⎞

⎟

⎠

Φ =

×360°

2¹⁴

When the RAM enable bit is set, CFR1<31> = 1, and the RAM

destination is cleared, CFR1<30> = 0, the RAM supplies the

phase offset word and this register has no effect on device

operation.

RAM Segment Mode Control RSCW<7:5>

Frequency Tuning Word 1 (FTW1)

This 3-bit sequence determines the RAM segment’s mode of

operation. There are only five possible RAM modes, so only

values of 0–5 are valid. See Table 9 to determine the bit combi-

nation for various RAM modes.

The frequency tuning word is a 32-bit register that sets the

upper frequency in a linear sweep operation.

Negative and Positive Linear Sweep Control Word (NLSCW,

PLSCW)

RAM Segment No-Dwell Bit RSCW<4>

Registers 0x07 and 0x08 are multifunctional registers. When the

linear sweep bit CFR1<21> is enabled, Register 0x07 acts as the

negative linear sweep control word (NLSCW) and Register 0x08

acts as the positive linear sweep control word (PLSCW). Each of

the linear sweep control words contains a 32-bit delta frequency

tuning word (FDFTW, RDFTW) and an 8-bit sweep ramp rate

word (FSRRW, RSRRW). The delta frequency tuning words

determine the amount the frequency accumulator will incre-

ment or decrement the resultant tuning word. The sweep ramp

rate words determine the rate at which the accumulator will

increment or decrement, in number of synchronization clock

cycles.

This bit sets the No-Dwell feature of sweeping profiles. In pro-

files that sweep from a defined beginning to a defined end, the

RAM controller can either dwell at the final address until the

next profile is selected or, when this bit is set, the RAM control-

ler will return to the beginning address and dwell there until the

next profile is selected.

RAM

The AD9954 incorporates a 1024 × 32 block of SRAM. The

RAM is a bidirectional single-port. Both read and write opera-

tions from and to the RAM are valid, but they cannot occur

simultaneously. Write operations from the serial I/O port have

precedence, and if an attempt to write to RAM is made during a

read operation, the read operation will be halted. The RAM is

controlled in multiple ways, dictated by the modes of operation

described in the RAM Segment Control Word <7:5> as well as

data in the control function register. Read/write control for the

RAM will be described for each mode supported.

RAM Segment Control Words (RSCW0, RSCW1, RSCW2,

RSCW3)

When the Linear Sweep Enable bit CFR1<21> is clear,

Registers 0x07, 0x08, 0x09, and 0x0A act as the RAM segment

control words for each of the RAM segments. Each of the RAM

segment control words is comprised of a RAM segment address

ramp rate, a final address value, a beginning address value, a

RAM segment mode control, and a No-Dwell Bit.

When the RAM enable bit (CFR1<31>) is set, the RAM output

optionally drives the input to the phase accumulator or the

phase offset adder, depending on the state of the RAM destina-

Rev. 0 | Page 21 of 36

AD9954

tion bit (CFR1<30>). If CFR1<30> is a Logic 1, the RAM output

is connected to the phase offset adder and supplies the phase

offset control word(s) for the device. When CFR1<30> is Logic

0 (default condition), the RAM output is connected to the input

of the phase accumulator and supplies the frequency tuning

word(s) for the device. When the RAM output drives the phase

accumulator, the phase offset word (POW, Address 0x05) drives

the phase-offset adder. Similarly, when the RAM output drives

the phase offset adder, the frequency tuning word (FTW,

Address 0x04) drives the phase accumulator. When CFR1<31>

is Logic 0, the RAM is inactive unless being written to via the

serial port. The power-up state of the AD9954 is single-tone

mode, in which the RAM enable bit is inactive. The RAM is

segmented into four unique slices controlled by the Profile<1:0>

input pins.

RAM Controlled Modes of Operation

Direct Switch Mode

Direct switch mode enables FSK or PSK modulation. The

AD9954 is programmed for direct switch mode by writing the

RAM enable bit true and programming the RAM segment

mode control bits of each desired profile to Logic 000(b). This

mode simply reads the RAM contents at the RAM segment

beginning address for the current profile. No address ramping is

enabled in direct switch mode.

To perform 4-tone FSK, the user programs each RAM segment

control word for direct switch mode and a unique beginning

address value. In addition, the RAM enable bit is written true,

which enables the RAM, and the RAM destination bit is written

false, setting the RAM output to be the frequency tuning word.

The Profile<1:0> inputs are the 4-tone FSK data inputs. When

the profile is changed, the frequency tuning word stored in the

new profile is loaded into the phase accumulator and used to

increment the currently stored value in a phase continuous

fashion. The phase offset word drives the phase-offset adder.

Two-tone FSK is accomplished by using only one profile pin for

data.

All RAM writes/reads, unless otherwise specified, are controlled

by the Profile<1:0> input pins and the respective RAM segment

control word. The RAM can be written to during normal opera-

tion, but any I/O operation that commands the RAM to be writ-

ten immediately suspends read operation from the RAM, causing

the current mode of operation to be nonfunctional. This excludes

single-tone mode, as the RAM is not read in this mode.

Programming the AD9954 for PSK modulation is similar to

FSK except the RAM destination bit is set to a Logic 1, enabling

the RAM output to drive the phase offset adder. The FTW0

drives the input to the phase accumulator. Toggling the profile

pins changes (modulates) the current phase value. The upper

14 bits of the RAM drive the phase adder (<31:18>).

Bits <17:0> of the RAM output are unused when the RAM des-

tination bit is set. The no dwell bit is a Don’t Care in direct

switch mode.

Writing the RAM is accomplished as follows. After configuring

the desired RAM segment control words, the desired RAM

segment must be selected via the profile select pins PS<1:0>.

During the instruction byte, write the address for the RAM,

0x0B. The serial port and RAM controller will work in conjunc-

tion to determine the width of the profile and the serial port

will accept the defined number of 32-bit words sequentially

from the beginning address to the ending address. Consider the

following example:

Ramp-Up Mode

•

The RAM Segment Control Word 1 lists the beginning

RAM address at 256 and the ending address at 511.

Ramp-up mode, in conjunction with the segmented RAM capa-

bility, allows up to four different “sweep profiles” to be pro-

grammed into the AD9954. The AD9954 is programmed for

ramp-up mode by writing the RAM enable bit true and pro-

gramming the RAM mode control bits of each profile to be

used to Logic 001(b). As in all modes that enable the memory,

the RAM destination bit controls whether the RAM output

drives the phase accumulator or the phase offset adder.

•

PS0 = 1 and PS1 = 0.

The instruction byte is 10001001.

The RAM controller would configure the serial port to expect

256 32-bit words. The first 32 bits would be parsed as a word

and sent to RAM Address 256. The next 32 bits would be parsed

and sent to 257, and so forth, all the way through until the 256

word was sent (grand total of 8192 data bits in this operation).

Upon starting a sweep (via an I/O UPDATE or change in profile

bits), the RAM address generator loads the RAM segment be-

ginning address bits of the current RSCW, driving the RAM

output from this address, and the ramp rate timer loads the

RAM segment address ramp rate bits. When the ramp rate timer

finishes a cycle, the RAM address generator increments to the

next address, the timer reloads the ramp rate bits and begins a

new countdown cycle. This sequence continues until the RAM

address generator has incremented to an address equal to the

RAM segment final address bits of the current RSCW.

MODES OF OPERATION

Single-Tone Mode

In single-tone mode, the DDS core uses a single tuning word.

Whatever value is stored in FTW0 is supplied to the phase

accumulator. This value can only be changed manually, which is

done by writing a new value to FTW0 and by issuing an I/O

UPDATE. Phase adjustment is possible through the phase

offset register.

Rev. 0 | Page 22 of 36

AD9954

If the no dwell bit is clear when the RAM address generator

equals the final address, the generator stops incrementing as the

terminal frequency has been reached. The sweep is complete

and does not restart until an I/O UPDATE or change in profile

is detected to enable another sweep from the beginning to the

final RAM address as described above.

The sequence of ramping up and down is controlled via the

Profile<0> input signal for as long as the part is programmed

into this mode. The no dwell bit is a Don’t Care in this mode as

is all data in the RAM segment control words associated with

Profiles 1, 2, and 3. Only the information in the RAM segment

control word for Profile 0 is used to control the RAM in the

bidirectional ramp mode.

If the no dwell bit is set when the RAM address generator

equals the final address, after the next ramp rate timer cycle, the

phase accumulator is cleared. The phase accumulator remains

cleared until another sweep is initiated via an I/O UPDATE

input or change in profile.

Continuous Bidirectional Ramp Mode

Continuous bidirectional ramp mode allows the AD9954 to

offer an automatic symmetrical sweep between two frequencies.

The AD9954 is programmed for continuous bidirectional ramp

mode by writing the RAM enable bit true and the RAM mode

control bits of each profile to be used to Logic 011(b).

Another application for ramp-up mode is nonsymmetrical FSK

modulation. With the RAM configured for two segments, using

the Profile<0> bit as the data input allows nonsymmetrical

ramped FSK.

Upon entering this mode (via an I/O UPDATE or changing

Profile<1:0>), the RAM address generator loads the RAM seg-

ment beginning address bits of the current RSCW and the ramp

rate timer loads the RAM segment address ramp rate bits. The

RAM drives data from the beginning address, and the ramp rate

timer begins to count down to 1. When the ramp rate timer

completes a cycle, the RAM address generator increments to the

next address, and the timer reloads the ramp rate bits and con-

tinues counting down. This sequence continues until the RAM

address generator has incremented to an address equal to the

RAM segment final address bits of the current RSCW. Upon

reaching this terminal address, the RAM address generator will

decrement in value at the ramp rate until it reaches the RAM

segment beginning address. Upon reaching the beginning ad-

dress, the entire sequence repeats.

Bidirectional Ramp Mode

Bidirectional ramp mode allows the AD9954 to offer a symmet-

rical sweep between two frequencies using the Profile<0> signal

as the control input. The AD9954 is programmed for bidirec-

tional ramp mode by writing the RAM enable bit true and the

RAM mode control bits of RSCW0 to Logic 010(b). In bidirec-

tional ramp mode, the Profile<1> input is ignored and the Pro-

file<0> input is the ramp direction indicator. In this mode, the

memory is not segmented and uses only a single beginning and

final address. The address registers that affect the control of the

RAM are located in the RSCW associated with Profile 0.

Upon entering this mode (via an I/O UPDATE or changing

Profile<0>), the RAM address generator loads the RAM seg-

ment beginning address bits of RSCW0 and the ramp rate timer

loads the RAM segment address ramp rate bits. The RAM

drives data from the beginning address, and the ramp rate timer

begins to count down to 1. While operating in this mode, tog-

gling the Profile<0> pin does not cause the device to generate

an internal I/O UPDATE. When the Profile<0> pin is acting as

the ramp direction indicator, any transfer of data from the I/O

buffers to the internal registers can only be initiated by a rising

edge on the I/O UPDATE pin.

The entire sequence repeats for as long as the part is pro-

grammed for this mode. The no dwell bit is a Don’t Care in this

mode. In general, this mode is identical in control to the bidi-

rectional ramp mode except the ramp up and down is automatic

(no external control via the Profile<0> input) and switching

profiles is valid. Once in this mode, the address generator ramps

from the beginning address to the final address, then back to

the beginning address at the rate programmed into the ramp

rate register. This mode enables generation of an automatic saw

tooth sweep characteristic.

RAM address control now is a function of the Profile<0> input.

When the Profile<0> bit is a Logic 1, the RAM address genera-

tor increments to the next address when the ramp rate timer

completes a cycle (and reloads to start the timer again). As in

the ramp-up mode, this sequence continues until the RAM

address generator has incremented to an address equal to the

final address as long as the Profile<0> input remains high. If the

Profile<0> input goes low, the RAM address generator immedi-

ately decrements and the ramp rate timer is reloaded. The RAM

address generator will continue to decrement at the ramp rate

period until the RAM address is equal to the beginning address

as long as the Profile<0> input remains low.

Continuous Recirculate Mode

Continuous recirculate mode allows the AD9954 to offer

an automatic, continuous unidirectional sweep between two

frequencies. The AD9954 is programmed for continuous

recirculate mode by writing the RAM enable bit true and the RAM

mode control bits of each profile to be used to Logic 100(b).

Upon entering this mode (via an I/O UPDATE or changing

Profile<1:0>), the RAM address generator loads the RAM seg-

ment beginning address bits of the current RSCW and the ramp

rate timer loads the RAM segment address ramp rate bits. The

RAM drives data from the beginning address, and the ramp rate

timer begins to count down to 1. When the ramp rate timer

Rev. 0 | Page 23 of 36

AD9954

completes a cycle, the RAM address generator increments to the

next address, and the timer reloads the ramp rate bits and con-

tinues counting down. This sequence continues until the RAM

address generator has incremented to an address equal to the

RAM segment final address bits of the current RSCW. Upon

reaching this terminal address, the RAM address generator

reloads the RAM segment beginning address bits and the

sequence repeats.

When any of the CFR1<29:27> bits are active, the

internal profile control mode is engaged. Internal profile control

is only valid when the device is operating in RAM mode. There

is no internal profile control for linear sweeping operations.

When the internal profile control mode is engaged, the RAM

segment mode control bits are Don’t Care and the device oper-

ates all profiles as if these mode control bits were programmed

for ramp-up mode. Switching between profiles occurs when the

RAM address generator has exhausted the memory contents for

the current profile.

The sequence of circulating through the specified RAM

addresses repeats for as long as the part is programmed for this

mode. The no dwell bit is a Don’t Care in this mode.

Table 10. Internal Profile Control

RAM Controlled Modes of Operation Notes and Summary

CFR1<29:27>

Notes:

(Binary)

Mode Description

000

001

Internal Control Inactive

Internal Control Active, Single Burst, Activate

Profile 0, Then 1, Then Stop

1) The user must ensure that the beginning address is lower

than the final address.

010

011

100

101

110

Internal Control Active, Single Burst, Activate

Profile 0, Then 1, Then 2, Then Stop

Internal Control Active, Single Burst, Activate

Profile 0, Then 1, Then 2, Then 3, Then Stop

Internal Control Active, Continuous, Activate

Profile 0, Then 1, Then Loop Starting 0

Internal Control Active, Continuous, Activate

Profile 0, Then 1, Then 2, Then Loop Starting 0

2) Changing profiles or issuing an I/O UPDATE automatically

terminates the current sweep and starts the next sweep.

3) Setting the RAM destination bit true such that the RAM

output drives the phase offset adder is valid. While the

above discussion describes a frequency sweep, a phase

sweep operation is also available.

Internal Control Active, Continuous, Activate

Profile 0, Then 1, Then 2, Then 3, Then Loop

Starting 0

The AD9954 offers five modes of RAM controlled operation

(see Table 9).

111

Invalid

Table 9. RAM Modes of Operation

RSCW<7:5>

(Binary)

A single burst mode is one in which the composite sweep is

executed once. For example, assume the device is programmed

for ramp-up mode and the CFR1<29:27> bits are written to

Logic 010(b). Upon receiving an I/O UPDATE, the internal

control logic signals the device to begin executing the ramp-up

mode sequence for Profile 0. Upon reaching the RAM segment

final address value for Profile 0, the device automatically

switches to Profile 1 and begins executing that ramp-up

sequence. Upon reaching the RAM segment final address value

for Profile 1, the device automatically switches to Profile 2 and

begins executing that ramp-up sequence. When the RAM seg-

ment final address value for Profile 2 is reached, the sequence is

over and the composite sweep has completed. Issuing another

I/O UPDATE restarts the burst process.

Mode

Notes

000

Direct Switch

No Sweeping, Profiles

Valid, No Dwell Invalid

Sweeping, Profiles Valid,

No Dwell Valid

Sweeping, Profile <0> Is a

Direction Control Bit, No

Dwell Invalid

Sweeping, Profiles Valid,

No Dwell Invalid

001

010

Ramp Up

Bidirectional

Ramp

011

Continuous

Bidirectional

Ramp

Continuous

Recirculate

100

Sweeping, Profiles Valid,

No Dwell Invalid

Invalid Mode—Default To

Direct Switch

101, 110, 111

Open

A continuous internal profile control mode is one in which the

composite sweep is continuously executed for as long as the

device is programmed into that mode. Using the example above,

except programming the CFR1<29:27> bits to Logic 101(b), the

operation would be identical until the RAM segment final

address value for Profile 2 is reached. At this point, instead of

stopping the sequence, it repeats, starting with Profile 0.

Internal Profile Control

The AD9954 offers a mode in which a composite frequency

sweep can be built, for which the timing control is software

programmable. The internal profile control capability disen-

gages the Profile<1:0> pins and enables the AD9954 to take

control of switching between profiles. Modes are defined that

allow continuous or single burst profile switches for three com-

binations of profile selection bits. These are listed in Table 10.

Rev. 0 | Page 24 of 36

AD9954

2)

3)

4)

5)

Program the rising and falling delta frequency tuning

words and ramp rate values.

Linear Sweep Mode

The AD9954 is placed in linear sweep mode by setting the lin-

ear sweep enable bit CR1<21>. When in linear sweep mode, the

AD9954 output frequency will ramp up from a starting fre-

quency, programmed by FTW0 to a finishing frequency FTW1,

or down from FTW1 to FTW0. The delta frequency tuning

words and the ramp rate word determine the rate at which this

ramping takes place. The linear sweep no-dwell bit CFR1<2>

controls the behavior of the device upon reaching the terminal

frequency. The 32-bit rising delta frequency tuning word

(RDFTW) increments the frequency accumulator when ramp-

ing up from FTW0 to FTW1. The 8-bit rising sweep ramp rate

word (RSRRW) controls the rate at which the frequency accu-

mulator is incremented. The 32-bit falling delta frequency tun-

ing word (FDFTW) decrements the accumulator when ramping

down from FTW1 to FTW0. The 8-bit falling sweep ramp rate

word (FSRRW) determines the rate at which the accumulator is

decremented.

Program the lower and higher output frequencies into

the FTW0 and FTW1 registers, respectively.

Apply an I/O UPDATE to move this data into the reg-

isters (the output frequency will be FTW0).

Change the PS<0> input as desired to sweep between

the lower to higher frequency and back.

Figure 20 shows that the device initially powers up in single

tone mode. The profile inputs are low, which places the FTW0

input to the phase accumulator. The user then configures the

device as desired by writing the rising and falling delta

frequency tuning words and ramp rates, as well as the linear

sweep enable bit, via the serial port (Point A in Figure 20). In this

example, the linear sweep no-dwell bit is cleared (CFR1<2> = 0).

The PS<0> pin controls the direction of the sweep, rising to

FTW1 or falling to FTW0. Upon reaching the destination fre-

quency, the AD9954 linear sweep function will either hold at the

destination frequency until the state on the PS<0> pin is

changed or immediately return to the initial frequency, FTW0,

depending on the state of the linear sweep no-dwell bit

CFR1<02>. While operating in linear sweep mode, toggling the

Profile<0> pin does not cause the device to generate an internal

I/O UPDATE. When the PS<0> pin is acting as the sweep direc-

tion indicator, any transfer of data from the I/O buffers to the

internal registers can only be initiated by a rising edge on the

I/O UPDATE pin.

General Operation of Linear Sweep Capability

In linear sweep mode, the PS<1> pin must be tied to Logic 0.

With linear sweep mode active, when the PS<0> pin transitions

from low to high, the RDFTW is applied to the input of the

frequency accumulator and the RSRR register is loaded into the

sweep rate timer. The sweep rate timer counts down from an

initial value to one, at which point the frequency accumulator is

allowed to accumulate the input. This accumulation of the

RDFTW at the rate given by the ramp rate (RSRR) continues

until the output of the frequency adder is equal to the FTW1

register value. At this time the accumulation is stopped, causing

the AD9954 to output the frequency given by the FTW1. The

output remains at FTW1 for as long as the PS<0> pin remains

at Logic 1.

The linear sweep function of the AD9954 requires the lowest

frequency to be loaded into the FTW0 register and the highest

frequency into the FTW1 register. For piece-wise, nonlinear

frequency transitions, it is necessary to reprogram the registers

while the frequency transition is in progress to affect the desired

response. Figure 20 demonstrates a typical frequency ramping

operation. After a reset, the device will initially be in single tone

mode. The programming steps to operate in linear sweep mode

are

When the PS<0> pin transitions from high to low, the

negated FDFTW is applied to the input of the frequency accu-

mulator and the FSRR register is loaded into the sweep rate

timer. Each time the timer counts down to one, the frequency

accumulator is allowed to accumulate the input. This accumula-

tion of the negated FDFTW at the rate given by the ramp rate

(FSRR) continues until the output of the frequency adder is

equal to the FTW0 register value. At this time the accumulation

is stopped, causing the AD9954 to output the frequency given

by the FTW0. The output remains at FTW0 for as long as the

PS<0> pin remains at Logic 0.

0)

1)

Profile inputs at 00.

Set the linear sweep enable bit (CFR1<21> = 1) and

set or clear the linear sweep no-dwell bit (CFR1<2> =

{0,1}) as desired.

Rev. 0 | Page 25 of 36

AD9954

F

OUT

B

FTW1

A

FTW0

TIME

SINGLE–TONE

MODE

LINEAR SWEEP MODE

PS<0> = 1

PS<0> = 0

AT POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RISING DFTW.

AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FALLING DFTW.

Figure 20. Linear Sweep Frequency Plan

F

OUT

B

FTW1

A

FTW0

TIME

SINGLE–TONE

MODE

PS<0> = 0

PS<0> = 1 PS<0> = 0 PS<0> = 1

PS<0> = 0

PS<0> = 1

LINEAR SWEEP MODE ENABLE–NO DWELL BIT SET

Figure 21. Linear Sweep Using No Dwell Frequency Plan

mode operation when the linear sweep no dwell bit is set. The

points labeled A indicate where a rising edge on PS0 is detected;

the points labeled B indicate where the AD9954 has determined

Linear Sweep No Dwell Feature

The linear sweep function can be operated with a no dwell fea-

ture. If the linear sweep no dwell bit is set, CFR1<2> = 1, the

rising sweep is started in an identical manner to the non-no

dwell linear sweep mode. Upon detecting a rising edge on the

PS<0> input pin, the rising sweep action is initiated. The fre-

quency continues to sweep up at the rate set by the rising sweep

ramp rate at the resolution set by the rising delta frequency

tuning word until it reaches the terminal frequency. Upon

reaching the terminal frequency, the output frequency immedi-

ately returns to the starting frequency and remains at the start-

ing frequency until the device detects a subsequent rising edge

on the PS<0> pin. Figure 21 is an example of the linear sweep

F

_OUThas reached the terminal frequency and automatically

returns to the starting frequency. Note that in this mode, each

sweep will require a separate rising edge on the Profile <0> pin.

Linear sweeps using the no-dwell bit can only be swept from

FTW0 to FTW1 using the positive linear sweep control word.

Toggling the PS<0> from 1 to 0 will not initiate a falling sweep

when the no dwell bit is set, nor will it interrupt a positive

sweep already underway.

Rev. 0 | Page 26 of 36

AD9954

Clear and Release Function

Programming the Ramp Rate Timer

The linear sweep ramp rate timer is a loadable down counter

that, when enabled, continuously counts down from the loaded

value to a count of 1. When in a rising transition, the loaded

value is the RSRRW; when in a falling transition, the value is the

FSRRW. When the ramp rate timer equals 1, the proper

RFDTW or FDFTW is loaded and the counter begins counting

down to 1 again. This load and count down operation continues

for as long as the timer is enabled, unless the timer is forced to

load before reaching a count of 1.

The auto clear frequency accumulator bit, when set, clears

and releases the frequency accumulator upon receiving an I/O

UPDATE signal or change in one of the profile pins. The auto

clear phase accumulator, when set, clears and releases the phase

accumulator upon receiving an I/O UPDATE or change on one

of the profile pins. The automatic clearing function is repeated

for every subsequent I/O UPDATE or change on one of the

profile pins until the appropriate auto-clear control bit is

cleared.

The ramp timer can be loaded before reaching a count of 1 by

three methods.

Note that these bits are programmed independently and do not

have to be active at the same time. For example, one accumula-

tor may be using the clear and release function while the other

is continuously cleared.

Method one is by changing the PS<0> input pin. When the

PS<0> input pin changes from a Logic 0 to a Logic 1, the

RSRRW value is loaded into the ramp rate timer, which then

proceeds to count down as normal. When the Profile<0> input

pin changes from a Logic 1 to a Logic 0, the FSRR value is

loaded into the ramp rate timer, which then proceeds to count

down as normal.

Programming AD9954 Features

Phase Offset Control

A 14-bit phase offset (θ) may be added to the output of the

phase accumulator by means of the control registers. This fea-

ture provides the user with three different methods of phase

control.

The second method in which the sweep ramp rate timer can be

loaded before reaching a count of 1 is if the CFR1<15> bit is set

and an I/O UPDATE is issued. If sweep is enabled and

CFR1<15> is set, the ramp rate timer loads the value deter-

mined by the Profile<0> pin every time an I/O UPDATE is

issued. If the Profile<0> pin is low (high), the ramp rate timer

loads the FSRRW (RSRRW).

The first method is a static phase adjustment, where a fixed

phase offset is loaded into the appropriate phase offset register

and left unchanged. The result is that the output signal is offset

by a constant angle relative to the nominal signal. This allows

the user to phase align the DDS output with some external sig-

nal, if necessary.

The last method in which the sweep ramp rate timer can be

loaded before reaching a count of 1 is going from the inactive

linear sweep mode to the active linear sweep mode. That is

when the sweep enable bit is being set. The ramp rate loaded is a

function of the Profile<0> input pin.

The second method of phase control is where the user regularly

updates the phase offset register via the I/O port. By properly

modifying the phase offset as a function of time, the user can

implement a phase modulated output signal. However, both the

speed of the I/O port and the frequency of SYSCLK limit the

rate at which phase modulation can be performed.

Continuous and “Clear and Release” Frequency and Phase

Accumulator Clear Functions

The third method of phase control involves the RAM and the

profile input pins. The AD9954 can be configured such that the

RAM drives the phase adjust circuitry. The user can control the

phase offset via the RAM in an identical manner allowed for

frequency sweeping. See the RAM Controlled Modes of Opera-

tion and the Linear Sweep Mode sections for details.

The AD9954 allows for a programmable continuous zeroing of

the frequency sweep logic and the phase accumulator as well as

a clear and release or automatic zeroing function. Each feature is

individually controlled via Bits CFR1. CFR1<14> is the auto-

matic clear frequency accumulator bit and CFR1<13> is the

automatic clear phase accumulator bit. The continuous clear

bits are located in CFR1<11:10>, where CFR1<11> clears the

frequency accumulator and CFR1<10> clears the phase accu-

mulator.

Shaped On-Off Keying

The shaped on-off keying function of the AD9954 allows the

user to control the ramp-up and ramp-down time of an on-off

emission from the DAC. This function is used in burst trans-

missions of digital data to reduce the adverse spectral impact of

short, abrupt bursts of data.

Continuous Clear Bits

The continuous clear bits are simply static control signals that,

when active high, hold the respective accumulator at zero for

the entire time the bit is active. When the bit goes low, inactive,

the respective accumulator is allowed to operate.

Auto and manual shaped on-off keying modes are supported.

The auto mode generates a linear scale factor at a rate deter-

mined by the amplitude ramp rate (ARR) register controlled by

an external pin (OSK). Manual mode allows the user to directly

Rev. 0 | Page 27 of 36

AD9954

control the output amplitude by writing the scale factor value

into the amplitude scale factor (ASF) register.

Table 11. Auto-Scale Factor Internal Step Size

ASF<15:14> (Binary)

Increment/Decrement Size

00

01

10

11

1

2

4

8

The shaped on-off keying function may be bypassed (disabled)

by clearing the OSK enable bit (CFR1<25> = 0).

The modes are controlled by two bits located in the most sig-

nificant byte of the control function register (CFR). CFR1<25>

is the shaped on-off keying enable bit. When CFR1<25> is set,

the output scaling function is enabled; CFR1<25> bypasses the

function. CFR1<24> is the internal shaped on-off keying active

bit. When CFR1<24> is set, internal shaped on-off keying mode

is active; CFR1<24> cleared is external shaped on-off keying

mode active. CFR1<24> is a Don’t Care if the shaped on-off

keying enable bit (CFR1<25>) is cleared. The power up condi-

tion is shaped on-off keying disabled (CFR1<25> = 0).

OSK Ramp Rate Timer

The OSK ramp rate timer is a loadable down counter, which

generates the clock signal to the 14-bit counter that generates

the internal scale factor. The ramp rate timer is loaded with the

value of the ASFR every time the counter reaches 1 (decimal).

This load and countdown operation continues for as long as the

timer is enabled, unless the timer is forced to load before reach-

ing a count of 1.

Figure 22 shows the block diagram of the OSK circuitry.

AUTO Shaped On-Off Keying Mode Operation

If the load OSK timer bit (CFR1<26>) is set, the ramp rate timer

is loaded upon an I/O UPDATE, upon a change in profile input,

or upon reaching a value of 1. The ramp timer can be loaded

before reaching a count of 1 by three methods.

The auto shaped on-off keying mode is active when CFR1<25>

and CFR1<24> are set. When auto shaped on-off keying mode

is enabled, a single scale factor is internally generated and

applied to the multiplier input for scaling the output of the DDS

core block (see Figure 22). The scale factor is the output of a

14-bit counter that increments/decrements at a rate determined

by the contents of the 8-bit output ramp rate register. The scale

factor increases if the OSK pin is high and decreases if the OSK

pin is low. The scale factor is an unsigned value such that all 0s

multiply the DDS core output by 0 (decimal) and 0x3FFF mul-

tiplies the DDS core output by 16383 (decimal).

Method one is by changing the OSK input pin. When the OSK

input pin changes state, the ASFR value is loaded into the ramp

rate timer, which then proceeds to count down as normal.

The second method in which the sweep ramp rate timer can be

loaded before reaching a count of 1 is if the load OSK timer bit

(CFR1<26>) is set and an I/O UPDATE (or change in profile) is

issued.

For those users who use the full amplitude (14-bits) but need

fast ramp rates, the internally generated scale factor step size

is controlled via the ASF<15:14> bits. Table 11 describes the

increment/decrement step size of the internally generated scale

factor per the ASF<15:14> bits.

The last method in which the sweep ramp rate timer can be

loaded before reaching a count of 1 is when going from the

inactive auto shaped on-off keying mode to the active auto

shaped on-off keying mode. That is, when the sweep enable bit

is being set.

A special feature of this mode is that the maximum output

amplitude allowed is limited by the contents of the amplitude

scale factor register. This allows the user to ramp to a value less

than full scale.

DDS CORE

AUTO DESK

EMABLE

CFR1<24>

TO DAC

COS(X)

OSK ENABLE

CFR<25>

SYNC_CLK

LOAD OSK TIMER

CFR1<26>

0

1

OSK PIN

AMPLITUDE RAMP

RATE REGISTER

(ASF)

AMPLITUDE SCALE

FACTOR REGISTER

(ASF)

0

HOLD

UP/DN

OUT

LOAD DATA

EN

INC/DEC ENABLE

CLOCK

RAMP RATE TIMER

AUTO SCALE

FACTOR GENERATOR

Figure 22. On-Off Shaped Keying, Block Diagram

Rev. 0 | Page 28 of 36

AD9954

External Shaped On-Off Keying Mode Operation

with SYNC_CLK is used to transfer internal buffer contents

into the control registers of the device. The combination of the

SYNC_CLK and I/O UPDATE pins provide the user with

constant latency relative to SYSCLK and also ensures phase

continuity of the analog output signal when a new tuning word

or phase offset value is asserted. Figure 23 demonstrates an I/O

UPDATE timing cycle and synchronization.

The external Shaped On-Off Keying mode is enabled by writing

CFR1<25> to a logic 1 AND writing CFR1<24> to a Logic 0.

When configured for external Shaped On-Off Keying, the

content of the ASFR becomes the scale factor for the data path.

The scale factors are synchronized to SYNC_CLK via the I/O

UPDATE functionality.

Notes to synchronization logic:

Synchronization; Register Updates (I/O UPDATE)

Functionality of the SYNC_CLK and I/O UPDATE

1) The I/O UPDATE signal is edge detected to generate a

single rising edge clock signal that drives the register bank

flops. The I/O UPDATE signal has no constraints on duty

cycle. The minimum low time on I/O UPDATE is one

SYNC_CLK clock cycle.

Data into the AD9954 is synchronous to the SYNC_CLK signal

(supplied externally to the user on the SYNC_CLK pin). The

I/O UPDATE pin is sampled on the rising edge of the

SYNC_CLK.

2) The I/O UPDATE pin is set up and held around the rising

edge of SYNC_CLK and has zero hold time and 4 ns setup

time.

Internally, SYSCLK is fed to a divide-by-4 frequency divider to

produce the SYNC_CLK signal. The SYNC_CLK signal is pro-

vided to the user on the SYNC_CLK pin. This enables synchro-

nization of external hardware with the device’s internal clocks.

This is accomplished by forcing any external hardware to obtain

its timing from SYNC_CLK. The I/O UPDATE signal coupled

SYNC_CLK

DISABLE

0

SYSCLK

÷ 4

OSK

PROFILE<1:0>

I/O UPDATE

D

Q

D

Q

EDGE

DETECTION

LOGIC

TO CORE LOGIC

SYNC_CLK

GATING

SCLK

SDI

CS

REGISTER

MEMORY

I/O BUFFER

LATCHES

Figure 23. I/O Synchronization Block Diagram

Rev. 0 | Page 29 of 36

AD9954

SYSCLK

A

B

SYNC_CLK

I/O UPDATE

DATA IN

REGISTERS

DATA 2

DATA 3

DATA 1

DATA IN

I/O BUFFERS

DATA 1

DATA 2

DATA 3

THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.

Figure 24. I/O Synchronization Timing Diagram

Synchronizing Multiple AD9954s

edge of the SYNC_CLK signal each time the device detects a

rising edge on the SYNC_IN pin. To put the device into hard-

ware manual synchronization mode, set the hardware manual

synchronization bit (CFR2<10> = 1). Unlike the software man-

ual synchronization bit, this bit does not self-clear. Once the

hardware manual synchronization mode is enabled, all rising

edges detected on the SYNC_IN input will cause the device to

advance the rising edge of the SYNC_CLK by one SYSCLK

cycle until this enable bit is cleared (CFR2<10> = 0).

The AD9954 product allows easy synchronization of multiple

AD9954s. There are three modes of synchronization available

to the user: an automatic synchronization mode, a software

controlled manual synchronization mode, and a hardware

controlled manual synchronization mode. In all cases, when a

user wants to synchronize two or more devices, the following

considerations must be observed. First, all units must share a

common clock source. Trace lengths and path impedance of the

clock tree must be designed to keep the phase delay of the dif-

ferent clock branches as closely matched as possible. Second, the

I/O UPDATE signal’s rising edge must be provided synchro-

nously to all devices in the system. Finally, regardless of the

internal synchronization method used, the DVDD_I/O supply

should be set to 3.3 V for all devices that are to be synchronized.

AVDD and DVDD should be left at 1.8 V.

Using a Single Crystal to Drive Multiple AD9954 Clock

Inputs

The AD9954 crystal oscillator output signal is available on the

CRYSTAL OUT pin, enabling one crystal to drive multiple

AD9954s. In order to drive multiple AD9954s with one crystal,

the CRYSTAL OUT pin of the AD9954 using the external crys-

tal should be connected to the REFCLK input of the other

AD9954.

In automatic synchronization mode, one device is chosen as a

master, the other device(s) will be slaved to this master. When

configured in this mode, all the slaves will automatically syn-

chronize their internal clocks to the SYNC_CLK output signal

of the master device. To enter automatic synchronization mode,

set the slave device’s automatic synchronization bit (CFR1<23>

= 1). Connect the SYNC_IN input(s) to the master SYNC_CLK

output. The slave device will continuously update the phase

relationship of its SYNC_CLK until it is in phase with the

SYNC_IN input, which is the SYNC_CLK of the master device.

When attempting to synchronize devices running at SYSCLK

speeds beyond 250 MSPS, the high speed sync enhancement

enable bit should be set (CFR2<11> = 1).

The CRYSTAL OUT pin is static until the CFR2<1> bit is set,

enabling the output. The drive strength of the CRYSTAL OUT

pin is typically very low, so this signal should be buffered prior

to using it to drive any loads.

SERIAL PORT OPERATION

With the AD9954, the instruction byte specifies read/write

operation and register address. Serial operations on the AD9954

occur only at the register level, not the byte level. For the

AD9954, the serial port controller recognizes the instruction

byte register address and automatically generates the proper

register byte address. In addition, the controller expects that all

bytes of that register will be accessed. It is a requirement that all

bytes of a register be accessed during serial I/O operations, with

one exception. The IOSYNC function can be used to abort an

I/O operation, thereby allowing less than all bytes to be ac-

cessed.

In software manual synchronization mode, the user forces the

device to advance the SYNC_CLK rising edge one SYSCLK

cycle (1/4 SYNC_CLK period). To activate the manual

synchronization mode, set the slave device’s software manual

synchronization bit (CFR1<22> = 1). The bit (CFR1<22>) will be

immediately cleared. To advance the rising edge of the SYNC_CLK

multiple times, this bit will need to be set multiple times.

There are two phases to a communication cycle with the

AD9954. Phase 1 is the instruction cycle, which is the writing of

an instruction byte into the AD9954, coincident with the first

In hardware manual synchronization mode, the SYNC_IN

input pin is configured such that it will now advance the rising

Rev. 0 | Page 30 of 36

AD9954

eight SCLK rising edges. The instruction byte provides the

AD9954 serial port controller with information regarding the

data transfer cycle, which is Phase 2 of the communication cycle.

The Phase 1 instruction byte defines whether the upcoming data

transfer is read or write and the serial address of the register

being accessed. [Note that the serial address of the register

being accessed is NOT the same address as the bytes to be

written. See the Example Operation section for details].

register being accessed. For example, when accessing the Control

Function Register 2, which is three bytes wide, Phase 2 requires that

three bytes be transferred. If accessing the frequency tuning word,

which is four bytes wide, Phase 2 requires that four bytes be

transferred. After transferring all data bytes per the instruction,

the communication cycle is completed.

At the completion of any communication cycle, the AD9954

serial port controller expects the next eight rising SCLK edges

to be the instruction byte of the next communication cycle. All

data input to the AD9954 is registered on the rising edge of

SCLK. All data is driven out of the AD9954 on the falling edge

of SCLK. Figure 25 through Figure 28 are useful in understand-

ing the general operation of the AD9954 serial port

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the AD9954. The

remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the AD9954

and the system controller. The number of bytes transferred

during Phase 2 of the communication cycle is a function of the

.

INSTRUCTION CYCLE

CS

DATA TRANSFER CYCLE

SCLK

I

D

0

SDIO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

Figure 25. Serial Port Write Timing–Clock Stall Low

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CS

SCLK

I

0

DON'T CARE

SDIO

SDO

7

6

5

4

3

2

1

D

O 0

O 7

O 6

O 5

O 4

O 3

O 2

O 1

Figure 26. 3-Wire Serial Port Read Timing–Clock Stall Low

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CS

SCLK

I

D

0

SDIO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

Figure 27. Serial Port Write Timing–Clock Stall High

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CS

SCLK

I

D

SDIO

7

6

5

4

3

2

1

0

O 7

O 6

O 5

O 4

O 3

O 2

O 1 O 0

Figure 28. 2-Wire Serial Port Read Timing—Clock Stall High

Rev. 0 | Page 31 of 36

AD9954

INSTRUCTION BYTE

The instruction byte contains the following information:

Table 12.

MSB

D6

D5

D4

D3

D2

D1

LSB

R/Wb

X

A4

A3

A2

A1

A0

written in the format indicated by Control Register 0x00 <8>. If

the AD9954 is in LSB first mode, the instruction byte must be

written from least significant bit to most significant bit.

R/Wb—Bit 7 of the instruction byte determines whether a read

or write data transfer will occur after the instruction byte write.

Logic High indicates read operation. Logic 0 indicates a write

operation.

For MSB first operation, the serial port controller will generate

the most significant byte (of the specified register) address first

followed by the next lesser significant byte addresses until the

I/O operation is complete. All data written to (read from) the

AD9954 must be (will be) in MSB first order. If the LSB mode is

active, the serial port controller will generate the least signifi-

cant byte address first followed by the next greater significant

byte addresses until the I/O operation is complete. All data writ-

ten to (read from) the AD9954 must be (will be) in LSB first

order.

X, X—Bits 6 and 5 of the instruction byte are Don’t Care.

A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte

determine which register is accessed during the data transfer

portion of the communications cycle.

SERIAL INTERFACE PORT PIN DESCRIPTION

SCLK—Serial Clock. The serial clock pin is used to synchronize

data to and from the AD9954 and to run the internal state ma-

chines. SCLK maximum frequency is 25 MHz.

Example Operation

CSB—Chip Select Bar. CSB is active low input that allows more

than one device on the same serial communications line. The

SDO and SDIO pins will go to a high impedance state when this

input is high. If driven high during any communications cycle,

that cycle is suspended until CS is reactivated low. Chip select

can be tied low in systems that maintain control of SCLK.

To write the amplitude scale factor register in MSB first format,

apply an instruction byte of 0x02 (serial address is 00010(b)).

From this instruction, the internal controller will generate an

internal byte address of 0x07 (see the register map) for the first

data byte written and an internal address of 0x08 for the next

byte written. Since the amplitude scale factor register is two

bytes wide, this ends the communication cycle.

SDIO — Serial Data I/O. Data is always written into the

AD9954 on this pin. However, this pin can be used as a

bidirectional data line. Bit 7 of Register Address 0x0 controls

the configuration of this pin. The default is Logic 0, which

configures the SDIO pin as bidirectional.

To write the amplitude scale factor register in LSB first format,

apply an instruction byte of 0x40. From this instruction, the

internal controller will generate an internal byte address of 0x08

(see the register map) for the first data byte written and an in-

ternal address of 0x07for the next byte written. Since the ampli-

tude scale factor register is two bytes wide, this ends the com-

munication cycle.

SDO—Serial Data Out. Data is read from this pin for protocols

that use separate lines for transmitting and receiving data. In the

case where the AD9954 operates in a single bidirectional I/O

mode, this pin does not output data and is set to a high imped-

ance state.

RAM I/O VIA SERIAL PORT

Accessing the RAM via the serial port is identical to any other

serial I/O operation except that the number of bytes transferred

is determined by the address space between the beginning

address and the final address as specified in the current RAM

segment control word (RSCW). The final address describes the

most significant word address for all I/O transfers and the

beginning address specifies the least significant address.

IOSYNC—It synchronizes the I/O port state machines without

affecting the addressable registers contents. An active high input

on the IOSYNC pin causes the current communication cycle to

abort. After IOSYNC returns low (Logic 0), another communi-

cation cycle may begin, starting with the instruction byte write.

MSB/LSB TRANSFERS

RAM I/O supports MSB/LSB first operation. When in MSB first

mode, the first data byte will be for the most significant byte of

the memory address described by the final address with the

remaining three bytes making up the lesser significant bytes of

that address. The remaining bytes come in most significant to

least significant, destined for RAM addresses generated in

descending order until the final four bytes are written into the

The AD9954 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by the Control Register 0x00 <8> bit.

The default value of Control Register 0x00 <8> is low (MSB

first). When Control Register 0x00 <8> is set high, the AD9954

serial port is in LSB first format. The instruction byte must be

Rev. 0 | Page 32 of 36

AD9954

address specified as the beginning address. When in LSB first

mode, the first data byte will be for the least significant byte

of the memory (specified by the beginning address) with the

remaining three bytes making up the greater significant bytes of

that address. The remaining bytes come in least significant to

most significant, destined for RAM addresses generated in

ascending order until the final four bytes are written into the

memory address described by the final address. Of course, the

bit order for all bytes is least significant to most significant first

when the LSB first bit is set. When the LSB first bit is cleared

(default), the bit order for all bytes is most significant to least

significant.

3) Reading profile registers requires that the profile select pins

(Profile<1:0>) be configured to select the desired register

bank. When reading a register that resides in one of the

profiles, the register address acts as an offset to select one

of the registers among the group of registers defined by the

profile, while the profile select pins select the appropriate

register group.

Power-Down Functions of the AD9954

The AD9954 supports an externally controlled or hardware

power-down feature as well as the more common software pro-

grammable power-down bits found in previous ADI DDS products.

The software control power-down allows the DAC, comparator,

PLL, input clock circuitry, and the digital logic to be individu-

ally power down via unique control bits (CFR1<7:4>). With the

exception of CFR1<6>, these bits are not active when the exter-

nally controlled power-down pin (PWRDWNCTL) is high.

External power-down control is supported on the AD9954 via

the PWRDWNCTL input pin. When the PWRDWNCTL input

pin is high, the AD9954 will enter a power-down mode based

on the CFR1<3> bit. When the PWRDWNCTL input pin is low,

the external power-down control is inactive.

The RAM uses serial address 01011(b), so the instruction byte

to write the RAM is 0×0B, in MSB first notation. As mentioned

above, the RAM addresses generated are specified by the begin-

ning and final address of the RSCW currently selected by the

Profile<1:0> pins.

Notes on serial port operation:

1) The AD9954 serial port configuration bits reside in Bits 8

and 9 of CFR1 (Address 0x00). The configuration changes

immediately upon writing to this register. For multibyte

transfers, writing to this register may occur during the

middle of a communication cycle. Care must be taken to

compensate for this new configuration for the remainder

of the current communication cycle.

When the CFR1<3> bit is 0, and the PWRDWNCTL input pin

is high, the AD9954 is put into a fast recovery power-down

mode. In this mode, the digital logic and the DAC digital logic

are powered down. The DAC bias circuitry, comparator, PLL,

oscillator, and clock input circuitry is NOT powered down. The

comparator can be powered down by setting the comparator

power-down bit, CFR1<6> = 1.

2) The system must maintain synchronization with the

AD9954 or the internal control logic will not be able to

recognize further instructions. For example, if the system

sends an instruction byte that describes writing a 2-byte

register, then pulses the SCLK pin for a 3-byte write (24

additional SCLK rising edges), communication synchroni-

zation is lost. In this case, the first 16 SCLK rising edges

after the instruction cycle will properly write the first two

data bytes into the AD9954, but the next eight rising SCLK

edges are interpreted as the next instruction byte not the

final byte of the previous communication cycle. In the case

where synchronization is lost between the system and the

AD9954, the IOSYNC pin provides a means to re-establish

synchronization without re-initializing the entire chip. The

IOSYNC pin enables the user to reset the AD9954 state

machine to accept the next eight SCLK rising edges to be

coincident with the instruction phase of a new communi-

cation cycle. By applying and removing a high signal to the

IOSYNC pin, the AD9954 is set to once again begin per-

forming the communication cycle in synchronization with

the system. Any information that had been written to the

AD9954 registers during a valid communication cycle

prior to loss of synchronization will remain intact.

When the CFR1<3> bit is high, and the PWRDWNCTL input

pin is high, the AD9954 is put into the full power-down mode.

In this mode, all functions are powered down. This includes the

DAC and PLL, which take a significant amount of time to

power up.

When the PWRDWNCTL input pin is high, the individual

power-down bits (CFR1<7>, <5:4>) are invalid (Don’t Care)

and unused; however, the comparator power-down bit,

CFR1<6>, will continue to control the power-down of the com-

parator.When the PWRDWNCTL input pin is low, the individual

power-down bits control the power-down modes of operation.

Note that the power-down signals are all designed such that a

Logic 1 indicates the low power mode and a Logic 0 indicates

the active or powered up mode.

Rev. 0 | Page 33 of 36

AD9954

Layout Considerations

Table 13 indicates the logic level for each power-down bit that

drives out of the AD9954 core logic to the analog section and

the digital clock generation section of the chip for the external

power-down operation.

For the best performance, the following layout guidelines

should be observed. Always provide the analog power supply

(AVDD) and the digital power supply (DVDD) on separate

supplies, even if just from two different voltage regulators

driven by a common supply. Likewise, the ground connections

(AGND, DGND) should be kept separate as far back to the

source as possible (i.e., separate the ground planes on a local-

ized board, even if the grounds connect to a common point in

the system). Bypass capacitors should be placed as close to the

device pin as possible. Usually a multitiered bypassing scheme

consisting of a small high frequency capacitor (100 pF) placed

close to the supply pin and progressively larger capacitors

(0.1 µF, 10 µF) further back to the actual supply source works best.

Table 13. Power-Down Control Functions

Control

Mode Active

Description

PWRDWNCTL = 0 CFR1<3> Don’t Care

Software Control

Digital Power-Down = CFR1<7>

Comparator Power-Down = CFR1<6>

DAC Power-Down = CFR1<5>

Input Clock Power-Down = CFR1<4>

Digital Power-Down = 1’b1

Comparator Power-Down = 1’b0 Or CFR1<6>

DAC Power-Down = 1’b0

Input Clock Power-Down = 1’b0

Digital Power-Down = 1’b1

PWRDWNCTL = 1 CFR1<3> = 0

PWRDWNCTL = 1 CFR1<3> = 1

External Control,

Fast Recovery Power-Down Mode

External Control,

Full Power-Down Mode

Comparator Power-Down = 1’b1

DAC Power-Down = 1’b1

Input Clock Power-Down = 1’b1

Rev. 0 | Page 34 of 36

AD9954

SUGGESTED APPLICATION CIRCUITS

TUNING WORD

MODULATED/

DEMODULATED

SIGNAL

RF/IF INPUT

IOUT

LPF

AD9954 DDS

LPF

AD9954

ON-CHIP

REFCLK

COMPARATOR

Figure 29. Synchronized L.O. for Upconversion/Down Conversion

CMOS LEVEL CLOCK

Figure 31. Frequency Agile Clock Generator

PHASE

COMPARATOR

LOOP

FILTER

FREQUENCY

TUNING

WORD

PHASE

OFFSET

WORD 1

REF

SIGNAL

VCO

I/I-BAR

BASEBAND

REFCLK

FILTER

AD9954

IOUT

SAW

LPF

AD9954 DDS

CRYSTAL

IOUT

REFCLK

CRYSTAL OUT

SYNC OUT

TUNING

WORLD

RF OUT

SYNC IN

IOUT

Figure 30. Digitally Programmable Divide-by-N Function in PLL

LPF

AD9954 DDS

IOUT

REFCLK

Q/Q-BAR

BASEBAND

FREQUENCY

TUNING

WORD

PHASE

OFFSET

WORD 2

Figure 32. Two AD9954s Synchronized to Provide I and

Q Carriers with Independent Phase Offsets for Nulling

Rev. 0 | Page 35 of 36

AD9954

OUTLINE DIMENSIONS

9.00

BSC SQ

37

36

48

1

7.00

BSC SQ

EXPOSED

PAD

TOP VIEW

(PINS DOWN)

2.00

SQ

BOTTOM VIEW

(PINS UP)

12

25

24

13

0.50

BSC

0.27

0.22

0.17

VIEW A

1.20

MAX

1.05

1.00

0.95

7°

3.5°

0°

0.15

0.05

0.75

0.60

0.45

SEATING

PLANE

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-ABC

Figure 33. 48-Lead Thin Plastic Quad Flat Package, Exposed Pad [TQFP/EP] (SV-48)—Dimensions shown in millimeters

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

WARNING—Please note that this device in its current form does not meet Analog Devices’ standard requirements for ESD as

measured against the charged device model (CDM). As such, special care should be used when handling this product, especially in

a manufacturing environment. Analog Devices will provide a more ESD hardy product in the near future at which time this warn-

ing will be removed from this data sheet.

ORDERING GUIDE

AD9954 Products

Temperature Range

Package Description

Package Outline

SV-48

AD9954YSV

–40°C to +105°C

48-Lead Thin Plastic Quad Flat Package, Exposed Pad (TQFP/EP)

500 Device 7-Inch Reel of 48-Lead TQFP/EP

Evaluation Board

AD9954YSV-REEL7

AD9954/PCB

–40°C to +105°C

tered trademarks are the property of their respective owners.

C03374-0-10/03(0)

Rev. 0 | Page 36 of 36


型号：	AD9954YSVZ
厂家：	ADI
描述：	400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer
文件：	总36页 (文件大小：1299K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9954YSVZ [ADI]

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