AD9956XCPZ [ADI]
IC SPECIALTY ANALOG CIRCUIT, QCC48, 7 X 7 MM, MO-220-VKKD-2, LFCSP-48, Analog IC:Other;型号: | AD9956XCPZ |
厂家: | ADI |
描述: | IC SPECIALTY ANALOG CIRCUIT, QCC48, 7 X 7 MM, MO-220-VKKD-2, LFCSP-48, Analog IC:Other |
文件: | 总32页 (文件大小:441K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
2.7 GHz DDS-Based AgileRFTM Synthesizer
AD9956
3.3 V supply for I/O and charge pump
Software controlled power-down
48-lead LFCSP package
FEATURES
400 MSPS internal DDS clock speed
48-bit frequency tuning word
14-bit programmable phase offset
Integrated 14-bit DAC
Automatic linear frequency sweeping capability (in DDS)
Programmable charge pump current (up to 4 mA)
Phase modulation capability
Excellent dynamic performance
Multichip synchronization
Phase noise ≤ 135 dBc/Hz @ 1 KHz offset
−80 dB SFDR @ 160 MHz ( 100 KHz offset IOUT
25 Mb/s write-speed serial I/O control
200 MHz phase frequency detector inputs
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant driver
)
APPLICATIONS
655 MHz programmable input dividers for the phase
Agile LO frequency synthesis
frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 phase/frequency profiles
FM chirp source for radar and scanning systems
Automotive radars
Test and measurement equipment
Acousto-optic device drivers
1.8 V supply for device operation
FUNCTIONAL BLOCK DIAGRAM
DAC_RSET
DELTA
DDS CORE
PHASE TO
PHASE
OFFSET
48
FREQUENCY
TUNING WORD
FREQUENCY
ACCUMULATOR
IOUT
IOUT
19
14
AMPLITUDE
CONVERSION
DAC
PHASE
ACCUMULATOR
DELTA
FREQUENCY
RAMP RATE
FTW
48
PHASE
OFFSET
WORD
14
24
SYSCLK
SYSCLK
16
PLL_LOCK/SYNC_IN
I/O_UPDATE
I/O_RESET
TIMING AND CONTROL LOGIC
OSCILLATOR
LOCK
DETECT
CHARGE
PUMP
SCALER
SYSCLK
SYNC_CLK
SYNC_OUT
÷4
RF-DIVIDER
÷R
÷M
÷N
3
REFCLK
REFCLK
BUFFER
Φ
CHARGE
PUMP
CP_OUT
CML CLOCK DRIVER
3
BUFFER
FROM PLLOSC
DRV DRV DRV_RSET
RESET I/O PORT
CP_RSET
PS<2:0>
PLLREF/ PLLOSC/
PLLREF PLLOSC
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD9956
TABLE OF CONTENTS
Product Overview............................................................................. 3
CML Driver................................................................................. 19
Modes of Operation ....................................................................... 20
DDS Modes of Operation ......................................................... 20
Synchronization Modes for Multiple Devices.............................. 20
Serial Port Operation..................................................................... 22
Instruction Byte.......................................................................... 23
Serial Interface Port Pin Description....................................... 23
MSB/LSB Transfers .................................................................... 23
Register Map and Description...................................................... 24
Control Function Register Descriptions ................................. 27
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
Specifications..................................................................................... 4
Loop Measurement Conditions.................................................. 9
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Typical Application Circuits.......................................................... 16
Application Circuit Explanations............................................. 17
General Description....................................................................... 18
DDS Core..................................................................................... 18
PLL Circuitry .............................................................................. 18
REVISION HISTORY
9/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to the Pin Configuration................................................ 11
Changes to the Pin Function Descriptions ................................. 12
Changes to Table 5.......................................................................... 24
Changes to CFR2<15:12> PLLREF Divider
Control Bits (÷N)............................................................................ 31
Changes to CFR2<11:8> PLLREF Divider
Control Bits (÷M)........................................................................... 31
Changes to Ordering Guide .......................................................... 32
7/04—Revision: Initial Version
Rev. A | Page 2 of 32
AD9956
PRODUCT OVERVIEW
The AD9956 is Analog Devices’ newest AgileRF synthesizer.
The device is comprised of DDS and PLL circuitry. The DDS
features a 14-bit DAC operating at up to 400 MSPS and a 48-bit
frequency tuning word (FTW). The PLL circuitry includes a
phase frequency detector with scaleable 200 MHz inputs
(divider inputs operate up to 655 MHz) and digital control over
the charge pump current. The device also includes a 655 MHz
CML-mode PECL-compliant driver with programmable slew
rates. The AD9956 uses advanced DDS technology, an internal
high speed, high performance DAC, and an advanced phase
frequency detector/charge pump combination, which, when
used with an external VCO, enables the synthesis of digitally
programmable, frequency-agile analog output sinusoidal wave-
forms up to 2.7 GHz. The AD9956 is designed to provide fast
frequency hopping and fine tuning resolution (48-bit frequency
tuning word). Information is loaded into the AD9956 via a
serial I/O port that has a device write-speed of 25 Mb/s. The
AD9956 DDS block also supports a user-defined linear sweep
mode of operation.
The AD9956 is specified to operate over the extended
automotive range of −40°C to +125°C.
Rev. A | Page 3 of 32
AD9956
SPECIFICATIONS
AVDD = DVDD = 1.8 V 5ꢀ; DVDD_I/O = CP_VDD = 3.3 V 5ꢀ (@ TA = 25°C) DAC_RSET = 3.92 kΩ, CP_RSET = 3.09 kΩ,
DRV_RSET = 4.02 kΩ, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RF DIVIDER (REFCLK ) INPUT SECTION (÷R)
RF Divider Input Range
1
2700
MHz
DDS SYSCLK not to exceed
400 MSPS
Input Capacitance (DC)
Input Impedance (DC)
Input Duty Cycle
Input Power/Sensitivity
Input Voltage Level
3
pF
Ω
%
dBm
mV p-p
1500
50
42
−10
350
58
+4
1000
Single-ended, into a 50 Ω load1
PHASE FREQUENCY DETECTOR/CHARGE PUMP
PLLREF Input
Input Frequency2
÷M Set to Divide by at Least 4
÷M Bypassed
Input Voltage Levels
Input Capacitance
Input Resistance
PLLOSC Input
Input Frequency
÷N Set to Divide by at Least 4
÷N Bypassed
Input Voltage Levels
655
200
600
10
MHz
MHz
mV p-p
pF
200
200
450
1500
Ω
655
200
600
10
MHz
MHz
mV p-p
pF
450
Input Capacitance
Input Resistance
1500
Ω
Charge Pump Source/Sink Maximum Current
Charge Pump Source/Sink Accuracy
Charge Pump Source/Sink Matching
Charge Pump Output Compliance Range3
PLL_LOCK Drive Strength
PHASE FREQUENCY DETECTOR NOISE FLOOR
@ 50 kHz PFD Frequency
@ 2 MHz PFD Frequency
@ 100 MHz PFD Frequency
@ 200 MHz PFD Frequency
CML OUTPUT DRIVER (DRV)
Differential Output Voltage Swing4
Maximum Toggle Rate
Common-Mode Output Voltage
Output Duty Cycle
4
+5
+5
mA
%
%
V
mA
−15
−5
0.5
CP_VDD − 0.5
2
149
133
116
113
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
720
mV
MHz
V
50 Ω load to supply, both lines
655
42
1.75
50
58
%
Output Current
Continuous5
Rising Edge Surge
Falling Edge Surge
Output Rise Time
7.2
mA
mA
mA
ps
20.9
13.5
250
100 Ω terminated, 5 pF load
Rev. A | Page 4 of 32
AD9956
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS (SDI/O, I/O_RESET, RESET,
I/O_UPDATE, PS0 to PS2, SYNC_IN)
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL Input Current
CIN, Maximum Input Capacitance
LOGIC OUTPUTS (SDO, SYNC_OUT, PLL_LOCK)6
VOH, Output High Voltage
VOH, Output Low Voltage
IOH
2.0
V
V
µA
pF
0.8
5
1
3
2.7
V
V
µA
µA
0.4
100
100
IOL
POWER CONSUMPTION
Total Power Consumed, All Functions On
IAVDD
IDVDD
IDVDD_I/O
400
85
45
20
15
mW
mA
mA
mA
mA
mW
ICP_VDD
Power-Down Mode
80
WAKE-UP TIME (from Power-Down Mode)
Digital Power-Down (CFR1<7>)
DAC Power-Down (CFR2<39>)
RF Divider Power-Down (CFR2<23>)
Clock Driver Power-Down (CFR2<20>)
Charge Pump Full Power-Down (CFR2<4>)
Charge Pump Quick Power-Down (CFR2<3>)
DAC OUTPUT CHARACTERISTICS
Resolution
12
7
400
6
10
150
ns
µs
ns
µs
µs
ns
14
10
Bits
mA
% FS
µA
Full-Scale Output Current
Gain Error
Output Offset
15
+10
0.6
−10
Output Capacitance
5
pF
Voltage Compliance Range
Wideband SFDR (DC to Nyquist)
10 MHz Analog Out
40 MHz Analog Out
80 MHz Analog Out
AVDD − 0.50
AVDD + 0.50
V
−64
−62
−60
−55
−55
dBc
dBc
dBc
dBc
dBc
120 MHz Analog Out
160 MHz Analog Out
Narrowband SFDR
10 MHz Analog Out ( 1 MHz)
10 MHz Analog Out ( 250 kHz)
10 MHz Analog Out ( 50 kHz)
40 MHz Analog Out ( 1 MHz)
40 MHz Analog Out ( 250 kHz)
40 MHz Analog Out ( 50 kHz)
80 MHz Analog Out ( 1 MHz)
80 MHz Analog Out ( 250 kHz)
80 MHz Analog Out ( 50 kHz)
120 MHz Analog Out ( 1 MHz)
120 MHz Analog Out ( 250 kHz)
120 MHz Analog Out ( 50 kHz)
−89
−91
−93
−87
−89
−91
−85
−87
−89
−83
−85
−87
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Rev. A | Page 5 of 32
AD9956
Parameter
Min
Typ
−81
−83
−85
Max
Unit
dBc
dBc
dBc
Test Conditions/Comments
160 MHz Analog Out ( 1 MHz)
160 MHz Analog Out ( 250 kHz)
160 MHz Analog Out ( 50 kHz)
DAC Residual Phase Noise
19.7 MHz FOUT
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
125
135
143
152
158
163
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
51.84 MHz FOUT
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
119
125
132
142
150
155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
105.3 MHz Analog Out
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
105
115
122
131
139
142
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@ 100 kHz Offset
>1 MHz Offset
155.52 MHz Analog Out
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
105
110
119
127
135
142
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@ 100 kHz Offset
>1 MHz Offset
CRYSTAL OSCILLATOR (ON PLLREF INPUT)
Operating Range
Residual Phase Noise (@ 25 MHz)
@ 10 Hz Offset
20
25
30
MHz
95
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
120
137
156
164
170
DIGITAL TIMING SPECIFICATIONS
CS
6
ns
ns
ns
ns
ns
ns
ns
ns
to SCLK Setup Time TPRE
Period of SCLK (Write Speed) TSCLKW
Period of SCLK (Read Speed) TSCLKR
Serial Data Setup Time TDSU
Serial Data Hold Time TDHLD
TDV Data Valid Time TDV
40
400
6.5
0
40
7
I/O Update to SYNC_CLK Setup Time TUD
PS<2:0> to SYNC_CLK Setup Time TPS
7
Rev. A | Page 6 of 32
AD9956
Parameter
Latencies/Pipeline Delays7
Min
Typ
Max
Unit
Test Conditions/Comments
I/O Update to DAC Frequency Change
I/O Update to DAC Phase Change
PS<2:0> to DAC Frequency Change
PS<2:0> to DAC Phase Change
I/O Update to CP_OUT Scaler Change
33
33
29
29
4
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
I/O Update to Frequency Accumulator
Step Size Change
4
I/O Update to Frequency Accumulator
Ramp Rate Change
4
SYSCLK Cycles
RF DIVIDER/CML DRIVER EQUIVALENT
INTRINSIC TIME JITTER
FIN = 414.72 MHz, FOUT = 51.84 MHz
BW = 12 kHz −> 400 kHz
FIN = 1244.16 MHz, FOUT = 155.52 MHz
BW = 12 kHz −> 1.3 MHz
FIN = 2488.32 MHz, FOUT = 622.08 MHz
136
101
108
fS rms
fS rms
fS rms
OC1, RF Divider R = 8
OC3, RF Divider R = 8
OC12, RF Divider R = 4
RF Divider R = 8
BW = 12 kHz −> 5 MHz
RF DIVIDER/CML DRIVER RESIDUAL PHASE NOISE
FIN = 157.6 MHz, FOUT = 19.7 MHz
@ 10 Hz
@ 100 Hz
@ 1 kHz
@ 10 kHz
@ 100 kHz
> 1 MHz
−115
−126
−134
−143
−150
−151
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
FIN = 1240 MHz, FOUT = 155 MHz
RF Divider R = 8
@ 10 Hz
@ 100 Hz
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
>3 MHz
−111
−122
−129
−138
−146
−150
−153
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
FIN = 2488MHz, FOUT = 622 MHz
RF Divider R = 4
@ 10 Hz
@ 100 Hz
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
>3 MHz
−97
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−110
−120
−126
−136
−141
−144
TOTAL SYSTEM TIME JITTER FOR 622 MHz CLOCK
See the Loop Measurement Condi-
tions section
12 kHz to 5 MHz Bandwidth
0.7
ps rms
Rev. A | Page 7 of 32
AD9956
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TOTAL SYSTEM JITTER AND PHASE NOISE FOR
105.33 MHz ADC CLOCK GENERATION CIRCUIT
See the Loop Measurement Condi-
tions section
Converter Limiting Jitter
Resultant SNR
0.53
67
ps rms
dB
Phase Noise of Fundamental
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
−75
−87
−93
−105
−145
−152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@ 100 kHz Offset
@ ≥1 MHz Offset
1 The input impedance of the REFCLK input is 1500 Ω. However, in order to provide matching on the clock line, an external 50 Ω load is used.
2 Driving the PLLREF input buffer, the crystal oscillator section of this input stage performs up to only 30 MHz.
3 The charge pump output compliance range is functionally 0.2 V to (CP_VDD − 0.2 V). The value listed here is the compliance range for 5% matching.
4
DRV
Measured as peak-to-peak from DRV to
.
5 For a 4.02 kΩ resistor from DRV_RSET to GND.
6 Assumes a 1 mA load.
7 I/O_UPDATE/PS<2:0> are detected by the AD9956 synchronous to the rising edge of SYNC_CLK. Each latency measurement is from the first SYNC_CLK rising edge
after the I/O_UPDATE/PS<2:0> state change.
Rev. A | Page 8 of 32
AD9956
LOOP MEASUREMENT CONDITIONS
622 MHz OC-12 Clock
105 MHz Converter Clock
VCO = Sirenza 190-640T
VCO = Sirenza 190-845T
Reference = Wenzel 500-10116 (30.3 MHz)
Loop Filter = 10 kHz BW, 60° Phase Margin
Reference = Wenzel 500-10116 (30.3 MHz)
Loop Filter = 10 kHz BW, 45° Phase Margin
C1 = 170 nF, R1 = 14.4 Ω, C2 = 5.11 µF, R2 = 89.3 Ω,
C3 Omitted
C1 = 117 nF, R1 = 28 Ω, C2 = 1.6 µF, R2 = 57.1 Ω, C3 = 53.4 nF
CP_OUT = 4 mA (Scaler = ×8)
CP_OUT = 4 mA (Scaler = ×8)
÷R = 2, ÷M = 1, ÷N = 1
÷R = 8, ÷M = 1, ÷N = 1
R2
INPUT
OUTPUT
R1
C2
C1
C3
Figure 2. Generic Loop Filter
Rev. A | Page 9 of 32
AD9956
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
2 V
2 V
Analog Supply Voltage (AVDD)
Digital Supply Voltage (DVDD)
Digital I/O Supply Voltage
(DVDD_I/0)
3.6 V
Charge Pump Supply Voltage
(CPVDD)
3.6 V
Maximum Digital Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
−0.5 V to DVDD_I/O + 0.5 V
−65°C to +150°C
−40°C to +125°C
300°C
Junction Temperature
Thermal Resistance (θJA)
150°C
26°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-
trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
or loss of functionality.
Rev. A | Page 10 of 32
AD9956
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND
AVDD
1
2
3
4
5
6
7
8
9
36 CP_OUT
35 CP_VDD
34 AGND
33 DRV
PIN 1
INDICATOR
AGND
AVDD
IOUT
32 DRV
IOUT
31 CP_VDD
30 AGND
29 REFCLK
28 REFCLK
27 AVDD
26 AGND
25 DVDD
AD9956
AVDD
TOP VIEW
(Not to Scale)
AGND
I/O_RESET
RESET 10
DVDD 11
DGND 12
NC = NO CONNECT
Figure 3. 48-Lead LFCSP Pin Configuration
Note that the exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. For the device to
function properly, the paddle MUST be attached to analog ground.
Rev. A | Page 11 of 32
AD9956
Table 3. 48-Lead LFCSP Pin Function Description
Pin No.
Mnemonic
Description
1, 3, 8, 26, 30,
34, 37, 43, 49
AGND
Analog Ground.
2, 4, 7, 27, 38,
44, 48
AVDD
Analog Core Supply (1.8 V).
5
6
9
IOUT
IOUT
DAC Analog Output.
DAC Analog Complementary Output.
I/O_RESET
Resets the serial port when synchronization is lost in communications but does not reset the de-
vice itself (ACTIVE HIGH). When not being used, this pin should be forced low, because it floats to
the threshold value.
10
RESET
Master RESET. Clears all accumulators and returns all registers to their default values (ACTIVE
HIGH).
11, 25
12, 24
13
DVDD
DGND
SDO
Digital Core Supply (1.8 V).
Digital Ground.
Serial Data Output. Used only when device is programmed for 3-wire serial data mode.
14
SDI/O
Serial Data I/O. When the part is programmed for 3-wire serial data mode, this is input only; in
2-wire mode, it serves as both the input and output.
15
16
SCLK
CS
Serial Data Clock. Provides the clock signal for the serial data port.
Active Low Signal That Enables Shared Serial Busses. When brought high, the serial port ignores
the serial data clocks.
17
18
19
DVDD_I/O
SYNC_OUT
Digital Interface Supply (3.3 V).
Synchronization Clock Output.
PLL_LOCK/SYNC_IN Bidirectional Dual Function Pin. Depending on device programming, it is either the DDS’ synchro-
nization input (allows alignment of multiple subclocks) or the PLL lock detect output signal.
20
I/O_UPDATE
This input pin, when set high, transfers the data from the I/O buffers to the internal registers on the
rising edge of the internal SYNC_CLK, which can be observed on SYNC_OUT.
21 to 23
PS0 to PS2
Profile Select Pins. Specify one of eight frequency tuning word/phase offset word profiles. In linear
sweep mode, PS0 determines the state of the sweep. In linear sweep no dwell mode, PS0 is a trig-
ger that initiates the sweep. PS1 and PS2 have no function during linear sweep mode or linear
sweep no dwell mode.
28
REFCLK
REFCLK
DRV
RF Divider and DDS REFCLK Complementary Input.
RF Divider and DDS REFCLK Input.
CML Driver Complementary Output.
CML Driver Output.
29
32
33
DRV
31, 35
CP_VDD
Charge Pump Supply Pin (3.3 V). To minimize noise on the charge pump, isolate this supply from
DVDD_I/O.
36
39
40
41
42
45
46
47
CP_OUT
PLLREF
PLLREF
Charge Pump Output.
Phase Frequency Detector Reference Input.
Phase Frequency Detector Reference Complementary Input.
Phase Frequency Detector Oscillator (Feedback) Complementary Input.
Phase Frequency Detector Oscillator (Feedback) Input.
Charge Pump Current Set (Program Charge Pump Current with a Resistor to AGND).
CML Driver Output Current Set (Program CML Output Current with a Resistor to AGND).
DAC Output Current Set (Program DAC Output Current with a Resistor to AGND).
PLLOSC
PLLOSC
CP_RSET
DRV_RSET
DAC_RSET
Note that the exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. In order for the
device to function properly, the paddle MUST be attached to analog ground.
Rev. A | Page 12 of 32
AD9956
TYPICAL PERFORMANCE CHARACTERISTICS
DELTA 1 [T1]
–84.82dB
RBW 500Hz RF ATT
VBW 500Hz
DELTA 1 [T1]
–67.45dB
74.50901804MHz
RBW 10kHz RF ATT
VBW 10kHz
20dB
dB
20dB
dB
A
REF LVL
0dBm
REF LVL
0dBm
–404.80961924kHz
SWT
20s UNIT
SWT
4.3s UNIT
0
–10
–20
–30
0
–10
–20
–30
1
1
A
–40
–50
–60
–70
–40
–50
–60
–70
1 AP
1 AP
1
–80
–90
–80
–90
1
–100
–100
CENTER 10.1MHz
100kHz/
SPAN 1MHz
START 0Hz
16.9MHz/
STOP 169MHz
Figure 4. AD9956 DAC Performance: 400 MSPS Clock,
10 MHz FOUT, 1 MHz Span
Figure 7. AD9956 DAC Performance: 400 MSPS Clock,
10 MHz FOUT, 200 MHz Span
DELTA 1 [T1]
–78.67dB
–100.20040080kHz
RBW 500Hz RF ATT
VBW 500Hz
DELTA 1 [T1]
–62.65dB
100.20040080MHz
RBW 10kHz RF ATT
VBW 10kHz
20dB
dB
20dB
dB
REF LVL
0dBm
REF LVL
0dBm
SWT
20s UNIT
SWT
5s UNIT
0
–10
–20
–30
0
–10
–20
–30
1
1
A
A
–40
–50
–60
–70
–40
–50
–60
–70
1 AP
1 AP
1
–80
–90
–80
–90
1
–100
–100
CENTER 40.1MHz
100kHz/
SPAN 1MHz
START 0Hz
20MHz/
STOP 200MHz
Figure 5. AD9956 DAC Performance: 400 MSPS Clock,
40 MHz FOUT, 1 MHz Span
Figure 8. AD9956 DAC Performance: 400 MSPS Clock,
40 MHz FOUT, 200 MHz Span
DELTA 1 [T1]
–48.78dB
–400.80160321kHz
RBW 10kHz RF ATT
VBW 10kHz
20dB
dB
DELTA 1 [T1]
–57.74dB
–400.80160321kHz
RBW 500Hz RF ATT
VBW 500Hz
20dB
dB
REF LVL
0dBm
REF LVL
0dBm
SWT
5s UNIT
SWT
20s UNIT
0
–10
–20
–30
0
–10
–20
–30
1
1
A
A
–40
–50
–60
–70
–40
–50
–60
–70
1 AP
1 AP
1
1
–80
–90
–80
–90
–100
–100
START 0Hz
20MHz/
STOP 200MHz
CENTER 100.1MHz
100kHz/
SPAN 1MHz
Figure 9. AD9956 DAC Performance: 400 MSPS Clock,
100 MHz FOUT, 200 MHz Span
Figure 6. AD9956 DAC Performance: 400 MSPS Clock,
100 MHz FOUT, 1 MHz Span
Rev. A | Page 13 of 32
AD9956
DELTA 1 [T1] RBW 500kHz RF ATT
–78.13dB VBW 500kHz
DELTA 1 [T1]
–56.33dB
–80.96192385MHz
RBW 10kHz RF ATT
VBW 10kHz
20dB
dB
20dB
dB
REF LVL
0dBm
REF LVL
0dBm
–100.20040080kHz SWT
20s UNIT
SWT
5s UNIT
0
–10
–20
–30
0
–10
–20
–30
1
1
A
A
–40
–50
–60
–70
–40
–50
–60
–70
1 AP
1 AP
1
–80
–90
–80
–90
1
–100
–100
CENTER 159.5MHz
100kHz/
SPAN 1MHz
START 0Hz
20MHz/
STOP 200MHz
Figure 10. AD9956 DAC Performance: 400 MSPS Clock,
160 MHz FOUT, 1 MHz Span
Figure 13. AD9956 DAC Performance: 400 MSPS Clock,
160 MHz FOUT, 200 MHz Span
0
0
–10
–10
–20
–30
–40
–50
–60
–70
–80
–90
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. AD9956 DDS/DAC Residual Phase Noise
400 MHz Clock, 10 MHz Output
Figure 14. AD9956 DDS/DAC Residual Phase Noise
400 MHz Clock, 103 MHz Output
0
–10
0
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12. AD9956 DDS/DAC Residual Phase Noise
400 MHz Clock, 40 MHz Output
Figure 15. AD9956 DDS/DAC Residual Phase Noise
400 MHz Clock, 159 MHz Output
Rev. A | Page 14 of 32
AD9956
0
–10
0
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16. RF Divider and CML Driver Residual
Phase Noise (840 MHz In, 105 MHz Out)
Figure 19. RF Divider and CML Driver Residual
Phase Noise (2488 MHz In, 622 MHz Out)
0
–10
0
–10
–20
–20
–30
–30
–40
–50
–40
–50
–60
–60
–70
–80
–90
–100
–110
–120
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–130
–140
–150
–160
–170
–180
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. RF Divider and CML Driver Residual
Phase Noise (1240 MHz In, 155 MHz Out)
Figure 20. Total System Phase Noise for 105 MHz Converter Clock
0
–10
0
–10
–20
–20
–30
–40
–50
–30
–40
–50
–60
–60
–70
–80
–90
–100
–110
–120
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–130
–140
–150
–160
–170
–180
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21. Total System Phase Noise for 622 MHz OC-12 Clock
Figure 18. RF Divider and CML Driver Residual
Phase Noise (1680 MHz In, 210 MHz Out)
Rev. A | Page 15 of 32
AD9956
TYPICAL APPLICATION CIRCUITS
PHASE FREQUENCY
DETECTOR/CHARGE PUMP
25MHz
CRYSTAL
÷M
÷N
PLLREF
400MHz
VCO
CP_OUT
PLLOSC
LPF
CML
DRIVER
÷R
CLOCK1
AD9956
DAC
DDS
CLOCK1′
LPF
Figure 22. Dual-Clock Configuration
PLLREF
CP_OUT
PLLOSC
VCO
LPF
DAC
DDS
÷R
LPF
AD9956
Figure 23. Fractional-Divider Loop
8-LEVEL FSK
(FC = 100MHz)
DAC
CML
DDS
DRIVER
BPF
÷R
AD9956
BPF
PLLREF
25MHz
CRYSTAL
2.5GHz
TONE
CP_OUT
PLLOSC
VCO
LPF
÷N
Figure 24. LO and Baseband Modulation Generation
Rev. A | Page 16 of 32
AD9956
PHASE FREQUENCY
DETECTOR
EXTERNAL
REFERENCE
÷M
REF
OSC
622MHz
VCO
CHARGE
PUMP
÷N
LPF
CML
DRIVER
÷R
CLOCK1
CLOCK2
AD9956
DAC
DDS
Figure 25. Optical Networking Clock
PHASE
FREQUENCY
DETECTOR
DAC
DDS
PLLREF
LPF
≤650MHz
CHARGE
PUMP
VCO
PLLOSC
÷N
LPF
Figure 26. Direct Upconversion
LO and Baseband Modulation Generation
APPLICATION CIRCUIT EXPLANATIONS
Using the AD9956’s PLL section to generate an LO and the
DDS portion to generate a modulated baseband, this circuit
uses an external mixer to perform some simple modulation at
RF frequencies (see Figure 24).
Dual-Clock Configuration
In this loop, M = 1, N = 16, and R = 4. The DDS tuning word is
also equal to ¼ so that the frequency of CLOCK 1’ equals the
frequency of CLOCK 1. Phase adjustments in the DDS provide
a 14-bit programmable rising edge skew capability of CLOCK 1’
with respect to CLOCK 1 (see Figure 22).
Optical Networking Clock
This is the AD9956 configured as an optical networking clock.
The loop can be used to generate a 622 MHz clock for OC12.
The DDS can be programmed to output 8 kHz to serve as a base
reference for other circuits in the subsystem (see Figure 25).
Fractional-Divider Loop
This loop offers the precise frequency division (48-bit) of the
DDS in the feedback path as well as the frequency sweeping
capability of the DDS. Programming the DDS to sweep from
24 MHz to 25 MHz sweeps the output of the VCO from
2.7 GHz to 2.6 GHz. The reference in this case is a simple
crystal (see Figure 23).
Direct Upconversion
The AD9956 is configured to use the DDS as a precision refer-
ence to the PLL loop. Since the VCO is < 655 MHz, it can be fed
straight into the phase frequency detector feedback input (with
the divider enabled), as seen in Figure 26.
Rev. A | Page 17 of 32
AD9956
GENERAL DESCRIPTION
The RF divider accepts differential or single-ended signals up to
2.7 GHz. The RF divider also supplies the SYSCLK input to the
DDS. Because the DDS operates up to only 400 MSPS, device
function requires that for any RF input signal > 400 MHz, the
RF divider be engaged. The RF divider can be programmed to
take values of 1, 2, 4, or 8. The ratio for the divider is pro-
grammed in the control register. The output of the divider can
be routed to the input of the on-chip CML driver. For lower
frequency input signals, it is possible to use the divider to divide
the input signal to the CML driver and use the undivided input
of the divider as the SYSCLK input to the DDS, or vice versa. In
all cases, the clock to the DDS should not exceed 400 MSPS.
DDS CORE
The DDS can create digital phase relationships by clocking a
48-bit accumulator. The incremental value loaded into the
accumulator, known as the frequency tuning word, controls the
overflow rate of the accumulator. Similar to a sine wave com-
pleting a 2π radian revolution, the overflow of the accumulator
is cyclical in nature and generates a base frequency according to
the following equation.
FTW ×( fs )
fo =
{0 ≤ FTW ≤ 247}
248
The instantaneous phase of the sine wave is, therefore, the out-
put of the phase accumulator block. This signal can be phase-
offset by programming an additive digital phase added to each
and every phase sample coming out of the accumulator.
The on-chip phase frequency detector has two differential
inputs, PLLREF (the reference input) and PLLOSC (the feed-
back or oscillator input). These differential inputs can be driven
by single-ended signals; however, when doing so, tie the unused
input through a 100 pF capacitor to the analog supply (AVDD).
The maximum speed of the phase frequency detector inputs is
200 MHz. Each of the inputs has a buffer and a divider (÷M on
PLLREF and ÷N on PLLOSC) that operates at up to 655 MHz.
If the signal exceeds 200 MHz, however, the divider must be
used. The dividers are programmed through the control registers
and take any integer value between 1 and 16.
These instantaneous phase values are then piped through a
phase-to-amplitude conversion (sometimes called an angle-
to-amplitude conversion or AAC) block. This algorithm follows
a COS(x) relationship where x is the phase coming out of the
phase offset block, normalized to 2π.
Finally, the amplitude words are piped to a 14-bit DAC. Because
the DAC is a sampled data system, the output is a reconstructed
sine wave that needs to be filtered to take high frequency
images out of the spectrum. The DAC is a current-steering
DAC that is AVDD referenced. To get a measurable voltage
output, the DAC outputs must terminate through a load resistor
to AVDD, typically 50 Ω. At positive full scale, IOUT sinks no
current and the voltage drop across the load resistor is zero.
The PLLREF input also has the option of engaging an in-line
oscillator circuit. Engaging this circuit means that the PLLREF
input can be driven with a crystal in the of 20 MHz ≤ PLLREF ≤
30 MHz range.
The charge pump outputs a current in response to an error
signal generated in the phase frequency detector. The output
current is programmed through by placing a resistor (CP_RSET
from the CP_RSET pin to ground. The value is dictated by the
following equation:
IOUT
However, the
output sinks the DAC’s programmed full-
)
scale output current, causing the maximum output voltage to
drop across the load resistor. At negative full-scale, the situation
is reversed and IOUT sinks the full-scale current (and generates
the maximum drop across the load resistor). At the same time,
1.55
CP_R
SET
CP_OUT =
IOUT
sinks no current (and generates no voltage drop). At
midscale, the outputs sink equal amounts of current, generating
equal voltage drops.
This sets the charge pump’s reference output current. Also, a
programmable scaler multiplies this base value by any integer
from 1 to 8, programmable through the CP current scale bits in
the Control Function Register 2, CFR2<2:0>.
PLL CIRCUITRY
The AD9956 includes an RF divider (divide-by-R), a phase
frequency detector, and a programmable output current charge
pump. Incorporating these blocks together, users can generate
many useful circuits for frequency synthesis. A few simple
examples are shown in the Typical Application Circuits.
Rev. A | Page 18 of 32
AD9956
CML DRIVER
For clocking applications, an on-chip current mode logic
(CML) driver is included. This CML driver generates very low
jitter clock edges. The outputs of the CML driver are current
outputs and drives PECL levels when terminated into a 100 Ω
load. The base output current of the driver is programmed by
attaching a resistor from the DRV_RSET pin to ground (nomi-
nally 4.02 kΩ for a continuous current of 7.2 mA). An optional
on-chip current programming resistor is enabled by setting a bit
in the control register. The rising edge and falling edge slew
rates are independently programmable to help control over-
shoot and ringing through the application of surge current
during rising edge transitions and falling edge transitions (see
Figure 27). There is a default surge current of 7.6 mA on the
rising edge and 4.05 mA on the falling edge. Bits in the control
register enable additional rising edge and falling edge surge
current, as well disable the default surge current (see the
Control Function Register Descriptions section for details). The
CML driver can be driven by the
RISING EDGE SURGE
CONTINUOUS
I(t)
CONTINUOUS
FALLING EDGE SURGE
t
~250ps
~250ps
•
•
•
RF divider input
RF divider output
PLLOSC input
Figure 27. Rising Edge and Falling Edge Surge Current Output of the
CML Clock Driver, as Opposed to the Steady State Continuous Current
Rev. A | Page 19 of 32
AD9956
MODES OF OPERATION
If a sweep is interrupted and the state of the PS0 pin is changed
during the midst of a sweep, the part begins sweeping in the
new direction at the rate dictated by the relevant delta fre-
quency tuning word and sweep ramp rate word. For example, if
the part is programmed to sweep from 100 MHz to 140 MHz
and to take 1 kHz steps every 1000 sync clock cycles (rising and
falling sweep words are the same), it would take four seconds to
complete a sweep. If the PS0 has been low for a very long time
(more than four seconds), changing the PS0 pin to high starts a
sweep up to 140 MHz. If after two seconds (not enough time for
a full sweep in this example) the PS0 pin is brought low again,
the part begins sweeping down from the current value, roughly
120 MHz.
DDS MODES OF OPERATION
Single-Tone Mode
This is the default mode of operation for the DDS core. The
phase accumulator runs at a fixed frequency, as per the active
profile’s tuning word. Likewise, any phase offset applied to the
signal is a static value, which comes from the phase offset word
of the active profile. The device has eight different phase/fre-
quency profiles, each with its own 48-bit frequency tuning word
and 14-bit phase offset word. Profiles are selected by applying
their digital value on the profile-select pins (PS2, PS1, and PS0).
It is impossible to use the phase offset of one profile and the
frequency tuning word of another.
Linear Sweep Mode
Linear Sweep No Dwell Mode
This mode is entered by setting the linear sweep enable bit in
the control register (CFR1<17> = 1) but leaving the linear
sweep no dwell bit clear (CFR1<16> = 0). When the part is in
linear sweep mode, the frequency accumulator ramps the
output frequency of the device from a programmed lower
frequency to a programmed upper frequency or from the upper
frequency to the lower frequency. The lower frequency is set by the
frequency tuning word stored in Profile 0, and the upper frequency
is set by the frequency tuning word stored in Profile 1.
This mode is entered by setting the linear sweep enable bit and
the linear sweep no dwell bit in the control register
(CFR<17:16> =1). When the part is in linear sweep no dwell
mode, the frequency accumulator ramps the output frequency
of the device from a programmed lower frequency to a pro-
grammed upper frequency. Upon reaching the upper frequency,
the accumulator returns to the lower frequency directly, without
ramping back down. Unlike the default mode of the linear
sweep, this mode uses only the rising delta frequency tuning
word (RDFTW) and the rising sweep ramp rate (RSRR). The
operation is still controlled by the PS0 pin. In this mode, how-
ever, it acts as a trigger for the sweep, not a direction bit. Once a
PS0 low-to-high transition is detected, the part completes the
entire sweep, regardless of whether or not the PS0 pin is
changed back to low during the sweep. After the sweep is com-
pleted, another sweep may be initiated by applying another
rising edge on the PS0 pin. This means that the PS0 pin needs to
be brought low prior to the next sweep.
The combinational logic within the frequency accumulator
requires that the value stored at FTW0 must always be less than
the value stored in FTW. The direction of the sweep (sweep up
to FTW1, sweep down to FTW0) is controlled by the PS0 pin. A
high state on this pin tells the part to sweep up to FTW1. A low
state on this pin tells the part to sweep down to FTW0. The
frequency accumulator requires four values, which are stored in
the register map. First, it requires an incremental frequency
value that tells the frequency accumulator how big of a fre-
quency step to take each time it takes a step when ramping up.
This value is stored in the rising delta frequency tuning word
(RDFTW). The second value required is the rate at which the
frequency accumulator should increment, that is, how often it
should take a step. This value is stored in the rising sweep ramp
rate word (RSRR). The RSRR value specifies the number of
SYNC_CLK cycles the frequency accumulator should count
between steps. The third and fourth values are the falling ramp
equivalents, the falling delta frequency tuning word (FDFTW)
and the falling sweep ramp rate (FSRR).
SYNCHRONIZATION MODES FOR MULTIPLE DEVICES
In a DDS system, the SYNC_CLK is derived internally off the
master system clock, SYSCLK, with a ÷4 divider. Because the
divider does not power up to a known state, it is possible for
multiple devices in a system to have staggered clock-phase
relationships. This is because each device could potentially gen-
erate the SYNC_CLK rising edge from any one of four rising
edges of SYSCLK. This ambiguity can be resolved by employing
digital synchronization logic to control the phase relationships
of the derived clocks among different devices in the system. It is
important to note that the synchronization functions included
on the AD9956 control only the timing relationships among
different digital clocks. They do not compensate for the analog
timing skew on the system clock due to mismatched phase
relationships on the input clock, REFCLK. Figure 28 illustrates
this concept.
When operating in the linear sweep default mode, combina-
tional logic ensures that the part never ramps up past FTW1,
even if the next RDFTW increments the frequency past FTW1.
Once it reaches FTW1, as long as the PS0 pin stays high, the
frequency remains at FTW1. Likewise, the internal logic ensures
that the part never ramps down past FTW0, even if the next
RDFTW increments the frequency past FTW0. During a sweep
down (PS0 = 0), once the part reaches FTW0, as long as the PS0
pin stays low, the frequency remains at FTW0.
Rev. A | Page 20 of 32
AD9956
Automatic Synchronization
Manual Synchronization, Software Controlled
In automatic synchronization mode, the device is placed into
slave mode and automatically aligns the internal SYNC_CLK to
a master SYNC_CLK signal, supplied on the SYNC_IN input.
When this bit is enabled, the PLL_LOCK is not available as an
output, however, an out-of-lock condition can be detected by
reading Control Function Register 1 and checking the status of
the PLL_LOCK_ERROR bit, CFR1<24>. The automatic
synchronization function is enabled by setting the Control
Function Register 1 automatic synchronization bit, CFR1<3>.
To employ this function at higher clock rates (SYNC_CLK >
62.5 MHz and SYSCLK > 250 MHz), the high speed sync
enable bit (CFR1<0>) should be set as well.
In this mode, the user controls the timing relationship between
SYNC_CLK and SYSCLK through software programming.
When the software manual synchronization bit (CFR1<2>) is
set high, the SYNC_CLK is advanced by one SYSCLK cycle.
Once this operation is complete, the bit is cleared. The user can
set this bit repeatedly to advance the SYNC_CLK rising edge
multiple times. Because the operation does not use the
PLL_LOCK/ SYNC_IN pin as a SYNC_IN input, the
PLL_LOCK signal can be monitored on the PLL_LOCK pin
during this operation.
SYNCHRONIZATION FUNCTIONS CAN ALIGN DIGITAL CLOCK
RELATIONSHIPS, THEY CANNOT DESKEW THE EDGES OF CLOCKS
Manual Synchronization, Hardware Controlled
In this mode, the user controls the timing relationship of the
SYNC_CLK with respect to SYSCLK. When hardware manual
synchronization is enabled, the PLL_LOCK/ SYNC_IN pin
becomes a digital input. For each and every rising edge detected
on the SYNC_IN input, the device advances the SYNC_IN
rising edge by one SYSCLK period. When this bit is enabled, the
PLL_LOCK is not available as an output. However, an out-of-
lock condition can be detected by reading Control Function
Register 1 and checking the status of the PLL Lock Error bit,
CFR1<24>. This synchronization function is enabled by setting
the hardware manual synchronization enable bit, CFR1<1>.
2
SYSCLK DUT 1
0
1
3
0
SYNC CLK
DUT1
SYSCLK DUT 2
3
0
1
2
3
SYNC CLK DUT2 WITHOUT
SYNC_CLK ALIGNED
SYNC CLK DUT2 WITH
SYNC_CLK ALIGNED
Figure 28. Synchronization Functions: Capabilities and Limitations
Rev. A | Page 21 of 32
AD9956
SERIAL PORT OPERATION
register being accessed. For example, when accessing Control
Function Register 2, which is four bytes wide, Phase 2 requires that
four bytes be transferred. If accessing a frequency tuning word,
which is six bytes wide, Phase 2 requires that six bytes be
transferred. After transferring all data bytes per the instruction,
the communication cycle is completed.
An AD9956 serial data-port communication cycle has two
phases. Phase 1 is the instruction cycle, which is the writing of
an instruction byte to the AD9956, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9956 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the
register being accessed.
At the completion of any communication cycle, the AD9956
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9956 is registered on the rising edge of
SCLK. All data is driven out of the AD9956 on the falling edge
of SCLK. Figure 29 through Figure 32 are useful in understand-
ing the general operation of the AD9956 serial port.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9956. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9956
and the system controller. The number of bytes transferred
during Phase 2 of the communication cycle is a function of the
INSTRUCTION CYCLE
CS
DATA TRANSFER CYCLE
SCLK
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
0
SDI/O
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Figure 29. Serial Port Write Timing—Clock Stall Low
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
I
I
I
I
I
I
I
I
0
DON'T CARE
SDI/O
SDO
7
6
5
4
3
2
1
D
D
D
D
D
D
D
D
O 0
O 7
O 6
O 5
O 4
O 3
O 2
O 1
Figure 30. 3-Wire Serial Port Read Timing—Clock Stall Low
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
0
SDI/O
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Figure 31. Serial Port Write Timing—Clock Stall High
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
SDI/O
7
6
5
4
3
2
1
0
O 7
O 6
O 5
O 4
O 3
O 2
O 1 O 0
Figure 32. 2-Wire Serial Port Read Timing—Clock Stall High
Rev. A | Page 22 of 32
AD9956
MSB/LSB TRANSFERS
INSTRUCTION BYTE
The AD9956 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the LSB first bit in Control
Register 1 (CFR1<15>). The default value of this bit is low
(MSB first). When CFR1 <15> is set high, the AD9956 serial
port is in LSB first format. The instruction byte must be written
in the format indicated by CFR1 <15>. If the AD9956 is in LSB
first mode, the instruction byte must be written from least
significant bit to most significant bit. However, the instruction
byte phase of the communications cycle still precedes the data
transfer cycle.
The instruction byte contains the following information:
Table 4.
D7
D6
D5
D4
D3
D2
D1
D0
R/Wb
X
X
A4
A3
A2
A1
A0
R/Wb—Bit 7 of the instruction byte determines whether a read
or write data transfer occurs after the instruction byte write.
Logic 1 indicates a read operation. Logic 0 indicates a write
operation.
X, X—Bits 6 and 5 of the instruction byte are Don’t Care.
For MSB first operation, all data written to (read from) the
AD9956 are in MSB first order. If the LSB mode is active, all
data written to (read from) the AD9956 are in LSB first order.
A4 to A0—Bits 4 to 0 of the instruction byte determine which
register is accessed during the data transfer portion of the
communications cycle.
T
PRE
T
SCLKW
SERIAL INTERFACE PORT PIN DESCRIPTION
CS
T
DSU
SCLK—Serial Clock. The serial clock pin is used to synchronize
data to and from the AD9956 and to run the internal state
machines. The SCLK maximum frequency is 25 MHz.
SCLK
SDI/O
T
DHLD
CS
—Chip Select Bar.
CS
is an active low input that allows more
FIRST BIT
SECOND BIT
DEFINITION
than one device on the same serial communications line. The
SDO and SDI/O pins go to a high impedance state when this
input is high. If driven high during any communications cycle,
SYMBOL
MIN
T
T
T
T
6ns
CS SETUP TIME
PRE
40ns
6.5ns
0ns
PERIOD OF SERIAL DATA CLOCK (WRITE)
SERIAL DATA SETUP TIME
SERIAL DATA HOLD TIME
SCLKW
DSU
CS
that cycle is suspended until
is reactivated low. Chip select
DHLD
can be tied low in systems that maintain control of SCLK.
Figure 33. Timing Diagram for Data Write to AD9956
SDI/O—Serial Data Input/Output. Data is always written to the
AD9956 on this pin. However, this pin can be used as a bidirec-
tional data line. CFR1<7> controls the configuration of this pin.
The default value (0) configures the SDI/O pin as bidirectional.
T
SCLKR
CS
SCLK
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. When
the AD9956 operates in a single bidirectional I/O mode, this pin
does not output data and is set to a high impedance state.
SDI/O
SDO
FIRST BIT
SECOND BIT
T
DV
SYMBOL MAX DEFINITION
T
T
40ns DATA VALID TIME
400ns PERIOD OF SERIAL DATA CLOCK (READ)
DV
I/O_RESET—A high signal on this pin resets the I/O port state
machines without affecting the addressable registers’ contents.
An active high input on the I/O_RESET pin causes the current
communication cycle to abort. After I/O_RESET returns low
(0), another communication cycle can begin, starting with the
instruction byte write. Note that when not in use, this pin
should be forced low, because it floats to the threshold value.
SCLKR
Figure 34. Timing Diagram for Data Read to AD9956
Rev. A | Page 23 of 32
AD9956
REGISTER MAP AND DESCRIPTION
Table 5.
Register
Name
(Serial
Default
Value/
Profile
Bit
Range
<31:24> Open1
Bit 0
(LSB)
Address)
(MSB) Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Control
Function
Register 1
(CFR1)
Open1
Open1
Open1
Open1
Open1
Open1
PLL Lock
Error
0x00
<23:16> LOAD SRR @ Auto-Clr
Auto-
Enable
Sine
Output
Clear
Frequency Phase
Accum.
Clear
Linear
Sweep
Enable
Linear
Sweep
No Dwell
0x00
I/O_UPDATE Frequency Clr
(0x00)
Accum.
Phase
Accum.
Accum.
Open1
<15:8>
<7:0>
LSB First
SDI/O
Input
Only
Open1
Open1
Open1
Open1
Open1
0x00
0x00
Digital
Power-
Down
PFD Input PLLREF SYNC_CLK Auto Sync Software Hardware High
Power-
Down
Crystal
Enable
Disable
Multiple
AD9956s
Manual
Sync
Manual
Sync
Speed
Sync
Enable
Control
Function
Register 2
(CFR2)
<39:32> DAC
Power-
Down
Open1
Open1
Open1
Open1
Open1
Internal
Internal
0x00
Band Gap CML
Power-
Down
Driver
DRV_RSET
(0x01)
<31:24>
Clock Driver Rising Edge <31:29>
Clock Driver Falling Edge Control
<28:26>
PLL Lock
Detect
Enable
PLL Lock
Detect
Mode
0x00
0x78
<23:16> RF Divider
Power-
RF Divider Ratio
<22:21>
Clock
Clock Driver Input
Select <19:18>
Slew Rate RF Div
Control
Driver
Power-
Down
REFCLK
Mux Bit
Down
<15:8>
Divider N Control <15:12>
Divider M Control <11:8>
CP Current Scale <2:0>
0x00
0x07
<7:0>
Open1
Open1
CP
CP
CP
Polarity Full PD
Quick PD
Rising Delta
Frequency
Tuning
<23:16>
<15:8>
<7:0>
Rising Delta Frequency Tuning Word <23:16>
Rising Delta Frequency Tuning Word <15:8>
Rising Delta Frequency Tuning Word <7:0>
0x00
0x00
0x00
Word
(RDFTW)
(0x02)
Falling Delta <23:16>
Falling Delta Frequency Tuning Word <23:16>
Falling Delta Frequency Tuning Word <15:8>
Falling Delta Frequency Tuning Word <7:0>
0x00
0x00
0x00
Frequency
Tuning
Word
<15:8>
<7:0>
(FDFTW)
(0x03)
Rising
<15:8>
<7:0>
Rising Sweep Ramp Rate <15:8>
Rising Sweep Ramp Rate <7:0>
0x00
0x00
Sweep
Ramp Rate
(RSRR)
(0x04)
Falling
Sweep
Ramp Rate
(FSRR)
<15:8>
<7:0>
Rising Sweep Ramp Rate <15:8>
Rising Sweep Ramp Rate <7:0>
0x00
0x00
(0x05)
1 In all cases, open bits must be written to 0.
Rev. A | Page 24 of 32
AD9956
Register Name
(Serial Address)
Bit 0
Default Value/
Bit Range
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
(MSB) Bit 7
Open1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB) Profile
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Profile Control Register
No. 0 (PCR0) (0x06)
Phase Offset Word 0 (POW0) <13:8>
Phase Offset Word 0 (POW0) <7:0>
Frequency Tuning Word 0 (FTW0) <47:40>
Frequency Tuning Word 0 (FTW0) <39:32>
Frequency Tuning Word 0 (FTW0) <31:24>
Frequency Tuning Word 0 (FTW0) <23:16>
Frequency Tuning Word 0 (FTW0) <15:8>
Frequency Tuning Word 0 (FTW0) <7:0>
<7:0>
Profile Control Register
No. 1 (PCR1) (0x07)
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Open1
Open1
Open1
Phase Offset Word 1 (POW1) <13:8>
Phase Offset Word 1 (POW1) <7:0>
Frequency Tuning Word 1 (FTW1) <47:40>
Frequency Tuning Word 1 (FTW1) <39:32>
Frequency Tuning Word 1 (FTW1) <31:24>
Frequency Tuning Word 1 (FTW1) <23:16>
Frequency Tuning Word 1 (FTW1) <15:8>
Frequency Tuning Word 1 (FTW1) <7:0>
<7:0>
Profile Control Register
No. 2 (PCR2) (0x08)
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Phase Offset Word 2 (POW2) <13:8>
Phase Offset Word 2 (POW2) <7:0>
Frequency Tuning Word 2 (FTW1) <47:40>
Frequency Tuning Word 2 (FTW2) <39:32>
Frequency Tuning Word 2 (FTW2) <31:24>
Frequency Tuning Word 2 (FTW2) <23:16>
Frequency Tuning Word 2 (FTW2) <15:8>
Frequency Tuning Word 2 (FTW2) <7:0>
<7:0>
Profile Control Register
No. 3 (PCR3) (0x09)
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Phase Offset Word 3 (POW3) <13:8>
Phase Offset Word 3 (POW3) <7:0>
Frequency Tuning Word 3 (FTW3) <47:40>
Frequency Tuning Word 3 (FTW3) <39:32>
Frequency Tuning Word 3 (FTW3) <31:24>
Frequency Tuning Word. 3 (FTW3) <23:16>
Frequency Tuning Word 3 (FTW3) <15:8>
Frequency Tuning Word 3 (FTW3) <7:0>
<7:0>
1 In all cases, open bits must be written to 0.
Rev. A | Page 25 of 32
AD9956
Default
Value/
Profile
Register Name
(Serial Address)
Bit
Range
(MSB)
Bit 7
Bit 0
(LSB)
Bit 6
Open1
Bit 5
Bit 4
Phase Offset Word 4 (POW4) <13:8>
Phase Offset Word 4 (POW4) <7:0>
Bit 3
Bit 2
Bit 1
Profile Control
Register
No. 4 (PCR4) (0x0A)
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Frequency Tuning Word 4 (FTW4) <47:40>
Frequency Tuning Word 4 (FTW4) <39:32>
Frequency Tuning Word 4 (FTW4) <31:24>
Frequency Tuning Word 4 (FTW4) <23:16>
Frequency Tuning Word 4 (FTW4) <15:8>
Frequency Tuning Word 4 (FTW4) <7:0>
Phase Offset Word 5 (POW5) <13:8>
<7:0>
Profile Control
Register
No. 5 (PCR5) (0x0B)
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Open1
Open1
Open1
Phase Offset Word 5 (POW5) <7:0>
Frequency Tuning Word 5 (FTW5) <47:40>
Frequency Tuning Word 5 (FTW5) <39:32>
Frequency Tuning Word 5 (FTW5) <31:24>
Frequency Tuning Word 5 (FTW5) <23:16>
Frequency Tuning Word 5 (FTW5) <15:8>
Frequency Tuning Word 5 (FTW5) <7:0>
Phase Offset Word 6 (POW6) <13:8>
<7:0>
Profile Control
Register
No. 6 (PCR6) (0x0C)
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Phase Offset Word 6 (POW6) <7:0>
Frequency Tuning Word 6 (FTW6) <47:40>
Frequency Tuning Word 6 (FTW6) <39:32>
Frequency Tuning Word 6 (FTW6) <31:24>
Frequency Tuning Word 6 (FTW6) <23:16>
Frequency Tuning Word 6 (FTW6) <15:8>
Frequency Tuning Word 6 (FTW6) <7:0>
Phase Offset Word 7 (POW7) <13:8>
<7:0>
Profile Control
Register
No. 7 (PCR7) (0x0D)
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Phase Offset Word 7 (POW7) <7:0>
Frequency Tuning Word 7 (FTW7) <47:40>
Frequency Tuning Word 7 (FTW7) <39:32>
Frequency Tuning Word 7 (FTW7) <31:24>
Frequency Tuning Word 7 (FTW7) <23:16>
Frequency Tuning Word 7 (FTW7) <15:8>
Frequency Tuning Word 7 (FTW7) <7:0>
<7:0>
1 In all cases, open bits must be written to 0.
Rev. A | Page 26 of 32
AD9956
CONTROL FUNCTION REGISTER DESCRIPTIONS
CFR1 <22> = 0 (default). Issuing an I/O_UPDATE has no effect
on the current state of the frequency accumulator.
Control Function Register 1 (CFR1)
This control register is comprised of four bytes, all of which
must be written during a write operation involving CFR1. CFR1
is used to control various functions, features, and operating
modes of the AD9956. The functionality of each bit(s) is
described below. In general, the bit is named for the function it
serves when the bit is set.
CFR1 <22> = 1. Issuing an I/O_UPDATE signal to the part
clears the current contents of the frequency accumulator for
one sync-clock period.
CFR1 <21> Auto-Clear Phase Accumulator
This bit enables the auto-clear function for the phase accumula-
tor. The auto-clear function serves as a reset function for the
phase accumulator, which then begins accumulating from a
known phase value of 0.
CFR1<31:25> Open. Unused locations. Write a Logic 0
CFR1<24> PLL Lock Error (Read-Only)
When the device is operating in automatic synchronization
mode or hardware manual synchronization mode (see below),
the PLL_LOCK/ SYNC_IN pin behaves as the SYNC_IN. To
determine whether or not the PLL has become unlocked while
in synchronization mode, this bit serves as a flag to indicate that
an unlocked condition has occurred within the phase frequency
detector. Once set, the flag stays high until it is cleared by a
readback of the value even though the loop might have
relocked. Readback of the CFR1 register clears this bit.
CFR1<21> = 0 (default). Issuing an I/O_UPDATE has no effect
on the current state of the phase accumulator.
CFR1<21> = 1. Issuing an I/O_UPDATE clears the current con-
tents of the phase accumulator for one SYNC_CLK period.
CFR1 <20> Enable Sine Output
Two different trigonometric functions can be used to convert
the phase angle to an amplitude value, cosine or sine. This bit
selects the function used.
CFR1<24> = 0 indicates that the loop has maintained lock since
the last readback.
CFR1<20> = 0 (default). The phase-to-amplitude conversion
block uses a cosine function.
CFR1<24> = 1 indicates that the loop became unlocked at some
point since the last readback of this bit.
CFR1<20> = 1. The phase-to-amplitude conversion block uses a
sine function.
CFR1<23> Load Sweep Ramp Rate at I/O_UPDATE, also
known as Load SRR @ I/O_UPDATE
The sweep ramp rate is set by entering a value to a down
counter that is clocked by the SYNC_CLK. Each time a new step
is taken in the linear sweep algorithm, the ramp rate value is
passed from the linear sweep ramp rate register to this down
counter. When set, CFR1<23>, enables the user to force the part
to restart the countdown sequence for the current linear sweep
step by toggling the I/O_UPDATE pin.
CFR1 <19> Clear Frequency Accumulator
This bit serves as a static-clear or a clear-and-hold bit for the
frequency accumulator. It prevents the frequency accumulator
from incrementing the value as long as it is set.
CFR1 <19> = 0 (default). The frequency accumulator operates
normally.
CFR1<23> = 0 (default). The linear sweep ramp rate countdown
value is loaded only upon completion of a countdown sequence.
CFR1 <19> = 1. The frequency accumulator is cleared and held
at a value of 0.
CFR1<23> = 1. The linear sweep ramp rate countdown value is
reloaded, if an I/O_UPDATE signal is sent to the part during a
sweep.
CFR1 <18> Clear Phase Accumulator
This bit serves as a static-clear or a clear-and-hold it for the
phase accumulator. It prevents the phase accumulator from
incrementing the value as long as it is set.
CFR1<22> Auto-Clear Frequency Accumulator
This bit enables the auto-clear function for the frequency accu-
mulator. The auto-clear function serves as a clear and release func-
tion for the frequency accumulator (which performs the linear
sweep operation), which then begins sweeping from a known value
of FTW0.
CFR1 <18> = 0 (default). The phase accumulator operates
normally.
CFR1 <18> = 1. The phase accumulator is cleared and held at a
value of 0.
Rev. A | Page 27 of 32
AD9956
CFR1<7> Digital Power-Down
CFR1 <17> Linear Sweep Enable
This bit powers down the digital circuitry not directly related to
the I/O port. The I/O port functionality is not suspended, re-
gardless of the state of this bit.
This bit turns on the frequency accumulator, which enables the
DDS to perform linear sweeping.
CFR1<17> = 0 (default). The DDS generates frequencies in
single-tone mode.
CFR1<7> = 0 (default). Digital logic operating as normal.
CFR1<7> = 1. All digital logic not directly related to the I/O
port is powered down. Internal digital clocks are suspended.
CFR1<17> = 1. The DDS uses the frequency accumulator to
sweep the frequency tuning word being sent to the phase
accumulator according to the values set in the delta frequency
tuning word and delta frequency ramp rate registers. For a
detailed explanation of this mode, see the linear sweep mode of
operation section.
CFR1<6> Phase Frequency Detector Input Power-Down
This bit controls the input buffers on the phase frequency detec-
tor. It provides a way to gate external signals from the phase
frequency detector itself.
CFR1 <16> Linear Sweep No Dwell
CFR1<6> = 0 (default). Phase frequency detector input buffers
are functioning normally.
This bit dictates the behavior of the DDS core upon completion
of a linear sweep.
CFR1<6> = 1. Phase frequency detector input buffers are pow-
ered down, isolating the phase frequency detector from the
outside world.
CFR1<16> = 0 (default). Upon reaching the upper value of the
sweep (FTW1), the DDS holds at the frequency value stored in
FTW1.
CFR1<5> PLLREF Crystal Enable
CFR1<16> = 1. Upon reaching the upper value of the sweep
(FTW1), the DDS returns to the initial value in the sweep
(FTW0) and continues to output that frequency until a new
sweep is initiated (by bringing PS0 low and then high).
The AD9956 phase frequency detector has an on-chip oscillator
circuit. When enabled, the reference input to the phase fre-
PLLREF
quency detector (PLLREF/
) can be driven by a crystal.
CFR1<5> = 0 (default). Phase frequency detector reference
input operates as a standard analog input.
CFR1 <15> LSB First Serial Data Mode
The serial data transfer to the device can be either MSB first or
LSB first. This bit controls that operation.
CFR1<5> = 1. Reference input oscillator circuit is enabled,
allowing the use of a crystal for the reference of the phase
frequency detector.
CFR1<15> = 0 (default). Serial data transfer to the device is in
MSB first mode.
CFR1<4> SYNC_CLK Disable
CFR1<15> = 1. Serial data transfer to the device is in LSB first
mode.
If synchronization of multiple devices is not required, the spec-
tral energy resulting from this signal can be reduced by gating
the output buffer off. This function gates the internal clock ref-
erence SYNC_CLK (SYSCLK/4) off of the SYNC_OUT pin.
CFR1<14> SDI/O Input Only (3-Wire Serial Data Mode)
The serial port on the AD9956 can act in 2-wire mode (SCLK
and SDI/O) or 3-wire mode (SCLK, SDI/O, and SDO). This bit
toggles the serial port between these two modes.
CFR1<4> = 0 (default). SYNC_CLK signal is present on the
SYNC_OUT pin and is ready to be ported to other devices.
CFR1<4> = 1. SYNC_CLK signal is gated off, putting the
SYNC_OUT pin into a high impedance state.
CFR1<14> = 0 (default). Serial data transfer to the device is in
2-wire mode. The SDI/O pin is bidirectional.
CFR1<14> = 1. Serial data transfer to the device is in 3-wire
mode. The SDI/O pin is input only.
CFR1<3> Automatic Synchronization
One of the synchronization modes of the AD9956 forces the
DDS core to derive the internal reference from an external ref-
erence supplied on the SYNC_IN pin. For details on synchroni-
zation modes for the DDS core, see the Synchronization Modes
for Multiple Devices section.
CFR1<13:8> Open
Unused locations. Write a Logic 0.
Rev. A | Page 28 of 32
AD9956
CFR1<3> = 0 (default). The automatic synchronization function
of the DDS core is disabled.
CFR2<39> DAC Power-Down Bit
This bit powers down the DAC portion of the AD9956 and puts
it into the lowest power dissipation state.
CFR1<3> = 1. The automatic synchronization function is on.
The device is slaved to an external reference and adjusts the
internal SYNC_CLK to match the external reference, which is
supplied on the SYNC_IN input.
CFR2<39> = 0 (default). DAC is powered on and operating.
CFR2<39> = 1. DAC is powered down and the output is in a
high impedance state.
CFR1<2> Software Manual Synchronization
CFR2<38> to CFR2<34> Open
Rather than relying on the part to automatically synchronize the
internal clocks, the user can program the part to advance the
internal SYNC_CLK one system clock cycle. This bit is self
clearing and can be set multiple times.
Unused locations.Write a Logic 0.
CFR2<33> Internal Band Gap Power-Down
To shut off all internal quiescent current, the band gap needs to
be powered down. This is normally not done because it takes a
long time (~10 ms) for the band gap to power up and settle to
its final value.
CFR1<2> = 0 (default). The SYNC_CLK stays in the current
timing relationship to SYSCLK.
CFR1<2> = 1. The SYNC_CLK advances the rising and falling
edges by one SYSCLK cycle. This bit is then self-cleared.
CFR2<33> = 0. Even when all other sections are powered down,
the band gap is powered up and is providing a regulated voltage.
CFR1<1> Hardware Manual Synchronization
Similar to the software manual synchronization (CFR1<2>),
this function enables the user to advance the SYNC_CLK rising
edge by one system clock period. This bit enables the
PLL_LOCK/SYNC_IN pin as a digital input. Once enabled,
every rising edge on the SYNC_IN input advances the
SYNC_CLK by one SYSCLK period. While enabled, the
PLL_LOCK signal is not available on an external pin. However,
loop out-of-lock events trigger a flag in the control register
(CFR1<24>).
CFR2<33> = 1. The band gap is powered down.
CFR2<32> Internal CML Driver DRV_RSET
To program the CML driver’s output current, a resistor
must be placed between the DRV_RSET pin and ground. This
bit enables an internal resistor to program the output current of
the driver.
CFR2<32> = 0 (default). The DRV_RSET pin is enabled,
and an external resistor must be attached to the CP_RSET pin
to program the output current.
CFR1<1> = 0 (default). The hardware manual synchronization
function is disabled. Either the part is outputting the
PLL_LOCK (CFR1<3> = 0), or it is using the SYNC_IN to slave
the SYNC_CLK signal to an external reference provided on
SYNC_IN (CFR1<3> = 1).
CFR2<32> = 1. The CML current is programmed by the inter-
nal resistor and ignores the resistor on the DRV_REST pin.
CFR2<31:29> Clock Driver Rising Edge
CFR1<1> = 1. PLL_LOCK/SYNC_IN is set as a digital input.
Each subsequent rising edge on this pin advances the
SYNC_CLK rising edge by one SYSCLK period.
These bits control the slew rate of the CML clock driver output’s
rising edge. When these bits are on, additional current is sent to
the output driver to increase the rising edge slew rate capability;
the contributions of each bit are cumulative. Table 6 describes
how the bits increase the current. Note that the additional cur-
rent is on only during the rising edge of the waveform for ap-
proximately 250 ps, but not on during the entire transition.
CFR1<0> High Speed Synchronization Enable Bit
This bit enables extra functionality in the auto synchronization
algorithm, which enables the device to synchronize high speed
clocks (SYNC_CLK > 62.5 MHz).
CFR1<0> = 0 (default). High speed synchronization is disabled.
Table 6. CML Clock Driver Rising Edge Slew Rate
Control Bits and Associated Surge Current
CFR1<0> = 1. High speed synchronization is enabled.
CFR2<31> = 1
CFR2<30> = 1
CFR2<29> = 1
7.6 mA
3.8 mA
1.9 mA
Control Function Register 2 (CFR2)
This control register is comprised of five bytes, which must be
written during a write operation involving CFR2. With some
minor exceptions, the CFR2 primarily controls analog and tim-
ing functions on the AD9956.
Rev. A | Page 29 of 32
AD9956
CFR2<28:26> Clock Driver Falling Edge Control
CFR2<22:21> = 00. RF Divider R = 1. Note that this is not the
same as bypassing the RF divider.
These bits control the slew rate of the CML clock driver output’s
falling edge. When these bits are on, additional current is sent to
the output driver to increase the rising edge slew rate capability.
Table 7 describes how the bits increase the current; the contri-
butions of each bit are cumulative. Note that the additional cur-
rent is on only during the rising edge of the waveform, for ap-
proximately 250 ps, but not on during the entire transition.
CFR2<20> Clock Driver Power-Down
This bit powers down the CML clock driver circuit.
CFR2<20> =1 (default). CML clock driver circuit is powered down.
CFR2<20> = 0. CML clock driver is powered up.
Table 7. CML Clock Drive Falling Edge Slew Rate
Control Bits and Associated Surge Current
CFR2<19:18> Clock Driver Input Select
These bits control the mux on the input for the CML clock driver.
CFR2<28> = 1
CFR2<30> = 1
CFR2<29> = 1
5.4 mA
2.7 mA
1.35 mA
CFR2<19:18> = 00. The CML clock driver is disconnected from
all inputs (and does not toggle).
CFR2<19:18> = 01. The CML clock driver is driven by the
PLLOSC input pin.
CFR2<25> PLL_LOCK_DETECT Enable
This bit enables the PLL_LOCK/SYNC_IN pin as a lock detect
output for the PLL.
CFR2<19:18> = 10 (default). The CML clock driver is driven by
the output of the RF divider.
CFR2<25> = 0 (default).The PLL_LOCK_DETECT signal is
disabled.
CFR2<19:18> = 11. The CML clock driver is driven by the input
of the RF divider
CFR2<25> = 1. The PLL_LOCK_DETECT signal is enabled.
CFR2<17> Slew Rate Control Bit
CFR2<24> PLL_LOCK_DETECT Mode
Even without the additional surge current supplied by the rising
edge slew rate control bits and the falling edge slew rate control
bits, the device applies a default 7.6 mA surge current to the
rising edge and a 4.05 mA surge current to the falling edge. This
bit disables all slew rate enhancement surge current, including
the default values.
This bit toggles the modes of the PLL_LOCK_DETECT func-
tion. The lock detect can either be a status indicator (locked or
unlocked), or it can indicate a lead-lag relationship between the
two phase frequency detector inputs.
CFR2<24> = 0 (default). The lock detect acts as a status indica-
tor (PLL is locked 0 or unlocked 1).
CFR2<17> = 0 (default). The CML driver applies default surge
current to rising and falling edges.
CFR2<24> = 1. The lock detect acts as a lead/lag indicator. A
1 on the PLL_LOCK pin means that the PLLOSC pin lags the
reference. A 0 means that the PLLOSC pin leads the reference.
CFR2<17> = 1. Driver applies no surge current during transi-
tions. The only current is the continuous current.
CFR2<16> RF Divider SYSCLK Mux Bit
CFR2<23> RF Divider Power-Down
This bit toggles the mux to control whether the RF divider out-
put or input is supplying SYSCLK to the device.
This bit powers the RF divider down to save power when not in
used.
CFR2<16> = 0 (default). The RF divider output supplies the
DDS SYSCLK.
CFR2<23> = 0 (default). RF divider is on.
CFR2<23> = 1. RF divider is powered down and an alternate
path between the REFCLK inputs and SYSCLK is enabled.
CFR2<16> = 1. The RF divider input supplies the DDS SYSCLK
(bypass the divider). Note that regardless of the condition of the
configuration of the clock input, the DDS SYSCLK must not
exceed the maximum rated clock speed.
CFR2<22:21> RF Divider Ratio
These two bits control the RF divider ratio (÷R).
CFR2<22:21> = 11 (default). RF Divider R = 8.
CFR2<22:21> = 10. RF Divider R= 4.
CFR2<22:21> = 01. RF Divider R = 2.
Rev. A | Page 30 of 32
AD9956
CFR2<15:12> PLLREF Divider Control Bits (÷N)
CFR2<5> = 1. The charge pump is configured to operate with a
ground referenced VCO. If PLLOSC lags PLLREF, the charge
pump will attempt to drive the VCO control node voltage lower.
If PLLOSC leads PLLREF, the charge pump will attempt to drive
the VCO control node voltage higher.
These 4 bits set the PLLREF divider (÷N) ratio where N is a
value equal to 1 to 16. CFR2<15:12> = 0000 means that
N = 1 and CFR2<15:12> = 1111 means that N = 16, or simply,
N = CFR2<15:12> + 1.
CFR2<15:12> =
0000
N =
1
CFR2<15:12> =
1000
N =
9
CFR2<4> Charge Pump Full Power-Down
0001
0010
0011
0100
0101
0110
0111
2
3
4
5
6
7
8
1001
1010
1011
1100
1101
1110
1111
10
11
12
13
14
15
16
This bit, when set, will put the charge pump into a full power-
down mode.
CFR2<4> = 0 (default). The charge pump is powered on and
operating normally.
CFR2<4> = 1. The charge pump is completely powered down.
CFR2<3> Charge Pump Quick Power-Down
Rather than power down the charge pump, which can take a
long time to recover from, a quick power-down mode, which
powers down only the charge pump output buffer, is included.
While this doesn’t reduce the power consumption significantly,
it does shut off the output to the charge pump and allows it to
come back on in a rapidly.
CFR2<11:8> PLLREF Divider Control Bits (÷M)
These 4 bits set the PLLOSC divider (÷M) ratio where
M is a value equal to 1 to 16. CFR2<11:8> = 0000 means
that M = 1 and CFR2<11:8> = 1111 means that M = 16, or
M = CFR2<11:8> + 1.
CFR2<11:8> =
0000
M =
1
CFR2<11:8> =
1000
M =
9
CFR2<3> = 0 (default). The charge pump is powered on and
operating normally.
0001
2
1001
10
11
12
13
14
15
16
0010
3
1010
CFR2<3> = 1. The charge pump is on and running, but the
output buffer is powered down.
0011
4
1011
0100
5
1100
0101
6
1101
CFR2<2:0> Charge Pump Current Scale.
0110
7
1110
A base output current from the charge pump is determined by a
resistor connected from the CP_RSET pin to ground (see the
PLL Circuitry section). However, it is possible to multiply the
charge pump output current by a value from 1:8 by programming
these bits. The charge pump output current is scaled by
CFR2<2:0> +1.
0111
8
1111
CFR2<7:6> Open
Unused locations.Write a Logic 0.
CFR2<5> CP Polarity
CFR2<2:0> = 000 (default). Scale factor = 1 to CFR2<2:0> = 111 (8).
This bit sets the polarity of the charge pump, in response to a
ground referenced or a supply referenced VCO.
CFR2<2:0>
000
001
010
011
100
101
110
111
Scale Factor
1
2
3
4
5
6
7
8
CFR2<5> = 0 (default). The charge pump is configured to
operate with a supply referenced VCO. If PLLOSC lags PLLREF,
the charge pump will attempt to drive the VCO control node
voltage higher. If PLLOSC leads PLLREF, the charge pump will
attempt to drive the VCO control node voltage lower.
Rev. A | Page 31 of 32
AD9956
OUTLINE DIMENSIONS
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 35. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body (CP-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
–40°C to +125°C
–40°C to +125°C
Package Description
Package Option
CP-48
CP-48
AD9956YCPZ1
48-Lead Lead Frame Chip Scale Package (LFCSP)
AD9956YCPZ-REEL1
AD9956/PCB
AD9956-VCO/PCB
48-Lead Lead Frame Chip Scale Package (LFCSP), Tape and Reel
Evaluation Board with No VCO and Charge Pump Filter
Evaluation Board with 2.4 GHz VCO and Charge Pump Filter
1 Z = Pb-free part.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04806–0–9/04(A)
Rev. A | Page 32 of 32
相关型号:
AD9957BSVZ-REEL13
IC SPECIALTY TELECOM CIRCUIT, QFP48, PLASTIC, MS-026-AED-HD, TQFP-48, Telecom IC:Other
ADI
©2020 ICPDF网 联系我们和版权申明