AD9974 [ADI]
Dual-Channel, 14-Bit, CCD Signal Processor with Precision Timing⑩ Core; 双通道， 14位CCD信号处理器具有精密Timing⑩核心
| 型号： | AD9974 |
| 厂家： | 
ADI |
| 描述： | Dual-Channel, 14-Bit, CCD Signal Processor with Precision Timing⑩ Core |
| 文件： | 总2页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual-Channel, 14-Bit, CCD Signal
Processor with Precision Timing™ Core
AD9974
FEATURES
GENERAL DESCRIPTION
1.8 V analog and digital core supply voltage
Correlated double sampler (CDS) with
−3 dB, 0 dB, +3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
14-bit, 65 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
The AD9974 is a highly integrated, dual-channel CCD signal
processor for high speed digital video camera applications. Each
channel is specified at pixel rates of up to 65 MHz. The AD9974
consists of a complete analog front end with analog-to-digital
conversion combined with a programmable timing driver. The
Precision Timing core allows adjustment of high speed clocks
with approximately 240 ps resolution at 65 MHz operation.
Precision Timing core with 240 ps resolution @ 65 MHz
On-chip 3 V horizontal and RG drivers
100-lead, 9 mm × 9 mm, 0.8 mm pitch, CSP_BGA package
Internal LDO regulator circuitry
Each analog front end includes black level clamping, CDS, VGA,
and a 65 MSPS, 14-bit ADC. The timing driver provides the high
speed CCD clock drivers for the RG_A, RG_B, H1_A to H4_A,
and H1_B to H4_B outputs. A 3-wire serial interface is used to
program each channel of the AD9974.
APPLICATIONS
Available in a space-saving, 9 mm × 9 mm, CSP_BGA package,
the AD9974 is specified over an operating temperature range of
−25°C to +85°C.
Professional HDTV camcorders
Professional/high end digital cameras
Broadcast cameras
For more information on the AD9974, email Analog Devices, Inc. at
afe.ccd@analog.com.
Industrial high speed cameras
FUNCTIONAL BLOCK DIAGRAM
REFT_A REFB_A
REFT_B REFB_B
AD9974
VREF_A
VREF_B
CCDINP_A
CCDINM_A
14
DOUT_A
DOUT_B
ADC
CDS
VGA
VGA
6dB TO 42dB
6dB TO 42dB
–3, 0, +3, +6dB
CLAMP
CLAMP
–3, 0, +3, +6dB
14
CCDINP_B
CCDINM_B
ADC
CDS
1.8V OUTPUT
1.8V OUTPUT
LDO A
LDO B
INTERNAL CLOCKS
RG_A
RG_B
PRECISION
TIMING
CORE
CLI_A
CLI_B
HORIZONTAL
DRIVERS
4
4
H1_A TO H4_A
H1_B TO H4_B
SCK_A
SCK_B
SYNC
GENERATOR
INTERNAL
REGISTERS
HD_A VD_A HD_B VD_B
SL_A
SL_B
SDATA_A SDATA_B
Figure 1.
Rev. Sp0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD9974
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D005955F-0-2/07(Sp0)
Rev. Sp0 | Page 2 of 2
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