AD9993-EBZ_技术文档

Integrated Mixed-Signal Front End (MxFE)

Data Sheet

AD9993

FEATURES

GENERAL DESCRIPTION

Quad 14-bit 250 MSPS ADC

SFDR = 83 dBc at 87 MHz input

Dual 14-bit 500 MSPS DAC

SFDR = 75 dBc at 20 MHz output

On-chip PLL clock synthesizer

Low power

The AD9993 is a mixed-signal front-end (MxFE®) device that

integrates four 14-bit ADCs and two 14-bit DACs. Figure 1

shows the block diagram of the MxFE. The MxFE is

programmable using registers accessed via a serial peripheral

interface (SPI). ADC and DAC datapaths include FIFO buffers

to absorb phase differences between LVDS lane clocks and the

1536 mW, 1 GHz master clock, on-chip synthesizer

500 MHz double data rate (DDR)

LVDS interfaces for DACs and ADCs

data converter sampling clocks.

The MxFE DACs are part of the Analog Devices, Inc., high

speed CMOS DAC core family. These DACs are designed to be

used in wide bandwidth communication system transmitter

(Tx) signal chains.

Small 12 mm × 12 mm lead-free BGA package

APPLICATIONS

Point to point microwave backhaul radios

Wireless repeaters

The MxFE ADCs are multistage pipelined CMOS ADC cores

designed for use in communications receivers.

FUNCTIONAL BLOCK DIAGRAM

DOUT3A_x TO DOUT0A_x

DOUT3B_x TO DOUT0B_x

DOUT3C_x TO DOUT0C_x

DOUT3D_x TO DOUT0D_x

DCO_x

2

14

4

ADC_A

ADC_B

ADC_C

ADC_D

LVDS

BUFFER

DCO CLOCK

STROBE

STROBE_x

DIGITAL

–ADC AND DAC

DATAPATHS

–CONTROLS

–SPI REGISTERS

–FIFO BUFFERS

14

DIN6A_x TO DIN0A_x

LVDS

BUFFER

DIN6B_x TO DIN0B_x

DCI_x

DCI CLOCK

2

14

DAC_A

DAC_B

4

SPI_SCLK, SPI_CS, SPI_SDI, SPI_SDO

RST

ALERT

PLL

0

1

MxFE

AD9993

CLOCK GENERATOR

31.25MHz

OR

62.5MHz

DIV

1GHz

Figure 1.

Rev. A

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Last Content Update: 02/23/2017

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DESIGN RESOURCES

• AD9993 Material Declaration

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• Symbols and Footprints

EVALUATION KITS

• AD9993 Evaluation board

DOCUMENTATION

Data Sheet

DISCUSSIONS

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• AD9993: Integrated Mixed-Signal Front End (MxFE) Data

Sheet

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TOOLS AND SIMULATIONS

• AD9993 IBIS Model

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AD9993

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

LVDS Interface Timing.............................................................. 22

LVDS Lane Testing Using PRBS............................................... 23

Power Mode Programming....................................................... 23

Interrupt Request Operation .................................................... 23

Temperature Sensor ................................................................... 23

Start-Up Register Sequences......................................................... 25

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 5

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 11

Receiver ADC Performance...................................................... 11

Transmitter DAC Performance................................................. 13

Terminology .................................................................................... 15

Theory of Operation ...................................................................... 16

Product Description................................................................... 16

SPI Port ........................................................................................ 16

SPI Configuration Programming............................................. 17

Register Update Transfer Method............................................ 17

ADC Register Update Indexing................................................ 17

ADCs............................................................................................ 17

ADC Architecture ...................................................................... 17

ADC Section Programming...................................................... 17

Analog Input Considerations.................................................... 17

DACs ............................................................................................ 18

DAC Transfer Function ............................................................. 18

Power-Up Routine When Using the On-Chip Clock

Synthesizer .................................................................................. 25

Power-Up Routine When Using External Clock ................... 25

Applications Information.............................................................. 27

Direct Conversion Radio Application..................................... 27

Register Map ................................................................................... 28

Register Descriptions..................................................................... 30

SPI Configuration Register ....................................................... 30

Chip ID Register......................................................................... 30

Chip Grade Register................................................................... 31

Device Index Register................................................................ 31

Power Mode Control Register .................................................. 32

Align ADC LVDS Clocks, ADC FIFO, DAC FIFO Register 32

Strobe Lane Control Register.................................................... 33

Output Mode Register ............................................................... 33

LVDS Tx Control Register ........................................................ 34

V_REFControl Register................................................................. 34

PRBS Generator Control Register............................................ 35

8-Bit Seed MSB of PRBS Generator for Lane 0 Register....... 35

8-Bit Seed MSB of PRBS Generator for Lane 1 Register....... 36

8-Bit Seed MSB of PRBS Generator for Lane 2 Register....... 36

8-Bit Seed MSB of PRBS Generator for Lane 3 Register....... 36

Synthesizer Status Register........................................................ 37

Loop Filter Control Signals Register........................................ 37

Loop Filter Control Signals Register........................................ 38

Integer Value of Synthesizer Divider Register........................ 39

Synthesizer Control Register .................................................... 39

Clock Generator Control Register ........................................... 39

CLKGEN Control Register ....................................................... 40

DAC LVDS Rx Control Register .............................................. 40

DAC LVDS Current Bias Control Register............................. 41

DAC Cores Control Register .................................................... 42

DAC Datapath Format Control Register ................................ 42

DAC Output Compliance Voltage Range and AC

Performance ................................................................................ 18

DAC Voltage Reference ............................................................. 19

DAC Gain Setting....................................................................... 19

DAC Datapath Format Selection.............................................. 19

DAC Test Tone Generator DDS................................................ 19

Clocking....................................................................................... 20

On-Chip PLL Clock Multiplier ................................................ 20

Selecting Clocking Options....................................................... 21

ADC Datapath and DAC Datapath FIFOs ............................. 21

LVDS Interfaces.......................................................................... 21

Rev. A | Page 2 of 56

Data Sheet

AD9993

DAC IQ Calibration Control Register......................................43

DAC IQ Calibration Status Register.........................................43

DAC Rx FIFO Status 1 Register ................................................43

PRBS Detector Control Register...............................................44

PRBS Detector Error Count 0 for DAC A Register................44

PRBS Detector Error Count 1 for DAC A Register................44

PRBS Detector Error Count 2 for DAC A Register................45

PRBS Detector Error Count 3 for DAC A Register................45

PRBS Detector Error Count 4 for DAC A Register................45

PRBS Detector Error Count 5 for DAC A Register................46

PRBS Detector Error Count 6 for DAC A Register................46

PRBS Detector Error Count 0 for DAC B Register ................46

PRBS Detector Error Count 1 for DAC B Register ................47

PRBS Detector Error Count 2 for DAC B Register ................47

PRBS Detector Error Count 3 for DAC B Register ................47

PRBS Detector Error Count 4 for DAC B Register ................48

PRBS Detector Error Count 5 for DAC B Register ................48

PRBS Detector Error Count 6 for DAC B Register ................48

Bits[7:0] of Temperature Sensor Data Readback Register.....49

Bits[15:8] of Temperature Sensor Data Readback Register...49

Temperature Sensor Control Signals Register ........................49

Interrupt Pin Control Register..................................................50

DDS Control Register.................................................................50

DDS Tuning Word for Tone 1 Register....................................51

DDS Tuning Word for Tone 1 Register....................................52

Interrupt Status Register ............................................................53

Interrupt Enable Register...........................................................53

Interrupt Source Status Register ...............................................54

Global Device Update Register .................................................55

Outline Dimensions........................................................................56

Ordering Guide ...........................................................................56

REVISION HISTORY

5/14—Rev. 0 to Rev. A

Changes to Ordering Guide...........................................................56

5/14—Revision 0: Initial Version

Rev. A | Page 3 of 56

AD9993

Data Sheet

SPECIFICATIONS

DC SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 3.3 V, DVDD = AVDD = 1.8 V, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Tx DAC RESOLUTION

Tx DAC OUTPUT CHARACTERISTICS

Offset Error

14

Bits

±±.5

±2.±

2±.±

% FSR

mA

Gain Error

Full-Scale Output Current (I_OUTFS

)

Output Compliance Voltage Range

CML_A, CML_B connected to AVSS, setting of

DAC_VCM_VREF_BIT[2:±] following reset

CML_A, CML_B connected to a bypass capacitor,

DAC_VCM_VREF_BIT[2:±] set to ±1±

−±.5

±.±

+±.5

1.±

V

Output Compliance Voltage Range

V

Output Resistance

Tx DAC TEMPERATURE DRIFT

Gain

Reference Voltage (VREF_DAC)

REFERENCE (VREF_DAC)

Internal Reference Voltage

Rx ADC RESOLUTION

Rx ADC CHARACTERISTICS

Gain Error

1±

MΩ

Gain using on-chip VREF_DAC

On-chip VREF_DAC

±ꢀ5

±215

ppm/°C

±.95

1.±

14

1.±5

V

Bits

±1.±

1.75

% FSR

V p-p

Peak-to-Peak Differential Input Voltage

Range

Input Capacitance

Setting of VREF_FS_ADJ[4:±] at reset

ADC inputs are not self biased

2.5

pF

V

Rx ADC FULL-SCALE V_REFADJUSTMENT

1.3ꢀ3 1.75

2.±ꢀ7

±.96

COMMON-MODE VOLTAGE REFERENCE

(A_CML, B_CML, C_CML, D_CML)

ADC Common-Mode Voltage Output

±.ꢀ4

±.9

V

ANALOG SUPPLY VOLTAGES

AVDD33

AVDD

3.14

1.71

3.3

1.ꢀ

3.47

1.ꢀ9

V

DIGITAL SUPPLY VOLTAGES

DVDD

1.62

1.ꢀ

1.9ꢀ

V

POWER CONSUMPTION

Single Tone Input, Single Tone Output

AVDD33

AVDD

DVDD

1536

55

65

21±

1±.±

+25

mW

mA

°C

Power-Down Mode

OPERATING RANGE

−4±

+ꢀ5

Rev. A | Page 4 of 56

Data Sheet

AD9993

AC SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 3.3 V, DVDD = AVDD = 1.8 V, DAC sampling rate = 500 MSPS and ADC sampling rate = 250 MSPS, unless

otherwise specified.

Table 2.

Parameter

Test Conditions/Comments

Min Typ

Max Unit

DAC OUTPUT

Spurious-Free Dynamic Range

(SFDR)

Two Tone Intermodulation

Distortion (IMD3)

f_OUT= 2± MHz

75

dBc

f

_OUT= ꢀ± MHz

65

Noise Spectral Density (NSD),

Single Tone

256-QAM Adjacent Channel

Power (ACP)

f_OUT= ꢀ± MHz

−16±

76

dBm/Hz

f_CENTER= 5± MHz, single carrier, 3.375 MHz offset frequency

dBc

ADC INPUT

Signal to Noise Ratio (SNR)

f_IN= ꢀ7 MHz

Spurious-Free Dynamic Range

(SFDR)

Measured with −1.± dBFS sine wave input

7±

f_IN= 1± MHz

f_IN= ꢀ7 MHz

Two-Tone IMD3

Full Power Bandwidth

ꢀ6

ꢀ3

9±

1±±±

dBc

MHz

f_IN1= ꢀ9 MHz, f_IN2= 92 MHz, A_IN= −12 dBFS

Bandwidth of operation in which proper ADC performance can be

achieved

DIGITAL SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 3.3 V, DVDD = AVDD = 1.8 V, unless otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max Unit

CMOS INPUT LOGIC LEVEL

Input V_INLogic High

Input V_INLogic Low

1.ꢀ

±.±

V

CMOS OUTPUT LOGIC LEVEL

Output V_OUTLogic High

1.2

V

Output V_OUTLogic Low

±.ꢀ

V

ADC AND DAC LVDS DATA INTERFACES

ADC LVDS Transmitter Outputs

DCO_P/DCO_N to Data Skew (t_SKEW

)

Data to DDR DCO_P/DCO_N transition delay

35±

ps

Output Voltage High, V_OH, Single

Ended

Output Voltage Low, V_OL, Single

Ended

Applies to output voltage, positive and negative, V_OUTP

and V_OUTN

Applies to V_OUTPand V_OUTN

1375

1±25

mV

Output Differential Voltage

Output Offset Voltage

2±±

12±±

mV

DAC LVDS Receiver Inputs

Specifications apply to DAC data inputs and DCI_P/DCI_N

Input Voltage Range, Single Ended

Applies to input voltage, positive and negative, V_INPand

V_INN

ꢀ25

1575 mV

Input Differential Threshold

Input Differential Hysteresis

Receiver Differential Input

Impedance

−1±±

ꢀ5

+1±± mV

mV

25

115

Ω

Rev. A | Page 5 of 56

AD9993

Data Sheet

Parameter

Test Conditions/Comments

Min

Typ

Max Unit

CLOCK INPUT (CLKP, CLKN)

Differential Peak to Peak Voltage

Common Mode Voltage

Master Clock Frequency

REFCLK Input (REFCLK)

Input V_INLogic High

35±

1.2

mV

V

1±±± MHz

2±±

1.ꢀ

±.±

V

Input V_INLogic Low

REFCLK Frequency

31.25 or

62.5

MHz

SERIAL PERIPHERAL INTERFACE (SPI)

SPI_SCLK Frequency

SPI_SCLK Pulse Width High

SPI_SCLK Pulse Width Low

Setup Time, SPI_SDI to SPI_SCLK Rising

Edge

25

MHz

ns

1±

2

ns

Hold Time, SPI_SCLK Rising Edge to

SPI_SDI

Setup Time, SPI_CS to SPI_SCLK Rising

Edge

Hold Time, SPI_SCLK Rising Edge to

SPI_CS

2

ns

Data Valid, SPI_SCLK Falling Edge to

SPI_SDO

Rev. A | Page 6 of 56

Data Sheet

AD9993

ABSOLUTE MAXIMUM RATINGS

Table 4.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Parameter

Rating

AVSS to DVSS

−±.3 V to +±.3 V

−±.3 V to +3.9 V

−±.3 V to +2.2 V

−±.3 V to AVDD + ±.3 V

AVDD33 to AVSS, DVSS

AVDD to AVSS, DVSS

DVDD to DVSS, AVSS

CP, A_VINP, A_VINN, B_VINP, B_VINN,

C_VINP, C_VINN, D_VINP, D_VINN,

IBIAS_TEST to AVSS

THERMAL RESISTANCE

Table 5. Thermal Resistances and Characterization Parameters

VREF_DAC, FSAJ_A, FSAJ_B, CML_A,

CML_B, A_CML, B_CML, B_CML,

D_CML to AVSS

IOUTA_P, IOUTA_N, IOUTB_P,

IOUTB_N to AVSS

−±.3 V to AVDD + ±.3 V

Package Type

θ_JA

θ_JB

θ_JC

ψ_JT

ψ_JB

Unit

196-Ball CSP_BGA

27.± 15.4 5.3ꢀ ±.11 15.± ºC/W

CLKP, CLKN, REFCLK to AVSS

PDWN, ALERT, RST, MODE, SPI_SCLK,

SPI_CS, SPI_SDI, SPI_SDO to DVSS

−±.3 V to AVDD + ±.3 V

−±.3 V to DVDD + ±.3 V

ESD CAUTION

LVDS Data Inputs to DVSS

LVDS Data Outputs to DVSS

STROBE_P, STROBE_N to DVSS

DCI_N, DCI_P, DCO_N, DCO_P

Junction Temperature

−±.3 V to DVDD + ±.3 V

125°C

Storage Temperature Range

−65°C to +16±°C

Rev. A | Page 7 of 56

AD9993

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

IBIAS_

TEST

AVSS

CLKP

AVSS

D_VINP

C_CML

C_VINP

AVSS

B_VINP

B_CML

A_VINP

AVSS

A

B

C

D

E

F

CLKN

AVSS

REFCLK

AVSS

CP

AVSS

AVDD

RST

D_VINN

AVSS

D_CML

AVSS

C_VINN

AVSS

AVDD

AVSS

DVSS

DVDD

AVSS

AVDD

AVSS

DVSS

DVDD

DCO_N

AVSS

AVDD

AVSS

DVSS

DVDD

DCO_P

B_VINN

AVSS

AVDD

AVSS

DVSS

DVDD

A_CML

AVSS

AVDD

AVSS

DVSS

DVDD

A_VINN

AVSS

AVDD

AVSS

DVSS

DVDD

AVSS

IOUTA_N IOUTA_P

AVDD33

LDO15

AVDD

PDWN

AVSS

IOUTB_N IOUTB_P

AVDD

ALERT

AVDD

AVDD33

DVDD

DVSS

DVDD

AVDD

FSAJ_B

CML_B

DVSS

AVDD

FSAJ_A

CML_A

DVSS

MODE

SPI_SDO

DVSS

VREF_DAC

AVDD

SPI_SCLK SPI_CS

SPI_SDI

DVSS

DVDD

G

H

J

DVSS

DVDD

DVSS

DVDD

DVSS

DVDD

DIN6B_N DIN4B_N DIN1B_N DOUT3D_P DOUT3D_N DOUT3C_P

DOUT3B_P DOUT3A_N DOUT3A_P DIN1A_N DIN4A_N DIN6A_N

K

L

DIN6B_P DIN4B_P DIN1B_P DOUT1D_N DOUT2D_N DOUT1C_N DOUT3C_N DOUT3B_N DOUT1B_N DOUT2A_N DOUT1A_N DIN1A_P DIN4A_P DIN6A_P

DIN5B_N DIN3B_N DIN3B_P DOUT1D_P DOUT2D_P DOUT1C_P STROBE_N STROBE_P DOUT1B_P DOUT2A_P DOUT1A_P DIN3A_N DIN3A_P DIN5A_N

M

N

P

DIN5B_P DIN2B_N DIN0B_N DOUT0D_N DOUT0C_N DOUT2C_N

DVSS

DCI_N

DVSS

DCI_P

DOUT2B_N DOUT0B_N DOUT0A_N DIN0A_N DIN2A_N DIN5A_P

DVSS

DIN2B_P DIN0B_P DOUT0D_P DOUT0C_P DOUT2C_P

DOUT2B_P DOUT0B_P DOUT0A_P DIN0A_P DIN2A_P

DVSS

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

A1, A3, A7, Aꢀ, A12, A14, B3, B7, Bꢀ, B12, C1, C2,

C3, C4, C5, C6, C7, Cꢀ, C9, C1±, C11, C12, D3, D4,

D5, D6, D7, Dꢀ, D9, D1±, D11, D12, F6, F7, Fꢀ, F9,

F1±, F11, G6, G7, Gꢀ, G9, G1±, G11

AVSS

Analog Ground.

A2

A4

A5

A6

A9

A1±

CLKP

External Master Clock Input Positive.

ADC D Input Voltage Positive.

Common-Mode Level Bias Voltage Output ADC C.

ADC C Input Voltage Positive.

ADC B Voltage Input Positive.

Common-Mode Level Bias Voltage Output for ADC B.

D_VINP

C_CML

C_VINP

B_VINP

B_CML

Rev. A | Page ꢀ of 56

Data Sheet

AD9993

Pin No.

A11

A13

B1

B2

B4

B5

B6

B9

B1±

B11

B13

B14

C13, C14, F5

D1

D2

D13

D14

Mnemonic

A_VINP

IBIAS_TEST

CLKN

REFCLK

D_VINN

D_CML

C_VINN

B_VINN

A_CML

A_VINN

IOUTA_N

IOUTA_P

AVDD33

LDO15

Description

ADC A Voltage Input Positive.

Test. Connect to ground.

External Master Clock Input Negative

On-Chip PLL Synthesizer Reference Clock Input.

ADC D Input Voltage Negative.

Common-Mode Level Bias Voltage Output ADC D.

ADC C Input Voltage Negative.

ADC B Voltage Input Negative.

Common-Mode Level Bias Voltage Output for ADC A.

ADC A Voltage Input Negative.

DAC A Output Current Negative.

DAC A Output Current Positive.

3.3 V Analog Power Supply.

On-Chip Regulator Output. Bypass with 4.7 μF capacitor to ground.

Connection for On-Chip PLL Optional External Portion of Loop Filter.

DAC B Output Current Negative.

CP

IOUTB_N

IOUTB_P

DAC B Output Current Positive.

E1, E2, E3, E4, E5, E6, E7, Eꢀ, E9, E1±, E11, E12, E13, AVDD

E14, G12

1.ꢀ V Analog Power Supply.

F1

F2

PDWN

ALERT

Power-Down. Set to 1 to place the device in low power mode.

Active Low Alarm Indicator Output, Open Drain.

Reset Input, Active Low.

F3

RST

F4

MODE

Connect to ground.

F12

F13

F14

G1

G2

G3

G4

VREF_DAC

FSAJ_B

FSAJ_A

SPI_SCLK

SPI_CS

SPI_SDI

SPI_SDO

DAC A and DAC B Reference Voltage Input/Output.

DAC B Full-Scale Current Output Adjust.

DAC A Full-Scale Current Output Adjust.

SPI Clock.

SPI Chip Select, Active Low.

SPI Serial Data Input.

SPI Serial Data Output.

G5, J1, J2, J3, J4, J5, J6, J7, Jꢀ, J9, J1±, J11, J12, J13, DVDD

J14

1.ꢀ V Digital Supply.

G13

CML_B

DAC B Common-Mode Control. Connect to ground for DAC bias < ±.5 V.

Connect a ±.1 μF capacitor between CML_B and ground for other DAC

bias values ≥ ±.5 V.

G14

CML_A

DAC A Common-Mode Control. Connect to ground for DAC bias < ±.5 V.

Connect a ±.1 μF capacitor between CML_A and ground for other DAC

bias values ≥ ±.5 V.

H1, H2, H3, H4, H5, H6, H7, Hꢀ, H9, H1±, H11, H12, DVSS

H13, H14, N7, Nꢀ, P1, P14

Digital Ground.

K1

K2

K3

K4

K5

K6

K7

Kꢀ

DIN6B_N

DAC B Data Input Lane 6 Negative.

DAC B Data Input Lane 4 Negative.

DAC B Data Input Lane 1 Negative.

ADC D Data Output Lane 3 Positive.

ADC D Data Output Lane 3 Negative.

ADC C Data Output Lane 3 Positive.

LVDS Data Clock Output Negative.

LVDS Data Clock Output Positive.

ADC B Data Output Lane 3 Positive.

ADC A Data Output Lane 3 Negative.

ADC A Data Output Lane 3 Positive.

DAC A Data Input Lane 1 Negative.

DAC A Data Input Lane 4 Negative.

DAC A Data Input Lane 6 Negative.

DIN4B_N

DIN1B_N

DOUT3D_P

DOUT3D_N

DOUT3C_P

DCO_N

DCO_P

K9

DOUT3B_P

DOUT3A_N

DOUT3A_P

DIN1A_N

DIN4A_N

DIN6A_N

K1±

K11

K12

K13

K14

Rev. A | Page 9 of 56

AD9993

Data Sheet

Pin No.

L1

L2

L3

L4

L5

L6

L7

Lꢀ

Mnemonic

DIN6B_P

DIN4B_P

Description

DAC B Data Input Lane 6 Positive.

DAC B Data Input Lane 4 Positive.

DAC B Data Input Lane 1 Positive.

ADC D Data Output Lane 1 Negative.

ADC D Data Output Lane 2 Negative.

ADC C Data Output Lane 1 Negative.

ADC C Data Output Lane 3 Negative.

ADC B Data Output Lane 3 Negative.

ADC B Data Output Lane 1 Negative.

ADC A Data Output Lane 2 Negative.

ADC A Data Output Lane 1 Negative.

DAC A Data Input Lane 1 Positive.

DAC A Data Input Lane 4 Positive.

DAC A Data Input Lane 6 Positive.

DAC B Data Input Lane 5 Negative.

DAC B Data Input Lane 3 Negative.

DAC B Data Input Lane 3 Positive.

ADC D Data Output Lane 1 Positive.

ADC D Data Output Lane 2 Positive.

ADC C Data Output Lane 1 Positive.

LVDS Data Output Strobe Negative.

LVDS Data Output Strobe Positive.

ADC B Data Output Lane 1 Positive.

ADC A Data Output Lane 2 Positive.

ADC A Data Output Lane 1 Positive.

DAC A Data Input Lane 3 Negative.

DAC A Data Input Lane 3 Positive.

DAC A Data Input Lane 5 Negative.

DAC B Data Input Lane 5 Positive.

DAC B Data Input Lane 2 Negative.

DAC B Data Input Lane ± Negative.

ADC D Data Output Lane ± Negative.

ADC C Data Output Lane ± Negative.

ADC C Data Output Lane 2 Negative.

ADC B Data Output Lane 2 Negative.

ADC B Data Output Lane ± Negative.

ADC A Data Output Lane ± Negative.

DAC A Data Input Lane ± Negative.

DAC A Data Input Lane 2 Negative.

DAC A Data Input Lane 5 Positive.

DAC B Data Input Lane 2 Positive.

DAC B Data Input Lane ± Positive.

ADC D Data Output Lane ± Positive.

ADC C Data Output Lane ± Positive.

ADC C Data Output Lane 2 Positive.

LVDS Data Clock Input Negative.

LVDS Data Clock Input Positive.

DIN1B_P

DOUT1D_N

DOUT2D_N

DOUT1C_N

DOUT3C_N

DOUT3B_N

DOUT1B_N

DOUT2A_N

DOUT1A_N

DIN1A_P

DIN4A_P

DIN6A_P

DIN5B_N

DIN3B_N

L9

L1±

L11

L12

L13

L14

M1

M2

M3

M4

M5

M6

M7

Mꢀ

M9

M1±

M11

M12

M13

M14

N1

N2

N3

N4

N5

N6

N9

N1±

N11

N12

N13

N14

P2

P3

P4

P5

P6

DIN3B_P

DOUT1D_P

DOUT2D_P

DOUT1C_P

STROBE_N

STROBE_P

DOUT1B_P

DOUT2A_P

DOUT1A_P

DIN3A_N

DIN3A_P

DIN5A_N

DIN5B_P

DIN2B_N

DIN±B_N

DOUT±D_N

DOUT±C_N

DOUT2C_N

DOUT2B_N

DOUT±B_N

DOUT±A_N

DIN±A_N

DIN2A_N

DIN5A_P

DIN2B_P

DIN±B_P

DOUT±D_P

DOUT±C_P

DOUT2C_P

DCI_N

P7

Pꢀ

DCI_P

P9

DOUT2B_P

DOUT±B_P

DOUT±A_P

DIN±A_P

ADC B Data Output Lane 2 Positive.

ADC B Data Output Lane ± Positive.

ADC A Data Output Lane ± Positive.

DAC A Data Input Lane ± Positive.

DAC A Data Input Lane 2 Positive.

P1±

P11

P12

P13

DIN2A_P

Rev. A | Page 1± of 56

Data Sheet

AD9993

TYPICAL PERFORMANCE CHARACTERISTICS

RECEIVER ADC PERFORMANCE

f_ADC= 250 MHz, unless otherwise specified.

IMD3 (dBc)

IMD3 (dBFS)

0

–15

–30

–45

–60

–75

–20

–40

–60

2

3

–90

–105

–120

–135

–80

6

4

5

–100

–120

15

30

45

60

75

90

105

120

–90

–80

–70

–60

–50

–40

–30

–20

–10

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 3. Single Tone FFT, f_IN= 87 MHz

Figure 6. Two Tone IMD3 vs. Input Amplitude (A_IN), f_IN1= 89.12 MHz, f_IN2

92.12 MHz

=

95

90

85

80

75

70

65

120

100

80

60

40

20

0

SNR (dBc)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

20

40

60

80

f_IN(MHz)

100

120

INPUT AMPLITUDE (dBFS)

Figure 4. Single Tone SNR and SFDR vs. Input Amplitude (A_IN), f_IN= 87 MHz

Figure 7. Single Tone SNR vs. Input Frequency (f_IN

)

0

95

90

85

80

75

70

65

SFDR (dBc)

SFDR (dBFS)

–20

–40

–60

–80

–100

–120

–90

–80

–70

–60

–50

–40

–30

–20

–10

20

40

60

80

f_IN(MHz)

100

120

INPUT AMPLITUDE (dBFS)

Figure 5. Two Tone SFDR vs. Input Amplitude (A_IN), f_IN1= 89.12 MHz,

_IN2= 92.12 MHz

Figure 8. Single Tone SNR vs. Input Frequency (f_IN

)

f

Rev. A | Page 11 of 56

AD9993

Data Sheet

f_ADC= 250 MHz, unless otherwise specified.

100

95

90

85

80

75

70

65

60

ADC A

ADC B

ADC C

ADC D

0

–15

–30

–45

–60

–75

F2 – F1

2F2 + F1

2F1 – F2

–90

–105

–120

–135

2F1 + F2

2F2 – F1

F1 + F2

15

30

45

60

75

90

105

120

100

120

140

160

180

200

220

240

FREQUENCY (MHz)

ADC SAMPLING FREQUENCY (MSPS)

Figure 11. Single Tone SFDR vs. ADC Sampling Freqency (f_ADC), f_IN= 90.0 MHz,

All Four ADCs

Figure 9. Two Tone FFT, f_IN1= 89.12 MHz, f_IN2= 92.12 MHz

100

ADC A

ADC B

ADC C

ADC D

95

90

85

80

75

70

65

60

100

120

140

160

180

200

220

240

ADC SAMPLING FREQUENCY (MSPS)

Figure 10. Single Tone SNR vs. ADC Sampling Freqency (f_ADC), f_IN= 90.0 MHz,

All Four ADCs

Rev. A | Page 12 of 56

Data Sheet

AD9993

TRANSMITTER DAC PERFORMANCE

f_DAC= 500 MHz, unless otherwise specified.

–76.2dBc

–76.4dBc –75.5dBc

–75.9dBc

–76.2dBc

–75.9dBc

2R

11.2dBm

–76.3dBc

–30

–40

–50

–60

–70

2

–80

–90

1

–100

–110

START 1MHz

#RES BW 1kHz

STOP 250MHz

SWEEP 300.2s (601pts)

VBW 1kHz

CENTER 50MHz

#RES BW 30kHz

#VBW 300kHz

LOWER

SPAN 54MHz

SWEEP 175.1ms

MARKER

TRACE

TYPE

FREQ

X AXIS

AMPLITUDE

1R

1

47.9MHz –0.56dBm

48.0MHz –83.28dB

47.9MHz –0.56dBm

96.4MHz –71.74dB

UPPER

dBc dBm Filter

OFFSET FREQ INTEG BW

dBc

dBm

2R

2

3.375MHz

6.375MHz

12MHz

18MHz

24MHz

750kHz –80.81 –92.04 –29.72 –40.95 OFF

5.25MHz –75.93 –87.16 –75.95 –87.18 OFF

6MHz –75.49 –86.72 –76.30 –87.53 OFF

6MHz –76.23 –87.46 –76.17 –87.41 OFF

6MHz –76.42 –87.65 –75.93 –87.16 OFF

Figure 12. 5 MHz Bandwidth 256-QAM Adjacent Channel Power

Figure 15. 1^stNyquist Zone Output Spectrum, f_OUT= 48 MHz

–40

f_DAC= 250MHz, DAC B

f_DAC= 350MHz, DAC B

f_DAC= 500MHz, DAC B

SECOND HARMONIC (dBc)

THIRD HARMONIC (dBc)

SFDR (dBc)

–45

–50

–55

–60

–65

–70

–75

–80

–50

–60

–70

–80

–90

–100

0

50

100

150

200

250

0

50

100

150

200

250

f_OUT(MHz)

Figure 13. SFDR, 2^ndand 3^rdHarmonics vs. f_OUT, Maximum I_OUTFS(DAC Gain)

Figure 16. SFDR at Three DAC Sampling Frequencies (f_DAC) vs. f_OUT

–45

–50

–55

–60

–65

–40

DAC: b, TEMP: +25°C

DAC B, +25°C

DAC: b, TEMP: +85°C

DAC B, +85°C

DAC: b, TEMP: –40°C

DAC B, –40°C

–45

–50

–55

–60

–65

–70

–75

–80

DACA

–70

DACB

–75

–80

–85

–90

0

50

100

150

200

250

0

50

100

150

200

250

f_OUT(MHz)

Figure 17. IMD3 vs. f_OUT, Both DACs

Figure 14. SFDR at Three Temperatures vs. f_OUT

Rev. A | Page 13 of 56

AD9993

Data Sheet

f_DAC= 500 MHz, unless otherwise specified.

–45

–50

–55

–60

–65

–70

–75

–80

–135

–140

–145

–150

–155

–160

–165

f

_DAC= 500MHz, DAC A, +25°C, EXTERNAL CLOCK

_DAC= 500MHz, DAC A, +85°C, EXTERNAL CLOCK

_DAC= 500MHz, DAC A, –40°C, EXTERNAL CLOCK

f

_DAC= 300MHz, DAC B, EXTERNAL CLOCK

_DAC= 400MHz, DAC B, EXTERNAL CLOCK

_DAC= 500MHz, DAC B, EXTERNAL CLOCK

–85

–90

0

50

100

150

200

250

0

50

100

150

200

250

f_OUT(MHz)

Figure 18. IMD3 at Three DAC Sampling Frequencies (f_DAC) vs. f_OUT

Figure 19. NSD at Three Temperatures vs. f_OUT

Rev. A | Page 14 of 56

Data Sheet

AD9993

TERMINOLOGY

Settling Time

Linearity Error (Integral Nonlinearity or INL)

INL is defined as the maximum deviation of the actual analog

output from the ideal output, determined by a straight line

drawn from zero to full scale.

Settling time is the time required for the output to reach and

remain within a specified error band about its final value,

measured from the start of the output transition.

Spurious-Free Dynamic Range (SFDR)

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input code.

SFDR is the difference, in decibels (dB), between the rms

amplitude of the output signal and the peak spurious signal

over the specified bandwidth.

Monotonicity

Noise Spectral Density (NSD)

A digital-to-analog converter is monotonic if the output either

increases or remains constant as the digital input increases.

Noise spectral density is the average noise power normalized to

a 1 Hz bandwidth, with the DAC converting and producing an

output tone.

Offset Error

Offset error is the deviation of the output current from the ideal

of zero. For IOUTx_P, 0 mA output is expected when the inputs

are all 0s. For IOUTx_N, 0 mA output is expected when all

inputs are set to 1.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal

to the rms sum of all other spectral components below the

Nyquist frequency, excluding the first six harmonics and dc.

The value for SNR is expressed in decibels.

Gain Error

Gain error is the difference between the actual and ideal output

span. The actual span is determined by the output when all inputs

are set to 1, minus the output when all inputs are set to 0. The

ideal gain is calculated using the measured VREF. Therefore,

the gain error does not include effects of the reference.

Signal to Noise and Distortion (SINAD)

The ratio of the total signal power level (wanted signal + noise +

distortion or SND) to unwanted signal power (noise +

distortion or ND).

Output Compliance Voltage

Output compliance voltage is the range of allowable voltage

at the output of a current output DAC. Operation beyond the

maximum compliance limits can cause either output stage

saturation or breakdown, resulting in nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from

the ambient (25°C) value to the value at either T_MINor T_MAX

.

For offset and gain drift, the drift is reported in ppm of full-

scale range (FSR) per °C. For reference drift, the drift is

reported in ppm per °C.

Rev. A | Page 15 of 56

AD9993

Data Sheet

THEORY OF OPERATION

SPI_CS

(chip select) is an active low control signal used by the

PRODUCT DESCRIPTION

SPI_CS

SPI master to select the AD9993 SPI port. When

is

Figure 1 shows a block diagram of the MxFE. This product

integrates four 14-bit ADCs and two 14-bit DACs. The DAC

data interface consists of six DDR LVDS data lanes for each

DAC and a shared DCI_P/DCI_N clock (hereafter referred to

as DCI). The ADC data interface consists of four DDR LVDS

data lanes for each ADC with a shared DCO_P/DCO_N clock

(hereafter referred to as DCO) and a shared STROBE output.

The MxFE control and status registers are written/read via an

SPI interface. ADC and DAC datapaths include FIFO buffers to

absorb phase differences between LVDS lane timing and the

data converter sampling clocks. Internal AD9993 clock signals

can be developed from an external clock signal or from the

output of an on-chip PLL frequency multiplier driven by an

external reference oscillator.

high, SPI_SDO is in a high impedance state. During the

communication cycle, chip select must remain low.

SPI_SDI (serial data input) is the address and data input,

sampled on the rising edge of SPI_SCLK.

SPI_SDO (serial data output) is the data output pin. Data is

shifted out on the falling edge of SCLK

Figure 20 shows a timing diagram for a single byte MSB first

AD9993 SPI write operation. Each AD9993 register address is

an 8-bit value. During the first SPI_SCLK cycle, SPI_SDI = 0,

indicating that the operation is a data write. SPI_SDI is always

held low for the next two clock cycles. The next 13 clock cycles

are the first register address. The next eight clock cycles contain

SPI_CS

data to be written. The write operation ends when

high. In this example, data for one 8-bit register is written.

Multiple registers can be written in a single write operation by

SPI_CS

goes

SPI PORT

The AD9993 provides a 4-wire synchronous serial communica-

tions SPI port that allows easy interfacing to ASICs, FPGAs, and

industry-standard microcontrollers. The interface facilitates

read/write access to all registers that configure the AD9993. Its

data rate can be up to 25 MHz.

keeping

address is automatically updated using an address counter as

SPI_CS

low for multiple byte periods. The register

bytes are written while

remains low.

Figure 21 depicts an MSB first register read operation. Register

data from the AD9993 appears on SPI_SDO starting on the

SPI_SCLK cycle following the last bit of the 16-bit instruction

header on SPI_SDI. Multiple registers can be read in a single

SPI Port Signals

SPI_SCLK (serial clock) is the serial shift clock. The serial clock

pin synchronizes data to and from the device and runs the

internal state machines. All address and input data bits are

sampled on the rising edge of SPI_SCLK. All output data is

driven out on the falling edge of SPI_SCLK.

SPI_CS

read operation by keeping

periods.

low for multiple byte

SPI_CS

DON’T CARE

SPI_SCLK

DON’T CARE

R/W W1

DON’T CARE

W0

A12 A11 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SPI_SDI

SPI_SDO

16-BIT INSTRUCTION HEADER

REGISTER DATA

Figure 20. 4-Wire SPI Interface Timing, MSB First Write

SPI_CS

SPI_SCLK

SPI_SDI

DON’T CARE

W1

R/W

W0

A12 A11 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

REGISTER DATA

SPI_SDO

16-BIT INSTRUCTION HEADER

Figure 21. 4-Wire SPI Interface Timing, MSB First Read

Rev. A | Page 16 of 56

Data Sheet

AD9993

A_CML, B_CML, C_CML, and D_CML pins. Using these

SPI CONFIGURATION PROGRAMMING

common-mode voltage outputs to set the input common mode

of each ADC is recommended. Optimum performance is

achieved when the common-mode voltage of the analog input is

set by the on-chip common mode references. The A_CML,

B_CML, C_CML, and D_CML pins must be decoupled to

ground by a 0.1 μF capacitor.

The SPI_CONFIG register controls AD9993 SPI interface

operation. By default, the SPI bus operates MSB first. In MSB

fist mode, the register address counter decrements automati-

cally during multiple byte reads or writes. The SPI bus can be

configured to run LSB first by setting the SPI_LSB_FIRSTx bits

to 1. During LSB first multiple register read or write operations,

the register address counter is incremented automatically. SPI

registers can be reset to their Reset values by setting the self

clearing SPI_SOFT_RESETx bits to 1.

ADC SECTION PROGRAMMING

Each of the four ADCs has its power mode programmed by

the indexed ADC_PDWN_MODE bit field of the POWER_

MODES register (see the ADC Register Update Indexing

section). At reset, all four ADC cores are in power-down mode.

REGISTER UPDATE TRANSFER METHOD

Changes to the writeable SPI registers labeled transfer in Table 10

do not take effect immediately when written to the device via

the SPI. Values are held in a shadow register set until the self

clearing CHIP_REGMAP_TRANSFER bit in the DEVICE_

UPDATE register is set. All changes to transfer register values

then take effect simultaneously.

ADC digital data output modes are programmed by the indexed

FLEX_OUTPUT_MODE register (see the ADC Register Update

Indexing section). Setting the DP_OUT_DATA_EN_N bit to 0

enables the data output of each ADC selected in the DEVICE_

INDEX register. At reset, ADC output data is disabled. Setting

the DP_OUT_DATA_INV bit to 1 inverts the data output from

selected ADCs. The DP_OUT_DFS bit field selects the output

code for each selected ADC, offset binary (twos complement with

the sine bit inverted), twos complement (reset value), or gray code.

ADC REGISTER UPDATE INDEXING

In addition to the register transfer mechanism, the POWER_

MODES and FLEX_OUTPUT_MODE registers have an

indexing mechanism. Each of the four ADC cores has its own

page containing these registers. These pages can be

programmed independently or simultaneously in any

combination. ADC core register sets are addressed for a

particular register map master/slave transfer by setting the

SPI_ADC_x_INDEX bits in the DEVICE_INDEX register.

Register data is transferred to the ADC core pages that have

these bits set when the next transfer occurs.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9993 is a differential switched

capacitor circuit that has been designed for optimum

performance while processing a differential input signal.

For baseband applications where SNR is a key parameter,

differential transformer coupling is the recommended input

configuration. An example is shown in Figure 22. To bias the

analog input, the V_CMvoltage can be connected to the center tap

of the secondary winding of the transformer.

ADCs

The MxFE ADCs are multistage pipelined CMOS ADC cores

designed for use in communications receivers.

C2

R3

R2

ADC ARCHITECTURE

x_VINP

R1

The AD9993 architecture consists of a dual front-end sample-

and-hold circuit, followed by a pipelined switched capacitor

ADC. The quantized outputs from each stage are combined into

a final 14-bit result.

2V p-p

49.9Ω

C1

R1

ADC

x_CML

R2

x_VINN

33Ω

0.1µF

R3

The input stage of each ADC core contains a differential

sampling circuit that can be ac- or dc-coupled in differential or

single-ended modes.

C2

Figure 22. Differential Transformer-Coupled Configuration

Input Common-Mode Voltage (V_CM) References

Differential double balun coupling is used as the input

The analog inputs of the AD9993 are not internally dc biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that V_CM= 0.5 × AVDD (or

0.9 V) is recommended for optimum performance. Four

on-board common-mode voltage references are included in the

design, one for each AD9993 ADC, and are available from the

configuration for AD9993 ADC performance characterization

(see Figure 23). In this configuration, the input is ac-coupled and

the V_CMvoltage is provided to each input through a 33 Ω resistor.

These resistors compensate for losses in the input baluns to

provide a 50 Ω impedance to the driver.

Rev. A | Page 17 of 56

AD9993

Data Sheet

C2

R3

R1

0.1µF

R2

x_VINP

ADC

x_CML

2V p-p

33Ω

P

A

S

P

C1

R1

0.1µF

x_VIN

N

R3

33Ω

0.1µF

C2

Figure 23. Differential Double Balun Input Configuration

In the double balun and transformer configurations, the value of

the input capacitors and resistors is dependent on the input

frequency and source impedance. Based on these parameters,

the value of the input resistors and capacitors may need to be

adjusted or some components may need to be removed. Table 7

displays recommended values to set the RC network for the

0 MHz to 100 MHz frequency range:

DACs

The MxFE DACs are part of the Analog Devices high speed

CMOS DAC core family. These DACs are designed to be used

as part of wide bandwidth communication system transmitter

signal chains.

DAC TRANSFER FUNCTION

The AD9993 DACs provide two differential current outputs:

IOUTA_P/IOUTA_N, and IOUTB_P/IOUTB_N.

Table 7. Example RC Network

Component

R1 Series

C1 Differential

R2 Series

Value

33 Ω

ꢀ.2 pF

± Ω

15 pF

49.9 Ω

The DAC output current equations are as follows:

IOUTx_P = I_OUTFS× DACx input code/2¹⁴

IOUTx_N = I_OUTFS× ((2¹⁴− 1) − DACx input code)/2¹⁴

C2 Shunt

R3 Shunt

where:

DACx input code = 0 to 2¹⁴− 1.

The values given in Table 7 are for each R1, R2, C1, C2, and R3

component shown in Figure 22 and Figure 23.

I

_OUTFSis the full-scale output current or DAC gain specified in

Table 1.

ADRF6518 as ADC Driver

I

_OUTFS= 32 × I_IREFx

The ADRF6518 is a variable gain amplifier and low-pass filter

that is designed to drive the analog inputs of analog-to-digital

converters like the ones included in the AD9993. A principle

application of the ADRF6518 is as part of the signal chain in a

wideband radio receiver. Figure 32 shows a block diagram for a

wideband microwave radio that includes the ADRF6518 and

the AD9993.

where I_REFx= V_REFDAC/R_{FSADJ_x}

.

Each DAC has its own I_REFxset resistor, R_{FSADJ_x}. R_{FSADJ_x}resistors

can be on or off chip at the discretion of the users. The nominal

value of R_{FSADJ_x}is 1.6 kΩ. The nominal value of V_REFDACis 1.0 V.

V

_REFDACcan be selected as the on-chip band gap reference or as

an external user supplied reference.

DAC outputs have a sin(πf_OUT/f_DAC)/(πf_OUT/f_DAC) envelope

response as a function frequency. This response is also referred

to as a sinc envelope.

The low impedance (<10 Ω) output buffers of the ADRF6518

are designed to drive ADC inputs. They are capable of delivering

up to 4 V p-p composite two-tone signals into 400 Ω differential

loads with >60 dBc IMD3. The output common-mode voltage

can be adjusted to 900 mV (the AD9993 input common-mode

voltage) without loss of drive capability by presenting the

ADRF6518 VOCM pin with the desired common-mode voltage.

The high input impedance of VOCM allows the AD9993 refer-

ence output (A_CML, B_CML, C_CML or D_CML) to be

connected directly.

DAC OUTPUT COMPLIANCE VOLTAGE RANGE

AND AC PERFORMANCE

Each DAC has a pair of differential current outputs. The

compliance voltage range for each of these two outputs is

specified in Table 1. Optimal DAC ac performance is achieved

when the output common-mode voltage is between 0.0 V and

0.5 V. and the signal swing falls within the compliance range.

Rev. A | Page 1ꢀ of 56

Data Sheet

AD9993

DAC_REF_EXT = 0

REG 0x039[0]

CLKA

BAND GAP

TRIM

I

25ꢀ

OUTP

1.0V

DAC_A

I

OUTN

±1%

I

A

MEAS

NOTE:

DEFAULT VALUES FOR

DAC A GAIN AND

DAC B GAIN ARE

SET AT FACTORY TRIM

FOR IFS = 20mA WITH

DAC_RSET_EN = 1

DAC_CAL_IQ_SEL

REG 0x03C[1]

–0.25V

TO +0.25V

CAL IQ

1

0

I

B

MEAS

I

25ꢀ

OUTP

DAC_RSET_EN = 1

REG 0x039[1]

I

DAC_B

CLKB

OUTN

DAC_RSET_EN = 0

REG 0x039[1]

1.6kꢀ

TRIM

±3%

–0.25V

TO +0.25V

ON CHIP

1.6kꢀ

±2%

1.6kꢀ

±2%

0.1µF

Figure 24. DACs, Band Gap Reference, On-Chip and Off-Chip R_{FSADJ_x}, DAC Gain Setting, and IQ Calibration

DAC IQ Gain Calibration

Selecting DAC Output Common-Mode Voltage

When board level R_{FSADJ_x}resistors are used, the gains of the two

DACs can be better matched by running the automatic DAC IQ

gain calibration procedure. This is done by programming the

DAC_CAL_IQ_CTRL register and observing the

Two steps are required to select the common-mode output

voltages for the two DACs. For a common-mode voltage less

than 0.5 V, the CML_A and CML_B pins are grounded. For

common-mode voltages that are greater than or equal to 0.5 V,

connect a 0.1 ꢀF capacitor between CML_A or CML_B and

ground. The second step is to program the DAC_VCM_

VREF_BIT bit field. There are three common-mode level

settings to choose from. This common-mode setting applies to

both DACs.

DAC_CAL_IQ_STAT register as follows:

1. Write 0x23 to DAC_CAL_IQ_CTRL (power up the DAC

clock, enable IQ calibration, and start IQ calibration).

2. Read the DAC_CAL_IQ_DONE bit of the

DAC_CAL_IQ_STAT register until it goes high.

3. Write 0x4 to DAC_CAL_IQ_CTRL.

DAC VOLTAGE REFERENCE

DAC DATAPATH FORMAT SELECTION

The DACs use a single common voltage reference. An on-chip

band gap reference is provided. Optionally, an off-chip voltage

reference can be used. If an off-chip DAC reference is used, set

the DAC_REF_EXT bit in the DAC_CTRL register to 1. After

reset, the on-chip reference is selected.

At reset, the DAC_BINARY bit in the DAC_DP_FMT register is

set to 0, selecting twos complement as the data input format for

both DACs. To select binary offset, set the DAC_BINARY bit to 1.

DAC TEST TONE GENERATOR DDS

DAC GAIN SETTING

The AD9993 includes a tunable direct digital synthesizer for

DAC output tone generation. When the DDS_EN bit of the

DDS_CTRL register is set to 1, the DDS becomes the digital

signal source for the two DACs. The DDS_CTRL register also

has a clock inversion control and amplitude attenuation

controls. At reset, the 32-bit DDS tuning word in the

DDS_TW1_3, DDS_TW1_2, DDS_TW1_1, and DDS_TW1_0

registers is set to 0x19A00000. This value programs the DDS to

produce a 50 MHz tone at both DAC outputs if the master clock

frequency is 1 GHz (DAC sampling rate = 500 MSPS). The

equation for DDS output frequency is

Figure 24 is a diagram of the AD9993 DACs gain setting

section. It shows the two transmit DACs, the bypassable built-in

1.0 V band gap reference, and the selectable internal and board

level R_{FSADJ_x}resistors. By default, the on-chip band gap

reference is selected. If using a board level. DAC reference

voltage, write 1 to the DAC_REF_EXT bit of the DAC_CTRL

register.

Each DAC has its own R_{FSADJ_x}set resistor. These resistors can be

on or off chip at the discretion of the user. When the on-chip

resistors are in use, their gain accuracy is factory calibrated.

When the off-chip R_{FSADJ_x}resistors are used, an on-chip IQ

calibration scheme can be employed to maintain accuracy

between DAC pairs. By default, the on-chip R_{FSADJ_x}is selected.

If using a board level R_{FSADJ_x}, write 0 to the DAC_RSET_EN bit

of the DAC_CTRL register.

f

_DDS= (DDS_TW1/2³²) × f_DAC

Rev. A | Page 19 of 56

AD9993

Data Sheet

the master clock, the buffered VCO output signal is divided by 4

to produce the synthesized master clock signal.

CLOCKING

The clock signals for the LVDS lanes, the DACs, and the ADCs

are developed from a single master clock signal. This signal is

either input directly on the CLKP/CLKN pins or synthesized by

an on-chip PLL multiplier using the REFCLK input signal as a

reference. The ADC output and DAC input LVDS lanes run at

the master clock frequency divided by 2 and are DDR. Data is

clocked on both edges. The sampling rate of the ADCs is ¼ the

master clock rate. The sampling rate of the DACs is ½ the

master clock frequency. A 1 GHz master clock is shown in

Figure 1.

The reference clock of the on-chip PLL can be either 31.25 MHz

or 62.5 MHz. When using a 62.5 MHz clock, a divide by 2

option is provided, as shown in Figure 25, such that the internal

PLL reference clock can be set to 31.25 MHz.

A programmable loop filter is integrated on chip. At reset, the

on-chip loop filter bandwidth is set to 500 kHz. Lower loop

bandwidth can be achieved using an external loop filter

connected to the CP pin, as shown in Figure 25.

An on-chip LDO provides the supply voltage for the VCO.

At a 1 GHz master clock frequency, the other on-chip clock

frequencies are as follows:

PLL Synthesizer Control and Status Registers

At reset, the SYNTH_INT register contains the reset default

value for the VCO output divider of 64 (shown in Figure 25).

The PLL multiplier lock status can be read back on Bit 1 of the

SYNTH_STAT register. Calibration status is also read from this

register. Bits in the SYNTH_CTRL register are used to enable

charge pump calibration and to start synthesizer calibration.

Synthesizer calibration is required as part of the process of

acquiring lock. Charge pump calibration and synthesizer

calibration are steps described in the Power-Up Routine When

Using the On-Chip Clock Synthesizer section.



DCO (ADC DDR LVDS output lane clock): 500 MHz

DCI (DAC DDR LVDS input lane clock): 500 MHz

DAC sampling rate: 500 MSPS

ADC sampling rate: 250 MSPS

ON-CHIP PLL CLOCK MULTIPLIER

Figure 25 shows a block diagram of the MxFE on-chip PLL

clock multiplier. If the PLL clock multiplier is used to generate

PROGRAMABLE

REG 0x031

VDD = 1.8V

FIXED

DIVIDER

÷64

DIVIDER

0.1µF

÷2

VCO

LDO

BYP_R3

BUF

1.5V

0.1µF

PFD

BUF

REFCLK =

31.25MHz

R3

C3

R1

C1

VCO

4GHz

EXT_CP

_SEL

C2

VCO

CAL

ON-CHIP LOOP FILTER

PROGRAMABLE BY

REG 0x02E TO REG 0x030

CP

R110

487ꢀ

C62

390pF

C67

22nF

NOTES

1. WHEN USING EXTERNAL LOOP FILTER SET C1, C2, C3, R1, AND R3 TO

MIN OR MAX VALUES AS DEFINED IN REGISTER DESCRIPTION, AS DESIRED.

Figure 25. On-Chip PLL Clock Multiplier Block Diagram

Rev. A | Page 2± of 56

Data Sheet

AD9993

MASTER

CLOCK INPUT

CLKP

CLKN

Reg 0x034[1:0]

CLKGEN_MODE

00 = INTERNAL 1GHz CLOCK

11 = EXTERNAL CLOCK (200MHz TO 1GHz)

200MHz TO

1000MHz

100ꢀ

1.8V

DIFF

8kꢀ

15kꢀ

8kꢀ

1

0

TO DAC,

ADC, AND

LVDS

REG 0x034[1:0]

CLKGEN_MODE

REFCLK = 31.25MHz

OR

1

0

62.5MHz

PLL

÷2

Reg 0x031[7:0]

PLL Input Freq | SYNTH_INT

31.25MHz | 0x80

62.5MHz | 0x40

Reg 0x031[7:0]

SYNTH_INT

Reg 0x033[5]

CLKGEN_REFCLK_DIV1

Figure 26. MxFE Clock Control

as the RXFIFO_THERM[7:0] value in the DAC_FIFO_STS1

register. This value is a thermometer code. FIFO depths remain

constant after initialization when all clocks are running

properly.

SELECTING CLOCKING OPTIONS

Figure 26 is a block diagram of the MxFE clocking system and

its controls. Options of using either an external master clock or

a master clock generated from the on-chip PLL are provided.

CLKGEN_MODE[1:0] in the CLKGEN_CTRL2 register selects

the PLL multiplier or CLKP/CLKN as the master clock source.

LVDS INTERFACES

Each DAC has seven DDR LVDS input data lanes. Each DAC

sample input requires the user to input two 7-bit words to the

interface with appropriate zero stuffing. Each ADC has four

DDR LVDS output data lanes. For each ADC output sample,

four 4-bit words are output.

ADC DATAPATH AND DAC DATAPATH FIFOS

In the AD9993, data FIFOs are placed between the ADC core

outputs and the LVDS buffers and drivers. Similarly, on the

DAC side, data FIFOs are placed between the LVDS input

buffers and the DAC cores. These FIFOs absorb the phase

difference between DCI and the DAC sampling clock and

between the ADC sampling clock and DCO. DAC sampling

clock and DCI are locked in frequency but have an unknown

phase relationship. The ADC sampling clock and DCO have the

same characteristics.

LVDS ADC Data Link

There are two LVDS ADC buses for the two ADCs. Each LVDS

ADC Data bus has four lanes for 14-bit data output in two full

DDR cycles. A strobe lane is shared by the four ADC LVDS

links to identify the MSB of the 14-bit data. Figure 27 shows one

LVDS ADC output data link with four lanes. Lane 0 to Lane 2

output the 12 MSBs of the 14-bit ADC data. Lane 3 carries the

two LSBs of the 14-bit ADC data and an overrange bit.

FIFOs are eight samples deep. During a start-up register

sequence, both the DAC input datapath FIFOs and the ADC

output data path FIFOs have their read and write pointers

initialized (see the Start-Up Register Sequences section). This

occurs after all clocks in the AD9993 are running and settled.

The pointers are set four data samples apart. The ADC datapath

FIFO depth can be read in the RXFIFO_WR_OFFSET bit field

in the align register. The DAC datapath FIFO depth can be read

LVDS DAC Data Link

There are two LVDS DAC data links for the dual DAC. Each

LVDS DAC data link has seven lanes capable of transmitting

14-bit data in one DDR full cycle. Figure 28 shows one LVDS

DAC input data link with seven lanes.

Rev. A | Page 21 of 56

AD9993

Data Sheet

ADC LVDS

A/B/C/D

DCO_P

(DATA CLOCK OUTPUT PORT)

STROBE+

LANE 3

LANE 2

LANE 1

LANE 0

D[–2]

OVERRANGE

(SAMPLE N)

D[–1]

D[–2]

OVERRANGE

0

(SAMPLE N – 1)

(SAMPLE N)

(SAMPLE N + 1)

D[2]

(SAMPLE N – 1)

D[11]

(SAMPLE N)

D[8]

(SAMPLE N)

D[5]

(SAMPLE N)

D[2]

(SAMPLE N)

D[11]

(SAMPLE N + 1)

D[1]

(SAMPLE N – 1)

D[10]

(SAMPLE N)

D[7]

(SAMPLE N)

D[4]

(SAMPLE N)

D[1]

(SAMPLE N)

D[10]

(SAMPLE N + 1)

D[0]

(SAMPLE N – 1)

D[9]

(SAMPLE N)

D[6]

(SAMPLE N)

D[3]

(SAMPLE N)

D[0]

(SAMPLE N)

D[9]

(SAMPLE N + 1)

Figure 27. Output Sample Data Format

DCI_P

(DATA CLOCK INPUT PORT)

D[6]

(SAMPLE N – 1)

D[13]

(SAMPLE N)

D[6]

(SAMPLE N)

D[13]

(SAMPLE N + 1)

D[6]

(SAMPLE N + 1)

D[13]

(SAMPLE N + 2)

LANE 6

LANE 5

D[5]

(SAMPLE N – 1)

D[12]

(SAMPLE N)

D[5]

(SAMPLE N)

D[12]

(SAMPLE N + 1)

D[5]

(SAMPLE N + 1)

D[12]

(SAMPLE N + 2)

D[4]

(SAMPLE N – 1)

D[4]

(SAMPLE N)

D[4]

(SAMPLE N + 1)

D[11]

(SAMPLE N)

D[11]

(SAMPLE N + 1)

D[11]

(SAMPLE N + 2)

LANE 4

D[3]

(SAMPLE N – 1)

D[10]

(SAMPLE N)

D[3]

(SAMPLE N)

D[10]

(SAMPLE N + 1)

D[3]

(SAMPLE N + 1)

D[10]

(SAMPLE N + 2)

LANE 3

LANE 2

LANE 1

D[2]

(SAMPLE N – 1)

D[9]

(SAMPLE N)

D[2]

(SAMPLE N)

D[9]

(SAMPLE N + 1)

D[2]

(SAMPLE N + 1)

D[9]

(SAMPLE N + 2)

D[1]

(SAMPLE N – 1)

D[8]

(SAMPLE N)

D[1]

(SAMPLE N)

D[8]

(SAMPLE N + 1)

D[1]

(SAMPLE N + 1)

D[8]

(SAMPLE N + 2)

D[0]

(SAMPLE N – 1)

D[7]

(SAMPLE N)

D[0]

(SAMPLE N)

D[7]

(SAMPLE N + 1)

D[0]

(SAMPLE N + 1)

D[7]

(SAMPLE N + 2)

LANE 0

Figure 28. DAC Input Sample Data Format

LVDS INTERFACE TIMING

DATA PERIOD

DAC Input Interface

Table 8 specifies the setup and hold time requirements for DAC

LVDS data lane inputs relative to DCI. Figure 29 shows a timing

diagram for this interface. DDR DCI edges occur at the position

within the data eye (the white region in Figure 29) listed in

Table 8.

CLOCK

DATA

t_SUt_HOLD

Table 8. DAC DDR LVDS Input Setup and Hold Times

Relative to DCI (Guaranteed)

Figure 29. DAC Input LVDS Lane Timing

ADC Output Interface

Parameter

Minimum

Unit

DATA

PERIOD

DATA

PERIOD

|t_SU|

15±

ps

|t_HOLD

Data Period

|

2±±

1±±±

ps

Ps

DCO_P/

DCO_N

STROBE_P/

STROBE_N

DATA

t_SUt_HOLD

Figure 30. ADC Output LVDS Lane Timing

Rev. A | Page 22 of 56

Data Sheet

AD9993

Table 9 specifies the time between the ADC LVDS data lane

output transitions and the DDR DCO clock edge 50% transition

point.

The eight events that trigger an interrupt (if enabled) are



PLL lock lost

PLL locked

FIFO Warning 1

FIFO Warning 2

ADC A overrange

ADC B overrange

ADC C overrange

ADC D overrange

Table 9. ADC DDR LVDS Data and Strobe Output Setup and

Hold Times Relative to DCO (Guaranteed)

Parameter

Minimum

Unit

|t_SU|

4±±

ps

|t_HOLD

|

43±

ps

Data Period

1±±±

ps

Interrupt Service Routine

LVDS LANE TESTING USING PRBS

For the interrupt service routine, interrupt request management

starts by selecting the set of events that require host interven-

tion or monitoring using the bits in the INTEN register. For

One pseudorandom binary sequence (PRBS) generator is

included for each ADC LVDS lane and one PRBS detector on

each DAC LVDS lane. The designs for the generator and

detector are implemented as a 23^rd-order pseudorandom noise

(PN23) sequence defined by the generator polynomial x²³+ x¹⁸+ 1.

The initial seed of the generator is programmable so that each

lane can output different values if started simultaneously. The

four seed registers are indexed as described in the ADC Register

Update Indexing section.

ALERT

events requiring host intervention, upon

activation, run

the following routine to clear an interrupt request:

1. Read the status of the latched bits in the INT register that

are being monitored.

2. Monitor the unlatched status bits in the INT_RAW register

directly if needed.

3. Perform any actions that may be required to clear the

interrupt(s).

4. Read the INT_RAW bits to verify that the actions taken

have cleared the event.

DAC PRBS test results are read back on the DAC_A_PRBS_ERRx

and DAC_B_PRBS_ERRx error counter registers. The DAC

input PRBS error counters are enabled and the error counters

cleared by the bits in the DAC_PRBS_CTRL register. ADC

output lane PRBS generation is controlled by the bits in the

PRBS_GEN_CTRL register.

5. Clear the interrupt by writing 1 to the event flag bit in the

INT register.

TEMPERATURE SENSOR

POWER MODE PROGRAMMING

The AD9993 has a diode-based temperature sensor for

measuring the temperature of the die. The temperature reading

is accessed using the TS_RD_LSB and TS_RD_MSB registers.

The temperature of the die can be calculated as

The AD9993 has a POWER_MODES register that allows the

user to place sections of the chip into different power modes.

The PDWN_PIN_FUNC bit programs the function of the

PDWN pin. By default, assertion of PDWN causes the AD9993

to go into full power-down. The clock generator, indexed

ADCs, DACs, and PLL synthesizer are all powered down at

reset. The indexed ADCs have four power modes. See the ADC

Register Update Indexing section for a definition of indexing.

Die Temp[15:0]  41,237

T_DIE



106

where:

_DIEis the die temperature in degrees Celsius.

T

INTERRUPT REQUEST OPERATION

Die Temp is the concatenated 16-bit contents of the TD_RD_LSB

and TD_RD_MSB registers. The temperature accuracy is 7°C

typical over the −40°C to +85°C range with one point

temperature calibration against a known temperature. A typical

plot of the die temperature code readback vs. die temperature is

shown in Figure 31.

ALERT

The AD9993 provides an interrupt request signal,

used to notify the user system of significant on-chip events. The

ALERT

. It is

pin is an open-drain, active low output.

Eight different event flags provide visibility into the device.

These raw events are located in the INT_RAW register. These

raw events are always latched in the INT register. If the event is

left unmasked, the latched event triggers an external interrupt

ALERT

on

event is masked, the INT register captures the event in latched

ALERT

. INTEN is the interrupt enable register. When an

form. A masked event does not cause

to go true.

Rev. A | Page 23 of 56

AD9993

Data Sheet

51000

49000

47000

45000

43000

41000

39000

37000

35000

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE (°C)

Figure 31. Die Temperature Code Readback vs. Die Temperature

Estimates of the ambient temperature can be made if the power

dissipation of the device is known.

Rev. A | Page 24 of 56

Data Sheet

AD9993

START-UP REGISTER SEQUENCES

POWER-UP ROUTINE WHEN USING THE ON-CHIP

CLOCK SYNTHESIZER

Synchronize LVDS Interface

SPI.Write(0x00A, 0x82); synchronize ADC

data with DCO clock, self cleared but

needs following SPI clock

To power up the device, set the register settings as described in

the following sections.

SPI.Write(0x00A, 0x81); realign Tx FIFO

read and write pointers, self cleared but

need following SPI clock

Chip Power-Up

SPI.Write(0x008, 0x00); power up all

blocks

SPI.Write(0x00A, 0x90); realign Rx FIFO

read and write pointers, DCI clock must be

present, self cleared but need following

SPI clock

DAC Setup

SPI.Write(0x03A, 0x02); DAC data format

offset binary

Miscellaneous

or

Clear Interrupt

SPI.Write(0x03A, 0x00); DAC data format

twos complement

SPI.Write(0x0F0, 0xFF)

Enable Interrupt

ADC Setup

SPI.Write(0x013, 0x00); enable ADC LVDS

output and offset binary

SPI.Write(0x0F1, 0xFF)

SPI.Write(0x055, 0x01); ALERT_PULLUP_EN

(optional)

or

SPI.Write(0x013, 0x01); enable ADC LVDS

output and twos complement

SPI.Write(0x0FF, 0x01); transfer

SPI.Write(0x039, 0x12); set DAC CML based

on compliance range of 0.7 V and on-chip

R_{FSADJ_x}resistors

SPI.Write(0x014, 0x01); set LVDS to 2 mA

(optional: 1 mA is default)

SPI.Write(0x0FF, 0x01); transfer

Set this bit if using DAC compliance range > 0.7 V.

Synthesizer Setup (62.5 MHz Reference Clock Input)

SPI.Write(0x032, 0x01); SYNTH_CP_CAL_EN

SPI.Write(0x0FF, 0x01); transfer

SPI.Write(0x0ff, 0x001); data transfer

POWER-UP ROUTINE WHEN USING EXTERNAL

CLOCK

SPI.Write(0x032, 0x11); start synthesizer

calibration

Chip Power-Up

SPI.Write(0x008, 0x00); power up all

blocks

SPI.Write(0x0FF, 0x01); transfer

SPI.Read(0x02D); synthesizer status

0x01; calibration in progress

DAC Setup

SPI.Write(0x03A, 0x02); DAC data format

offset binary

0x04; calibration done, synthesizer no

lock

or

0x06;calibration done, synthesizer locked

Sythesizer Setup (31.25 MHz Reference Clock Input)

SPI.Write(0x033, 0x20); CLKGEN_REFCLK_DIV1

SPI.Write(0x03A, 0x00); DAC data format

twos complement

ADC Setup

SPI.Write(0x013, 0x00); enable ADC LVDS

output and offset binary

SPI.Write(0x032, 0x01); synthesizer

CP_CAL_EN

or

SPI.Write(0x0FF, 0x01); transfer

SPI.Write(0x013, 0x01); enable ADC LVDS

output and twos complement

SPI.Write(0x032, 0x11); start synth

calibration

SPI.Write(0x014, 0x01); set LVDS to 2 mA

(optional: 1 mA is default)

SPI.Write(0x0FF, 0x01); transfer

SPI.Read(0x02D); synthesizer status

0x01; calibration in progress

SPI.Write(0x0FF, 0x01); transfer

External Clock Setup

0x04; calibration done, synthesizer no

lock

SPI.Write(0x034, 0x07); set external clock

mode

0x06; calibration done, synthesizer

locked

SPI.Write(0x0FF, 0x01); transfer

Rev. A | Page 25 of 56

AD9993

Data Sheet

Synchronize LVDS Interface

Enable Interrupt

SPI.Write(0x00A, 0x82); synchronize ADC

data with DCO clock, self cleared but

needs following SPI clock

SPI.Write(0x0F1, 0xFF)

SPI.Write(0x055, 0x01); ALERT_PULLUP_EN

(optional)

SPI.Write(0x00A, 0x81); realign Tx FIFO

read and write pointers, self cleared but

need following SPI clock

SPI.Write(0x0FF, 0x01); transfer

SPI.Write(0x039, 0x12); set DAC CML based

on compliance range of 0.7 V and on-chip

R_{FSADJ_x}resistors,

SPI.Write(0x00A, 0x90); realign Rx FIFO

read and write pointers, DCI clock must be

present, self cleared but need following

SPI clock.

Set this bit if using DAC compliance range > 0.7 V

SPI.Write(0x0FF, 0x001); data transfer

Miscellaneous

Clear Interrupt

SPI.Write(0x0F0, 0xFF)

Rev. A | Page 26 of 56

Data Sheet

AD9993

APPLICATIONS INFORMATION

must fall within an allowable voltage range, which gives rise to a

common-mode voltage requirement at the outputs of the DACs.

DIRECT CONVERSION RADIO APPLICATION

A direct conversion radio application of the MxFE is shown in

Figure 32. The DAC output signals, IOUTA_P/IOUTA_N and

IOUTB_P/IOUTB_N, are differential currents. At 500 MSPS,

DAC output signals fall within the 1^stNyquist zone (dc to

250 MHz). DAC current outputs are converted to a voltage and

then processed by passive low-pass filters (LPF). The low-pass

filters reject out of band signal harmonics and their sampling

images. The filter outputs feed the baseband inputs of a

The MxFE receive signal chain consists of a VGA followed by a

quadrature demodulator, then by a programmable LPF, and

another VGA. The ADRF6518 is an LPF and VGA specifically

designed to drive the analog inputs of high speed ADCs like the

ones on the MxFE. The LPF is an antialiasing filter. At

250 MSPS, the ADC signal bandwidth is 125 MHz.

See the ADRF6518 as ADC Driver section for further

information about this interface.

quadrature modulator. Quadrature modulator baseband inputs

AD9993

PLL AND CLOCK

CLKP

DISTRIBUTION

500MSPS

DACs

CLKN

OR BYPASS

PASSIVE LPF

IOUTA_x

DINxA_x, DINxB_x

DCI_x

QUAD

MODULATOR

RF OUT

VGA

IOUTB_x

DATA

ASSEMBLER

DOUTxA_x/DOUxB_x

PROGRAMMABLE

LPF AND VGA

DCO_x

A_VINx, B_VINx

C_VINx, D_VINx

RF IN

STROBE_x

QUAD

DEMOD

VGA

ADRF6518

RST

SPI_SDI, SPI_SDO

SPI_SCLK

SERIAL

250MSPS

ADCs

PORT

REFERENCES

AND BIAS

LOGIC

SPI_CS

Figure 32. Radio Signal Chain Example

Rev. A | Page 27 of 56

AD9993

Data Sheet

REGISTER MAP

Table 10. SPI Accessible Register Summary

Address Name

Description

Reset Value

RW

R

±x±±±

±x±±1

±x±±2

±x±±5

±x±±ꢀ

±x±±A

±x±±C

±x±1±

±x±11

±x±12

±x±13

±x±14

±x±16

±x±17

±x±2±

±x±21

±x±22

±x±23

±x±2D

±x±2E

±x±2F

±x±3±

±x±31

±x±32

±x±33

±x±34

±x±35

±x±36

±x±37

±x±3ꢀ

±x±39

±x±3A

±x±3C

±x±3D

±x±3F

±x±4±

±x±41

±x±42

±x±43

±x±44

±x±45

±x±46

±x±47

±x±4ꢀ

±x±49

±x±4A

±x±4B

±x±4C

±x±4D

±x±4E

SPI_CONFIG

CHIP_ID

SPI configuration

Chip ID

±x1ꢀ

±xB2

±x±1

±x±F

±x55

±xꢀ±

±x±1

±x±±

±x11

±x±±

±x±1

±x±2

±x±3

±x±4

±x±±

±x77

±xF7

±x±±

±x4±

±x±±

±x±4

±x4D

±x±±

±x±2

±x±±

±x±4

±x±±

±x55

±x±±

CHIP_GRADE

Device index

Power mode control (indexed)

Align ADC LVDS clocks, ADC FIFO, DAC FIFO

Reserved

Strobe lane control (transfer)

Output mode (transfer, indexed)

LVDS Tx control (transfer)

R

DEVICE_INDEX

POWER_MODES

ALIGN

Reserved

RW

R

Reserved

STROBE_CTRL

RW

R

RW

R

RW

R

FLEX_OUTPUT_MODE

FLEX_OUTPUT_ADJUST

FLEX_VREF

PRBS_GEN_CTRL

PRBS±_SEED_MSB

PRBS1_SEED_MSB

PRBS2_SEED_MSB

PRBS3_SEED_MSB

SYNTH_STAT

LF_CTRL1

LF_CTRL2

LF_CTRL3

SYNTH_INT

V_REFcontrol (transfer)

PRBS generator control (transfer, indexed)

ꢀ-bit seed MSB of PRBS generator for Lane± (transfer, indexed)

ꢀ-bit seed MSB of PRBS generator for Lane1 (transfer, indexed)

ꢀ-bit seed MSB of PRBS generator for Lane2 (transfer, indexed)

ꢀ-bit seed MSB of PRBS generator for Lane3 (transfer, indexed)

Synthesizer status

Loop filter control signals (transfer)

Integer value of synthesize divider (transfer)

Synthesizer control (transfer)

Clock generator control (transfer)

CLKGEN control (transfer)

DAC LVDS Rx control (transfer)

DAC LVDS current bias control (transfer)

Reserved

SYNTH_CTRL

CLKGEN_CTRL1

CLKGEN_CTRL2

DAC_LVDS_CTRL

DAC_LVDS_BIAS

Reserved

DAC_CTRL

DAC_DP_FMT

DAC_CAL_IQ_CTRL

DAC_CAL_IQ_STAT

DAC_FIFO_STS1

DAC_PRBS_CTRL

DAC_A_PRBS_ERR±

DAC_A_PRBS_ERR1

DAC_A_PRBS_ERR2

DAC_A_PRBS_ERR3

DAC_A_PRBS_ERR4

DAC_A_PRBS_ERR5

DAC_A_PRBS_ERR6

DAC_B_PRBS_ERR±

DAC_B_PRBS_ERR1

DAC_B_PRBS_ERR2

DAC_B_PRBS_ERR3

DAC_B_PRBS_ERR4

DAC_B_PRBS_ERR5

DAC_B_PRBS_ERR6

Reserved

DAC cores control (transfer)

DAC datapath format control (transfer)

DAC IQ calibration control (transfer)

DAC IQ calibration status

DAC Rx FIFO Status 1

PRBS detector control (transfer)

PRBS Detector Error Count ± for DAC A

PRBS Detector Error Count 1 for DAC A

PRBS Detector Error Count 2 for DAC A

PRBS Detector Error Count 3 for DAC A

PRBS Detector Error Count 4 for DAC A

PRBS Detector Error Count 5 for DAC A

PRBS Detector Error Count 6 for DAC A

PRBS Detector Error Count ± for DAC B

PRBS Detector Error Count 1 for DAC B

PRBS Detector Error Count 2 for DAC B

PRBS Detector Error Count 3 for DAC B

PRBS Detector Error Count 4 for DAC B

PRBS Detector Error Count 5 for DAC B

PRBS Detector Error Count 6 for DAC B

Rev. A | Page 2ꢀ of 56

Data Sheet

AD9993

Address Name

Description

Reset Value

RW

R

RW

R

±x±5±

±x±51

±x±52

±x±53

±x±54

±x±55

±x±6±

±x±61

±x±62

±x±63

±x±64

±x±F±

±x±F1

±x±F2

±x±FF

TS_RD_LSB

TS_RD_MSB

Reserved

TS_CTRL

IRQ_CTRL

DDS_CTRL

DDS_TW1_±

DDS_TW1_1

DDS_TW1_2

DDS_TW1_3

INT

Bits[7:±] of Temperature sensor data readback

Bits[15:ꢀ] of Temperature sensor data readback

Reserved

Temperature sensor control signals

Interrupt pin control

±x±±

±x±1

±x±±

±xA±

±x19

±x±±

DDS control

DDS tuning word for Tone 1

Interrupt status

Interrupt enable (transfer)

Interrupt source status

Global device update register

INTEN

INT_RAW

DEVICE_UPDATE

RW

R

RW

Rev. A | Page 29 of 56

AD9993

Data Sheet

REGISTER DESCRIPTIONS

SPI CONFIGURATION REGISTER

Address: 0x000, Reset: 0x18, Name: SPI_CONFIG

Table 11. Bit Descriptions for SPI_CONFIG

Bits

Bit Name

Description

Reset

Access

6

SPI_LSB_FIRST2

SPI least significant bit first.

±x±

RW

1 = least significant bit shifted first for all SPI operations. On multibyte SPI

operations, addressing increments automatically.

± = most significant bit shifted first for all SPI operations. On multibyte SPI

operations, addressing decrements automatically.

This bit must be accessed with all devices enabled and is not reset by

setting the SPI_SOFT_RESET1 or SPI_SOFT_RESET2 bit.

5

SPI_SOFT_RESET2

Self Clearing Soft Reset 1. Reset the SPI registers (self clearing).

This bit must be accessed with all devices enabled.

13-bit addressing mode always enabled.

±x±

RW

[4:3]

2

SPI_ADDR_MODE

SPI_SOFT_RESET1

±x3

±x±

R

Self Clearing Soft Reset 1. Reset the SPI registers (self clearing).

This bit must be accessed with all devices enabled.

SPI least significant bit first.

RW

1

SPI_LSB_FIRST1

±x±

RW

1 = least significant bit shifted first for all SPI operations. On multibyte SPI

operations, addressing increments automatically.

± = most significant bit shifted first for all SPI operations. On multibyte SPI

operations, addressing decrements automatically.

This bit must be accessed with all devices enabled and is not reset by

setting the SPI_SOFT_RESET1 or SPI_SOFT_RESET2 bit.

CHIP ID REGISTER

Address: 0x001, Reset: 0xB2, Name: CHIP_ID

Table 12. Bit Descriptions for CHIP_ID

Bits

Bit Name

Description

Reset

Access

[7:±]

CHIP_ID

Chip ID.

±xB2

R

Rev. A | Page 3± of 56

Data Sheet

AD9993

CHIP GRADE REGISTER

Address: 0x002, Reset: 0x01, Name: CHIP_GRADE

Table 13. Bit Descriptions for CHIP_GRADE

Bits

[5:4]

[2:±]

Bit Name

Description

Reset

±x±

±x1

Access

CHIP_SPEED_GRADE

CHIP_DIE_REV

Chip ID/speed grade.

Chip die revision.

R

DEVICE INDEX REGISTER

Address: 0x005, Reset: 0x0F, Name: DEVICE_INDEX

Table 14. Bit Descriptions for DEVICE_INDEX

Bits

Bit Name

Description

Reset

Access

3

SPI_ADC_D_INDEX

ADC Core D access enable.

±x1

RW

1 = ADC Core D receives the next read/write access from the SPI interface.

± = ADC Core D does not receive the next read/write access from the SPI

interface.

2

1

±

SPI_ADC_C_INDEX

SPI_ADC_B_INDEX

SPI_ADC_A_INDEX

ADC Core C access enable.

1 = ADC Core C receives the next read/write access from the SPI interface.

± = ADC Core C does not receive the next read/write access from the SPI

interface.

±x1

RW

ADC Core B access enable.

1 = ADC Core B receives the next read/write access from the SPI interface.

± = ADC Core B does not receive the next read/write access from the SPI

interface.

ADC Core A access enable.

1 = ADC Core A receives the next read/write access from the SPI interface.

± = ADC Core A does not receive the next read/write access from the SPI

interface.

Rev. A | Page 31 of 56

AD9993

Data Sheet

POWER MODE CONTROL REGISTER

Address: 0x008, Reset: 0x55, Name: POWER_MODES

Table 15. Bit Descriptions for POWER_MODES

Bits

Bit Name

Description

Reset

Access

7

PDWN_PIN_FUNC

Power-down pin function. External power-down pin mode.

±x±

RW

± = assertion of external power-down pin (PDWN) causes chip to enter full

power-down mode.

1 = assertion of external power-down pin (PDWN) causes chip to enter

standby mode.

6

CLKGEN_PDWN

Clock generation power-down mode.

Synthesizer power-down mode.

DAC power-down mode.

±x1

RW

[5:4]

[3:2]

[1:±]

SYNTH_PDWN_MODE

DAC_PDWN_MODE

ADC_PDWN_MODE

ADC power-down mode. (ADC indexed)

±± = normal mode (power up).

±1 = power-down mode; digital datapath clocks disabled; digital datapath

held in reset; outputs disabled.

1± = standby mode; digital datapath clocks disabled; outputs disabled.

11 = reserved.

ALIGN ADC LVDS CLOCKS, ADC FIFO, DAC FIFO REGISTER

Address: 0x00A, Reset: 0x80, Name: ALIGN

Table 16. Bit Descriptions for ALIGN

Bits

Bit Name

Description

Reset

Access

[7:5]

RXFIFO_WR_OFFSET

The distance of Rx FIFO write pointer away from read pointer; needs

RXFIFO_ALIGN_REQ asserted to apply this value to datapath.

±x4

RW

4

1

±

RXFIFO_ALIGN_REQ

LVDS_DCO_SYNC

TXFIFO_ALIGN

Align Rx FIFO read and write pointers.

Sync LVDS Tx DCO with data and strobe (self clear with following SPI clock). ±x±

Align Tx FIFO read and write pointers (self clear with following SPI clock).

±x±

RW

±x±

Rev. A | Page 32 of 56

Data Sheet

AD9993

STROBE LANE CONTROL REGISTER

Address: 0x012, Reset: 0x00, Name: STROBE_CTRL

Table 17. Bit Descriptions for STROBE_CTRL

Bits

Bit Name

Description

Reset

Access

[7:4]

STROBE_SAMPLE_RATE

Sample rate of strobe output.

± = 1/1 of data sample rate.

1 = 1/2 of data sample rate.

2 = 1/4 of data sample rate.

3 = 1/ꢀ of data sample rate.

4 = 1/16 of data sample rate.

5 = 1/32 of data sample rate.

6 = 1/64 of data sample rate.

7 = 1/12ꢀ of data sample rate.

ꢀ = 1/256 of data sample rate.

Needs at least one ADC channel working.

±x±

RW

±

STROBE_DUTY_CYCLE_EN

Enable 5±% duty cycle of strobe lane. Needs at least one ADC channel

working.

±x±

RW

OUTPUT MODE REGISTER

Address: 0x013, Reset: 0x11, Name: FLEX_OUTPUT_MODE

Table 18. Bit Descriptions for FLEX_OUTPUT_MODE

Bits

Bit Name

Description

Reset

Access

4

DP_OUT_DATA_EN_N

Digital datapath output enable (active low) (ADC indexed).

± = digital output from ADC is enabled.

1 = digital output from ADC is disabled.

Digital datapath output invert (ADC indexed).

± = output from ADC is not inverted.

1 = output from ADC is inverted.

Digital datapath output data format select (DFS) (ADC indexed).

±± = offset binary.

±x1

RW

2

DP_OUT_DATA_INV

DP_OUT_DFS

±x±

±x1

RW

[1:±]

±1 = twos complement.

1± = gray code.

11 = reserved.

Rev. A | Page 33 of 56

AD9993

Data Sheet

LVDS TX CONTROL REGISTER

Address: 0x014, Reset: 0x00, Name: FLEX_OUTPUT_ADJUST

Table 19. Bit Descriptions for FLEX_OUTPUT_ADJUST

Bits

Bit Name

Description

Reset

Access

[7:5]

LVDS_BIAS_DAC

Sets LVDS output swing.

±±± = 2±± mV.

±x±

RW

±±1 = 227 mV.

±1± = 257 mV.

±11 = 2ꢀ2 mV.

1±± = 296 mV.

1±1 = 33± mV.

11± = 35± mV.

111 = 372 mV.

[4:2]

[1:±]

LVDS_BG_TRIM

LVDS_DRIVE

Band gap trim for LVDS Tx DOUTxx_P and DOUTxx_N pins.

Output LVDS drive current.

±± = 1 mA output drive current (default).

±1 = 2 mA output drive current.

1± = 3 mA output drive current.

11 = 4 mA output drive current.

±x±

RW

V_REFCONTROL REGISTER

Address: 0x016, Reset: 0x00, Name: FLEX_VREF

Table 20. Bit Descriptions for FLEX_VREF

Bits

Bit Name

Description

Reset

Access

[4:±]

VREF_FS_ADJ

Main reference full-scale V_REFadjustment.

±1111 = internal 2.±ꢀ7 V p-p.

…

±x±

RW

±±±±1 = internal 1.772 V p-p.

±±±±± = internal 1.75 V p-p.

11111 = internal 1.727 V p-p.

…

1±±±± = internal 1.3ꢀ3 V p-p.

Rev. A | Page 34 of 56

Data Sheet

AD9993

PRBS GENERATOR CONTROL REGISTER

Address: 0x017, Reset: 0x00, Name: PRBS_GEN_CTRL

Table 21. Bit Descriptions for PRBS_GEN_CTRL

Bits

Bit Name

Description

Reset

Access

5

STROBE_PRBS_RESET

Reset PRBS generator on strobe lane (transfer not needed).

± = normal working if PRBS enabled.

1 = reset the PRBS on strobe lane.

Enable PRBS testing on strobe lane.

±x±

RW

4

STROBE_PRBS_EN

±x±

RW

± = normal mode working with STROBE_DUTY_CYCLE_EN and

STROBE_SAMPLE_RATE.

1 = test mode only.

Note: needs at least one ADC channel working.

1

±

DP_PRBS_GEN_RESET

DP_PRBS_GEN_EN

Pseudorandom binary sequence generator reset (transfer not needed,

ADC indexed).

± = PRBS generator enabled.

±x±

RW

1 = PRBS generator held in reset.

Enable PRBS generating on ADC data lanes (ADC indexed).

8-BIT SEED MSB OF PRBS GENERATOR FOR LANE 0 REGISTER

Address: 0x020, Reset: 0x01, Name: PRBS0_SEED_MSB

Table 22. Bit Descriptions for PRBS0_SEED_MSB

Bits

Bit Name

Description

Reset

Access

[7:±]

DP_PRBS±_SEED_MSB

ꢀ-bit MSB seed of PRBS generator in Lane ± (ADC indexed).

The 15-bit LSB is always ±x3AFF.

±x1

RW

Rev. A | Page 35 of 56

AD9993

Data Sheet

8-BIT SEED MSB OF PRBS GENERATOR FOR LANE 1 REGISTER

Address: 0x021, Reset: 0x02, Name: PRBS1_SEED_MSB

Table 23. Bit Descriptions for PRBS1_SEED_MSB

Bits

Bit Name

Description

Reset

Access

[7:±]

DP_PRBS1_SEED_MSB

ꢀ-bit MSB seed of PRBS generator in Lane 1 (ADC indexed.)

The 15-bit LSB is always ±x3AFF.

±x2

RW

8-BIT SEED MSB OF PRBS GENERATOR FOR LANE 2 REGISTER

Address: 0x022, Reset: 0x03, Name: PRBS2_SEED_MSB

Table 24. Bit Descriptions for PRBS2_SEED_MSB

Bits

Bit Name

Description

Reset

Access

[7:±]

DP_PRBS2_SEED_MSB

ꢀ-bit MSB seed of PRBS generator in Lane 2 (ADC indexed).

The 15-bit LSB is always ±x3AFF.

±x3

RW

8-BIT SEED MSB OF PRBS GENERATOR FOR LANE 3 REGISTER

Address: 0x023, Reset: 0x04, Name: PRBS3_SEED_MSB

Table 25. Bit Descriptions for PRBS3_SEED_MSB

Bits

Bit Name

Description

Reset

Access

[7:±]

DP_PRBS3_SEED_MSB

ꢀ-bit MSB seed of PRBS generator in Lane 3 (ADC indexed).

The 15-bit LSB is always ±x3AFF.

±x4

RW

Rev. A | Page 36 of 56

Data Sheet

AD9993

SYNTHESIZER STATUS REGISTER

Address: 0x02D, Reset: 0x00, Name: SYNTH_STAT

Table 26. Bit Descriptions for SYNTH_STAT

Bits

Bit Name

Description

Reset

±x±

Access

2

1

±

SYNTH_CP_CAL_DONE

SYNTH_LOCKDET

SYNTH_VCO_CAL_IN_PROGRESS VCO calibration in progress.

Charge pump calibration done.

Synthesizer frequency locked.

R

±x±

LOOP FILTER CONTROL SIGNALS REGISTER

Address: 0x02E, Reset: 0x77, Name: LF_CTRL1

Table 27. Bit Descriptions for LF_CTRL1

Bits

Bit Name

Description

Reset

±x7

Access

[6:4]

LF_C2

Loop filter coefficient.

±±± = 3.13 pF.

RW

±±1 = 2.26 pF.

±1± = 9.39 pF.

±11 = 12.52 pF.

1±± = 15.65 pF.

1±1 = 1ꢀ.7ꢀ pF.

11± = 21.91 pF.

111 = 25.±4 pF.

Loop filter coefficient.

±±± = 46.5ꢀ4 pF.

±±1 = 93.16ꢀ pF.

±1± = 139.752 pF.

±11 = 1ꢀ6.336 pF.

1±± = 232.92± pF.

1±1 = 279.5±4 pF.

11± = 326.±ꢀꢀ pF.

111 = 372.672 pF.

[2:±]

LF_C1

±x7

RW

Rev. A | Page 37 of 56

AD9993

Data Sheet

LOOP FILTER CONTROL SIGNALS REGISTER

Address: 0x02F, Reset: 0xF7, Name: LF_CTRL2

Table 28. Bit Descriptions for LF_CTRL2

Bits

Bit Name

Description

Reset

Access

[7:6]

LF_R3

Loop filter coefficient.

±± = 4.63 kΩ.

±1 = 2.315 kΩ.

1± = 1.543 kΩ.

11 = 1.157 kΩ

±x3

±x7

RW

[5:4]

[2:±]

LF_R1

LF_C3

Loop filter coefficient.

±± = 12.±4 kΩ.

±1 = 6.±2 kΩ.

1± = 4.±1 kΩ.

11 = 3.±1 kΩ.

RW

Loop filter coefficient.

±±± = ±.6325 pF.

±±1 = 1.265 pF.

±1± = 1.ꢀ975 pF.

±11 = 2.53± pF.

1±± = 3.1625 pF.

1±1 = 3.795 pF.

11± = 4.4275 pF.

111 = 5.±6 pF.

LOOP FILTER CONTROL SIGNALS REGISTER

Address: 0x030, Reset: 0x00, Name: LF_CTRL3

Table 29. Bit Descriptions for LF_CTRL3

Bits

Bit Name

EXT_CP_SEL

BYP_R3

Description

Reset

±x±

Access

RW

1

±

Short external CP pin to charge pump output.

Bypass R3 in loop filter.

Rev. A | Page 3ꢀ of 56

Data Sheet

AD9993

INTEGER VALUE OF SYNTHESIZER DIVIDER REGISTER

Address: 0x031, Reset: 0x40, Name: SYNTH_INT

Table 30. Bit Descriptions for SYNTH_INT

Bits

Bit Name

Description

Reset

Access

[7:±]

SYNTH_INT

Integer part on the synthesizer divider (N). N = freq (MHz)/31.25.

±x4±

RW

SYNTHESIZER CONTROL REGISTER

Address: 0x032, Reset: 0x00, Name: SYNTH_CTRL

Table 31. Bit Descriptions for SYNTH_CTRL

Bits

Bit Name

Description

Reset

±x±

Access

RW

4

±

SYNTH_CAL_START

SYNTH_CP_CAL_EN

Start synthesizer calibration.

Enable charge pump calibration.

CLOCK GENERATOR CONTROL REGISTER

Address: 0x033, Reset: 0x00, Name: CLKGEN_CTRL1

Table 32. Bit Descriptions for CLKGEN_CTRL1

Bits

Bit Name

Description

Reset

Access

7

CLKGEN_DC_MODE

DAC clock direct connect to ADC.

± = ADC clock from 1 GHz.

±x±

RW

1 = ADC clock from DAC.

6

5

CLKGEN_DC_MODE_INV

CLKGEN_REFCLK_DIV1

Not used.

±x±

RW

± = select REFCLK as PLL reference.

1 = select REFCLK/2 as PLL reference.

Selects the output of the on-chip reference clock divider to the PLL.

Sets the divider ratio for the on-chip reference clock divider.

Rev. A | Page 39 of 56

4

CLKGEN_REFDIV_EN

CLKGEN_REFDIV_SEL

±x±

RW

[1:±]

AD9993

Data Sheet

CLKGEN CONTROL REGISTER

Address: 0x034, Reset: 0x04, Name: CLKGEN_CTRL2

Table 33. Bit Descriptions for CLKGEN_CTRL2

Bits

Bit Name

Description

Reset

Access

3

CLKGEN_DAC_M±_INV

Swaps CMOS and differential clock buffer for DAC only.

± = normal mode.

1 = inverts CLKGEN_MODE[±] for DAC only.

Swaps CMOS and differential clock buffer for ADC only.

± = normal mode.

±x±

±x1

±x±

RW

2

CLKGEN_ADC_M±_INV

CLKGEN_MODE

RW

1 = inverts CLKGEN_MODE[±] for ADC only.

Configures the IC for external or internal clock.

[1:±]

±± = selects on-chip synthesizer to drive LVDS at 1 GHz, ADC at 25± MHz,

and DAC at 5±± MHz.

±1 = same as ±± except uses differential clock buffer for DAC and ADC.

1± = selects external clock source to drive LVDS at clock rate, ADC at clock

rate divide by 4, and DAC at clock rate divide by 2. Minimum clock rate =

2±± MHz.

11 = same as 1± except uses differential clock buffer for DAC and ADC.

DAC LVDS RX CONTROL REGISTER

Address: 0x035, Reset: 0x4D, Name: DAC_LVDS_CTRL

Rev. A | Page 4± of 56

Data Sheet

AD9993

Table 34. Bit Descriptions for DAC_LVDS_CTRL

Bits

Bit Name

Description

Reset

Access

[3:±]

DAC_RES_CAL

DAC LVDS Rx termination selection.

±±±1 = 977 Ω.

±±1± = 497 Ω.

±±11 = 341 Ω.

±1±± = 267 Ω.

±1±1 = 215 Ω.

±11± = 1ꢀ4 Ω.

±111 = 16± Ω.

1±±± = 145Ω.

1±±1 = 131 Ω.

1±1± = 121 Ω.

1±11 = 112 .

±xD

RW

11±± = 1±5 Ω.

11±1 = 99 Ω.

111± = 93Ω.

1111 = ꢀ9 Ω.

DAC LVDS CURRENT BIAS CONTROL REGISTER

Address: 0x036, Reset: 0x00, Name: DAC_LVDS_BIAS

Table 35. Bit Descriptions for DAC_LVDS_BIAS

Bits

Bit Name

Description

Reset

Access

[5:4]

DAC_IAMP

Adjust bias current for LVDS DAC receiver.

±x±

RW

±± = nominal.

±1 = 25%.

1± = 5±%.

11 = 75%.

[1:±]

DAC_IRCV

Adjust the bias current to cascade voltage for LVDS DAC receiver.

±x±

RW

±± = nominal.

±1 = 25%.

1± = 5±%.

11 = 75%.

Rev. A | Page 41 of 56

AD9993

Data Sheet

DAC CORES CONTROL REGISTER

Address: 0x039, Reset: 0x02, Name: DAC_CTRL

Table 36. Bit Descriptions for DAC_CTRL

Bits

Bit Name

Description

Reset

Access

7

DAC_TRANS

DAC input latch data transfer method select.

± = edge triggered.

1 = level triggered.

Sets DAC common-mode level.

±±± = ±.± V.

±x±

RW

[6:4]

DAC_VCM_VREF_BIT

±x±

RW

±±1 = ±.2 V.

±1± = ±.3 V.

±11 = ±.4 V

1±± = ±.5 V

1±1 = ±.6 V

11± = ±.7 V.

111 = ±.ꢀ V.

1

±

DAC_RSET_EN

DAC_REF_EXT

Selects on-chip R_{FSADJ_x}resistor.

±x1

±x±

RW

Selects external DAC Reference voltage. Set to 1 to use an off-chip DAC

reference.

DAC DATAPATH FORMAT CONTROL REGISTER

Address: 0x03A, Reset: 0x00, Name: DAC_DP_FMT

Table 37. Bit Descriptions for DAC_DP_FMT

Bits

Bit Name

Description

Reset

Access

1

DAC_BINARY

Enable binary offset data format (default is twos complement).

± = twos complement.

±x±

RW

1 = binary offset.

Rev. A | Page 42 of 56

Data Sheet

AD9993

DAC IQ CALIBRATION CONTROL REGISTER

Address: 0x03C, Reset: 0x04, Name: DAC_CAL_IQ_CTRL

Table 38. Bit Descriptions for DAC_CAL_IQ_CTRL

Bits

Bit Name

Description

Reset

±x±

Access

RW

5

DAC_CAL_IQ_START

DAC_CAL_IQ_RESET

PD_DAC_CAL_CLK

Starts DAC IQ calibration.

4

Resets DAC IQ calibration.

±x±

RW

2

± = DAC IQ calibration clock enabled. Must be ± to run IQ calibration.

1 = DAC IQ calibration clock disabled.

±x1

RW

1

±

DAC_CAL_IQ_SEL

DAC_CAL_IQ_EN

Selects output of IQ calibration. Must be 1 to run IQ calibration.

Enables DAC I to Q calibration. Must stay high until DAC_CAL_IQ_DONE = 1.

±x±

RW

DAC IQ CALIBRATION STATUS REGISTER

Address: 0x03D, Reset: 0x00, Name: DAC_CAL_IQ_STAT

Table 39. Bit Descriptions for DAC_CAL_IQ_STAT

Bits

[7:1]

±

Bit Name

Description

Reset

Access

DAC_CAL_IQ_RD

DAC_CAL_IQ_DONE

Value of DAC IQ calibration, valid when DAC_CAL_IQ_DONE = 1.

Indicates when DAC IQ calibration is done.

±x±

R

DAC RX FIFO STATUS 1 REGISTER

Address: 0x03F, Reset: 0x55, Name: DAC_FIFO_STS1

Table 40. Bit Descriptions for DAC_FIFO_STS1

Bits

Bit Name

Description

Reset

Access

[7:±]

RXFIFO_THERM

Thermal value of FIFO usage.

±x55

R

Rev. A | Page 43 of 56

AD9993

Data Sheet

PRBS DETECTOR CONTROL REGISTER

Address: 0x040, Reset: 0x00, Name: DAC_PRBS_CTRL

Table 41. Bit Descriptions for DAC_PRBS_CTRL

Bits

Bit Name

Description

Reset

Access

RW

1

PRBS_DET_ERRCLR

PRBS_DET_EN

Clear the error count of PRBS detector (transfer not required).

Enable the PRBS detector.

±x±

±

RW

PRBS DETECTOR ERROR COUNT 0 FOR DAC A REGISTER

Address: 0x041, Reset: 0x00, Name: DAC_A_PRBS_ERR0

Table 42. Bit Descriptions for DAC_A_PRBS_ERR0

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_A±

Error count of Lane ± of DAC A.

±x±

R

PRBS DETECTOR ERROR COUNT 1 FOR DAC A REGISTER

Address: 0x042, Reset: 0x00, Name: DAC_A_PRBS_ERR1

Table 43. Bit Descriptions for DAC_A_PRBS_ERR1

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_A1

Error count of Lane 1 of DAC A.

±x±

R

Rev. A | Page 44 of 56

Data Sheet

AD9993

PRBS DETECTOR ERROR COUNT 2 FOR DAC A REGISTER

Address: 0x043, Reset: 0x00, Name: DAC_A_PRBS_ERR2

Table 44. Bit Descriptions for DAC_A_PRBS_ERR2

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_A2

Error count of Lane 2 of DAC A.

±x±

R

PRBS DETECTOR ERROR COUNT 3 FOR DAC A REGISTER

Address: 0x044, Reset: 0x00, Name: DAC_A_PRBS_ERR3

Table 45. Bit Descriptions for DAC_A_PRBS_ERR3

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_A3

Error count of Lane 3 of DAC A.

±x±

R

PRBS DETECTOR ERROR COUNT 4 FOR DAC A REGISTER

Address: 0x045, Reset: 0x00, Name: DAC_A_PRBS_ERR4

Table 46. Bit Descriptions for DAC_A_PRBS_ERR4

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_A4

Error count of Lane 4 of DAC A.

±x±

R

Rev. A | Page 45 of 56

AD9993

Data Sheet

PRBS DETECTOR ERROR COUNT 5 FOR DAC A REGISTER

Address: 0x046, Reset: 0x00, Name: DAC_A_PRBS_ERR5

Table 47. Bit Descriptions for DAC_A_PRBS_ERR5

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_A5

Error count of Lane 5 of DAC A.

±x±

R

PRBS DETECTOR ERROR COUNT 6 FOR DAC A REGISTER

Address: 0x047, Reset: 0x00, Name: DAC_A_PRBS_ERR6

Table 48. Bit Descriptions for DAC_A_PRBS_ERR6

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_A6

Error count of Lane 6 of DAC A.

±x±

R

PRBS DETECTOR ERROR COUNT 0 FOR DAC B REGISTER

Address: 0x048, Reset: 0x00, Name: DAC_B_PRBS_ERR0

Table 49. Bit Descriptions for DAC_B_PRBS_ERR0

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_B±

Error count of Lane ± of DAC B.

±x±

R

Rev. A | Page 46 of 56

Data Sheet

AD9993

PRBS DETECTOR ERROR COUNT 1 FOR DAC B REGISTER

Address: 0x049, Reset: 0x00, Name: DAC_B_PRBS_ERR1

Table 50. Bit Descriptions for DAC_B_PRBS_ERR1

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_B1

Error count of Lane 1 of DAC B.

±x±

R

PRBS DETECTOR ERROR COUNT 2 FOR DAC B REGISTER

Address: 0x04A, Reset: 0x00, Name: DAC_B_PRBS_ERR2

Table 51. Bit Descriptions for DAC_B_PRBS_ERR2

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_B2

Error count of Lane 2 of DAC B.

±x±

R

PRBS DETECTOR ERROR COUNT 3 FOR DAC B REGISTER

Address: 0x04B, Reset: 0x00, Name: DAC_B_PRBS_ERR3

Table 52. Bit Descriptions for DAC_B_PRBS_ERR3

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_B3

Error count of Lane 3 of DAC B.

±x±

R

Rev. A | Page 47 of 56

AD9993

Data Sheet

PRBS DETECTOR ERROR COUNT 4 FOR DAC B REGISTER

Address: 0x04C, Reset: 0x00, Name: DAC_B_PRBS_ERR4

Table 53. Bit Descriptions for DAC_B_PRBS_ERR4

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_B4

Error count of Lane 4 of DAC B.

±x±

R

PRBS DETECTOR ERROR COUNT 5 FOR DAC B REGISTER

Address: 0x04D, Reset: 0x00, Name: DAC_B_PRBS_ERR5

Table 54. Bit Descriptions for DAC_B_PRBS_ERR5

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_B5

Error count of Lane 5 of DAC B.

±x±

R

PRBS DETECTOR ERROR COUNT 6 FOR DAC B REGISTER

Address: 0x04E, Reset: 0x00, Name: DAC_B_PRBS_ERR6

Table 55. Bit Descriptions for DAC_B_PRBS_ERR6

Bits

Bit Name

Description

Reset

Access

[7:±]

PRBS_DET_ERRCNT_B6

Error count of Lane 6 of DAC B.

±x±

R

Rev. A | Page 4ꢀ of 56

Data Sheet

AD9993

BITS[7:0] OF TEMPERATURE SENSOR DATA READBACK REGISTER

Address: 0x050, Reset: 0x00, Name: TS_RD_LSB

Table 56. Bit Descriptions for TS_RD_LSB

Bits

Bit Name

Description

Reset

Access

[7:±]

TEMP_SENSE_RDBK_LSB

Temperature sensor measurement MSB.

±x±

R

BITS[15:8] OF TEMPERATURE SENSOR DATA READBACK REGISTER

Address: 0x051, Reset: 0x00, Name: TS_RD_MSB

Table 57. Bit Descriptions for TS_RD_MSB

Bits

Bit Name

Description

Reset

Access

[7:±]

TEMP_SENSE_RDBK_MSB

Temperature sensor neasurement LSB.

±x±

R

TEMPERATURE SENSOR CONTROL SIGNALS REGISTER

Address: 0x054, Reset: 0x01, Name: TS_CTRL

Table 58. Bit Descriptions for TS_CTRL

Bits

Bit Name

Description

Reset

Access

±

TEMP_SENSE_PD

Turn off temperature sensor.

±x1

RW

Rev. A | Page 49 of 56

AD9993

Data Sheet

INTERRUPT PIN CONTROL REGISTER

Address: 0x055, Reset: 0x00, Name: IRQ_CTRL

Table 59. Bit Descriptions for IRQ_CTRL

Bits

Bit Name

Description

Reset

Access

±

ALERT_PULLUP_EN

Interrupt (alarm) pin pull-up enable.

±x±

RW

DDS CONTROL REGISTER

Address: 0x060, Reset: 0x00, Name: DDS_CTRL

Table 60. Bit Descriptions for DDS_CTRL

Bits

Bit Name

Description

Reset

±x±

Access

RW

6

DDS_1DB_DIS

DDS_ATTEN

Disable the −1 db attenuation on both DDS tone outputs.

Amplitude attenuation.

±± = ×1/1 amplitude.

[3:2]

±x±

RW

±1 = ×1/2 amplitude.

1± = ×1/4 amplitude.

11 = ×1/ꢀ amplitude.

1

±

DDS_CLK_INV

DDS_EN

DDS clock invert bit.

± = normal. DDS clock not inverted.

1 = DDS clock inverted.

±x±

RW

Enable DDS Tone 1 output.

Rev. A | Page 5± of 56

Data Sheet

AD9993

DDS TUNING WORD FOR TONE 1 REGISTER

Address: 0x061, Reset: 0x00, Name: DDS_TW1_0

Table 61. Bit Descriptions for DDS_TW1_0

Bits

Bit Name

Description

Reset

Access

[7:±]

DDS_TW1_±

32-bit tuning word for Tone 1 combined by DDS_TW1_3, DDS_TW1_2,

DDS_TW1_1, and DDS_TW1_±. The default configuration is for 5± MHz

when working with 5±± MHz DAC clock.

±x±

RW

DDS TUNING WORD FOR TONE 1 REGISTER

Address: 0x062, Reset: 0x00, Name: DDS_TW1_1

Table 62. Bit Descriptions for DDS_TW1_1

Bits

Bit Name

Description

Reset

Access

[7:±]

DDS_TW1_1

32-bit tuning word for Tone 1 combined by DDS_TW1_3, DDS_TW1_2,

DDS_TW1_1, and DDS_TW1_±. The default configuration is for 5± MHz

when working with 5±± MHz DAC clock.

±x±

RW

Rev. A | Page 51 of 56

AD9993

Data Sheet

DDS TUNING WORD FOR TONE 1 REGISTER

Address: 0x063, Reset: 0xA0, Name: DDS_TW1_2

Table 63. Bit Descriptions for DDS_TW1_2

Bits

Bit Name

Description

Reset

Access

[7:±]

DDS_TW1_2

32-bit tuning word for Tone 1 combined by DDS_TW1_3, DDS_TW1_2,

DDS_TW1_1, and DDS_TW1_±. The default configuration is for 5± MHz

when working with 5±± MHz DAC clock.

±xa±

RW

DDS TUNING WORD FOR TONE 1 REGISTER

Address: 0x064, Reset: 0x19, Name: DDS_TW1_3

Table 64. Bit Descriptions for DDS_TW1_3

Bits

Bit Name

Description

Reset

Access

[7:±]

DDS_TW1_3

32-bit tuning word for Tone 1 combined by DDS_TW1_3, DDS_TW1_2,

DDS_TW1_1, and DDS_TW1_±. The default configuration is for 5± MHz

when working with 5±± MHz DAC clock.

±x19

RW

Rev. A | Page 52 of 56

Data Sheet

AD9993

INTERRUPT STATUS REGISTER

Address: 0x0F0, Reset: 0x00, Name: INT

Table 65. Bit Descriptions for INT

Bits

Bit Name

Description

Reset

±x±

Access

RW1C

7

6

5

4

3

2

1

±

ADC_D_OVR_IRQ

ADC_C_OVR_IRQ

ADC_B_OVR_IRQ

ADC_A_OVR_IRQ

FIFO_WARN2_IRQ

FIFO_WARN1_IRQ

PLL_UNLOCK_IRQ

PLL_LOCKED_IRQ

ADC D overrange interrupt (write 1 to clear).

ADC C overrange interrupt (write 1 to clear).

ADC B overrange interrupt(write 1 to clear).

ADC A overrange interrupt (write 1 to clear).

FIFO Warning 2 interrupt (write 1 to clear).

FIFO Warning 1 interrupt (write 1 to clear).

PLL unlock interrupt (write 1 to clear).

PLL lock interrupt (write 1 to clear).

INTERRUPT ENABLE REGISTER

Address: 0x0F1, Reset: 0x00, Name: INTEN

Rev. A | Page 53 of 56

AD9993

Data Sheet

Table 66. Bit Descriptions for INTEN

Bits

Bit Name

Description

Reset

Access

RW

7

6

5

ADC_D_OVR_IRQ_EN

ADC_C_OVR_IRQ_EN

ADC_B_OVR_IRQ_EN

ADC_A_OVR_IRQ_EN

FIFO_WARN2_IRQ_EN

FIFO_WARN1_IRQ_EN

PLL_UNLOCK_IRQ_EN

PLL_LOCKED_IRQ_EN

Enable ADC D Overrange interrupt.

Enable ADC C Overrange interrupt.

Enable ADC B Overrange interrupt.

Enable ADC A Overrange interrupt.

Enable FIFO Warning 2 interrupt.

Enable FIFO Warning 1 interrupt.

Enable PLL unlock interrupt.

Enable PLL lock interrupt.

±x±

RW

4

3

2

1

RW

±

RW

INTERRUPT SOURCE STATUS REGISTER

Address: 0x0F2, Reset: 0x00, Name: INT_RAW

Table 67. Bit Descriptions for INT_RAW

Bits

Bit Name

Description

Reset

±x±

Access

7

6

5

4

3

2

1

±

ADC_D_OVR_RAW

ADC_C_OVR_RAW

ADC_B_OVR_RAW

ADC_A_OVR_RAW

FIFO_WARN2_RAW

FIFO_WARN1_RAW

PLL_UNLOCK_RAW

PLL_LOCKED_RAW

ADC D overrange interrupt source.

ADC C overrange interrupt source.

ADC B overrange interrupt source.

ADC A overrange interrupt source.

FIFO Warning 2 interrupt source.

FIFO Warning 1 interrupt source.

PLL unlock interrupt source.

PLL lock interrupt source.

R

Rev. A | Page 54 of 56

Data Sheet

AD9993

GLOBAL DEVICE UPDATE REGISTER

Address: 0x0FF, Reset: 0x00, Name: DEVICE_UPDATE

Table 68. Bit Descriptions for DEVICE_UPDATE

Bits

Bit Name

Description

Reset

Access

±

CHIP_REGMAP_TRANSFER

Register map master/slave transfer bit. Self clearing bit used to

±x±

RW

synchronize the transfer of data from the master to the slave registers.

± = no effect

1 = transfer data from the master registers written by the register maps

to the slave registers seen by the datapath.

Rev. A | Page 55 of 56

AD9993

Data Sheet

OUTLINE DIMENSIONS

12.10

12.00 SQ

11.90

A1 BALL

CORNER

A1 BALL

CORNER

14 13 12 11 10 9

8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

10.40

BSC SQ

0.80

BSC

K

L

M

N

P

0.80

REF

TOP VIEW

DETAIL A

BOTTOM VIEW

*

1.40

1.24

1.15

0.97

0.90

0.83

0.54

REF

DETAIL A

0.39

0.34

0.29

0.36

REF

0.50

0.45

0.40

COPLANARITY

0.12

SEATING

PLANE

BALL DIAMETER

*

COMPLIANT TO JEDEC STANDARDS MO-219 WITH

EXCEPTION TO PACKAGE HEIGHT.

Figure 33. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-196-9)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

AD9993BBCZ

AD9993BBCZRL

AD9993-EBZ

Temperature Range

−4±°C to +ꢀ5°C

Package Description

Package Option

BC-196-9

196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Evaluation Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D12260-0-5/14(A)

Rev. A | Page 56 of 56


型号：	AD9993-EBZ
厂家：	ADI
描述：	Integrated Mixed-Signal Front End
文件：	总57页 (文件大小：2436K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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