ADA4075-2 [ADI]
Ultralow Noise Amplifier at Lower Power; 超低噪声放大器的低功耗
| 型号： | ADA4075-2 |
| 厂家： | 
ADI |
| 描述： | Ultralow Noise Amplifier at Lower Power |
| 文件： | 总24页 (文件大小：861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Noise Amplifier at Lower Power
ADA4075-2
PIN CONFIGURATION
FEATURES
Ultralow noise: 2.8 nV/√Hz at 1 kHz typical
Ultralow distortion: 0.0002% typical
Low supply current: 1.8 mA per amplifier typical
Offset voltage: 1 mV maximum
Bandwidth: 6.5 MHz typical
OUTA
–INA
+INA
V–
1
2
3
4
8
7
6
5
V+
ADA4075-2
TOP VIEW
(Not to Scale)
OUTB
–INB
+INB
Figure 1. 8-Lead SOIC
Slew rate: 12 V/μs typical
Unity-gain stable
Extended industrial temperature range
SOIC package
APPLICATIONS
Precision instrumentation
Professional audio
Active filters
Low noise amplifier front end
Integrators
GENERAL DESCRIPTION
Table 1. Low Noise Precision Op Amps
The ADA4075-2 is a dual, high performance, low noise operational
amplifier combining excellent dc and ac characteristics on the
Analog Devices, Inc., iPolar® process. The iPolar process is an
advanced bipolar technology implementing vertical junction
isolation with lateral trench isolation. This allows for low noise
performance amplifiers in smaller die size at faster speed and
lower power. Its high slew rate, low distortion, and ultralow
noise make the ADA4075-2 ideal for high fidelity audio and
high performance instrumentation applications. It is also
especially useful for lower power demands, small enclosures,
and high density applications. The ADA4075-2 is specified for
the temperature range of −40°C to +125°C and is available in a
standard SOIC package.
Supply 44 V
36 V
12 V to 16 V
AD8665
OP162
5 V
Single
OP27
AD8671
AD8675
AD797
AD8605
AD8655
AD8691
AD8606
AD8656
AD8692
AD8608
AD8694
Dual
OP275
AD8672
AD8676
AD8599
ADA4004-4
AD8674
AD8666
OP262
Quad
AD8668
OP462
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADA4075-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information.............................................................. 15
Input Protection ......................................................................... 15
Total Harmonic Distortion ....................................................... 15
Phase Reversal ............................................................................ 15
DAC Output Filter...................................................................... 16
Balanced Line Driver................................................................. 17
Balanced Line Receiver.............................................................. 18
Low Noise Parametric Equalizer.............................................. 19
Schematic......................................................................................... 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
Power Sequencing ........................................................................ 4
ESD Caution.................................................................................. 4
Typical Performance Characteristics ............................................. 5
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADA4075-2
SPECIFICATIONS
VSY
= 15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol Conditions
Min
Typ
0.2
30
5
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
1
mV
mV
nA
nA
nA
nA
V
dB
dB
dB
dB
dB
dB
μV/°C
MΩ
pF
−40°C ≤ TA ≤ +125°C
1.2
100
150
50
75
+12.5
Input Bias Current
IB
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
−12.5
110
106
114
108
112
106
CMRR
AVO
VCM = −12.5 V to +12.5 V
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ, VO = −11 V to +11 V
−40°C ≤ TA ≤ +125°C
118
117
117
Large-Signal Voltage Gain
RL = 600 Ω, VO = −10 V to +10 V
−40°C ≤ TA ≤ +125°C
∆VOS/∆T −40°C ≤ TA ≤ +125°C
RIN
Offset Voltage Drift
Input Resistance
Input Capacitance, Differential Mode CINDM
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
0.3
40
2.4
2.1
CINCM
VOH
pF
RL = 2 kΩ to GND
12.8
12.5
12.4
12
15.4
15
13
V
V
V
V
V
V
V
V
−40°C ≤ TA ≤ +125°C
RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
12.8
15.8
−14
VSY
=
18 V, RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to GND
Output Voltage Low
VOL
−13.6
−13
−13
−12.5
−16
−40°C ≤ TA ≤ +125°C
RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
−13.6
−16.6
V
V
V
VSY
=
18 V, RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
−15.5
V
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ISC
ZOUT
40
0.3
mA
Ω
f = 100 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY
−40°C ≤ TA ≤ +125°C
VSY 4.5 V to 18 V, IO = 0 mA
=
4.5 V to 18 V
106
100
110
1.8
dB
dB
mA
mA
Supply Current per Amplifier
=
2.25
3.35
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
SR
tS
GBP
ΦM
RL = 2 kΩ, AV = 1
12
3
6.5
60
V/μs
μs
MHz
Degrees
To 0.01%, VIN = 10 V step, RL = 1 kΩ
RL = 1 MΩ, CL = 35 pF, AV = 1
RL = 1 MΩ, CL = 35 pF, AV = 1
THD + NOISE
Total Harmonic Distortion and Noise THD + N RL = 2 kΩ, AV = 1, VIN = 3V rms, f = 20 Hz to 20 kHz
NOISE PERFORMANCE
0.0002
%
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
60
2.8
1.2
nV p-p
nV/√Hz
pA/√Hz
Rev. 0 | Page 3 of 24
ADA4075-2
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. This
was measured using a standard 2-layer board.
Parameter
Rating
Supply Voltage
Input Voltage
Input Current1
Differential Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
20 V
VSY
10 mA
1 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
Table 3. Thermal Resistance
Package Type
θJA
θJC
Unit
8-Lead SOIC
158
43
°C/W
POWER SEQUENCING
The op amp supplies must be established simultaneously with,
or before, any input signals are applied. If this is not possible,
the input current must be limited to 10 mA.
Lead Temperature (Soldering, 60 sec) 300°C
1 The input pins have clamp diodes to the power supply pins.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 4 of 24
ADA4075-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
250
200
150
100
50
250
V
V
= ±5V
= 0V
V
V
= ±15V
= 0V
SY
CM
SY
CM
200
150
100
50
0
–1.0
0
–1.0
–0.5
0
0.5
1.0
–0.5
0
0.5
1.0
V
(mV)
V
(mV)
OS
OS
Figure 2. Input Offset Voltage Distribution
Figure 5. Input Offset Voltage Distribution
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
V
= ±5V
V
= ±15V
SY
–40°C ≤ T ≤ +125°C
SY
–40°C ≤ T ≤ +125°C
A
A
–2.0 –1.6 –1.2 –0.8 –0.4
0
0.4
0.8
1.2
1.6
2.0
–2.0 –1.6 –1.2 –0.8 –0.4
0
0.4
0.8
1.2
1.6
2.0
TCV (μV/°C)
TCV (μV/°C)
OS
OS
Figure 6. Input Offset Voltage Drift Distribution
Figure 3. Input Offset Voltage Drift Distribution
300
200
100
0
300
200
100
0
V
= ±15V
V
= ±5V
SY
SY
–100
–200
–300
–100
–200
–300
–15
–10
–5
0
5
10
15
–5
–4
–3
–2
–1
0
1
2
3
4
5
V
(V)
V
(V)
CM
CM
Figure 4. Input Offset Voltage vs. Common-Mode Voltage
Figure 7. Input Offset Voltage vs. Common-Mode Voltage
Rev. 0 | Page 5 of 24
ADA4075-2
80
100
80
60
40
20
0
V
= ±15V
V
= ±5V
SY
SY
60
40
20
0
–40 –25 –10
5
20
35
50
65
80
95 110 125
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. Input Bias Current vs. Temperature
Figure 11. Input Bias Current vs. Temperature
60
50
40
30
20
10
0
60
50
40
30
20
10
0
V
= ±15V
V
= ±5V
SY
SY
–15
–10
–5
0
5
10
15
–4
–3
–2
–1
0
1
2
3
4
V
(V)
V
(V)
CM
CM
Figure 9. Input Bias Current vs. Input Common-Mode Voltage
Figure 12. Input Bias Current vs. Input Common-Mode Voltage
10
10
V
= ±15V
V
= ±5V
SY
SY
V
– V
– V
V
– V
OH
CC
OH
CC
1
1
V
– V
EE
V
OL
OL
EE
0.1
0.001
0.1
0.001
0.01
0.1
1
10
100
0.01
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 10. Output Voltage to Supply Rail vs. Load Current
Figure 13. Output Voltage to Supply Rail vs. Load Current
Rev. 0 | Page 6 of 24
ADA4075-2
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
V
= ±15V
V
= ±5V
SY
L
SY
L
V
– V
OH
CC
R
= 2kΩ
R
= 2kΩ
V
– V
OH
CC
V
– V
EE
OL
V
– V
EE
OL
–40 –25 –10
5
20
35
50
65
80
95 110 125
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. Output Voltage to Supply Rail vs. Temperature
Figure 17. Output Voltage to Supply Rail vs. Temperature
140
120
100
80
140
120
100
80
140
120
100
80
140
120
100
80
V
= ±15V
V
= ±5V
SY
SY
PHASE
PHASE
60
60
60
60
GAIN
40
40
40
40
20
20
20
20
GAIN
0
0
0
0
–20
–40
–60
–80
–100
–20
–40
–60
–80
–100
–20
–40
–60
–80
–100
–20
–40
–60
–80
–100
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. Open-Loop Gain and Phase vs. Frequency
Figure 18. Open-Loop Gain and Phase vs. Frequency
50
40
50
40
V
= ±15V
SY
V
= ±5V
SY
A
= +100
= +10
= +1
A
= +100
= +10
= +1
V
V
V
V
V
V
30
30
A
A
A
A
20
20
10
10
0
0
–10
–20
–30
–10
–20
–30
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16. Closed-Loop Gain vs. Frequency
Figure 19. Closed-Loop Gain vs. Frequency
Rev. 0 | Page 7 of 24
ADA4075-2
1k
1k
100
10
V
= ±15V
V
= ±5V
SY
SY
A
= +10
A
= +10
V
100
10
V
A
= +100
A
= +100
V
V
A
= +1
V
A
= +1
V
1
1
0.1
0.1
0.01
0.01
0.001
0.001
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20. Output Impedance vs. Frequency
Figure 23. Output Impedance vs. Frequency
140
120
100
80
140
120
100
80
V
= ±15V
V
= ±5V
SY
SY
60
60
40
40
20
20
0
100
0
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21. CMRR vs. Frequency
Figure 24. CMRR vs. Frequency
120
100
80
120
100
80
V
= ±15V
V
= ±5V
SY
SY
60
60
PSRR–
PSRR+
PSRR–
PSRR+
40
40
20
20
0
0
–20
10
–20
10
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. PSRR vs. Frequency
Figure 25. PSRR vs. Frequency
Rev. 0 | Page 8 of 24
ADA4075-2
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
V
A
R
= ±5V
= +1
V
A
R
= ±15V
= +1
SY
SY
V
L
V
L
= 2kΩ
= 2kΩ
0
10
0
10
100
1000
100
1000
CAPACITANCE (pF)
CAPACITANCE (pF)
Figure 26. Small-Signal Overshoot vs. Load Capacitance
Figure 29. Small-Signal Overshoot vs. Load Capacitance
V
V
A
R
C
= ±5V
= 7V p-p
= +1
V
V
A
R
C
= ±15V
= 20V p-p
= +1
SY
IN
SY
IN
V
L
L
V
L
L
= 2kΩ
= 2kΩ
= 100pF
= 100pF
0V
0V
TIME (4µs/DIV)
TIME (4µs/DIV)
Figure 30. Large-Signal Transient Response
Figure 27. Large-Signal Transient Response
V
V
A
R
C
= ±15V
= 100mV p-p
= +1
SY
IN
V
V
A
R
C
= ±5V
SY
IN
V
L
L
= 100mV p-p
= +1
V
L
L
= 2kΩ
= 2kΩ
= 100pF
= 100pF
0V
0V
TIME (10µs/DIV)
TIME (10µs/DIV)
Figure 31. Small-Signal Transient Response
Figure 28. Small-Signal Transient Response
Rev. 0 | Page 9 of 24
ADA4075-2
4
2
0
4
2
0
V
= ±5V
V
= ±15V
SY
SY
INPUT
INPUT
OUTPUT
OUTPUT
0
0
–2
–4
–6
–8
–5
–10
–15
–20
TIME (1µs/DIV)
TIME (1µs/DIV)
Figure 32. Negative Overload Recovery
Figure 35. Negative Overload Recovery
4
2
4
2
V
= ±5V
V
= ±15V
SY
SY
INPUT
INPUT
0
0
–2
–2
15
10
5
4
2
OUTPUT
OUTPUT
0
0
–2
–4
–5
–10
TIME (1µs/DIV)
TIME (1µs/DIV)
Figure 33. Positive Overload Recovery
Figure 36. Positive Overload Recovery
V
= ±5V
V
= ±15V
SY
SY
INPUT
INPUT
+6mV
+10mV
OUTPUT
OUTPUT
0V
0V
ERROR BAND
ERROR BAND
–10mV
–6mV
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 37. Positive Settling Time to 0.01%
Figure 34. Positive Settling Time to 0.01%
Rev. 0 | Page 10 of 24
ADA4075-2
V
= ±5V
V
= ±15V
SY
SY
INPUT
INPUT
+6mV
+10mV
0V
ERROR BAND
OUTPUT
OUTPUT
0V
ERROR BAND
–10mV
–6mV
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 41. Negative Settling Time to 0.01%
Figure 38. Negative Settling Time to 0.01%
10
10
V
= ±15V
V
= ±5V
SY
SY
1
1
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 39. Voltage Noise Density
Figure 42. Voltage Noise Density
10
10
R
V
= ±15V
V
= ±5V
R
S1
SY
SY
S1
R
R
S2
S2
UNCORRELATED
= 0
UNCORRELATED
= 0
R
R
S1
S1
1
1
CORRELATED
= R
CORRELATED
= R
R
R
S1
S2
S1
S2
0.1
0.1
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 43. Current Noise Density
Figure 40. Current Noise Density
Rev. 0 | Page 11 of 24
ADA4075-2
V
= ±15V
V
= ±5V
SY
SY
TIME (1s/DIV)
TIME (1s/DIV)
Figure 44. 0.1 Hz to 10 Hz Noise
Figure 47. 0.1 Hz to 10 Hz Noise
8
6
6
5
4
3
2
1
0
V
= ±15V
SY
+125°C
V
= ±5V
SY
+85°C
4
2
0
+25°C
–40°C
4
6
8
10
12
14
16
18
–40 –25 –10
5
20
35
50
65
80
95 110 125
SUPPLY VOLTAGE (±V)
TEMPERATURE (°C)
Figure 48. Supply Current vs. Temperature
Figure 45. Supply Current vs. Supply Voltage
0
–20
0
–20
V
V
R
= ±15V
= 10V p-p
= 2kΩ
V
V
R
= ±5V
= 5V p-p
= 2kΩ
SY
SY
IN
IN
L
L
–40
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
100
1k
10k
FREQUENCY (Hz)
100k
100
1k
10k
FREQUENCY (Hz)
100k
Figure 46. Channel Separation vs. Frequency
Figure 49. Channel Separation vs. Frequency
Rev. 0 | Page 12 of 24
ADA4075-2
10
1
10
1
V
= ±5V
V
= ±15V
SY
f = 1kHz
SY
f = 1kHz
0.1
0.1
0.01
0.01
0.001
0.0001
0.00001
0.001
0.0001
0.00001
600ꢀ
2kꢀ
600ꢀ
2kꢀ
0.0001
0.001
0.01
0.1
1
10
0.0001
0.001
0.01
0.1
1
10
AMPLITUDE (V rms)
AMPLITUDE (V rms)
Figure 50. THD + Noise vs. Amplitude
Figure 53. THD + Noise vs. Amplitude
1
0.1
1
0.1
V
V
= ±15V
= 3V rms
V
V
= ±5V
= 1.5V rms
SY
IN
SY
IN
0.01
0.01
600ꢀ
0.001
0.001
0.0001
600ꢀ
2kꢀ
2kꢀ
0.0001
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 54. THD + Noise vs. Frequency
Figure 51. THD + Noise vs. Frequency
10
1
1
V
V
= ±18V
= 8V rms
V
= ±18V
SY
IN
SY
f = 1kHz
0.1
0.01
0.1
0.01
0.001
0.001
0.0001
0.00001
600ꢀ
2kꢀ
600ꢀ
2kꢀ
0.0001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
10
100
1k
10k
100k
AMPLITUDE (V rms)
FREQUENCY (Hz)
Figure 52. THD + Noise vs. Amplitude
Figure 55. THD + Noise vs. Frequency
Rev. 0 | Page 13 of 24
ADA4075-2
10
2.5
2.0
1.5
1.0
0.5
V = ±18V
SY
V
= ±18V
SY
L
R
= 2kꢀ
V
– V
OH
CC
V
– V
OH
CC
1
V
– V
EE
OL
V
– V
EE
OL
0.1
0.001
0
0.01
0.1
1
10
100
–40 –25 –10
5
20
35
50
65
80
95 110 125
LOAD CURRENT (mA)
TEMPERATURE (°C)
Figure 56. Output Voltage to Supply Rail vs. Temperature
Figure 57. Output Voltage to Supply Rail vs. Load Current
Rev. 0 | Page 14 of 24
ADA4075-2
APPLICATIONS INFORMATION
1
0.1
INPUT PROTECTION
The maximum differential input voltage that can be applied to
the ADA4075-2 is determined by the internal diodes connected
across its inputs. These diodes limit the maximum differential
input voltage to 1 V and are needed to prevent base-emitter
junction breakdown from occurring in the input stage of the
ADA4075-2 when very large differential voltages are applied. To
make sure that the ultralow voltage noise feature of the ADA4075-2
is preserved, the commonly used internal resistors in series with
the inputs were not used to limit the current in the diodes.
V
R
= ±4V
= 2kꢀ
= 1.5V rms
SY
0.01
L
V
IN
V
R
= ±15V
= 2kꢀ
= 3V rms
SY
L
0.001
0.0001
V
IN
In small-signal applications, this is not an issue; however, in
applications where large differential voltages can be inadvertently
applied to the device, large currents may flow through these
diodes. If the differential voltage of the ADA4075-2 exceeds 1 V,
external resistors should be used at both inputs of the op amp to
limit the input currents to less than 10 mA (see Figure 58).
However, when series resistors are added, the total voltage noise
degrades because the resistors may have a thermal noise that is
greater than the voltage noise of the op amp itself. For example, a
1 kΩ resistor at room temperature has a thermal noise of 4 nV/√Hz,
whereas the ADA4075-2 has an ultralow voltage noise of only
2.8 nV/√Hz typical.
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 59. THD + Noise vs. Frequency
PHASE REVERSAL
Phase reversal occurs in some amplifiers when the input
common-mode voltage range is exceeded. When the voltage
driving the input to these amplifiers exceeds the maximum
input common-mode voltage range, the output of the amplifiers
changes polarity. Phase reversal can cause permanent damage to
the amplifier as well as system lockups in feedback loops.
The ADA4075-2 amplifiers have been carefully designed to prevent
output phase reversal when both inputs are maintained within
the specified input voltage range. If one or both inputs exceed
the input voltage range but remain within the supply rails, the
output is capped at the maximum output that it can swing to.
For a supply voltage of 15 V and a load resistance of 2 kΩ, the
output is capped at 13 V typical when the input voltage exceeds
the input voltage range but stays within the supply rails. Figure 60
shows the output voltage of the AD4075-2 configured as a unity-
gain buffer with a supply voltage of 15 V.
ADA4075-2
R1
R2
2
3
1
Figure 58. Input Protection
TOTAL HARMONIC DISTORTION
The total harmonic distortion + noise (THD + N) of the
ADA4075-2 is 0.0002% typical with a load resistance of 2 kΩ.
Figure 59 shows the performance of the ADA4075-2 driving a
2 kΩ load with supply voltages of 4 V and 15 V. Notice that
there is more distortion for the supply voltage of 4 V than for a
supply voltage of 15 V. Thus, it is very important to operate the
ADA4075-2 at a supply voltage greater than 5 V for optimum
distortion. The THD + noise graphs for supply voltages of 5 V
and 18 V are available in Figure 54 and Figure 55.
V
= ±15V
SY
V
IN
V
OUT
TIME (40µs/DIV)
Figure 60. No Phase Reversal
Rev. 0 | Page 15 of 24
ADA4075-2
on the output pins of the DAC. It also provides differential-to-
single-ended conversion from the differential outputs of the DAC.
DAC OUTPUT FILTER
The ultralow voltage noise, low distortion, and high slew rate of
the ADA4075-2 make it an ideal choice for professional audio
signal processing. Figure 61 shows the ADA4075-2 used in a
typical audio DAC output filter configuration. The differential
outputs of the DAC are fed into the ADA4075-2. The ADA4075-2
is configured as a differential Sallen-key filter. It operates as an
external low-pass filter to remove high frequency noise present
For a DAC output filter, an op amp with reasonable slew rate
and bandwidth is required. The slew rate of the ADA4075-2 is
at a high 12 V/μs, and the bandwidth is 6.5 MHz. The cutoff
frequency of the low-pass filter is approximately 167 kHz. In
addition, the 100 kΩ and 47 μF RC network perform ac coupling
to block out the dc components at the output.
11kꢀ
68pF
11kꢀ
3.01kꢀ
47µF
DAC OUTN
DAC OUTP
100ꢀ
1/2
OUTPUT
100kꢀ
5.62kꢀ
1.5kꢀ
270pF
2.2nF
ADA4075-2
560pF
150pF
5.62kꢀ
Figure 61. Typical DAC Output Filter Circuit (Differential)
Rev. 0 | Page 16 of 24
ADA4075-2
Finally, even with these precautions, it is vital that the positive
feedback be accurately controlled. This is partly achieved by
using 1% resistors. In addition, the following setup procedure
ensures that the positive feedback does not become excessive:
BALANCED LINE DRIVER
The circuit of Figure 62 shows a balanced line driver designed
for audio use. Such drivers are intended to mimic an output
transformer in operation, whereby the common-mode voltage
can be impressed by the load. Furthermore, either output can be
shorted to ground in single-ended applications without affecting
the overall operation.
1. Set R11 to its mid position (or short the ends together,
whichever is easier), and temporarily short the negative
output to ground.
2. Apply a 10 V p-p sine wave at approximately 1 kHz to the
input, and adjust R7 to provide 930 mV p-p at the point
marked “test.”
3. Remove the short from the negative output (and across
R11, if used), and adjust R11 until the output waveforms
are symmetric.
Circuits of this type use positive and negative feedback to obtain a
high common-mode output impedance, and they are somewhat
notorious for component sensitivity and susceptibility to latch-up.
This circuit uses several techniques to avoid spurious behavior.
First, the 4-op-amp arrangement ensures that the input impedance
is load independent (the input impedance can become negative
with some configurations). Note that the output op amps are
packaged with the input op amps to maximize drive capability.
The overall gain of the driver is equal to 2, which provides an
extra 6 dB of headroom in balanced differential mode. The
output noise is about −109 dBV in a 20 kHz bandwidth.
Second, the positive feedback is ac-coupled by C2 and C3, which
eliminates the need for offset trim. Because the circuit is ac-coupled
at the input, these capacitors do not have significant dc voltage
across them, thus tantalum types of capacitors can be used.
C5
IN
50pF
R5
C1
R4
10µF
A1
1/2
4.7kꢀ
4.7kꢀ
A2
R1
R13
10kꢀ
OUT+
1/2
100ꢀ
ADA4075-2
ADA4075-2
R7
250ꢀ
R6
R8
R9
R2
4.7kꢀ
4.7kꢀ
100ꢀ 4.7kꢀ
FEEDBACK
TRIM
C4
50pF
R3
SYMMETRY
TRIM
TEST
C3
10µF
C2
10µF
R10
R12
4.7kꢀ
C6
4.7kꢀ
4.7kꢀ
R11
250ꢀ
A3
1/2
50pF
A4
R14
ADA4075-2
OUT–
1/2
R15
100ꢀ
4.7kꢀ
ADA4075-2
R16
R17
4.7kꢀ
100ꢀ
NOTES
1. ALL RESISTORS SHOULD HAVE 1% TOLERANCE.
2. A1/A2 IN SAME PACKAGE; A3/A4 IN SAME PACKAGE.
Figure 62. Balanced Line Driver
Rev. 0 | Page 17 of 24
ADA4075-2
complementary output. A3 raises the common-mode input
impedance from about 7.5 kꢀ to about 70 kꢀ, reducing the
degradation of CMRR due to mismatches in source impedance.
It should be noted that A3 is not in the signal path, and almost any
op amp will work well here. Although it may seem as though the
inverting output should be noisier than the noninverting one,
they are in fact symmetric at about −111 dBV (20 kHz bandwidth).
BALANCED LINE RECEIVER
Figure 63 depicts a unity-gain balanced line receiver capable of
a high degree of hum rejection. The CMRR is approximately
given by
R1R4
R2R3
⎛
⎜
⎝
⎞
⎟
⎠
20 log10
Therefore, R1 to R4 should be close-tolerance components to
obtain the best possible CMRR without adjustment. The presence
of A2 ensures that the impedances are symmetric at the two inputs
(unlike many other designs), and, as a bonus, A2 also provides a
Sometimes an overall gain of ½ is desired to provide an extra
6 dB of differential input headroom. This can be attained by
reducing R3 and R4 to 5 kꢀ and increasing R9 to 22 kꢀ.
C2
50pF
R3
OUT+
C3
10kꢀ
50pF
R6
R1
5kꢀ
A1
IN–
IN+
R5
A2
5kꢀ
1/2
R2
5kꢀ
OUT–
1/2
5kꢀ
ADA4075-2
ADA4075-2
R7
5.6kꢀ
R8
5.6kꢀ
R4
10kꢀ
C1
22µF
A3*
(NON-POLAR)
R9
R10
11kꢀ
11kꢀ
*A3 REDUCES THE DEGRADATION OF CMRR
(SEE THE BALANCED LINE RECEIVER SECTION FOR MORE DETAILS).
Figure 63. Balanced Line Receiver
Rev. 0 | Page 18 of 24
ADA4075-2
48 Hz/Ct, where Ct is the value of C1 and C2 in microfarads.
The bandwidth control adjusts the Q from 0.9 to about 11. The
overall noise is setting dependent, but with all controls centered
it is about −104 dBV in a 20 kHz bandwidth. Such a low noise
level can obviate the need for a bypass switch in many applications.
LOW NOISE PARAMETRIC EQUALIZER
The circuit of Figure 64 is a reciprocal parametric equalizer
yielding 20 dB of cut or boost with variable bandwidth and
frequency. The frequency control range is 6.9:1, with the geometric
mean center frequency conveniently occurring at the midpoint
of the potentiometer setting. The center frequency is equal to
47µF
6.2kꢀ
6.2kꢀ
620ꢀ
IN
OUT
1/2
ADA4075-2
100ꢀ
BOOST
CUT
BANDWIDTH
1kꢀ
5kꢀ
2.7kꢀ
1.5kꢀ
ADA4075-2
C1*
C2*
1.5kꢀ
2.5kꢀ
1/2
1.3kꢀ
1.3kꢀ
2.5kꢀ
2.5kꢀ
620ꢀ
2.5kꢀ
1/2
1/2
ADA4075-2
ADA4075-2
620ꢀ
FREQUENCY (GANGED POTENTIOMETER)
*THE CENTER FREQUENCY IS AFFECTED BY THE VALUE OF C1 AND C2
(SEE THE LOW NOISE PARAMETRIC EQUALIZER SECTION FOR MORE DETAILS).
Figure 64. Low Noise Parametric Equalizer
Rev. 0 | Page 19 of 24
ADA4075-2
SCHEMATIC
V+
OUTA/
OUTB
–INA/
–INB
+INA/
+INB
V–
Figure 65. Simplified Schematic
Rev. 0 | Page 20 of 24
ADA4075-2
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 66. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
ADA4075-2ARZ1
ADA4075-2ARZ-R71
ADA4075-2ARZ-RL1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
R-8
R-8
R-8
1 Z = RoHS Compliant Part.
Rev. 0 | Page 21 of 24
ADA4075-2
NOTES
Rev. 0 | Page 22 of 24
ADA4075-2
NOTES
Rev. 0 | Page 23 of 24
ADA4075-2
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07642-0-10/08(0)
Rev. 0 | Page 24 of 24
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