ADA4411-3ARQZ-RL [ADI]
Integrated Triple Video Filter and Buffer with Selectable Cutoff Frequencies and Multiplexed Inputs for RGB, HD/SD; 集成三通道视频滤波器和缓冲器，具有可选截止频率和多路复用输入的RGB ， HD / SD
| 型号： | ADA4411-3ARQZ-RL |
| 厂家： | 
ADI |
| 描述： | Integrated Triple Video Filter and Buffer with Selectable Cutoff Frequencies and Multiplexed Inputs for RGB, HD/SD |
| 文件： | 总16页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated Triple Video Filter and Buffer with Selectable
Cutoff Frequencies and Multiplexed Inputs for RGB, HD/SD
ADA4411-3
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Sixth-order adjustable video filters
36 MHz, 18 MHz, and 9 MHz
Many video standards supported: RGB, YPbPr, YUV, SD, Y/C
Ideal for 720p and 1080i resolutions
−1 dB bandwidth of 30.5 MHz for HD
Low quiescent power
Only 265 mW for 3 channels on 5 V supply
Disable feature cuts supply current to 15 μA
2:1 mux on all inputs
Y1/G1 IN
×2
Y/G OUT
×4
Y2/G2 IN
36MHz, 18MHz, 9MHz
36MHz, 18MHz, 9MHz
Pb1/B1 IN
Pb2/B2 IN
×2
×4
Pb/B OUT
Pr/R OUT
Pr1/R1 IN
Pr2/R2 IN
×2
×4
36MHz, 18MHz, 9MHz
Variable gain: ×2 or ×4
INPUT SELECT
DC output offset adjust: 0.5 V, input referred
Excellent video specifications
Wide supply range: +4.5 V to 5 V
Rail-to-rail output
Output can swing 4.5 V p-p on single 5 V supply
Small packaging: 24-lead QSOP
DC
OFFSET
ADA4411-3
LEVEL1
LEVEL2
2
CUTOFF SELECT
GAIN SELECT
DISABLE
Figure 1.
APPLICATIONS
Set-top boxes
Personal video recorders
DVD players and recorders
HDTVs
Projectors
GENERAL DESCRIPTION
The ADA4411-3 is a comprehensive filtering solution designed
to give designers the flexibility to easily filter and drive various
video signals, including high definition video. Cutoff frequen-
cies of the sixth-order video filters range from 9 MHz to
36 MHz and can be selected by two logic pins to obtain four
filter combinations that are tuned for RGB, high definition, and
standard definition video signals. The ADA4411-3 has a rail-
to-rail output that can swing 4.5 V p-p on a single 5 V supply.
The ADA4411-3 can operate on a single +5 V supply as well as
on 5 V supplies. Single-supply operation is ideal in
applications where power consumption is critical. The disable
feature allows for further power conservation by reducing the
supply current to typically 15 μA when a particular device is not
in use.
Dual-supply operation is best for applications where the
negative-going video signal excursions must swing at or
below ground while maintaining excellent video performance.
The output buffers have the ability to drive two 75 Ω doubly
terminated cables that are either dc-coupled or ac-coupled.
The ADA4411-3 offers gain and voltage offset adjustments.
With a single logic pin, the throughput filter gain can be
selected to be ×2 or ×4. Output voltage offset is continuously
adjustable over an input-referred range of 5ꢀꢀ mV by applying
a differential voltage to an independent offset control input.
The ADA4411-3 is available in the 24-lead, wide body
QSOP and is rated for operation over the extended
industrial temperature range of −4ꢀ°C to +85°C.
The ADA4411-3 offers 2:1 multiplexers on all of its video
inputs, which are useful in applications where filtering is
required for multiple sources of video signals.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADA4411-3
TABLE OF CONTENTS
Features .............................................................................................. 1
Overview ..................................................................................... 11
Multiplexer Select Inputs........................................................... 11
Throughput Gain........................................................................ 11
Disable ......................................................................................... 11
Cutoff Frequency Selection....................................................... 11
Output DC Offset Control........................................................ 11
Input and Output Coupling ...................................................... 12
Printed Circuit Board Layout ................................................... 13
Video Encoder Reconstruction Filter...................................... 13
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration And Function Descriptions............................ 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 1ꢀ
Applications..................................................................................... 11
REVISION HISTORY
7/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADA4411-3
SPECIFICATIONS
VS = 5 V, @ TA = 25°C, VO = 1.4 V p-p, G = ×2, RL = 15ꢀ Ω, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
OVERALL PERFORMANCE
Offset Error
Offset Adjust Range
Input Voltage Range, All Inputs
Output Voltage Swing, All Outputs
Input referred, all channels
Input referred
12
±±00
30
mV
mV
V
V
V
VS− − 0.1
VS+ − 2.0
Positive swing
Negative swing
VS+ − 0.33 VS+ − 0.22
VS− + 0.10 VS− + 0.13
Linear Output Current per Channel
Integrated Voltage Noise, Referred to Input
Filter Input Bias Current
Total Harmonic Distortion at 1 MHz
Gain Error Magnitude
30
0.±2
6.6
0.01/0.04
mA
mV rms
μA
%
All channels
All channels
FC = 36 MHz, FC = 18 MHz/FC = 9 MHz
G = ×2/G = ×4
0.13/0.1±
0.38/0.40
dB
FILTER DYNAMIC PERFORMANCE
−1 dB Bandwidth
Cutoff frequency select = 36 MHz
Cutoff frequency select = 18 MHz
Cutoff frequency select = 9 MHz
Cutoff frequency select = 36 MHz
Cutoff frequency select = 18 MHz
Cutoff frequency select = 9 MHz
f = 7± MHz
f = ± MHz, FC = 36 MHz
f = 1 MHz, RSOURCE = 300 Ω
f = ± MHz, FC = 36 MHz
26.±
13.±
6.±
34
16
8
30.±
1±.±
7.8
37
18
9
−43
−62
91
20
7
MHz
MHz
MHz
MHz
MHz
MHz
dB
dB
dB
ns
ns
−3 dB Bandwidth
Out-of-Band Rejection
Crosstalk
Input Mux Isolation
Propagation Delay
Group Delay Variation
−31
Cutoff frequency select = 36 MHz
Cutoff frequency select = 18 MHz
Cutoff frequency select = 9 MHz
NTSC, FC = 9 MHz
11
24
0.16
0.0±
ns
ns
%
Differential Gain
Differential Phase
NTSC, FC = 9 MHz
Degrees
CONTROL INPUT PERFORMANCE
Input Logic 0 Voltage
Input Logic 1 Voltage
Input Bias Current
All inputs except DISABLE
All inputs except DISABLE
All inputs except DISABLE
0.8
1±
V
V
μA
2.0
10
DISABLE PERFORMANCE
DISABLE Assert Voltage
DISABLE Assert Time
DISABLE Deassert Time
DISABLE Input Bias Current
Input-to-Output Isolation—Disabled
POWER SUPPLY
VS+ − 0.±
100
130
10
90
V
ns
ns
μA
dB
1±
f = 10 MHz
Operating Range
4.±
12
V
Quiescent Current
±3
1±
70
6±
±6
1±0
mA
μA
dB
dB
Quiescent Current—Disabled
PSRR, Positive Supply
PSRR, Negative Supply
All channels
All channels
62
±7
Rev. 0 | Page 3 of 16
ADA4411-3
VS = 5 V, @ TA = 25°C, VO = 1.4 V p-p, G = ×2, RL = 15ꢀ Ω, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
OVERALL PERFORMANCE
Offset Error
Offset Adjust Range
Input Voltage Range, All Inputs
Output Voltage Swing, All Outputs
Input referred, all channels
Input referred
13
±±00
32
mV
mV
V
V
V
VS− − 0.1
VS+ − 2.0
Positive swing
Negative swing
VS+ − 0.42 VS+ − 0.24
VS− + 0.24 VS− + 0.42
Linear Output Current per Channel
Integrated Voltage Noise, Referred to Input
Filter Input Bias Current
Total Harmonic Distortion at 1 MHz
Gain Error Magnitude
30
0.±0
6.3
0.01/0.03
mA
mV rms
μA
%
All channels
All channels
FC = 36 MHz, FC = 18 MHz/FC = 9 MHz
G = ×2/G = ×4
0.13/0.13
0.34/0.36
dB
FILTER DYNAMIC PERFORMANCE
−1 dB Bandwidth
Cutoff frequency select = 36 MHz
Cutoff frequency select = 18 MHz
Cutoff frequency select = 9 MHz
Cutoff frequency select = 36 MHz
Cutoff frequency select = 18 MHz
Cutoff frequency select = 9 MHz
f = 7± MHz
f = ± MHz, FC = 36 MHz
f = 1 MHz, RSOURCE = 300 Ω
f = ± MHz, FC = 36 MHz
30.0
1±.0
7.8
36
18
9
−42
−62
91
19
7
MHz
MHz
MHz
MHz
MHz
MHz
dB
dB
dB
ns
ns
−3 dB Bandwidth
33
17
8
Out-of-Band Rejection
Crosstalk
Input MUX Isolation
Propagation Delay
Group Delay Variation
−31
2±
Cutoff frequency select = 36 MHz
Cutoff frequency select = 18 MHz
Cutoff frequency select = 9 MHz
NTSC, FC = 9 MHz
13
22
0.04
0.16
ns
ns
%
Differential Gain
Differential Phase
NTSC, FC = 9 MHz
Degrees
CONTROL INPUT PERFORMANCE
Input Logic 0 Voltage
Input Logic 1 Voltage
Input Bias Current
All inputs except DISABLE
All inputs except DISABLE
All inputs except DISABLE
0.8
1±
V
V
μA
2.0
10
DISABLE PERFORMANCE
DISABLE Assert Voltage
DISABLE Assert Time
DISABLE Deassert Time
DISABLE Input Bias Current
Input-to-Output Isolation—Disabled
POWER SUPPLY
VS+ − 0.±
7±
12±
34
V
ns
ns
μA
dB
4±
f = 10 MHz
90
Operating Range
4.±
12
V
Quiescent Current
±7
1±
74
6±
60
1±0
mA
μA
dB
dB
Quiescent Current—Disabled
PSRR, Positive Supply
PSRR, Negative Supply
All channels
All channels
64
±7
Rev. 0 | Page 4 of 16
ADA4411-3
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Storage Temperature
Operating Temperature Range
Lead Temperature Range (Soldering 10 sec)
Junction Temperature
The power dissipated in the package (PD) is the sum of the
Rating
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to load drive
depends on the particular application. For each output, the
power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to all of the loads is equal to the sum of
the power dissipations due to each individual load. RMS
voltages and currents must be used in these calculations.
12 V
See Figure 2
–6±°C to +12±°C
–40°C to +8±°C
300°C
1±0°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads from metal traces, through-holes, ground, and power
planes reduces the θJA.
THERMAL RESISTANCE
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 24-lead QSOP
(83°C/W) on a JEDEC standard 4-layer board. θJA values are
approximations.
θJA is specified for the worst-case conditions, that is, θJA is
specified for device soldered in circuit board for surface-mount
packages.
Table 4. Thermal Resistance
Package Type
24 Lead QSOP
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
θJA
Unit
83
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4411-3
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 15ꢀ°C, which is the glass
transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4411-3.
Exceeding a junction temperature of 15ꢀ°C for an extended
period can result in changes in the silicon devices potentially
causing failure.
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page ± of 16
ADA4411-3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
24
23
22
21
20
19
18
17
16
15
14
13
LEVEL1
DISABLE
Y1/G1
LEVEL2
G_SEL
VCC
3
4
GND
Y/G_OUT
VEE
5
Pb1/B1
GND
ADA4411-3
6
Pb/B_OUT
VEE
TOP VIEW
(Not to Scale)
7
Pr1/R1
F_SEL_A
F_SEL_B
Y2/G2
8
Pr/R_OUT
VCC
9
10
11
12
MUX
DGND
Pr2/R2
DGND
Pb2/B2
Figure 3. 24-Lead QSOP Pin Configuration
Table 5. 24-Lead QSOP Pin Function Descriptions
Pin No.
Name
LEVEL1
DISABLE
Y1/G1
GND
Description
1
2
3
4
±
6
7
8
DC Level Adjust Pin 1
Disable/Power Down
Channel 1 Y/G Video Input
Signal Ground Reference
Channel 1 Pb/B Video Input
Signal Ground Reference
Channel 1 Pr/R Video Input
Filter Cutoff Select Input A
Filter Cutoff Select Input B
Channel 2 Y/G Video Input
Digital Ground Reference
Channel 2 Pb/B Video Input
Digital Ground Reference
Channel 2 Pr/R Video Input
Input Mux Select Line
Positive Power Supply
Pr/R Video Output
Negative Power Supply
Pb/B Video Output
Negative Power Supply
Y/G Video Output
Positive Power Supply
Gain Select
DC Level Adjust Pin 2
Pb1/B1
GND
Pr1/R1
F_SEL_A
F_SEL_B
Y2/G2
DGND
Pb2/B2
DGND
Pr2/R2
MUX
VCC
Pr/R_OUT
VEE
Pb/B_OUT
VEE
Y/G_OUT
VCC
9
10
11
12
13
14
1±
16
17
18
19
20
21
22
23
24
G_SEL
LEVEL2
Rev. 0 | Page 6 of 16
ADA4411-3
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, G = ×2, RL = 15ꢀ ꢁ, VO = 1.4 V p-p, VS = 5 V, TA = 25°C.
9
6
3
15
12
9
F
= 36MHz
C
F
= 36MHz
C
6
3
0
–3
0
–3
–6
–9
F
= 9MHz
C
F
= 9MHz
C
–6
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
–48
–9
F
= 18MHz
F = 18MHz
C
C
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
BLACK LINE: V = +5V
GRAY LINE: V = ±5V
S
S
BLACK LINE: V = +5V
S
GRAY LINE: V = ±5V
S
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
Figure 4. Frequency Response vs. Power Supply and
Cutoff Frequency (G = ×2)
Figure 7. Frequency Response vs. Power Supply and
Cutoff Frequency (G = ×4)
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
F
= 36MHz
C
F
= 9MHz
C
F
= 36MHz
C
F
= 9MHz
C
F
= 18MHz
C
F
= 18MHz
C
BLACK LINE: V = +5V
S
GRAY LINE: V = ±5V
BLACK LINE: V = +5V
GRAY LINE: V = ±5V
S
S
S
9.0
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
Figure 5. Frequency Response Flatness vs. Power Supply and
Cutoff Frequency (G = ×2)
Figure 8. Frequency Response Flatness vs. Power Supply and Cutoff Frequency
(G = ×4)
9
6
3
0
9
6
3
0
F
= 36MHz
F = 36MHz
C
C
F
= 9MHz
–3
–6
–9
–3
–6
–9
C
F
F
= 9MHz
C
= 18MHz
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
–48
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
–48
C
F
= 18MHz
C
–40°C
+25°C
+85°C
BLACK LINE:
= 100mV p-p
GRAY LINE:
= 2V p-p
V
OUT
V
OUT
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
Figure 9. Frequency Response vs. Temperature and Cutoff Frequency
Figure 6. Frequency Response vs. Cutoff Frequency and Output Amplitude
Rev. 0 | Page 7 of 16
ADA4411-3
100
BLACK LINE: V = +5V
S
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
2.5
GRAY LINE: V = ±5V
90
S
2 × INPUT
OUTPUT
2.0
80
1.5
F
= 9MHz
C
70
60
50
40
30
20
10
1.0
0.5% (70ns)
0.5
ERROR
0
F
= 18MHz
C
–0.5
–1.0
–1.5
–2.0
–2.5
1% (58ns)
F
= 36MHz
C
50ns/DIV
1
10
FREQUENCY (MHz)
100
Figure 13. Settling Time
Figure 10. Group Delay vs. Frequency, Power Supply, and Cutoff Frequency
–40
–30
R
= 300Ω
R
= 300Ω
SOURCE
SOURCE
UNSELECTED MUX IS DRIVEN
Y AND Pr SOURCE CHANNELS
Pb RECEPTOR CHANNEL
–40
–50
–50
F
= 36MHz
= 18MHz
C
–60
–70
–60
F
= 9MHz
C
F
= 9MHz
–70
C
F
C
–80
–80
F
= 18MHz
–90
C
F
= 36MHz
C
–90
–100
–100
–110
–110
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 11. Channel-to-Channel Crosstalk vs. Frequency and Cutoff Frequency
Figure 14. MUX Isolation vs. Frequency and Cutoff Frequency
3.5
3.3
3.1
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
F
F
= 36MHz
= 18MHz
F
F
= 36MHz
= 18MHz
C
C
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
C
F
= 9MHz
C
F
= 9MHz
C
C
100ns/DIV
100ns/DIV
Figure 15. Transient Response vs. Cutoff Frequency (G = ×4)
Figure 12. Transient Response vs. Cutoff Frequency (G = ×2)
Rev. 0 | Page 8 of 16
ADA4411-3
5
–5
5
–5
F
= 18MHz
C
F
= 9MHz
C
–15
–25
–35
–45
–55
–65
–75
–15
–25
–35
–45
–55
–65
–75
F
= 9MHz
C
F
= 18MHz
C
F
= 36MHz
C
F
= 36MHz
C
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 16. Positive Supply PSRR vs. Frequency and Cutoff Frequency
Figure 18. Negative Supply PSRR vs. Frequency and Cutoff Frequency
6
F
= 36MHz
2× INPUT
C
5
4
F
= 18MHz
C
3
NETWORK
ANALYZER Tx
NETWORK
ANALYZER Rx
R
= 150Ω
L
F
= 9MHz
C
2
50Ω
118Ω
DUT
50Ω
1
50Ω
86.6Ω
0
MINIMUM-LOSS MATCHING NETWORK LOSS CALIBRATED OUT
200ns/DIV
–1
Figure 19. Basic Test Circuit for Swept Frequency Measurements
Figure 17. Overdrive Recovery vs. Cutoff Frequency
Rev. 0 | Page 9 of 16
ADA4411-3
THEORY OF OPERATION
The ADA4411-3 is an integrated video filtering and driving
solution that offers variable bandwidth to meet the needs of a
number of different video resolutions. There are three filters,
targeted for use with component video signals. The filters
have selectable bandwidths that correspond to the popular
component video standards. Each filter has a sixth-order
Butterworth response that includes group delay optimization.
The group delay variation from 1 MHz to 36 MHz in the
36 MHz section is 7 ns, which produces a fast settling pulse
response.
For single-supply applications (VS− = GND), the input voltage
range extends from 1ꢀꢀ mV below ground to within 2.ꢀ V of
the most positive supply. Each filter section has a 2:1 input
multiplexer that includes level-shifting circuitry. The level-
shifting circuitry adds a dc component to ground-referenced
input signals so that they can be reproduced accurately without
the output buffers hitting the negative rail. Because the filters
have negative rail input and rail-to-rail output, dc level shifting
is generally not necessary, unless accuracy greater than that of
the saturated output of the driver is required at the most
negative edge. This varies with load but is typically 1ꢀꢀ mV
in a dc-coupled, single-supply application. If ac coupling is
used, the saturated output level is higher because the drivers
have to sink more current on the low side. If dual supplies are
used (VS− < GND), no level shifting is required. In dual-supply
applications, the level-shifting circuitry can be used to take a
ground referenced signal and put the blanking level at ground
while the sync level is below ground.
The ADA4411-3 is designed to operate in many video
environments. The supply range is 5 V to 12 V, single supply or
dual supply, and requires a relatively low nominal quiescent
current of 15 mA per channel. In single-supply applications,
the PSRR is greater than 6ꢀ dB, providing excellent rejection
in systems with supplies that are noisy or under-regulated. In
applications where power consumption is critical, the part
can be powered down to draw typically 15 μA by pulling the
DISABLE pin to the most positive rail. The ADA4411-3 is also
well-suited for high encoding frequency applications because it
maintains a stop-band attenuation of more than 4ꢀ dB to 4ꢀꢀ MHz.
The output drivers on the ADA4411-3 have rail-to-rail output
capabilities. They provide either 6 dB or 12 dB of gain with
respect to the ground pins. Gain is controlled by the external
gain select pin. Each output is capable of driving two ac- or dc-
coupled 75 Ω source-terminated loads. If a large dc output level
is required while driving two loads, ac coupling should be used
to limit the power dissipation.
The ADA4411-3 is intended to take dc-coupled inputs
from an encoder or other ground referenced video signals.
The ADA4411-3 input is high impedance. No minimum or
maximum input termination is required, though input
terminations above 1 kΩ can degrade crosstalk performance
at high frequencies. No clamping is provided internally. For
applications where dc restoration is required, dual supplies
work best. Using a termination resistance of less than a few
hundred ohms to ground on the inputs and suitably adjusting
the level-shifting circuitry provides precise placement of the
output voltage.
Input MUX isolation is primarily a function of the source
resistance driving into the ADA4411-3. Higher resistances
result in lower isolation over frequency, while a low source
resistance, such as 75 Ω, has the best isolation performance.
See Figure 14 for the MUX isolation performance.
Rev. 0 | Page 10 of 16
ADA4411-3
APPLICATIONS
OVERVIEW
CUTOFF FREQUENCY SELECTION
With its high impedance multiplexed inputs and high output
drive, the ADA4411-3 is ideally suited to video reconstruction
and antialias filtering applications. The high impedance inputs
give designers flexibility with regard to how the input signals
are terminated. Devices with DAC current source outputs that
feed the ADA4411-3 can be loaded in whatever resistance
provides the best performance, and devices with voltage outputs
can be optimally terminated as well. The ADA4411-3 outputs
can each drive up to two source-terminated 75 Ω loads and can
therefore directly drive the outputs from set-top boxes, DVD
players, and the like without the need for a separate output
buffer.
Four combinations of cutoff frequencies are provided for the
video signals. The cutoff frequencies have been selected to
correspond with the most commonly deployed component
video scanning systems. Selection between the cutoff frequency
combinations is controlled by the logic signals applied to the
F_SEL_A and F_SEL_B inputs. Table 7 summarizes cutoff
frequency selection.
Table 7. Filter Cutoff Frequency Selection
F_SEL_A F_SEL_B Y/G Cutoff Pb/B Cutoff Pr/R Cutoff
0
0
1
1
0
1
0
1
36 MHz
36 MHz
18 MHz
9 MHz
36 MHz
18 MHz
18 MHz
9 MHz
36 MHz
18 MHz
18 MHz
9 MHz
Binary control inputs are provided to select cutoff frequency,
throughput gain, and input signal. These inputs are compatible
with 3 V and 5 V TTL and CMOS logic levels referenced to
GND. The disable feature is asserted by pulling the DISABLE
pin to the positive supply.
OUTPUT DC OFFSET CONTROL
The LEVEL1 and LEVEL2 inputs work as a differential, input-
referred output offset control. In other words, the output offset
voltage of a given channel is equal to the difference in voltage
between the LEVEL1 and LEVEL2 inputs, multiplied by the
overall filter gain. This relationship is expressed in Equation 1.
The LEVEL1 and LEVEL2 inputs comprise a differential input
that controls the dc level at the output pins.
MULTIPLEXER SELECT INPUTS
VOS (OUT) = (LEVEL1− LEVEL2)(G)
(1)
Selection between the two multiplexer inputs is controlled by
the logic signals applied to the MUX inputs. Table 6
summarizes the multiplexer operation.
LEVEL1 and LEVEL2 are the voltages applied to the respective
inputs, and G is the throughput gain.
For example, with the G_SEL input set for ×2 gain, setting
LEVEL1 to 3ꢀꢀ mV and LEVEL2 to ꢀ V shifts the offset voltages
at the ADA4411-3 outputs to 6ꢀꢀ mV. This particular setting
can be used in most single-supply applications to keep the
output swings safely above the negative supply rail.
THROUGHPUT GAIN
The throughput gain of the ADA4411-3 signal paths can
be either × 2 or × 4. Gain selection is controlled by the logic
signal applied to the G_SEL pin. Table 6 summarizes how the
gain is selected.
The maximum differential voltage that can be applied across the
LEVEL1 and LEVEL2 inputs is 5ꢀꢀ mV. From a single-ended
standpoint, the LEVEL1 and LEVEL2 inputs have the same
range as the filter inputs. See the Specifications tables for the
limits. The LEVEL1 and LEVEL2 inputs must each be bypassed
to GND with a ꢀ.1 μF ceramic capacitor.
DISABLE
The ADA4411-3 includes a disable feature that can be used
to save power when a particular device is not in use. As
indicated in the Overview section, the disable feature is
asserted by pulling the DISABLE pin to the positive supply.
Table 6 summarizes the disable feature operation. The
DISABLE pin also functions as a reference level for the logic
inputs and therefore must be connected to ground when the
device is not disabled.
In single-supply applications, a positive output offset must be
applied to keep the negative-most excursions of the output
signals above the specified minimum output swing limit.
Table 6. Logic Pin Function Description
DISABLE
MUX
G_SEL
VS+ = Disabled
GND = Enabled
1 = Channel 1 Selected
0 = Channel 2 Selected
1 = ×2 Gain
0 = ×4 Gain
Rev. 0 | Page 11 of 16
ADA4411-3
Figure 2ꢀ and Figure 21 illustrate several ways to use the
LEVEL1 and LEVEL2 inputs. Figure 2ꢀ shows examples of how
to generate fully adjustable LEVEL1 and LEVEL2 voltages from
5 V and single +5 V supplies. These circuits show a general
case, but a more practical approach is to fix one voltage and
vary the other. Figure 21 illustrates an effective way to produce
a 6ꢀꢀ mV output offset voltage in a single-supply application.
Although the LEVEL2 input could simply be connected to
GND, Figure 21 includes bypassed resistive voltage dividers for
each input so that the input levels can be changed, if necessary.
Additionally, many in-circuit testers require that I/O signals not
be tied directly to the supplies or GND. DNP indicates do not
populate.
INPUT AND OUTPUT COUPLING
Inputs to the ADA4411-3 are normally dc-coupled. Ac coupling
the inputs is not recommended; however, if ac coupling is
necessary, suitable circuitry must be provided following the ac
coupling element to provide proper dc level and bias currents at
the ADA4411-3 input stages. The ADA4411-3 outputs can be
either ac- or dc-coupled.
When driving single ac-coupled loads in standard 75 Ω video
distribution systems, 22ꢀ μF coupling capacitors are recom-
mended for use on all but the chrominance signal output. Since
the chrominance signal is a narrow-band modulated carrier, it
has no low frequency content and can therefore be coupled with
a ꢀ.1 μF capacitor.
DUAL SUPPLY
+5V
9.53kΩ
+5V
There are two ac coupling options when driving two loads from
one output. One simply uses the same value capacitor on the
second load, while the other is to use a common coupling
capacitor that is at least twice the value used for the single load
(see Figure 22 and Figure 23).
9.53kΩ
LEVEL1
0.1μF
LEVEL2
0.1μF
1kΩ
1kΩ
9.53kΩ
9.53kΩ
–5V
–5V
75Ω
CABLE
220μF
75Ω
SINGLE SUPPLY
ADA4411-3
+5V
+5V
75Ω
75Ω
75Ω
CABLE
9.09kΩ
1kΩ
9.09kΩ
1kΩ
220μF
75Ω
LEVEL1
0.1μF
LEVEL2
0.1μF
Figure 20. Generating Fully Adjustable Output Offsets
Figure 22. Driving Two AC-Coupled Loads with Two Coupling Capacitors
75Ω
CABLE
+5V
10kΩ
+5V
DNP
75Ω
ADA4411-3
470μF
75Ω
75Ω
CABLE
LEVEL1
0.1μF
LEVEL2
DNP
75Ω
634Ω
0Ω
75Ω
Figure 21. Flexible Circuits to Set the LEVEL1 and LEVEL2 Inputs to
Obtain a 600 mV Output Offset on a Single Supply
Figure 23. Driving Two AC-Coupled Loads with One Common Coupling Capacitor
When driving two parallel 15ꢀ Ω loads (75 Ω effective load),
the 3 dB bandwidth of the filters typically varies from that of
the filters with a single 15ꢀ Ω load. For the 9 MHz and 18 MHz
filters, the typical variation is within 1.ꢀ%; for the 36 MHz
filters, the typical variation is within 2.5%.
Rev. 0 | Page 12 of 16
ADA4411-3
When the ADA4411-3 receives its inputs from a device
PRINTED CIRCUIT BOARD LAYOUT
with current outputs, the required load resistor value for
the output current is often different from the characteristic
impedance of the signal traces. In this case, if the intercon-
nections are sufficiently short (<< ꢀ.1 wavelength), the trace
does not have to be terminated in its characteristic impedance.
Traces of 75 ꢁ can be used in this instance, provided their
lengths are an inch or two at the most. This is easily achieved
because the ADA4411-3 and the device feeding it are usually
adjacent to each other, and connections can be made that are
less than one inch in length.
As with all high speed applications, attention to printed
circuit board layout is of paramount importance. Standard high
speed layout practices should be adhered to when designing
with the ADA4411-3. A solid ground plane is recommended,
and surface-mount, ceramic power supply decoupling
capacitors should be placed as close as possible to the supply
pins. All of the ADA4411-3 GND pins should be connected to
the ground plane with traces that are as short as possible.
Controlled impedance traces of the shortest length possible
should be used to connect to the signal I/O pins and should not
pass over any voids in the ground plane. A 75 Ω impedance
level is typically used in video applications. All signal outputs of
the ADA4411-3 should include series termination resistors
when driving transmission lines.
VIDEO ENCODER RECONSTRUCTION FILTER
The ADA4411-3 is easily applied as a reconstruction filter at
the DAC outputs of a video encoder. Figure 24 illustrates how to
use the ADA4411-3 in this type of application with an ADV7322
video encoder in a single-supply application with ac-coupled
outputs.
Rev. 0 | Page 13 of 16
ADA4411-3
5V
(ANALOG)
0.1μF
0.1μF
DNP
10kΩ
634Ω
16
22
VCC
VCC
0.1μF
0Ω
1
LEVEL1
24
LEVEL2
ADA4411-3
0.1μF
2
DISABLE
23
15
8
G_SEL
MUX
BINARY
CONTROL
INPUTS
F_SEL_A
F_SEL_B
ADV7322
VIDEO ENCODER
9
3
220μF
220μF
220μF
75Ω
75Ω
75Ω
Y1/G1
Y2/G2
21
Y/G_OUT
10
R
L
L
L
VIDEO
5
DAC
Pb1/B1
Pb2/B2
19
17
OUTPUTS
Pb/B_OUT
Pr/R_OUT
12
R
R
7
Pr1/R1
Pr2/R2
14
GND
DGND
11, 13
VEE
4, 6
18, 20
CHANNEL 2
VIDEO
INPUTS
Figure 24. The ADA4411-3 Applied as a Single-Supply Reconstruction Filter Following the ADV7322
Rev. 0 | Page 14 of 16
ADA4411-3
OUTLINE DIMENSIONS
0.341
BSC
24
1
13
0.154
BSC
0.236
BSC
12
PIN 1
0.065
0.049
0.069
0.053
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
SEATING
PLANE
0.050
0.016
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137AE
Figure 25. 24-Lead Shrink Small Outline Package [QSOP]
(RQ-24)
Dimensions shown in inches
ORDERING GUIDE
Model
ADA4411-3ARQZ1
ADA4411-3ARQZ-R71
ADA4411-3ARQZ-RL1
Temperature Range
–40°C to +8±°C
–40°C to +8±°C
Package Description
24-Lead QSOP
24-Lead QSOP
Order Quantity
Package Option
1
RQ-24
RQ-24
RQ-24
1,000
2,±00
–40°C to +8±°C
24-Lead QSOP
1 Z = Pb-free part.
Rev. 0 | Page 1± of 16
ADA4411-3
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05527–0–7/05(0)
Rev. 0 | Page 16 of 16
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