ADA4666-2ARMZ-RL [ADI]
18 V, 725 A, 4 MHz CMOS RRIO Operational Amplifier; 18 V ， 725 A， 4 MHz的CMOS RRIO运算放大器
| 型号： | ADA4666-2ARMZ-RL |
| 厂家： | 
ADI |
| 描述： | 18 V, 725 A, 4 MHz CMOS RRIO Operational Amplifier |
| 文件： | 总32页 (文件大小：896K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
18 V, 725 µA, 4 MHz
CMOS RRIO Operational Amplifier
ADA4666-2
Data Sheet
FEATURES
PIN CONNECTION DIAGRAMS
Low power at high voltage (18 V): 725 μA maximum
Low offset voltage:
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
ADA4666-2
OUT B
–IN B
+IN B
TOP VIEW
2.2 mV maximum over entire common-mode range
Low input bias current: 15 pA maximum
Gain bandwidth product: 4 MHz typical at AV = 100
Unity-gain crossover: 4 MHz typical
−3 dB closed-loop bandwidth: 2.1 MHz typical
Single-supply operation: 3 V to 18 V
Dual-supply operation: 1.5 V to 9 V
Unity-gain stable
(Not to Scale)
Figure 1. 8-Lead MSOP
OUT A 1
8 V+
7 OUT B
6 –IN B
5 +IN B
–IN A 2
+IN A 3
V– 4
ADA4666-2
TOP VIEW
(Not to Scale)
NOTES
APPLICATIONS
1. CONNECT THE EXPOSED PAD TO V– OR
LEAVE IT UNCONNECTED.
Current shunt monitors
Active filters
Portable medical equipment
Buffer/level shifting
High impedance sensor interfaces
Battery powered instrumentation
Figure 2. 8-Lead LFCSP
10000
1000
100
10
V
= 18V
SY
GENERAL DESCRIPTION
–40°C
+25°C
+85°C
+125°C
The ADA4666-2 is a dual, rail-to-rail input/output amplifier
optimized for low power, high bandwidth, and wide operating
supply voltage range applications.
The ADA4666-2 performance is guaranteed at 3.0 V, 10 V,
and 18 V power supply voltages. It is an excellent selection for
applications that use single-ended supplies of 3.3 V, 5 V, 1 0 V,
12 V, and 15 V, and dual supplies of 2.5 V, 3.3 V, and 5 V.
1
0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
Figure 3. Output Voltage (VOH) to Supply Rail vs. Load Current
The ADA4666-2 is specified over the extended industrial
temperature range (−40°C to +125°C) and is available in
8-lead MSOP and 8-lead LFCSP (3 mm × 3 mm) packages.
Table 1. Precision Low Power Op Amps (<1 mA)
Supply Voltage
5 V
12 V to 16 V 30 V
Single
ADA4505-1
AD8500
ADA4505-2
AD8502
AD8506
AD8546
ADA4505-4
AD8504
AD8508
AD8548
OP196
OP777
Dual
AD8657
OP296
ADA4661-2
ADA4666-2
AD8659
OP496
ADA4096-2
OP727
AD8682
AD8622
ADA4096-4
OP747
Quad
AD8684
AD8624
Rev. 0
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Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
ADA4666-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Stage................................................................................... 22
Gain Stage.................................................................................... 23
Output Stage................................................................................ 23
Maximum Power Dissipation................................................... 23
Rail-to-Rail Input and Output.................................................. 23
Comparator Operation.............................................................. 24
EMI Rejection Ratio .................................................................. 25
Current Shunt Monitor.............................................................. 25
Active Filters ............................................................................... 25
Capacitive Load Drive ............................................................... 26
Noise Considerations with High Impedance Sources........... 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
Applications....................................................................................... 1
General Description......................................................................... 1
Pin Connection Diagrams............................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—18 V Operation ............................. 3
Electrical Characteristics—10 V Operation ............................. 5
Electrical Characteristics—3.0 V Operation ............................ 7
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 11
Applications Information .............................................................. 22
REVISION HISTORY
7/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
ADA4666-2
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—18 V OPERATION
VSY = 18 V, VCM = VSY/ 2 V, T A = 25°C, unless otherwise specified.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
0.5
2.2
2.2
3.5
3.1
15
100
900
11
mV
mV
mV
μV/°C
pA
pA
pA
pA
pA
pA
V
VCM = 0 V to 18 V
VCM = 0 V to 18 V; −40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
0.6
0.5
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
30
300
18
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 18 V
80
77
120
120
95
dB
dB
dB
dB
VCM = 0 V to 18 V; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 0.5 V to 17.5 V
−40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain
147
Input Resistance
Differential Mode
Common Mode
RINDM
RINCM
>10
>10
GΩ
GΩ
Input Capacitance
Differential Mode
Common Mode
CINDM
CINCM
8.5
3
pF
pF
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 1 kΩ to VCM
17.95 17.97
17.94
V
V
V
17.6
17.79
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 1 kΩ to VCM
−40°C ≤ TA ≤ +125°C
Dropout voltage = 1 V
Pulse width = 10 ms; refer to the Maximum
Power Dissipation section
17.58
V
Output Voltage Low
VOL
14
25
40
200
300
mV
mV
mV
mV
mA
mA
120
Continuous Output Current
Short-Circuit Current
IOUT
ISC
40
220
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
ZOUT
PSRR
ISY
f = 100 kHz, AV = 1
0.2
Ω
VSY = 3.0 V to 18 V
−40°C ≤ TA ≤ +125°C
IOUT = 0 mA
120
120
145
630
dB
dB
µA
µA
Supply Current per Amplifier
725
975
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Closed-Loop Bandwidth
Phase Margin
SR
RS = 1 kΩ, RL = 10 kΩ, CL = 10 pF, AV = 1
2
4
4
2.1
60
1.3
V/µs
MHz
MHz
MHz
Degrees
µs
GBP
UGC
f−3 dB
ΦM
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AV = 100
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AVO = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AVO = 1
VIN = 1 V step, RL = 10 kΩ, CL = 10 pF
Settling Time to 0.1%
tS
Rev. 0 | Page 3 of 32
ADA4666-2
Data Sheet
Parameter
Symbol
CS
EMIRR
Test Conditions/Comments
Min
Typ
Max Unit
Channel Separation
EMI Rejection Ratio of +IN x
f = 400 MHz
f = 900 MHz
f = 1800 MHz
VIN = 17.9 V p-p, f = 10 kHz, RL = 10 kΩ
VIN = 100 mV peak (200 mV p-p)
80
dB
34
42
50
60
dB
dB
dB
dB
f = 2400 MHz
NOISE PERFORMANCE
Total Harmonic Distortion Plus Noise THD + N AV = 1, VIN = 5.4 V rms at 1 kHz
Bandwidth = 80 kHz
Bandwidth = 500 kHz
Peak-to-Peak Noise
0.0004
0.0008
3
18
14
%
%
µV p-p
nV/√Hz
nV/√Hz
fA/√Hz
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
Voltage Noise Density
Current Noise Density
in
f = 1 kHz
360
Rev. 0 | Page 4 of 32
Data Sheet
ADA4666-2
ELECTRICAL CHARACTERISTICS—10 V OPERATION
VSY = 10 V, VCM = VSY/ 2 V, T A = 25°C, unless otherwise specified.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
2.2
2.2
3.5
3.1
15
80
750
11
mV
mV
mV
μV/°C
pA
pA
pA
pA
pA
pA
V
VCM = 0 V to 10 V
VCM = 0 V to 10 V; −40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
0.6
0.25
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
30
270
10
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 10 V
75
72
120
120
90
dB
dB
dB
dB
VCM = 0 V to 10 V; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 0.5 V to 9.5 V
−40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain
145
Input Resistance
Differential Mode
Common Mode
RINDM
RINCM
>10
>10
GΩ
GΩ
Input Capacitance
Differential Mode
Common Mode
CINDM
CINCM
8.5
3
pF
pF
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 1 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 1 kΩ to VCM
−40°C ≤ TA ≤ +125°C
Dropout voltage = 1 V
Pulse width = 10 ms; refer to the Maximum
Power Dissipation section
9.96
9.96
9.7
9.98
9.88
10
V
V
V
V
mV
mV
mV
mV
mA
mA
9.7
Output Voltage Low
VOL
15
30
110
200
77
Continuous Output Current
Short-Circuit Current
IOUT
ISC
40
220
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
ZOUT
PSRR
ISY
f = 100 kHz, AV = 1
0.2
Ω
VSY = 3.0 V to 18 V
−40°C ≤ TA ≤ +125°C
IOUT = 0 mA
120
120
145
620
dB
dB
µA
µA
Supply Current per Amplifier
725
975
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Closed-Loop Bandwidth
Phase Margin
SR
RS = 1 kΩ, RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AV = 100
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AVO = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AVO = 1
VIN = 1 V step, RL = 10 kΩ, CL = 10 pF
1.8
4
4
2.1
60
1.3
85
V/µs
MHz
MHz
MHz
Degrees
µs
GBP
UGC
f−3 dB
ΦM
tS
Settling Time to 0.1%
Channel Separation
CS
VIN = 9.9 V p-p, f = 10 kHz, RL = 10 kΩ
dB
Rev. 0 | Page 5 of 32
ADA4666-2
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max Unit
EMI Rejection Ratio of +IN x
f = 400 MHz
f = 900 MHz
f = 1800 MHz
f = 2400 MHz
EMIRR
VIN = 100 mV peak (200 mV p-p)
34
42
50
60
dB
dB
dB
dB
NOISE PERFORMANCE
Total Harmonic Distortion Plus Noise THD + N
Bandwidth = 80 kHz
Bandwidth = 500 kHz
AV = 1, VIN =2.2 V rms at 1 kHz
0.0004
0.0008
3
18
14
%
%
µV p-p
nV/√Hz
nV/√Hz
fA/√Hz
Peak-to-Peak Noise
Voltage Noise Density
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
Current Noise Density
in
f = 1 kHz
360
Rev. 0 | Page 6 of 32
Data Sheet
ADA4666-2
ELECTRICAL CHARACTERISTICS—3.0 V OPERATION
VSY = 3.0 V, VCM = VSY/2 V, T A = 25°C, unless otherwise specified.
Table 4.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
0.5
2.2
2.2
3.5
3.1
8
45
650
11
30
27
3
mV
mV
mV
μV/°C
pA
pA
pA
pA
pA
pA
V
VCM = 0 V to 3.0 V
VCM = 0 V to 3.0 V; −40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
0.6
0.15
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 3.0 V
64
61
105
105
80
dB
dB
dB
dB
VCM = 0 V to 3.0 V; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 0.5 V to 2.5 V
−40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain
130
Input Resistance
Differential Mode
Common Mode
RINDM
RINCM
>10
>10
GΩ
GΩ
Input Capacitance,
Differential Mode
Common Mode
CINDM
CINCM
8.5
3
pF
pF
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 1 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 1 kΩ to VCM
−40°C ≤ TA ≤ +125°C
Dropout voltage = 1 V
Pulse width = 10 ms; refer to the Maximum
Power Dissipation section
2.98
2.98
2.9
2.99
2.96
4
V
V
V
V
mV
mV
mV
mV
mA
mA
2.9
Output Voltage Low
VOL
8
15
40
65
25
Continuous Output Current
Short-Circuit Current
IOUT
ISC
40
220
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
ZOUT
PSRR
ISY
f = 100 kHz, AV = 1
0.2
Ω
VSY = 3.0 V to 18 V
−40°C ≤ TA ≤ +125°C
IOUT = 0 mA
120
120
145
615
dB
dB
µA
µA
Supply Current per Amplifier
725
975
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
SR
RS = 1 kΩ, RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AV = 100
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AVO = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 1 V step, RL = 10 kΩ, CL = 10 pF
1.7
4
4
1.7
1.3
60
90
V/µs
MHz
MHz
MHz
µs
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Closed-Loop Bandwidth
Settling Time to 0.1%
Phase Margin
GBP
UGC
f−3 dB
tS
ΦM
CS
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AVO = 1
VIN = 2.9 V p-p, f = 10 kHz, RL = 10 kΩ
Degrees
dB
Channel Separation
Rev. 0 | Page 7 of 32
ADA4666-2
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
EMI Rejection Ratio of +IN x
f = 400 MHz
f = 900 MHz
f = 1800 MHz
f = 2400 MHz
EMIRR
VIN = 100 mV peak (200 mV p-p)
34
42
50
60
dB
dB
dB
dB
NOISE PERFORMANCE
Total Harmonic Distortion Plus Noise THD + N AV = 1, VIN = 0.44 V rms at 1 kHz
Bandwidth = 80 kHz
Bandwidth = 500 kHz
Peak-to-Peak Noise
0.002
0.003
3
18
14
%
%
µV p-p
nV/√Hz
nV/√Hz
fA/√Hz
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
Voltage Noise Density
Current Noise Density
in
f = 1 kHz
360
Rev. 0 | Page 8 of 32
Data Sheet
ADA4666-2
ABSOLUTE MAXIMUM RATINGS
Table 5.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages using a
standard 4-layer JEDEC board. The exposed pad of the LFCSP
package is soldered to the board.
Parameter
Rating
Supply Voltage
Input Voltage
Input Current1
20.5 V
(V−) − 300 mV to (V+) + 300 mV
10 mA
Differential Input Voltage
Limited by maximum input
current
Refer to the Maximum Power
Dissipation section
Table 6. Thermal Resistance
Package Type
8-Lead MSOP
8-Lead LFCSP
θJA
θJC
Unit
°C/W
°C/W
Output Short-Circuit
Duration to GND
Temperature Range
Storage
Operating
Junction
142
83.5
45
48.51
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
1 θJC is measured on the top surface of the package.
ESD CAUTION
Lead Temperature
(Soldering, 60 sec)
ESD
4 kV
Human Body Model2
Machine Model3
400 V
Field-Induced Charged-
Device Model (FICDM)4
1.25 kV
1 The input pins have clamp diodes to the power supply pins and to each
other. Limit the input current to 10 mA or less when input signals exceed the
power supply rail by 0.3 V.
2 Applicable standard: MIL-STD-883, Method 3015.7.
3 Applicable standard: JESD22-A115-A (ESD machine model standard of
JEDEC).
4 Applicable Standard JESD22-C101C (ESD FICDM standard of JEDEC).
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 9 of 32
ADA4666-2
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
OUT A 1
–IN A 2
+IN A 3
V– 4
8 V+
7 OUT B
6 –IN B
5 +IN B
ADA4666-2
TOP VIEW
(Not to Scale)
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
ADA4666-2
OUT B
–IN B
+IN B
TOP VIEW
NOTES
(Not to Scale)
1. CONNECT THE EXPOSED PAD TO V– OR
LEAVE IT UNCONNECTED.
Figure 5. Pin Configuration, 8-Lead LFCSP
Figure 4. Pin Configuration, 8-Lead MSOP
Table 7. Pin Function Descriptions
Pin No.1
8-Lead MSOP 8-Lead LFCSP Mnemonic Description
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
92
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
Output, Channel A.
Negative Input, Channel A.
Positive Input, Channel A.
Negative Supply Voltage.
Positive Input, Channel B.
Negative Input, Channel B.
Output, Channel B.
Positive Supply Voltage.
Exposed Pad. For the 8-lead LFCSP only, connect the exposed pad to V− or leave it
unconnected.
N/A
EPAD
1 N/A means not applicable.
2 The exposed pad is not shown in the pin configuration diagram, Figure 5.
Rev. 0 | Page 10 of 32
Data Sheet
ADA4666-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
70
70
60
50
40
30
20
10
0
V
V
= 3V
V
= 18V
SY
SY
= V /2
V
= V /2
CM
SY
CM
SY
60
50
40
30
20
10
0
600 CHANNELS
600 CHANNELS
V
(mV)
V
(mV)
OS
OS
Figure 6. Input Offset Voltage Distribution
Figure 9. Input Offset Voltage Distribution
20
18
16
14
12
10
8
20
18
16
14
12
10
8
V
V
= 3V
V
= 18V
SY
SY
= V /2
= V /2
V
CM
SY
CM
SY
–40°C ≤ T ≤ +125°C
100 CHANNELS
–40°C ≤ T ≤ +125°C
100 CHANNELS
A
A
6
6
4
4
2
2
0
0
TCV (µV/°C)
TCV (µV/°C)
OS
OS
Figure 7. Input Offset Voltage Drift Distribution
Figure 10. Input Offset Voltage Drift Distribution
1500
1000
500
1500
1000
500
V = 18V
SY
16 CHANNELS
V
= 3V
SY
16 CHANNELS
0
0
–500
–1000
–1500
–500
–1000
–1500
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
3.0
0
1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 16.5 18.0
V
V
(V)
CM
CM
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
Figure 11. Input Offset Voltage vs. Common-Mode Voltage
Rev. 0 | Page 11 of 32
ADA4666-2
Data Sheet
1500
1000
500
1500
V
= 18V
SY
V
= 3V
SY
25 CHANNELS AT –40°C AND +85°C
25 CHANNELS AT –40°C AND +85°C
1000
500
0
0
–500
–1000
–1500
–500
–1000
–1500
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
3.0
V
V
(V)
CM
CM
Figure 12. Input Offset Voltage vs. Common-Mode Voltage
Figure 15. Input Offset Voltage vs. Common-Mode Voltage
1500
1000
500
1500
1000
500
V
= 18V
SY
V
= 3V
SY
25 CHANNELS AT –40°C AND +125°C
25 CHANNELS AT –40°C AND +125°C
0
0
–500
–1000
–1500
–500
–1000
–1500
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
3.0
V
V
(V)
CM
CM
Figure 13. Input Offset Voltage vs. Common-Mode Voltage
Figure 16. Input Offset Voltage vs. Common-Mode Voltage
0
0
V
ΔV
= 10V
= 400mV
CM
V
= 10V
SY
SY
–20
–40
–20
–40
ΔV = 400mV
SY
PSRR–
PSRR+
–60
–60
–80
–100
–120
–140
–160
–180
–80
–100
–120
–140
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V
(V)
V
(V)
CM
CM
Figure 17. Small Signal PSRR vs. Common-Mode Voltage
Figure 14. Small Signal CMRR vs. Common-Mode Voltage
Rev. 0 | Page 12 of 32
Data Sheet
ADA4666-2
1000
1000
100
10
V
V
= 3V
= V /2
SY
V = 18V
SY
SY
V
= V /2
SY
CM
CM
100
10
1
|I –|
B
|I –|
B
|I +|
|I +|
B
B
1
0.1
0.1
25
50
75
TEMPERATURE (°C)
100
125
25
50
75
TEMPERATURE (°C)
100
125
Figure 18. Input Bias Current vs. Temperature
Figure 21. Input Bias Current vs. Temperature
3
2
3
V
V
= 3V
= V /2
SY
V
V
= 18V
SY
SY
2
1
= V /2
CM
CM
SY
1
0
0
–1
–2
–3
–4
–1
–2
–3
–4
25°C
85°C
125°C
25°C
85°C
125°C
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
0
2
4
6
8
10
(V)
12
14
16
18
V
V
CM
CM
Figure 19. Input Bias Current vs. Common-Mode Voltage
Figure 22. Input Bias Current vs. Common-Mode Voltage
10000
1000
100
10
10000
1000
100
10
V
= 3V
V
= 18V
SY
SY
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
1
1
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 20. Output Voltage (VOH) to Supply Rail vs. Load Current
Figure 23. Output Voltage (VOH) to Supply Rail vs. Load Current
Rev. 0 | Page 13 of 32
ADA4666-2
Data Sheet
10000
10000
1000
100
10
V
= 3V
V
= 18V
SY
SY
1000
100
10
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
1
1
0.1
0.1
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 24. Output Voltage (VOL) to Supply Rail vs. Load Current
Figure 27. Output Voltage (VOL) to Supply Rail vs. Load Current
3.00
18.00
17.95
17.90
17.85
17.80
17.75
17.70
R
= 10kΩ
L
2.99
2.98
2.97
2.96
2.95
2.94
R
= 10kΩ
L
R = 1kΩ
L
R
= 1kΩ
L
V
= 3V
–25
V
= 18V
–25
SY
SY
–50
0
25
50
75
100
125
–50
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25. Output Voltage (VOH) vs. Temperature
Figure 28. Output Voltage (VOH) vs. Temperature
50
40
30
20
10
0
200
180
160
140
120
100
80
V
= 18V
SY
V
= 3V
SY
R = 1kΩ
L
R
= 1kΩ
L
60
40
R
= 10kΩ
R
= 10kΩ
L
L
20
0
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 26. Output Voltage (VOL) vs. Temperature
Figure 29. Output Voltage (VOL) vs. Temperature
Rev. 0 | Page 14 of 32
Data Sheet
ADA4666-2
1000
1000
900
800
700
600
500
400
300
200
100
0
V
= 3V
V
= 18V
SY
SY
900
800
700
600
500
400
300
200
100
0
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
0
3
6
9
12
15
18
V
V
(V)
CM
CM
Figure 30. Supply Current vs. Common-Mode Voltage
Figure 33. Supply Current vs. Common-Mode Voltage
1000
900
800
700
600
500
400
300
200
100
0
1000
800
600
400
200
0
V
= V /2
SY
V
= V /2
SY
CM
CM
V
V
V
= 3V
= 10V
= 18V
SY
SY
SY
–40°C
+25°C
+85°C
+125°C
0
2
4
6
8
10
(V)
12
14
16
18
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
V
SY
Figure 34. Supply Current vs. Temperature
Figure 31. Supply Current vs. Supply Voltage
80
60
40
20
0
135
80
60
40
20
0
135
V
R
= 18V
V
R
= 3V
SY
L
SY
L
= 10kΩ
= 10kΩ
PHASE
PHASE
90
45
0
90
45
0
GAIN
GAIN
–45
–45
–90
C
= 0pF
C
C
C
C
= 0pF
L
L
L
L
L
L
L
L
C
C
C
= 10pF
= 0pF
= 10pF
= 0pF
= 10pF
= 10pF
–90
10M
–20
10k
–20
10k
100k
FREQUENCY (Hz)
1M
10M
100k
1M
FREQUENCY (Hz)
Figure 32. Open-Loop Gain and Phase vs. Frequency
Figure 35. Open-Loop Gain and Phase vs. Frequency
Rev. 0 | Page 15 of 32
ADA4666-2
Data Sheet
60
60
40
V
C
= 3V
= 5pF
V
= 18V
C = 5pF
L
SY
SY
L
A
= 100
A
= 100
= 10
V
V
40
20
A
= 10
A
V
V
20
A
= 1
A = 1
V
V
0
0
–20
–40
–20
–40
1k
10k
100k
FREQUENCY (Hz)
1M
10M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 36. Closed-Loop Gain vs. Frequency
Figure 39. Closed-Loop Gain vs. Frequency
10k
1k
10k
1k
V
CM
= 3V
V
V
= 18V
SY
= V /2
CM SY
SY
V
= V /2
SY
100
10
100
10
A
= 100
A
= 100
V
V
A
= 10
1
1
V
A
= 10
V
A
= 1
A
= 1
V
V
0.1
0.01
0.1
0.01
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 37. Output Impedance vs. Frequency
Figure 40. Output Impedance vs. Frequency
120
100
80
60
40
20
0
120
100
80
60
40
20
0
V
= 18V
V
CM
= 3V
SY
CM
SY
V
= V /2
V
= V /2
SY
SY
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 38. CMRR vs. Frequency
Figure 41. CMRR vs. Frequency
Rev. 0 | Page 16 of 32
Data Sheet
ADA4666-2
100
80
60
40
20
0
100
V
= 3V
V
= 18V
PSRR+
PSRR–
PSRR+
PSRR–
SY
SY
80
60
40
20
0
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 42. PSRR vs. Frequency
Figure 45. PSRR vs. Frequency
60
50
40
30
20
10
0
60
50
40
30
20
10
0
V
= 3V
V
= 18V
SY
IN
V
L
SY
IN
V
L
V
= 100mV p-p
= 1
V
= 100mV p-p
= 1
A
R
A
R
= 10kΩ
= 10kΩ
OS–
OS+
OS–
OS+
0
10
20
30
40
50
0
10
20
30
40
50
CAPACITANCE (pF)
CAPACITANCE (pF)
Figure 43. Small Signal Overshoot vs. Load Capacitance
Figure 46. Small Signal Overshoot vs. Load Capacitance
V
V
A
R
C
R
= ±9V
= 17V p-p
= 1
= 10kΩ
= 10pF
= 1kΩ
V
V
A
R
C
R
= ±1.5V
= 2.5V p-p
= 1
= 10kΩ
= 10pF
= 1kΩ
SY
IN
V
L
L
S
SY
IN
V
L
L
S
TIME (5µs/DIV)
TIME (5µs/DIV)
Figure 44. Large Signal Transient Response
Figure 47. Large Signal Transient Response
Rev. 0 | Page 17 of 32
ADA4666-2
Data Sheet
V
V
A
R
C
= ±9V
= 100mV p-p
= 1
V
V
A
R
C
= ±1.5V
= 100mV p-p
= 1
SY
IN
SY
IN
V
L
L
V
L
L
= 10kΩ
= 10pF
= 10kΩ
= 10pF
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 48. Small Signal Transient Response
Figure 51. Small Signal Transient Response
0.2
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1
0
18
15
12
9
V
IN
–0.2
–0.4
–0.6
–0.8
–1
V
–1
–2
–3
–4
–5
–6
IN
V
OUT
V
OUT
6
3
V
= ±1.5V
= –10
V
= ±9V
= –10
SY
SY
A
R
C
A
R
C
V
L
L
V
L
L
0
–1.2
–1.4
= 10kΩ
= 10pF
= 225mV
= 10kΩ
= 10pF
= 1.35V
V
V
IN
IN
–0.5
–3
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 49. Positive Overload Recovery
Figure 52. Positive Overload Recovery
0.4
0.2
2.0
2
1
9
V
IN
V
IN
1.5
6
0
1.0
0
3
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
0.5
–1
–2
–3
–4
–5
0
0
–3
–6
–9
–12
–0.5
–1.0
–1.5
–2.0
V
= ±9V
V
= ±1.5V
SY
V
SY
OUT
A
R
C
V
= –10
V
A
R
C
V
= –10
V
L
L
OUT
V
L
L
= 10kΩ
= 10pF
= 1.35V
= 10kΩ
= 10pF
= 225mV
IN
IN
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 50. Negative Overload Recovery
Figure 53. Negative Overload Recovery
Rev. 0 | Page 18 of 32
Data Sheet
ADA4666-2
INPUT
INPUT
OUTPUT
OUTPUT
ERROR BAND
ERROR BAND
V
= ±9V
= 1V p-p
= 10kΩ
= 10pF
= –1
V
V
R
C
A
= ±1.5V
SY
SY
IN
V
R
C
A
= 1V p-p
IN
= 10kΩ
= 10pF
= –1
L
L
V
L
L
V
TIME (400ns/DIV)
TIME (400ns/DIV)
Figure 57. Positive Settling Time to 0.1%
Figure 54. Positive Settling Time to 0.1%
INPUT
INPUT
OUTPUT
OUTPUT
ERROR BAND
ERROR BAND
V
V
R
C
A
= ±1.5V
= 1V p-p
= 10kΩ
= 10pF
= –1
V
V
R
C
A
= ±9V
= 1V p-p
= 10kΩ
= 10pF
= –1
SY
IN
SY
IN
L
L
V
L
L
V
TIME (400ns/DIV)
TIME (400ns/DIV)
Figure 58. Negative Settling Time to 0.1%
Figure 55. Negative Settling Time to 0.1%
1k
1k
100
10
V
CM
A
= 18V
V
= 3V
SY
SY
CM
V
V
= V /2
V
= V /2
SY
SY
= 1
A
= 1
V
100
10
1
1
10
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 59. Voltage Noise Density vs. Frequency
Figure 56. Voltage Noise Density vs. Frequency
Rev. 0 | Page 19 of 32
ADA4666-2
Data Sheet
V
V
= 3V
V
V
= 18V
SY
SY
= V /2
= V /2
CM
SY
CM
SY
A
= 1
A
= 1
V
V
TIME (2s/DIV)
TIME (2s/DIV)
Figure 60. 0.1 Hz to 10 Hz Noise
Figure 63. 0.1 Hz to 10 Hz Noise
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
20
18
16
14
12
10
8
6
V
V
R
C
A
= 3V
= 2.9V
= 10kΩ
= 10pF
= 1
V
V
R
C
A
= 18V
= 17.9V
= 10kΩ
= 10pF
= 1
4
SY
IN
L
L
V
SY
IN
L
L
V
2
0
10
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 61. Output Swing vs. Frequency
Figure 64. Output Swing vs. Frequency
1
1
0.1
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
V
= 3V
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
V
= 18V
SY
V
L
SY
V
L
A
R
V
= 1
A
= 1
= 10kΩ
= 440mV rms
R
V
= 10kΩ
= 5.4V rms
IN
IN
0.1
0.01
0.01
0.001
0.0001
0.001
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 62. THD + N vs. Frequency
Figure 65. THD + N vs. Frequency
Rev. 0 | Page 20 of 32
Data Sheet
ADA4666-2
100
10
100
V
= 18V
V
= 3V
SY
V
L
SY
V
L
A
R
= 1
A
R
= 1
= 10kΩ
= 10kΩ
f = 1kHz
f = 1kHz
10
1
1
0.1
0.1
0.01
0.001
0.0001
0.01
80kHz LOW-PASS FILTER
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
0.001
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
AMPLITUDE (V rms)
AMPLITUDE (V rms)
Figure 66. THD + N vs. Amplitude
Figure 68. THD + N vs. Amplitude
0
–20
0
–20
V
V
V
= 0.5V p-p
= 1.5V p-p
= 2.9V p-p
V
V
V
= 0.5V p-p
IN
IN
IN
IN
IN
IN
= 9V p-p
= 17.9V p-p
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
V
= 3V
= 100
V
= 18V
= 100
SY
SY
A
R
A
V
L
V
= 10kΩ
R
= 10kΩ
L
500kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
10
100
1k
10k 100k
10
100
1k
10k 100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 67. Channel Separation vs. Frequency
Figure 69. Channel Separation vs. Frequency
Rev. 0 | Page 21 of 32
ADA4666-2
Data Sheet
APPLICATIONS INFORMATION
V+
M19
M17
M20
M18
HIGH VOLTAGE PROTECTION
I2
M11
M9
M12
M10
M22
C2
C3
+IN x
–IN x
R1
R2
C1
M3 M4
Q1
Q2
OUT x
D1
D2
V1
M1 M2
M7
M5
M8
M6
M21
M15
M13
M16
M14
I1
I3
HIGH VOLTAGE PROTECTION
V–
Figure 70. Simplified Schematic
The ADA4666-2 is a low power, rail-to-rail input and output,
CMOS amplifier that operates over a wide supply voltage range
of 3 V to 18 V. To achieve a rail-to-rail input and output range
with very low supply current, the ADA4666-2 uses unique input
and output stages.
For most of the input common-mode voltage range, the PMOS
differential pair is active. When the input common-mode
voltage is within a few volts of the power supplies, the input
transistors are exposed to these voltage changes. As the
common-mode voltage approaches the positive power supply,
the active differential pair changes from the PMOS pair to the
NMOS pair. Differential pairs commonly exhibit different offset
voltages. The handoff of control from one differential pair to the
other creates a step like characteristic that is visible in the VOS vs.
INPUT STAGE
Figure 70 shows the simplified schematic of the ADA4666-2.
The amplifier uses a three-stage architecture with a fully
differential input stage to achieve excellent dc performance
specifications.
VCM graphs (see Figure 8, Figure 11, Figure 12, Figure 13, Figure 15,
and Figure 16). This characteristic is inherent in all rail-to-rail
input amplifiers that use the dual differential pair topology.
The input stage comprises two differential transistor pairs—a
NMOS pair (M1, M2), a PMOS pair (M3, M4)—and folded-
cascode transistors (M5 to M12). The input common-mode
voltage determines which differential pair is active. The PMOS
differential pair is active for most of the input common-mode
range. The NMOS pair is required for input voltages up to and
including the upper supply rail. This topology allows the
amplifier to maintain a wide dynamic input voltage range and
maximize signal swing to both supply rails.
Additional steps in the VOS vs. VCM graphs are visible as the
common-mode voltage approaches the negative power supply.
These changes are a result of the load transistors (M5, M6)
running out of headroom. As the load transistors are forced into
the triode region of operation, the mismatch of their drain
impedance becomes a significant portion of the amplifier offset.
This effect can also be seen in the VOS vs. VCM graphs (see Figure 8,
Figure 11, Figure 12, Figure 13, Figure 15, and Figure 16).
The proprietary high voltage protection circuitry in the
ADA4666-2 minimizes the common-mode voltage changes
seen by the amplifier input stage for most of the input common-
mode range. This results in the amplifier having excellent
disturbance rejection when operating in this preferred
common-mode range. The performance benefits of operating
within this preferred range are shown in the PSRR vs. VCM (see
Figure 17), CMRR vs. VCM (see Figure 14) and VOS vs. VCM
graphs (see Figure 8, Figure 11, Figure 12, Figure 13, Figure 15,
and Figure 16). The CMRR performance benefits of the reduced
common-mode range are guaranteed at final test and shown in the
electrical characteristics (see Table 2 to Table 4).
Current Source I2 drives the PMOS transistor pair. As the input
common-mode voltage approaches the upper power supply,
this current is reduced to zero. At the same time, a replica
current source, I1, is increased from zero to enable the NMOS
transistor pair.
The ADA4666-2 achieves its high performance specifications by
using low voltage MOS devices for its differential inputs. These
low voltage MOS devices offer excellent noise and bandwidth
per unit of current. The input stage is isolated from the high
system voltages with proprietary protection circuitry. This regu-
lation circuitry protects the input devices from the high supply
voltages at which the amplifier can operate.
Rev. 0 | Page 22 of 32
Data Sheet
ADA4666-2
The input devices are also protected from large differential
input voltages by clamp diodes (D1 and D2). These diodes are
buffered from the inputs with two 120 Ω resistors (R1 and R2).
The diodes conduct significant current whenever the differential
voltage exceeds approximately 600 mV; in this condition, the
differential input resistance falls to 240 Ω. It is possible for a
significant amount of current to flow through these protection
diodes. The user must ensure that current flowing into the input
pins is limited to the absolute maximum of 10 mA.
Do not exceed the maximum junction temperature for the
device, 150°C. Exceeding the junction temperature limit can
cause degradation in the parametric performance or even
destroy the device. To ensure proper operation, it is necessary to
observe the maximum power derating curves. Figure 71 shows
the maximum safe power dissipation in the package vs. the
ambient temperature on a standard 4-layer JEDEC board. The
exposed pad of the LFCSP package is soldered to the board.
1.6
T
= 150°C
J MAX
GAIN STAGE
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
The second stage of the amplifier is composed of an NPN
differential pair (Q1,Q2) and folded cascode transistors (M13
to M20). The amplifier features nested Miller compensation
(C1 to C3).
8-LEAD LFCSP
= 83.5°C/W
θ
JA
OUTPUT STAGE
8-LEAD MSOP
= 142°C/W
θ
JA
The ADA4666-2 features a complementary output stage
consisting of the M21 and M22 transistors. These transistors are
configured in a Class AB topology and are biased by the voltage
source, V1. This topology allows the output voltage to go within
millivolts of the supply rails, achieving a rail-to-rail output
swing. The output voltage is limited by the output impedance of
the transistors, which are low RON MOS devices. The output
voltage swing is a function of the load current and can be
estimated using the output voltage to the supply rail vs. load
current graphs (see Figure 20, Figure 23, Figure 24, and Figure 27).
The high voltage and high current capability of the ADA4666-2
output stage requires the user to ensure that it operates within
the thermal safe operating area (see the Maximum Power
Dissipation section).
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
Figure 71. Maximum Power Dissipation vs. Ambient Temperature
Refer to Technical Article MS-2251, Data Sheet Intricacies—
Absolute Maximum Ratings and Thermal Resistances, for more
information.
RAIL-TO-RAIL INPUT AND OUTPUT
The ADA4666-2 features rail-to-rail input and output with a
supply voltage from 3 V to 18 V. Figure 72 shows the input and
output waveforms of the ADA4666-2 configured as a unity-gain
buffer with a supply voltage of 9 V. With an input voltage of
9 V, t h e ADA4666-2 allows the output to swing very close to
both rails. Additionally, it does not exhibit phase reversal.
10
MAXIMUM POWER DISSIPATION
The ADA4666-2 is capable of driving an output current up to
220 mA. However, the usable output load current drive is
limited to the maximum power dissipation allowed by the
device package. The absolute maximum junction temperature
for the ADA4666-2 is 150°C (see Table 5). The junction
temperature can be estimated as follows:
V
V
IN
OUT
8
6
4
TJ = PD × θJA + TA
2
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated by the
output stage transistor. It can be calculated as follows:
0
–2
–4
–6
–8
–10
PD = (VSY × ISY) + (VSY − VOUT) × ILOAD
V
V
A
R
C
= ±9V
= ±9V
= 1
SY
IN
where:
V
L
L
V
I
V
I
SY is the power supply rail.
SY is the quiescent current.
OUT is the output of the amplifier.
LOAD is the output load.
= 10kΩ
= 10pF
TIME (200µs/DIV)
Figure 72. Rail-to-Rail Input and Output
Rev. 0 | Page 23 of 32
ADA4666-2
Data Sheet
Figure 75 and Figure 76 show the ADA4666-2 configured as a
comparator, with 100 kΩ resistors in series with the input pins.
Any unused channels are configured as buffers with the input
voltage kept at the midpoint of the power supplies.
COMPARATOR OPERATION
An op amp is designed to operate in a closed-loop configuration
with feedback from its output to its inverting input. Figure 73
shows the ADA4666-2 configured as a voltage follower with an
input voltage that is always kept at the midpoint of the power
supplies. The same configuration is applied to the unused
channel. A1 and A2 indicate the placement of ammeters to
measure supply current. ISY+ refers to the current flowing from
the upper supply rail to the op amp, and ISY− refers to the
current flowing from the op amp to the lower supply rail. As
shown in Figure 74, in normal operating conditions, the total
current flowing into the op amp is equivalent to the total current
flowing out of the op amp, where ISY+ = ISY− = 630 μA per amplifier
at VSY = 18 V.
+V
SY
A1
I
+
SY
100kΩ
100kΩ
ADA4666-2
V
OUT
1/2
A2
I
–
SY
+V
SY
–V
SY
Figure 75. Comparator A
A1
I
+
SY
+V
SY
A1
I
+
SY
100kΩ
100kΩ
ADA4666-2
V
OUT
1/2
100kΩ
ADA4666-2
V
OUT
A2
I
–
SY
1/2
100kΩ
A2
I
–
SY
–V
SY
Figure 73. Voltage Follower
700
600
500
400
300
200
100
0
–V
SY
Figure 76. Comparator B
Figure 77 shows the supply currents for both comparator
configurations. In comparator mode, the ADA4666-2 does not
power up completely. For more information about configuring
using op amps as comparators, see the AN-849 Application
Note, Using Op Amps as Comparators.
700
600
500
0
2
4
6
8
10
(V)
12
14
16
18
COMPARATOR A
400
V
SY
COMPARATOR B
Figure 74. Supply Current vs. Supply Voltage (Voltage Follower)
300
In contrast to op amps, comparators are designed to work in an
open-loop configuration and to drive logic circuits. Although
op amps are different from comparators, occasionally an unused
section of a dual op amp is used as a comparator to save board
space and cost; however, this is not recommended for the
ADA4666-2.
200
100
0
0
2
4
6
8
10
(V)
12
14
16
18
V
SY
Figure 77. Supply Current vs. Supply Voltage (ADA4666-2 as a Comparator)
Rev. 0 | Page 24 of 32
Data Sheet
ADA4666-2
Figure 79 shows a low-side current sensing circuit, and Figure 80
shows a high-side current sensing circuit. Current flowing
through the shunt resistor creates a voltage drop. The ADA4666-2,
configured as a difference amplifier, amplifies the voltage drop
by a factor of R2/R1. Note that for true difference amplification,
matching of the resistor ratio is very important, where R2/R1 =
R4/R3. The rail-to-rail output feature of the ADA4666-2 allows
the output of the op amp to almost reach its positive supply.
This allows the current shunt monitor to sense up to approximately
VSY/(R2/R1 × RS) amperes of current. For example, with VSY =
18 V, R2/R1 = 100, and RS = 100 mΩ, this current is approxi-
mately 1.8 A.
EMI REJECTION RATIO
Circuit performance is often adversely affected by high frequency
electromagnetic interference (EMI). When the signal strength is
low and transmission lines are long, an op amp must accurately
amplify the input signals. However, all op amp pins—the
noninverting input, inverting input, positive supply, negative
supply, and output pins—are susceptible to EMI signals. These
high frequency signals are coupled into an op amp by various
means, such as conduction, near field radiation, or far field
radiation. For instance, wires and PCB traces can act as antennas
and pick up high frequency EMI signals.
Amplifiers do not amplify EMI or RF signals due to their
relatively low bandwidth. However, due to the nonlinearities of
the input devices, op amps can rectify these out-of-band signals.
When these high frequency signals are rectified, they appear as
a dc offset at the output.
I
R
SUPPLY
L
R
S
I
R1
R2
V
*
OUT
V
SY
To describe the ability of the ADA4666-2 to perform as
intended in the presence of electromagnetic energy, the
electromagnetic interference rejection ratio (EMIRR) of the
noninverting pin is specified in Table 2, Table 3, and Table 4 of
the Specifications section. A mathematical method of
measuring EMIRR is defined as follows:
1/2
ADA4666-2
R3
R4
*V
= AMPLIFIER GAIN × VOLTAGE ACROSS R = R2/R1 × R × I
OUT
S
S
Figure 79. Low-Side Current Sensing Circuit
R
S
I
EMIRR = 20 log (VIN_PEAK/ΔVOS)
140
R
SUPPLY
L
I
V
= 3V TO 18V
SY
R3
R4
120
100
80
V
SY
V
*
1/2
OUT
ADA4666-2
R1
R2
*V
= AMPLIFIER GAIN × VOLTAGE ACROSS R = R2/R1 × R × I
OUT
S
S
60
Figure 80. High-Side Current Sensing Circuit
V
V
= 100mV PEAK
= 50mV PEAK
IN
IN
ACTIVE FILTERS
40
Active filters are used to separate signals, passing those of
interest and attenuating signals at unwanted frequencies. For
example, low-pass filters are often used as antialiasing filters in
data acquisition systems or as noise filters to limit high
frequency noise.
20
10M
100M
1G
10G
FREQUENCY (Hz)
Figure 78. EMIRR vs. Frequency
CURRENT SHUNT MONITOR
The high input impedance, high bandwidth, low input bias
current, and dc precision of the ADA4666-2 make it a good fit
for active filters application. Figure 81 shows the ADA4666-2 in
a four-pole Sallen-Key Butterworth low-pass filter configuration.
The four-pole low-pass filter has two complex conjugate pole
pairs and is implemented by cascading two two-pole low-pass
filters. Section A and Section B are configured as two-pole low-
pass filters in unity gain. Table 8 shows the Q requirement and
pole position associated with each stage of the Butterworth
filter. Refer to Chapter 8, “Analog Filters,” in Linear Circuit
Design Handbook, available at www.analog.com/AnalogDialogue,
for pole locations on the S plane and Q requirements for filters
of a different order.
Many applications require the sensing of signals near the
positive or negative rail. Current shunt monitors are one such
application and are mostly used for feedback control systems.
They are also used in a variety of other applications, including
power metering, battery fuel gauging, and feedback controls in
electrical power steering. In such applications, it is desirable to
use a shunt with very low resistance to minimize the series
voltage drop. This not only minimizes wasted power but also
allows the measurement of high currents while saving power.
The low input bias current, low offset voltage, and rail-to-rail
feature of the ADA4666-2 makes the amplifier an excellent
choice for precision current monitoring.
Rev. 0 | Page 25 of 32
ADA4666-2
Data Sheet
C2
6.8nF
C4
6.8nF
R1
R2
+V
SY
2.55kΩ 2.55kΩ
R3
R4
+V
V
SY
IN
6.19kΩ 6.19kΩ
1/2
C1
5.6nF
V
V
OUT2
OUT1
1/2
ADA4666-2
C3
1nF
–V
ADA4666-2
SY
–V
SY
SECTION A
SECTION B
Figure 81. Four-Pole Low-Pass Filter
CAPACITIVE LOAD DRIVE
Table 8. Q Requirements and Pole Positions
The ADA4666-2 can safely drive capacitive loads of up to 50 pF
in any configuration. As with most amplifiers, driving larger
capacitive loads than specified may cause excessive overshoot
and ringing, or even oscillation. Heavy capacitive load reduces
phase margin and causes the amplifier frequency response to
peak. Peaking corresponds to overshooting or ringing in the
time domain. Therefore, it is recommended that external
compensation be used if the ADA4666-2 must drive a load
exceeding 50 pF. This compensation is particularly important in
the unity-gain configuration, which is the worst case for
stability.
Section
Poles
Q
A
B
−0.9239 j0.3827
−0.3827 j0.9239
0.5412
1.3065
The Sallen-Key topology is widely used due to its simple design
with few circuit elements. This topology provides the user the
flexibility of implementing either a low-pass or a high-pass filter
by simply interchanging the resistors and capacitors. The
ADA4666-2 is configured in unity gain with a corner frequency
at 10 kHz. An active filter requires an op amp with a unity-gain
bandwidth that is at least 100 times greater than the product of
the corner frequency, fC, and the quality factor, Q. The resistors
and capacitors are also important in determining the perfor-
mance over manufacturing tolerances, time, and temperature.
At least 1% or better tolerance resistors and 5% or better
tolerance capacitors are recommended.
A quick and easy way to stabilize the op amp for capacitive load
drive is by adding a series resistor, RISO, between the amplifier
output terminal and the load capacitance, as shown in Figure 83.
RISO isolates the amplifier output and feedback network from
the capacitive load. However, with this compensation scheme,
the output impedance as seen by the load increases, and this
reduces gain accuracy.
Figure 82 shows the frequency response of the low-pass Sallen-
Key filter, where:
V
OUT1 is the output of the first stage.
+V
SY
VOUT2 is the output of the second stage.
R
ISO
V
OUT
1/2
VOUT1 shows a 40 dB/decade roll-off and VOUT2 shows an
80 dB/decade roll-off. The transition band becomes sharper as
the order of the filter increases.
V
IN
ADA4666-2
SY
C
L
–V
20
Figure 83. Stability Compensation with Isolating Resistor, RISO
Figure 84 shows the effect of the compensation scheme on the
frequency response of the amplifier in unity-gain configuration
driving 250 pF of load.
0
–20
V
1
OUT
–40
–60
V
2
OUT
–80
–100
V
V
= ±9V
SY
IN
= 50mV p-p
–120
100
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 82. Low-Pass Filter: Gain vs. Frequency
Rev. 0 | Page 26 of 32
Data Sheet
ADA4666-2
10
0
–10
–20
–30
V
V
A
C
R
= ±9V
SY
IN
V
= 100mV p-p
= 1
R
R
R
R
= 0Ω
–40
–50
ISO
ISO
ISO
ISO
= 210Ω
= 301Ω
= 499Ω
= 250pF
L
= 301Ω
ISO
TIME (10µs/DIV)
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 87. Output Response (RISO = 301 Ω)
Figure 84. Frequency Response of Compensation Scheme
Figure 85 shows the output response of the unity-gain amplifier
driving 250 pF of capacitive load. With no compensation, the
amplifier is unstable. Figure 86 to Figure 88 show the amplifier
output response with 210 Ω, 301 Ω, and 750 Ω of RISO
compensation. Note that with lower RISO values, ringing is still
noticeable, whereas with higher RISO values, higher frequency
signals are filtered out.
V
V
A
C
R
= ±9V
SY
IN
V
= 100mV p-p
= 1
= 250pF
L
= 750Ω
ISO
TIME (10µs/DIV)
Figure 88. Output Response (RISO = 750 Ω)
V
V
A
C
R
= ±9V
SY
IN
V
= 100mV p-p
= 1
= 250pF
L
= 0Ω
ISO
TIME (10µs/DIV)
Figure 85. Output Response with No Compensation (RISO = 0 Ω)
V
V
A
C
R
= ±9V
SY
IN
V
= 100mV p-p
= 1
= 250pF
L
= 210Ω
ISO
TIME (10µs/DIV)
Figure 86. Output Response (RISO = 210 Ω)
Rev. 0 | Page 27 of 32
ADA4666-2
Data Sheet
10
NOISE CONSIDERATIONS WITH HIGH IMPEDANCE
SOURCES
Current noise from input terminals can become a dominant
contributor to the total circuit noise when an amplifier is driven
with a high impedance source. Unlike bipolar amplifiers,
CMOS amplifiers like the ADA4666-2 do not have an intrinsic
shot noise source at the input terminals. The small amount of
shot noise present is produced by the reverse saturation current
in the ESD protection diodes. This current noise is typically on
the order of 1 fA/√Hz to 10 fA/√Hz. Therefore, to measure
current noise in this range, a large source impedance of greater
than 10 GΩ is required.
1
R
= 10MΩ
S
R
= 1MΩ
S
0.1
0.01
0.1
1
10
100
1k
10k
100k
For the ADA4666-2, the more relevant discussion centers
around an effect referred to as blowback noise. The blowback
effect comes from noise in the tail current source of the
amplifier, which is capacitively coupled to the amplifier inputs
through the gate-to-source capacitance (CGS) of the input
transistors. This blowback noise is multiplied by the source
impedance and appears as voltage noise at the input terminal. A
10× increase in the source impedance results in a 10× increase
in the voltage noise due to blowback.
FREQUENCY (Hz)
Figure 89. Voltage Noise Density vs. Frequency (with Input Series Resistor, RS)
1
NOISE BANDWIDTH
LIMITATION
R
R
= 1MΩ
= 10MΩ
S
S
0.1
The blowback noise spectrum has a high-pass response at low
frequencies due to CGS coupling. At high frequencies, the
spectrum tends to roll off with two poles: an internal pole due
to parasitic capacitances of the tail current source and an
external pole due to parasitic capacitances on the PCB.
NOISE MEASUREMENT
LIMITATION
0.01
Figure 89 shows the voltage noise density of the ADA4666-2
with source impedances of 1 MΩ and 10 MΩ. At low
frequencies (<1 Hz to 10 Hz), the amplifier 1/f voltage noise
dominates the spectrum. At moderate frequencies, the
spectrum flattens due to the thermal noise of the source
resistors. As the frequency increases, blowback noise dominates
and causes the voltage noise spectrum to increase. The noise
spectrum continues to increase until it reaches either the
internal or external pole frequency. After these poles, the
spectrum starts to decrease.
0.01
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 90. Current Noise Density vs. Frequency
Figure 90 shows the current noise density of the ADA4666-2
with source impedances of 1 MΩ and 10 MΩ. This current
noise is extracted only from the voltage noise density curves in
the frequency band where blowback noise is the dominant
contributor. At low frequencies, the noise measurement is
dominated by resistor thermal noise and amplifier 1/f noise. At
high frequencies, parasitic capacitances dominate the source
impedance. The uncertainty of this scale factor prevents an
accurate current noise measurement for the entire frequency
range.
Blowback noise is present in all amplifiers. The magnitude of
the effect depends on the size of the input transistors and the
construction of the biasing circuitry. CMOS amplifiers typically
have more blowback noise than JFET amplifiers due to noisier
MOS transistor biasing. On the other hand, bipolar amplifiers
typically do not exhibit blowback noise because the large base
current shot noise masks any blowback noise present.
Rev. 0 | Page 28 of 32
Data Sheet
ADA4666-2
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 91. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
2.44
2.34
2.24
3.10
3.00 SQ
0.50 BSC
2.90
8
5
PIN 1 INDEX
EXPOSED
PAD
1.70
1.60
1.50
AREA
0.50
0.40
0.30
0.20 MIN
4
1
PIN 1
TOP VIEW
BOTTOM VIEW
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
Figure 92. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Package Option
CP-8-11
CP-8-11
RM-8
RM-8
RM-8
Branding
A34
A34
A34
A34
ADA4666-2ACPZ-R7
ADA4666-2ACPZ-RL
ADA4666-2ARMZ
ADA4666-2ARMZ-RL
ADA4666-2ARMZ-R7
A34
1 Z = RoHS Compliant Part.
Rev. 0 | Page 29 of 32
ADA4666-2
NOTES
Data Sheet
Rev. 0 | Page 30 of 32
Data Sheet
NOTES
ADA4666-2
Rev. 0 | Page 31 of 32
ADA4666-2
NOTES
Data Sheet
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11382-0-7/13(0)
Rev. 0 | Page 32 of 32
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