ADA4805-2ACPZ-R2 [ADI]
Dual, 0.2 µV/°C Offset Drift, 105 MHz Low Power, Low Noise, Rail-to-Rail Amplifier;
| 型号： | ADA4805-2ACPZ-R2 |
| 厂家： | 
ADI |
| 描述： | Dual, 0.2 µV/°C Offset Drift, 105 MHz Low Power, Low Noise, Rail-to-Rail Amplifier 放大器 光电二极管 |
| 文件： | 总25页 (文件大小：830K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.2 µV/°C Offset Drift, 105 MHz Low Power,
Low Noise, Rail-to-Rail Amplifiers
ADA4805-1/ADA4805-2
Data Sheet
FEATURES
TYPICAL APPLICATIONS CIRCUIT
+7.5V
Low input offset voltage: 125 µV (maximum)
Low input offset voltage drift
5V REF
ADA4805-1/
ADA4805-2
ADR435
VDD
0.2 µV/°C (typical)
1.5 µV/°C (maximum)
C4
100nF
C2
10µF
C3
0.1µF
Ultralow supply current: 500 µA per amplifier
Fully specified at VS = 3 V, 5 V, 5 V
High speed performance
−3 dB bandwidth: 105 MHz
Slew rate: 160 V/µs
+7.5V
ADA4805-1/
0V TO
REF
ADA4805-2
REF VDD
V
IN+
IN–
R3
20Ω
AD7980
GND
Settling time to 0.1%: 35 ns
Rail-to-rail outputs
C1
2.7nF
Input common-mode range: −VS − 0.1 V to +VS − 1 V
Low noise: 5.9 nV/√Hz at 100 kHz; 0.6 pA/√Hz at 100 kHz
Low distortion: −102 dBc/−126 dBc HD2/HD3 at 100 kHz
Low input bias current: 470 nA (typical)
Dynamic power scaling
Turn-on time: 3 µs (maximum) fully settled
Small packaging
6-lead SC70, 6-lead SOT-23, and 8-lead MSOP
Figure 1. Driving the AD7980 with the ADA4805-1/ADA4805-2
The Analog Devices, Inc., proprietary extra fast complementary
bipolar (XFCB) process allows both low voltage and low current
noise (5.9 nV/√Hz, 0.6 pA/√Hz). The ADA4805-1/ADA4805-2
operate over a wide range of supply voltages from 1.5 V to
5 V, as well as single 3 V and 5 V supplies, making them ideal
for high speed, low power instruments.
The ADA4805-1 is available in a 6-lead SOT-23 and a 6-lead
SC70 package. The ADA4805-2 is available in an 8-lead MSOP
and a 10-lead LFCSP package. These amplifiers are rated to
work over the industrial temperature range of −40°C to +125°C.
APPLICATIONS
High resolution, high precision analog-to-digital converter
(ADC) drivers
Battery-powered instrumentation
Micropower active filters
Portable point of sales terminals
Active RFID readers
0
INPUT FREQUENCY = 10kHz
SNR = 89.4dB
–20
THD = 104dB
SINAD = 89.3dB
–40
Photo multipliers
ADC reference buffers
–60
–80
GENERAL DESCRIPTION
–100
–120
–140
–160
–180
The ADA4805-1/ADA4805-2 are high speed voltage feedback,
rail-to-rail output amplifiers with an exceptionally low
quiescent current of 500 µA, making them ideal for low power,
high resolution data conversion systems. Despite being low
power, these amplifiers provide excellent overall performance.
They offer a high bandwidth of 105 MHz at a gain of +1, a high
slew rate of 160 V/µs, and a low input offset voltage of 125 µV
(maximum).
0
10
20
30
40
50
60
70
80
FREQUENCY (kHz)
Figure 2. FFT Plot for the Circuit Configuration in Figure 1
Table 1. Complementary ADCs to the ADA4805-1/ADA4805-2
A shutdown pin allows further reduction of the quiescent
supply current to 2.9 µA. For power sensitive applications, the
shutdown mode offers a very fast turn-on time of 3 µs. This
allows the user to dynamically manage the power of the
amplifier by turning the amplifier off between ADC samples.
Throughput Resolution SNR
Product ADC Power (mW) (MSPS)
(Bits)
(dB)
AD7982
AD7984
AD7980
AD7685
7.0
10.5
4.0
10
1
1.33
1
18
18
16
16
98
98.5
91
0.25
88
Rev. B
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ADA4805-1/ADA4805-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Amplifier Description................................................................ 18
Input Protection ......................................................................... 18
Shutdown Operation.................................................................. 18
Noise Considerations................................................................. 19
Applications Information.............................................................. 20
Slew Enhancement..................................................................... 20
Effect of Feedback Resistor on Frequency Response ............ 20
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Applications Circuit............................................................ 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
±± ꢀ Supply................................................................................... 3
± ꢀ Supply...................................................................................... 4
3 ꢀ Supply...................................................................................... ±
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 10
Test Circuits..................................................................................... 17
Theory of Operation ...................................................................... 18
REVISION HISTORY
Compensating Peaking in Large Signal Frequency Response
....................................................................................................... 20
Driving Low Power, High Resolution Successive
Approximation Register (SAR) ADCs..................................... 20
Dynamic Power Scaling............................................................. 21
Single-Ended to Differential Conversion ................................... 23
Layout Considerations............................................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 2±
12/14—Rev. A to Rev. B
Changes to Figure 7 Caption, Figure 8 Caption, Figure 9
Added 10-Lead LFCSP....................................................... Universal
Caption, Figure 10 Caption, and Figure 11 Caption.....................9
Changes to Figure 13 Caption, Figure 14, Figure 17, and
SHUTDOWN
SHUTDOWN
SHUTDOWN
Changes to
Changes to
Changes to
Current Parameter, Table 2................3
Current Parameter, Table 3................±
Current Parameter, Table 4................6
Figure 18 ...........................................................................................10
Change to Figure 29 ........................................................................12
Moved Figure 41..............................................................................1±
Changes to Figure 42.......................................................................1±
Added Figure 43 ..............................................................................1±
Changes to Figure 47 and Figure 48..............................................16
Changes to Amplifier Description Section, Input Protection
Section, Shutdown Operation Section, and Figure ±1................17
Changes to Noise Considerations Section and Figure ±2 ..........18
Changes to Effect of Feedback Resistor on Frequency Response
Section, Compensating Peaking in Large Signal Frequency
Response Section, Figure ±7, and Driving Low Power, High
Resolution Successive Approximation Register (SAR) ADC
Section...............................................................................................19
Changes to Figure ±8, Dynamic Power Scaling Section,
Changes to Table 6 and Figure 3......................................................7
Changes to Table 8.............................................................................9
Added Figure 6, Renumbered Sequentially ...................................9
Added Figure 42...............................................................................16
Changed Layout...............................................................................16
Changes to Shutdown Operation Section ....................................18
Changes to Dynamic Power Scaling Section and Figure 61 ......21
Changes to Figure 62 and Figure 63..............................................22
Updated Outline Dimensions........................................................2±
Changes to Ordering Guide ...........................................................2±
9/14—Rev. 0 to Rev. A
Added ADA480±-2............................................................. Universal
Changes to Features Section, General Description Section, and
Table 1 .................................................................................................1
Changes to Table 2.............................................................................3
Changes to Table 3.............................................................................4
Changes to Table 4.............................................................................±
Changes to Table 6 and Figure 3......................................................7
Added Figure 6; Renumbered Sequentially; and Table 8;
Renumbered Sequentially.................................................................8
Figure ±9, and Table 10...................................................................20
Change to Figure 60 ........................................................................21
Changes to Single-Ended to Differential Conversion Section,
Table 11, and Figure 62...................................................................22
Updated Outline Dimensions, Figure 6± .....................................24
Changes to Ordering Guide...........................................................24
7/14—Revision 0: Initial Version
Rev. B | Page 2 of 25
Data Sheet
ADA4805-1/ADA4805-2
SPECIFICATIONS
5 V SUPPLY
VS = 5 V at TA = 25°C; RF = 0 Ω for G = +1; otherwise, RF = 1 kΩ; RL = 2 kΩ to ground; unless otherwise noted. All specifications are per
amplifier.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VOUT = 0.02 V p-p
G = +1, VOUT = 2 V p-p
G = +1, VOUT = 0.02 V p-p
G = +1, VOUT = 2 V step
G = +2, VOUT = 4 V step
G = +1, VOUT = 2 V step
G = +2, VOUT = 4 V step
120
40
18
190
250
35
MHz
MHz
MHz
V/µs
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
78
ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion, HD2/HD31
fC = 20 kHz, VOUT = 2 V p-p
−114/−140
−102/−128
−109/−143
−93/−130
−113/−142
−96/−130
5.2
8
44
0.7
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
Hz
nV rms
pA/√Hz
fC = 100 kHz, VOUT = 2 V p-p
fC = 20 kHz, VOUT = 4 V p-p, G = +1
fC = 100 kHz, VOUT = 4 V p-p, G = +1
fC = 20 kHz, VOUT = 4 V p-p, G = +2
fC = 100 kHz, VOUT = 4 V p-p, G = +2
f = 100 kHz
Input Voltage Noise
Input Voltage Noise 1/f Corner Frequency
0.1 Hz to 10 Hz Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift2
Input Bias Current
Input Offset Current
Open-Loop Gain
f = 100 kHz
13
125
1.5
800
25
µV
µV/°C
nA
nA
dB
TMIN to TMAX, 4 σ
VOUT = −4.0 V to +4.0 V
0.2
550
2.1
111
107
INPUT CHARACTERISTICS
Input Resistance
Common Mode
Differential Mode
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
SHUTDOWN PIN
50
260
1
MΩ
kΩ
pF
V
−5.1
103
+4
VIN, CM = −4.0 V to +4.0 V
130
dB
SHUTDOWN Voltage
Low
High
Powered down
Enabled
<−1.3
>−0.9
V
V
SHUTDOWN Current
Low
High
Powered down
Enabled
50% of SHUTDOWN to <10% of enabled
quiescent current
−1.0
0.2
0.02
1.25
µA
µA
µs
1.0
2.75
Turn-Off Time
Turn-On Time
50% of SHUTDOWN to >90% of final VOUT
2
3
µs
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
Output Voltage Swing
VIN = +6 V to −6 V, G = +2
95/100
ns
V
RL = 2 kΩ
−4.98
+4.98
Rev. B | Page 3 of 25
ADA4805-1/ADA4805-2
Data Sheet
Parameter
Test Conditions/Comments
Sinking/sourcing
<1% THD at 100 kHz, VOUT = 2 V p-p
VIN = 0.5 V p-p, f = 1 MHz, SHUTDOWN = −VS
30% overshoot
Min
Typ
85/73
58
Max
Unit
mA
mA
dB
Short-Circuit Current
Linear Output Current
Off Isolation
41
Capacitive Load Drive
POWER SUPPLY
15
pF
Operating Range
2.7
10
V
Quiescent Current per Amplifier
Enabled
SHUTDOWN = −VS
570
7.4
625
12
µA
µA
Power Supply Rejection Ratio
Positive
Negative
+VS = 3 V to 5 V, −VS = −5 V
+VS = 5 V, −VS = −3 V to −5 V
100
100
119
122
dB
dB
1 fC is the fundamental frequency.
2 Guaranteed, but not tested.
5 V SUPPLY
VS = 5 V at TA = 25°C; RF = 0 Ω for G = +1; otherwise, RF = 1 kΩ; RL = 2 kΩ to midsupply; unless otherwise noted. All specifications are
per amplifier.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VOUT = 0.02 V p-p
G = +1, VOUT = 2 V p-p
G = +1, VOUT = 0.02 V p-p
G = +1, VOUT = 2 V step
G = +2, VOUT = 4 V step
G = +1, VOUT = 2 V step
G = +2, VOUT = 4 V step
105
35
20
160
220
35
MHz
MHz
MHz
V/µs
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
82
ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion, HD2/HD31
fC = 20 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 20 kHz, G = +2, VOUT = 4 V p-p
fC = 100 kHz, G = +2, VOUT = 4 V p-p
f = 100 kHz
−114/−135
−102/−126
−107/−143
−90/−130
5.9
8
54
0.6
dBc
dBc
dBc
dBc
nV/√Hz
Hz
nV rms
pA/√Hz
Input Voltage Noise
Input Voltage Noise 1/f Corner
0.1 Hz to 10 Hz Voltage Noise
Input Current Noise
f = 100 kHz
DC PERFORMANCE
Input Offset Voltage
9
125
1.5
720
µV
µV/°C
nA
nA
dB
Input Offset Voltage Drift2
TMIN to TMAX, 4 σ
VOUT = 1.25 V to 3.75 V
0.2
470
0.4
109
Input Bias Current
Input Offset Current
Open-Loop Gain
105
INPUT CHARACTERISTICS
Input Resistance
Common Mode
Differential Mode
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
50
260
1
MΩ
kΩ
pF
V
−0.1
103
+4
VIN, CM = 1.25 V to 3.75 V
133
dB
Rev. B | Page 4 of 25
Data Sheet
ADA4805-1/ADA4805-2
Parameter
SHUTDOWN PIN
SHUTDOWN Voltage
Low
Test Conditions/Comments
Min
Typ
Max
Unit
Powered down
Enabled
<1.5
>1.9
V
V
High
SHUTDOWN Current
Low
High
Powered down
Enabled
50% of SHUTDOWN to <10% of enabled
quiescent current
−1.0
0.1
0.01
0.9
µA
µA
µs
1.0
1.25
Turn-Off Time
Turn-On Time
50% of SHUTDOWN to >90% of final VOUT
3
4
µs
ns
OUTPUT CHARACTERISTICS
Overdrive Recovery Time (Rising/Falling
Edge)
VIN = −1 V to +6 V, G = +2
130/145
Output Voltage Swing
Short-Circuit Current
Linear Output Current
Off Isolation
RL = 2 kΩ
Sinking/sourcing
<1% THD at 100 kHz, VOUT = 2 V p-p
VIN = 0.5 V p-p, f = 1 MHz, SHUTDOWN = −VS
30% overshoot
0.02
2.7
4.98
V
73/63
47
41
mA
mA
dB
pF
Capacitive Load Drive
POWER SUPPLY
Operating Range
15
10
520
4
V
µA
µA
Quiescent Current per Amplifier
Enabled
SHUTDOWN = −VS
500
2.9
Power Supply Rejection Ratio
Positive
Negative
+VS = 1.5 V to 3.5 V, −VS = −2.5 V
+VS = 2.5 V, −VS = −1.5 V to −3.5 V
100
100
120
126
dB
dB
1 fC is the fundamental frequency.
2 Guaranteed, but not tested.
3 V SUPPLY
VS = 3 V at TA = 25°C; RF = 0 Ω for G = +1; otherwise, RF = 1 kΩ; RL = 2 kΩ to midsupply; unless otherwise noted. All specifications are
per amplifier.
Table 4.
Parameter
Test Conditions/Comments
Min Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VOUT = 0.02 V p-p
G = +1, VOUT = 1 V p-p, +VS = 2 V, −VS = −1 V
G = +1, VOUT = 0.02 V p-p
G = +1, VOUT = 1 V step, +VS = 2 V, −VS = −1 V
G = +1, VOUT = 1 V step
95
30
35
85
41
MHz
MHz
MHz
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion, HD2/HD31
fC = 20 kHz, VOUT = 1 V p-p, +VS = 2 V, −VS = −1 V
fC = 100 kHz, VOUT = 1 V p-p, +VS = 2 V, −VS = −1 V
f = 100 kHz
−123/−143
−107/−133
6.3
8
55
0.8
dBc
dBc
nV/√Hz
Hz
nV rms
pA/√Hz
Input Voltage Noise
Input Voltage Noise 1/f Corner
0.1 Hz to 10 Hz Voltage Noise
Input Current Noise
f = 100 kHz
Rev. B | Page 5 of 25
ADA4805-1/ADA4805-2
Data Sheet
Parameter
Test Conditions/Comments
TMIN to TMAX, 4 σ
Min Typ
Max Unit
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift2
Input Bias Current
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Common Mode
Differential Mode
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
SHUTDOWN PIN
SHUTDOWN Voltage
Low
7
125
1.5
690
µV
µV/°C
nA
0.2
440
0.5
nA
dB
VOUT = 1.1 V to 1.9 V
100
107
50
260
1
MΩ
kΩ
pF
V
−0.1
89
+2
VIN, CM = 0.5 V to 2 V
117
dB
Powered down
Enabled
<0.7
>1.1
V
V
High
SHUTDOWN Current
Low
High
Powered down
Enabled
−1.0 0.1
0.01
µA
µA
1.0
Turn-Off Time
50% of SHUTDOWN to <10% of enabled
quiescent current
0.9
1.25 µs
Turn-On Time
50% of SHUTDOWN to >90% of final VOUT
7
8
µs
ns
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
VIN = −1 V to +4 V, G = +2
135/175
Output Voltage Swing
Short-Circuit Current
Linear Output Current
Off Isolation
RL = 2 kΩ
Sinking/sourcing
<1% THD at 100 kHz, VOUT = 1 V p-p
VIN = 0.5 V p-p, f = 1 MHz, SHUTDOWN = −VS
30% overshoot
0.02
2.7
2.98
V
65/47
40
41
mA
mA
dB
pF
Capacitive Load Drive
POWER SUPPLY
Operating Range
15
10
495
3
V
µA
µA
Quiescent Current per Amplifier
Enabled
SHUTDOWN = −VS
470
1.3
Power Supply Rejection Ratio
Positive
Negative
+VS = 1.5 V to 3.5 V, −VS = −1.5 V
+VS = 1.5 V, −VS = −1.5 V to −3.5 V
96
96
119
125
dB
dB
1 fC is the fundamental frequency.
2 Guaranteed, but not tested.
Rev. B | Page 6 of 25
Data Sheet
ADA4805-1/ADA4805-2
ABSOLUTE MAXIMUM RATINGS
The quiescent power dissipation is the voltage between the supply
pins (VS) multiplied by the quiescent current (IS).
Table 5.
Parameter
Rating
PD = Quiescent Power + (Total Drive Power − Load Power)
Supply Voltage
11 V
Power Dissipation
See Figure 3
−VS − 0.7 V to +VS + 0.7 V
1 V
−65°C to +125°C
−40°C to +125°C
2
VS VOUT
VOUT
RL
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
PD VS IS
2
RL
RMS output voltages must be considered. If RL is referenced
to −VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
2
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
VS / 4
PD
VS IS
RL
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads and
exposed pad from metal traces, through holes, ground, and
power planes reduces θJA.
THERMAL RESISTANCE
θJA is specified for the worst case conditions, that is, θJA is specified
for a device soldered in a circuit board for surface-mount packages.
Table 6 lists the θJA for the ADA4805-1/ADA4805-2.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a JEDEC standard,
4-layer board. θJA values are approximations.
4.0
Table 6. Thermal Resistance
T
= 150°C
J
Package Type
θJA
Unit
°C/W
°C/W
°C/W
°C/W
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6-Lead SC70
223.6
209.1
123.8
51.4
10-LEAD LFCSP
6-Lead SOT-23
8-Lead MSOP
10-Lead LFCSP
MAXIMUM POWER DISSIPATION
8-LEAD MSOP
6-LEAD SOT-23
The maximum safe power dissipation for the ADA4805-1/
ADA4805-2 is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150C, which is
the glass transition temperature, the properties of the plastic
change. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4805-1/ADA4805-2.
Exceeding a junction temperature of 175C for an extended
period of time can result in changes in silicon devices, potentially
causing degradation or loss of functionality.
6-LEAD SC70
–50
–30
–10
10
30
50
70
90
110
130
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the ADA4805-1/ADA4805-2 output load drive.
Rev. B | Page 7 of 25
ADA4805-1/ADA4805-2
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADA4805-1
ADA4805-1
V
1
2
3
6
5
4
+V
S
V
1
2
3
6
5
4
+V
S
OUT
OUT
–V
S
–V
S
SHUTDOWN
–IN
SHUTDOWN
–IN
+IN
+IN
Figure 5. 6-Lead SOT-23 Pin Configuration
Figure 4. 6-Lead SC70 Pin Configuration
Table 7. ADA4805-1 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
VOUT
−VS
+IN
−IN
SHUTDOWN
+VS
Output.
Negative Supply.
Noninverting Input.
Inverting Input.
Active Low Power-Down.
Positive Supply.
Rev. B | Page 8 of 25
Data Sheet
ADA4805-1/ADA4805-2
ADA4805-2
10 +V
V
1
2
3
4
5
S
OUT1
–IN1
+IN1
9
8
7
6
V
OUT2
–IN2
ADA4805-2
–V
+IN2
S
V
1
2
3
4
8
7
6
5
+V
SHUTDOWN1
NOTES
OUT1
–IN1
S
SHUTDOWN2
V
OUT2
+IN1
–IN2
+IN2
1. THE EXPOSED PAD CAN BE CONNECTED TO
GROUND OR POWER PLANES, OR IT CAN
BE LEFT FLOATING.
–V
S
Figure 6. 10-Lead LFCSP Pin Configuration
Figure 7. 8-Lead MSOP Pin Configuration
Table 8. ADA4805-2 Pin Function Descriptions
Pin No.
10-Lead LFCSP
8-Lead MSOP1
Mnemonic
VOUT1
−IN1
+IN1
−VS
SHUTDOWN1
SHUTDOWN2
+IN2
−IN2
VOUT2
Description
1
2
3
4
5
6
7
8
9
10
1
2
3
4
N/A
N/A
5
6
7
Output 1.
Inverting Input 1.
Noninverting Input 1.
Negative Supply.
Active Low Power-Down 1.
Active Low Power-Down 2.
Noninverting Input 2.
Inverting Input 2.
Output 2.
8
+VS
Positive Supply.
N/A
EPAD
Exposed Pad. For the 10-Lead LFCSP, the EPAD can be connected to ground or
power planes, or it can be left floating.
1 N/A means not applicable.
Rev. B | Page 9 of 25
ADA4805-1/ADA4805-2
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
RL = 2 kΩ, unless otherwise noted. When G = +1, RF = 0 Ω.
3
0
3
G = +2
G = +1
0
G = +1
G = +10
G = +5
–3
–6
–9
–12
–3
G = +5
–6
G = +2
G = +10
–9
V
V
= ±2.5V
OUT
= 2kΩ
V
V
= ±2.5V
S
S
= 20mV p-p
= 2V p-p
OUT
R
R
R
R
= 1kΩ
L
F
F
L
= 2kΩ
= 1kΩ
–12
0.1
0.1
1
10
100
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. Small Signal Frequency Response for Various Gains
Figure 11. Large Signal Frequency Response for Various Gains
3
3
–40°C
–40°C
+25°C
0
0
+25°C
–3
+125°C
+125°C
–3
–6
–9
–6
V
= ±2.5V
V
= ±2.5V
S
S
G = +1
= 20mV p-p
G = +1
= 2V p-p
V
R
V
R
OUT
= 2kΩ
OUT
= 2kΩ
L
L
–12
0.1
–9
0.1
1
10
FREQUENCY (MHz)
100
1000
1
10
FREQUENCY (MHz)
100
Figure 9. Small Signal Frequency Response for Various Temperatures
Figure 12. Large Signal Frequency Response for Various Temperatures
3
3
V
= ±5V
S
V
= 0.5V p-p
OUT
V
= ±2.5V
S
V
= 20mV p-p
OUT
0
–3
V
= ±1.5V
S
0
–3
–6
–6
V
= 2V p-p
OUT
–9
V
= 100mV p-p
10
G = +1
= 20mV p-p
L
V
= ±2.5V
OUT
S
V
R
G = +1
= 2kΩ
OUT
= 2kΩ
R
L
–12
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
100
1000
FREQUENCY (MHz)
Figure 10. Small Signal Frequency Response for Various Supply Voltages
Figure 13. Frequency Response for Various Output Voltages
Rev. B | Page 10 of 25
Data Sheet
ADA4805-1/ADA4805-2
12
0.6
0.5
V
= ±2.5V
V
V
= ±2.5V
S
S
G = +1
= 20mV p-p
IN
R
V
= 2kΩ
9
6
G = +1
L
= 20mV p-p
R
= 2kΩ
0.4
OUT
L
0.3
0.2
3
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–3
–6
–9
–12
C
C
C
C
C
= 15pF
= 10pF
= 5pF
L
L
L
L
L
= 0pF
= 15pF, R
=
226Ω
10
FREQUENCY (MHz)
S
1
100
1
10
100
FREQUENCY (MHz)
Figure 14. Small Signal Frequency Response for Various Capacitive Loads
(See Figure 46)
Figure 17. Small Signal 0.1 dB Bandwidth
–50
–60
–50
V
V
V
= ±5V, V
= ±2.5V, V
= +2V/–1V, V
= 2V p-p
= 2V p-p
V
= ±5V, V
= 4V p-p
S
S
S
OUT
S
OUT
–60
–70
OUT
= 1V p-p
OUT
–70
HD2, G = +1
HD2, G = +2
HD2 V = ±5V
S
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
HD2 V = +2V/–1V
S
HD2 V = ±2.5V
S
HD3, G = +2
HD3 V = +2V/–1V
S
HD3 V = ±2.5V
S
HD3 V = ±5V
S
HD3, G = +1
1
10
100
FREQUENCY (kHz)
1000
1
10
100
FREQUENCY (kHz)
1000
Figure 15. Distortion vs. Frequency for Various Gains
Figure 18. Distortion vs. Frequency for Various Supplies, G = +1
–40
–50
–50
V
V
V
= ±5V, V
= ±2.5V, V
= +2V/–1V, V
= 4V p-p
= 4V p-p
V
V
= ±2.5V
IN, CM
INPUT COMMON-MODE
VOLTAGE UPPER LIMIT
S
S
S
OUT
S
= 0V
–60
–70
HD2 V = ±5V
S
OUT
(+V – 1V)
G = +1
R
= 1V p-p
S
OUT
= 2kΩ
L
–60
HD2 V = ±2.5V
S
–80
–70
V
= 1MHz
IN
–90
–80
–100
–110
–120
–130
–140
–150
–160
–90
HD2 V = +2V/–1V
S
–100
–110
–120
–130
–140
V
V
= 100kHz
= 10kHz
IN
HD3 V = +2V/–1V
S
IN
HD3 V = ±2.5V
S
HD3 V = ±5V
S
1
10
100
1000
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
FREQUENCY (kHz)
OUTPUT VOLTAGE (V peak)
Figure 16. Total Harmonic Distortion vs. Output Voltage For Various
Frequencies
Figure 19. Distortion vs. Frequency, G = +2
Rev. B | Page 11 of 25
ADA4805-1/ADA4805-2
Data Sheet
90
80
70
60
50
40
30
20
10
0
12
10
8
V
= ±2.5V
V
= +2.5V
S
S
G = +1
6
4
2
0
0.1
1
10
100
1k
10k 100k
1M
10M 100M
1M
10M
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20. Voltage Noise vs. Frequency
Figure 23. Current Noise vs. Frequency (See Figure 47)
800
750
700
650
600
550
500
450
400
350
300
300
V
= ±2.5V
S
AVERAGE NOISE = 54nV rms
250
200
150
100
50
V
= ±5V
S
0
–50
–100
–150
–200
–250
–300
V
= ±1.5V
S
V
= ±2.5V
S
–40 –25 –10
5
20
35
50
65
80
95 110 125
0
1
2
3
4
5
6
7
8
9
10
TEMPERATURE (°C)
TIME (Seconds)
Figure 21. 0.1 Hz to 10 Hz Voltage Noise
Figure 24. Quiescent Supply Current vs. Temperature for Various Supplies
20
0
–10
V
= ±2.5V
V
= ±2.5V
S
S
G = +1
∆V , ∆V
= 100mV p-p
S
CM
R
= 2kΩ
= 0.5V p-p
–20
–30
–40
–50
–60
–70
–80
–90
L
V
IN
SHUTDOWN = –2.5V
–20
–40
–60
–80
–100
–120
–140
–PSRR
CMRR
+PSRR
10
100
1k
10k
100k
1M
10M
100M
0.01
0.1
1
10
100
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 22. CMRR, PSRR vs. Frequency
Figure 25. Forward/Off Isolation vs. Frequency
Rev. B | Page 12 of 25
Data Sheet
ADA4805-1/ADA4805-2
35
30
25
20
15
10
5
30
V
= ±2.5V
SOT-23
S
SC70
V = ±2.5V
S
S
V
= ±2.5V
T = –40°C TO +125°C
297 UNITS SOLDERED TO PCB
300 UNITS
300 UNITS
25
20
15
10
5
= 7.5µV
= 10.2µV
= –0.19µV/°C
SOT-23
σ = 14.5µV
σ = 18.9 µV
σ = 0.28µV/°C
SC70
0
0
–120 –100 –80 –60 –40 –20
0
20 40 60 80 100 120
–1.9 –1.6 –1.2 –0.8 –0.4
0
0.4 0.8 1.2 1.6 1.9
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
Figure 29. Input Offset Voltage Drift Distribution
Figure 26. Input Offset Voltage Distribution
100
80
150
V
= ±2.5V
V
= ±2.5V
S
S
10 UNITS
30 UNITS
100
50
60
40
20
0
0
–20
–40
–60
–80
–50
–100
–150
–100
–
3.0 –2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
2.0
–40 –25 –10
5
20
35
50
65
80
95 110 125
INPUT COMMON-MODE VOLTAGE (V)
TEMPERATURE (°C)
Figure 27. Input Offset Voltage vs. Input Common-Mode Voltage
Figure 30. Input Offset Voltage vs. Temperature
650
630
6
–400
–450
–500
–550
–600
–650
–700
–750
–800
V
= ±5V
I
S
B–
610
590
570
550
530
510
490
470
450
430
410
390
4
I
B+
2
INPUT OFFSET CURRENT
0
V
= ±2.5V
S
–2
–4
V
= ±1.5V
S
–
6
–40 –25 –10
5
20
35
50
65
80
95 110 125
–0.4
0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
INPUT COMMON-MODE VOLTAGE (V)
TEMPERATURE (°C)
Figure 28. Input Bias Current vs. Temperature for Various Supplies
(See Figure 48)
Figure 31. Input Bias Current and Input Offset Current vs.
Input Common-Mode Voltage
Rev. B | Page 13 of 25
ADA4805-1/ADA4805-2
Data Sheet
15
1.5
1.0
G = +1
= 20mV p-p
V
= ±5V, V
= 0V, V
= 2V p-p
G = +1
S
IN, CM
OUT
V
OUT
V
= ±2.5V, V
= 0V, V
= 2V p-p
S
IN, CM
OUT
10
V
= ±2.5V
S
5
0
0.5
0
–5
–0.5
–1.0
–1.5
V
= ±1.5V
= ±5V
S
–10
–15
V
= ±1.5V, V
50
= –0.5V, V
= 1V p-p
OUT
S
IN, CM
V
S
0
50
100
150
TIME (ns)
200
250
300
0
100
150
200
250
300
350
TIME (ns)
Figure 32. Small Signal Transient Response for Various Supplies, G = +1
Figure 35. Large Signal Transient Response for Various Supplies, G = +1
5
4
V
= ±2.5V
V
= ±2.5V
S
S
2×V
IN
V
G = +1
G = +2
IN
4
3
3
2
2
V
1
OUT
V
OUT
1
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
0
100 200 300 400 500 600 700 800 900 1000
TIME (ns)
0
100 200 300 400 500 600 700 800 900 1000
TIME (ns)
Figure 33. Input Overdrive Recovery Time, G = +1
Figure 36. Output Overdrive Recovery Time, G = +2
120
100
80
0
0.3
0.2
V
= +5V
S
G = +1
= 2V STEP
–20
V
R
OUT
= 2kΩ
L
GAIN
–40
–60
–80
0.1
60
0
–100
–120
–140
–160
–180
PHASE
40
–0.1
–0.2
–0.3
20
0
–20
10
100
1k
10k
100k
1M
10M
100M
0
20
40
60
80
100
120
140
160
180
FREQUENCY (Hz)
TIME (ns)
Figure 34. Settling Time to 0.1%
Figure 37. Open-Loop Gain and Phase Margin
Rev. B | Page 14 of 25
Data Sheet
ADA4805-1/ADA4805-2
0.9
0.8
0.7
0.6
0.9
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= ±2.5V
V
= ±2.5V
S
S
G = +1
= 2kΩ
G = +1
= 2kΩ
R
R
L
L
SHUTDOWN = +2.5V
SHUTDOWN = +2.5V
V
= ±5V
S
+125˚C
0.5
V
= +2V/–1V
S
V
= ±2.5V
0.4
S
+25˚C
0.3
0.2
0.1
0
–40˚C
–0.1
–0.1
0
1
2
3
4
5
6
0
1
2
3
4
5
6
TIME (µs)
TIME (µs)
Figure 38. Turn-On Response Time for Various Temperatures (See Figure 49)
Figure 40. Turn-On Response Time for Various Supplies (See Figure 49)
800
800
V
= ±2.5V
V
= ±2.5V
S
S
G = +1
= 2kΩ
G = +1
R = 2kΩ
L
700
600
500
400
300
200
100
0
R
700
600
500
400
300
200
100
L
V
= ±5V
S
SHUTDOWN = –2.5V
SHUTDOWN = –V
S
+125°C
+25°C
V
= ±2.5V
S
V
= ±1.5V
S
–
40°C
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
TIME (µs)
TIME (µs)
Figure 39. Turn-Off Response Time for Various Temperatures (See Figure 50)
Figure 41. Turn-Off Response Time for Various Supplies (See Figure 50)
Rev. B | Page 15 of 25
ADA4805-1/ADA4805-2
Data Sheet
0
–20
–40
–60
–80
0
–20
–40
–60
–80
–100
–120
–140
–160
–100
–120
–140
–160
AMP2 TO AMP1
AMP2 TO AMP1
AMP1 TO AMP2
AMP1 TO AMP2
0.1
FREQUENCY (MHz)
0.001
0.01
1
10
100
1000
0.001
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 44. Crosstalk vs. Frequency (MSOP)
Figure 42. Crosstalk vs. Frequency (LFCSP)
3
25.5
25.0
24.5
24.0
23.5
23.0
22.5
22.0
21.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
= ±2.5V
S
6 UNITS, SOLDERED TO PCB
2
1
DEVICE ENABLED
–40°C
OIL BATH
TEMPERATURE
0
+125°C
+25°C
–1
–2
–3
–4
–5
DEVICE DISABLED
0
200
400
600
800
1000
1200
1400
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
TIME (Hours)
SUPPLY VOLTAGE FROM GROUND (V)
SHUTDOWN
Figure 45. Long-Term VOS Drift
Figure 43.
Threshold vs. Supply Voltage from Ground for
Various Temperatures
Rev. B | Page 16 of 25
Data Sheet
ADA4805-1/ADA4805-2
TEST CIRCUITS
+2.5V
V
OUT
+2.5V
–2.5V
R
S
0.5V
SHUTDOWN
2kΩ
V
OUT
V
IN
20mV p-p
C
2kΩ
L
–2.5V
50Ω
+
5V
–
–2.5V
Figure 46. Output Capacitive Load Behavior Test Circuit (See Figure 14)
Figure 49. Turn-On Response Test Circuit (See Figure 38 and Figure 40)
+2.5V
I
S
+2.5V
V
OUT
V
OUT
SHUTDOWN
2kΩ
75kΩ
–2.5V
–2.5V
+
–
5V
–2.5V
Figure 47. Current Noise Test Circuit (See Figure 23)
Figure 50. Turn-Off Response Test Circuit (See Figure 39 and Figure 41)
+Ib
–Ib
Figure 48. Input Bias Current Temperature Test Circuit (See Figure 28)
Rev. B | Page 17 of 25
ADA4805-1/ADA4805-2
Data Sheet
THEORY OF OPERATION
For differential voltages above approximately 1.2 V at room
AMPLIFIER DESCRIPTION
temperature, and 0.8 V at 125°C, the diode clamps begin to
conduct. If large differential voltages must be sustained across
the input terminals, the current through the input clamps must
be limited to less than 10 mA. Series input resistors that are sized
appropriately for the expected differential overvoltage provide
the needed protection.
The ADA4805-1/ADA4805-2 have a bandwidth of 105 MHz and
a slew rate of 160 V/μs. They have an input referred voltage
noise of only 5.9 nV/√Hz. e ADA4805-1/ADA4805-2 operate
over a supply voltage range of 2.7 V to 10 V and consume only
500 μA of supply current at VS = 5 V. The low end of the supply
range allows for −10% variation of a 3 V supply. The amplifiers
are unity-gain stable, and the input structure results in an
extremely low input 1/f noise. The ADA4805-1/ADA4805-2 use
a slew enhancement architecture, as shown in Figure 51. The
slew enhancement circuit detects the absolute difference
The ESD clamps begin to conduct for input voltages that are
more than 0.7 V above the positive supply and input voltages
more than 0.7 V below the negative supply. If an overvoltage
condition is expected, the input current must be limited to less
than 10 mA.
between the two inputs. It then modulates the tail current, ITAIL
,
of the input stage to boost the slew rate. The architecture allows
higher slew rate and fast settling time with low quiescent
current while maintaining low noise.
SHUTDOWN OPERATION
Figure 53 shows the ADA4805-1/ADA4805-2 shutdown
circuitry. To maintain very low supply current in shutdown
mode, no internal pull-up resistor is supplied; therefore, the
SLEW ENHANCEMENT CIRCUIT
V
S
SHUTDOWN
pin must be driven high or low externally and
SHUTDOWN
not be left floating. Pulling the
pin to ≥1 V below
I
TAIL
TO DETECT
ABSOLUTE
VALUE
midsupply turns the device off, reducing the supply current to
2.9 μA for a 5 V supply. When the amplifier is powered down,
its output enters a high impedance state. The output impedance
decreases as frequency increases. In shutdown mode, a forward
isolation of −62 dB can be achieved at 100 kHz (see Figure 25).
V
V
IN–
IN+
+IN/+INx
+V
S
–IN/−INx
2.2R
INPUT
STAGE
1.1V
ESD
ESD
Figure 51. Slew Enhancement Circuit
SHUTDOWN
INPUT PROTECTION
The ADA4805-1/ADA4805-2 are fully protected from ESD
events, withstanding human body model ESD events of 3.5 kV
and charged device model events of 1.25 kV with no measured
performance degradation. The precision input is protected with
an ESD network between the power supplies and diode clamps
across the input device pair, as shown in Figure 52.
1.8R
S
TO ENABLE
AMPLIFIER
–V
Figure 53. Shutdown Circuit
SHUTDOWN
The
Figure 53. Voltages beyond the power supplies cause these
SHUTDOWN
pin is protected by ESD clamps, as shown in
+V
S
diodes to conduct. To protect the
pin, ensure that
BIAS
the voltage to this pin does not exceed 0.7 V above the positive
supply or 0.7 V below the negative supply. If an overvoltage
condition is expected, the input current must be limited to less
than 10 mA with a series resistor. Table 9 summarizes the
threshold voltages for the powered down and enabled modes for
various supplies.
ESD
+IN/+INx
ESD
ESD
ESD
–IN/–INx
–V
S
Table 9. Threshold Voltages for Powered Down and Enabled
Modes
TO THE REST OF THE AMPLIFIER
Figure 52. Input Stage and Protection Diodes
Mode
+3 V
+5 V
5 V
+7 V/−2 V
>+1.52 V
<+1.52 V
Enabled
>+1.1 V >+1.9 V >−0.9 V
Powered Down <+0.7 V <+1.5 V <−1.3 V
Rev. B | Page 18 of 25
Data Sheet
ADA4805-1/ADA4805-2
Figure 55 shows the total referred to input (RTI) noise due to
the amplifier vs. the source resistance. Note that with a
5.9 nV/√Hz input voltage noise and 0.6 pA/√Hz input current
noise, the noise contributions of the amplifier are relatively
small for source resistances from approximately 2.6 kΩ to
47 kΩ.
NOISE CONSIDERATIONS
Figure 54 illustrates the primary noise contributors for the
typical gain configurations. The total output noise (vn_out) is the
root sum square of all the noise contributions.
R
v
=
4kTR
F
n_RF
F
v
n
R
v
=
=
G
S
4kTR
n_RG
G
The Analog Devices silicon germanium (SiGe) bipolar process
makes it possible to achieve a low noise of 5.9 nV/√Hz for the
ADA4805-1/ADA4805-2. This noise is much improved
compared to similar low power amplifiers with a supply current
in the range of hundreds of microamperes.
+ v
–
i
n_out
n–
R
v
4kTR
n_RS
S
i
n+
1000
Figure 54. Noise Sources in Typical Connection
TOTAL NOISE
SOURCE RESISTANCE NOISE
AMPLIFIER NOISE
The output noise spectral density is calculated by
vn_ out
=
2
2
RF
RG
RF
RG
100
2
2
2
4kTRs + in+2RS + vn
]
+
4kTRG + in−2 RF
4kTRF + 1+
[
where:
k is Boltzmann’s constant.
T is the absolute temperature in degrees Kelvin.
RF and RG are the feedback network resistances, as shown in
Figure 54.
10
SOURCE RESISTANCE = 47kΩ
SOURCE RESISTANCE = 2.6kΩ
RS is the source resistance, as shown in Figure 54.
in+ and in− represent the amplifier input current noise spectral
density in pA/√Hz.
1
100
1k
10k
100k
1M
SOURCE RESISTANCE (Ω)
vn is the amplifier input voltage noise spectral density in
nV/√Hz.
Figure 55. RTI Noise vs. Source Resistance
Source resistance noise, amplifier input voltage noise (vn), and
the voltage noise from the amplifier input current noise
(in+ × RS) are all subject to the noise gain term (1 + RF/RG).
Rev. B | Page 19 of 25
ADA4805-1/ADA4805-2
Data Sheet
APPLICATIONS INFORMATION
5
4
SLEW ENHANCEMENT
V
= ±2.5V
S
G = +2
R
V
= 2 kꢀ
R
= 2.6kꢀ
L
The ADA4805-1/ADA4805-2 have an internal slew enhancement
circuit that increases the slew rate as the feedback error voltage
increases. This circuit allows the amplifier to settle a large step
response faster, as shown in Figure 56. This is useful in ADC
applications where multiple input signals are multiplexed. The
impact of the slew enhancement can also be seen in the large
signal frequency response, where larger input signals cause a
slight increase in peaking, as shown in Figure 57.
1.5
F
= 200mV p-p
IN
3
R
= 4.99kꢀ
F
2
1
0
–1
–2
–3
–4
–5
–6
R
= 1kꢀ
F
R
= 2.6kꢀ, C = 1pF
F
F
R
= 4.99kꢀ, C = 1pF
F
F
V
= ±2.5V
S
G = +1
R
= 2kΩ
L
V
= 2V p-p
= 1V p-p
OUT
OUT
1.0
0.5
100k
1M
10M
100M
V
FREQUENCY (Hz)
Figure 58. Peaking in Frequency Response at Selected RF Values
V
= 500mV p-p
OUT
0
COMPENSATING PEAKING IN LARGE SIGNAL
FREQUENCY RESPONSE
–0.5
–1.0
–1.5
At high frequency, the slew enhancement circuit can contribute to
peaking in the large signal frequency response. Figure 58 shows the
effect of a feedback capacitor on the small signal response, whereas
Figure 59 shows that the same technique is effective for reducing
peaking in the large signal response.
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
6
V
= ±2.5V
S
Figure 56. Step Response with Selected Output Steps
G = +2
R
V
= 2 kꢀ
= 632mV p-p
L
3
0
2
1
IN
V
= ±2.5V
S
G = +1
= 2kꢀ
R
L
R
F
= 2.6kꢀ, C = 0pF
F
F
0
R
= 1kꢀ, C = 0pF
–3
F
F
R
= 2.6kꢀ, C = 2.7pF
F
V
= 2V p-p
IN
R
= 1 kꢀ, C = 2 pF
F
F
V
V
V
= 200mV p-p
= 632mV p-p
= 400mV p-p
–1
–2
–3
–4
–5
–6
IN
IN
IN
–6
–9
–12
–15
V
= 100mV p-p
IN
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 59. Peaking Mitigation in Large Signal Frequency Response
100k
1M
10M
FREQUENCY (Hz)
100M
DRIVING LOW POWER, HIGH RESOLUTION
SUCCESSIVE APPROXIMATION REGISTER (SAR)
ADCs
Figure 57. Peaking in Frequency Responses as Signal Level Changes, G = +1
EFFECT OF FEEDBACK RESISTOR ON FREQUENCY
RESPONSE
The ADA4805-1/ADA4805-2 are ideal for driving low power,
high resolution SAR ADCs. The 5.9 nV/√Hz input voltage noise
and rail-to-rail output stage of the ADA4805-1/ADA4805-2
help to minimize distortion at large output levels. With its low
power of 500 μA, the amplifier consumes power that is
compatible with low power SAR ADCs, which are usually in the
microwatt (μW) to low milliwatt (mW) range. Furthermore, the
ADA4805-1/ADA4805-2 support a single-supply configuration;
their input common-mode range extends to 0.1 V below the
negative supply, and 1 V below the positive supply.
The amplifiers input capacitance and feedback resistor form a
pole that, for larger value feedback resistors, can reduce phase
margin and contribute to peaking in the frequency response.
Figure 58 shows the peaking for selected feedback resistors (RF)
when the amplifier is configured in a gain of +2. Figure 58 also
shows how peaking can be mitigated with the addition of a
small value capacitor placed across the feedback resistor of the
amplifier.
Rev. B | Page 20 of 25
Data Sheet
ADA4805-1/ADA4805-2
Figure 60 shows a typical 16-bit, single-supply application. The
ADA4805-1/ADA4805-2 drive the AD7980, a 16-bit, 1 MSPS,
SAR ADC in a low power configuration. The AD7980 operates
on a 2.5 V supply and supports an input from 0 V to VREF. In
this case, the ADR435 provides a 5 V reference. The ADA4805-1/
ADA4805-2 are used both as a driver for the AD7980 and as a
reference buffer for the ADR435.
DYNAMIC POWER SCALING
One of the merits of a SAR ADC, like the AD7980, is that its
power scales with the sampling rate. This power scaling makes
SAR ADCs very power efficient, especially when running at a
low sampling frequency. However, the ADC driver used with
the SAR ADC traditionally consumes constant power regardless
of the sampling frequency.
The low-pass filter formed by R3 and C1 reduces the noise to
the input of the ADC (see Figure 60). In lower frequency
applications, the designer can reduce the corner frequency of
the filter to remove additional noise.
Figure 61 illustrates a method by which the quiescent power of
the ADC driver can be dynamically scaled with the sampling
rate of the system. By providing properly timed signals to the
SHUTDOWN
convert start (CNV) pin of the ADC and the
pin
+7.5V
of the ADA4805-1/ADA4805-2, both devices can be run at
optimum efficiency.
5V REF
ADA4805-2
ADR435
ADA4805-1/
VDD
C4
100nF
+5V
C2
10µF
C3
0.1µF
+6V
+2.5V
0.1µF
V
IN
REF
VDD
ADA4805-1/
ADA4805-2
+7.5V
20ꢀ
AD7980
ADA4805-1/
2.7nF
0V TO
ADA4805-2
GND CNV
REF VDD
V
REF
IN+
IN–
R3
20Ω
AD7980
GND
TIMING
GENERATOR
C1
2.7nF
Figure 61. ADA4805-1/ADA4805-2/AD7980 Power Management Circuitry
Figure 60. Driving the AD7980 with the ADA4805-1/ADA4805-2
Figure 62 illustrates the relative signal timing for power scaling
the ADA4805-1/ADA4805-2 and the AD7980. To prevent any
degradation in the performance of the ADC, the ADA4805-1/
ADA4805-2 must have a fully settled output into the ADC
before the activation of the CNV pin. In this example, the
amplifier is switched to full power mode 3 μs prior to the rising
In this configuration, the ADA4805-1/ADA4805-2 consume
7.2 mW of quiescent power. The measured signal-to-noise ratio
(SNR), total harmonic distortion (THD), and signal-to-noise-
and-distortion ratio (SINAD) of the whole system for a 10 kHz
signal are 89.4 dB, 104 dBc, and 89.3 dB, respectively. This
translates to an effective number of bits (ENOB) of 14.5 at
10 kHz, which is compatible with the AD7980 performance.
Table 10 shows the performance of this setup at selected input
frequencies.
SHUTDOWN
edge of the CNV signal. The
pin of the
ADA4805-1/ADA4805-2 is pulled low when the ADC input is
inactive in between samples. The quiescent current of the
amplifier typically falls to 10% of the normal operating value
within 0.9 μs at VS = 5 V. While in shutdown mode, the
ADA4805-1/ADA4805-2 output impedance is high.
Table 10. System Performance at Selected Input Frequency for Driving the AD7980 Single-Ended
ADC Driver Reference Buffer
Results
THD (dBc)
Input Frequency (kHz)
Supply (V)
Gain
Supply (V)
Gain
SNR (dB)
89.8
89.4
89.9
88.5
SINAD (dB)
89.6
ENOB
14.6
14.5
14.6
14.3
13.9
1
7.5
7.5
7.5
7.5
7.5
1
1
1
1
1
7.5
7.5
7.5
7.5
7.5
1
1
1
1
1
103
104
103
99
10
20
50
100
89.3
89.7
88.1
86.3
93.7
85.6
Rev. B | Page 21 of 25
ADA4805-1/ADA4805-2
Data Sheet
SAMPLING FREQUENCY = 100kHz
tS = 10µs
ACQUISITION
CONVERSION
ACQUISITION
CONVERSION
ACQUISITION
CONVERSION
ADC
MODE
CNV
POWERED
POWERED
POWERED
ADA4805-1/
ADA4805-2
ON
ON
ON
SHUTDOWN
SHUTDOWN
SHUTDOWN
SHUTDOWN
tAMP, ON
MINIMUM
POWERED ON TIME = 3µs
3µs
3µs
V
V
f3
f1
V
f2
ADA4805-1/
ADA4805-2
OUTPUT
tTURNOFF1
tTURNOFF3
tTURNOFF2
t
t
t
f3
f1
f2
Figure 62. Timing Waveforms
100000
10000
1000
100
Figure 63 shows the quiescent power of the ADA4805-1/
ADA4805-1/ADA4805-2, 6V SINGLE SUPP LY
V
f
= 4.72V p-p (–0.5dBFS)
= 100Hz
ON TIME = 3µs
IN
ADA4805-2 with and without the power scaling. Without power
scaling, the ADA4805-1/ADA4805-2 consumes constant power
regardless of the sampling frequency, as shown in Equation 1.
IN
PQ = IQ × VS
(1)
With power scaling, the quiescent power becomes proportional
to the ratio between the amplifier on time, tAMP, ON, and the
sampling time, tS:
ADA4805-1/ADA4805-2
CONTINUOUSLY ON
ADA4805-1/ADA4805-2
ON TIME = 3µs
tAMP,ON
AD7980 (ADC)
PQ IQ VS
(2)
tS
10
Thus, by dynamically switching the ADA4805-1/ADA4805-2
between shutdown and full power modes between consecutive
samples, the quiescent power of the driver scales with the
sampling rate.
10
100
1k
10k
100k
1M
ADC SAMPLING FREQUENCY (Hz/s)
Figure 63. Quiescent Power Consumption of the ADA4805-1/ADA4805-2 vs.
ADC Sampling Frequency
Rev. B | Page 22 of 25
Data Sheet
ADA4805-1/ADA4805-2
SINGLE-ENDED TO DIFFERENTIAL CONVERSION
LAYOUT CONSIDERATIONS
Most high resolution ADCs have differential inputs to reduce
common-mode noise and harmonic distortion. Therefore, it is
necessary to use an amplifier to convert a single-ended signal
into a differential signal to drive the ADCs.
To ensure optimal performance, careful and deliberate attention
must be paid to the board layout, signal routing, power supply
bypassing, and grounding.
Ground Plane
There are two common ways the user can convert a single-ended
signal into a differential signal: either use a differential
It is important to avoid ground in the areas under and around the
input and output of the ADA4805-1/ADA4805-2. Stray capacitance
between the ground plane and the input and output pads of a
device is detrimental to high speed amplifier performance.
Stray capacitance at the inverting input, together with the
amplifier input capacitance, lowers the phase margin and can
cause instability. Stray capacitance at the output creates a pole in
the feedback loop, which can reduce phase margin and cause
the circuit to become unstable.
amplifier, or configure two amplifiers as shown in Figure 64.
The use of a differential amplifier yields better performance,
whereas the 2-op-amp solution results in lower system cost. The
ADA4805-1/ADA4805-2 solve this dilemma of choosing between
the two methods by combining the advantages of both. Their
low harmonic distortion, low offset voltage, and low bias current
mean that they can produce a differential output that is well
matched with the performance of the high resolution ADCs.
Power Supply Bypassing
Figure 64 shows how the ADA4805-1/ADA4805-2 convert a
single-ended signal into a differential output. The first amplifier
is configured in a gain = +1 with its output then inverted to
produce the complementary signal. The differential output then
drives the AD7982, an 18-bit, 1 MSPS SAR ADC. To further
reduce noise, the user can reduce the values of R1 and R2.
However, note that this increases the power consumption. The
low-pass filter of the ADC driver limits the noise to the ADC.
Power supply bypassing is a critical aspect in the performance
of the ADA4805-1/ADA4805-2. A parallel connection of
capacitors from each power supply pin to ground works best.
Smaller value ceramic capacitors offer better high frequency
response, whereas larger value ceramic capacitors offer better
low frequency performance.
Paralleling different values and sizes of capacitors helps to ensure
that the power supply pins are provided with a low ac impedance
across a wide band of frequencies. This is important for minimizing
the coupling of noise into the amplifier—especially when the
amplifier PSRR begins to roll off—because the bypass capacitors
can help lessen the degradation in PSRR performance.
The measured SNR, THD, and SINAD of the whole system for a
10 kHz signal are 93 dB, 113 dBc, and 93 dB, respectively. This
translates to an ENOB of 15.1 at 10 kHz, which is compatible
with the performance of the AD7982. Table 11 shows the
performance of this setup at selected input frequencies.
Place the smallest value capacitor on the same side of the board
as the amplifier and as close as possible to the amplifier power
supply pins. Connect the ground end of the capacitor directly to
the ground plane.
Table 11. System Performance at Selected Input Frequency
for Driving the AD7982 Differentially
Results
Input Frequency
(kHz)
SNR
(dB)
THD
(dBc)
SINAD
(dB)
It is recommended that a 0.1 μF ceramic capacitor with a
0508 case size be used. The 0508 case size offers low series
inductance and excellent high frequency performance. Place a
10 μF electrolytic capacitor in parallel with the 0.1 μF capacitor.
Depending on the circuit parameters, some enhancement to
performance can be realized by adding additional capacitors.
Each circuit is different and must be analyzed individually for
optimal performance.
ENOB
15.1
15.1
15.1
14.8
14.3
1
93
93
93
92
89
104
113
110
102
96
93
93
93
91
88
10
20
50
100
VDD
C4
0.1µF
R3
22ꢀ
+5V
R2
1kꢀ
C2
2.7nF
+7.5V
REF VDD
IN+
AD7982
IN–
+7.5V
R1
1kꢀ
R4
22ꢀ
ADA4805-1/
ADA4805-2
C3
2.7nF
ADA4805-1/
ADA4805-2
V
C1
0.1µF
IN
+2.5V
+2.5V
Figure 64. Driving the AD7982 with the ADA4805-1/ADA4805-2
Rev. B | Page 23 of 25
ADA4805-1/ADA4805-2
OUTLINE DIMENSIONS
Data Sheet
3.00
2.90
2.80
6
1
5
2
4
3
3.00
2.80
2.60
1.70
1.60
1.50
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
4°
0°
SEATING
PLANE
0.60
BSC
0.50 MAX
0.30 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 65. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
2.20
2.00
1.80
2.40
2.10
1.80
6
1
5
2
4
3
1.35
1.25
1.15
0.65 BSC
1.30 BSC
1.00
0.90
0.70
0.40
0.10
1.10
0.80
0.46
0.36
0.26
0.22
0.08
SEATING
PLANE
0.10 MAX
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 66. 6-Lead Plastic Surface-Mount Package [SC70]
(KS-6)
Dimensions shown in millimeters
Rev. B | Page 24 of 25
Data Sheet
ADA4805-1/ADA4805-2
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 67. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
0.50 BSC
2.90
10
6
PIN 1 INDEX
AREA
EXPOSED
PAD
1.74
1.64
1.49
0.50
0.40
0.30
0.20 MIN
1
5
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 68. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Package Description
Package Option Branding
ADA4805-1ARJZ-R2
ADA4805-1ARJZ-R7
ADA4805-1AKSZ-R2
ADA4805-1AKSZ-R7
ADA4805-2ARMZ
ADA4805-2ARMZ-R7
ADA4805-2ACPZ-R7
ADA4805-2ACPZ-R2
ADA4805-1ARJZ-EBZ
ADA4805-1AKSZ-EBZ
ADA4805-2ARMZ-EBZ
ADA4805-2ACPZ-EBZ
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
6-Lead Small Outline Transistor Package [SOT-23]
RJ-6
RJ-6
KS-6
KS-6
RM-8
RM-8
H3H
H3H
H3H
H3H
H3K
H3K
H3K
H3K
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Plastic Surface-Mount Package [SC70]
6-Lead Plastic Surface-Mount Package [SC70]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-10-9
10-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-10-9
Evaluation Board for 6-Lead SOT-23
Evaluation Board for 6-Lead SC70
Evaluation Board for 8-Lead MSOP
Evaluation Board for 10-Lead LFCSP
1 Z = RoHS Compliant Part.
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11345-0-12/14(B)
Rev. B | Page 25 of 25
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