ADA4807-1AKSZ-EBZ [ADI]
3.1 nV/âHz, 1 mA, 180 MHz, Rail-to-Rail Input/Output Amplifiers;
| 型号： | ADA4807-1AKSZ-EBZ |
| 厂家： | 
ADI |
| 描述： | 3.1 nV/âHz, 1 mA, 180 MHz, Rail-to-Rail Input/Output Amplifiers |
| 文件： | 总33页 (文件大小：748K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.1 nV/√Hz, 1 mA, 180 MHz,
Rail-to-Rail Input/Output Amplifiers
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
FEATURES
PIN CONNECTION DIAGRAMS
Low input noise
V
1
2
3
6
5
4
+V
S
OUT
3.1 nV/√Hz at f = 100 kHz with 29 Hz 1/f corner
0.7 pA/√Hz at f = 100 kHz with 2 kHz 1/f corner
High speed performance with dc precision
180 MHz, −3 dB bandwidth (G = +1, VOUT = 20 mV p-p)
225 V/μs slew rate for 5 V step (rise)
47 ns settling time to 0.1% for 4 V step
125 μV and 3.7 μV/°C maximum input offset voltage and drift
100 nA and 250 pA/°C maximum input offset current and drift
Low distortion (HD2/HD3), VS = 5 V, VOUT = 2 V p-p
−141 dBc/−144 dBc at 1 kHz
–V
S
DISABLE
–IN
+IN
Figure 1. 6-Lead SC70 and 6-Lead SOT-23 Pin Configuration (ADA4807-1)
V
1
2
3
4
8
7
6
5
+V
OUT1
–IN1
S
V
OUT2
+IN1
–IN2
+IN2
–V
S
Figure 2. 8-Lead MSOP Pin Configuration (ADA4807-2)
−112 dBc/−115 dBc at 100 kHz
−95 dBc/−79 dBc at 1 MHz
Low power operation
1.0 mA quiescent supply current per amplifier at 5 V
Dynamic power scaling
10 +V
V
1
2
3
4
5
S
OUT1
–IN1
+IN1
9
8
7
6
V
OUT2
–IN2
–V
+IN2
S
DISABLE1
DISABLE2
Fully specified at +3 V, +5 V, and 5 V supplies
Rail-to-rail inputs and outputs
Figure 3. 10-Lead LFCSP Pin Configuration (ADA4807-2)
1
2
3
4
5
6
7
14
13
V
OUT4
V
OUT1
APPLICATIONS
–IN1
–IN4
High resolution analog-to-digital converter (ADC) drivers
Portable and battery-powered instruments and systems
High component density data acquisition systems
Audio signal conditioning
12 +IN4
+IN1
11
–V
S
+V
S
ADA4807-4
10
9
+IN3
–IN3
V
+IN2
–IN2
Active filters
8
V
OUT3
OUT2
Figure 4. 14-Lead TSSOP Pin Configuration (ADA4807-4)
GENERAL DESCRIPTION
The ADA4807-1 (single), ADA4807-2 (dual), and ADA4807-4
(quad) are low noise, rail-to-rail input and output, voltage
feedback amplifiers. These amplifiers combine low power, low
noise, high speed, and dc precision to provide an attractive
solution for a wide range of applications from high resolution
data acquisition instrumentation to high performance battery-
powered and high component density systems where power
consumption is of key importance.
These amplifiers are fully specified at +3 V, +5 V, and 5 V supplies
and can operate over the industrial −40°C to +125°C
temperature range.
The ADA4807-1 is available in 6-lead SOT-23 and space-saving
6-lead SC70 packages. The ADA4807-2 is available in an 8-lead
MSOP and a compact, 3 mm × 3 mm, 10-lead LFCSP. The
ADA4807-4 is available in a 14-lead TSSOP package.
Table 1. Other Rail-to-Rail Amplifiers
With only 1.0 mA of supply current per amplifier, the ADA4807-1/
ADA4807-2/ADA4807-4 feature the lowest input voltage noise
among high speed, rail-to-rail input/output amplifiers in the
industry and offer a wide bandwidth, high slew rate, fast settling
time, and excellent distortion performance. Additionally, these
amplifiers offer very low input offset voltage and drift performance,
making them ideal for driving multiplexed and high throughput
precision 16-/18-bit successive approximation registers (SARs)
and 24-bit - ADCs.
Slew
Voltage
Noise
Max.
VOS
Bandwidth Rate
Device
(MHz)
(V/μs)
(nV/√Hz) (mV)
AD8031/AD8032
AD8027/AD8028
AD8029/AD8030/
AD8040
80
190
125
35
90
62
15
4ꢀ3
16ꢀ5
1ꢀ5
0ꢀ8
5
Rev. B
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ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Slew, Transient, Settling Time, and Crosstalk............................. 18
Distortion and Noise.................................................................. 20
Output Characteristics............................................................... 22
Overdrive Recovery and Turn On/Turn Off Times .............. 23
Theory of Operation ...................................................................... 24
Disable Circuitry ........................................................................ 2±
Input Protection ......................................................................... 2±
Noise Considerations................................................................. 2±
Applications Information.............................................................. 26
Capacitive Load Drive ............................................................... 26
Low Noise FET Operational Amplifier................................... 26
Power Mode ADC Driver ......................................................... 27
ADC Driving............................................................................... 28
ADC Driving with Dynamic Power Scaling........................... 29
Layout, Grounding, and Bypassing.......................................... 30
Outline Dimensions....................................................................... 31
Ordering Guide .......................................................................... 33
Applications....................................................................................... 1
Pin Connection Diagrams............................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
±± ꢀ Supply................................................................................... 3
± ꢀ Supply...................................................................................... ±
3 ꢀ Supply...................................................................................... 7
Absolute Maximum Ratings............................................................ 9
Maximum Power Dissipation ..................................................... 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 13
Frequency Response................................................................... 13
Frequency and Supply Current................................................. 1±
DC and Input Common-Mode Performance......................... 16
REVISION HISTORY
9/15—Rev. A to Rev. B
Added Figure ±8 ............................................................................. 33
Changes to Ordering Guide.......................................................... 33
Added ADA4807-4.............................................................Universal
Changes to Features Section, General Description Section, and
Table 1 ..........................................................................................................1
Added Figure 4, Renumbered Sequentially .................................. 1
Changes to Table 2............................................................................ 3
Changes to Table 3............................................................................ ±
Changes to Table 4............................................................................ 7
Deleted Figure 6, Renumbered Sequentially............................... 10
Changes to Figure 6........................................................................ 10
Added Figure 9 and Table 9, Renumbered Sequentially ........... 12
Changes to Figure 20...................................................................... 14
Added Figure 21.............................................................................. 14
Added Figure 31 and Figure 32..................................................... 16
Added Figure 3±.............................................................................. 17
Changes to Figure 39...................................................................... 18
Added Figure 42.............................................................................. 19
Deleted Figure ±0, Figure ±1, Figure ±3, and Figure ±4............. 19
Added Figure 46.............................................................................. 20
Added Figure 49 and Figure ±1..................................................... 21
Added Figure ±9 and Figure 61..................................................... 23
4/15—Rev. 0 to Rev. A
Added ADA4807-2.............................................................Universal
Changes to Features Section, General Description
Section, and Pin Connection Diagrams Heading.........................1
Added Figure 2 and Figure 3; Renumbered Sequentially ............1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................±
Changes to Table 3.............................................................................7
Changes to Table 6 and Figure 4......................................................9
Added Figure 7, Figure 8, and Table 8; Renumbered Sequentially....11
Reorganized Layout, Typical Performance Characteristics
Section.............................................................................................. 12
Added Figure 36 ............................................................................. 16
Changes to Figure 37 Caption, Figure 38 Caption, Figure 39
Caption, and Figure 40 Caption ................................................... 17
Changes to Figure 44 and Figure 47............................................. 18
Change to Theory of Operation Section ..................................... 20
DISABLE
Changes to
Circuitry Section, Table 9, and Noise
DISABLE
Changes to
Circuitry Section...................................... 2±
Considerations Section.................................................................. 21
Added Figure 6± and Figure 66 .................................................... 23
Changes to Ordering Guide.......................................................... 2±
Added Low Noise FET Operational Amplifier Section............. 26
Added Figure 70, Figure 71, Figure 72, and Power Mode ADC
Driver Section ................................................................................. 27
Added ADC Driving Section and Figure 73 through Figure 77.....28
Added ADC Driving with Dynamic Power Scaling Section,
Figure 78, Figure 79, and Figure 80.............................................. 29
12/14—Revision 0: Initial Version
Rev. B | Page 2 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
SPECIFICATIONS
±±5 5ꢀSUUPL5
TA = 25°C, VS = 5 V, RLOAD = 1 kΩ to midsupply, RF = 0 ꢀ, G = +1, −VS ≤ VICM ≤ +VS − 1.5 V, unless otherwise noted.
Table 2.
Uarameter5Test5
Conditions/Comments5
Min5
Typ5
Max5
Snit5
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, VOUT = 20 mV p-p
G = +1, VOUT = 2 V p-p
G = +1, VOUT = 5 V step, 20% to 80%, rise/fall
G = +1, VOUT = 4 V step
180
28
225/250
47
MHz
MHz
V/μs
ns
Slew Rate
Settling Time to 0.1%
DISTORTION/NOISE PERFORMANCE
Second Harmonic (HD2)
fC = 1 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p, ADA4807-1
fC = 1 MHz, VOUT = 2 V p-p, ADA4807-2,
ADA4807-4
−141
−112
−95
dBc
dBc
dBc
dBc
−84
Third Harmonic (HD3)
fC = 1 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p
f = 0.1 Hz to 10 Hz
f = 100 kHz
−144
−115
−79
160
3.1
3.3
5.8
29
0.7
dBc
dBc
dBc
Peak-to-Peak Noise
Input Voltage Noise
nV p-p
nV/√Hz
nV/√Hz
nV/√Hz
Hz
pA/√Hz
pA/√Hz
kHz
f = 1 kHz
f = 10 Hz
Input Voltage Noise 1/f Corner
Input Current Noise
f = 100 kHz
f = 10 Hz
10
2
Input Current Noise 1/f Corner
DC PERFORMANCE
Input Offset Voltage
−VS ≤ VICM ≤ +VS − 1.5 V
ADA4807-1, ADA4807-2
ADA4807-4
ADA4807-1, ADA4807-2
ADA4807-4
−VS ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
−VS ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
−VS ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
−VS ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
−VS ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
−125
−175
−750
−850
20
20
+125
+175
+750
+850
3.7
−1.6
1000
3.6
μV
μV
μV
μV
μV/°C
μA
nA
nA/°C
nA
nA
+VS − 1.5 V ≤ VICM ≤ +VS
140
140
0.7
−1.2
530
2.5
8
25
30
130
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
100
150
250
Input Offset Current Drift
Open-Loop Gain
pA/°C
dB
120
INPUT CHARACTERISTICS
Common-Mode Input Resistance
Differential Input Resistance
Common-Mode Input Capacitance
Differential Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio (CMRR)
45
35
1
MΩ
kΩ
pF
pF
V
1
−VS − 0.2
96
+VS + 0.2
VICM = −3 V to +2 V
110
dB
Rev. B | Page 3 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DISABLE CHARACTERISTICS1
DISABLE Input Voltage2
Low
High
Disabled
Enabled
<1.3
>1.7
V
V
DISABLE Input Current
Low
High
Disabled
Enabled
−470
−3
1.3
nA
nA
μs
DISABLE On Time
DISABLE input midswing point to >90%
of final VOUT, VPD = +VS
1.8
DISABLE Off Time
DISABLE input midswing point to <10%
of enabled quiescent current, VPD = −VS
270
340
ns
OUTPUT CHARACTERISTICS
Saturated Output Voltage Swing
High
RLOAD = 1 kΩ
+VS − 0.08
−VS + 0.1
+VS − 0.04
−VS + 0.07
50
60
80
V
V
mA
mA
mA
Low
Linear Output Current3
Sourcing, G = +1, VIN = +VS, RLOAD = varied
Sinking, G = +1, VIN = −VS, RLOAD = varied
Sourcing, G = +1, VIN =+VS, RLOAD= 0 Ω to
10 Ω
Short-Circuit Current
Sinking, G= +1, VIN = −VS, RLOAD = 0 Ω to 10 Ω
CLOAD = 15 pF, VOUT = 20 mV p-p
80
17
mA
% overshoot
Capacitive Load Drive
POWER SUPPLY
Operating Range
2.7
11
V
Quiescent Current per Amplifier
Enabled, no load, TA = 25°C
Disabled, TA = 25°C
1.0
2.4
1.1
4.0
mA
μA
Power Supply Rejection Ratio (PSRR)
Positive
Negative
+VS = 3 V to 5 V, −VS = −5 V
+VS = 5 V, −VS = −3 V to −5 V
98
98
107
120
dB
dB
1
DISABLE
DISABLE1 DISABLE2
or
DISABLE
for the ADA4807-2 LFCSP package, hereafter referred to as for the ADA4807-1/ADA4807-2.
The disable pin is
on the ADA4807-1 and
2 See the Disable Circuitry section.
3 See Figure 53 and Figure 56.
Rev. B | Page 4 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
5 V SUPPLY
TA = 25°C, VS = 5 V, RLOAD = 1 kΩ to midsupply, RF = 0 ꢀ, G = +1, 0 V ≤ VICM ≤ +VS − 1.5 V, unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, VOUT = 20 mV p-p
G = +1, VOUT = 2 V p-p
G = +1, VOUT = 2V step, 20% to 80%, rise/fall
G = +1, VOUT = 2 V step
170
28
145/160
40
MHz
MHz
V/μs
ns
Slew Rate
Settling Time to 0.1%
DISTORTION/NOISE PERFORMANCE
Second Harmonic (HD2)
fC = 1 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p, ADA4807-1
fC = 1 MHz, VOUT = 2 V p-p, ADA4807-2,
ADA4807-4
−141
−111
−93
dBc
dBc
dBc
dBc
−83
Third Harmonic (HD3)
fC = 1 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p
f = 0.1 Hz to 10 Hz
f = 100 kHz
−153
−115
−78
160
3.1
3.3
5.8
29
0.7
dBc
dBc
dBc
Peak-to-Peak Noise
Input Voltage Noise
nV p-p
nV/√Hz
nV/√Hz
nV/√Hz
Hz
pA/√Hz
pA/√Hz
kHz
f = 1 kHz
f = 10 Hz
Input Voltage Noise 1/f Corner
Input Current Noise
f = 100 kHz
f = 10 Hz
10
2
Input Current Noise 1/f Corner
DC PERFORMANCE
Input Offset Voltage
0 V ≤ VICM ≤ +VS − 1.5 V
ADA4807-1, ADA4807-2
ADA4807-4
ADA4807-1, ADA4807-2
ADA4807-4
0 V ≤VICM ≤ +VS − 1.2 V, TMIN to TMAX
0 V ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
0 V ≤VICM ≤ +VS − 1.2 V, TMIN to TMAX
0 V ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
0 V ≤VICM ≤ +VS − 1.2 V, TMIN to TMAX
−125
−175
−720
−850
20
20
+125
+175
+720
+850
3.7
−2.0
1000
3.8
μV
μV
μV
μV
μV/°C
μA
nA
nA/°C
nA
nA
+VS − 1.5 V ≤ VICM ≤ +VS
110
110
0.7
−1.2
500
2.6
8
25
30
130
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
100
150
250
Input Offset Current Drift
Open-Loop Gain
pA/°C
dB
113
INPUT CHARACTERISTICS
Common-Mode Input Resistance
Differential Input Resistance
Common-Mode Input Capacitance
Differential Input Capacitance
Input Common-Mode Voltage Range
CMRR
45
35
1
MΩ
kΩ
pF
pF
V
1
−VS − 0.2
96
+VS + 0.2
VICM = 1 V to 3 V
110
dB
Rev. B | Page 5 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DISABLE CHARACTERISTICS1
DISABLE Input Voltage2
Low
High
Disabled
Enabled
<1.3
>1.8
V
V
DISABLE Input Current
Low
High
Disabled
Enabled
−360
−1.3
450
nA
nA
ns
DISABLE On Time
DISABLE input midswing point to >90%
of final VOUT, VPD = +VS
DISABLE input midswing point to <10%
of enabled quiescent current, VPD = −VS
700
450
DISABLE Off Time
270
ns
OUTPUT CHARACTERISTICS
Saturated Output Voltage Swing
High
RLOAD = 1 kΩ
+VS − 0.05
−VS + 0.05
+VS − 0.03
−VS + 0.04
50
60
80
V
V
mA
mA
mA
Low
Linear Output Current3
Sourcing, G = +1, VIN = +VS, RLOAD = varied
Sinking, G = +1, VIN = −VS, RLOAD = varied
Sourcing, G = +1, VIN = +VS, RLOAD = 0 Ω
to 10 Ω
Short-Circuit Current
Sinking, G = +1, VIN = −VS, RLOAD = 0 Ω to
10 Ω
CLOAD = 15 pF, VOUT = 20 mV p-p
80
24
mA
Capacitive Load Drive
POWER SUPPLY
% overshoot
Operating Range
2.7
11
V
Quiescent Current per Amplifier
Enabled, no load, TA = 25°C
Disabled, TA = 25°C
950
1.3
1000
2.0
μA
μA
PSRR
Positive
Negative
+VS = 1.5 V to 3.5 V, −VS = −2.5 V
+VS = 2.5 V, −VS = −1.5 V to −3.5 V
98
98
115
130
dB
dB
1
DISABLE
DISABLE1 DISABLE2
or
DISABLE
for the ADA4807-2 LFCSP package, hereafter referred to as for the ADA4807-1/ADA4807-2.
The disable pin is
on the ADA4807-1 and
2 See the Disable Circuitry section.
3 See Figure 53 and Figure 56.
Rev. B | Page 6 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
3 V SUPPLY
TA = 25°C, VS = 3 V, RLOAD = 1 kΩ to midsupply, RF = 0 ꢀ, G = +1, 0 V ≤ VICM ≤ +VS − 1.5 V, unless otherwise noted.
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = +1, VOUT = 20 mV p-p
G = +1, VOUT = 2 V p-p
G = +1, VOUT = 2 V step, 20% to 80%, rise/fall
G = +1, VOUT = 2 V step
165
28
118/237
40
MHz
MHz
V/μs
ns
Slew Rate
Settling Time to 0.1%
DISTORTION/NOISE PERFORMANCE
Second Harmonic (HD2)
fC = 1 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p
fC = 1 kHz, VOUT = 2 V p-p
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p
f = 0.1 Hz to 10 Hz
f = 100 kHz
−98
−85
−65
−94
−91
−68
160
3.1
3.3
5.8
29
dBc
dBc
dBc
dBc
dBc
dBc
nV p-p
nV/√Hz
nV/√Hz
nV/√Hz
Hz
pA/√Hz
pA/√Hz
kHz
Third Harmonic (HD3)
Peak-to-Peak Noise
Input Voltage Noise
f = 10 kHz
f = 10 Hz
Input Voltage Noise 1/f Corner
Input Current Noise
f = 100 kHz
f = 10 Hz
0.7
10
2
Input Current Noise 1/f Corner
DC PERFORMANCE
Input Offset Voltage
0 V ≤ VICM ≤ +VS − 1.5 V
ADA4807-1, ADA4807-2
ADA4807-4
ADA4807-1, ADA4807-2
ADA4807-4
0 V ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
0 V ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
0 V ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
0 V ≤ VICM ≤ +VS − 1.5 V
+VS − 1.5 V ≤ VICM ≤ +VS
0 V ≤ VICM ≤ +VS − 1.2 V, TMIN to TMAX
−125
−175
−720
−850
20
20
+125
+175
+720
+850
3.8
−2.0
1000
3.8
μV
μV
μV
μV
μV/°C
μA
nA
nA/°C
nA
nA
+VS − 1.5 V ≤ VICM ≤ +VS
125
125
0.7
−1.2
500
2.7
8
25
40
113
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
130
150
230
Input Offset Current Drift
Open-Loop Gain
pA/°C
dB
104
INPUT CHARACTERISTICS
Common-Mode Input Resistance
Differential Input Resistance
Common-Mode Input Capacitance
Differential Input Capacitance
Input Common-Mode Voltage Range
CMRR
45
35
1
MΩ
kΩ
pF
pF
V
1
−VS − 0.2
92
+VS + 0.2
VICM = 0.3 V to 1.3 V
110
dB
Rev. B | Page 7 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DISABLE CHARACTERISTICS1
DISABLE Input Voltage2
Low
High
Disabled
Enabled
<1.1
>1.5
V
V
DISABLE Input Current
Low
High
Disabled
Enabled
−325
−500
nA
nA
DISABLE On Time
DISABLE Off Time
DISABLE input midswing point to >90%
of final VOUT, VPD = +VS
DISABLE input midswing point to <10%
of enabled quiescent current, VPD = −VS
500
270
700
460
ns
ns
OUTPUT CHARACTERISTICS
Saturated Output Voltage Swing
High
RLOAD = 1 kΩ
+VS − 0.04
−VS + 0.04
+VS − 0.02
−VS + 0.03
50
60
65
V
V
mA
mA
mA
Low
Linear Output Current3
Sourcing, G = +1, VIN = +VS, RLOAD = varied
Sinking, G = +1, VIN = −VS, RLOAD = varied
Sourcing, G = +1, VIN = +VS, RLOAD = 0 Ω to
10 Ω
Short-Circuit Current
Sinking, G = +1, VIN = −VS, RLOAD = 0 Ω to
10 Ω
CLOAD = 15 pF, VOUT = 20 mV p-p
70
30
mA
Capacitive Load Drive
POWER SUPPLY
% overshoot
Operating Range
2.7
11
V
Quiescent Current per Amplifier
Enabled, no load, TA = 25°C
Disabled, TA = 25°C
915
1.0
1000
2.0
μA
μA
PSRR
Positive
Negative
+VS = 1.5 V to 3.5 V, −VS = −1.5 V
+VS = 1.5 V, −VS = −1.5 V to −3.5 V
97
97
113
130
dB
dB
1
DISABLE
DISABLE1 DISABLE2
or
DISABLE
for the ADA4807-2 LFCSP package, hereafter referred to as for the ADA4807-1/ADA4807-2.
The disable pin is
on the ADA4807-1 and
2 See the Disable Circuitry section.
3 See Figure 53 and Figure 56.
Rev. B | Page 8 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
ABSOLUTE MAXIMUM RATINGS
Table 5.
THERMAL RESISTANCE
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
Supply Voltage
11 V
Internal Power Dissipation
Input Voltage (Common Mode)
Differential Input Voltage
Output Short-Circuit Duration
See Figure 5
VS 0.2 V
1.4 V
See power
derating curves in
Figure 5
Table 6. Thermal Resistance
Package Type
θJA
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
6-Lead SC70, 4-Layer Board
6-Lead SOT-23, 4-Layer Board
8-Lead MSOP
209
223
123
51
10-Lead LFCSP
Storage Temperature Range (All Packages)
Lead Temperature (Soldering 10 sec)
−65°C to +125°C
300°C
14-Lead TSSOP
130
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
4.0
3.5
3.0
2.5
2.0
1.5
LFCSP
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
ADA4807-1/ADA4807-2/ADA4807-4 is limited by the associated
rise in junction temperature. The maximum safe junction
temperature for plastic encapsulated devices is determined by
the glass transition temperature of the plastic, approximately
150°C. Exceeding this limit temporarily can cause a shift in
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure.
1.0 SOT-23
TSSOP
MSOP
SC70
0.5
0
–40 –25 –10
5
20
35
50
65
80
95 110 125
AMBIENT TEMPERATURE (°C)
Figure 5. Maximum Power Dissipation vs. Ambient Temperature for a
4-Layer Board
ESD CAUTION
Although the ADA4807-1/ADA4807-2/ADA4807-4 are
internally short-circuit protected, this may not be sufficient to
guarantee that the maximum junction temperature (150°C) is
not exceeded under all conditions. To ensure proper operation,
it is necessary to observe the power derating curves shown in
Figure 5.
Rev. B | Page 9 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
6
5
4
+V
S
OUT
–V
S
DISABLE
–IN
+IN
Figure 6. ADA4807-1 Pin Configuration
Table 7. ADA4807-1 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
VOUT
−VS
+IN
−IN
DISABLE
+VS
Output
Negative Supply
Noninverting Input
Inverting Input
Active Low Power-Down
Positive Supply
Rev. B | Page 10 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
10 +V
V
1
2
3
4
5
S
OUT1
–IN1
+IN1
9
8
7
6
V
OUT2
–IN2
V
1
2
3
4
8
7
6
5
+V
V
OUT1
S
–IN1
–V
+IN2
OUT2
S
DISABLE1
NOTES
DISABLE2
+IN1
–IN2
+IN2
–V
S
1. THE EXPOSED PAD CAN BE CONNECTED TO
GROUND OR POWER PLANES, OR IT CAN
BE LEFT FLOATING.
Figure 7. ADA4807-2 10-Lead LFCSP Pin Configuration
Figure 8. ADA4807-2 8-Lead MSOP Pin Configuration
Table 8. ADA4807-2 Pin Function Descriptions
Pin No.
10-Lead LFCSP
8-Lead MSOP
Mnemonic
VOUT1
−IN1
+IN1
−VS
DISABLE1
DISABLE2
+IN2
−IN2
VOUT2
Description
1
2
3
4
5
6
7
8
9
10
1
2
3
4
Output 1.
Inverting Input 1.
Noninverting Input 1.
Negative Supply.
Active Low Power-Down 1.
Active Low Power-Down 2.
Noninverting Input 2.
Inverting Input 2.
Output 2.
Not applicable
Not applicable
5
6
7
8
+VS
Positive Supply.
Not applicable
EPAD
Exposed Pad. For the 10-Lead LFCSP, the exposed pad can be connected to ground
or power planes, or it can be left floating.
Rev. B | Page 11 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
1
2
3
4
5
6
7
14
13
V
V
OUT4
OUT1
–IN1
+IN1
–IN4
12 +IN4
11
–V
S
+V
S
ADA4807-4
10
9
+IN3
–IN3
V
+IN2
–IN2
8
V
OUT3
OUT2
Figure 9. ADA4807-4 Pin Configuration
Table 9. ADA4807-4 Pin Function Descriptions
Pin No.
Mnemonic
VOUT1
−IN1
+IN1
+VS
+IN2
−IN2
VOUT2
VOUT3
−IN3
+IN3
−VS
Description
1
2
3
4
5
6
7
8
Output 1
Inverting Input 1
Noninverting Input 1
Positive Supply
Noninverting Input 2
Inverting Input 2
Output 2
Output 3
9
Inverting Input 3
Noninverting Input 3
Negative Supply
Noninverting Input 4
Inverting Input 4
Output 4
10
11
12
13
14
+IN4
−IN4
VOUT4
Rev. B | Page 12 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY RESPONSE
6
3
27
V
= ±2.5V
LOAD
= 20mV p-p
V RANGE = ±2.5V TO ±5V
S
S
24
21
18
15
12
9
200mV p-p
R
= 1kΩ
G = +1
G = +10
G = +5
V
R
= 1kΩ
OUT
LOAD
0
20mV p-p
–3
G = +2
–6
6
3
–9
2V p-p
0
G = +1
–3
–6
–9
–12
–15
–18
–21
–24
–12
–15
–18
–21
–24
G = –1
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
Figure 10. Small Signal Frequency Response for Various Gains,
RF = 499 Ω
Figure 13. Frequency Response for Various Output Amplitudes, G = +1
6
6
V
= 20mV p-p
V
= 2V p-p
OUT
±1.5V
OUT
G = +1
G = +1
3
0
3
0
R
= 1kΩ
R
= 1kΩ
LOAD
LOAD
–3
±5.0V
–3
–6
–9
–6
–12
–15
–18
–21
–24
–27
–30
–9
–12
–15
–18
–21
±5.0V
±1.5V
±2.5V
±2.5V
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
Figure 11. Small Signal Frequency Response for Various Supplies
Figure 14. Large Signal Frequency Response for Various Supplies
6
3
6
–40°C
+25°C
3
0
+85°C
+125°C
0
–3
–6
–9
–3
–6
–12
–9
–40°C
+125°C
–15
–12
–15
–18
–21
–24
–18
+25°C
–21
V
RANGE = ±2.5V TO ±5V
–24
–27
–30
V
RANGE = ±1.5V TO ±5V
S
S
G = +1
= 2V p-p
G = +1
V
R
V
= 20mV p-p
OUT
LOAD
OUT
= 1kΩ
R
= 1kΩ
LOAD
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Small Signal Frequency Response for Various Temperatures
Figure 15. Large Signal Frequency Response for Various Temperatures
Rev. B | Page 13 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
6
6
3
V
V
RANGE = ±2.5V TO ±5V
= 2V p-p
V
V
= ±2.5V
OUT
G = +1
S
S
= 20mV p-p
OUT
3
0
G = +1
0
1kΩ
–3
–3
–6
1kΩ
–6
–9
–9
–12
–15
–18
–21
–24
–27
–30
100Ω
100Ω
–12
–15
–18
–21
–24
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. Small Signal Frequency Response for Various Resistive Loads
Figure 19. Large Signal Frequency Response for Various Resistive Loads
0.6
12
G = +1
LOAD
V
= ±2.5V
S
R
= 1kΩ
0.5
0.4
9
6
G = +1
= 20mV p-p
V
R
OUT
= 1kΩ
LOAD
V
V
RANGE = ±1.5V TO ±5V
OUT
S
0.3
3
= 20mV p-p
0.2
0
0.1
–3
0pF
0
–6
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–9
5pF
–12
–15
–18
–21
–24
V
V
RANGE = ±2.5V TO ±5V
OUT
S
10pF
= 2V p-p
15pF
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
1000
Figure 17. Small Signal Frequency Response for Various Capacitive Loads
Figure 20. 0.1 dB Flatness Frequency Response for Various Output Amplitudes
6
6
V
= ±2.5V
Vs = ±2.5V, ±5V
V = 200mV p-p
OUT
G = 2
F
LOAD
S
G = +1
= 20mV p-p
R
R
= 499Ω
3
0
3
0
V
= 1kΩ
OUT
V
= 0V
CM
R
= 1kΩ
LOAD
Vs = ±2.5V, ±5V
= 20mV p-p
V
OUT
B)
d
–3
–3
N(
AI
–6
G
–6
V
= +V – 0.5V
CM S
P
–9
LO
–9
-
D
–12
–15
–18
–21
–24
E
–12
–15
–18
–21
LOS
Vs = ±2.5V, ±5V
= 2V p-p
C
V
OUT
Vs = ±5V
= 4V p-p
V
OUT
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
Figure 18. Small Signal Frequency Response for
Various Input Common-Mode Voltages (VCM
Figure 21. Frequency Response for Various Output Amplitudes, G = +2
)
Rev. B | Page 14 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
FREQUENCY AND SUPPLY CURRENT
20
–40
–50
V
= ±2.5V
V
= ±2.5V
ON
S
S
G = +1
ΔV
= 0dBm
DISABLE = +V
CM
S
0
–20
–60
–70
–40
–80
–60
–90
OFF
–80
DISABLE = –V
S
–100
–110
–120
–130
–100
–120
–140
0.01
0.1
1
10
100
1000
0.001
0.01
0.1
1
10
100
100
6
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 22. Off Isolation vs. Frequency
Figure 25. CMRR vs. Frequency
120
160
140
120
100
80
–30
–40
V
= ±2.5V
S
V
= ±5V
S
ΔV = –16dBm
S
100
80
60
40
20
0
–50
–PSRR
–60
–70
+PSRR
–80
60
–90
40
–100
–110
–120
–20
–40
20
0
0.001
0.01
0.1
1
10
100
1000
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 23. Open-Loop Gain and Phase vs. Frequency
Figure 26. PSRR vs. Frequency
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5
2.0
DISABLE = –V
S
+I
S
V
= ±5.0V
1.5
S
1.0
0.5
V
= ±1.5V
S
V
= ±2.5V
S
0
–0.5
–1.0
–1.5
–2.0
–I
S
–40 –25 –10
5
20
35
50
65
80
95 110 125
0
1
2
3
4
5
TEMPERATURE (°C)
POWER SUPPLY, ±V (V)
S
Figure 24. Quiescent Supply Current vs. Temperature
DISABLE
Figure 27.
Supply Current vs. Power Supply, VS
Rev. B | Page 15 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
DC AND INPUT COMMON-MODE PERFORMANCE
400
60
50
40
30
20
10
0
NPN
= ±5V
PNP
V
= ±2.5V
S
V
V
V
V
= ±5V
–40°C TO +125°C
COUNT = 361 AMPLIFIERS
x = 0.7µV/°C
S
S
= +V – 0.5V
350
300
250
200
150
100
50
= 0V
CM
S
CM
450 UNITS
x = –32.7µV
σ = 109.4µV
450 UNITS
x = –1.5µV
σ = 17.9µV
σ
= 0.5µV/°C
0
–600
–2.8 –2.2 –1.6 –1.0 –0.4
0.2
0.8
1.4
2.0
2.6
3.2
3.8
–400
–200
0
200
400
600
INPUT REFERRED OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
Figure 28. Input Referred Offset Voltage Distribution for the ADA4807-1 and
ADA4807-2
Figure 31. Input Referred Offset Voltage Drift Distribution, VCM = 0 V
90
NPN
= ±5V
PNP
V
= ±2.5V
S
300
250
200
150
100
50
V
V
V
V
= ±5V
CM
S
S
–40°C TO +125°C
COUNT = 283 AMPLIFIERS
x = 30pA/°C
80
70
60
50
40
30
20
10
0
= +V – 0.5V
= 0V
CM
S
450 UNITS
x = –1.18nA
σ = 22.59nA
450 UNITS
x = –1.58nA
σ = 6.62nA
σ = 35pA/°C
0
–150
–200
–140
–80
–20
40
100
160
220
280
–100
–50
0
50
100
150
INPUT OFFSET CURRENT (nA)
INPUT OFFSET CURRENT DRIFT (pA/°C)
Figure 29. Input Offset Current Distribution
Figure 32. Input Offset Current Drift Distribution, VCM = 0 V
40
30
1.0
V
= ±5.0V
V
= ±5.0V
S
S
10 UNITS
10 UNITS
0.5
0
20
10
0
–0.5
–1.0
–1.5
–10
–20
–30
–40
–
–2.0
–
5.2
–3.9
–2.6
–1.3
0
1.3
2.6
3.9
5.2
5.2
–3.9
–2.6
–1.3
0
1.3
2.6
3.9
5.2
INPUT COMMON-MODE VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
Figure 30. Input Bias Current vs. Input Common-Mode Voltage
Figure 33. Input Offset Current vs. Input Common-Mode Voltage
Rev. B | Page 16 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
300
10
9
25
V
= ±5V
S
OIL BATH TEMPERATURE
24
10 UNITS
8
23
22
21
20
19
18
17
16
15
14
13
200
100
0
7
6
5
4
3
2
1
–100
–200
0
–1
–2
–3
–4
V
= ±2.5V
S
12
11
8 UNITS, SOLDERED TO PCB
100 200 300
TIME (Hours)
–300
–
5.2
–3.9
–
2.6
–
1.3
0
1.3
2.6
3.9
5.2
0
400
500
600
INPUT COMMON-MODE VOLTAGE (V)
Figure 34. Input Referred Offset Voltage vs. Input Common-Mode Voltage
Figure 35. Long-Term Input Offset Voltage (VOS) Drift
Rev. B | Page 17 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
SLEW, TRANSIENT, SETTLING TIME, AND CROSSTALK
280
1.5
1.0
G = +1
LOAD
G = +1
LOAD
R
= 1kΩ
R
= 1kΩ
V
OUT
= ±5V
S
FALLING EDGE
RISING EDGE
260
240
220
200
180
160
140
120
100
V
= 5V p-p
±2.5V
0.5
0
FALLING EDGE
V
OUT
= ±2.5V
= 2V p-p
S
V
–0.5
–1.0
–1.5
±1.5V
RISING EDGE
±5V
–40 –25 –10
5
20
35
50
65
80
95 110 125
0
100
200
300
400
500
600
700
800
900
TEMPERATURE (°C)
TIME (ns)
Figure 36. Slew Rate vs. Temperature
Figure 38. Large Signal Transient Response for Various Supplies
0.5
0.4
0.3
15
10
5
V
= ±2.5V
S
OUTPUT STEP = 2V p-p
0.2
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–5
–10
–15
V
= ±5V
S
OUTPUT STEP = 5V p-p
G = +1
R
= 1kΩ
LOAD
V
RANGE = ±1.5V TO ±5V
S
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
20
40
60
80
90
TIME (µs)
TIME (ns)
Figure 39. Settling Time to 0.1%
Figure 37. Small Signal Transient Response for Various Supplies
Rev. B | Page 18 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
15
10
5
0
–20
V
V
= ±2.5V
, V
V
= ±2.5V
S
S
, V
= 1V p-p
G = +1
OUT2 OUT3 OUT4
G = +1
R
= 1kΩ
LOAD
–40
0pF
–60
5pF
10pF
15pF
V
OUT1
0
–80
–5
–10
–15
–100
–120
–140
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
100
1k
10k
100k
1M
10M
100M
1G
TIME (µs)
FREQUENCY (Hz)
Figure 40. Small Signal Transient Response for Various Capacitive Loads
Figure 42. ADA4807-4 All Hostile Crosstalk
0
V
V
= ±2.5V
OUT
S
= 2V p-p
–20
–40
DISABLE = 2.5V
–60
–80
–100
–120
–140
–160
DRIVING AMP 1
DRIVING AMP 2
0.0001
0.001
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 41. ADA4807-2 Crosstalk vs. Frequency
Rev. B | Page 19 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
DISTORTION AND NOISE
0
–10
–20
G = +1
V
V
V
= ±1.5V
= ±2.5V
= ±5V
G = +1
S
S
S
R
V
= 1kΩ
R
V
= 1kΩ
LOAD
LOAD
= 2V p-p
–20
= 2V p-p
–40
–60
OUT
OUT
HD2
HD3
–30
V
= ±1.5V, HD2
S
–40
–50
V
= ±1.5V, HD3
S
–60
–80
–70
–80
–100
–120
–140
–160
–180
–90
V
= ±5V, HD2
S
–100
–110
–120
–130
–140
–150
–160
–170
V
= ±5V, HD3
S
V
= ±2.5V, HD2
10
S
V
= ±2.5V, HD3
100
S
1
1000
10000
0.001
0.01
0.1
1
10
FREQUENCY (kHz)
FREQUENCY (MHz)
Figure 43. ADA4807-1 Harmonic Distortion vs. Frequency for Various Supplies
Figure 46. ADA4807-2/ADA4807-4 Harmonic Distortion vs. Frequency for
Various Supplies
0
V
V
= ±2.5V
S
–20
= 2V p-p
OUT
G = +1
–20
–40
R
= 1kΩ
LOAD
V
V
= 2V p-p
OUT
–40
–60
= ±2.5V
S
R
= 100Ω
HD2
LOAD
–60
G = +5, HD2
–80
–80
R
= 1kΩ
HD2
LOAD
G = +2, HD2
G = +1, HD2
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
R
= 1kΩ
LOAD
HD3
G = +5, HD3
G = +2, HD3
R
= 100Ω
LOAD
HD3
G = +1, HD3
1
10
100
FREQUENCY (kHz)
1000
10000
1
10
100
FREQUENCY (kHz)
1000
10000
Figure 44. ADA4807-1 Harmonic Distortion vs. Frequency for Various Gains
Figure 47. ADA4807-1 Harmonic Distortion vs. Frequency for Various
Resistive Loads
–40
0
V
= ±2.5V
S
G = + 1
VOUT = 2V p-p
G = +1
LOAD
–50
–60
–10
RLOAD = 1kΩ
f = 100kHz
R
= 1kΩ
–20
–30
V
= 10V
V
= 5V
V
= 3V
S
S
S
–70
f = 1MHz
–40
–80
–50
–90
–60
HD2
HD3
–70
HD2
HD2
HD3
–100
–110
–120
–130
–140
–150
f = 100kHz
f = 1kHz
–80
–90
–100
–110
–120
–130
–140
HD3
9
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
1
2
3
4
5
6
7
8
10
V
(V p-p)
OUT
INPUT COMMON-MODE VOLTAGE (V)
Figure 45. Total Harmonic Distortion vs. Output Voltage (VOUT
)
Figure 48. Harmonic Distortion vs. Input Common-Mode Voltage
Rev. B | Page 20 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
6
5
4
3
2
12
10
8
V
= ±2.5V
V = ±5V
S
S
G = +2
G = +2
R
R
= 499Ω
R
= 499Ω
F
F
= 1kΩ
R
= 1kΩ
LOAD
LOAD
6
4
THD = –80dB
THD = –90dB
THD = –80dB
THD = –90dB
THD = –100dB
THD = –100dB
1
2
ADA4807-1,
ADA4807-2
ADA4807-1,
ADA4807-2
ADA4807-4
ADA4807-4
0
1
0
10
100
FREQUENCY (kHz)
1000
1
10
100
FREQUENCY (kHz)
1000
Figure 49. Output Voltage vs. Frequency for VS = 2.5 V
Figure 51. Output Voltage vs. Frequency for VS = 5 V
1
0.1
V
= ±2.5V
S
G = +1
f = 1kHz
0.01
0.001
0.0001
0.00001
16Ω
32Ω
600Ω
0.001
0.01
0.1
1
OUTPUT VOLTAGE (V rms)
Figure 50. Total Harmonic Distortion vs. Output Voltage for Various
Resistive Loads
Rev. B | Page 21 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
OUTPUT CHARACTERISTICS
100
100
10
1
100
10
1
100
V
RANGE = ±1.5V TO ±5V
V RANGE = ±1.5V TO ±5V
S
NPN ACTIVE
S
PNP ACTIVE
10
10
VOLTAGE NOISE
VOLTAGE NOISE
1
1
CURRENT NOISE
CURRENT NOISE
0.1
0.1
100M
0.1
0.1
100M
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 52. Input Voltage Noise and Current Noise vs. Frequency,
VCM = 0 V
Figure 55. Input Voltage Noise and Current Noise vs. Frequency,
VCM = +VS − 0.5 V
1.8
1.8
V
= ±2.5V
S
V
= ±2.5V
S
G = +1
G = +1
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
+125°C
+85°C
+25°C
+85°C
+25°C
+125°C
–40°C
–40°C
60
0
10
20
30
40
50
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 56. Negative Rail Output Saturation Voltage (−VS + VOUT) vs.
Load Current for Various Temperatures
Figure 53. Positive Rail Output Saturation Voltage (+VS – VOUT) vs.
Load Current for Various Temperatures
1000
1000
V
= ±2.5V
V
= ±2.5V
S
S
DISABLE = –V
DISABLE = +V
S
S
100
10
100
10
1
1
0.1
0.1
0.01
0.01
0.001
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 57. Disabled Output Impedance vs. Frequency
Figure 54. Enabled Output Impedance vs. Frequency
Rev. B | Page 22 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
OVERDRIVE RECOVERY AND TURN ON/TURN OFF TIMES
3
1.5
1.0
3
V
= ±2.5V
V
= ±2.5V
V
S
V
V
S
IN
IN
OUT
V
G = +1
OUT
G = +2
R
= 1kΩ
R
= 1kΩ
LOAD
LOAD
2
1
2
0.5
1
0
0
0
–1
–2
–3
–0.5
–1.0
–1.5
–1
–2
–3
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TIME (µs)
TIME (µs)
Figure 58. Input Overdrive Recovery
Figure 60. Output Overdrive Recovery
1800
1600
1400
1200
1000
800
600
400
200
0
400
350
300
250
200
150
100
G = +1
LOAD
DISABLE = –V TO +V
G = +1
LOAD
DISABLE = +V TO –V
S
R
= 1kΩ
R
= 1kΩ
S
S
S
V
= ±1.5V
S
V
= ±5.0V
V
= ±5.0V
S
S
V
= ±2.5V
S
V
V
= ±2.5V
= ±1.5V
S
S
–40 –25 –10
5
20
35
50
65
80
95 110 125
–40 –25 –10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 59. Turn On Time vs. Temperature and Supply
Figure 61. Turn Off Time vs. Temperature and Supply
Rev. B | Page 23 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
THEORY OF OPERATION
The ADA4807-1/ADA4807-2/ADA4807-4 have a rail-to-rail
input stage with an input range that goes 200 mV beyond either
rail. A PNP transistor input pair is active for a majority of the
input range, while an NPN transistor input pair is active for the
common-mode voltages within 1.3 V of the positive rail. The
ADA4807-1/ADA4807-2/ADA4807-4 are fabricated using the
Analog Devices, Inc., third generation, extra fast complementary
bipolar (XFCB) process resulting in exceptionally good distortion,
noise, slew rate, and settling characteristics for 1 mA devices.
Given traditional rail-to-rail input architecture performance, the
input 1/f noise is surprisingly low, and the current noise is only
0.7 pA/√Hz for a 3 nV/√Hz voltage noise. Typical high slew rate
devices suffer from increased current noise because of input pair
degeneration and higher input stage current. The ADA4807-1/
ADA4807-2/ADA4807-4 exceed current benchmark parameters
given the performance of the XFCB process.
The rail-to-rail input stage is useful in many different applications.
Although the precision is reduced from input to input, many
applications can tolerate this loss when the alternative is no
functionality at all. The positive rail input range is indispensable
for servo loops with a high-side input range
The ADA4807-1/ADA4807-2/ADA4807-4 input operates 200 mV
beyond either rail. Internal protection circuitry prevents the output
from phase inverting when the input range is exceeded. When
the input exceeds a diode beyond either rail, internal electrostatic
discharge (ESD) protection diodes source or sink current through
the input.
I2
I1
Q51
Q42
Q47
DIFFERENTIAL
DRIVE
Q37
Q38
FROM
Q68
INPUT STAGE
C9
The multistage design of the ADA4807-1/ADA4807-2/
ADA4807-4 has excellent precision specifications, such as input
drift, offset, open-loop gain, CMRR, and PSRR. Typical harmonic
distortion numbers fall in the range of −130 dBc for a 10 kHz
fundamental (see the Distortion and Noise section). This level of
performance makes the ADA4807-1/ADA4807-2/ADA4807-4 the
best choices when driving 18-bit precision converters.
Q20
R29
Q27
Q21
V
OUT
Q43
Q48
C5
Q49
I4
I5
Q50
Q44
The ADA4807-1/ADA4807-2 are optimized for a low shutdown
current (4 μA maximum), in the order of a few microamperes. In
power sensitive applications, this can eliminate the use of a power
FET and enable time interleaved power saving operation schemes.
Figure 62. Differential Drive from Input Stage
+V
S
R1
R2
I2
Q9
1.3V
V
Q3
Q2
R5
IN
Q8
Q7
Q5
V
BIAS1
V
Q13
Q17
IP
OUTPUT STAGE,
COMMON-MODE
FEEDBACK
Q14
Q11
V
BIAS2
R3
R4
I1
5µA
Q18
Q4
–V
S
Figure 63. Simplified Schematic
Rev. B | Page 24 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
heating. If large differential voltages must be sustained across the
input terminals, it is recommended that the current through the
input clamps be limited to less than 10 mA. Series input resistors
sized appropriately for the expected differential overvoltage
provide the needed protection.
DISABLE CIRCUITRY
DISABLE
When the
if the logic leakage currents exceed 300 nA. For a 10 V supply,
DISABLE
pin is an option, a pull-up resistor is required
pulling the
ADA4807-2 off, which reduces the supply current to 2.4 µA.
DISABLE
pin to below 6.3 V turns the ADA4807-1/
+V
S
Conversely, pulling the
pin voltage to above 6.6 V
enables the ADA4807-1/ADA4807-2 with a quiescent current of
1 mA. When the ADA4807-1/ADA4807-2 device is disabled, its
output enters a high impedance state. Figure 64 and Table 10
BIAS
ESD
+INx
ESD
ESD
ESD
–INx
DISABLE
show the
functionality over the complete supply range.
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
–V
S
TO THE REST OF THE AMPLIFIER
NOTES
1. THE ±INx PINS ARE ±IN ON THE ADA4807-1,
±IN1 AND ±IN2 ON THE ADA4807-2,
AND ±IN1 TO ±IN4 ON THE ADA4807-4.
Figure 65. Input Stage and Protection Diodes
NOISE CONSIDERATIONS
Figure 66 illustrates the primary noise contributors for the typical
gain configurations. The total output noise (VN_OUT) is the root
sum square of all the noise contributions.
V
V
V
TH
ON
OFF
= V +150mV
TH
= V –150mV
TH
V
_ R =
4kT × R
F
R
N
F
F
3
4
5
6
7
8
9
10
POWER SUPPLY, V (V)
S
ven
R
V
_ R
=
G
G
S
4kT × R
N
G
DISABLE
Figure 64.
Trigger Voltage
+ vout_en –
ien
iep
Table 10. Threshold Voltages for Disabled and Enabled Modes
R
V
_ R =
S
4kT × R
N
S
Mode
+3 V
+5 V
1.6 V
1.3 V
+10 V
6.6 V
6.3 V
5 V
1.6 V
1.3 V
+7 V/−2 V
Enabled
Disabled
1.35 V
1.05 V
3.6 V
3.3 V
Figure 66. Noise Sources in Typical Gain Configurations
Source resistance noise, amplifier input voltage noise, and the
voltage noise from the amplifier input current noise (IN+ × RS)
are all subject to the noise gain term (1 + RF/RG).
The output impedance decreases as the frequency increases. When
disabled, a forward isolation of 120 dB is achieved at 100 kHz (see
DISABLE
Figure 22). ESD clamps protect the
pin, as shown in
Figure 65. Voltages beyond the power supplies cause these diodes
to conduct. To avoid excessive current in the ESD diodes, ensure
Calculate the output noise spectral density using the following
equation:
DISABLE
that the voltage to the
pin is not 0.7 V greater than the
2
2
RF
RG
RF
RG
2
2
positive supply or that it is not 0.7 V less than the negative supply.
If an overvoltage condition is expected, limit the input current to
less than 10 mA with a series resistor.
VN
=
4kTRF + 1+
[
4kTRs + IN+2RS2 +VN
]
+
4kTRG + IN−2 RF
_
OUT
where:
k is Boltzmann’s constant.
T is the absolute temperature in degrees Kelvin.
RF and RG are the feedback network resistances, as shown in
Figure 66.
INPUT PROTECTION
The ADA4807-1/ADA4807-2/ADA4807-4 are fully protected
from ESD events, withstanding human body model ESD events
of 3 kV and charged device model events of 1.25 kV with no
measured performance degradation. The precision input is
protected with an ESD network between the power supplies and
diode clamps across the input device pair, as shown in Figure 65.
RS is the source resistance, as shown in Figure 66.
IN+ and IN− represent the amplifier input current noise spectral
density in pA/√Hz.
VN is the amplifier input voltage noise spectral density in nV/√Hz.
For differential voltages above approximately 1.2 V at room
temperature and 0.8 V at 125°C, the diode clamps begin to
conduct. Too much current can cause damage due to excessive
Rev. B | Page 25 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
APPLICATIONS INFORMATION
CAPACITIVE LOAD DRIVE
LOW NOISE FET OPERATIONAL AMPLIFIER
Figure 67 shows the schematic for driving large capacitive loads, and
Figure 68 shows the frequency response for a gain of +2. Note that
the bandwidth decreases with larger capacitive loads (see Figure 68).
Low noise amplifiers for photodiode, piezoelectric, and other
instrumentation applications typically call for circuit parameters
such as extremely high input impedance, low 1/f noise, or sub-
picoamp bias currents that can be met only with a discrete
amplifier design.
Figure 69 shows the required series resistor (RSERIES) when
limiting the peaking to 3 dB for a range of load capacitors
(CLOAD) at a gain of +2. From Figure 69, no series resistors are
necessary to maintain stability for larger capacitors.
The discrete amplifier shown in Figure 70 uses a high-speed op
amp preceded by a differential amplifier stage. This discrete config-
uration is implemented with dual matched JFETs, which provide
high input impedance and some initial gain, reducing the noise
and precision specifications of the second stage. The low current
consumption of the ADA4807-1/ADA4807-2/ADA4807-4, in
addition to their precision and low noise characteristics, results
in a composite design with 7 mA of total supply current,
1.5 nV/√Hz noise at 1 kHz, and 4 nV/√Hz noise at 10 Hz.
R
F
R
G
V
R
V
OUT
SERIES
LOAD
V
IN
C
LOAD
R
LOAD
R
T
49.9Ω
Figure 67. Schematic for Driving Large Capacitive Loads
6
3
The unbalanced output impedance of the FETs is negated by
the use of an inverting amplifier cascode. The ADA4807-1/
ADA4807-2/ADA4807-4 are ideally suited for the cascode due
to their rail-to-rail input structure, which results in excellent
overload behavior of the overall discrete amplifier. Using this
cascode structure, the CMRR is greater than 100 dB.
15pF, 100Ω
47pF, 82.5Ω
470pF, 20Ω
1nF, 10.5Ω
0
–3
–6
10nF, 1.69Ω
100nF, 0.5Ω
A high output impedance current source is also needed to
maintain the CMRR of the discrete amplifier. An ADR510
maintains a precise current over the supply voltage, and the low
collector capacitance of the PMP4201 results in a balanced and
predictable slew rate behavior. This is shown in Figure 71 with a
0.4 V p-p input and a 4 V p-p output with a gain of 10. Figure 72
shows output referred total harmonic distortion plus noise
(THD + N) for a gain of 10.
–9
–12
–15
–18
V
= ±5V
S
R
= 1kΩ
LOAD
G = +2
V
= 70mV p-p
OUT
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 68. Frequency Response for Driving Large Capacitive Loads,
RF = RG = 249 Ω
100
90
80
70
60
50
40
30
20
10
0
0.001
0.01
0.1
1
10
100
C
(nF)
LOAD
Figure 69. Required Series Resistor (RSERIES) vs. Capacitive Load (CLOAD
)
at 3 dB Peaking
Rev. B | Page 26 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
C7
27pF
R0
100Ω
Rb
V
OS
100Ω
V
TRIM
TRIM
OS
C0
20pF
R1
10Ω
R13
100Ω
R12
100Ω
+5V
–
+
V
OUT
–5V
ADA4807-1/
ADA4807-2/
ADA4807-4
+5V
–5V
C9
2pF
R4
5kΩ
ADA4807-1/
ADA4807-2/
ADA4807-4
+
–
V+
V–
1/2 LSK489
+5V
1/2 LSK489
R2
100Ω
R3
1kΩ
R6
5kΩ
qn1
qn0
1/2 PMP4201
1/2 PMP4201
R7
200Ω
ADR510
–5V
Figure 70. Low Noise FET Operational Amplifier Schematic
POWER MODE ADC DRIVER
One of the merits of a SAR ADC, such as the AD7980, is that its
power scales with the sampling rate. This power scaling makes
SAR ADCs very power efficient, especially when running at a
low sampling frequency. However, the ADC driver used with
the SAR ADC traditionally consumes constant power regardless
of the sampling frequency.
1
2
Figure 73 illustrates a method by which the quiescent power of
the ADC driver can be reduced by 95% while still maintaining
the input signal to the ADC. Both the ADA4807-1/ADA4807-2/
ADA4807-4 and the AD8603 are rail-to-rail input and output
(RRIO) amplifiers and can operate on a single 5 V analog supply.
Connecting the AD8603 in parallel with a sharing resistor allows
the ADA4807-1/ADA4807-2/ADA4807-4 to be powered down,
reducing the total supply current for the driver from 1 mA to
50 μA. The sampling frequency of the AD7980 can then be
reduced to match the power consumption of the AD8603. With
the ADA4807-1/ADA4807-2/ADA4807-4 powered on, the SNR
and THD are 84.1 dB and −100.3 dB for a 3 V p-p, 1 kHz input
and a 4.096 V reference. The SNR and THD degrade to 81.4 dB
and −77.3 dB for the same input signal in the low power mode
when only the AD8603 is on.
CH1 200mV
CH2 1V
Ω
M100ns
A CH1
0V
Figure 71. Pulse Response, G = 10, 4 V p-p Output
–60
–65
–70
–75
–80
–85
–90
–95
One issue with this method is that the reference and reference
buffer power do not scale with the ADC or the driver. This
makes this configuration most useful in multichannel systems
where the reference can be reused across many inputs.
Alternately, the reference buffer can be scaled in the same
fashion as the input driver; however, the reference itself must
remain on in any of the modes.
–100
–105
–110
100
1k
10k
20k
FREQUENCY (Hz)
Figure 72. 8 V p-p Output, THD + N for G = 10, RLOAD = 600 Ω
Rev. B | Page 27 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
5V
5V
–
+
ADA4807-1/
ADA4807-2/
ADA4807-4
ADR4540
C3
10µF
C2
0.1µF
C4
0.1µF
LP MODE
5V
R10
–
ADA4807-1/
ADA4807-2/
ADA4807-4
22Ω
REF
IN+
IN–
AD7980
C1
2.7µF
V
+
IN
R11
49.9Ω
GND
5V
–
+
AD8603
Figure 73. Dual Power Mode ADC Driver
Figure 76 shows the ADA4807-1/ADA4807-2/ADA4807-4
configured to convert a single-ended to differential signal and
drive an 18-bit ADC. This configuration results in an ENOB of
15.3. The FFT is shown in Figure 77.
ADC DRIVING
The ADA4807-1/ADA4807-2/ADA4807-4 can be used in ADC
driving applications. Figure 74 is a simplified schematic of the
ADA4807-1/ADA4807-2/ADA4807-4 driving an 18-bit differential
ADC, the AD7982, in a fully differential signal chain. This configu-
ration results in an effective number of bits (ENOB) of 15.7; results
are shown in Figure 75.
20Ω
V
2.7nF
IN
ADA4807-1/
ADA4807-2/
ADA4807-4
IN+
IN–
ADA4807-1/
ADA4807-2/
ADA4807-4
ADC
1kΩ
1kΩ
20Ω
V
IN+
20Ω
REF
2
2.7nF
2.7nF
ADA4807-1/
ADA4807-2/
ADA4807-4
IN+
IN–
ADC
20Ω
Figure 76. Schematic for Driving the AD7982 Differential Converter from a
Single-Ended Input Signal, +VS = +7 V, −VS = −1 V
V
2.7nF
IN–
0
ADA4807-1/
ADA4807-2/
ADA4807-4
fs = 200kSPS
fIN = 1kHz
–20
SNR = 94.5dB
THD = –110.3dB
–40
–60
SFDR = –111.1dB
SINAD = 94.4dB
Figure 74. Schematic for Driving the AD7982, +VS = +7 V, −VS = −1 V
0
fs = 200kSPS
fIN = 1kHz
–20
–80
SNR = 96.6dB
THD = –111.5dB
–40
–60
SFDR = –112.3dB
SINAD = 96.5dB
–100
–120
–140
–160
–180
–80
–100
–120
–140
–160
–180
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
Figure 77. FFT for Driving a Single-Ended Input Signal into a Differential
Converter
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
Figure 75. FFT for Driving a Differential Converter, −0.5 dBFS
Rev. B | Page 28 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
ADC DRIVING WITH DYNAMIC POWER SCALING
CONV
In power sensitive applications, the ADA4807-1/ADA4807-2
can be switched on prior to the ADC turning on. Figure 78
shows the timing diagram for dynamically power scaling the
ADA4807-1/ADA4807-2 with the AD7982 configuration shown in
1
DISABLE
DISABLE
Figure 79. The falling edge of the
signal must align
with the rising edge of the CONV signal of the ADC to obtain a
clean data acquisition. Figure 79 gives the FFT for driving a fully
differential signal chain with a 1.2 µs on time as shown in Figure 78.
With this method, the ADA4807-1/ADA4807-2 quiescent current
(per amplifier) is reduced from 2 mA to 0.25 mA. Figure 81 gives
the FFT for dynamically power scaling a single-ended input
signal chain into a differential ADC with a 4 µs on time as
shown in Figure 80. This configuration results in a quiescent
current reduction of 20%.
2
CH1 2V
CH2 2V M1µs
A CH1
2.56V
Figure 80. Dynamic Power Scaling Timing Diagram for Driving a Single-
Ended Input Signal Chain into a Differential ADC (AD7982)
0
fs = 200kSPS
fIN = 1kHz
–20
SNR = 94.7dB
CONV
THD = –107.11dB
SFDR = –108.8dB
SINAD = 94.4dB
–40
–60
1
–80
DISABLE
–100
–120
–140
–160
–180
2
0
2
4
6
8
10
12
14
16
18
20
CH1 2V
CH2 2V M1µs
A CH1
2.56V
FREQUENCY (kHz)
Figure 78. Dynamic Power Scaling Timing Diagram for Driving a Fully
Differential Signal Chain into a Differential ADC (AD7982)
Figure 81. FFT for Driving a Single-Ended to Differential Converter Using
Dynamic Power Scaling, −0.5 dBFS, On Time of 4 µs, for the Schematic Shown in
Figure 76
0
fs = 200kSPS
fIN = 1kHz
–20
SNR = 96.7dB
THD = –110.9dB
SFDR = –111.8dB
SINAD = 96.6dB
–40
–60
–80
–100
–120
–140
–160
–180
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
Figure 79. FFT for Driving a Differential Converter using Dynamic Power Scaling,
−0.5 dBFS, On Time of 1.2 µs, for the Schematic Shown in Figure 74
Rev. B | Page 29 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
high frequencies, resulting in excessive gain peaking or possible
oscillation. Signal routing must be short and direct to avoid such
parasitic effects. Provide symmetrical layout for complementary
signals to maximize balanced performance.
LAYOUT, GROUNDING, AND BYPASSING
The ADA4807-1/ADA4807-2/ADA4807-4 are high speed
devices. Realizing their superior performance requires attention
to the details of high speed printed circuit board (PCB) design.
Use radio frequency transmission lines to connect the driver
and receiver to the amplifier.
The first requirement is to use a multilayer PCB with solid ground
and power planes that cover as much of the board area as possible.
Minimize stray capacitance at the input and output pins by
clearing the underlying ground and low impedance planes
near these pins.
Bypass each power supply pin directly to a nearby ground plane,
as close to the device as possible. Use 0.1 µF high frequency
ceramic chip capacitors.
If the driver and receiver are more than one-eighth of the
wavelength from the amplifier, minimize the signal trace
widths. This nontransmission line configuration requires
clearing of the underlying and adjacent ground and low
impedance planes near the signal lines.
Provide low frequency bulk bypassing using 10 µF tantalum
capacitors from each supply to ground.
Stray transmission line capacitance in combination with
package parasitics can potentially form a resonant circuit at
Rev. B | Page 30 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
OUTLINE DIMENSIONS
2.20
2.00
1.80
2.40
2.10
1.80
6
1
5
2
4
3
1.35
1.25
1.15
0.65 BSC
1.30 BSC
1.00
0.90
0.70
0.40
0.10
1.10
0.80
0.46
0.36
0.26
0.22
0.08
SEATING
PLANE
0.10 MAX
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 82. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
3.00
2.90
2.80
6
1
5
2
4
3
3.00
2.80
2.60
1.70
1.60
1.50
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
4°
0°
SEATING
PLANE
0.60
BSC
0.50 MAX
0.30 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 83. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
Rev. B | Page 31 of 33
ADA4807-1/ADA4807-2/ADA4807-4
Data Sheet
3.20
3.00
2.80
8
5
4
5.15
4.90
4.65
3.20
3.00
2.80
1
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 84. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
0.50 BSC
2.90
10
6
PIN 1 INDEX
AREA
EXPOSED
PAD
1.74
1.64
1.49
0.50
0.40
0.30
0.20 MIN
1
5
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 85. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
Rev. B | Page 32 of 33
Data Sheet
ADA4807-1/ADA4807-2/ADA4807-4
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 86. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Branding
H3J
H3J
H3J
H3J
ADA4807-1AKSZ-R2
ADA4807-1AKSZ-R7
ADA4807-1ARJZ-R2
ADA4807-1ARJZ-R7
ADA4807-2ACPZ-R2
ADA4807-2ACPZ-R7
ADA4807-2ARMZ
6-Lead Thin Shrink Small Outline Transistor Package [SC70]
6-Lead Thin Shrink Small Outline Transistor Package [SC70]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board for 6-Lead SC70
KS-6
KS-6
RJ-6
RJ-6
CP-10-9
CP-10-9
RM-8
RM-8
RU-14
RU-14
H3S
H3S
H3S
H3S
ADA4807-2ARMZ-R7
ADA4807-4ARUZ
ADA4807-4ARUZ-R7
ADA4807-1AKSZ-EBZ
ADA4807-1ARJZ-EBZ
ADA4807-2ACPZ-EBZ
ADA4807-2ARMZ-EBZ
ADA4807-4AURZ-EBZ
Evaluation Board for 6-Lead SOT-23
Evaluation Board for 10-Lead LFCSP_WD
Evaluation Board for 8-Lead MSOP
Evaluation Board for 14-Lead TSSOP
1 Z = RoHS Compliant Part.
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12611-0-9/15(B)
Rev. B | Page 33 of 33
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