ADA4938-1_15 [ADI]
Ultralow Distortion Differential ADC Driver;
| 型号： | ADA4938-1_15 |
| 厂家： | 
ADI |
| 描述： | Ultralow Distortion Differential ADC Driver |
| 文件： | 总28页 (文件大小：573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Distortion
Differential ADC Driver
ADA4938-1/ADA4938-2
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Extremely low harmonic distortion (HD)
−106 dBc HD2 @ 10 MHz
−82 dBc HD2 @ 50 MHz
−109 dBc HD3 @ 10 MHz
−82 dBc HD3 @ 50 MHz
Low input voltage noise: 2.6 nV/√Hz
High speed
ADA4938-1
12 PD
–FB
+IN
–IN
1
2
3
4
11 –OUT
10 +OUT
+FB
9 V
OCM
−3 dB bandwidth of 1000 MHz, G = +1
Slew rate: 4700 V/μs
0.1 dB gain flatness to 150 MHz
Fast overdrive recovery of 4 ns
1 mV typical offset voltage
Figure 1. ADA4938-1 Functional Block Diagram
Externally adjustable gain
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Wide supply voltage range: +5 V to 5 V
Single or dual amplifier configuration available
–IN1
+FB1
1
2
3
4
5
6
18 +OUT1
17 V
OCM1
16 –V
+V
S2
S2
S1
ADA4938-2
–V
15
14
+V
S1
–FB2
+IN2
PD2
13 –OUT2
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Figure 2. ADA4938-2 Functional Block Diagram
–50
–60
G = +2, V
G = +2, V
G = +2, V
G = +2, V
= 5V p-p
= 3.2V p-p
= 2V p-p
= 1V p-p
O, dm
O, dm
O, dm
O, dm
Line drivers
–70
GENERAL DESCRIPTION
–80
The ADA4938-x is a low noise, ultralow distortion, high speed
differential amplifier. It is an ideal choice for driving high per-
formance ADCs with resolutions up to 16 bits from dc to 27 MHz,
or up to 12 bits from dc to 74 MHz. The output common-mode
voltage is adjustable over a wide range, allowing the ADA4938 to
match the input of the ADC. The internal common-mode
feedback loop also provides exceptional output balance as well
as suppression of even-order harmonic distortion products.
–90
–100
–110
–120
–130
1
10
FREQUENCY (MHz)
100
Full differential and single-ended-to-differential gain configurations
are easily realized with the ADA4938-x. A simple external feedback
network of four resistors determines the closed-loop gain of the
amplifier.
Figure 3. SFDR vs. Frequency and Output Voltage
The ADA4938-1 (single amplifier) is available in a Pb-free,
3 mm × 3 mm, 16-lead LFCSP. The ADA4938-2 (dual
amplifier) is available in a Pb-free, 4 mm × 4 mm, 24-lead
LFCSP. The pinouts have been optimized to facilitate layout and
minimize distortion. The parts are specified to operate over the
extended industrial temperature range of −40°C to +85°C.
The ADA4938-x is fabricated using the Analog Devices, Inc.,
proprietary third generation, high voltage XFCB process, enabling
it to achieve very low levels of distortion with an input voltage
noise of only 2.6 nV/√Hz. The low dc offset and excellent dynamic
performance of the ADA4938-x make it well-suited for a wide
variety of data acquisition and signal processing applications.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
ADA4938-1/ADA4938-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 19
Analyzing an Application Circuit ............................................ 19
Setting the Closed-Loop Gain .................................................. 19
Estimating the Output Noise Voltage...................................... 19
The Impact of Mismatches in the Feedback Networks......... 20
Calculating the Input Impedance of an Application Circuit 20
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual-Supply Operation ............................................................... 3
Single-Supply Operation ............................................................. 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuts...................................................................................... 17
Terminology .................................................................................... 18
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 20
Terminating a Single-Ended Input .......................................... 21
Setting the Output Common-Mode Voltage.......................... 21
Layout, Grounding, and Bypassing.............................................. 23
High Performance ADC Driving ................................................. 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
10/09—Rev. 0 to Rev. A
Added Settling Time Parameter, Table 1 ....................................... 3
Changes to Linear Output Current Parameter, Table 1............... 3
Added Settling Time Parameter, Table 3 ....................................... 5
Changes to Linear Output Current Parameter, Table 3............... 5
Changes to Figure 5 and Figure 6................................................... 8
Added EP Row to Table 7 and EP Row to Table 8........................ 8
Changes to Figure 41...................................................................... 14
Added New Figure 53, Renumbered Sequentially ..................... 16
Changes to Table 9.......................................................................... 19
Added Exposed Pad Notation to Outline Dimensions ............. 25
Changes to Ordering Guide .......................................................... 25
11/07—Revision 0: Initial Version
Rev. A | Page 2 of 28
ADA4938-1/ADA4938-2
SPECIFICATIONS
DUAL-SUPPLY OPERATION
TA = 25°C, +VS = 5 V, −VS = −5 V, VOCM = 0 V, RT = 61.9 Ω, RG = RF = 200 Ω, G = +1, RL, dm = 1 kꢀ, unless otherwise noted.
All specifications refer to single-ended input and differential output, unless otherwise noted. For gains other than G = +1, values for RF
and RG are shown in Table 11.
±±IN to ±ꢀOU Performance
Table 1.
Parameter
Conditions
Min Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
VOUT = 0.1 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
1000
150
800
4700
6.5
MHz
MHz
MHz
V/μs
ns
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
VIN = 5 V to 0 V step, G = +2
4
ns
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 50 MHz
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 50 MHz
f1 = 30.0 MHz, f2 = 30.1 MHz
f = 30 MHz, RL, dm = 100 Ω
f = 10 MHz
G = +4, f = 10 MHz
f = 10 MHz
f = 100 MHz
−106
−82
−109
−82
89
45
2.6
15.8
4.8
−85
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
dB
pA/√Hz
dB
Third Harmonic
IMD
IP3
Input Voltage Noise
Noise Figure
Input Current Noise
Crosstalk (ADA4938-2)
INPUT CHARACTERISTICS
Offset Voltage
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = 0 V
TMIN to TMAX variation
1
4
−13
−0.01
6
4
mV
μV/°C
μA
μA/°C
MΩ
MΩ
pF
Input Bias Current
Input Resistance
−18
TMIN to TMAX variation
Differential
Common mode
3
1
Input Capacitance
Input Common-Mode Voltage
CMRR
−VS + 0.3 to +VS − 1.6
−75
V
dB
∆VOUT, dm/∆VIN, cm; ∆VIN, cm = 1 V, f = 1 MHz
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
Maximum ∆VOUT; single-ended output
Per amplifier, RL, dm = 20 Ω, f = 10 MHz
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V; f = 10 MHz
−VS + 1.2 to +VS − 1.2
75
−60
V
mA
dB
Rev. A | Page 3 of 28
ADA4938-1/ADA4938-2
VꢀCM to ±ꢀOU Performance
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
230
1700
7.5
MHz
V/μs
nV/√Hz
VIN = −3.4 V to +3.4 V, 25% to 75%
−VS + 1.3 to +VS − 1.3
10
3
0.5
−81
1.00
V
kΩ
mV
μA
dB
V/V
VOS, cm = VOUT, cm; VDIN+ = VDIN− = 0 V
∆VOUT, dm/∆VOCM; ∆VOCM = 1 V
∆VOUT, cm/∆VOCM; ∆VOCM = 1 V
Gain
0.95
4.5
1.05
POWER SUPPLY
Operating Range
Quiescent Current
11
40
V
Per amplifier
TMIN to TMAX variation
Powered down
37
40
2.0
−80
mA
μA/°C
mA
dB
3.0
Power Supply Rejection Ratio
POWER DOWN (PD)
∆VOUT, dm/∆VS; ∆VS = 1 V
PD Input Voltage
Powered down
Enabled
≤2.5
≥3
V
V
Turn-Off Time
Turn-On Time
PD Bias Current
Enabled
1
200
μs
ns
PD = 5 V
1
μA
μA
°C
Disabled
PD = −5 V
−760
OPERATING TEMPERATURE RANGE
−40
+85
Rev. A | Page 4 of 28
ADA4938-1/ADA4938-2
SINGLE-SUPPLY OPERATION
TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = +VS/2, RT = 61.9 Ω, RG = RF = 200 Ω, G = +1, RL, dm = 1 kꢀ, unless otherwise noted.
All specifications refer to single-ended input and differential output, unless otherwise noted. For gains other than G = 1, values for RF and
RG are shown in Table 11.
±±IN to ±ꢀOU Performance
Table 3.
Parameter
Conditions
Min Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
VOUT = 0.1 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
1000
150
750
3900
6.5
MHz
MHz
MHz
V/μs
ns
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
VIN = 2.5 V to 0 V step, G = +2
4
ns
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 50 MHz
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 50 MHz
f = 10 MHz
G = +4, f = 10 MHz
f = 10 MHz
f = 100 MHz
−110
−79
−100
−79
2.6
15.8
4.8
−85
dBc
dBc
dBc
dBc
nV/√Hz
dB
Third Harmonic
Input Voltage Noise
Noise Figure
Input Current Noise
Crosstalk (ADA4938-2)
INPUT CHARACTERISTICS
Offset Voltage
pA/√Hz
dB
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 2.5 V
TMIN to TMAX variation
1
4
−13
−0.01
6
4
mV
μV/°C
μA
μA/°C
MΩ
MΩ
pF
Input Bias Current
Input Resistance
−18
TMIN to TMAX variation
Differential
Common mode
3
1
Input Capacitance
Input Common-Mode Voltage
CMRR
−VS + 0.3 to +VS − 1.6
−80
V
dB
∆VOUT, dm/∆VIN, cm; ∆VIN, cm = 1 V
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
Maximum ∆VOUT; single-ended output
Per amplifier, RL, dm = 20 Ω, f = 10 MHz
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V
−VS + 1.2 to +VS − 1.2
65
−60
V
mA
dB
Rev. A | Page 5 of 28
ADA4938-1/ADA4938-2
VꢀCM to ±ꢀOU Performance
Table 4.
Parameter
Conditions
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
400
1700
7.5
MHz
V/μs
nV/√Hz
VIN = 1.6 V to 3.4 V, 25% to 75%
−VS + 1.3 to +VS − 1.3
10
3
0.5
−89
V
kΩ
mV
μA
dB
V/V
VOS, cm = VOUT, cm; VDIN+ = VDIN– = VOCM = 2.5 V
∆VOUT, dm/∆VOCM; ∆VOCM = 1 V
∆VOUT, cm/∆VOCM; ∆VOCM = 1 V
Gain
0.95 1.00
1.05
POWER SUPPLY
Operating Range
Quiescent Current
4.5
34
11
36.5
V
mA
μA/°C
mA
dB
TMIN to TMAX variation
Powered down
∆VOUT, dm/∆VS; ∆VS = 1 V
40
1.0
−80
1.7
Power Supply Rejection Ratio
POWER DOWN (PD)
PD Input Voltage
Powered down
Enabled
≤2.5
≥3
V
V
Turn-Off Time
Turn-On Time
PD Bias Current
Enabled
1
200
μs
ns
PD = 5 V
PD = 0 V
1
−260
μA
μA
°C
Disabled
OPERATING TEMPERATURE RANGE
−40
+85
Rev. A | Page 6 of 28
ADA4938-1/ADA4938-2
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Table 5.
Parameter
Rating
Supply Voltage
12 V
Power Dissipation
See Figure 4
−65°C to +125°C
−40°C to +85°C
300°C
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
150°C
Airflow increases heat dissipation, which effectively reducing
θJA. In addition, more metal directly in contact with the package
leads/exposed pad from metal traces, through-holes, ground,
and power planes reduces the θJA.
Stresses above those listed under Absolute Maximum Rating
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the ADA4938-1,
16-lead LFCSP (95°C/W) and the ADA4938-2, 24-lead LFCSP
(65°C/W) on a JEDEC standard 4-layer board.
THERMAL RESISTANCE
3.5
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 4-layer circuit board, as described in
EIA/JESD 51-7. The exposed pad is not electrically connected to
the device. It is typically soldered to a pad on the PCB that is
thermally and electrically connected to an internal ground plane.
3.0
2.5
ADA4938-2
2.0
Table 6. Thermal Resistance
Package Type
16-Lead LFCSP (Exposed Pad)
24-Lead LFCSP (Exposed Pad)
1.5
θJA
95
65
Unit
°C/W
°C/W
ADA4938-1
1.0
0.5
0
Maximum Power ±issipation
The maximum safe power dissipation in the ADA4938-x
packages is limited by the associated rise in junction temper-
ature (TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4938. Exceeding a junction
temperature of 150°C for an extended period can result in changes
in the silicon devices, potentially causing failure.
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature, 4-Layer Board
ESD CAUTION
Rev. A | Page 7 of 28
ADA4938-1/ADA4938-2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
PIN 1
INDICATOR
INDICATOR
12 PD
–FB
+IN
–IN
1
2
3
4
–IN1
+FB1
1
2
3
4
5
6
18
17 V
16 –V
15
14
+OUT1
11 –OUT
10 +OUT
ADA4938-1
OCM1
+V
ADA4938-2
TOP VIEW
(Not to Scale)
S2
S2
S1
TOP VIEW
(Not to Scale)
–V
+V
S1
–FB2
+IN2
+FB
9
V
OCM
PD2
13 –OUT2
NOTES
1. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED
TOTHE DEVICE. IT IS TYPICALLY SOLDERED TO GROUND
OR A POWER PLANE ON THE PCB THAT IS THERMALLY
CONDUCTIVE.
NOTES
1. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED
TOTHE DEVICE. IT IS TYPICALLY SOLDERED TO GROUND
OR A POWER PLANE ON THE PCB THAT IS THERMALLY
CONDUCTIVE.
Figure 6. ADA4938-2 Pin Configuration
Figure 5. ADA4938-1 Pin Configuration
Table 7. ADA4938-1 Pin Function Descriptions
Table 8. ADA4938-2 Pin Function Descriptions
Pin No.
Mnemonic Description
Pin No.
Mnemonic
Description
1
2
3
4
−FB
+IN
−IN
+FB
+VS
VOCM
+OUT
−OUT
PD
Negative Output Feedback Pin.
1
2
3, 4
5
6
7
8
9, 10
11
12
−IN1
+FB1
+VS1
−FB2
+IN2
−IN2
+FB2
+VS2
VOCM2
+OUT2
−OUT2
PD2
Negative Input Summing Node 1.
Positive Output Feedback Pin 1.
Positive Supply Voltage 1.
Negative Output Feedback Pin 2.
Positive Input Summing Node 2.
Negative Input Summing Node 2.
Positive Output Feedback Pin 2.
Positive Supply Voltage 2.
Positive Input Summing Node.
Negative Input Summing Node.
Positive Output Feedback Pin.
Positive Supply Voltage.
Output Common-Mode Voltage.
Positive Output for Load Connection.
Negative Output for Load Connection.
Power-Down Pin.
5 to 8
9
10
11
12
Output Common-Mode Voltage 2.
Positive Output 2.
Negative Output 2.
13 to 16 −VS
EP
Negative Supply Voltage.
Exposed Paddle. The exposed pad is not
electrically connected to the device. It is
typically soldered to ground or a
power plane on the PCB that is
thermally conductive.
13
14
Power-Down Pin 2.
−VS2
15, 16
17
18
19
20
Negative Supply Voltage 2.
Output Common-Mode Voltage 1.
Positive Output 1.
Negative Output 1.
Power-Down Pin 1.
VOCM1
+OUT1
−OUT1
PD1
21, 22
23
24
−VS1
−FB1
+IN1
Negative Supply Voltage 1.
Negative Output Feedback Pin 1.
Positive Input Summing Node 1.
EP
Exposed Paddle. The exposed pad is
not electrically connected to the
device. It is typically soldered to
ground or a power plane on the PCB
that is thermally conductive.
Rev. A | Page 8 of 28
ADA4938-1/ADA4938-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −VS = −5 V, VOCM = 0 V, RT = 61.9 Ω, RG = RF = 200 Ω, G = +1, RL, dm = 1 kꢀ, unless otherwise noted.
All measurements were performed with single-ended input and differential output, unless otherwise noted. For gains other than G = +1,
values for RF and RG are shown in Table 11.
3
3
0
0
–3
–6
–9
–12
–3
–6
–9
–12
G = +1
G = +2
G = +3.16
G = +5
G = +1
G = +2
G = +3.16
G = +5
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response for Various Gains, VOUT = 0.1 V p-p
Figure 10. Large Signal Frequency Response for Various Gains
3
3
0
–3
–6
–9
0
–3
–6
–9
V
V
= +5V
= ±5V
V
V
= +5V
= ±5V
S
S
S
S
–12
–12
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. Small Signal Response for Various Supplies, VOUT = 0.1 V p-p
Figure 11. Large Signal Response for Various Supplies
3
3
0
0
–3
–6
–3
–6
–9
–12
–9
–40°C
–40°C
+25°C
+85°C
+25°C
+85°C
–12
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Small Signal Frequency Response for
Various Temperatures, VOUT = 0.1 V p-p
Figure 12. Large Signal Frequency Response for Various Temperatures
Rev. A | Page 9 of 28
ADA4938-1/ADA4938-2
3
3
0
0
–3
–3
–6
–6
–9
–9
–12
–15
–12
–15
–18
–21
R
R
R
= 1kΩ
R
R
R
= 1kΩ
L
L
L
L
L
L
–18
–21
= 100Ω
= 200Ω
= 100Ω
= 200Ω
1
1
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. Small Signal Frequency Response for
Various Loads, VOUT = 0.1 V p-p
Figure 16. Large Signal Frequency Response for Various Loads
3
0
3
0
–3
–6
–3
–6
–9
–12
–9
G = +1
G = +2
G = +3.16
G = +5
G = +1
G = +2
G = +3.16
G = +5
–12
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14. Small Signal Frequency Response for
Various Gains, VS = 5 V, VOUT = 0.1 V p-p
Figure 17. Large Signal Frequency Response for Various Gains, VS = 5 V
6
3
6
3
0
0
–3
–6
–9
–12
–3
–6
G = +1
G = +2
G = +3.16
G = +5
G = +1
G = +2
G = +3.16
G = +5
–9
–12
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Small Signal Response for Various Gains, RF = 402 Ω, VOUT = 0.1 V p-p
Figure 18. Large Signal Response for Various Gains, RF = 402 Ω
Rev. A | Page 10 of 28
ADA4938-1/ADA4938-2
6
3
6
3
0
0
–3
–6
–9
–12
–3
–6
–9
–12
G = +1
G = +2
G = +3.16
G = +5
G = +1
G = +2
G = +3.16
G = +5
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19. Small Signal Frequency Response for Various Gains, RF = 402 Ω,
VS = 5 V, VOUT = 0.1 V p-p
Figure 22. Large Signal Frequency Response for Various Gains, RF = 402 Ω,
VS = 5 V
3
3
0
0
–3
–6
–9
–3
–6
–9
V
V
= +5V
= ±5V
V
V
= +5V
= ±5V
S
S
S
S
–12
–12
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 20. VOUT, cm Small Signal Frequency Response, VOUT = 0.1 V p-p
Figure 23. VOUT, cm Large Signal Frequency Response
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
R
R
R
= 1kΩ
R
R
R
= 1kΩ
L, dm
L, dm
L, dm
L, dm
L, dm
L, dm
= 100Ω
= 200Ω
= 100Ω
= 200Ω
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 21. 0.1 dB Flatness Response for Various Loads, ADA4938-1,
VOUT = 0.1 V p-p
Figure 24. 0.1 dB Flatness Response for Various Loads, ADA4938-2,
VOUT = 0.1 V p-p
Rev. A | Page 11 of 28
ADA4938-1/ADA4938-2
–40
–40
–50
HD2, V = +5V
HD2, +5V
HD3, +5V
S
HD3, V = +5V
S
–50
–60
HD2, ±5V
HD3, ±5V
HD2, V = ±5V
S
HD3, V = ±5V
S
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
1
10
100
0
1
2
3
4
5
6
7
8
9
FREQUENCY (MHz)
V
(V)
OUT, dm
Figure 25. Harmonic Distortion vs. Frequency and Supply Voltage
Figure 28. Harmonic Distortion vs. VOUT and Supply Voltage
–40
–40
HD2, G = +1
HD3, G = +1
HD2, R = 1kΩ
L
HD3, R = 1kΩ
L
–50
–50
–60
HD2, G = +2
HD3, G = +2
HD2, R = 200Ω
L
HD3, R = 200Ω
L
–60
HD2, G = +5
HD3, G = +5
HD2, R = 100Ω
L
HD3, R = 100Ω
L
–70
–70
–80
–90
–80
–90
–100
–110
–120
–130
–100
–110
–120
1
10
100
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 26. Harmonic Distortion vs. Frequency and Gain
Figure 29. Harmonic Distortion vs. Frequency for Various Loads
–40
–50
–40
HD2, 10MHz
HD3, 10MHz
HD2, 10MHz
HD3, 10MHz
–50
HD2, 70MHz
HD3, 70MHz
HD2, 70MHz
HD3, 70MHz
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–3.3 –2.7 –2.1 –1.5 –0.9 –0.3 0.3 0.9 1.5 2.1 2.7 3.3
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
V
(V)
V
(V)
OCM
OCM
Figure 30. Harmonic Distortion vs. VOCM and Frequency, VS = 5 V
Figure 27. Harmonic Distortion vs. VOCM and Frequency
Rev. A | Page 12 of 28
ADA4938-1/ADA4938-2
10
0
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–PSRR
+PSRR
29.5 29.6 29.7 29.8 29.9 30.0 30.1 30.2 30.3 30.4 30.5
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 31. Intermodulation Distortion
Figure 34. PSRR vs. Frequency
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
S22
S11
V
= ±5V
S
V
= +5V
S
0.1
1
10
FREQUENCY (MHz)
100
1000
1
10
100
1000
FREQUENCY (MHz)
Figure 32. VIN CMRR vs. Frequency
Figure 35. Return Loss (S11, S22) vs. Frequency
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–40
R
R
R
= 1kΩ
R
= 200Ω
L
L
L
L
= 200Ω
= 100Ω
–50
–60
–70
–80
–90
–100
–110
–120
1
10
100
1000
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 33. Output Balance vs. Frequency
Figure 36. SFDR vs. Frequency for Various Loads
Rev. A | Page 13 of 28
ADA4938-1/ADA4938-2
26
100
10
1
24
G = +1
22
20
G = +2
18
G = +4
16
14
12
10
10
100
1k
10k
100k
1M
10M
100M
10
100
500
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 40. Input Voltage Noise vs. Frequency
Figure 37. Noise Figure vs. Frequency
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
8
6
PD INPUT
4
2
0
–2
–4
–6
–8
–10
NEGATIVE OUTPUT
V
V
× 3.16
IN
, dm
OUT
–0.5
TIME (200ns/DIV)
0
5
10 15 20 25 30 35 40 45 50 55 60
TIME (5ns/DIV)
Figure 41. Power-Down Response Time
Figure 38. Overdrive Recovery Time (Pulse Input)
45
40
35
30
25
20
15
10
5
12
10
8
+85°C
+25°C
–40°C
6
4
2
0
–2
–4
–6
–8
–10
–12
V
V
× 3.16
IN
, dm
OUT
0
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
0
50
100 150 200 250 300 350 400 450 500
TIME (50ns/DIV)
VOLTAGE (V)
Figure 42. Supply Current vs. Power-Down Voltage and Temperature
Figure 39. Overdrive Amplitude Characteristics (Triangle Wave Input)
Rev. A | Page 14 of 28
ADA4938-1/ADA4938-2
0.20
0.15
0.10
0.05
0
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.05
–0.10
–0.15
–0.20
TIME (1ns/DIV)
TIME (1ns/DIV)
Figure 43. Small Signal Transient Response, VOUT = 0.1 V p-p
Figure 46. Large Signal Transient Response
0.10
0.08
0.06
0.04
0.02
0
2.5
2.0
1.5
1.0
0.5
0
–0.02
–0.04
–0.06
–0.08
–0.5
–1.0
–1.5
–2.0
–2.5
–0.10
TIME (2ns/DIV)
TIME (2ns/DIV)
Figure 44. VOCM Small Signal Transient Response, VOUT = 0.1 V p-p
Figure 47. VOCM Large Signal Transient Response
60
3
0
+85°C
+25°C
–40°C
ALL CURVES ARE
NORMALIZED TO V
= 0V
OCM
50
40
30
20
10
0
–3
–6
–9
V
= –3.7V
= –3.5V
= –3V
= 0V
= +3V
OCM
OCM
OCM
OCM
OCM
OCM
OCM
V
V
V
V
V
V
= +3.5V
= +3.7V
–12
1
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
10
100
1000
VOLTAGE (V)
FREQUENCY (MHz)
Figure 45. Supply Current vs. Power-Down Voltage and Temperature, VS = 5 V
Figure 48. VOUT, dm Small Signal Frequency Response for Various VOCM
VOUT = 0.1 V p-p
,
Rev. A | Page 15 of 28
ADA4938-1/ADA4938-2
–40
–50
55
–60
50
INPUT1, OUTPUT2
INPUT2, OUTPUT1
100
–70
IP3 100Ω
–80
45
40
35
30
–90
–100
–110
–120
–130
–140
10
100
0.3
1
10
FREQUENCY (MHz)
1000
1.0
FREQUENCY (MHz)
Figure 49. IP3 vs. Frequency
Figure 52. Crosstalk vs. Frequency for ADA4938-2
3
2
1
ALL CURVES ARE
NORMALIZED TO V
= 0V
OCM
V
IN
0
–3
0.5
0.1
0
0
–0.1
–6
V
V
V
V
V
V
V
= –3.7V
= –3.5V
= –3V
= 0V
= +3V
OCM
OCM
OCM
OCM
OCM
OCM
OCM
SETTLING ERROR
–1
–2
–0.5
–1.0
–9
= +3.5V
= +3.7V
–12
1
10
100
FREQUENCY (MHz)
1000
TIME (1ns/DIV)
Figure 53. 0.1% Settling Time
Figure 50. VOUT, dm Large Signal Frequency Response for Various VOCM
100
10
1
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 51. Input Current Noise vs. Frequency
Rev. A | Page 16 of 28
ADA4938-1/ADA4938-2
TEST CIRCUTS
200Ω
+5V
50Ω
200Ω
V
V
IN
OCM
61.9Ω
ADA4938
1kΩ
200Ω
27.5Ω
–5V
200Ω
Figure 54. Equivalent Basic Test Circuit
200Ω
+5V
50Ω
200Ω
50Ω
V
V
IN
OCM
61.9Ω
ADA4938
200Ω
50Ω
27.5Ω
–5V
200Ω
Figure 55. Test Circuit for Output Balance
200Ω
+5V
0.1µF
412Ω
50Ω
200Ω
FILTER
FILTER
V
V
IN
OCM
61.9Ω
ADA4938
0.1µF
200Ω
412Ω
27.5Ω
–5V
200Ω
Figure 56. Test Circuit for Distortion Measurements
Rev. A | Page 17 of 28
ADA4938-1/ADA4938-2
TERMINOLOGY
–FB
Common-Mode Voltage
The common-mode voltage is the average of two node voltages.
ADA4938
R
F
R
G
+IN
–OUT
The output common-mode voltage is defined as
V
R
V
OUT, dm
OCM
L, dm
V
OUT, cm = (V+OUT + V−OUT)/2
–IN
+OUT
R
G
R
F
Balance
+FB
Balance is a measure of how well differential signals are matched in
amplitude and are exactly 180° apart in phase. Balance is most
easily determined by placing a well-matched resistor divider
between the differential voltage nodes and comparing the
magnitude of the signal at the midpoint of the divider with
the magnitude of the differential signal. By this definition,
output balance is the magnitude of the output common-mode
voltage divided by the magnitude of the output differential
mode voltage.
Figure 57. Circuit Definitions
Differential Voltage
The differential voltage is the difference between two node
voltages. For example, the output differential voltage (or
equivalently, output differential-mode voltage) is defined as
V
OUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
VOUT, cm
Output Balance Error =
VOUT, dm
Rev. A | Page 18 of 28
ADA4938-1/ADA4938-2
THEORY OF OPERATION
The ADA4938-x differs from conventional op amps in that it
has two outputs whose voltages move in opposite directions.
Like an op amp, it relies on open-loop gain and negative
feedback to force these outputs to the desired voltages. The
ADA4938-x behaves much like a standard voltage feedback op
amp and makes it easier to perform single-ended-to-differential
conversions, common-mode level shifting, and amplifications of
differential signals. Also like an op amp, the ADA4938-x has
high input impedance and low output impedance.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 57 can be
determined by
VOUT, dm
RF
RG
=
VIN, dm
This assumes the input resistors (RG) and feedback resistors (RF)
on each side are equal.
Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback, set
with external resistors, controls only the differential output
voltage. The common-mode feedback controls only the common-
mode output voltage. This architecture makes it easy to set the
output common-mode level to any arbitrary value. It is forced,
by internal common-mode feedback, to be equal to the voltage
applied to the VOCM input, without affecting the differential
output voltage.
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4938 can be estimated
using the noise model in Figure 58. The input-referred noise
voltage density, vnIN, is modeled as a differential input, and the
noise currents, inIN− and inIN+, appear between each input and
ground. The noise currents are assumed to be equal and produce a
voltage across the parallel combination of the gain and feedback
resistances. vn, cm is the noise voltage density at the VOCM pin.
Each of the four resistors contributes (4kTR)1/2. Table 9 summarizes
the input noise sources, the multiplication factors, and the output-
referred noise density terms.
The ADA4938-x architecture results in outputs that are highly
balanced over a wide frequency range without requiring tightly
matched external components. The common-mode feedback
loop forces the signal component of the output common-
mode voltage to zero, which results in nearly perfectly balanced
differential outputs that are identical in amplitude and are
exactly 180° apart in phase.
V
V
nRG1
nRF1
R
R
F1
G1
inIN+
+
V
nIN
V
nOD
inIN–
ADA4938
ANALYZING AN APPLICATION CIRCUIT
V
OCM
The ADA4938-x uses open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and −IN (see
Figure 57). For most purposes, this voltage can be assumed
to be zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also
be assumed to be zero. Starting from these two assumptions,
any application circuit can be analyzed.
V
nCM
R
R
F2
G2
V
V
nRG2
nRF2
Figure 58. ADA4938 Noise Model
Table 9. Output Noise Voltage Density Calculations
Input Noise
Voltage Density
Output
Multiplication Factor
Output Noise
Voltage Density Term
Input Noise Contribution
Differential Input
Inverting Input
Noninverting Input
VOCM Input
Gain Resistor, RG1
Gain Resistor, RG2
Feedback Resistor, RF1
Feedback Resistor, RF2
Input Noise Term
vnIN
inIN−
inIN+
vn, cm
vnRG1
vnRG2
vnRF1
vnRF2
vnIN
GN
GN
GN
vnO1 = GN(vnIN)
vnO2 = GN[inIN− × (RG2||RF2)]
vnO3 = GN[inIN+ × (RG1||RF1)]
inIN− × (RG2||RF2)
inIN+ × (RG1||RF1)
vn, cm
(4kTRG1)1/2
(4kTRG2)1/2
(4kTRF1)1/2
(4kTRF2)1/2
GN(β1 − β2)
GN(1 − β1)
GN(1 − β2)
1
1
vnO4 = GN(β1 − β2)(vnCM)
vnO5 = GN(1 − β1)(4kTRG1)1/2
vnO6 = GN(1 − β2)(4kTRG2)1/2
vnO7 = (4kTRF1)1/2
vnO8 = (4kTRF2)1/2
Rev. A | Page 19 of 28
ADA4938-1/ADA4938-2
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the input-
referred terms at +IN and −IN by the appropriate output factor,
where:
CALCULATING THE INPUT IMPEDANCE OF AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 59, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = 2 × RG.
2
GN
=
is the circuit noise gain.
(
β1 + β2
RG1
F1 + RG1
)
RG2
β1 =
and β2 =
are the feedback factors.
R
RF2 + RG2
R
F
ADA4938
When RF1/RG1 = RF2/RG2, β1 = β2 = β, and the noise gain
becomes
+V
S
R
G
G
+IN
+D
–D
IN
1
RF
RG
V
OCM
V
GN
=
=1+
OUT, dm
β
IN
–IN
R
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
R
F
Figure 59. ADA4938 Configured for Balanced (Differential) Inputs
For an unbalanced, single-ended input signal (see Figure 60),
the input impedance is
8
vnOD
=
v2
nOi
∑
i =1
⎛
⎜
⎞
⎟
THE IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
RG
RF
RG + RF
⎜
⎜
⎟
⎟
RIN, cm
=
1−
⎜
⎟
2×
(
)
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output, differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
⎝
⎠
R
F
+V
S
R
G
R
S
R
V
OCM
T
V
ADA4938
OUT, dm
R
G
As well as causing a noise contribution from VOCM, ratio matching
errors in the external resistors result in a degradation of the
ability of the circuit to reject input common-mode signals, much
the same as for a four-resistor difference amplifier made from a
conventional op amp.
R
R
T
S
R
F
Figure 60. ADA4938-x Configured for Unbalanced (Single-Ended) Input
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the Input Gain Resistor RG.
In addition, if the dc levels of the input and output common-
mode voltages are different, matching errors result in a small
differential-mode output offset voltage. When G = +1, with a
ground referenced input signal and the output common-mode
level set to 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worst-case
input CMRR of about 40 dB, a worst-case differential-mode
output offset of 25 mV due to 2.5 V level-shift, and no significant
degradation in output balance error.
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The ADA4938 is optimized for level-shifting, ground-referenced
input signals. As such, the center of the input common-mode
range is shifted approximately 1 V down from midsupply. The
input common-mode range at the summing nodes of the amplifier
is from 0.3 V above −VS to 1.6 V below +VS. To avoid clipping at
the outputs, the voltage swing at the +IN and −IN terminals must
be confined to these ranges.
Rev. A | Page 20 of 28
ADA4938-1/ADA4938-2
R
F
TERMINATING A SINGLE-ENDED INPUT
200Ω
+V
Using an example with an input source of 2 V, a source
resistance of 50 ꢀ, and an overall gain of 1 V/V, four simple
steps must be followed to terminate a single-ended input to the
ADA4938-x.
S
R
R
TH
G
27.4Ω
200Ω
V
TH
1.1V
V
O
V
OCM
ADA4938
R
0.97V
L
R
1. The input impedance is calculated using the formula
G
200Ω
R
TS
27.4Ω
⎛
⎜
⎞
⎟
⎛
⎜
⎞
⎟
–V
S
RG
RF
RG + RF
200
200
2×(200 +200)
⎜
⎜
⎟
⎟
⎜
⎟
RIN
=
=
= 267 Ω
R
F
⎜
⎜
⎝
⎟
⎟
⎠
1−
1−
200Ω
⎜
⎝
⎟
⎠
2×
(
)
Figure 64. Balancing Gain Resistor RG
R
F
4. Finally, the feedback resistor is recalculated to adjust the
output voltage to the desired level.
R
200Ω
+V
IN
267Ω
S
R
S
R
a. To make the output voltage VO = 1 V, RF is calculated
using
G
50Ω
200Ω
V
S
V
OCM
ADA4938
R
V
O
2V
L
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VO ×(RG + RTS )
1×(200 +27.4)
⎛
⎜
⎝
⎞
⎟
⎠
R
G
RF =
=
= 207 Ω
VTH
1.1
200Ω
b. To return the overall gain to 1 V/V (VO = VS = 2 V), RF
should be
–V
S
R
F
200Ω
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VO ×(RG + RTS )
2×(200 +27.4)
⎛
⎜
⎝
⎞
⎟
⎠
Figure 61. Single-Ended Input Impedance
RF =
=
= 414 Ω
VTH
1.1
2. To provide a 50 ꢀ termination for the source, the Resistor RT
is calculated such that RT || RIN = 50 ꢀ, or RT = 61.9 ꢀ.
R
F
R
F
+V
S
200Ω
+V
50Ω
R
R
S
S
G
50Ω
200Ω
R
61.9Ω
T
R
R
S
G
V
2V
S
V
OCM
ADA4938
R
L
V
O
50Ω
200Ω
R
T
V
2V
S
61.9Ω
R
V
G
OCM
ADA4938
R
V
O
L
200Ω
R
TS
27.4Ω
R
G
200Ω
–V
S
R
F
–V
S
R
F
Figure 65. Complete Single-Ended-to-Differential System
200Ω
SETTING THE OUTPUT COMMON-MODE VOLTAGE
Figure 62. Adding Termination Resistor RT
The VOCM pin of the ADA4938-x is internally biased at a voltage
approximately equal to the midsupply point (average value of
the voltages on V+ and V−). Relying on this internal bias results
in an output common-mode voltage that is within about 100 mV of
the expected value.
3. To compensate for the imbalance of the gain resistors, a correc-
tion resistor (RTS) is added in series with the inverting Input
Gain Resistor RG. RTS is equal to the Thevenin equivalent of
the source resistance (RS||RT).
R
R
S
TH
50Ω
R
61.9Ω
27.4Ω
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source or resistor divider (10 kꢀ or greater resistors) be used.
T
V
2V
V
S
TH
1.1V
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 10 kꢀ. If multiple
ADA4938-x devices share one reference output, it is recommended
that a buffer be used.
Figure 63. Calculating Thevenin Equivalent
RTS = RTH = RS || RT = 27.4 ꢀ. Note that VTH is not equal to
VS/2, which would be the case if the amplifier circuit did
not affect the termination.
Rev. A | Page 21 of 28
ADA4938-1/ADA4938-2
Table 10 and Table 11 list several common gain settings, associated
resistor values, input impedances, and output noise densities for
both balanced and unbalanced input configurations. Also shown
are the input common-mode voltages under the given conditions
for different VOCM settings for both a 10 V single supply and
5 V dual supplies.
Table 10. Differential Ground-Referenced Input, DC-Coupled; See Figure 59
Common-Mode Level at +IN, −IN (V)
+VS = 10 V, −VS = 0 V +VS = 5 V, −VS = −5 V
VOUT, dm = 2.0 V p-p VOUT, dm = 2.0 V p-p
VOCM = 2.5 V VOCM = 3.5 V VOCM = 1.0 V VOCM = 3.2 V
Differential
Output
Noise Density
(nV/√Hz)
Nominal
Gain (V/V)
RF (Ω)
200
402
402
402
RG (Ω)
200
200
127
80.6
RIN, dm (Ω)
400
400
254
161
1
2
3.16
5
6.5
1.25
0.83
0.60
0.42
1.75
1.16
0.84
0.58
0.50
0.33
0.24
0.17
1.60
1.06
0.77
0.53
10.4
13.4
18.2
Table 11. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω; See Figure 60
Differential
Output
Noise
Common-Mode Swing at +IN, −IN (V)
+VS = 10 V, −VS = 0 V +VS = 5 V, −VS = −5 V
VOUT, dm = 2.0 V p-p VOUT, dm = 2.0 V p-p
Nominal
Overall
Density
Gain (V/V) RF (Ω) RG1 (Ω) RT (Ω) RIN,se (Ω) RG2 (Ω)1 Gain (V/V)2 (nV/√Hz)
VOCM = 2.5 V
VOCM = 3.5 V
1.50 to 2.00
1.00 to 1.33
0.72 to 0.96
0.50 to 0.67
VOCM = 0 V
VOCM = 2.0 V
0.75 to 1.25
0.50 to 0.83
0.36 to 0.60
0.25 to 0.42
1
2
3.16
5
200
402
402
402
200
200
127
80.6
60.4
60.4
66.5
76.8
267
300
205
138
226
226
158
110
0.9
1.8
2.5
3.6
6.2
9.8
11.8
14.7
1.00 to 1.50
0.66 to 1.00
0.48 to 0.72
0.33 to 0.50
−0.25 to +0.25
−0.17 to +0.17
−0.12 to +0.12
−0.08 to +0.08
1 RG2 = RG1 + RTS.
2 Includes effects of termination match.
Rev. A | Page 22 of 28
ADA4938-1/ADA4938-2
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4938-x is sensitive to the
PCB environment in which it operates. Realizing its superior
performance requires attention to the details of high speed
PCB design.
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency ceramic
chip capacitors. It is recommended that two parallel bypass capa-
citors (1000 pF and 0.1 μF) be used for each supply with the
1000 pF capacitor placed closer to the device; if further away,
provide low frequency bypassing using 10 μF tantalum capacitors
from each supply to ground.
The first requirement is a solid ground plane that covers as much of
the board area around the ADA4938-x as possible. However, the
area near the feedback resistors (RF), input gain resistors (RG),
and the input summing nodes should be cleared of all ground
and power planes (see Figure 66). Clearing the ground and
power planes minimizes any stray capacitance at these nodes
and prevents peaking of the response of the amplifier at high
frequencies.
Signal routing should be short and direct to avoid parasitic
effects. Wherever complementary signals exist, provide a
symmetrical layout to maximize balanced performance.
When routing differential signals over a long distance, keep
PCB traces close together and twist any differential wiring to
minimize loop area. Doing this reduces radiated energy and
makes the circuit less susceptible to interference.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD 51-7. The exposed pad
is electrically isolated from the device; therefore, it can be con-
nected to a ground plane using vias. Examples of the thermal
attach pad and via structure for the ADA4938-1 are shown in
Figure 67 and Figure 68.
1.30
0.80
1.30 0.80
Figure 67. Recommended PCB Thermal Attach Pad (ADA4938-1)
(Dimensions in mm)
Figure 66. Ground and Power Plane Voiding in Vicinity of RF and RG
1.30
TOP METAL
GROUND PLANE
0.30
PLATED
VIA HOLE
POWER PLANE
BOTTOM METAL
Figure 68. Cross-Section of a 4-Layer PCB (ADA4938-1) Showing a Thermal Via Connection to the Buried Ground Plane (Dimensions in mm)
Rev. A | Page 23 of 28
ADA4938-1/ADA4938-2
HIGH PERFORMANCE ADC DRIVING
The ADA4938-x is ideally suited for dc-coupled baseband
applications. The circuit in Figure 69 shows a front-end connection
for an ADA4938-x driving an AD9446, 16-bit, 80 MSPS ADC.
The AD9446 achieves its optimum performance when it is
driven differentially. The ADA4938-x eliminates the need for a
transformer to drive the ADC, performs a single-ended-to-
differential conversion, buffers the driving signal, and provides
appropriate level shifting for dc coupling.
The circuit in Figure 70 shows a simplified front-end connection
for an ADA4938-x driving an AD9246, 14-bit, 125 MSPS ADC.
The AD9246 achieves its optimum performance when it is
driven differentially. The ADA4938-x eliminates the need for a
transformer to drive the ADC, performs a single-ended-to-
differential conversion, buffers the driving signal, and provides
appropriate level shifting for dc coupling.
The ADA4938-x is configured with dual 5 V supplies and a
gain of ~2 V/V for a single-ended input to differential output.
The 76.8 ꢀ termination resistor, in parallel with the single-
ended input impedance of 137 ꢀ, provides a 50 ꢀ dc termination
for the source. The additional 30.1 ꢀ (120 ꢀ total) at the inverting
input balances the parallel dc impedance of the 50 ꢀ source and
the termination resistor driving the noninverting input.
The ADA4938-x is configured with a single 10 V supply and
unity gain for a single-ended input to differential output. The
61.9 ꢀ termination resistor, in parallel with the single-ended
input impedance of 267 ꢀ, provides a 50 ꢀ termination for the
source. The additional 26 ꢀ (226 ꢀ total) at the inverting input
balances the parallel impedance of the 50 ꢀ source and the
termination resistor driving the noninverting input.
The signal generator has a symmetric, ground-referenced
bipolar output. The VOCM pin of the ADA4938-x is connected to
the CML pin of the AD9246 to set the output common-mode
level at the appropriate point. A portion of this is fed back to the
summing nodes, biasing −IN and +IN at 0.55 V. For a common-
mode voltage of 0.9 V, each ADA4938 output swings between
0.4 V and 1.4 V, providing a 2 V p-p differential output.
The signal generator has a symmetric, ground-referenced bipolar
output. The VOCM pin of the ADA4938-x is biased with an external
resistor divider to obtain the desired 3.5 V output common-mode.
One-half of the common-mode voltage is fed back to the summing
nodes, biasing −IN and +IN at 1.75 V. For a common-mode vol-
tage of 3.5 V, each ADA4938-x output swings between 2.7 V
and 4.3 V, providing a 3.2 V p-p differential output.
The output is dc-coupled to a single-pole, low-pass filter. The filter
reduces the noise bandwidth of the amplifier and provides some
level of isolation from the switched capacitor inputs of the ADC.
The AD9246 is set for a 2 V p-p full-scale input by connecting the
SENSE pin to AGND. The inputs of the AD9246 are biased at
1 V by connecting the CML output, as shown in Figure 70.
The output of the amplifier is dc-coupled to the ADC through a
second-order, low-pass filter with a −3 dB frequency of 50 MHz.
The filter reduces the noise bandwidth of the amplifier and
isolates the driver outputs from the ADC inputs.
The AD9446 is configured for a 4.0 V p-p full-scale input by
setting R1 = R2 = 1 kꢀ between the VREF pin and SENSE pin
in Figure 69.
10V
200Ω
5V (A) 3.3V (A) 3.3V (D)
10V
AVDD2 AVDD1 DRVDD
30nH
30nH
200Ω
50Ω
VIN+
47pF
VIN–
AD9446
+
BUFFER T/H
24.3Ω
24.3Ω
V
61.9Ω
OCM
ADA4938
16
ADC
SIGNAL
GENERATOR
226Ω
CLOCK/
TIMING
REF
200Ω
AGND SENSE
VREF
R1
R2
Figure 69. ADA4938 Driving an AD9446, 16-Bit, 80 MSPS ADC
200Ω
1.8V
+5V
76.8Ω
50Ω
33Ω
90Ω
V
AVDD DRVDD
VIN–
+
OCM
D13 TO
D0
V
IN
AD9246
10pF
ADA4938
90Ω
VIN+
AGND SENSE CML
33Ω
30.1Ω
0.1µF
–5V
200Ω
Figure 70. ADA4938 Driving an AD9246, a 14-Bit, 125 MSPS ADC
Rev. A | Page 24 of 28
ADA4938-1/ADA4938-2
OUTLINE DIMENSIONS
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
13
16
1
0.45
(BOTTOM VIEW)
12
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
4
9
0.50
BSC
8
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 71. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body
(CP-16-2)
Dimensions shown in millimeters
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
PIN 1
INDICATOR
0.50
BSC
2.25
TOP
VIEW
3.75
BSC SQ
EXPOSED
2.10 SQ
1.95
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
6
13
12
7
0.25 MIN
0.80 MAX
0.65TYP
2.50 REF
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.30
0.23
0.18
0.20 REF
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 72. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Package Option
CP-16-2
CP-16-2
CP-16-2
CP-24-1
Ordering Quantity
Branding
H11
H11
ADA4938-1ACPZ-R21
ADA4938-1ACPZ-RL1
ADA4938-1ACPZ-R71
ADA4938-2ACPZ-R21
ADA4938-2ACPZ-RL1
ADA4938-2ACPZ-R71
250
5,000
1,500
250
5,000
1,500
H11
CP-24-1
CP-24-1
1 Z = RoHS Compliant Part.
Rev. A | Page 25 of 28
ADA4938-1/ADA4938-2
NOTES
Rev. A | Page 26 of 28
ADA4938-1/ADA4938-2
NOTES
Rev. A | Page 27 of 28
ADA4938-1/ADA4938-2
NOTES
©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06592-0-10/09(A)
Rev. A | Page 28 of 28
相关型号：
©2020 ICPDF网 联系我们和版权申明