ADA4939-1 [ADI]
Ultralow Distortion Differential ADC Driver; 超低失真差分ADC驱动器
| 型号： | ADA4939-1 |
| 厂家： | 
ADI |
| 描述： | Ultralow Distortion Differential ADC Driver |
| 文件： | 总24页 (文件大小：518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Distortion
Differential ADC Driver
ADA4939-1/ADA4939-2
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Extremely low harmonic distortion
−102 dBc HD2 @ 10 MHz
−83 dBc HD2 @ 70 MHz
−77 dBc HD2 @ 100 MHz
−101 dBc HD3 @ 10 MHz
−97 dBc HD3 @ 70 MHz
ADA4939-1
12 PD
–FB
+IN
–IN
1
2
3
4
11 –OUT
10 +OUT
+FB
9
V
OCM
−91 dBc HD3 @ 100 MHz
Low input voltage noise: 2.3 nV/√Hz
High speed
−3 dB bandwidth of 1.4 GHz, G = 2
Slew rate: 6800 V/μs, 25% to 75%
Fast overdrive recovery of <1 ns
0.5 mV typical offset voltage
Externally adjustable gain
Stable for differential gains ≥2
Differential-to-differential or single-ended-to-differential
operation
Figure 1. ADA4939-1
–IN1
+FB1
1
18 +OUT1
17 V
2
3
4
5
6
OCM1
16 –V
15
14
+V
S2
S2
S1
ADA4939-2
–V
+V
S1
–FB2
+IN2
PD2
13 –OUT2
Adjustable output common-mode voltage
Single-supply operation: 3.3 V to 5 V
APPLICATIONS
ADC drivers
Figure 2. ADA4939-2
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
–60
–65
V
= 2V p-p
OUT, dm
HD2
HD3
–70
Line drivers
–75
GENERAL DESCRIPTION
–80
The ADA4939 is a low noise, ultralow distortion, high speed
differential amplifier. It is an ideal choice for driving high
performance ADCs with resolutions up to 16 bits from dc to
100 MHz. The output common-mode voltage is user adjustable
by means of an internal common-mode feedback loop, allowing
the ADA4939 output to match the input of the ADC. The internal
feedback loop also provides exceptional output balance as well as
suppression of even-order harmonic distortion products.
–85
–90
–95
–100
–105
–110
1
10
100
FREQUENCY (MHz)
With the ADA4939, differential gain configurations are easily
realized with a simple external feedback network of four resistors
that determine the closed-loop gain of the amplifier.
Figure 3. Harmonic Distortion vs. Frequency
The ADA4939 is available in a Pb-free, 3 mm × 3 mm 16-lead
LFCSP (ADA4939-1, single) or a Pb-free, 4 mm × 4 mm 24-lead
LFCSP (ADA4939-2, dual). The pinout has been optimized to
facilitate PCB layout and minimize distortion. The ADA4939-1
and the ADA4939-2 are specified to operate over the −40°C to
+105°C temperature range; both operate on supplies between
3.3 V and 5 V.
The ADA4939 is fabricated using Analog Devices, Inc., proprietary
silicon-germanium (SiGe), complementary bipolar process,
enabling it to achieve very low levels of distortion with an input
voltage noise of only 2.3 nV/√Hz. The low dc offset and excellent
dynamic performance of the ADA4939 make it well suited for a
wide variety of data acquisition and signal processing applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADA4939-1/ADA4939-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 17
Analyzing an Application Circuit ............................................ 17
Setting the Closed-Loop Gain .................................................. 17
Stable for Gains ≥2 ..................................................................... 17
Estimating the Output Noise Voltage...................................... 17
Impact of Mismatches in the Feedback Networks................. 18
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Operation ............................................................................... 3
3.3 V Operation ............................................................................ 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 15
Operational Description................................................................ 16
Definition of Terms.................................................................... 16
Calculating the Input Impedance for an Application Circuit
....................................................................................................... 19
Input Common-Mode Voltage Range..................................... 21
Input and Output Capacitive AC-Coupling ........................... 21
Minimum RG Value of 50 Ω...................................................... 21
Setting the Output Common-Mode Voltage.......................... 21
Layout, Grounding, and Bypassing.............................................. 22
High Performance ADC Driving ................................................. 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
5/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADA4939-1/ADA4939-2
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = +VS/2, RF = 402 ꢀ, RG = 200 ꢀ, RT = 60.4 ꢀ (when used), RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 42 for signal definitions.
±±IN to VOUT, dm Performance
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
VOUT, dm = 0.1 V p-p
1400
300
90
1400
6800
<1
MHz
MHz
MHz
MHz
V/μs
ns
VOUT, dm = 0.1 V p-p, ADA4939-1
VOUT, dm = 0.1 V p-p, ADA4939-2
VOUT, dm = 2 V p-p
Large Signal Bandwidth
Slew Rate
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
VOUT, dm = 2 V p-p, 25% to 75%
VIN = 0 V to 1.5 V step, G = 3.16
See Figure 41 for distortion test circuit
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 70 MHz
VOUT, dm = 2 V p-p, 100 MHz
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 70 MHz
VOUT, dm = 2 V p-p, 100 MHz
f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p
f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p
f = 100 kHz
−102
−83
−77
−101
−97
−91
−95
−89
2.3
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Third Harmonic
IMD
Voltage Noise (RTI)
Input Current Noise
Crosstalk
nV/√Hz
pA/√Hz
dB
f = 100 kHz
f = 100 MHz, ADA4939-2
6
−80
INPUT CHARACTERISTICS
Offset Voltage
VOS, dm = VOUT, dm/2, VDIN+ = VDIN− = 2.5 V
TMIN to TMAX variation
−3.4
−26
0.5
2.0
−10
0.5
+0.5
180
450
1
+2.8
+2.2
+11.2
mV
μV/°C
μA
μA/°C
μA
kΩ
kΩ
pF
V
Input Bias Current
TMIN to TMAX variation
Input Offset Current
Input Resistance
−11.2
Differential
Common mode
Input Capacitance
Input Common-Mode Voltage
CMRR
1.1
0.9
3.9
−77
∆VOUT, dm/∆VIN, cm, ∆VIN, cm = 1 V
−83
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
Maximum ∆VOUT; single-ended output, RF = RG = 10 kΩ
4.1
V
mA
dB
100
−64
∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V, 10 MHz,
see Figure 40 for test circuit
Rev. 0 | Page 3 of 24
ADA4939-1/ADA4939-2
VOCM to VOUT, cm Performance
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
VOCM CMRR
670
2500
7.5
MHz
V/μs
nV/√Hz
VIN = 1.5 V to 3.5 V, 25% to 75%
f = 100 kHz
1.3
8.3
−3.7
3.5
V
9.7
0.5
−90
0.98
11.5
+3.7
−73
0.99
kΩ
mV
dB
V/V
VOS, cm = VOUT, cm, VDIN+ = VDIN− = +VS/2
ΔVOUT, dm/ΔVOCM, ΔVOCM = 1 V
ΔVOUT, cm/ΔVOCM, ΔVOCM = 1 V
Gain
0.97
General Performance
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
3.0
35.1
5.25
37.7
V
36.5
16
0.32
−90
mA
μA/°C
mA
dB
TMIN to TMAX variation
Powered down
ΔVOUT, dm/ΔVS, ΔVS = 1 V
0.26
0.38
−80
Power Supply Rejection Ratio
POWER-DOWN (PD)
PD Input Voltage
Powered down
Enabled
≤1
V
≥2
V
Turn-Off Time
Turn-On Time
500
100
ns
ns
PD Pin Bias Current per Amplifier
Enabled
PD = 5 V
PD = 0 V
30
μA
μA
°C
Disabled
−200
OPERATING TEMPERATURE RANGE
−40
+105
Rev. 0 | Page 4 of 24
ADA4939-1/ADA4939-2
3.3 V OPERATION
TA = 25°C, +VS = 3.3 V, −VS = 0 V, VOCM = +VS/2, RF = 402 ꢀ, RG = 200 ꢀ, RT = 60.4 ꢀ (when used), RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 42 for signal definitions.
±±IN to VOUT, dm Performance
Table 4.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
VOUT, dm = 0.1 V p-p
1400
300
90
1400
5000
<1
MHz
MHz
MHz
MHz
V/μs
ns
VOUT, dm = 0.1 V p-p, ADA4939-1
VOUT, dm = 0.1 V p-p, ADA4939-2
VOUT, dm = 2 V p-p
Large Signal Bandwidth
Slew Rate
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
VOUT, dm = 2 V p-p, 25% to 75%
VIN = 0 V to 1.0 V step, G = 3.16
See Figure 41 for distortion test circuit
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 70 MHz
VOUT, dm = 2 V p-p, 100 MHz
VOUT, dm = 2 V p-p, 10 MHz
VOUT, dm = 2 V p-p, 70 MHz
VOUT, dm = 2 V p-p, 100 MHz
f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p
f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p
f = 100 kHz
−100
−90
−83
−94
−82
−75
−87
−70
2.3
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Third Harmonic
IMD
Voltage Noise (RTI)
Input Current Noise
Crosstalk
nV/√Hz
pA/√Hz
dB
f = 100 kHz
f = 100 MHz, ADA4939-2
6
−80
INPUT CHARACTERISTICS
Offset Voltage
VOS, dm = VOUT, dm/2, VDIN+ = VDIN− = +VS/2
TMIN to TMAX variation
−3.5
−26
0.5
2.0
−10
0.5
0.4
180
450
1
+3.5
+2.2
+11.2
mV
μV/°C
μA
Input Bias Current
TMIN to TMAX variation
μA/°C
Input Offset Current
Input Resistance
−11.2
Differential
Common mode
kΩ
kΩ
pF
V
Input Capacitance
Input Common-Mode Voltage
CMRR
0.9
0.8
2.4
−75
∆VOUT, dm/∆VIN, cm, ∆VIN, cm = 1 V
−85
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
Maximum ∆VOUT, single-ended output, RF = RG = 10 kΩ
2.5
V
mA
dB
75
−61
∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V, f = 10 MHz,
see Figure 40 for test circuit
Rev. 0 | Page 5 of 24
ADA4939-1/ADA4939-2
VOCM to VOUT, cm Performance
Table 5.
Parameter
Conditions
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
VOCM CMRR
560
1250
7.5
MHz
V/μs
nV/√Hz
VIN = 0.9 V to 2.4 V, 25% to 75%
f = 100 kHz
1.3
8.3
−3.7
1.9
V
9.7
0.5
−75
0.98
11.2
+3.7
−73
0.99
kΩ
mV
dB
V/V
VOS, cm = VOUT, cm, VDIN+ = VDIN− = 1.67 V
∆VOUT, dm/∆VOCM, ∆VOCM = 1 V
∆VOUT, cm/∆VOCM, ∆VOCM = 1 V
Gain
0.97
General Performance
Table 6.
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
3.0
32.8
5.25
36.0
V
34.5
16
0.20
−84
mA
μA/°C
mA
dB
TMIN to TMAX variation
Powered down
∆VOUT, dm/∆VS, ∆VS = 1 V
0.16
0.26
−72
Power Supply Rejection Ratio
POWER-DOWN (PD)
PD Input Voltage
Powered down
Enabled
≤1
V
≥2
V
Turn-Off Time
Turn-On Time
500
100
ns
ns
PD Pin Bias Current per Amplifier
Enabled
PD = 3.3 V
PD = 0 V
26
μA
μA
°C
Disabled
−137
OPERATING TEMPERATURE RANGE
−40
+105
Rev. 0 | Page 6 of 24
ADA4939-1/ADA4939-2
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Table 7.
Parameter
Rating
Supply Voltage
5.5 V
Power Dissipation
Input Current, +IN, −IN,
See Figure 4
5 mA
PD
Storage Temperature Range
Operating Temperature Range
ADA4939-1
ADA4939-2
Lead Temperature (Soldering, 10 sec)
Junction Temperature
−65°C to +125°C
−40°C to +105°C
−40°C to +105°C
300°C
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, through holes, ground, and power
planes reduces θJA.
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the single 16-lead
LFCSP (98°C/W) and the dual 24-lead LFCSP (67°C/W) on a
JEDEC standard four-layer board with the exposed pad
soldered to a PCB pad that is connected to a solid plane.
3.0
THERMAL RESISTANCE
2.5
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD 51-7.
ADA4939-2
2.0
1.5
Table 8. Thermal Resistance
ADA4939-1
Package Type
θJA
98
67
Unit
°C/W
°C/W
1.0
0.5
0
ADA4939-1, 16-Lead LFCSP (Exposed Pad)
ADA4939-2, 24-Lead LFCSP (Exposed Pad)
MAXIMUM POWER DISSIPATION
–40
–20
0
20
40
60
80
100
The maximum safe power dissipation in the ADA4939 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4939. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Ambient Temperature for
a Four-Layer Board
ESD CAUTION
Rev. 0 | Page 7 of 24
ADA4939-1/ADA4939-2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
PIN 1
–IN1
+FB1
1
2
3
4
5
6
18 +OUT1
17 V
INDICATOR
12 PD
–FB
+IN
–IN
1
2
3
4
OCM1
16 –V
+V
11 –OUT
10 +OUT
ADA4939-2
TOP VIEW
(Not to Scale)
S2
S2
ADA4939-1
TOP VIEW
(Not to Scale)
S1
–V
15
14
+V
S1
–FB2
+IN2
PD2
+FB
9 V
OCM
13 –OUT2
Figure 5. ADA4939-1 Pin Configuration
Figure 6. ADA4939-2 Pin Configuration
Table 9. ADA4939-1 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
−FB
+IN
Negative Output for Feedback Component Connection
Positive Input Summing Node
3
4
−IN
+FB
+VS
VOCM
+OUT
−OUT
PD
Negative Input Summing Node
Positive Output for Feedback Component Connection
Positive Supply Voltage
Output Common-Mode Voltage
Positive Output for Load Connection
Negative Output for Load Connection
Power-Down Pin
5 to 8
9
10
11
12
13 to 16
−VS
Negative Supply Voltage
Table 10. ADA4939-2 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3, 4
5
6
7
8
9, 10
11
12
−IN1
+FB1
+VS1
−FB2
+IN2
−IN2
+FB2
+VS2
VOCM2
+OUT2
−OUT2
PD2
Negative Input Summing Node 1
Positive Output Feedback 1
Positive Supply Voltage 1
Negative Output Feedback 2
Positive Input Summing Node 2
Negative Input Summing Node 2
Positive Output Feedback 2
Positive Supply Voltage 2
Output Common-Mode Voltage 2
Positive Output 2
13
14
Negative Output 2
Power-Down Pin 2
15, 16
17
18
19
20
−VS2
Negative Supply Voltage 2
Output Common-Mode Voltage 1
Positive Output 1
Negative Output 1
Power-Down Pin 1
VOCM1
+OUT1
−OUT1
PD1
21, 22
23
24
−VS1
−FB1
+IN1
Negative Supply Voltage 1
Negative Output Feedback 1
Positive Input Summing Node 1
Rev. 0 | Page 8 of 24
ADA4939-1/ADA4939-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = +VS /2, RG = 200 ꢀ, RF = 402 ꢀ, RT = 60.4 Ω, G = 1, RL, dm = 1 kΩ, unless otherwise noted.
Refer to Figure 39 for test setup. Refer to Figure 42 for signal definitions.
2
2
V
= 100mV p-p
V
= 2V p-p
OUT, dm
OUT, dm
0
0
–2
–2
–4
–4
–6
–6
–8
–8
–10
–12
–14
–10
–12
–14
R
R
R
= 200Ω, R = 60.4Ω
R
R
R
= 200Ω, R = 60.4Ω
G = +2.00
G = +3.16
G = +5.00
G = +2.00
G = +3.16
G = +5.00
G
G
G
T
G
G
G
T
= 127Ω, R = 66.3Ω
= 127Ω, R = 66.3Ω
T
T
= 80.6Ω, R = 76.8Ω
= 80.6Ω, R = 76.8Ω
T
T
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response for Various Gains
Figure 10. Large Signal Frequency Response for Various Gains
3
2
V
= 100mV p-p
V
= 2V p-p
OUT, dm
OUT, dm
2
1
0
–2
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–4
–6
–8
–10
–12
V
S
= 3.3V
= 5.0V
V
S
= 3.3V
= 5.0V
V
V
S
S
1
10
100
FREQUENCY (MHz)
1k
1
10
100
1k
FREQUENCY (MHz)
Figure 11. Large Signal Frequency Response for Various Supplies
Figure 8. Small Signal Frequency Response for Various Supplies
3
3
V
= 100mV p-p
V
= 2V p-p
OUT, dm
OUT, dm
2
1
2
1
0
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–40°C
+25°C
+105°C
–40°C
+25°C
+105°C
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Small Signal Frequency Response for Various Temperatures
Figure 12. Large Signal Frequency Response for Various Temperatures
Rev. 0 | Page 9 of 24
ADA4939-1/ADA4939-2
3
3
2
V
= 100mV p-p
V
= 2V p-p
OUT, dm
OUT, dm
2
1
1
0
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
R
R
= 1kΩ
= 200Ω
R
R
= 1kΩ
= 200Ω
L
L
L
L
1
10
100
FREQUENCY (MHz)
1k
1
10
100
1k
FREQUENCY (MHz)
Figure 13. Small Signal Frequency Response for Various Loads
Figure 16. Large Signal Frequency Response for Various Loads
6
–55
V
= 100mV p-p
OUT, dm
V
= 2V p-p
OUT, dm
–60
–65
HD2, G = 2
HD3, G = 2
3
0
–70
HD2, G = 3.16
HD3, G = 3.16
HD2, G = 5
–75
–80
HD3, G = 5
–85
–3
–6
–9
–90
–95
–100
–105
–110
–115
V
V
V
= 1.0V
= 3.9V
= 2.5V
OCM
OCM
OCM
1
10
100
1k
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14. VOCM Small Signal Frequency Response at Various DC Levels
Figure 17. Harmonic Distortion vs. Frequency at Various Gains
–60
0.5
V
= 100mV p-p
V
V
= 2V p-p
= ±2.5V
OUT, dm
OUT, dm
–65
–70
0.4
0.3
S
HD2, R
HD3, R
HD2, R
HD3, R
= 1kΩ
= 1kΩ
= 200Ω
= 200Ω
L, dm
L, dm
L, dm
L, dm
–75
0.2
–80
0.1
–85
0
–90
–0.1
–0.2
–0.3
–0.4
–0.5
R
R
= 1kΩ
= 200Ω
L
L
–95
R
R
= 1kΩ OUT1
= 1kΩ OUT2
L
L
–100
–105
–110
R
R
= 200Ω OUT1
= 200Ω OUT2
L
L
1
10
FREQUENCY (MHz)
100
1
10
100
1k
FREQUENCY (MHz)
Figure 18. Harmonic Distortion vs. Frequency at Various Loads
Figure 15. 0.1 dB Flatness Small Signal Response for Various Loads
Rev. 0 | Page 10 of 24
ADA4939-1/ADA4939-2
–60
–65
–40
–50
V
= 2V p-p
OUT, dm
HD2, V (SPLIT SUPPLY) = ±2.5V
S
HD3, V (SPLIT SUPPLY) = ±2.5V
S
–70
–60
HD2, V (SPLIT SUPPLY) = ±1.65V
S
HD3, V (SPLIT SUPPLY) = ±1.65V
S
–75
–70
–80
–80
–85
–90
–90
–100
–110
–120
–130
–95
HD2, V = 5.0
S
–100
–105
–110
HD3, V = 5.0
S
HD2, V = 3.3
S
HD3, V = 3.3
S
1
10
100
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
V
(V p-p)
OUT, dm
Figure 19. Harmonic Distortion vs. Frequency at Various Supplies
Figure 22. Harmonic Distortion vs. VOUT, dm and Supply Voltage, f = 10 MHz
–40
10
V
= 2V p-p
OUT, dm
V
V
= 2V p-p
= ±2.5V
OUT, dm
–50
–60
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
S
–70
–80
–90
–100
–110
–120
HD2, f = 10MHz
HD3, f = 10MHz
HD2, f = 70MHz
HD3, f = 70MHz
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
69.5 69.6 69.7 69.8 69.9 70.0 70.1 70.2 70.3 70.4 70.5
V
(V)
OCM
FREQUENCY (MHz)
Figure 20. Harmonic Distortion vs. VOCM at Various Frequencies
Figure 23. 70 MHz Intermodulation Distortion
–40
–30
–35
–40
–45
–50
–55
–60
–65
–70
R
= 200Ω
V
= 2V p-p
L, dm
OUT, dm
–50
–60
–70
–80
–90
–100
–110
–120
–130
HD2, f = 10MHz
HD3, f = 10MHz
HD2, f = 70MHz
HD3, f = 70MHz
1.2
1.4
1.6
1.8
2.0
1
10
100
1k
V
(V)
FREQUENCY (MHz)
OCM
Figure 24. CMRR vs. Frequency
Figure 21. Harmonic Distortion vs. VOCM at Various Frequencies
Rev. 0 | Page 11 of 24
ADA4939-1/ADA4939-2
–60
–30
–35
–40
–45
–50
–55
–60
–65
–70
V
= ±1.65V
R
= 200Ω
V
V
V
V
= HD2, = 1V p-p
= HD3, = 1V p-p
= HD2, = 2V p-p
= HD3, = 2V p-p
S
L, dm
OUT, dm
OUT, dm
OUT, dm
OUT, dm
–70
–80
–90
–100
–110
–120
1
10
100
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25. Harmonic Distortion vs. Frequency at Various Output Voltages
Figure 28. Output Balance vs. Frequency
–30
70
60
50
40
30
20
10
0
100
R
= 200Ω
L, dm
GAIN
50
–40
–50
–60
–70
–80
–90
–100
0
PHASE
–50
–100
–150
–200
–250
–300
–350
–10
1
10
100
1k
0.01
0.1
1
10
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 26. PSRR vs. Frequency, RL = 200 Ω
Figure 29. Open-Loop Gain and Phase vs. Frequency
8
6
0
R
= 200Ω
L, dm
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
4
2
S22
S11
0
–2
–4
–6
–8
V
OUT
V
× 3.16V
30
IN
0
10
20
40
50
60
1
10
100
FREQUENCY (MHz)
1k
TIME (ns)
Figure 30. Overdrive Recovery, G = 3.16
Figure 27. Return Loss (S11, S22) vs. Frequency
Rev. 0 | Page 12 of 24
ADA4939-1/ADA4939-2
–60
–65
–40
–50
V
V
= 2V p-p
R
= 200Ω
OUT, dm
= ±2.5V
L, dm
S
–60
–70
–70
–75
INPUT AMP 1 TO OUTPUT AMP 2
R
= 200Ω
L
–80
–80
–90
–85
–100
–110
–120
–130
–140
R
= 1kΩ
L
INPUT AMP 2 TO OUTPUT AMP 1
–90
–95
–100
–105
1
10
FREQUENCY (MHz)
100
1
10
100
1k
FREQUENCY (MHz)
Figure 31. Spurious-Free Dynamic Range vs. Frequency at Various Loads
Figure 34. Crosstalk vs. Frequency for ADA4939-2
0.12
0.10
0.08
0.06
0.04
0.02
0
4
3
2
1
0
–1
–2
–3
–4
–0.02
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
TIME (ns)
TIME (ns)
Figure 32. Small Signal Pulse Response
Figure 35. Large Signal Pulse Response
2.60
2.55
2.50
2.45
2.40
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
TIME (ns)
Figure 33. VOCM Small Signal Pulse Response
Figure 36. VOCM Large Signal Pulse Response
Rev. 0 | Page 13 of 24
ADA4939-1/ADA4939-2
3.5
1k
100
10
R
= 200Ω
L, dm
3.0
V
OUT, dm
2.5
2.0
1.5
1.0
0.5
0
PD
–0.5
1
0
100 200 300 400 500 600 700 800 900 1000
TIME (ns)
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 38. Voltage Noise Spectral Density, RTI
PD
Figure 37.
Response Time
Rev. 0 | Page 14 of 24
ADA4939-1/ADA4939-2
TEST CIRCUITS
402Ω
5V
0.1µF
50Ω
200Ω
V
V
IN
OCM
60.4Ω
ADA4939
1kΩ
200Ω
0.1µF
402Ω
Figure 39. Equivalent Basic Test Circuit, G = 2
NETWORK
ANALYZER
OUTPUT
402Ω
+2.5V
49.9Ω
AC-COUPLED
NETWORK
ANALYZER
INPUT
50Ω
200Ω
49.9Ω
AC-COUPLED
V
V
IN
OCM
60.4Ω
ADA4939
50Ω
200Ω
49.9Ω
0.1µF
–2.5V
60.4Ω
402Ω
49.9Ω
Figure 40. Test Circuit for Output Balance, CMRR
402Ω
5V
200Ω
50Ω
0.1µF
0.1µF
0.1µF
50Ω
200Ω
442Ω
2:1
DUAL
FILTER
LOW-PASS
FILTER
CT
V
V
IN
OCM
60.4Ω
ADA4939
261Ω
442Ω
200Ω
0.1µF
402Ω
Figure 41. Test Circuit for Distortion Measurements
Rev. 0 | Page 15 of 24
ADA4939-1/ADA4939-2
OPERATIONAL DESCRIPTION
Common-Mode Voltage
DEFINITION OF TERMS
–FB
Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as
R
F
R
G
G
+IN
–IN
–OUT
+D
IN
V
OUT, cm = (V+OUT + V−OUT)/2
V
R
V
OUT, dm
OCM
L, dm
ADA4939
–D
IN
Balance
+OUT
R
R
F
Output balance is a measure of how close the differential signals
are to being equal in amplitude and opposite in phase. Output
balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
comparing the magnitude of the signal at the divider midpoint
with the magnitude of the differential signal (see Figure 39). By
this definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage.
+FB
Figure 42. Circuit Definitions
±ifferential Voltage
Differential voltage refers to the difference between two
node voltages. For example, the output differential voltage (or
equivalently, output differential-mode voltage) is defined as
V
OUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
VOUT, cm
Output Balance Error =
VOUT, dm
Rev. 0 | Page 16 of 24
ADA4939-1/ADA4939-2
THEORY OF OPERATION
The ADA4939 differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions and an
additional input, VOCM. Like an op amp, it relies on high open-
loop gain and negative feedback to force these outputs to the
desired voltages. The ADA4939 behaves much like a standard
voltage feedback op amp and facilitates single-ended-to-differential
conversions, common-mode level shifting, and amplifications of
differential signals. Like an op amp, the ADA4939 has high input
impedance and low output impedance. Because it uses voltage
feedback, the ADA4939 manifests a nominally constant gain-
bandwidth product.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 42 can be
determined by
VOUT, dm
RF
RG
=
VIN, dm
This presumes that the input resistors (RG) and feedback resistors
(RF) on each side are equal.
STABLE FOR GAINS ≥2
The ADA4939 frequency response exhibits excessive peaking
for differential gains <2; therefore, the part should be operated
with differential gains ≥2.
Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback, set
with external resistors, controls only the differential output voltage.
The common-mode feedback controls only the common-mode
output voltage. This architecture makes it easy to set the output
common-mode level to any arbitrary value within the specified
limits. The output common-mode voltage is forced, by the internal
common-mode feedback loop, to be equal to the voltage applied
to the VOCM input.
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4939 can be estimated
using the noise model in Figure 43. The input-referred noise
voltage density, vnIN, is modeled as a differential input, and the
noise currents, inIN− and inIN+, appear between each input and
ground. The output voltage due to vnIN is obtained by multiplying
v
nIN by the noise gain, GN (defined in the GN equation that
The internal common-mode feedback loop produces outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. This results in
differential outputs that are very close to the ideal of being
identical in amplitude and are exactly 180° apart in phase.
follows). The noise currents are uncorrelated with the same
mean-square value, and each produces an output voltage that is
equal to the noise current multiplied by the associated feedback
resistance. The noise voltage density at the VOCM pin is vnCM
.
When the feedback networks have the same feedback factor, as
in most cases, the output noise due to vnCM is common-mode.
Each of the four resistors contributes (4kTRxx)1/2. The noise
from the feedback resistors appears directly at the output, and
the noise from the gain resistors appears at the output multiplied
by RF/RG. Table 11 summarizes the input noise sources, the
multiplication factors, and the output-referred noise density terms.
ANALYZING AN APPLICATION CIRCUIT
The ADA4939 uses high open-loop gain and negative feedback
to force its differential and common-mode output voltages in
such a way as to minimize the differential and common-mode
error voltages. The differential error voltage is defined as the
voltage between the differential inputs labeled +IN and −IN
(see Figure 42). For most purposes, this voltage can be assumed
to be zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also
be assumed to be zero. Starting from these two assumptions,
any application circuit can be analyzed.
V
V
nRG1
nRF1
R
R
F1
G1
inIN+
+
V
nIN
V
nOD
inIN–
ADA4939
V
OCM
V
nCM
R
R
F2
G2
V
V
nRG2
nRF2
Figure 43. Noise Model
Rev. 0 | Page 17 of 24
ADA4939-1/ADA4939-2
Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks
Input Noise
Voltage Density
Output
Multiplication Factor
Differential Output Noise
Voltage Density Term
Input Noise Contribution
Differential Input
Inverting Input
Noninverting Input
VOCM Input
Gain Resistor RG1
Gain Resistor RG2
Feedback Resistor RF1
Feedback Resistor RF2
Input Noise Term
vnIN
inIN
inIN
vnCM
vnRG1
vnRG2
vnRF1
vnRF2
vnIN
GN
1
1
0
RF1/RG1
RF2/RG2
1
1
vnO1 = GN(vnIN)
vnO2 = (inIN)(RF2)
vnO3 = (inIN)(RF1)
vnO4 = 0
vnO5 = (RF1/RG1)(4kTRG1)1/2
vnO6 = (RF2/RG2)(4kTRG2)1/2
vnO7 = (4kTRF1)1/2
vnO8 = (4kTRF2)1/2
inIN × (RF2)
inIN × (RF1)
vnCM
(4kTRG1)1/2
(4kTRG2)1/2
(4kTRF1)1/2
(4kTRF2)1/2
Table 12. Differential Input, DC-Coupled
Nominal Gain (dB)
RF (Ω)
RG (Ω) RIN, dm (Ω) Differential Output Noise Density (nV/√Hz)
6
10
14
402
402
402
200
127
80.6
400
254
161
9.7
12.4
16.6
Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω
Nominal Gain (dB)
RF (Ω) RG1 (Ω)
RT (Ω) RIN, cm (Ω)
RG2 (Ω)1
228
155
111
Differential Output Noise Density (nV/√Hz)
6
10
14
402
402
402
200
127
80.6
60.4
66.5
76.8
301
205
138
9.1
11.1
13.5
1 RG2 = RG1 + (RS||RT).
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the input-
referred terms at +IN and −IN by the appropriate output factor,
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
where:
2
GN
=
is the circuit noise gain.
(
β1 + β2
RG1
)
RG2
β1 =
and β2 =
are the feedback factors.
RF1 + RG1
RF2 + RG2
The gain from the VOCM pin to VO, dm is equal to
2(β1 − β2)/(β1 + β2)
When the feedback factors are matched, RF1/RG1 = RF2/RG2, β1 =
β2 = β, and the noise gain becomes
When β1 = β2, this term goes to zero and there is no differential
output voltage due to the voltage on the VOCM input (including
noise). The extreme case occurs when one loop is open and the
other has 100% feedback; in this case, the gain from VOCM input
to VO, dm is either +2 or −2, depending on which loop is closed. The
feedback loops are nominally matched to within 1% in most
applications, and the output noise and offsets due to the VOCM
input are negligible. If the loops are intentionally mismatched by a
large amount, it is necessary to include the gain term from VOCM
to VO, dm and account for the extra noise. For example, if β1 = 0.5
and β2 = 0.25, the gain from VOCM to VO, dm is 0.67. If the VOCM pin
is set to 2.5 V, a differential offset voltage is present at the output of
(2.5 V)(0.67) = 1.67 V. The differential output noise contribution is
(7.5 nV/√Hz)(0.67) = 5 nV/√Hz. Both of these results are
undesirable in most applications; therefore, it is best to use
nominally matched feedback factors.
1
β
RF
RG
GN
=
=1+
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
8
vnOD
=
v2
nOi
∑
i=1
Table 12 and Table 13 list several common gain settings,
associated resistor values, input impedance, and output noise
density for both balanced and unbalanced input configurations.
Rev. 0 | Page 18 of 24
ADA4939-1/ADA4939-2
Mismatched feedback networks also result in a degradation of
the ability of the circuit to reject input common-mode signals,
much the same as for a four-resistor difference amplifier made
from a conventional op amp.
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor RG. The common-mode
voltage at the amplifier input terminals can be easily determined by
noting that the voltage at the inverting input is equal to the
noninverting output voltage divided down by the voltage divider
formed by RF and RG in the lower loop. This voltage is present at
both input terminals due to negative voltage feedback and is in
phase with the input signal, thus reducing the effective voltage
across RG in the upper loop and partially bootstrapping RG.
As a practical summarization of the above issues, resistors of 1%
tolerance produce a worst-case input CMRR of approximately
40 dB, a worst-case differential-mode output offset of 25 mV
due to a 2.5 V VOCM input, negligible VOCM noise contribution,
and no significant degradation in output balance error.
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 44, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = 2 × RG.
Terminating a Single-Ended Input
This section deals with how to properly terminate a single-
ended input to the ADA4939 with a gain of 2, RF = 400 Ω, and
RG = 200 Ω. An example using an input source with a terminated
output voltage of 1 V p-p and source resistance of 50 Ω illustrates
the four simple steps that must be followed. Note that because
the terminated output voltage of the source is 1 V p-p, the open
circuit output voltage of the source is 2 V p-p. The source shown
in Figure 46 indicates this open-circuit voltage.
R
F
ADA4939
+V
S
R
R
G
G
+IN
+D
–D
IN
V
OCM
V
OUT, dm
IN
1. The input impedance must be calculated using the formula
–IN
R
⎛
⎜
⎞
⎟
⎛
⎜
⎞
⎟
F
RG
RF
2×(RG + RF )
200
400
2×(200 + 400)
⎜
⎜
⎟
⎟
⎜
⎜
⎟
⎟
Figure 44. ADA4939 Configured for Balanced (Differential) Inputs
RIN =
=
= 300ꢀ
1−
1−
For an unbalanced, single-ended input signal (see Figure 45),
the input impedance is
⎜
⎝
⎟
⎠
⎜
⎟
⎝
⎠
R
F
⎛
⎜
⎞
⎟
400Ω
+V
S
R
300Ω
IN
RG
RF
RG + RF
⎜
⎜
⎟
⎟
RIN, SE
=
R
R
G
S
1−
⎜
⎟
2×
(
)
50Ω
200Ω
⎝
⎠
V
S
V
OCM
ADA4939
R
V
2V p-p
R
L
OUT, dm
F
R
G
+V
200Ω
R
, SE
IN
S
R
G
–V
S
R
F
V
OCM
400Ω
ADA4939
R
V
OUT, dm
L
R
Figure 46. Calculating Single-Ended Input Impedance RIN
G
–V
S
R
F
Figure 45. ADA4939 with Unbalanced (Single-Ended) Input
Rev. 0 | Page 19 of 24
ADA4939-1/ADA4939-2
2. In order to match the 50 Ω source resistance, the termi-
nation resistor, RT, is calculated using RT||300 Ω = 50 Ω.
The closest standard 1% value for RT is 60.4 Ω.
It is useful to point out two effects that occur with a
terminated input. The first is that the value of RG is increased
in both loops, lowering the overall closed-loop gain. The
second is that VTH is a little larger than 1 V p-p, as it would
be if RT = 50 Ω. These two effects have opposite impacts on
the output voltage, and for large resistor values in the feedback
loops (~1 kΩ), the effects essentially cancel each other out.
For small RF and RG, however, the diminished closed-loop
gain is not canceled completely by the increased VTH. This
can be seen by evaluating Figure 49.
R
F
400Ω
+V
R
50Ω
IN
S
R
R
S
G
50Ω
200Ω
R
60.4Ω
T
V
S
V
OCM
ADA4939
R
V
OUT, dm
2V p-p
L
R
G
200Ω
The desired differential output in this example is 2 V p-p
because the terminated input signal was 1 V p-p and the
closed-loop gain = 2. The actual differential output voltage,
however, is equal to (1.09 V p-p)(400/227.4) = 1.92 V p-p.
To obtain the desired output voltage of 2 V p-p, a final gain
adjustment can be made by increasing RF without modifying
any of the input circuitry. This is discussed in Step 4.
–V
S
R
F
400Ω
Figure 47. Adding Termination Resistor RT
3. It can be seen from Figure 47 that the effective RG in the
upper feedback loop is now greater than the RG in the
lower loop due to the addition of the termination resistors.
To compensate for the imbalance of the gain resistors,
a correction resistor (RTS) is added in series with RG in the
lower loop. RTS is equal to the Thevenin equivalent of the
source resistance RS and the termination resistance RT and
is equal to RS||RT.
4. The feedback resistor value is modified as a final gain
adjustment to obtain the desired output voltage.
To make the output voltage VOUT = 2 V p-p, RF must be
calculated using the following formula:
RF =
R
(
Desired VOUT,dm
(
) RG + RTS
)
2VP−P )(227.4Ω
( )
= = 417Ω
R
S
TH
50Ω
R
60.4Ω
27.4Ω
T
VTH
1.09VP−P
V
V
S
TH
2V p-p
1.09V p-p
The closest standard 1 % values to 417 Ω are 412 Ω and
422 Ω. Choosing 422 Ω gives a differential output voltage
of 2.02 V p-p.
Figure 48. Calculating the Thevenin Equivalent
RTS = RTH = RS||RT = 27.4 Ω. Note that VTH is greater than
1 V p-p, which was obtained with RT = 50 Ω. The modified
circuit with the Thevenin equivalent of the terminated source
and RTS in the lower feedback loop is shown in Figure 49.
The final circuit is shown in Figure 50.
R
F
422Ω
+V
1V p-p
S
R
F
R
R
S
G
400Ω
+V
50Ω
200Ω
R
60.4Ω
T
V
S
S
V
OUT, dm
V
OCM
ADA4939
R
2V p-p
L
2.02V p-p
R
R
TH
G
R
G
27.4Ω
200Ω
200Ω
R
27.4Ω
V
TS
TH
V
OCM
V
OUT, dm
ADA4939
R
1.09V p-p
L
–V
S
R
G
R
F
200Ω
R
27.4Ω
TS
422Ω
–V
S
Figure 50. Terminated Single-Ended-to-Differential System with G = 2
R
F
400Ω
Figure 49. Thevenin Equivalent and Matched Gain Resistors
Figure 49 presents a tractable circuit with matched
feedback loops that can be easily evaluated.
Rev. 0 | Page 20 of 24
ADA4939-1/ADA4939-2
INPUT COMMON-MODE VOLTAGE RANGE
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The ADA4939 input common-mode range is centered between the
two supply rails, in contrast to other ADC drivers with level-shifted
input ranges, such as the ADA4937. The centered input common-
mode range is best suited to ac-coupled, differential-to-differential
and dual supply applications.
The VOCM pin of the ADA4939 is internally biased with a voltage
divider comprising two 20 kΩ resistors at a voltage approximately
equal to the midsupply point, [(+VS) + (−VS)]/2. Because of this
internal divider, the VOCM pin sources and sinks current, depending
on the externally applied voltage and its associated source
resistance. Relying on the internal bias results in an output
common-mode voltage that is within about 100 mV of the
expected value.
For 5 V single-supply operation, the input common-mode
range at the summing nodes of the amplifier is specified as
1.1 V to 3.9 V and is specified as 0.9 V to 2.4 V with a 3.3 V
supply. To avoid nonlinearities, the voltage swing at the +IN
and −IN terminals must be confined to these ranges.
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source or resistor divider be used with source resistance less
than 100 Ω. The output common-mode offset listed in the
Specifications section assumes that the VOCM input is driven
by a low impedance voltage source.
INPUT AND OUTPUT CAPACITIVE AC COUPLING
Input ac coupling capacitors can be inserted between the source
and RG. This ac coupling blocks the flow of the dc common-
mode feedback current and causes the ADA4939 dc input
common-mode voltage to equal the dc output common-mode
voltage. These ac coupling capacitors must be placed in both
loops to keep the feedback factors matched.
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 10 kΩ. If multiple
ADA4939 devices share one reference output, it is recommended
that a buffer be used.
Output ac coupling capacitors can be placed in series between
each output and its respective load. See Figure 54 for an
example that uses input and output capacitive ac coupling.
MINIMUM RG VALUE OF 50 Ω
Due to the wide bandwidth of the ADA4939, the value of RG must
be greater than or equal to 50 Ω to provide sufficient damping in
the amplifier front end. In the terminated case, RG includes the
Thevenin resistance of the source and load terminations.
Rev. 0 | Page 21 of 24
ADA4939-1/ADA4939-2
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4939 is sensitive to the
PCB environment in which it operates. Realizing its superior
performance requires attention to the details of high speed
PCB design. This section shows a detailed example of how the
ADA4939-1 was addressed.
The power supply pins should be bypassed as close to the device
as possible and directly to a nearby ground plane. High frequency
ceramic chip capacitors should be used. It is recommended that
two parallel bypass capacitors (1000 pF and 0.1 μF) be used for
each supply. The 1000 pF capacitor should be placed closer to
the device. Further away, low frequency bypassing should be
provided, using 10 μF tantalum capacitors from each supply
to ground.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4939-1 as possible.
However, the area near the feedback resistors (RF), gain resistors
(RG), and the input summing nodes (Pin 2 and Pin 3) should be
cleared of all ground and power planes (see Figure 51). Clearing
the ground and power planes minimizes any stray capacitance at
these nodes and prevents peaking of the response of the amplifier
at high frequencies.
Signal routing should be short and direct to avoid parasitic
effects. Wherever complementary signals exist, a symmetrical
layout should be provided to maximize balanced performance.
When routing differential signals over a long distance, PCB
traces should be close together, and any differential wiring
should be twisted such that loop area is minimized. Doing this
reduces radiated energy and makes the circuit less susceptible
to interference.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity four-layer
circuit board, as described in EIA/JESD 51-7.
1.30
0.80
1.30 0.80
Figure 51. Ground and Power Plane Voiding in Vicinity of RF and RG
Figure 52. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)
1.30
TOP METAL
GROUND PLANE
0.30
PLATED
VIA HOLE
POWER PLANE
BOTTOM METAL
Figure 53. Cross-Section of Four-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)
Rev. 0 | Page 22 of 24
ADA4939-1/ADA4939-2
HIGH PERFORMANCE ADC DRIVING
The ADA4939 is ideally suited for broadband ac-coupled and
differential-to-differential applications on a single supply.
In this example, the signal generator has a 1 V p-p symmetric,
ground-referenced bipolar output when terminated in 50 Ω.
The VOCM pin of the ADA4939 is bypassed for noise reduction
and left floating such that the internal divider sets the output
common-mode voltage nominally at midsupply. Because the
inputs are ac-coupled, no dc common-mode current flows in
the feedback loops, and a nominal dc level of midsupply is
present at the amplifier input terminals. Besides placing the
amplifier inputs at their optimum levels, the ac coupling technique
lightens the load on the amplifier and dissipates less power than
applications with dc-coupled inputs. With an output common-
mode voltage of nominally 2.5 V, each ADA4937 output swings
between 2.0 V and 3.0 V, providing a gain of 2 and a 2 V p-p
differential signal to the ADC input.
The circuit in Figure 54 shows a front-end connection for an
ADA4939 driving an AD9445, 14-bit, 105 MSPS ADC, with ac
coupling on the ADA4939 input and output. (The AD9445
achieves its optimum performance when driven differentially.)
The ADA4939 eliminates the need for a transformer to drive
the ADC and performs a single-ended-to-differential conversion
and buffering of the driving signal.
The ADA4939 is configured with a single 5 V supply and gain
of 2 for a single-ended input to differential output. The 60.4 Ω
termination resistor, in parallel with the single-ended input
impedance of approximately 300 Ω, provides a 50 Ω termination
for the source. The additional 27.4 Ω (227.4 Ω total) at the
inverting input balances the parallel impedance of the 50 Ω
source and the termination resistor driving the noninverting input.
The output of the amplifier is ac-coupled to the ADC through a
second-order, low-pass filter with a cutoff frequency of 100 MHz.
This reduces the noise bandwidth of the amplifier and isolates
the driver outputs from the ADC inputs.
The AD9445 is configured for a 2 V p-p full-scale input by
connecting the SENSE pin to AGND, as shown in Figure 54.
5V (A) 3.3V (A) 3.3V (D)
412Ω
5V
AVDD2 AVDD1 DRVDD
30nH
0.1µF
0.1µF
0.1µF
200Ω
50Ω
VIN–
47pF
VIN+
AD9445
+
BUFFER T/H
24.3Ω
24.3Ω
V
60.4Ω
OCM
ADA4939
14
ADC
200Ω
SIGNAL
GENERATOR
30nH
0.1µF
0.1µF
CLOCK/
TIMING
REF
27.4Ω
412Ω
AGND
SENSE
Figure 54. ADA4939 Driving an AD9445 ADC with AC-Coupled Input and Output
Rev. 0 | Page 23 of 24
ADA4939-1/ADA4939-2
OUTLINE DIMENSIONS
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
13
12
16
1
0.45
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
9 (BOTTOM VIEW)
4
0.50
BSC
8
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 55. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad (CP-16-2)
Dimensions shown in millimeters
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
PIN 1
INDICATOR
0.50
BSC
2.25
TOP
VIEW
3.75
BSC SQ
EXPOSED
2.10 SQ
1.95
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
6
13
7
12
0.25 MIN
0.80 MAX
0.65TYP
2.50 REF
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad (CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Package Option
CP-16-2
CP-16-2
Ordering Quantity
Branding
H1E
H1E
ADA4939-1YCPZ-R21
ADA4939-1YCPZ-RL1
ADA4939-1YCPZ-R71
ADA4939-2YCPZ-R21
ADA4939-2YCPZ-RL1
ADA4939-2YCPZ-R71
250
5,000
1,500
250
5,000
1,500
CP-16-2
H1E
CP-24-1
CP-24-1
CP-24-1
1 Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07429-0-5/08(0)
Rev. 0 | Page 24 of 24
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