ADAR2004 [ADI]
10 GHz to 40 GHz, 4-Channel Rx Mixer with 4Ã LO Multiplier/Filter;
| 型号： | ADAR2004 |
| 厂家： | 
ADI |
| 描述： | 10 GHz to 40 GHz, 4-Channel Rx Mixer with 4Ã LO Multiplier/Filter |
| 文件： | 总37页 (文件大小：758K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10 GHz to 40 GHz, 4-Channel Rx Mixer with
4× LO Multiplier/Filter
Data Sheet
ADAR2004
FEATURES
GENERAL DESCRIPTION
Quad LNA, mixer, IF VGA
The ADAR2004 is a 4-channel receiver IC that is optimized for
4× LO multiplier with programmable harmonic filter
RF input frequency range: 10 GHz to 40 GHz
IF output frequency range: 0 MHz to 800 MHz
LO input frequency range: 2.4 GHz to 10.1 GHz
Gain range: 21 dB to 41 dB
Input P1dB: −20 dBm typical (at minimum gain)
Noise figure: 9 dB typical (at maximum gain)
3-wire or 4-wire SPI control
On-chip programmable state machines for fast
multiplier/filter and receiver switching and control
On-chip temperature sensor and ADC
DC power: 910 mW (2.5 V supply)
7 mm × 7 mm, 48-terminal LGA package
millimeter wave body scanning applications. Accepting differential
input signals from 10 GHz to 40 GHz, the ADAR2004 provides a
low intermediate frequency (IF) output up to 800 MHz. Each
receive channel also has independent gain control.
The mixer local oscillator (LO) path includes a 4× multiplier
requiring an applied LO frequency between 2.4 GHz and
10.1 GHz. The 4× multiplier block includes a programmable filter
that helps keep harmonics down before reaching the mixer.
Two programmable state machines are included to facilitate
simple configuration, control, and fast switching of the frequency
multiplier, filter, and receiver sections. These sequencers are
programmed through the serial peripheral interface (SPI) and
are then operated by pulsed inputs (reset and advance).
APPLICATIONS
Millimeter wave imaging
Security
Medical
Industrial
The ADAR2004 requires only a single 2.5 V supply with power
consumption of 910 mW with all channels turned on.
The ADAR2004 is available in a 7 × 7 mm, 48-terminal LGA
package and is specified from −40°C to +85°C.
Multichannel receivers
FUNCTIONAL BLOCK DIAGRAM
ADAR2004
RECEIVER SEQUENCER
RFIN1+
RFIN1–
IFOUT1+
IFOUT1–
LNA
LNA
LNA
LNA
VGA
VGA
VGA
VGA
RFIN2+
RFIN2–
IFOUT2+
IFOUT2–
RFIN3+
RFIN3–
IFOUT3+
IFOUT3–
RFIN4+
RFIN4–
IFOUT4+
IFOUT4–
MULTIPLIER/FILTER SEQUENCER
×4
LOIN
BUFFER
×4
×4
CS
SDIO
SCLK
SDO
SPI
CONTROL
ADC
TEMPERATURE
SENSOR
MULTIPLIER/FILTER
STATE MACHINE
(16 STATES)
RECEIVER
STATE MACHINE
(16 STATES)
MRST
MADV
RxRST
RxADV
Figure 1.
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice.
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Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
ADAR2004
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
ADC and ADC Clock ................................................................ 17
Applications Information ............................................................. 18
SPI Control.................................................................................. 18
State Machine Modes vs. States................................................ 18
State Machine Setup .................................................................. 18
Multiplier/Filter State Machine................................................ 19
Receiver State Machine ............................................................. 19
Frequency Sweep All Channels................................................ 20
Sequencer Sleep Control ........................................................... 20
Sequencer Sleep Hold................................................................ 21
Sequencer Control Latch Bypass.............................................. 21
Parallel Chip Control................................................................. 22
Multichip Frequency Sweep ..................................................... 22
Bias Points and Voltages ............................................................... 24
Register Summary .......................................................................... 25
Outline Dimensions....................................................................... 37
Ordering Guide .......................................................................... 37
Applications ...................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ........................................................... 7
Thermal Resistance...................................................................... 7
Electrostatic Discharge (ESD) Ratings...................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions ............................ 8
Typical Performance Characteristics........................................... 10
Theory of Operation ...................................................................... 16
Overview...................................................................................... 16
LO Input Buffer, 4× Multiplier, and Band-Pass Filter.......... 16
1:4 Signal Splitter Network ....................................................... 16
Receivers...................................................................................... 17
Temperature Sensor................................................................... 17
REVISION HISTORY
8/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 37
Data Sheet
ADAR2004
SPECIFICATIONS
VPOS1, VPOS2, VPOS4 = 2.5 V, VPOS3 = VREG, and TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
OVERALL PERFORMANCE
Input Power for 1 dB Compression (P1dB)
Minimum gain
Maximum gain
Minimum gain, −50 dBm per tone
Maximum gain, −50 dBm per tone
Minimum gain
−20
−36
−11
−25
11
dBm
dBm
dBm
dBm
dB
Input Third-Order Intercept (IP3)
Noise Figure
Gain
Maximum gain
Minimum gain
9
21
dB
dB
Maximum gain
41
dB
Gain Step
2.9
2
−0.05
dB
dB
dB/°C
Gain Flatness vs. RF Input Frequency
Gain Change vs. Temperature
RF INPUT
Frequency Range
Differential Input Impedance
Return Loss
10
0
40
GHz
Ω
dB
100
−11
10 GHz to 40 GHz
IF OUTPUT
Frequency Range
Bandwidth
Differential Output Impedance
Peak-to-Peak Output Voltage Swing
800
MHz
MHz
Ω
V
V
dB
ns
V
3 dB bandwidth, maximum gain
800
100
1.125
0.632
−20
5
At P1dB point, minimum gain
At P1dB point, maximum gain
Return Loss
Amplitude Settling time
Output Common-Mode Voltage (VOCM
<1 dB
Minimum
Maximum
)
0.65
1.2
V
LO INPUT
Frequency Range
Power Range
Impedance
2.4
−25
10.1
−10
GHz
dBm
Ω
−20
50
Return Loss
−12
dB
STATE MACHINES AND TIMING
Minimum Pulse Width
MADV, MRST
3
3
ns
ns
RxADV, RxRST
Minimum Pulse Separation
MADV, MRST
RxADV, RxRST
Switching Frequency
Switching Time
Multiplier Band Sleep to Active
Multiplier Band Switch
Receiver Sleep to Active
DIGITAL INPUT LOGIC LEVELS
Logic Low
Pulse start to pulse start
Using ready mode
10
10
ns
ns
MHz
100
0.3
50
10
50
ns
ns
ns
Using ready mode
0
1.8
V
V
Logic High
1
Rev. 0 | Page 3 of 37
ADAR2004
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL OUTPUT LOGIC LEVELS
Logic Low
Logic High
0
1.8
1.8
0.4
V
V
V
1.4
VREG OUTPUT
POWER SUPPLY
Analog
Supply Voltage Range (VPOS1, VPOS2, VPOS4
Current Consumption
)
2.25
1.6
2.5
364
3
910
7.5
2.75
V
All channels active
Chip disabled
All channels active
Chip disabled
mA
mA
mW
mW
Power Consumption
Digital
Supply Voltage Range (VPOS3
Current Consumption
Power Consumption
)
1.8
25
45
2
V
µA
µW
Rev. 0 | Page 4 of 37
Data Sheet
ADAR2004
TIMING SPECIFICATIONS
VPOS1, VPOS2, VPOS4 = 2.5 V, VPOS3 = VREG, and TA = −40°C to +85°C, unless otherwise noted. See Figure 2 to Figure 4 for the timing diagrams.
Table 2. SPI Timing
Parameter
Description
Test Conditions/Comments
Write only
Write and read
Min
Typ
Max
40
15
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
fSCLK
Maximum clock rate
tPWH
tPWL
tDS
tDH
tDV
tDCS
tR
Minimum pulse width high
Minimum pulse width low
Setup time, SDIO to SCLK
Hold time, SDIO to SCLK
Data valid, SDO to SCLK
Setup time, CS to SCLK
SDIO, SDO rise time
10
10
5
5
5
10
40
40
Outputs loaded with 10 pF, 10% to 90%
Outputs loaded with 10 pF, 10% to 90%
ns
ns
tF
SDIO, SDO fall time
Timing Diagrams
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK DON’T CARE
DON’T CARE
DON’T CARE
SDIO DON’T CARE
R/W
A14
A13
A2
A1
A0
D7
D6
D5
D2
D1
D0
Figure 2. SPI Transaction Structure (MSB First)
CS
t
t
PWH
DCS
SCLK DON’T CARE
DON’T CARE
DON’T CARE
t
DS
t
DH
t
PWL
A13
SDIO DON’T CARE WRITE
A14
A2
A1
A0
D7
D6
D5
D2
D1
D0
Figure 3. SPI Write Timing Diagram
CS
SCLK DON’T CARE
DON’T CARE
DON’T CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
SDIO DON’T CARE
READ
A14
A13
A2
A1
A0
t
DV
D7
D6
D5
D1
D0
SDO
t
t
F
R
Figure 4. SPI 4-Wire Read Timing Diagram
Rev. 0 | Page 5 of 37
ADAR2004
Data Sheet
SPI Block Write Mode
Data can be written to the SPI registers using the block write mode where the register address automatically increments and data for
CS
consecutive registers can be written without sending new address bits. Data writing can be continued indefinitely until
ending the transaction (see Figure 5).
is raised,
CS
SCLK DON’T CARE
DON’T CARE
DON’T CARE
SDIO DON’T CARE WRITE
A14
A13
A1
A0
D7
D6
D1
D0
D7
D6
D1
D0
FIRST REGISTER ADDRESS
FIRST REGISTER DATA
(n + FIRST REGISTER) DATA
Figure 5. SPI Block Write
Rev. 0 | Page 6 of 37
Data Sheet
ADAR2004
ABSOLUTE MAXIMUM RATINGS
Table 3.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
Parameter
VPOS1, VPOS2, VPOS4 to GND1
VPOS3 to GND1
Digital Input to GND1
RFINx , LOIN to GND1
RFINx Power
Rating
+3 V, −0.3 V
+2 V, −0.3 V
2 V
0.3 V
20 dBm
−5 dBm
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.
ESD Ratings for ADAR2004
LOIN Power
Table 5. ADAR2004, 48-Terminal LGA
Temperature
ESD Model
Withstand Threshold (V)
Class
1C
C3
Operating Range
Storage Range
Junction
−40°C to +85°C
−65°C to +150°C
135°C
HBM
CDM
1000 to 2000
1000 to 1250
Reflow Soldering
Peak Temperature
260°C
ESD CAUTION
1 GND is the common ground to which all GNDx pins are connected.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 4. Thermal Resistance
Package Type
θJA
θJC
Unit
CC-48-21
32.1
11
°C/W
1 Pad soldered.
Rev. 0 | Page 7 of 37
ADAR2004
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
48 47 46 45 44 43 42 41 40 39 38 37
V
POS1
36
35
34
33
GND1
RFIN2–
RFIN2+
GND2
GND13
LOIN
GND12
VREG
32
GND3
V
POS3
ADAR2004
31
GND4
MADV
MRST
RxADV
RxRST
SCLK
SDIO
TOP VIEW
(Not to Scale)
30
GND5
9
29
28
27
26
GND6
10
11
12
RFIN3+
RFIN3–
GND7
13 14 15 16 17 18 19 20 21 22 23 24 25
CS
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED
TO A GROUND PLANE WITH LOW THERMAL AND
ELECTRICAL IMPEDANCE.
Figure 6. Pin Configuration (Top View, Not to Scale)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 13, 38
VPOS1, VPOS2, VPOS4
2.5 V Power Supply for the Analog Section. Connect decoupling capacitors (one 10 nF and one
100 pF on each pin and a 1 µF for the rail) to the ground plane as close as possible to the VPOS1
POS2, and VPOS4 pins.
,
V
2, 5 to 9, 12, 14,
17, 18, 23, 34,
36, 37, 39, 44,
45, 48
GND1 to GND18
Ground. Connect all ground pins to a ground plane with low thermal and electrical impedance.
3, 4, 10, 11, 15,
16, 46, 47
RFIN2−, RFIN2+,
RFIN3+, RFIN3−,
RFIN4+, RFIN4−,
RFIN1−, RFIN1+
Differential RF Inputs. RFINx are 100 Ω differential pairs, ac-coupled internally. The RFINx pins
operate from 10 GHz to 40 GHz. All eight lines must have equal electrical and mechanical lengths
to ensure consistent performance from channel to channel.
19 to 22, 40 to 43 IFOUT4+, IFOUT4−, Differential IF Outputs. IFOUTx are 100 Ω differential pairs, dc-coupled internally. The IFOUTx
IFOUT3+, IFOUT3−, pins operate from low frequency to 800 MHz. VOCM = 0.8 V. All eight lines must have equal
IFOUT2−, IFOUT2+, electrical and mechanical lengths.
IFOUT1−, IFOUT1+
24
25
SDO
CS
Serial Data Output. Register states can be read back on the SDO line if Register 0x000, Bits[4:3] are
set high.
Chip Select Bar. Pull the CS pin low to activate the SPI port. CS is used to activate the SPI port on
the ADAR2004 and is active low. When CS goes high, the data stored in the shift registers is latched.
Connect a 200 kΩ pull-up resistor to 1.8 V to ensure that the SPI is shut off while not in use.
26
SDIO
Serial Data Input and Output. The SDIO pin is a high impedance data input for clocking in information.
The SDIO pin can also be used to read out data if Register 0x000, Bits[4:3] are set low (default).
27
28
SCLK
RxRST
Serial Clock. The SCLK pin is used to clock data into and out of the SPI.
Receive State Machine Reset. If the state machine is enabled, RxRST immediately sets the receiver
state machine back to the configuration in RX_EN_MODE_0, RX_GAIN12_MODE_0, and
RX_GAIN34_MODE_0 (Register 0x040, Register 0x041, and Register 0x042).
29
RxADV
Receive State Machine Advance. If the state machine is enabled, RxADV advances the receiver
state machine to the next state in its cycle. If currently at the end of the cycle, pulsing RxADV
returns the pointer to the mode defined in RX_STATE_1 (Register 0x01A, Bits[7:4]).
30
31
MRST
Multiplier State Machine Reset. If the state machine is enabled, MRST immediately sets the
multiplier/filter state machine back to the configuration in MULT_EN_MODE_0 (Register 0x070).
Multiplier State Machine Advance. If the state machine is enabled, MADV advances the
multiplier/filter state machine to the next state in its cycle. If currently at the end of the cycle,
pulsing MADV returns the pointer to the mode defined in MULT_STATE_1 (Register 0x022, Bits[7:4]).
MADV
Rev. 0 | Page 8 of 37
Data Sheet
ADAR2004
Pin No.
Mnemonic
Description
1.8 V Power Supply for the Digital Section. Connect this supply directly to VREG. Place a 1 µF
capacitor to ground as close as possible to VPOS3
1.8 V Low Dropout (LDO) Output. Connect VREG directly to VPOS3
LO Input. LOIN is a single-ended, 50 Ω input operating from 2.4 GHz to 10.1 GHz, ac-coupled
internally. The nominal input power level is −20 dBm.
32
VPOS3
.
33
35
VREG
LOIN
.
EPAD
Exposed Pad. The exposed pad must be connected to a ground plane with low thermal and
electrical impedance.
Rev. 0 | Page 9 of 37
ADAR2004
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
450
450
400
350
300
250
200
150
100
50
400
350
300
250
200
150
+85°C
100
+25°C
–40°C
+85°C
+25°C
–40°C
50
0
10
0
2.25
15
20
25
30
35
40
2.50
2.75
RF INPUT FREQUENCY (GHz)
SUPPLY VOLTAGE (V)
Figure 7. Supply Current (ICC) vs. RF Input Frequency and Temperature
Figure 10. ICC vs. Supply Voltage and Temperature
1200
1100
1000
900
800
700
600
500
400
300
1200
1000
800
600
400
200
0
+85°C
+25°C
–40°C
200
+85°C
+25°C
–40°C
100
0
10
15
20
25
30
35
40
2.25
2.50
2.75
RF INPUT FREQUENCY (GHz)
SUPPLY VOLTAGE (V)
Figure 8. DC Power Consumption vs. RF Input Frequency and Temperature
Figure 11. DC Power Consumption vs. Supply Voltage and Temperature
50
50
45
40
35
30
GAIN = 0x0
GAIN = 0x1
GAIN = 0x2
GAIN = 0x3
GAIN = 0x4
GAIN = 0x5
GAIN = 0x6
GAIN = 0x7
45
40
35
30
25
20
15
25
+85°C
+25°C
20
–40°C
15
10
10
15
20
25
30
35
40
15
20
25
30
35
40
RF INPUT FREQUENCY (GHz)
RF INPUT FREQUENCY (GHz)
Figure 9. Gain vs. RF Input Frequency and Gain Setting
Figure 12. Gain vs. RF Input Frequency and Temperature (Gain = 0x7)
Rev. 0 | Page 10 of 37
Data Sheet
ADAR2004
50
45
40
35
30
25
20
15
2.75V
2.50V
2.25V
–10dBm
–15dBm
–20dBm
–25dBm
10
15
20
25
30
35
40
10
15
20
25
30
35
40
RF INPUT FREQUENCY (GHz)
RF INPUT FREQUENCY (GHz)
Figure 13. Gain vs. RF Input Frequency and Supply Voltage (VCC) (Gain = 0x7)
Figure 16. Gain vs. RF Input Frequency and LO Input Power
50
50
GAIN = 0x0
GAIN = 0x1
GAIN = 0x2
GAIN = 0x3
GAIN = 0x4
GAIN = 0x5
GAIN = 0x6
GAIN = 0x7
45
40
35
30
25
20
15
45
40
35
30
25
20
15
+85°C
+25°C
–40°C
IF OUTPUT FREQUENCY (MHz)
IF OUTPUT FREQUENCY (MHz)
Figure 14. Gain vs. IF Output Frequency and Gain Setting (RF Input = 25 GHz)
Figure 17. Gain vs. IF Output Frequency and Temperature (RF Input = 25 GHz,
Gain = 0x7)
50
45
40
35
30
25
0
GAIN = 0x0
GAIN = 0x1
GAIN = 0x2
GAIN = 0x3
GAIN = 0x4
GAIN = 0x5
GAIN = 0x6
GAIN = 0x7
–5
–10
–15
–20
–25
–30
2.75V
2.50V
2.25V
20
15
10
15
20
25
30
35
40
RF INPUT FREQUENCY (GHz)
IF OUTPUT FREQUENCY (MHz)
Figure 18. Input IP3 vs. RF Input Frequency and Gain Setting
Figure 15. Gain vs. IF Output Frequency and VCC (RF Input = 25 GHz,
Gain = 0x7)
Rev. 0 | Page 11 of 37
ADAR2004
Data Sheet
0
0
–2
+85°C
+25°C
–40°C
–2
–4
–4
–6
–6
–8
–8
–10
–12
–14
–16
–10
–12
–10dBm
–15dBm
–20dBm
–25dBm
–14
–16
10
15
20
25
30
35
40
10
15
20
25
30
35
40
RF INPUT FREQUENCY (GHz)
RF INPUT FREQUENCY (GHz)
Figure 19. Input IP3 vs. RF Input Frequency and LO Input Power
Figure 22. Input IP3 vs. RF Input Frequency and Temperature
0
0
GAIN = 0x0
GAIN = 0x1
GAIN = 0x2
GAIN = 0x3
GAIN = 0x4
GAIN = 0x5
GAIN = 0x6
GAIN = 0x7
–10dBm
–15dBm
–5
–10
–15
–20
–25
–30
–35
–40
–5
–20dBm
–25dBm
–10
–15
–20
–25
–30
–35
–40
10
15
20
25
30
35
40
10
15
20
25
30
35
40
RF INPUT FREQUENCY (GHz)
RF INPUT FREQUENCY (GHz)
Figure 23. Input P1dB vs. RF Input Frequency and LO Input Power
Figure 20. Input P1dB vs. RF Input Frequency and Gain Setting
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–5
–10
–15
–20
–25
–30
–35
–40
–20
–40
–60
–80
–100
–120
10
15
20
25
30
35
40
RF INPUT FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 21. Input P1dB vs. RF Input Frequency and Temperature
Figure 24. LO Feedthrough vs. LO Frequency and Temperature
Rev. 0 | Page 12 of 37
Data Sheet
ADAR2004
0
100
90
80
70
60
50
40
30
20
10
0
GAIN = 0x0
GAIN = 0x4
GAIN = 0x5
GAIN = 0x6
GAIN = 0x7
GAIN = 0x1
GAIN = 0x2
GAIN = 0x3
GAIN = 0x0
GAIN = 0x1
GAIN = 0x2
GAIN = 0x3
GAIN = 0x4
GAIN = 0x5
GAIN = 0x6
GAIN = 0x7
–20
–40
–60
–80
–100
–120
10
15
20
25
30
35
40
RF INPUT FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 25. LO Feedthrough vs. LO Frequency and Gain Setting
Figure 28. DC Offset vs. RF Input Frequency and Gain Setting
0
100
–10dBm
–20dBm
–25dBm
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
90
80
70
60
50
40
30
20
10
0
–20
–30dBm
–40
–60
–80
–100
–120
50 100
200
300
400
500
600
700
800
900
IF OUTPUT FREQUENCY (MHz)
LO FREQUENCY (GHz)
Figure 29. DC Offset vs. IF Output Frequency and Channel
Figure 26. LO Feedthrough vs. LO Frequency and LO Input Power
90
100
CHANNEL 1
90
80
70
60
50
40
30
20
10
0
CHANNEL 2
CHANNEL 3
CHANNEL 4
80
70
60
50
40
30
20
10
0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
0
1
2
3
4
5
6
7
10
15
20
25
30
35
40
COMMON-MODE SETTING
RF INPUT FREQUENCY (GHz)
Figure 30. DC Offset vs. Common-Mode Setting and Channel
(RF Input = 25 GHz, Gain = 0x7)
Figure 27. DC Offset vs. RF Input Frequency and Channel
Rev. 0 | Page 13 of 37
ADAR2004
Data Sheet
2.0
16
14
12
10
8
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
CHANNEL 1
MADV
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6
+85°C
+25°C
–40°C
4
2
0
10
–0.2
80
–20 –10
0
10
20
30
40
50
60
70
15
20
25
30
35
40
TIME (ns)
RF INPUT FREQUENCY (GHz)
Figure 31. Noise Figure vs. RF Input Frequency and Temperature
Figure 34. Multiplier Sleep to Active Switching Time
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.2
0
16
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
GAIN = 0x0
GAIN = 0x1
GAIN = 0x2
GAIN = 0x3
GAIN = 0x4
GAIN = 0x5
GAIN = 0x6
GAIN = 0x7
CHANNEL 1
MADV
14
12
10
8
6
4
2
0
10
–0.2
–4
–2
0
2
4
6
8
10
12
15
20
25
30
35
40
TIME (ns)
RF INPUT FREQUENCY (GHz)
Figure 35. Frequency Band Switching Time
Figure 32. Noise Figure vs. RF Input Frequency and Gain Setting
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
16
14
12
10
8
CHANNEL 1
RxADV
6
4
–10dBm
–15dBm
2
–20dBm
–25dBm
0
–0.2
80
0
–20 –10
0
10
20
30
40
50
60
70
10
15
20
25
30
35
40
TIME (ns)
RF INPUT FREQUENCY (GHz)
Figure 36. Receiver Sleep to Active Switching Time
Figure 33. Noise Figure vs. RF Input Frequency and LO Input Power
(Gain = 0x0)
Rev. 0 | Page 14 of 37
Data Sheet
ADAR2004
0
–2
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
ENABLED
DISABLED
CHANNEL 1 (REFERENCE)
CHANNEL 2 (DISABLED)
CHANNEL 3 (DISABLED)
CHANNEL 4 (DISABLED)
–4
–6
–8
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
RF INPUT FREQUENCY (GHz)
10
13
16
19
22
25
28
31
34
37
40
RF INPUT FREQUENCY (GHz)
Figure 40. Channel to Channel Isolation vs. RF Input Frequency
Figure 37. RF Input Return Loss vs. RF Input Frequency
180
160
140
120
100
80
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
60
40
20
ENABLED
DISABLED
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
0
100 200 300 400 500 600 700 800 900 1000 1100
IF OUTPUT FREQUENCY (MHz)
Figure 41. ADC Code vs. Temperature
Figure 38. IF Output Return Loss vs. IF Output Frequency
0
–5
–10
–15
–20
–25
–30
–35
–40
LOW BAND
MID BAND
HIGH BAND
DISABLED
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
LO INPUT FREQUENCY (GHz)
Figure 39. LO Input Return Loss vs. LO Input Frequency
Rev. 0 | Page 15 of 37
ADAR2004
Data Sheet
THEORY OF OPERATION
shown in Table 7. SP3T switches at the input and output of the
multiplier block are used to select the desired subcircuit.
OVERVIEW
The main elements of the ADAR2004 are a quad LNA, a mixer,
an IF variable gain amplifier (VGA), a 4× LO frequency multiplier
with integrated switchable harmonic filter, and a 1:4 signal splitter.
Each subcircuit consists of a 4× multiplier and an adjustable
band-pass filter (BPF). The bias levels of the 4× multipliers are
adjustable through the SPI via Register 0x011 and Register 0x012.
See the Bias Points and Voltages section for more information.
The four differential RF inputs are intended to be connected
directly to a differential antenna structure, such as a dipole. Apply
a single-tone LO input signal in the 2.4 GHz to 10.1 GHz
frequency range with a power level of approximately −20 dBm
to the LOIN port. This signal is frequency multiplied by 4 and
filtered before driving the LO inputs of the four mixers.
When the LO input frequency is in the low end of the subcircuit
band, the BPF corner frequency must be set to its low state. Set
the associated bit high to set the BPF corner frequency to its
low state. See Table 7.
To complete a full 9.6 GHz to 40.4 GHz frequency sweep,
adjust the multiplier/filter block settings six times to ensure
optimum harmonic rejection and output power. These six
settings are shown in Table 7.
The operation of these subcircuits can be controlled from the
SPI port as well as two programmable state machines, one
focused on LO multiplier/filter control and the other focused
on quad receiver control.
In addition to having sleep and active modes, the 4× multipliers
can be set to ready mode. Ready mode is a hybrid state between
sleep and active mode. Current consumption in ready mode is
higher than sleep mode but lower than active mode. The switching
time between ready mode and active mode is significantly faster
than from sleep mode to active mode.
The ADAR2004 also includes an Analog Devices, Inc., SPI port
that is used for device configuration and readback. Although
the state machines provide fast switching between states, all
functions can also be controlled directly through the SPI port.
LO INPUT BUFFER, 4× MULTIPLIER, AND BAND-
PASS FILTER
1:4 SIGNAL SPLITTER NETWORK
The LO input buffer provides approximately 17 dB of gain and
provides an optimal drive signal to the 4× multiplier circuits for
LO input power levels down to −25 dBm. The bias levels of the
input and output stages of the input buffer are independently
adjustable through the SPI via Register 0x013. See the Bias Points
and Voltages section for more information.
The output of the multiplier/filter block is then applied to a 1:4
active power splitting network that is composed of two stages.
The first stage is a 1:2 active splitter, which then feeds the second
stage, two 1:2 active splitters. Each output path from the second
stage drives a single downconverting mixer, which results in a
single input signal being split into four independently controlled
channels. The bias levels of each splitter stage are adjustable
through the SPI via Register 0x014. See the Bias Points and
Voltages section for more information.
The broadband frequency multiplier consists of three parallel
subcircuits. Each subcircuit (low band, mid band, high band) is
optimized to multiply and filter a segment of the total frequency
range (2.4 GHz to 10.1 GHz input, 9.6 GHz to 40.4 GHz output).
Recommended ranges and register settings for each band are
Table 7. Multiplier/Filter Settings for Optimal LO Harmonic Rejection
LO Input Frequency
(GHz)
Internal LO Frequency
(GHz)
Multiplier Band
BPF MULT_x1 Register Value
2.40 to 3.00
3.00 to 4.00
4.00 to 5.00
5.00 to 6.25
6.25 to 8.00
8.00 to 10.10
9.6 to 12
12 to 16
16 to 20
20 to 25
25 to 32
32 to 40.4
Low band active (mid and high bands ready)
Low band active (mid and high bands ready)
Mid band active (mid and high bands ready)
Mid band active (low and high bands ready)
High band active (low and mid bands ready)
High band active (low and mid bands ready)
Low 0xFA
High 0x7A
Low 0xEE
High 0x6E
Low 0xEB
High 0x6B
1 MULT_x refers to the MULT_EN_MODE_x and MULT_SPI registers.
Rev. 0 | Page 16 of 37
Data Sheet
ADAR2004
RECEIVERS
ADC AND ADC CLOCK
There are four independent receive channels, each with fully
differential inputs and outputs. Each channel includes an RF
LNA front end, a downconverting mixer, and a dedicated IF
VGA. The inputs operate from 10 GHz to 40 GHz and are
intended to be connected to dipole antennas, whereas the outputs
operate from low frequency to 800 MHz and are meant to be
directly connected to an ADC. The bias levels of the LNAs, mixers,
and IF VGAs are adjustable through the SPI. There is one setting
for all the LNAs (LNA_BIAS in Register 0x015), one setting for
the mixers (MIX_BIAS in Register 0x015), and one setting for
the IF VGAs (IFAMP_BIAS in Register 0x016). The IF VGAs
also have a setting for VOCM (IFAMP_CM in Register 0x017).
See the Bias Points and Voltages section for more information.
The ADAR2004 has an on-chip, 8-bit ADC and a variable clock
input, each with their own enable control bits.
To take a measurement from the ADC, first write to the
ADC_CTRL register, Register 0x030. This register contains the
following bits:
•
Bit 0: ADC_EOC (read only). This bit is a flag for when the
ADC conversion is complete.
•
Bit 4: ST_CONV (read/write). This bit is set to start an
ADC conversion cycle.
•
•
•
Bit 5: CLK_EN (read/write). This bit enables the ADC clock.
Bit 6: ADC_EN (read/write). This bit enables the ADC.
Bit 7: ADC_CLKFREQ_SEL (read/write). This bit is used
to set the clock frequency. A low sets the clock to 2 MHz,
whereas a high sets the clock to 250 kHz.
Although normal operation envisages all four receive channels
operating at one time, the programmability allows any
combination of receive channels to be turned on or off
simultaneously.
After the ADC_CTRL register is written, it must be polled to wait
for the ADC_EOC bit to go high. When the ADC_EOC bit goes
high, the measured value can be read out from the
ADC_OUTPUT register, Register 0x031.
TEMPERATURE SENSOR
The ADAR2004 has an on-chip temperature sensor that feeds
into a dedicated 8-bit ADC for monitoring the temperature of
the chip. Use the following equation to calculate the approximate
temperature in Celsius from the ADC output:
TA = (1.05 × ADC_OUTPUT) – 80
where ADC_OUTPUT is the ADC output word in Register 0x031.
Rev. 0 | Page 17 of 37
ADAR2004
Data Sheet
•
•
•
•
The enabled status of the first 1:2 signal splitter (on or off,
one bit).
APPLICATIONS INFORMATION
SPI CONTROL
The enabled status of the 1:2 signal splitter feeding the
mixers on Channel 1 and Channel 2 (on or off, one bit).
The enabled status of the 1:2 signal splitter feeding the
mixers on Channel 3 and Channel 4 (on or off, one bit).
The gain of each channel (four bits for each, 16 total).
The ADAR2004 is designed to operate as part of a larger array.
The built in state machines help to ease the control of many
chips in parallel and to ensure that the fastest switching speeds
are achieved. However, it is possible to operate every aspect of
the ADAR2004 using the SPI port alone. When the state machines
are disabled by setting MULT_SEQ_EN (Register 0x019, Bit 7)
and RX_SEQ_EN (Register 0x018, Bit 7) low, the multiplier/filter
and receiver blocks respond to the SPI controlled registers
(Register 0x02B to Register 0x02F), rather than stepping
through the programmed states.
Each multiplier/filter state is used to select an operating mode.
Each state bit field contains four bits, allowing selection of any
mode between 0 and 15 (Register 0x070 to Register 0x07F).
There are 16 multiplier/filter states available (Register 0x022 to
Register 0x029). When the multiplier/filter state machine is
enabled and the sequencer depth is set, the multiplier/filter
state machine cycles through the states in order, up to the
defined state machine depth.
MULT_SPI (Register 0x02F) controls the multiplier/filter block
when in SPI mode and has all the same controls as a typical
multiplier/filter mode.
Similarly, each receiver state is used to select an operating mode.
Each state bit field has four bits, allowing the selection of any
mode between 0 and 15 (Register 0x040 to Register 0x06F). There
are 16 receiver states available (Register 0x01A to Register 0x021).
When the receiver state machine is enabled and the sequencer
depth is set, the receiver state machine cycles through the states
in order, up to the defined state machine depth.
Register 0x02B to Register 0x02E control the receiver block
when in SPI mode and have all the same controls as a typical
receiver mode, as well as individual enables for the LNAs, mixers,
and IF VGAs. Note that when the ADAR2004 receiver block is
in SPI mode, the channel enables do not turn on the desired
channel unless each piece of the receiver signal chain (LNA,
mixer, IF VGA) is enabled as well, which contrasts with the
sequencer modes, where a channel enable turns on the entire
channel. The sequencer does not have access to the individual
enables.
Figure 42 shows how the state machine pointer moves through
a loop. In this diagram, n is the total number of states inside the
loop. Because the sequencer depth bit field is 0 indexed, n is equal
to one more than the value in the sequencer depth bit field.
Operating the ADAR2004 in this manner can be thought of as a
manual, rather than an automatic, approach. With the sequencers
disabled, any changes to the configuration of the chip must be
made through an SPI write, because pulsing any of the sequencer
control pins has no effect.
n = MULT_STATES + 1
where:
n = 1 to 16.
MULT_STATES is the multiplier sequencer depth.
n = RX_STATES + 1
STATE MACHINE MODES vs. STATES
where:
n = 1 to 16.
RX_STATES is the receiver sequence depth.
Both the multiplier/filter state machine and the receiver state
machine have 16 modes available to set the configuration of
their respective subcircuitry. The sequencers also have 16 states
available to cycle through.
RESET
0
ADVANCE
Within each mode of the multiplier/filter state machine, the
user can define the following:
1
2
•
•
The enabled status of the RF input buffer (on or off, one bit).
The sleep, ready, or active state of each 4× multiplier band
(two bits for each band, six bits in total). The two bits
control the ready and active status, and if neither bit is
high, the multiplier band is set to sleep. Both bits must be
high to be fully active.
ADVANCE
ADVANCE
n
3
ADVANCE
Figure 42. State Machine Position Loop
STATE MACHINE SETUP
•
The BPF status (on or off, 1 bit for all bands).
Both state machines in the ADAR2004 have configuration
registers that control various aspects of the state machine.
Within each mode of the receiver state machine, the user can
define the following:
For the multiplier/filter sequencer, this register is Register 0x019
and contains the following bits:
•
The enabled status of each receive channel (one bit for
each band, four bits in total). Each bit enables the entire
channel, including the respective LNA, mixer, and IF VGA.
•
Bits 0 to Bit 3: MULT_STATES. These bits set the number
of states in the loop (see Figure 42).
Rev. 0 | Page 18 of 37
Data Sheet
ADAR2004
Eight default modes can be assigned to any of the 16 states.
•
Bit 4: MULT_CTL_LATCH_BYP. This bit bypasses the
These eight modes consist of a sleep mode, a ready mode, and
the six modes required to complete a 9.6 GHz to 40.4 GHz sweep,
as described in Table 7. It is possible to overwrite any of the
multiplier/filter modes with a custom set of operating conditions
by changing the bits in Register 0x070 to Register 0x07F.
latch on MADV and MRST. If the latch is enabled, the
next state is loaded up on the rising edge of a MRST or
MADV pulse. The state is then latched to the device on the
falling edge of the same pulse. If the latch is bypassed,
everything is applied as soon as possible after the rising
edge of the pulse, with no latching.
Bit 5: MULT_SLP_HOLD. This bit prevents the
multiplier/filter block from advancing when forced into a
sleep state by the receiver block. This bit is used in
conjunction with RX_SLP_CTRL (Register 0x018, Bit 6).
See the Sequencer Sleep Hold section for more
information.
Bit 6: MULT_SLP_CTRL. This bit forces the multiplier/filter
block to sleep whenever the receiver block is sleeping. See
the Sequencer Sleep Control section for more information.
Bit 7: MULT_SEQ_EN. This bit enables the multiplier/filter
block. This bit must be set high for the block to operate
with the external pins.
After the modes are defined, set the order in which the sequencer
moves through the desired modes by filling the state bits in
Register 0x022 to Register 0x029 in order with the modes of
interest. Any state can point to any mode, except State 0, which
always points to Mode 0. Note that the sequencer moves
through the states in order, up to the state machine depth.
•
Finally, the user must define how many states are used by setting
the state machine depth (MULT_STATES, Register 0x019,
Bits[3:0]). MULT_STATES is 0 indexed. Therefore, setting the
depth to 0 leaves MULT_STATE_1 (Register 0x022, Bits[7:4])
as the only state in the loop.
•
•
After the multiplier/filter state machine is programmed and
enabled, operation is controlled by the MRST and MADV pins.
Alternatively, operation can be controlled through the SPI using
the MULT_RST_SPI and MULT_ADV_SPI bits (Register 0x02A,
Bit 3 and Bit 2, respectively). Note that using the SPI is slower
than pulsing the sequencer pins directly.
For the receiver sequencer, the control register is Register 0x018
and contains the following bits:
•
Bit 0 to Bit 3: RX_STATES. These bits set the number of
states in the loop (see Figure 42).
•
Bit 4: RX_CTL_LATCH_BYP. This bit bypasses the latch
on RxADV and RxRST. If the latch is enabled, the next state is
loaded up on the rising edge of an RxRST or RxADV pulse.
The state is then latched to the device on the falling edge of
the same pulse. If the latch is bypassed, everything is applied
as soon as possible after the rising edge of the pulse, with
no latching.
Bit 5: RX_SLP_HOLD. This bit prevents the receiver block
from advancing when forced into a sleep state by the
multiplier/filter block. This bit is used in conjunction with
MULT_SLP_CTRL (Register 0x019, Bit 6). See the
Sequencer Sleep Hold section for more information.
Bit 6: RX_SLP_CTRL. This bit forces the receiver block to
sleep whenever the multiplier/filter block is sleeping. See the
Sequencer Sleep Control section for more information.
Bit 7: RX_SEQ_EN. This bit enables the receiver block.
This bit must be set high for the block to operate with the
external pins.
MRST moves the pointer on the multiplier/filter state machine
to State 0 regardless of the current position of the pointer and
can be asserted at any time. State 0 always refers to Mode 0 and
cannot be set to another mode. However, Mode 0 can be
overwritten with any multiplier/filter configuration. Mode 0 is
defined in Register 0x070.
MADV pulses advance the multiplier/filter state machine pointer
one state at a time until the defined sequencer depth is cycled
through. At that point, an additional MADV pulse moves the
pointer back to State 1, which is normally set to a ready mode
(however, State 1 can be set to any mode). State 1 applies the mode
defined in the MULT_STATE_1 bits (Register 0x022, Bits[7:4]).
•
•
•
RECEIVER STATE MACHINE
Like the multiplier/filter state machine, the receiver state
machine can be used to quickly cycle through receiver states
without using the comparatively slower SPI.
To enable the state machine, set the RX_SEQ_EN bit
(Register 0x018, Bit 7) high.
MULTIPLIER/FILTER STATE MACHINE
The receiver state machine controls the status of the four receive
channels (each with an LNA, mixer, and IF VGA) and the status of
the 1:4 splitter network by defining the desired modes of operation
in Register 0x040 to Register 0x06F. Each mode outlines a custom
set of operating conditions.
A programmable state machine provides a convenient and fast
control mechanism for the multiplier/filter block and avoids the
need for SPI writes each time the block must be reconfigured.
To enable the state machine, set the MULT_SEQ_EN bit
(Register 0x019, Bit 7) high.
Although only one active state is required to enable all receive
channels, a state machine depth of 16 is provided for optimum
flexibility of the receiver sequencer and to lower the total number
of control lines required to operate multiple ADAR2004 chips in
parallel. It is possible to control up to 16 ADAR2004 ICs using the
Although only six multiplier/filter modes are required for a
complete 9.6 GHz to 40.4 GHz sweep, as described in Table 7, a
maximum state machine depth of 16 is provided for optimum
flexibility.
Rev. 0 | Page 19 of 37
ADAR2004
Data Sheet
same four sequencer lines (MADV, MRST, RxADV, RxRST). See
the Parallel Chip Control section for more information.
As shown in Figure 43,
•
•
•
•
•
Multiplier/Filter State 0 = sleep (outside the loop)
Following the mode definitions, the user must fill the state bits
in Register 0x01A to Register 0x021 with the modes of interest.
Any state can point to any mode, except State 0, which always
points to Mode 0. Note that the sequencer moves through the
states in order, up to the state machine depth.
Multiplier/Filter State 1 = mid band multiplier ready
Multiplier/Filter State 2 = output 20 GHz to 25 GHz to mixers
Multiplier/Filter State 3 = output 25 GHz to 30 GHz to mixers
Multiplier/Filter State 4 = output 30 GHz to 40 GHz to mixers
The initial state is the sleep state where power consumption is
at a minimum. A pulse on MADV advances the state machine
to the second state, which is defined as a ready state. By partially
powering up the mid band multiplier with its BPF set high, an
additional pulse on MADV makes this subcircuit path active in
under 10 ns. By making use of the ready mode throughout the
sweep, the settling time can be kept under 10 ns.
After defining the states, the user must set the number of states
to be used by the sequencer by changing the RX_STATES bits
(Register 0x018, Bits[3:0]). RX_STATES is 0 indexed. Therefore,
setting the depth to 0 leaves RX_STATE_1 as the only state in
the loop.
After the multiplier/filter state machine is programmed and
enabled, operation is controlled by the RxRST and RxADV pins.
Alternatively, operation can be controlled through the SPI using
the RX_RST_SPI and RX_ADV_SPI bits (Register 0x02A,
Bits[1:0]). Note that using the SPI is slower than pulsing the
sequencer pins directly.
After the appropriate number of pulses is applied to MADV (4,
in this case), the state machine automatically returns to the
second state (ready mode).
SEQUENCER SLEEP CONTROL
To further simplify the control of the ADAR2004, it is possible
to link the sleep states of the two state machines so that one
sequencer going to sleep forces the other sequencer to sleep as
well. This link helps to limit the total number of required states
to achieve the desired type of operation. To use this feature, one
of the two sleep control bits must be set, but not both.
RxRST moves the pointer on the receiver state machine to State 0
regardless of the current position of the pointer and can be asserted
at any time. State 0 always refers to Mode 0 and cannot be set to
another mode. However, Mode 0 can be overwritten with any
receiver configuration. Mode 0 is defined in Register 0x040,
Register 0x041, and Register 0x042.
For example, when the ADAR2004 is configured for a frequency
sweep (as shown in Figure 43), if the RX_SLP_CTRL bit
(Register 0x018, Bit 6) is set, when the multiplier/filter
sequencer is reset, the receiver state machine is forced to sleep as
well. This means that the receiver state machine does not
require a state dedicated to sleep if it only needs to sleep when the
multiplier/filter sleeps. Furthermore, because the
multiplier/filter sleep state is controlling the sleep state of the
receiver, bringing the multiplier/filter out of sleep also brings the
receiver out of sleep. This routine is controlled with either the
SPI or one external line (MADV).
RxADV pulses advance the receiver state machine pointer one
state at a time until the defined sequencer depth is cycled through.
At that point, an additional RxADV pulse moves the pointer
back to State 1. State 1 applies the mode defined in the
RX_STATE_1 bits (Register 0x01A, Bits[7:4]).
FREQUENCY SWEEP ALL CHANNELS
Figure 43 shows a method of operation that can be used during
a 20 GHz to 40 GHz frequency sweep of all receive channels. As
described in Table 7, three multiplier/filter states are required
during a 20 GHz to 40 GHz sweep. In this example, the defined
state machine depth, MULT_STATES (Register 0x019, Bits[3:0]),
is 3 because there are four states inside the loop, and
MULT_STATES is 0 indexed.
Rev. 0 | Page 20 of 37
Data Sheet
ADAR2004
CHANNEL 1
READY
CHANNEL 1
20GHz TO 25GHz
SLEEP
MULT_STATE_0
RX_STATE_0
MULT_STATE_1
RX_STATE_1
MULT_STATE_2
RX_STATE_2
MULT: ALL SLEEP
BPF: N/A
MULT: MID READY
BPF: N/A
MULT: MID ACTIVE
BPF: HIGH
Rx:
ALL CHANNELS
Rx:
ALL CHANNELS
Rx:
ALL CHANNELS
MULTIPLIER RECEIVER
RESET RESET
MULTIPLIER RECEIVER
ADVANCE ADVANCE
MULTIPLIER RECEIVER
ADVANCE ADVANCE
CHANNEL 1
CHANNEL 1
25GHz TO 30GHz
30GHz TO 40GHz
MULT_STATE_3
RX_STATE_2
MULT_STATE_4
RX_STATE_2
MULT: HIGH ACTIVE
BPF: LOW
MULT: HIGH ACTIVE
BPF: HIGH
Rx:
ALL CHANNELS
Rx:
ALL CHANNELS
MULTIPLIER
ADVANCE
MULTIPLIER
ADVANCE
MULTIPLIER RECEIVER
ADVANCE ADVANCE
Figure 43. Multiplier State Machine Operating Example for a Frequency Sweep of All Receiver Channels Simultaneously From 20 GHz to 40 GHz (N/A Means Not Applicable)
SEQUENCER SLEEP HOLD
SEQUENCER CONTROL LATCH BYPASS
By default, when one of the sequencers is forced asleep using one
of the sleep control bits (MULT_SLP_CTRL or RX_SLP_CTRL),
the counter for the sequencer being controlled can still be
advanced. Because of this behavior, it is possible for a state
machine to be put to sleep in one condition and brought out of
sleep in another, depending on whether the sequencer advance
or reset signals were exercised while the sequencer was sleeping.
Typically, when a sequencer control line is pulsed, the upcoming
state is loaded on the rising edge of the control pulse and
latched to the various signal blocks on the falling edge of the
same pulse. The latching helps to line up all the internal control
signals so that the changes take place simultaneously.
It is possible to bypass the latching of the internal control signals by
setting the bypass bits (RX_CTL_LATCH_BYP and
MULT_CTL_LATCH_BYP) in the sequencer setup registers
(Register 0x018, Bit 4 and Register 0x019, Bit 4).
If this behavior is undesired, the sleep hold bits
(MULT_SLP_HOLD and RX_SLP_HOLD) can be asserted to
force the associated state machine counter to ignore any inputs
on the sequencer advance line. The counter also ignores advance
signals coming from the SPI.
Bypassing the latch results in the new state taking effect as soon
as possible after the rising edge. Because the internal control
signals are not aligned, it is possible that the overall switching
time between states increases when compared to using the latch.
Also, glitches are more likely to occur in the internal control
signals, resulting in undesired transients in the RF blocks.
Note that the counter always responds to a reset signal, even
when the sleep hold bit is high.
When sleep hold is used, take care when bringing the state
machines out of sleep mode to ensure that the desired modes
are reached. If the advance pins for both sequencers are pulsed
too closely together under this condition, it is possible for the
sequencer being controlled to not move into the expected state.
To prevent this issue, stagger the advance pulses so that the
rising edges are separated by a minimum of 3 ns with the pulse
of the controlled sequencer coming second. See Figure 44 for an
example of how to pulse the sequencers under this condition.
Note that this latch is the last check before any new data is sent
to the various individual blocks. Therefore, when using the
ADAR2004 in manual or SPI mode (sequencers disabled), the
latching must be bypassed. If the latching is not bypassed, the
blocks do not receive the new instructions unless the external
sequencer pins are pulsed. However, this issue is uncommon
because the sequencers are disabled in this mode of operation.
RX_SLP_HOLD REGISTER 0x018, BIT 5 = 1 MULT_SLP_HOLD REGISTER 0x019, BIT 5 = 0
RX_SLP_CTRL REGISTER 0x018, BIT 6 = 1 MULT_SLP_CTRL REGISTER 0x019, BIT 6 = 0
≥3ns
MADV
RxADV
Figure 44. Example of How to Pulse the Sequencer Advance Pins to Ensure
Advancement With Receiver State Machine Sleep Hold Enabled
Rev. 0 | Page 21 of 37
ADAR2004
Data Sheet
PARALLEL CHIP CONTROL
MULTICHIP FREQUENCY SWEEP
Up to 16 devices (a total of 64 channels) can be driven by a single
set of four state machine control lines, three common SPI lines,
Figure 46 shows an example of how the two state machines can
be used to complete a multichip frequency sweep from 10 GHz
to 16 GHz (that is, receive on all four channels on a single chip
while at a fixed frequency range, move to the next chip and receive
on all channels, moving through 16 chips in total, and then move
to the next frequency and repeat the process). This example
assumes that the state machine control lines are connected in
parallel for up to 16 devices (64 channels, see Figure 45).
CS
and a line for each chip. Using this method, the total number of
digital control lines is 7 + N, where N is the number of ADAR2004
ICs (see Figure 45 for a basic diagram). Parallel chip control can be
used to minimize the total number of digital control lines. The
SPI lines can be reduced to two common lines if 3-wire mode is
selected by setting the SDOACTIVE and SDOACTIVE_ bits
(Register 0x000, Bit 4 and Bit 3, respectively) low. If 3-wire SPI
mode is used, the total number of digital lines is 6 + N.
Initially, pulses on RxRST and MRST put both state machines
in State 0, which in this case, is a sleep mode.
ADAR2004
Next, pulses on MADV and RxADV advance both state machines
to their first active state (receiving on all channels of
ADAR2004 IC 1).
(1)
SPI
SEQUENCERS
COMMON
SEQUENCER
LINES
After ADAR2004 IC 1 receives the signal, an additional pulse
on RxADV activates all channels on ADAR2004 IC 2 while
putting the multiplier/filter of the first chip into a ready mode
and the receivers of that chip into a sleep mode to prevent
disrupting the multiplier/filter signal before the receiver turns
off. This sequence continues until all 16 ADAR2004 devices
receive at the first frequency or range.
ADAR2004
(2)
SPI CS
LINES
SPI
SEQUENCERS
At that point, a pulse is applied to both MADV and RxADV to
advance the multiplier/filter to the next frequency range of
interest and set the ADAR2004 IC 1 back into an active mode.
Another series of RxADV pulses follow until ADAR2004 IC 16
is receiving the new frequency range.
COMMON
SPI
LINES
Table 8 describes how the receiver state machine for each
ADAR2004 can be set up to work in sequence. Each device is
turned fully on for only one state, but these states are all offset
from each other. To run this sequence, where up to 16 devices are
swept with all state machines driven in parallel, 16 receive states
are used inside the loop, with the sleep state (State 0) used as a
reset condition.
ADAR2004
(16)
SPI
SEQUENCERS
If there were more tiles of 16 chips in the array that need to
receive after the tile described in Table 8, this tile can have a
reset pulse sent to put the sequencers into the initial sleep mode
to wait for their turn to receive again.
Figure 45. SPI and State Machine Digital Lines For Addressing and
Controlling Up to 16 ADAR2004 Devices
Rev. 0 | Page 22 of 37
Data Sheet
ADAR2004
IC 1
IC 1
10GHz TO 13GHz
13GHz TO 16GHz
SLEEP
MULT_STATE_0
RX _STATE_0
MULT_STATE_1
RX_STATE_1
MULT_STATE_2
RX_STATE_1
MULT: ALL SLEEP
BPF: N/A
MULT: LOW ACTIVE
BPF: LOW
MULT: LOW ACTIVE
BPF: HIGH
Rx:
ALL CHANNELS
Rx:
ALL CHANNELS
Rx:
ALL CHANNELS
ANY
MULTIPLIER RECEIVER
MULTIPLIER RECEIVER
ADVANCE ADVANCE
ADDITIONAL
MULTIPLIER
BANDS
RESET
RESET
RECEIVER
ADVANCE
RECEIVER
ADVANCE
MULT_STATE_1
MULT_STATE_2
RX_STATE_16
RX_STATE_16
IC 16
10GHz TO 13GHz
IC 16
13GHz TO 16GHz
MULT: LOW ACTIVE
BPF: LOW
MULT: LOW ACTIVE
BPF: HIGH
Rx:
ALL CHANNELS
Rx:
ALL CHANNELS
MULTIPLIER
ADVANCE
MULTIPLIER
ADVANCE
RECEIVER
ADVANCE
RECEIVER
ADVANCE
Figure 46. State Machine Loop Example For a 16-Chip Frequency Sweep (N/A Means Not Applicable)
Table 8. Receiver Sequencer Settings for Controlling 16 ADAR2004 Devices In Parallel1
ADAR2004 Chip Number
Rx State
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
0 (Reset)
1
2
3
4
5
6
7
SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP All sleep
All SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP Chip 1 receiving
SLP All SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP Chip 2 receiving
SLP SLP All SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP Chip 3 receiving
SLP SLP SLP All SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP Chip 4 receiving
SLP SLP SLP SLP All SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP Chip 5 receiving
SLP SLP SLP SLP SLP All SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP Chip 6 receiving
SLP SLP SLP SLP SLP SLP All SLP SLP SLP SLP SLP SLP SLP SLP SLP Chip 7 receiving
8
9
SLP SLP SLP SLP SLP SLP SLP All
SLP SLP SLP SLP SLP SLP SLP SLP All
SLP SLP SLP SLP SLP SLP SLP SLP Chip 8 receiving
SLP SLP SLP SLP SLP SLP SLP Chip 9 receiving
10
11
12
13
14
15
16
SLP SLP SLP SLP SLP SLP SLP SLP SLP All
SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP All
SLP SLP SLP SLP SLP SLP Chip 10 receiving
SLP SLP SLP SLP SLP Chip 11 receiving
SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP All
SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP All
SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP All
SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP All
SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP SLP All
SLP SLP SLP SLP Chip 12 receiving
SLP SLP SLP Chip 13 receiving
SLP SLP Chip 14 receiving
SLP Chip 15 receiving
Chip 16 receiving
1 SLP is the sleep state (State 0)
Rev. 0 | Page 23 of 37
ADAR2004
Data Sheet
BIAS POINTS AND VOLTAGES
Table 9. Default Bias Points
Register Address Register Name
Bit Field Name(s) Register Bit(s)
Default Value Description
0x011
BIAS_CURRENT_MULT1
0x55
Low and mid band multiplier
bias current
MULT_LOW_BIAS
MULT_MID_BIAS
[3:0]
[7:4]
0x5
0x5
Low band multiplier bias current
Mid band multiplier bias current
0x012
0x013
BIAS_CURRENT_MULT2
BIAS_CURRENT_LOAMP
0x07
High band multiplier bias
current
High band multiplier bias
current
MULT_HIGH_BIAS
[3:0]
0x7
0x78
0x08
0x07
LO buffer amplifier bias
current
LO buffer input stage bias
current
LO buffer output stage bias
current
LO_AMP1_BIAS
LO_AMP2_BIAS
[3:0]
[7:4]
0x014
0x015
BIAS_CURRENT_SPLT
0x7A
0xA
Active splitter bias current
First stage active splitter bias
current
Second stage active splitter
bias current
SPLT1_BIAS
SPLT2_BIAS
[3:0]
[7:4]
0x7
BIAS_CURRENT_LNAMIX
0x2A
0xA
0x2
LNA and mixer bias current
LNA bias current
Mixer bias current
LNA_BIAS
MIX_BIAS
[3:0]
[7:4]
0x016
0x017
BIAS_CURRENT_IFAMP
IFAMP_CM
0xC0
0xC
IF amplifier bias current
IF amplifier bias current
IFAMP_BIAS
IFAMP_CM
[7:4]
[3:0]
0x04
IF amplifier output
common-mode voltage
IF amplifier output common-
mode voltage
0x4
Rev. 0 | Page 24 of 37
Data Sheet
ADAR2004
REGISTER SUMMARY
Table 10. ADAR2004 Register Summary
Address Name
Bits Bit Name
Description
Soft Reset
LSB First
Address Ascension
SDO Active
Reset Access
0x000
INTERFACE_CONFIG_A
7
6
5
4
3
2
1
0
7
6
5
4
3
SOFTRESET
LSB_FIRST
ADDR_ASCN
SDOACTIVE
0x0
0x0
0x0
0x1
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x5
0x5
0x0
0x7
0x7
0x8
0x7
0xA
0x2
0xA
0xC
0x0
0x0
0x4
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
SDOACTIVE_
ADDR_ASCN_
LSB_FIRST_
SOFTRESET_
SINGLE_INSTRUCTION
CS_STALL
SDO Active
Address Ascension
LSB First
Soft Reset
Single Instruction
CS Stall
0x001
0x002
INTERFACE_CONFIG_B
MASTER_SLAVE_RB
SLOW_INTERFACE_CTRL
RESERVED
Master Slave Readback
Slow Interface Control
Reserved
[2:1] SOFT_RESET
RESERVED
[7:4] DEV_STATUS
Soft Reset
Reserved
Device Status
R/W
R
R/W
R/W
R/W
R
0
DEV_CONFIG
[3:2] CUST_OPERATING_MODE Custom Operating Modes
[1:0] NORM_OPERATING_MODE Normal Operating Modes
[7:0] CHIP_TYPE
0x003
0x004
0x005
0x00A
0x00B
0x00C
0x00D
0x00F
CHIP_TYPE
Chip Type
PRODUCT_ID_H
PRODUCT_ID_L
SCRATCH_PAD
SPI_REV
VENDOR_ID_H
VENDOR_ID_L
TRANSFER_REG
[7:0] PRODUCT_ID[15:8]
[7:0] PRODUCT_ID[7:0]
[7:0] SCRATCHPAD
[7:0] SPI_REV
[7:0] VENDOR_ID[15:8]
[7:0] VENDOR_ID[7:0]
[7:1] RESERVED
Product ID High
Product ID Low
Scratch Pad
SPI Revision
Vendor ID High
Vendor ID Low
Reserved
R
R
R/W
R
R
R
R
0
MASTER_SLAVE_XFER
[7:1] RESERVED
PWRON
Master Slave Transfer
Reserved
Chip Power-Up
Mid Band 4× Bias Current Setting
Low Band 4× Bias Current Setting
Reserved
High Band 4× Bias Current Setting
LO Amp Output Stage Bias Current Setting
LO Amp Input Stage Bias Current Setting
Second Active Splitter Stages Bias Current Setting
First Active Splitter Stage Bias Current Setting
Mixer Bias Current Setting
LNA Bias Current Setting
IF Output Amp Bias Current Setting
Reserved
R/W
R
0x010
0x011
0x012
0x013
0x014
0x015
0x016
0x017
0x018
PWRON
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
BIAS_CURRENT_MULT1
BIAS_CURRENT_MULT2
BIAS_CURRENT_LOAMP
BIAS_CURRENT_SPLT
BIAS_CURRENT_LNAMIX
BIAS_CURRENT_IFAMP
IFAMP_CM
[7:4] MULT_MID_BIAS
[3:0] MULT_LOW_BIAS
[7:4] RESERVED
[3:0] MULT_HIGH_BIAS
[7:4] LO_AMP2_BIAS
[3:0] LO_AMP1_BIAS
[7:4] SPLT2_BIAS
[3:0] SPLT1_BIAS
[7:4] MIX_BIAS
[3:0] LNA_BIAS
[7:4] IFAMP_BIAS
[3:0] RESERVED
[7:4] RESERVED
Reserved
[3:0] IFAMP_CM
IF Output Amp Common-Mode Voltage Setting
Enables Receiver Sequencer
Sets Receiver Sleep Mode Control
Holds the Receiver Sequencer State When
Multiplier Is in Sleep Mode
R/W
R/W
R/W
R/W
RX_SEQUENCER_SETUP
7
6
5
RX_SEQ_EN
RX_SLP_CTRL
RX_SLP_HOLD
4
RX_CTL_LATCH_BYP
Bypasses the Control Latch for Receiver Controls 0x1
Sets Number of Receiver Sequencer States 0x0
R/W
R/W
[3:0] RX_STATES
Rev. 0 | Page 25 of 37
ADAR2004
Data Sheet
Address Name
Bits Bit Name
MULT_SEQ_EN
Description
Enables Frequency Sequencer
Sets Multiplier Sleep Mode Control
Holds the Multiplier Sequencer State When
Receiver Is in Sleep Mode
Reset Access
0x019
MULT_SEQUENCER_SETUP 7
0x0
0x0
0x0
R/W
R/W
R/W
6
5
MULT_SLP_CTRL
MULT_SLP_HOLD
4
MULT_CTL_LATCH_BYP
Bypasses the Control Latch for Multiplier Controls 0x1
Sets Number of Multiplier/Filter Sequencer States 0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
[3:0] MULT_STATES
[7:4] RX_STATE_1
[3:0] RX_STATE_2
[7:4] RX_STATE_3
[3:0] RX_STATE_4
0x01A
0x01B
0x01C
0x01D
0x01E
0x01F
0x020
0x021
0x022
0x023
0x024
0x025
0x026
0x027
0x028
0x029
0x02A
RX_STATES_1_2
Mode Select for Receiver Sequencer State 1
Mode Select for Receiver Sequencer State 2
Mode Select for Receiver Sequencer State 3
Mode Select for Receiver Sequencer State 4
Mode Select for Receiver Sequencer State 5
Mode Select for Receiver Sequencer State 6
Mode Select for Receiver Sequencer State 7
Mode Select for Receiver Sequencer State 8
Mode Select for Receiver Sequencer State 9
Mode Select for Receiver Sequencer State 10
Mode Select for Receiver Sequencer State 11
Mode Select for Receiver Sequencer State 12
Mode Select for Receiver Sequencer State 13
Mode Select for Receiver Sequencer State 14
Mode Select for Receiver Sequencer State 15
Mode Select for Receiver Sequencer State 16
Mode Select for Multiplier Sequencer State 1
Mode Select for Multiplier Sequencer State 2
Mode Select for Multiplier Sequencer State 3
Mode Select for Multiplier Sequencer State 4
Mode Select for Multiplier Sequencer State 5
Mode Select for Multiplier Sequencer State 6
Mode Select for Multiplier Sequencer State 7
Mode Select for Multiplier Sequencer State 8
Mode Select for Multiplier Sequencer State 9
Mode Select for Multiplier Sequencer State 10
Mode Select for Multiplier Sequencer State 11
Mode Select for Multiplier Sequencer State 12
Mode Select for Multiplier Sequencer State 13
Mode Select for Multiplier Sequencer State 14
Mode Select for Multiplier Sequencer State 15
Mode Select for Multiplier Sequencer State 16
Reserved
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RX_STATES_3_4
RX_STATES_5_6
[7:4] RX_STATE_5
[3:0] RX_STATE_6
[7:4] RX_STATE_7
[3:0] RX_STATE_8
RX_STATES_7_8
RX_STATES_9_10
RX_STATES_11_12
RX_STATES_13_14
RX_STATES_15_16
MULT_STATES_1_2
MULT_STATES_3_4
MULT_STATES_5_6
MULT_STATES_7_8
MULT_STATES_9_10
MULT_STATES_11_12
MULT_STATES_13_14
MULT_STATES_15_16
SEQUENCER_CTRL_SPI
[7:4] RX_STATE_9
[3:0] RX_STATE_10
[7:4] RX_STATE_11
[3:0] RX_STATE_12
[7:4] RX_STATE_13
[3:0] RX_STATE_14
[7:4] RX_STATE_15
[3:0] RX_STATE_16
[7:4] MULT_STATE_1
[3:0] MULT_STATE_2
[7:4] MULT_STATE_3
[3:0] MULT_STATE_4
[7:4] MULT_STATE_5
[3:0] MULT_STATE_6
[7:4] MULT_STATE_7
[3:0] MULT_STATE_8
[7:4] MULT_STATE_9
[3:0] MULT_STATE_10
[7:4] MULT_STATE_11
[3:0] MULT_STATE_12
[7:4] MULT_STATE_13
[3:0] MULT_STATE_14
[7:4] MULT_STATE_15
[3:0] MULT_STATE_16
[7:4] RESERVED
3
2
1
0
7
6
5
4
3
2
1
0
MULT_RST_SPI
MULT_ADV_SPI
RX_RST_SPI
RX_ADV_SPI
LNA_EN_SPI
MIX_EN_SPI
IFAMP_EN_SPI
RESERVED
CH1_EN_SPI
CH2_EN_SPI
CH3_EN_SPI
CH4_EN_SPI
Resets Frequency Sequencer
Advances Multiplier Sequencer State
Resets Receiver Sequencer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Advances Receiver Sequencer State
SPI Mode LNA Enable
0x02B
RX_EN_SPI
SPI Mode Mixer Enable
SPI Mode IF Amp Enable
Reserved
SPI Mode Channel 1 Enable
SPI Mode Channel 2 Enable
SPI Mode Channel 3 Enable
SPI Mode Channel 4 Enable
Rev. 0 | Page 26 of 37
Data Sheet
ADAR2004
Address Name
Bits Bit Name
RESERVED
[6:4] CH1_GAIN_SPI
RESERVED
[2:0] CH2_GAIN_SPI
RESERVED
[6:4] CH3_GAIN_SPI
RESERVED
Description
Reserved
SPI Mode Channel 1 Gain Setting
Reserved
SPI Mode Channel 2 Gain Setting
Reserved
Reset Access
0x02C
0x02D
0x02E
RX_GAIN12_SPI
7
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R
R/W
R
R/W
R
R/W
R
3
RX_GAIN34_SPI
SPLT_EN_SPI
7
SPI Mode Channel 3 Gain Setting
Reserved
3
[2:0] CH4_GAIN_SPI
[7:3] RESERVED
SPI Mode Channel 4 Gain Setting
Reserved
SPI Mode Active Splitter 1 Enable
SPI Mode Channel 1 to Channel 2 Active Splitter 0x0
Enable
R/W
R
R/W
R/W
2
1
SPLT1_EN_SPI
SPLT12_EN_SPI
0
SPLT34_EN_SPI
SPI Mode Channel 3 to Channel 4 Active Splitter 0x0
Enable
R/W
0x02F
MULT_SPI
7
6
5
4
3
2
1
0
7
6
5
4
BPF_SPI
SPI Mode BPF Select
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
LOAMP_EN_SPI
MULT_LOW_RDY_SPI
MULT_LOW_ACT_SPI
MULT_MID_RDY_SPI
MULT_MID_ACT_SPI
MULT_HIGH_RDY_SPI
MULT_HIGH_ACT_SPI
ADC_CLKFREQ_SEL
ADC_EN
SPI Mode LO Amplifier Enable
SPI Mode Low Band Ready Enable
SPI Mode Low Band Active Enable
SPI Mode Mid Band Ready Enable
SPI Mode Mid Band Active Enable
SPI Mode High Band Ready Enable
SPI Mode High Band Active Enable
ADC Clock Frequency Selection
Turns on Comparator and Resets State Machine 0x0
Turns on Clock Oscillator
Pulse Triggers Conversion Cycle
Reserved
0x030
ADC_CTRL
CLK_EN
ST_CONV
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
[3:1] RESERVED
ADC_EOC
0
ADC End of Conversion Signal
ADC Output Word
Read Back Current Receiver Sequencer Count
Read Back Current Receiver Mode
Read Back Current Multiplier/Filter Sequencer
Count
0x031
0x032
ADC_OUTPUT
RX_STATUS
[7:0] ADC
R
R
R
R
[7:4] RX_CURR_STATE
[3:0] RX_CURR_MODE
[7:4] MULT_CURR_STATE
0x033
MULT_STATUS
[3:0] MULT_CURR_MODE
[7:0] REV_ID
Read Back Current Mode
Chip Revision ID
Reserved
Receiver Mode 0 Active Splitter 1 Enable
Receiver Mode 0 Channel 1 to Channel 2 Active
Splitter Enable
0x0
0x0
0x0
0x0
0x0
R
R
R
R/W
R/W
0x034
0x040
REV_ID
RX_EN_MODE_0
7
6
5
RESERVED
SPLT1_EN_MD0
SPLT12_EN_MD0
4
SPLT34_EN_MD0
Receiver Mode 0 Channel 3 to Channel 4 Active
Splitter Enable
0x0
R/W
3
2
1
0
7
CH1_EN_MD0
CH2_EN_MD0
CH3_EN_MD0
CH4_EN_MD0
RESERVED
Receiver Mode 0 Channel 1 Enable
Receiver Mode 0 Channel 2 Enable
Receiver Mode 0 Channel 3 Enable
Receiver Mode 0 Channel 4 Enable
Reserved
Receiver Mode 0 Channel 1 Gain
Reserved
Receiver Mode 0 Channel 2 Gain
Reserved
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
0x041
0x042
RX_GAIN12_MODE_0
RX_GAIN34_MODE_0
[6:4] CH1_GAIN_MD0
RESERVED
[2:0] CH2_GAIN_MD0
RESERVED
[6:4] CH3_GAIN_MD0
RESERVED
[2:0] CH4_GAIN_MD0
3
7
Receiver Mode 0 Channel 3 Gain
Reserved
Receiver Mode 0 Channel 4 Gain
R/W
R
R/W
3
Rev. 0 | Page 27 of 37
ADAR2004
Data Sheet
Address Name
Bits Bit Name
Description
Reset Access
0x043
RX_EN_MODE_1
7
6
5
RESERVED
SPLT1_EN_MD1
SPLT12_EN_MD1
Reserved
0x0
0x1
0x1
R
R/W
R/W
Receiver Mode 1 Active Splitter 1 Enable
Receiver Mode 1 Channel 1 to Channel 2 Active
Splitter Enable
4
SPLT34_EN_MD1
Receiver Mode 1 Channel 3 to Channel 4 Active
Splitter Enable
0x0
R/W
3
2
1
0
7
CH1_EN_MD1
CH2_EN_MD1
CH3_EN_MD1
CH4_EN_MD1
RESERVED
Receiver Mode 1 Channel 1 Enable
Receiver Mode 1 Channel 2 Enable
Receiver Mode 1 Channel 3 Enable
Receiver Mode 1 Channel 4 Enable
Reserved
Receiver Mode 1 Channel 1 Gain
Reserved
Receiver Mode 1 Channel 2 Gain
Reserved
Receiver Mode 1 Channel 3 Gain
Reserved
Receiver Mode 1 Channel 4 Gain
Reserved
Receiver Mode 2 Active Splitter 1 Enable
Receiver Mode 2 Channel 1 to Channel 2 Active
Splitter Enable
0x1
0x0
0x0
0x0
0x0
0x7
0x0
0x7
0x0
0x7
0x0
0x7
0x0
0x1
0x1
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R/W
0x044
0x045
0x046
RX_GAIN12_MODE_1
RX_GAIN34_MODE_1
RX_EN_MODE_2
[6:4] CH1_GAIN_MD1
RESERVED
[2:0] CH2_GAIN_MD1
RESERVED
[6:4] CH3_GAIN_MD1
RESERVED
[2:0] CH4_GAIN_MD1
3
7
3
7
6
5
RESERVED
SPLT1_EN_MD2
SPLT12_EN_MD2
4
SPLT34_EN_MD2
Receiver Mode 2 Channel 3 to Channel 4 Active 0x0
Splitter Enable
R/W
3
2
1
0
7
CH1_EN_MD2
CH2_EN_MD2
CH3_EN_MD2
CH4_EN_MD2
RESERVED
Receiver Mode 2 Channel 1 Enable
Receiver Mode 2 Channel 2 Enable
Receiver Mode 2 Channel 3 Enable
Receiver Mode 2 Channel 4 Enable
Reserved
Receiver Mode 2 Channel 1 Gain
Reserved
Receiver Mode 2 Channel 2 Gain
Reserved
Receiver Mode 2 Channel 3 Gain
Reserved
Receiver Mode 2 Channel 4 Gain
Reserved
Receiver Mode 3 Active Splitter 1 Enable
Receiver Mode 3 Channel 1 to Channel 2 Active
Splitter Enable
0x0
0x1
0x0
0x0
0x0
0x7
0x0
0x7
0x0
0x7
0x0
0x7
0x0
0x1
0x0
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R/W
0x047
0x048
0x049
RX_GAIN12_MODE_2
RX_GAIN34_MODE_2
RX_EN_MODE_3
[6:4] CH1_GAIN_MD2
RESERVED
[2:0] CH2_GAIN_MD2
RESERVED
[6:4] CH3_GAIN_MD2
RESERVED
[2:0] CH4_GAIN_MD2
3
7
3
7
6
5
RESERVED
SPLT1_EN_MD3
SPLT12_EN_MD3
4
SPLT34_EN_MD3
Receiver Mode 3 Channel 3 to Channel 4 Active
Splitter Enable
0x1
R/W
3
2
1
0
7
CH1_EN_MD3
CH2_EN_MD3
CH3_EN_MD3
CH4_EN_MD3
RESERVED
Receiver Mode 3 Channel 1 Enable
Receiver Mode 3 Channel 2 Enable
Receiver Mode 3 Channel 3 Enable
Receiver Mode 3 Channel 4 Enable
Reserved
0x0
0x0
0x1
0x0
0x0
0x7
0x0
0x7
R/W
R/W
R/W
R/W
R
0x04A
RX_GAIN12_MODE_3
[6:4] CH1_GAIN_MD3
RESERVED
[2:0] CH2_GAIN_MD3
Receiver Mode 3 Channel 1 Gain
Reserved
Receiver Mode 3 Channel 2 Gain
R/W
R
R/W
3
Rev. 0 | Page 28 of 37
Data Sheet
ADAR2004
Address Name
Bits Bit Name
RESERVED
[6:4] CH3_GAIN_MD3
RESERVED
[2:0] CH4_GAIN_MD3
Description
Reserved
Receiver Mode 3 Channel 3 Gain
Reserved
Receiver Mode 3 Channel 4 Gain
Reserved
Receiver Mode 4 Active Splitter 1 Enable
Receiver Mode 4 Channel 1 to Channel 2 Active
Splitter Enable
Reset Access
0x04B
RX_GAIN34_MODE_3
7
0x0
0x7
0x0
0x7
0x0
0x1
0x0
R
R/W
R
R/W
R
R/W
R/W
3
0x04C
RX_EN_MODE_4
7
6
5
RESERVED
SPLT1_EN_MD4
SPLT12_EN_MD4
4
SPLT34_EN_MD4
Receiver Mode 4 Channel 3 to Channel 4 Active
Splitter Enable
0x1
R/W
3
2
1
0
7
CH1_EN_MD4
CH2_EN_MD4
CH3_EN_MD4
CH4_EN_MD4
RESERVED
Receiver Mode 4 Channel 1 Enable
Receiver Mode 4 Channel 2 Enable
Receiver Mode 4 Channel 3 Enable
Receiver Mode 4 Channel 4 Enable
Reserved
Receiver Mode 4 Channel 1 Gain
Reserved
Receiver Mode 4 Channel 2 Gain
Reserved
Receiver Mode 4 Channel 3 Gain
Reserved
Receiver Mode 4 Channel 4 Gain
Reserved
Receiver Mode 5 Active Splitter 1 Enable
Receiver Mode 5 Channel 1 to Channel 2 Active
Splitter Enable
0x0
0x0
0x0
0x1
0x0
0x7
0x0
0x7
0x0
0x7
0x0
0x7
0x0
0x1
0x1
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R/W
0x04D
0x04E
0x04F
RX_GAIN12_MODE_4
RX_GAIN34_MODE_4
RX_EN_MODE_5
[6:4] CH1_GAIN_MD4
RESERVED
[2:0] CH2_GAIN_MD4
RESERVED
[6:4] CH3_GAIN_MD4
RESERVED
[2:0] CH4_GAIN_MD4
3
7
3
7
6
5
RESERVED
SPLT1_EN_MD5
SPLT12_EN_MD5
4
SPLT34_EN_MD5
Receiver Mode 5 Channel 3 to Channel 4 Active
Splitter Enable
0x1
R/W
3
2
1
0
7
CH1_EN_MD5
CH2_EN_MD5
CH3_EN_MD5
CH4_EN_MD5
RESERVED
Receiver Mode 5 Channel 1 Enable
Receiver Mode 5 Channel 2 Enable
Receiver Mode 5 Channel 3 Enable
Receiver Mode 5 Channel 4 Enable
Reserved
Receiver Mode 5 Channel 1 Gain
Reserved
Receiver Mode 5 Channel 2 Gain
Reserved
Receiver Mode 5 Channel 3 Gain
Reserved
Receiver Mode 5 Channel 4 Gain
Reserved
0x1
0x1
0x1
0x1
0x0
0x7
0x0
0x7
0x0
0x7
0x0
0x7
0x0
0x1
0x1
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
0x050
0x051
0x052
RX_GAIN12_MODE_5
RX_GAIN34_MODE_5
RX_EN_MODE_6
[6:4] CH1_GAIN_MD5
RESERVED
[2:0] CH2_GAIN_MD5
RESERVED
[6:4] CH3_GAIN_MD5
RESERVED
[2:0] CH4_GAIN_MD5
3
7
3
7
6
5
RESERVED
SPLT1_EN_MD6
SPLT12_EN_MD6
Receiver Mode 6 Active Splitter 1 Enable
Receiver Mode 6 Channel 1 to Channel 2 Active
Splitter Enable
R/W
R/W
4
SPLT34_EN_MD6
Receiver Mode 6 Channel 3 to Channel 4 Active
Splitter Enable
0x0
R/W
3
2
1
0
CH1_EN_MD6
CH2_EN_MD6
CH3_EN_MD6
CH4_EN_MD6
Receiver Mode 6 Channel 1 Enable
Receiver Mode 6 Channel 2 Enable
Receiver Mode 6 Channel 3 Enable
Receiver Mode 6 Channel 4 Enable
0x1
0x0
0x0
0x0
R/W
R/W
R/W
R/W
Rev. 0 | Page 29 of 37
ADAR2004
Data Sheet
Address Name
Bits Bit Name
RESERVED
[6:4] CH1_GAIN_MD6
RESERVED
[2:0] CH2_GAIN_MD6
RESERVED
[6:4] CH3_GAIN_MD6
RESERVED
[2:0] CH4_GAIN_MD6
Description
Reserved
Receiver Mode 6 Channel 1 Gain
Reserved
Receiver Mode 6 Channel 2 Gain
Reserved
Reset Access
0x053
0x054
0x055
RX_GAIN12_MODE_6
7
0x0
0x4
0x0
0x4
0x0
0x4
0x0
0x4
0x0
0x1
0x1
R
R/W
R
R/W
R
R/W
R
3
RX_GAIN34_MODE_6
RX_EN_MODE_7
7
Receiver Mode 6 Channel 3 Gain
Reserved
3
Receiver Mode 6 Channel 4 Gain
Reserved
Receiver Mode 7 Active Splitter 1 Enable
Receiver Mode 7 Channel 1 to Channel 2 Active
Splitter Enable
R/W
R
R/W
R/W
7
6
5
RESERVED
SPLT1_EN_MD7
SPLT12_EN_MD7
4
SPLT34_EN_MD7
Receiver Mode 7 Channel 3 to Channel 4 Active
Splitter Enable
0x0
R/W
3
2
1
0
7
CH1_EN_MD7
CH2_EN_MD7
CH3_EN_MD7
CH4_EN_MD7
RESERVED
Receiver Mode 7 Channel 1 Enable
Receiver Mode 7 Channel 2 Enable
Receiver Mode 7 Channel 3 Enable
Receiver Mode 7 Channel 4 Enable
Reserved
Receiver Mode 7 Channel 1 Gain
Reserved
Receiver Mode 7 Channel 2 Gain
Reserved
Receiver Mode 7 Channel 3 Gain
Reserved
Receiver Mode 7 Channel 4 Gain
Reserved
0x0
0x1
0x0
0x0
0x0
0x4
0x0
0x4
0x0
0x4
0x0
0x4
0x0
0x1
0x0
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
0x056
0x057
0x058
RX_GAIN12_MODE_7
RX_GAIN34_MODE_7
RX_EN_MODE_8
[6:4] CH1_GAIN_MD7
RESERVED
[2:0] CH2_GAIN_MD7
RESERVED
[6:4] CH3_GAIN_MD7
RESERVED
[2:0] CH4_GAIN_MD7
3
7
3
7
6
5
RESERVED
SPLT1_EN_MD8
SPLT12_EN_MD8
Receiver Mode 8 Active Splitter 1 Enable
Receiver Mode 8 Channel 1 to Channel 2 Active
Splitter Enable
R/W
R/W
4
SPLT34_EN_MD8
Receiver Mode 8 Channel 3 to Channel 4 Active
Splitter Enable
0x1
R/W
3
2
1
0
7
CH1_EN_MD8
CH2_EN_MD8
CH3_EN_MD8
CH4_EN_MD8
RESERVED
Receiver Mode 8 Channel 1 Enable
Receiver Mode 8 Channel 2 Enable
Receiver Mode 8 Channel 3 Enable
Receiver Mode 8 Channel 4 Enable
Reserved
Receiver Mode 8 Channel 1 Gain
Reserved
Receiver Mode 8 Channel 2 Gain
Reserved
0x0
0x0
0x1
0x0
0x0
0x4
0x0
0x4
0x0
0x4
0x0
0x4
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
0x059
0x05A
RX_GAIN12_MODE_8
RX_GAIN34_MODE_8
[6:4] CH1_GAIN_MD8
RESERVED
[2:0] CH2_GAIN_MD8
RESERVED
[6:4] CH3_GAIN_MD8
RESERVED
[2:0] CH4_GAIN_MD8
3
7
Receiver Mode 8 Channel 3 Gain
Reserved
Receiver Mode 8 Channel 4 Gain
R/W
R
R/W
3
Rev. 0 | Page 30 of 37
Data Sheet
ADAR2004
Address Name
Bits Bit Name
Description
Reset Access
0x05B
RX_EN_MODE_9
7
6
5
RESERVED
SPLT1_EN_MD9
SPLT12_EN_MD9
Reserved
0x0
0x1
0x0
R
R/W
R/W
Receiver Mode 9 Active Splitter 1 Enable
Receiver Mode 9 Channel 1 to Channel 2 Active
Splitter Enable
4
SPLT34_EN_MD9
Receiver Mode 9 Channel 3 to Channel 4 Active
Splitter Enable
0x1
R/W
3
2
1
0
7
CH1_EN_MD9
CH2_EN_MD9
CH3_EN_MD9
CH4_EN_MD9
RESERVED
Receiver Mode 9 Channel 1 Enable
Receiver Mode 9 Channel 2 Enable
Receiver Mode 9 Channel 3 Enable
Receiver Mode 9 Channel 4 Enable
Reserved
Receiver Mode 9 Channel 1 Gain
Reserved
Receiver Mode 9 Channel 2 Gain
Reserved
Receiver Mode 9 Channel 3 Gain
Reserved
Receiver Mode 9 Channel 4 Gain
Reserved
Receiver Mode 10 Active Splitter 1 Enable
Receiver Mode 10 Channel 1 to Channel 2 Active 0x1
Splitter Enable
0x0
0x0
0x0
0x1
0x0
0x4
0x0
0x4
0x0
0x4
0x0
0x4
0x0
0x1
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R/W
0x05C
0x05D
0x05E
RX_GAIN12_MODE_9
RX_GAIN34_MODE_9
RX_EN_MODE_10
[6:4] CH1_GAIN_MD9
RESERVED
[2:0] CH2_GAIN_MD9
RESERVED
[6:4] CH3_GAIN_MD9
RESERVED
[2:0] CH4_GAIN_MD9
3
7
3
7
6
5
RESERVED
SPLT1_EN_MD10
SPLT12_EN_MD10
4
SPLT34_EN_MD10
Receiver Mode 10 Channel 3 to Channel 4 Active 0x1
Splitter Enable
R/W
3
2
1
0
7
CH1_EN_MD10
CH2_EN_MD10
CH3_EN_MD10
CH4_EN_MD10
RESERVED
Receiver Mode 10 Channel 1 Enable
Receiver Mode 10 Channel 2 Enable
Receiver Mode 10 Channel 3 Enable
Receiver Mode 10 Channel 4 Enable
Reserved
Receiver Mode 10 Channel 1 Gain
Reserved
Receiver Mode 10 Channel 2 Gain
Reserved
Receiver Mode 10 Channel 3 Gain
Reserved
Receiver Mode 10 Channel 4 Gain
Reserved
Receiver Mode 11 Active Splitter 1 Enable
Receiver Mode 11 Channel 1 to Channel 2 Active 0x1
Splitter Enable
0x1
0x1
0x1
0x1
0x0
0x4
0x0
0x4
0x0
0x4
0x0
0x4
0x0
0x1
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R/W
0x05F
0x060
0x061
RX_GAIN12_MODE_10
RX_GAIN34_MODE_10
RX_EN_MODE_11
[6:4] CH1_GAIN_MD10
RESERVED
[2:0] CH2_GAIN_MD10
RESERVED
[6:4] CH3_GAIN_MD10
RESERVED
[2:0] CH4_GAIN_MD10
3
7
3
7
6
5
RESERVED
SPLT1_EN_MD11
SPLT12_EN_MD11
4
SPLT34_EN_MD11
Receiver Mode 11 Channel 3 to Channel 4 Active 0x0
Splitter Enable
R/W
3
2
1
0
7
CH1_EN_MD11
CH2_EN_MD11
CH3_EN_MD11
CH4_EN_MD11
RESERVED
Receiver Mode 11 Channel 1 Enable
Receiver Mode 11 Channel 2 Enable
Receiver Mode 11 Channel 3 Enable
Receiver Mode 11 Channel 4 Enable
Reserved
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R
0x062
RX_GAIN12_MODE_11
[6:4] CH1_GAIN_MD11
RESERVED
[2:0] CH2_GAIN_MD11
Receiver Mode 11 Channel 1 Gain
Reserved
Receiver Mode 11 Channel 2 Gain
R/W
R
R/W
3
Rev. 0 | Page 31 of 37
ADAR2004
Data Sheet
Address Name
Bits Bit Name
RESERVED
[6:4] CH3_GAIN_MD11
RESERVED
[2:0] CH4_GAIN_MD11
Description
Reserved
Receiver Mode 11 Channel 3 Gain
Reserved
Receiver Mode 11 Channel 4 Gain
Reserved
Receiver Mode 12 Active Splitter 1 Enable
Receiver Mode 12 Channel 1 to Channel 2 Active 0x1
Splitter Enable
Reset Access
0x063
RX_GAIN34_MODE_11
7
0x0
0x0
0x0
0x0
0x0
0x1
R
R/W
R
R/W
R
R/W
R/W
3
0x064
RX_EN_MODE_12
7
6
5
RESERVED
SPLT1_EN_MD12
SPLT12_EN_MD12
4
SPLT34_EN_MD12
Receiver Mode 12 Channel 3 to Channel 4 Active 0x0
Splitter Enable
R/W
3
2
1
0
7
CH1_EN_MD12
CH2_EN_MD12
CH3_EN_MD12
CH4_EN_MD12
RESERVED
Receiver Mode 12 Channel 1 Enable
Receiver Mode 12 Channel 2 Enable
Receiver Mode 12 Channel 3 Enable
Receiver Mode 12 Channel 4 Enable
Reserved
Receiver Mode 12 Channel 1 Gain
Reserved
Receiver Mode 12 Channel 2 Gain
Reserved
Receiver Mode 12 Channel 3 Gain
Reserved
Receiver Mode 12 Channel 4 Gain
Reserved
Receiver Mode 13 Active Splitter 1 Enable
Receiver Mode 13 Channel 1 to Channel 2 Active 0x0
Splitter Enable
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R/W
0x065
0x066
0x067
RX_GAIN12_MODE_12
RX_GAIN34_MODE_12
RX_EN_MODE_13
[6:4] CH1_GAIN_MD12
RESERVED
[2:0] CH2_GAIN_MD12
RESERVED
[6:4] CH3_GAIN_MD12
RESERVED
[2:0] CH4_GAIN_MD12
3
7
3
7
6
5
RESERVED
SPLT1_EN_MD13
SPLT12_EN_MD13
4
SPLT34_EN_MD13
Receiver Mode 13 Channel 3 to Channel 4 Active 0x1
Splitter Enable
R/W
3
2
1
0
7
CH1_EN_MD13
CH2_EN_MD13
CH3_EN_MD13
CH4_EN_MD13
RESERVED
Receiver Mode 13 Channel 1 Enable
Receiver Mode 13 Channel 2 Enable
Receiver Mode 13 Channel 3 Enable
Receiver Mode 13 Channel 4 Enable
Reserved
Receiver Mode 13 Channel 1 Gain
Reserved
Receiver Mode 13 Channel 2 Gain
Reserved
Receiver Mode 13 Channel 3 Gain
Reserved
Receiver Mode 13 Channel 4 Gain
Reserved
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
0x068
0x069
0x06A
RX_GAIN12_MODE_13
RX_GAIN34_MODE_13
RX_EN_MODE_14
[6:4] CH1_GAIN_MD13
RESERVED
[2:0] CH2_GAIN_MD13
RESERVED
[6:4] CH3_GAIN_MD13
RESERVED
[2:0] CH4_GAIN_MD13
3
7
3
7
6
5
RESERVED
SPLT1_EN_MD14
SPLT12_EN_MD14
Receiver Mode 14 Active Splitter 1 Enable
Receiver Mode 14 Channel 1 to Channel 2 Active 0x0
Splitter Enable
R/W
R/W
4
SPLT34_EN_MD14
Receiver Mode 14 Channel 3 to Channel 4 Active 0x1
Splitter Enable
R/W
3
2
1
0
CH1_EN_MD14
CH2_EN_MD14
CH3_EN_MD14
CH4_EN_MD14
Receiver Mode 14 Channel 1 Enable
Receiver Mode 14 Channel 2 Enable
Receiver Mode 14 Channel 3 Enable
Receiver Mode 14 Channel 4 Enable
0x0
0x0
0x0
0x1
R/W
R/W
R/W
R/W
Rev. 0 | Page 32 of 37
Data Sheet
ADAR2004
Address Name
Bits Bit Name
RESERVED
[6:4] CH1_GAIN_MD14
RESERVED
[2:0] CH2_GAIN_MD14
RESERVED
[6:4] CH3_GAIN_MD14
RESERVED
[2:0] CH4_GAIN_MD14
Description
Reserved
Receiver Mode 14 Channel 1 Gain
Reserved
Receiver Mode 14 Channel 2 Gain
Reserved
Reset Access
0x06B
0x06C
0x06D
RX_GAIN12_MODE_14
7
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
R
R/W
R
R/W
R
R/W
R
3
RX_GAIN34_MODE_14
RX_EN_MODE_15
7
Receiver Mode 14 Channel 3 Gain
Reserved
3
Receiver Mode 14 Channel 4 Gain
Reserved
Receiver Mode 15 Active Splitter 1 Enable
Receiver Mode 15 Channel 1 to Channel 2 Active 0x1
Splitter Enable
R/W
R
R/W
R/W
7
6
5
RESERVED
SPLT1_EN_MD15
SPLT12_EN_MD15
4
SPLT34_EN_MD15
Receiver Mode 15 Channel 3 to Channel 4 Active 0x1
Splitter Enable
R/W
3
2
1
0
7
CH1_EN_MD15
CH2_EN_MD15
CH3_EN_MD15
CH4_EN_MD15
RESERVED
Receiver Mode 15 Channel 1 Enable
Receiver Mode 15 Channel 2 Enable
Receiver Mode 15 Channel 3 Enable
Receiver Mode 15 Channel 4 Enable
Reserved
Receiver Mode 15 Channel 1 Gain
Reserved
Receiver Mode 15 Channel 2 Gain
Reserved
Receiver Mode 15 Channel 3 Gain
Reserved
Receiver Mode 15 Channel 4 Gain
Multiplier Mode 0 BPF Select
0x1
0x1
0x1
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x1
0x0
0x1
0x0
0x1
0x0
0x1
0x1
0x1
0x1
0x1
0x0
0x1
0x0
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
0x06E
0x06F
0x070
RX_GAIN12_MODE_15
RX_GAIN34_MODE_15
MULT_EN_MODE_0
[6:4] CH1_GAIN_MD15
RESERVED
[2:0] CH2_GAIN_MD15
RESERVED
[6:4] CH3_GAIN_MD15
RESERVED
[2:0] CH4_GAIN_MD15
3
7
R/W
R
3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
BPF_MD0
LOAMP_EN_MD0
Multiplier Mode 0 LO Amplifier Enable
Multiplier Mode 0 Low Band Ready Enable
Multiplier Mode 0 Low Band Active Enable
Multiplier Mode 0 Mid Band Ready Enable
Multiplier Mode 0 Mid Band Active Enable
Multiplier Mode 0 High Band Ready Enable
Multiplier Mode 0 High Band Active Enable
Multiplier Mode 1 BPF Select
Multiplier Mode 1 LO Amplifier Enable
Multiplier Mode 1 Low Band Ready Enable
Multiplier Mode 1 Low Band Active Enable
Multiplier Mode 1 Mid Band Ready Enable
Multiplier Mode 1 Mid Band Active Enable
Multiplier Mode 1 High Band Ready Enable
Multiplier Mode 1 High Band Active Enable
Multiplier Mode 2 BPF Select
Multiplier Mode 2 LO Amplifier Enable
Multiplier Mode 2 Low Band Ready Enable
Multiplier Mode 2 Low Band Active Enable
Multiplier Mode 2 Mid Band Ready Enable
Multiplier Mode 2 Mid Band Active Enable
Multiplier Mode 2 High Band Ready Enable
Multiplier Mode 2 High Band Active Enable
MULT_LOW_RDY_MD0
MULT_LOW_ACT_MD0
MULT_MID_RDY_MD0
MULT_MID_ACT_MD0
MULT_HIGH_RDY_MD0
MULT_HIGH_ACT_MD0
BPF_MD1
0x071
MULT_EN_MODE_1
LOAMP_EN_MD1
MULT_LOW_RDY_MD1
MULT_LOW_ACT_MD1
MULT_MID_RDY_MD1
MULT_MID_ACT_MD1
MULT_HIGH_RDY_MD1
MULT_HIGH_ACT_MD1
BPF_MD2
0x072
MULT_EN_MODE_2
LOAMP_EN_MD2
MULT_LOW_RDY_MD2
MULT_LOW_ACT_MD2
MULT_MID_RDY_MD2
MULT_MID_ACT_MD2
MULT_HIGH_RDY_MD2
MULT_HIGH_ACT_MD2
Rev. 0 | Page 33 of 37
ADAR2004
Data Sheet
Address Name
Bits Bit Name
Description
Reset Access
0x073
0x074
0x075
0x076
0x077
0x078
MULT_EN_MODE_3
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
BPF_MD3
LOAMP_EN_MD3
Multiplier Mode 3 BPF Select
0x0
0x1
0x1
0x1
0x1
0x0
0x1
0x0
0x1
0x1
0x1
0x0
0x1
0x1
0x1
0x0
0x0
0x1
0x1
0x0
0x1
0x1
0x1
0x0
0x1
0x1
0x1
0x0
0x1
0x0
0x1
0x1
0x0
0x1
0x1
0x0
0x1
0x0
0x1
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Multiplier Mode 3 LO Amplifier Enable
Multiplier Mode 3 Low Band Ready Enable
Multiplier Mode 3 Low Band Active Enable
Multiplier Mode 3 Mid Band Ready Enable
Multiplier Mode 3 Mid Band Active Enable
Multiplier Mode 3 High Band Ready Enable
Multiplier Mode 3 High Band Active Enable
Multiplier Mode 4 BPF Select
Multiplier Mode 4 LO Amplifier Enable
Multiplier Mode 4 Low Band Ready Enable
Multiplier Mode 4 Low Band Active Enable
Multiplier Mode 4 Mid Band Ready Enable
Multiplier Mode 4 Mid Band Active Enable
Multiplier Mode 4 High Band Ready Enable
Multiplier Mode 4 High Band Active Enable
Multiplier Mode 5 BPF Select
Multiplier Mode 5 LO Amplifier Enable
Multiplier Mode 5 Low Band Ready Enable
Multiplier Mode 5 Low Band Active Enable
Multiplier Mode 5 Mid Band Ready Enable
Multiplier Mode 5 Mid Band Active Enable
Multiplier Mode 5 High Band Ready Enable
Multiplier Mode 5 High Band Active Enable
Multiplier Mode 6 BPF Select
Multiplier Mode 6 LO Amplifier Enable
Multiplier Mode 6 Low Band Ready Enable
Multiplier Mode 6 Low Band Active Enable
Multiplier Mode 6 Mid Band Ready Enable
Multiplier Mode 6 Mid Band Active Enable
Multiplier Mode 6 High Band Ready Enable
Multiplier Mode 6 High Band Active Enable
Multiplier Mode 7 BPF Select
MULT_LOW_RDY_MD3
MULT_LOW_ACT_MD3
MULT_MID_RDY_MD3
MULT_MID_ACT_MD3
MULT_HIGH_RDY_MD3
MULT_HIGH_ACT_MD3
BPF_MD4
MULT_EN_MODE_4
MULT_EN_MODE_5
MULT_EN_MODE_6
MULT_EN_MODE_7
MULT_EN_MODE_8
LOAMP_EN_MD4
MULT_LOW_RDY_MD4
MULT_LOW_ACT_MD4
MULT_MID_RDY_MD4
MULT_MID_ACT_MD4
MULT_HIGH_RDY_MD4
MULT_HIGH_ACT_MD4
BPF_MD5
LOAMP_EN_MD5
MULT_LOW_RDY_MD5
MULT_LOW_ACT_MD5
MULT_MID_RDY_MD5
MULT_MID_ACT_MD5
MULT_HIGH_RDY_MD5
MULT_HIGH_ACT_MD5
BPF_MD6
LOAMP_EN_MD6
MULT_LOW_RDY_MD6
MULT_LOW_ACT_MD6
MULT_MID_RDY_MD6
MULT_MID_ACT_MD6
MULT_HIGH_RDY_MD6
MULT_HIGH_ACT_MD6
BPF_MD7
LOAMP_EN_MD7
Multiplier Mode 7 LO Amplifier Enable
Multiplier Mode 7 Low Band Ready Enable
Multiplier Mode 7 Low Band Active Enable
Multiplier Mode 7 Mid Band Ready Enable
Multiplier Mode 7 Mid Band Active Enable
Multiplier Mode 7 High Band Ready Enable
Multiplier Mode 7 High Band Active Enable
Multiplier Mode 8 BPF Select
MULT_LOW_RDY_MD7
MULT_LOW_ACT_MD7
MULT_MID_RDY_MD7
MULT_MID_ACT_MD7
MULT_HIGH_RDY_MD7
MULT_HIGH_ACT_MD7
BPF_MD8
LOAMP_EN_MD8
Multiplier Mode 8 LO Amplifier Enable
Multiplier Mode 8 Low Band Ready Enable
Multiplier Mode 8 Low Band Active Enable
Multiplier Mode 8 Mid Band Ready Enable
Multiplier Mode 8 Mid Band Active Enable
Multiplier Mode 8 High Band Ready Enable
Multiplier Mode 8 High Band Active Enable
MULT_LOW_RDY_MD8
MULT_LOW_ACT_MD8
MULT_MID_RDY_MD8
MULT_MID_ACT_MD8
MULT_HIGH_RDY_MD8
MULT_HIGH_ACT_MD8
Rev. 0 | Page 34 of 37
Data Sheet
ADAR2004
Address Name
Bits Bit Name
Description
Reset Access
0x079
0x07A
0x07B
0x07C
0x07D
0x07E
MULT_EN_MODE_9
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
BPF_MD9
LOAMP_EN_MD9
Multiplier Mode 9 BPF Select
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Multiplier Mode 9 LO Amplifier Enable
Multiplier Mode 9 Low Band Ready Enable
Multiplier Mode 9 Low Band Active Enable
Multiplier Mode 9 Mid Band Ready Enable
Multiplier Mode 9 Mid Band Active Enable
Multiplier Mode 9 High Band Ready Enable
Multiplier Mode 9 High Band Active Enable
Multiplier Mode 10 BPF Select
Multiplier Mode 10 LO Amplifier Enable
Multiplier Mode 10 Low Band Ready Enable
Multiplier Mode 10 Low Band Active Enable
Multiplier Mode 10 Mid Band Ready Enable
Multiplier Mode 10 Mid Band Active Enable
Multiplier Mode 10 High Band Ready Enable
Multiplier Mode 10 High Band Active Enable
Multiplier Mode 11 BPF Select
Multiplier Mode 11 LO Amplifier Enable
Multiplier Mode 11 Low Band Ready Enable
Multiplier Mode 11 Low Band Active Enable
Multiplier Mode 11 Mid Band Ready Enable
Multiplier Mode 11 Mid Band Active Enable
Multiplier Mode 11 High Band Ready Enable
Multiplier Mode 11 High Band Active Enable
Multiplier Mode 12 BPF Select
Multiplier Mode 12 LO Amplifier Enable
Multiplier Mode 12 Low Band Ready Enable
Multiplier Mode 12 Low Band Active Enable
Multiplier Mode 12 Mid Band Ready Enable
Multiplier Mode 12 Mid Band Active Enable
Multiplier Mode 12 High Band Ready Enable
Multiplier Mode 12 High Band Active Enable
Multiplier Mode 13 BPF Select
MULT_LOW_RDY_MD9
MULT_LOW_ACT_MD9
MULT_MID_RDY_MD9
MULT_MID_ACT_MD9
MULT_HIGH_RDY_MD9
MULT_HIGH_ACT_MD9
BPF_MD10
MULT_EN_MODE_10
MULT_EN_MODE_11
MULT_EN_MODE_12
MULT_EN_MODE_13
MULT_EN_MODE_14
LOAMP_EN_MD10
MULT_LOW_RDY_MD10
MULT_LOW_ACT_MD10
MULT_MID_RDY_MD10
MULT_MID_ACT_MD10
MULT_HIGH_RDY_MD10
MULT_HIGH_ACT_MD10
BPF_MD11
LOAMP_EN_MD11
MULT_LOW_RDY_MD11
MULT_LOW_ACT_MD11
MULT_MID_RDY_MD11
MULT_MID_ACT_MD11
MULT_HIGH_RDY_MD11
MULT_HIGH_ACT_MD11
BPF_MD12
LOAMP_EN_MD12
MULT_LOW_RDY_MD12
MULT_LOW_ACT_MD12
MULT_MID_RDY_MD12
MULT_MID_ACT_MD12
MULT_HIGH_RDY_MD12
MULT_HIGH_ACT_MD12
BPF_MD13
LOAMP_EN_MD13
Multiplier Mode 13 LO Amplifier Enable
Multiplier Mode 13 Low Band Ready Enable
Multiplier Mode 13 Low Band Active Enable
Multiplier Mode 13 Mid Band Ready Enable
Multiplier Mode 13 Mid Band Active Enable
Multiplier Mode 13 High Band Ready Enable
Multiplier Mode 13 High Band Active Enable
Multiplier Mode 14 BPF Select
MULT_LOW_RDY_MD13
MULT_LOW_ACT_MD13
MULT_MID_RDY_MD13
MULT_MID_ACT_MD13
MULT_HIGH_RDY_MD13
MULT_HIGH_ACT_MD13
BPF_MD14
LOAMP_EN_MD14
Multiplier Mode 14 LO Amplifier Enable
Multiplier Mode 14 Low Band Ready Enable
Multiplier Mode 14 Low Band Active Enable
Multiplier Mode 14 Mid Band Ready Enable
Multiplier Mode 14 Mid Band Active Enable
Multiplier Mode 14 High Band Ready Enable
Multiplier Mode 14 High Band Active Enable
MULT_LOW_RDY_MD14
MULT_LOW_ACT_MD14
MULT_MID_RDY_MD14
MULT_MID_ACT_MD14
MULT_HIGH_RDY_MD14
MULT_HIGH_ACT_MD14
Rev. 0 | Page 35 of 37
ADAR2004
Data Sheet
Address Name
Bits Bit Name
Description
Reset Access
0x07F
MULT_EN_MODE_15
7
6
5
4
3
2
1
0
BPF_MD15
LOAMP_EN_MD15
Multiplier Mode 15 BPF Select
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Multiplier Mode 15 LO Amplifier Enable
Multiplier Mode 15 Low Band Ready Enable
Multiplier Mode 15 Low Band Active Enable
Multiplier Mode 15 Mid Band Ready Enable
Multiplier Mode 15 Mid Band Active Enable
Multiplier Mode 15 High Band Ready Enable
Multiplier Mode 15 High Band Active Enable
Reserved
MULT_LOW_RDY_MD15
MULT_LOW_ACT_MD15
MULT_MID_RDY_MD15
MULT_MID_ACT_MD15
MULT_HIGH_RDY_MD15
MULT_HIGH_ACT_MD15
0x100
SCAN_MODE_EN
[7:1] RESERVED
SCAN_MODE_EN
0
Scan Mode Enable
R/W
Rev. 0 | Page 36 of 37
Data Sheet
ADAR2004
OUTLINE DIMENSIONS
7.10
7.00 SQ
6.90
0.30
0.25
0.20
0.25
BSC
PIN 1
PIN 1
INDICATOR
AREA
INDICATOR
C 0.20 × 0.45°
37
48
1
5.05 BSC
SQ
6.00 REF
SQ
2.40 BSC
SQ
25
13
0.50
BSC
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.38
BSC
0.78
0.68
0.58
0.45 REF
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.26
0.23
0.20
SEATING
PLANE
SECTION OF THIS DATA SHEET
Figure 47. 48-Terminal Land Grid Array [LGA] Package
7 mm × 7 mm Body and 0.68 mm Package Height
(CC-48-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CC-48-2
CC-48-2
ADAR2004ACCZ
ADAR2004ACCZ-R7
ADAR2004-EVALZ
48-Terminal Land Grid Array [LGA], Tray
48-Terminal Land Grid Array [LGA], 7” Tape and Reel
Evaluation Board
1 Z = RoHS compliant part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D20539-8/20(0)
Rev. 0 | Page 37 of 37
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