ADAS3022SCPZ-EP-RL [ADI]
16-Bit, 1 MSPS, 8 Channel Data Acquisition System;
| 型号： | ADAS3022SCPZ-EP-RL |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 1 MSPS, 8 Channel Data Acquisition System 转换器 |
| 文件： | 总21页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 1 MSPS, 8-Channel
Data Acquisition System
ADAS3022-EP
Enhanced Product
an 8-channel, low leakage multiplexer; a high impedance
programmable gain instrumentation amplifier (PGIA) stage with
high common-mode rejection; a precision, low drift 4.096 V
reference and buffer; and a 16-bit charge redistribution analog-
to-digital converter (ADC) with a successive approximation
register (SAR) architecture. The ADAS3022-EP can resolve eight
single-ended inputs or four fully differential inputs up to
±24.576 V when using 15 V supplies. In addition, the device
can accept the commonly used bipolar differential, bipolar
single-ended, pseudo bipolar, or pseudo unipolar input signals,
as shown in Table 1, thus enabling the use of almost any direct
sensor interface.
FEATURES
Ease of use—16-bit, 1 MSPS complete data acquisition system
High impedance, 8-channel input: >500 MΩ
Differential input voltage range: 24.576 V maximum
High input common-mode rejection: >100 dB
User-programmable input ranges
Channel sequencer with individual channel gains
On-chip 4.096 V reference and buffer
Auxiliary input—direct interface to PulSAR® ADC inputs
No latency or pipeline delay (SAR architecture)
Serial 4-wire, 1.8 V to 5 V SPI-/SPORT-compatible interface
40-Lead LFCSP package (6 mm × 6 mm)
The ADAS3022-EP simplifies design challenges by eliminating
signal buffering, level shifting, amplification/attenuation,
common-mode rejection, settling time, and any other analog
signal conditioning challenge while allowing a smaller form
factor, faster time to market, and lower cost.
ENHANCED FEATURES
Supports defense and aerospace applications (AQEC
standard)
Military temperature range (such as −55°C to +105°C)
Controlled manufacturing baseline
One assembly/test site
Additional application and technical information can be found
in the ADAS3022 data sheet.
Enhanced product change notification
Qualification data available on request
Table 1. Typical Input Range Selection
APPLICATIONS
Signal (V)
Differential
±±
±2.5
±5
Input Range, VIN (V)
Multichannel data acquisition and system monitoring
Process controls
Power line monitoring
Automated test equipment
Instrumentation
±±.28
±2.56
±5.±2
±±0.24
±±0
GENERAL DESCRIPTION
Single Ended
0 to ±
0 to 2.5
0 to 5
±±.28
±2.56
±5.±2
±±0.24
The ADAS3022-EP is a complete 16-bit, 1 MSPS, successive
approximation–based, analog-to-digital data acquisition system
that is manufactured on Analog Devices, Inc., proprietary iCMOS®
high voltage industrial process technology. The device integrates
0 to ±0
Rev. 0
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2017 Analog Devices, Inc. All rights reserved.
www.analog.com
ADAS3022-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ......................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
Enhanced Features............................................................................ 1
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ........................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Timing Specifications .................................................................. 8
REVISION HISTORY
6/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 2±
Enhanced Product
ADAS3022-EP
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VIO
RESET
PD
VDDH
DIFF TO
COM
DIFF
PAIR
ADAS3022-EP
CNV
LOGIC/
INTERFACE
IN0/IN1
BUSY
IN0
IN1
CS
IN2
IN2/IN3
IN4/IN5
IN6/IN7
IN3
®
SCK
DIN
SDO
PulSAR
ADC
PGIA
MUX
IN4
IN5
IN6
IN7
TEMP
SENSOR
COM
AUX+
REFIN
BUF
REF
AUX–
VSSH
AGND
DGND
REFx
Figure 1.
Rev. 0 | Page 3 of 21
ADAS3022-EP
Enhanced Product
SPECIFICATIONS
VDDH = 15 V 5%, VSSH = −15 V 5%, AVDD = DVDD = 5 V 5%, VIO = 1.8 V to AVDD, internal voltage reference (VREF) =
4.096 V, sampling frequency (fS) = 1 MSPS unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit1
RESOLUTION
±6
Bits
ANALOG INPUTS—IN[7:0], COM
Operating Input Voltage Range
Differential Input Voltage Range, VIN
VIN
VIN+ − VIN−
−VSSH + 2.5
VDDH − 2.5
V
PGIA gain = 0.±6, VIN = 49.±5 V p-p
PGIA gain = 0.2, VIN = 40.96 V p-p
PGIA gain = 0.4, VIN = 20.48 V p-p
PGIA gain = 0.8, VIN = ±0.24 V p-p
PGIA gain = ±.6, VIN = 5.±2 V p-p
PGIA gain = 3.2, VIN = 2.56 V p-p
PGIA gain = 6.4, VIN = ±.28 V p-p
−6 × VREF
−5 × VREF
+6 × VREF
+5 × VREF
+2.5 × VREF
+±.25 × VREF
+0.625 × VREF
+0.3±25 × VREF
+0.±563 × VREF
V
V
V
V
V
V
V
MΩ
nA
nA
−2.5 × VREF
−±.25 × VREF
−0.625 × VREF
−0.3±25 × VREF
−0.±563 × VREF
500
Input Impedance, ZIN
Channel Off Leakage
Channel On Leakage
±0.6
±0.02
Common-Mode Voltage Range
VIN+, VIN−; full-scale differential inputs
2
(VCM
)
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = ±.6
PGIA gain = 3.2
PGIA gain = 6.4
−5.±2
−7.68
−8.96
−9.60
−9.92
+5.±2
+7.68
+8.96
+9.60
+9.92
V
V
V
V
V
ANALOG INPUTS—AUX+, AUX−
Differential Input Voltage Range
THROUGHPUT
−VREF
+VREF
V
Conversion Rate
One channel and one pair
Two channels and two pairs
Four channels and four pairs
Eight channels
0
0
0
0
±000
500
250
±25
520
kSPS
kSPS
kSPS
kSPS
ns
Transient Response
DC ACCURACY
Full-scale step
No Missing Codes
Integral Linearity Error
±6
−2
−3
−5
−0.9
−0.9
−0.9
Bits
LSB
LSB
LSB
LSB
LSB
LSB
PGIA gain = 0.±6, 0.2, 0.4, 0.8, and ±.6
PGIA gain = 3.2
PGIA gain = 6.4
PGIA gain = 0.±6, 0.2, 0.4, 0.8, and ±.6
PGIA gain = 3.2
PGIA gain = 6.4
±0.6
±±.0
±±.5
±0.6
±0.75
±0.75
+2
+3
+5
+±.0
+±.25
+±.25
Differential Linearity Error
Transition Noise
External reference
PGIA gain = 0.±6, 0.2, 0.4, 0.8, and ±.6
PGIA gain = 3.2
5
7
LSB
LSB
PGIA gain = 6.4
±±
LSB
Gain Error
Gain Error Temperature Drift
External reference, all PGIA gains, TA = 25°C −9
External reference, all PGIA gains
+9
0.±
LSB
ppm/°C
Rev. 0 | Page 4 of 2±
Enhanced Product
ADAS3022-EP
Parameter
Test Conditions/Comments
External reference, TA = 25°C
PGIA gain = 0.±6, 0.2, 0.4, and 0.8
PGIA gain = ±.6
PGIA gain = 3.2
PGIA gain = 6.4
Min
Typ
Max
Unit1
Offset Error
−3.0
−4.0
−7.5
−±2.5
+0.2
+0.2
+0.2
+0.2
+3.0
+4.0
+7.5
+±2.5
LSB
LSB
LSB
LSB
Offset Error Temperature Drift
Total Unadjusted Error
External reference
PGIA gain = 0.±6, 0.2, 0.4, and 0.8
PGIA gain = ±.6
PGIA gain = 3.2
PGIA gain = 6.4
0.±
0.2
0.4
0.8
0.5
±.0
2.0
4.0
ppm/°C
ppm/°C
ppm/°C
ppm/°C
External reference, ambient temperature
(TA) = 25°C
PGIA gain = 0.±6, 0.2, 0.4, 0.8, ±.6, and 3.2
PGIA gain = 6.4
−9
−±5
+9
+±5
LSB
LSB
AC ACCURACY3
Signal-to-Noise Ratio (SNR)
fIN = ±0 kHz
PGIA gain = 0.±6
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = ±.6
PGIA gain = 3.2
PGIA gain = 6.4
Input frequency (fIN) = ±0 kHz
90.0
90.0
89.5
89.0
88.0
86.0
83.0
9±.5
9±.5
9±.5
9±.0
89.7
86.8
84.5
dB
dB
dB
dB
dB
dB
dB
Signal-to-Noise-and-Distortion
(SINAD)
PGIA gain = 0.±6
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = ±.6
88.0
88.0
88.5
88.5
87.5
85.5
82.5
90.0
90.0
9±.0
90.5
89.5
86.5
84.0
dB
dB
dB
dB
dB
dB
dB
PGIA gain = 3.2
PGIA gain = 6.4
Dynamic Range
fIN = ±0 kHz, −60 dB input
PGIA gain = 0.±6
PGIA gain = 0.2
9±.0
9±.0
90.5
90.0
89.0
86.0
83.5
92.0
92.0
9±.5
9±.0
90.0
87.0
85.0
−±00
±0±
dB
dB
dB
dB
dB
dB
dB
dB
dB
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = ±.6
PGIA gain = 3.2
PGIA gain = 6.4
fIN = ±0 kHz, all PGIA gains
fIN = ±0 kHz, all PGIA gains
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range
(SFDR)
Channel to Channel Crosstalk
Common-Mode Rejection Ratio
(CMRR)
fIN = ±0 kHz, all channels inactive
fIN = 2 kHz
−±20
dB
PGIA gain = 0.±6, 0.2, 0.4, and 0.8
PGIA gain = ±.6
PGIA gain = 3.2
PGIA gain = 6.4
−40 dBFS
90.0
90.0
90.0
90.0
±±0.0
±05.0
98.0
98.0
8
dB
dB
dB
dB
−3 dB Input Bandwidth
MHz
Rev. 0 | Page 5 of 2±
ADAS3022-EP
Enhanced Product
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit1
AUXILIARY ADC INPUT CHANNEL
DC Accuracy
External reference
Integral Nonlinearity Error
Differential Nonlinearity Error
Gain Error
−1.5
−0.8
−2.5
−5
0.5
0.6
0.2
0.2
+1.5
+1.0
+2.5
+5
LSB
LSB
LSB
LSB
Offset Error
AC Performance
Internal reference
SNR
SINAD
THD
SFDR
90.0
89.5
93.0
92.5
−105
110
dB
dB
dB
dB
INTERNAL REFERENCE
REF1 and REF2 Output Voltage
REF1 and REF2 Output Current
REF1 and REF2 Temperature Drift
TA = 25°C
TA = 25°C
REFEN = 1
REFEN = 0
AVDD = 5 V 5%
4.088
4.096
250
5
4.104
2.505
V
μA
ppm/°C
ppm/°C
1
REF1 and REF2 Line Regulation
Internal Reference
Buffer Only
REFIN Output Voltage4
Turn-On Settling Time
EXTERNAL REFERENCE
Voltage Range
20
4
2.500
100
μV/V
μV/V
V
TA = 25°C
CREFIN, CREF1, CREF2 = 10 μF and 0.1 μF
2.495
4.000
ms
REFx input
REFIN input (buffered)
VREF = 4.096 V
4.096
2.5
100
4.104
2.505
V
V
μA
Current Drain
TEMPERATURE SENSOR
Output Voltage
Temperature Sensitivity
DIGITAL INPUTS
TA = 25 °C
275
800
mV
μV/°C
Logic Levels
Input Voltage Low, VIL
VIO > 3 V
VIO ≤ 3 V
VIO > 3 V
VIO ≤ 3 V
−0.3
−0.3
0.7 × VIO
0.9 × VIO
−1
+0.3 × VIO
+0.1 × VIO
VIO + 0.3
VIO + 0.3
+1
V
V
V
V
μA
μA
Input Voltage High, VIH
Input Low Current, IIL
Input High Current, IIH
DIGITAL OUTPUTS5
Data Format
Output Low Voltage, VOL
Output High Voltage, VOH
POWER SUPPLIES
VIO
−1
+1
Twos complement
0.4
ISINK = +500 μA
ISOURCE = −500 μA
PD = 0
V
V
VIO − 0.3
1.8
4.75
4.75
14.25
−15.75
AVDD + 0.3
5.25
5.25
15.75
−14.25
V
V
V
V
V
AVDD
5
5
15
−15
DVDD
VDDH6
VDDH > input voltage + 2.5 V
VSSH < input voltage − 2.5 V
VSSH6
Rev. 0 | Page 6 of 21
Enhanced Product
ADAS3022-EP
Parameter
Test Conditions/Comments
PGIA gain = 0.16
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
All PGIA gains, PD = 1
PGIA gain = 0.16
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
All PGIA gains, PD = 1
PGIA gain = 6.4, reference buffer enabled
All other PGIA gains, reference buffer
enabled
Min
Typ
3.0
3.0
3.5
5.0
Max
Unit1
mA
mA
mA
mA
mA
mA
mA
μA
mA
mA
mA
mA
mA
mA
mA
μA
VDDH Capacitance, IVDDH
3.5
3.5
4.0
5.5
9.5
17.5
17.5
8.5
15.5
15.5
100
−2.5
−2.5
−3.0
−4.5
−8.0
−15
−15
10
Current at VSSH Supply, IVSSH
−3.0
−3.0
−3.5
−5.5
−9.5
−17.5
−17.5
Current at AVDD, IAVDD
18
16
21.0
19.0
mA
mA
PGIA gain = 6.4, reference buffer disabled
All other PGIA gains, reference buffer
disabled
14
12
17.5
16.0
mA
mA
All PGIA gains, PD = 1
All PGIA gains, PD = 0
All PGIA gains, PD = 1
VIO = 3.3 V, PD = 0
PD = 1
100
2.5
10
0.30
10
μA
mA
μA
mA
μA
Current at DVDD, IDVDD
Current at VIO, IVIO
3.5
1.2
Power Supply Sensitivity
At TA = 25°C
External reference
PGIA gain = 0.16, 0.2, 0.4, and 0.8;
VDDH/VSSH 5%
0.5
LSB
PGIA gain = 3.2, VDDH/VSSH 5%
PGIA gain = 6.4, VDDH/VSSH 5%
PGIA gain = 0.16, AVDD/DVDD 5%
PGIA gain = 0.2, AVDD/DVDD 5%
PGIA gain = 0.4, AVDD/DVDD 5%
PGIA gain = 0.8, AVDD/DVDD 5%
PGIA gain = 1.6, AVDD/DVDD 5%
PGIA gain = 3.2, AVDD/DVDD 5%
PGIA gain = 6.4, AVDD/DVDD 5%
1.0
2.0
0.6
0.8
1.0
1.5
2.0
3.5
7.0
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
−55
+105
°C
1 LSB means least significant bit and changes depending on the voltage range.
2 The common-mode voltage (VCM) for a PGIA gain of 0.16 or 0.2 is 0 V.
3 All ac accuracy specifications expressed in decibels are referred to a full-scale range (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise noted.
4 This is the output from the internal band gap reference.
5 There is no pipeline delay. Conversion results are available immediately after a conversion is complete.
6 The differential input common-mode voltage (VCM) range changes according to the maximum input range selected and the high voltage power supplies (VDDH and
VSSH). Note that the specified operating input voltage of any input pin requires 2.5 V of headroom from the VDDH and VSSH supplies; therefore, (VSSH + 2.5 V) ≤
INx/COM ≤ (VDDH − 2.5 V).
Rev. 0 | Page 7 of 21
ADAS3022-EP
Enhanced Product
TIMING SPECIFICATIONS
VDDH = 15 V 5%, VSSH = −15 V 5%, AVDD = DVDD = 5 V 5%, VIO = 1.8 V to AVDD, internal reference, VREF = 4.096 V,
fS = 1 MSPS unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Time Between Conversions
Warp Mode,± CMS = 0
Normal Mode (Default), CMS = ±
Conversion Time: CNV Rising Edge to Data Available
Warp Mode, CMS = 0
Normal Mode (Default), CMS = ±
Auxiliary ADC Input Channel Acquisition Time
CNV Pulse Width
CNV High to Hold Time (Aperture Delay)
CNV High to Busy Delay
Safe Data Access Time During Conversion
Quiet Conversion Time (BUSY High)
Warp Mode, CMS = 0
Normal Mode (Default), CMS = ±
Data Access During Quiet Conversion Time
Warp Mode, CMS = 0
Normal Mode (Default), CMS = ±
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Valid
SCK Falling Edge to Data Valid Delay
VIO > 4.5 V
tCYC
±
±.±
±000
µs
µs
tCONV
825
925
ns
ns
ns
ns
ns
ns
ns
±000
tACQ
tCH
tAD
tCBD
tDDC
tQUIET
600
±0
2
520
500
400
500
ns
ns
tDDCA
200
300
ns
ns
ns
ns
ns
ns
tSCK
±5
5
5
tSCKL
tSCKH
tSDOH
tSDOD
4
±2
±8
24
25
37
ns
ns
ns
ns
ns
VIO > 3.0 V
VIO > 2.7 V
VIO > 2.3 V
VIO > ±.8 V
CS/RESET/PD Low to SDO
VIO > 4.5 V
tEN
±5
±6
±8
23
28
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIO > 3.0 V
VIO > 2.7 V
VIO > 2.3 V
VIO > ±.8 V
CS/RESET/PD High to SDO High Impedance
DIN Valid Setup Time from SCK Rising Edge
DIN Valid Hold Time from SCK Rising Edge
CNV Rising to CS
tDIS
tDINS
tDINH
tCCS
tRH
4
4
5
5
RESET/PD High Pulse
± Exceeding the maximum time has an effect on the accuracy of the conversion.
Rev. 0 | Page 8 of 2±
Enhanced Product
ADAS3022-EP
Timing Diagrams
I
500µA
OL
70% VIO
30% VIO
tDELAY
tDELAY
1.4V
TO SDO
1
1
2V OR VIO – 0.5V
2V OR VIO – 0.5V
C
L
50pF
2
2
0.8V OR 0.5V
0.8V OR 0.5V
1
500µA
I
2V IF VIO > 2.5V; VIO – 0.5V IF VIO < 2.5V.
0.8V IF VIO > 2.5V; 0.5V IF VIO < 2.5V.
OH
2
Figure 3. Voltage Levels for Timing
Figure 2. Load Circuit for Digital Interface Timing
tACQ
tCYC
SOC
EOC
SOC
EOC
tQUIET
NOTE 2
tDDC
NOTE 1
tDAC
NOTE 1
POWER
UP
CONVERSION (n – 1)
UNDEFINED
ACQUISITION (n)
UNDEFINED
CONVERSION (n)
UNDEFINED
ACQUISITION (n + 1)
UNDEFINED
CONVERSION (n + 1)
UNDEFINED
PHASE
CNV
BUSY
tDDCA
NOTE 2
NOTE 5
tAD
NOTE 4
CS
X
1
16/32
NOTE 3
1
16
SCK
CFG
INVALID
CFG (n + 2)
CFG (n + 2)
CFG (n + 3)
CFG (n + 3)
DIN
DATA
INVALID
DATA (n – 1)
INVALID
DATA (n – 1)
INVALID
DATA (n)
INVALID
DATA (n)
INVALID
SDO
EOC
EOC
EOC
ACQUISITION
(n + 4)
CONVERSION
(n + 2)
ACQUISITION
(n + 3)
CONVERSION
(n + 3)
CONVERSION
(n + 4)
ACQUISITION
(n + 2)
PHASE
CNV
BUSY
CS
1
1
16
16
1
SCK
CFG (n + 4)
CFG (n + 4)
CFG (n + 5)
CFG (n + 5)
CFG (n + 6)
CFG (n + 6)
DIN
DATA (n + 1)
INVALID
DATA (n + 1)
INVALID
SDO
DATA (n + 2)
DATA (n + 2)
DATA (n + 3)
DATA (n + 3)
NOTES
1. DATA ACCESS CAN OCCUR DURING A CONVERSION (tDDC), AFTER A CONVERSION (tDAC), OR BOTH DURING AND AFTER A CONVERSION.
THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC).
2. DATA ACCESS CAN ALSO OCCUR UP TO tDDCA WHILE BUSY IS ACTIVE (SEE THE ADAS3022 DATA SHEET FOR DETAILS). ALL OF THE BUSY
TIME CAN BE USED TO ACQUIRE DATA.
3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO
READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION.
4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE.
5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME
OF THE APERTURE DELAY (tAD) SHOULD ELAPSE PRIOR TO DATA ACCESS.
Figure 4. General Timing Diagram
Rev. 0 | Page 9 of 21
ADAS3022-EP
Enhanced Product
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Analog Inputs/Outputs
INx, COM to AGND
AUX+, AUX− to AGND
REFx to AGND
REFIN to AGND
REFN to AGND
VSSH − 0.3 V to VDDH + 0.3 V
−0.3 V to AVDD + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V
AGND − 0.3 V to +2.7 V
0.3 V
ESD CAUTION
Ground Voltage Differences
AGND, RGND, DGND
Supply Voltages
0.3 V
VDDH to AGND
VSSH to AGND
−0.3 V to +16.5 V
+0.3 V to −16.5 V
−0.3 V to +7 V
AVDD, DVDD, VIO to AGND
ACAP, DCAP, RCAP to GND
Digital Inputs/Outputs
CNV, DIN, SCK, RESET, PD, CS
to DGND
−0.3 V to +2.7 V
−0.3 V to VIO + 0.3 V
SDO, BUSY to DGND
Internal Power Dissipation
Junction Temperature
Storage Temperature Range
Thermal Impedance
θJA
−0.3 V to VIO + 0.3 V
2 W
125°C
−65°C to +125°C
44.1°C/W
0.28°C/W
θJC
Rev. 0 | Page 10 of 21
Enhanced Product
ADAS3022-EP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN0
IN1
1
2
3
4
5
6
7
8
9
30 NC
29
28
27
NC
IN2
AVDD
DVDD
IN3
ADAS3022-EP
TOP VIEW
(Not to Scale)
AUX+
IN4
26 ACAP
25 DCAP
IN5
AGND
24
IN6
23 AGND
22 DGND
21 DGND
IN7
COM 10
NOTES
1. NC = NO CONNECT. THIS PIN IS NOT INTERNALLY CONNECTED.
2. CONNECT THE EXPOSED PADDLE TO VSSH.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1 to 4
5
6 to 9
10
Mnemonic Type1 Description
IN0 to IN3
AUX+
AI
AI
AI
AI
Input Channel 0 to Input Channel 3.
Auxiliary Input Channel Positive Input.
Input Channel 4 to Input Channel 7.
IN4 to IN7
COM
IN[7:0] Common Channel Input. The IN[7:0] input channels can be referenced to a common point. The
maximum voltage on this pin is 10.24 V for all PGIA gains except for a PGIA gain of 0.16, in which case,
the maximum voltage on this pin is 12.22ꢀ V. AUX+ and AUX− are not referenced to COM.
11
12
13
CS
DI
DI
DI
Chip Select. Active low signal. Enables the digital interface for writing and reading data. Use this pin
when sharing the serial bus. For a dedicated ADAS3022-EP serial interface, CS can be tied to DGND or
CNV to simplify the interface.
Data Input. Serial data input used for writing the 16-bit configuration word (CFG) that is latched on SCK
rising edges. CFG is an internal register that is updated on the rising edge of the end of a conversion, which is
the falling edge of BUSY. The configuration register can be written to during and after a conversion.
DIN
RESET
Asynchronous Reset. A low to high transition resets the ADAS3022-EP. The current conversion, if active,
is aborted and CFG is reset to the default state.
14, 29, 30
15
NC
PD
N/A
DI
No Connect. This pin is not connected internally.
Power-Down. A low to high transition powers down the ADAS3022-EP, minimizing the bias current.
Note that this pin must be held high until the user is ready to power on the device; after powering on
the device, the user must wait 100 ms until the reference is enabled and then wait for the completion of
two dummy conversions before the device is ready to convert.
16
17
1ꢀ
19
SCK
DI
Serial Clock Input. The DIN and SDO data sent to and from the ADAS3022-EP are synchronized with
SCK.
Digital Interface Supply. Nominally, this supply is at the same voltage as the supply of the host
interface: 1.ꢀ V, 2.5 V, 3.3 V, or 5 V.
Serial Data Output. The conversion result is output on this pin and is synchronized to SCK falling edges.
The conversion result is output in twos complement format.
Busy Output. An active high signal on this pin indicates that a conversion is in process. Reading or
writing data during the quiet conversion phase (tQUIET) may cause incorrect bit decisions.
VIO
P
SDO
BUSY
DO
DO
20
CNV
DI
P
P
Convert Input. A conversion is initiated on the rising edge of this pin.
Digital Ground. Connect these pins to the system digital ground plane.
Analog Ground. Connect these pins to the system analog ground plane.
Internal 2.5 V Digital Regulator Output. Decouple this internally regulated output using a 10 μF
capacitor and a 0.1 μF local capacitor.
21, 22
23, 24
25
DGND
AGND
DCAP
P
26
ACAP
P
Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal ADC core and all
of the supporting analog circuits with the exception of the internal reference. Decouple this internally
regulated output using a 10 μF capacitor and a 0.1 μF local capacitor.
Rev. 0 | Page 11 of 21
ADAS3022-EP
Enhanced Product
Pin No.
27
28
Mnemonic Type1 Description
DVDD
AVDD
RCAP
P
P
P
Digital 5 V Supply. Decouple this supply using a 10 μF capacitor and a 0.1 μF local capacitor.
Analog 5 V Supply. Decouple this supply using a 10 μF capacitor and a 0.1 μF local capacitor.
Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal reference.
Decouple this pin using a 1 μF capacitor connected to RCAP and a 0.1 μF local capacitor.
31
32
REFIN
AI/O
Internal 2.5 V Band Gap Reference Output, Reference Buffer Input, or Reference Power-Down Input. See
the Voltage Reference Input/Output section of the ADAS3022 data sheet for more information.
33, 34
REF1, REF2 AI/O
Reference Input/Output. Regardless of the reference method, these pins need individual decoupling
using external 10 μF ceramic capacitors connected as close to REF1, REF2, and REFN as possible. REF1
and REF2 must be tied together externally.
35
36, 37
RGND
REFN
P
P
Reference Supply Ground. Connect this pin to the system analog ground plane.
Reference Input/Output Ground. Connect the 10 μF capacitors on REF1 and REF2 to these pins, and
connect these pins to the system analog ground plane.
38
39
40
VSSH
P
High Voltage Analog Negative Supply. Nominally, the supply of this pin should be −15 V. Decouple this
pin using a 10 μF capacitor and a 0.1 μF local capacitor.
High Voltage Analog Positive Supply. Nominally, the supply of this pin should be +15 V. Decouple this
pin using a 10 μF capacitor and a 0.1 μF local capacitor.
Auxiliary Input Channel Negative Input.
Exposed Paddle. Connect the exposed paddle to VSSH.
VDDH
P
AUX−
EPAD
AI
1AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, N/A = not applicable, and P = power.
Rev. 0 | Page 12 of 21
Enhanced Product
ADAS3022-EP
TYPICAL PERFORMANCE CHARACTERISTICS
VDDH = 15 V, VSSH = −15 V, AVDD = DVDD = 5 V, VIO = 1.8 V to AVDD, unless otherwise noted.
2.0
1.00
0.75
0.50
0.25
0
GAIN = 0.16, 0.2, 0.4, 0.8, AND 1.6
INL MAX = +0.649
INL MIN = –0.592
FOR ALL GAINS
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.25
–0.50
–0.75
–1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE
Figure 9. Differential Nonlinearity (DNL) vs. Code for All PGIA Gains
Figure 6. Integral Nonlinearity (INL) vs. Code,
PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6
400,000
2.0
1.5
GAIN = 3.2
INL MAX = +1.026
INL MIN = –0.948
GAIN = 0.16, 0.2, 0.4, 0.8, 1.6
350,000
300,200
300,000
1.0
250,000
200,000
0.5
0
152,600
150,000
–0.5
–1.0
–1.5
–2.0
100,000
52,300
50,000
6,400
600
0
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE
CODE IN HEX
Figure 10. Histogram of a DC Input at Code Center,
PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6
Figure 7. Integral Nonlinearity vs. Code, PGIA Gain = 3.2
400,000
2.0
1.5
GAIN = 6.4
INL MAX = +0.558
INL MIN = –1.319
GAIN = 3.2
350,000
300,000
1.0
250,000
0.5
213,200
200,000
0
150,000
129,000
118,400
–0.5
–1.0
–1.5
–2.0
100,000
50,000
25,500
1,600
22,700
1,400
0
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE
CODE IN HEX
Figure 11. Histogram of a DC Input at Code Center, PGIA Gain = 3.2
Figure 8. Integral Nonlinearity vs. Code, PGIA Gain = 6.4
Rev. 0 | Page ±3 of 2±
ADAS3022-EP
Enhanced Product
400,000
100
90
80
70
60
50
40
30
20
10
0
EXTERNAL REFERENCE
GAIN = 6.4
fS = 1000kSPS
GAIN = 6.4
350,000
300,000
250,000
200,000
150,000
100,000
50,000
157,300
151,900
82,000
75,100
21,700
18,400
2,400
300
200
100
0
0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
OFFSET DRIFT (ppm/°C)
CODE IN HEX
Figure 12. Histogram of a DC Input at Code Center, PGIA Gain = 6.4
Figure 15. Offset Drift, PGIA Gain = 6.4
100
120
100
80
60
40
20
0
112
EXTERNAL REFERENCE
GAIN = 0.16, 0.2, 0.4, 0.8, AND 1.6
fS = 1000kSPS
fS = 1000kSPS
EXTERNAL 2.5V REFERENCE
INTERNAL BUFFER
90
80
70
60
50
40
30
20
10
0
72
23
3
2
0
1
2
4
5
6
7
8
9
10
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OFFSET DRIFT (ppm/°C)
REFERENCE BUFFER DRIFT (ppm/°C)
Figure 16. Reference Buffer Drift, External 2.5 V Reference
Figure 13. Offset Drift, PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6
120
100
fS = 1000kSPS
INTERNAL 2.5V REFERENCE
INTERNAL BUFFER
EXTERNAL REFERENCE
GAIN = 3.2
fS = 1000kSPS
90
80
70
60
50
40
30
20
10
0
100
80
60
40
20
0
46
38
35
30
15 15
11
10
8
6
2
1
0
1
2
3
4
5
6
7
9
10 11 12 13 14 15
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
OFFSET DRIFT (ppm/°C)
REFERENCE BUFFER DRIFT (ppm/°C)
Figure 17. Reference Buffer Drift, Internal 2.5 V Reference
Figure 14. Offset Drift, PGIA Gain = 3.2
Rev. 0 | Page ±4 of 2±
Enhanced Product
ADAS3022-EP
0
0
–20
GAIN = 0.16
fS = 1000kSPS
GAIN = 0.8
fS = 1000kSPS
–20
fIN = 10.1kHz
fIN = 10.1kHz
–40
–40
SNR = 91.7dB
SINAD = 89.2dB
THD = –92.5dB
SFDR = 92.5dB
SNR = 90.7dB
SINAD = 90.6dB
THD = –107dB
SFDR = 106dB
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
0
0
100
200
300
400
500
500
500
0
0
0
100
200
300
400
500
500
500
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 18. 10 kHz FFT, PGIA Gain = 0.16
Figure 21. 10 kHz FFT, PGIA Gain = 0.8
0
–20
0
–20
GAIN = 0.2
fS = 1000kSPS
fIN = 10.1kHz
SNR = 91.4dB
SINAD = 89.9dB
THD = –94.7dB
SFDR = 94.8dB
GAIN = 1.6
fS = 1000kSPS
fIN = 10.1kHz
SNR = 89.8dB
SINAD = 89.7dB
THD = –106dB
SFDR = 107dB
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
100
200
300
400
100
200
300
400
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 19. 10 kHz FFT, PGIA Gain = 0.2
Figure 22. 10 kHz FFT, PGIA Gain = 1.6
0
–20
0
–20
GAIN = 0.4
fS = 1000kSPS
fIN = 10.1kHz
SNR = 91.2dB
SINAD = 91.0dB
THD = –103dB
SFDR = 104dB
GAIN = 3.2
fS = 1000kSPS
fIN = 10.1kHz
SNR = 87.6dB
SINAD = 87.5dB
THD = –105dB
SFDR = 106dB
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
100
200
300
400
100
200
300
400
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 20. 10 kHz FFT, PGIA Gain = 0.4
Figure 23. 10 kHz FFT, PGIA Gain = 3.2
Rev. 0 | Page ±5 of 2±
ADAS3022-EP
Enhanced Product
–55
–60
0
GAIN = 0.4, –0.5dBFS
GAIN = 0.8, –0.5dBFS
GAIN = 1.6, –0.5dBFS
GAIN = 3.2, –0.5dBFS
GAIN = 0.4, –10dBFS
GAIN = 0.8, –10dBFS
GAIN = 1.6, –10dBFS
GAIN = 3.2, –10dBFS
GAIN = 6.4
fS = 1000kSPS
fIN = 10.1kHz
SNR = 85.7dB
SINAD = 85.6dB
THD = –101dB
SFDR = 103dB
–20
–65
–70
–40
–75
–60
–80
–85
–80
–90
–100
–120
–140
–160
–180
–95
–100
–105
–110
–115
–120
–125
0
1
1
100
200
300
400
500
1000
1000
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 24. 10 kHz FFT, PGIA Gain = 6.4
Figure 27. THD vs. Frequency
100
95
90
85
80
75
70
–60
–70
INTERNAL REFERENCE
CHANNEL 4 TO COM, SEQUENCER DISABLED
V
= –0.5dBFS ON CHANNEL 0 TO CHANNEL 3,
CHANNEL 5 TO CHANNEL 7
IN
fS = 1000kSPS
–80
–90
–100
–110
–120
–130
–140
GAIN = 0.4, –0.5dBFS
GAIN = 0.8, –0.5dBFS
GAIN = 1.6, –0.5dBFS
GAIN = 3.2, –0.5dBFS
GAIN = 0.4, –10dBFS
GAIN = 0.8, –10dBFS
GAIN = 1.6, –10dBFS
GAIN = 3.2, –10dBFS
0
20
40
60
80
100 120 140 160 180 200
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 28. Crosstalk vs. Frequency
Figure 25. SNR vs. Frequency
100
95
90
85
80
75
70
65
60
55
50
130
120
110
100
90
GAIN = 0.16
GAIN = 0.20
GAIN = 0.40
GAIN = 0.80
GAIN = 1.60
GAIN = 3.20
GAIN = 6.40
GAIN = 0.4, –0.5dBFS
GAIN = 0.8, –0.5dBFS
GAIN = 1.6, –0.5dBFS
GAIN = 3.2, –0.5dBFS
GAIN = 0.4, –10dBFS
GAIN = 0.8, –10dBFS
GAIN = 1.6, –10dBFS
GAIN = 3.2, –10dBFS
80
COMMON-MODE AMPLITUDE = 20.48V p-p
INTERNAL REFERENCE
fS = 1000kSPS
70
60
10
100
1
10
100
1k
10k
100k
FREQUENCY (kHz)
FREQUENCY (Hz)
Figure 26. SINAD vs. Frequency
Figure 29. CMRR vs. Frequency
Rev. 0 | Page ±6 of 2±
Enhanced Product
ADAS3022-EP
–50
20
18
16
14
12
10
PSRR VDDH
PSRR VSSH
AVDD, GAIN = 0.2
AVDD, GAIN = 1.6
AVDD, GAIN = 6.4
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
–55
AVDD, GAIN = 3.2
–60
–65
–70
–75
–80
–85
–90
–95
–100
0.01
0.1
1
10
100
10
100
THROUGHPUT (kSPS)
1000
FREQUENCY (kHz)
Figure 30. Power Supply Rejection Ration (PSRR) vs. Frequency
Figure 33. AVDD Current vs. Throughput, Internal Reference
19
15
14
13
12
11
10
9
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
18
17
16
15
14
13
4.7
4.8
4.9
5.0
AVDD SUPPLY (V)
5.1
5.2
5.3
10
100
THROUGHPUT (kSPS)
1000
Figure 31. AVDD Current vs. AVDD Supply, Internal Reference
Figure 34. AVDD Current vs. Throughput, External Reference
15
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
14
13
12
11
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
10
4.7
4.8
4.9
5.0
AVDD SUPPLY (V)
5.1
5.2
5.3
10
100
THROUGHPUT (kSPS)
1000
Figure 32. AVDD Current vs. AVDD Supply, External Reference
Figure 35. DVDD Current vs. Throughput
Rev. 0 | Page ±7 of 2±
ADAS3022-EP
Enhanced Product
0
–2
18
fS = 1000kSPS
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
15
12
9
–4
–6
–8
–10
–12
–14
–16
–18
–20
6
3
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
10
100
THROUGHPUT (kSPS)
1000
TEMPERATURE (°C)
Figure 36. VDDH Current vs. Throughput
Figure 39. VSSH Current vs. Temperature
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
0
–3
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
fS = 1000kSPS
–6
–9
–12
–15
–18
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
10
100
THROUGHPUT (kSPS)
1000
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
Figure 40. AVDD Current vs. Temperature
Figure 37. VSSH Current vs. Throughput
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
20
18
16
14
12
10
8
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
VIO = 3.3V
fS = 1000kSPS
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
fS = 1000kSPS
6
4
2
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 41. DVDD Current vs. Temperature
Figure 38. VDDH Current vs. Temperature
Rev. 0 | Page ±8 of 2±
Enhanced Product
ADAS3022-EP
5
4
4.00
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
GAIN = 0.16
GAIN = 0.2
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
fS = 1000kSPS
EXTERNAL REFERENCE
fS = 1000kSPS
3.75
3.50
3.25
3.00
2.75
2.50
2.25
2.00
3
2
1
0
–1
–2
–3
–4
–5
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 45. Gain Error vs. Temperature
Figure 42. VIO Current vs. Temperature
12
8
100
98
96
94
92
90
88
86
84
82
80
fS = 1000kSPS
GAIN = 0.16
GAIN = 0.16
fS = 1000kSPS
EXTERNAL REFERENCE
GAIN = 0.2
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
GAIN = 0.2
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
4
0
–4
–8
–12
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 43. SNR vs. Temperature
Figure 46. Offset Error vs. Temperature
–80
–85
5
4
GAIN = 0.16
fS = 1000kSPS
EXTERNAL REFERENCE
GAIN = 0.2
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
3
–90
2
GAIN ERROR
–95
1
–100
–105
–110
–115
–120
0
OFFSET ERROR
–1
–2
–3
–4
–5
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 44. THD vs. Temperature
Figure 47. Offset and Gain Errors of the AUX +/AUX− ADC Channel Pair vs.
Temperature
Rev. 0 | Page ±9 of 2±
ADAS3022-EP
Enhanced Product
5600
5400
5200
5000
4800
4600
4400
4200
4000
3800
3600
32
28
24
20
16
12
8
25
20
15
10
5
T
= 25°C
A
INTERNAL REFERENCE
4
3400
0
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
0
100 200 300 400 500 600 700 800 900 1000
TEMPERATURE (°C)
THROUGHPUT (kSPS)
Figure 48. Temperature Sensor Output Code vs. Temperature
Figure 50. Temperature Sensor Output Error vs. Throughput
0.5
fS = 1000kSPS
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–0.5dBFS
GAIN = 0.2
GAIN = 0.8
GAIN = 3.2
GAIN = 0.4
GAIN = 1.6
GAIN = 6.4
–4.5
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 49. Large Signal Frequency Response vs. Gain
Rev. 0 | Page 20 of 2±
Enhanced Product
ADAS3022-EP
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
40
31
30
1
0.50
BSC
*
4.70
EXPOSED
PAD
4.60 SQ
4.50
21
10
11
20
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.00
0.95
0.85
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5
WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.
Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.95 mm Package Height
(CP-40-15)
Dimensions shown in millimeters
(See the ADAS3022 Data Sheet for Additional Information)
ORDERING GUIDE
Model1
ADAS3022SCPZ-EP
ADAS3022SCPZ-EP-RL
EVAL-ADAS3022EDZ
Temperature Range
Package Description
Package Option
CP-40-15
CP-40-15
−55°C to +105°C
−55°C to +105°C
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15983-0-6/17(0)
Rev. 0 | Page 21 of 21
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