ADATE205BSV [ADI]
250 MHz Dual DCL; 250 MHz双通道DCL
| 型号： | ADATE205BSV |
| 厂家： | 
ADI |
| 描述： | 250 MHz Dual DCL |
| 文件： | 总16页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
250 MHz Dual DCL
ADATE205
FEATURES
Driver, comparator, and active load
250 MHz toggle rate
Inhibit mode function
Dynamic clamps
Operating voltage range: −1.5 V to +6.5 V
Output voltage swing: 200 mV to 8 V
Four range adjustable slew rate
True/complement data mode bit
100-lead thin quad flat package, exposed pad
Low per channel power
FUNCTIONAL BLOCK DIAGRAM
VCC
NC
(30, 46)
SHIELDS
(80, 82, 94, 96)
(18, 19, 57, 58, 77, 78, 89, 98, 99)
7
VIT
VIL
VIH
69
8
ADATE205
68
9
67
6
DR_INV
DR_DATA_P
70
22
54
23
53
10
65
CLAMPL
CLAMPH
11
66
DR_DATA_P_T
DR_DATA_N_T
DR_DATA_N
24
52
25
51
26
50
27
49
1.15 W with load off
81
95
DRIVER
DUT
LOGIC
1.50 W with load programmed at 20 mA nominal
Low leakage (<10 nA) in High-Z mode
Driver
50 Ω output resistance
1.6 ns minimum pulse width for a 3 V step
Load: −35 mA to +35 mA maximum current range
DR_EN_P
DR_EN_P_T
28
48
29
47
15
61
14
62
DR_EN_N_T
DR_EN_N
VTEN
LDEN
APPLICATIONS
Automatic test equipment
Semiconductor test systems
Board test systems
Instrumentation and characterization equipment
91
85
CVH
COMP_H_P
COMP_H_N
31
45
32
44
13
63
34
42
35
41
COMP_H
CLLM
COMP_L_P
GENERAL DESCRIPTION
COMP_L
COMP_L_N
CVL
The ADATE205 is a complete, single-chip solution that
performs the pin electronics functions of driver, comparator,
and active load (DCL) for ATE applications. The active load can
be powered down if not used.
90
86
IOL
LOAD
LOGIC
1
VCOM
1x
75
The driver is a proprietary design that features three active
modes: data high mode, data low mode, and term mode, as well
as an inhibit state.
4
72
3
VIOL
VIOH
IOH
73
2
GNDREF
The driver has low leakage (<10 nA) in High-Z mode. The
output voltage range is −1.5 V to +6.5 V to accommodate a wide
variety of test devices.
TEMP SENSOR
88 TEMP
74
(5 DIODES)
VEE
(16, 17, 33, 43, 59, 60, 84, 87, 92)
GND
(5, 12, 20, 21, 36, 40, 55, 56, 64, 71, 76, 79, 83, 93, 97,100)
Figure 1.
The ADATE205 supports four programmable Tr/Tf times for
applications where slower edge rates are required. The edge rate
selection is done via two static digital CMOS select bits. The
input data to the driver can be inverted using a single CMOS
logic bit. This feature can be used for system calibration or
applications where complement input data is needed.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADATE205
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................8
ESD Caution...................................................................................8
Pin Configuration and Function Descriptions..............................9
Typical Performace Characteristics ............................................. 12
Theory of Operation ...................................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
REVISION HISTORY
1/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADATE205
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 10 V, VEE = −5 V, TJ = 75°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Single-Ended Logic Input Characteristics
(VTEN, DRV_INV)
Threshold Voltage
Voltage Range
Bias Current
CMOS_VDD/2
V
V
μA
0
−10
5.5
+10
VIN = 0 V, 3.3 V
Single-Ended Logic Input Characteristics
(SLEW0, SLEW1)
Threshold Voltage
Voltage Range
Bias Current
CMOS_VDD/2
V
V
μA
mA
0
−10
5.5
+600 (@ 3.3 V) +800
1
VIN = 0 V, 3.3 V
VIN = 5.5 V
Bias Current
Differential Logic Input Characteristics
(DR_DATA_N, DR_DATA_P, DR_EN_N,
DR_EN_P)
Voltage Range
Differential Voltage with LVPECL Levels
Bias Current
VIH, VIL Reference Inputs
Input Bias Current
−2.0
250
−10
+3.5
V
mV
μA
300
+2
+10
+10
VIN = 3.24 V, 3.495 V
−10
−25
−2
μA
μA
Maximum value bias of
reference sweep
VIT Reference Inputs
Input Bias Current
+12
+25
Maximum value bias of
reference sweep
DC Output Characteristics
Logic Range, VIL, VIH, VIT
Amplitude [VH to VL]
Output Resistance
PSRR, Drive or Term Mode
Static Current Limit
−1.5
47.5
−125
+6.5
8
52.5
V
V
Ω
mV/V
mA
10
110
VCC, VEE 1ꢀ
Output to −1.5 V, VH = 6.5 V,
VT = 0 V
+125
Absolute Accuracy—VIH, VIL, VIT
VIH Offset
−100
0.98
−15
+30
+100
1.02
+15
mV
V/V
mV
Data = H, VH = 0 V, VL = −1.5 V,
VT = 3 V
Data = H, VH = 0 V to 5 V,
VL = −1.5 V, VT = 3 V
Data = VH relative to line
between 0 V to 5 V; full range of
VIH = −1.4 V to +6.5 V
VIH Gain Error
VIH Linearity Error
+5
VIL Offset
VIL Gain Error
−100
0.98
+30
+100
1.02
mV
V/V
Data = L, VL = 0 V to 5 V,
VH = 6.5 V, VT = 3 V
VIL Linearity Error
−15
+5
+15
mV
Data = VH relative to line
between 0 V to 5 V; full range of
VIH = −1.4 V to +6.5 V
VIT Offset
−100
0.98
+30
+100
1.02
mV
V/V
Data = VT, VT = 0 V, VL = 0 V,
VH = 3 V
Data = VT, VT = 0 V to 5 V,
VL = 0 V, VH = 3 V
VIT Gain Error
Rev. 0 | Page 3 of 16
ADATE205
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
VIT Linearity Error
−15
+5
+15
mV
Data = VH relative to line
between 0 V to 5 V; full range of
VIH = −1.4 V to +6.5 V
Offset Tempco
Driver Interaction
VH Interaction to VL
80
μV/°C
65°C to 105°C
−2
−2
−2
−2
−2
+2
+2
+2
+2
+2
mV
mV
mV
mV
mV
VIH = 5.0 V; VIL = −1.5 V, +4.7 V,
+4.8 V, +4.9 V
VIH = 3.0 V; VIT = −1.5 V, +2.9 V,
+3.1 V, +6.5 V
VIL = 0.0 V; VIH = 0.1 V, 0.2 V,
0.3 V, 6.5 V
VIL = 0.0 V; VIT = −1.5 V, −0.1 V,
+0.1 V, +6.5 V
VH Interaction to VT
VL Interaction to VH
VL Interaction to VT
VT Interaction to VH
VIT = 1.5 V, VIL = −1.0 V;
VIH = −0.8 V, +1.4 V, +1.6 V,
+6.5 V
VT Interaction to VL
−2
+2
mV
VIT = 1.5 V, VIH = 6.0 V; IL = −1.5
V, +1.4 V, +1.6 V, +5.8 V
Rise/Fall Times at Device Under Testing (DUT)
0.2 V Swing: Rise/Fall Time
300
500
800
1.1
ps
ps
ps
ns
ps
Terminated 20ꢀ to 80ꢀ,
VIH = 400 mV, VIL = 0 V, VIT = 0 V
Terminated 10ꢀ to 90ꢀ,
VIH = 1.0 V, VIL = 0 V, VIT = 0 V
Terminated 10ꢀ to 90ꢀ,
VIH = 2.0 V, VIL = 0 V, VIT = 0 V
Unterminated 10ꢀ to 90ꢀ,
VIH = 3.0 V, VIL = 0 V, VIT = 0 V
Terminated 20ꢀ to 80ꢀ,
VIH = 3.0 V, VIL = 0 V, VIT = 0 V
using DUT comparator
0.5 V Swing: Rise/Fall Time
1 V Swing: Rise/Fall Time
3 V Swing: Rise/Fall Time
3 V Swing: Rise/Fall Time
700
800
920
5 V Swing: Rise/Fall Time
1.8
ns
Unterminated 10ꢀ to 90ꢀ;
VIH = 5.0 V, VIL = 0 V, VIT = 0 V
Minimum Pulse Width at DUT
500 mV Swing1
500
800
250
ps
Terminated, VIH = 1.0 V, VIL = 0 V,
VIT = 0 V
Terminated, VIH = 3.0 V, VIL = 0 V,
VIT = 0 V
Unterminated, 50/50 dc
measured frequency when
amplitude drops 10ꢀ
1.5 V Swing1
ps
Toggle Rate @ 3 V
MHz
Dynamic Performance, Drive (VH and VL)
Propagation Delay Time2
1.4
2.0
ns
Terminated, VIH = 3.0 V,
VIL = 0.0 V, VIT = 0.0 V
Terminated, VIH = 3.0 V,
VIL = 0.0 V, VIT = 0.0 V,
65°C to 85°C
Propagation Delay Tempco2
ps/°C
Delay Matching, Edge-to-Edge
Delay Change vs. Pulse Width2
20
30
ps
ps
Terminated, VIH = 3.0 V,
VIL = 0.0 V, VIT = 0.0 V, 1μs
period, pulse width = 50 ns
to 1 ns
Terminated, VIH = 3.0 V,
VIL = 0.0 V, VIT = 0.0 V, 1 μs
period; 10ꢀ, 50ꢀ, and 90ꢀ duty
cycle
Delay Change vs. Duty Cycle2
5
ps
Rev. 0 | Page 4 of 16
ADATE205
Parameter
Settling Time to 15 mV
Min
Typ
Max
Unit
Test Conditions/Comments
8
ns
Terminated, VIH = 3 V,
VIL = 0.0 V, VIT = 0.0 V
Settling Time to 4 mV
32
ns
Terminated, VIH = 3 V, VIL = 0.0 V,
VIT = 0.0 V
Rise and Fall Time Temperature Coefficient
500 mV Swing
2
2
2
2
ps/°C
ps/°C
ps/°C
ps/°C
Terminated 10ꢀ to 90ꢀ,
VIH = 1.0 V, VIL = 0.0 V,
VIT = 0.0 V, 65°C to 85°C
Terminated 10ꢀ to 90ꢀ,
VIH = 2.0 V, VIL = 0.0 V,
VIT = 0.0 V, 65°C to 85°C
Unterminated 10ꢀ to 90ꢀ,
VIH = 3.0 V, VIL = 0.0 V,
VIT = 0.0 V, 65°C to 85°C
Unterminated 10ꢀ to 90ꢀ,
VIH = 5.0 V, VIL = 0.0 V,
VIT = 0.0 V, 65°C to 85°C
1 V Swing
3 V Swing
5 V Swing
Overshoot and Preshoot 200 mV swing
Overshoot and Preshoot 1 V swing
Overshoot and Preshoot 3 V swing
Overshoot and Preshoot 5 V swing
Dynamic Performance, Inhibit
1
1
2
2
ꢀ
ꢀ
ꢀ
ꢀ
Terminated, VIH = 400 mV
Terminated, VIH = 2 V
Unterminated
Unterminated
Delay Time, Active High to Inhibit3
3.1
2.1
2.5
3.9
350
ns
ns
ns
ns
mV
Terminated, VIH = 3.0 V,
VIL = −1.0 V
VH = 3.0 V, VL = −1.0 V,
terminated 50 Ω
Terminated, VIH = 3.0 V,
VIL = −1.0 V
Terminated, VIH = 3.0 V,
VIL = −1.0 V
Delay Time, Active Low to Inhibit3
Delay Time, Inhibit to Active High3
Delay Time, Inhibit to Active Low3
I/O Spike
Terminated, VIH = 0.0 V,
VIL = 0.0 V, VIT = 0.0 V
CLAMPS
VCPH, VCPL Clamp Inputs
VCPH Voltage Range
VCPL Voltage Range
Input Bias Current
CLAMPL
−1.8
−50
6.8
CLAMPH
+50
V
V
μA
−2
Maximum value bias of
reference sweep = −1.8 V to
+6.8 V
Absolute Accuracy VCPH, VCPL
VCPH Offset
VCPH Gain Error
−100
−100
+55
1
+10
+100
+100
mV
V/V
mV
Driver = INH, VCPH = 0 V
VCPH Linearity Error
Driver = INH, relative to line
between 0 V to 4.5 V,
VCPH = −1.5 V to +6.5 V,
VCPL = −1.8 V
VCPL Offset
VCPL Gain Error
VCPL Linearity Error
+55
1
+10
mV
V/V
mV
Driver = INH, VCPL = 0 V
Driver = INH, relative to line
between 0 V to 4.5 V,
VCPL = −1.5 V to +6.5 V,
VCPH = 6.5 V
COMPARATOR DC SPECIFICATIONS4
DC Input Characteristics (VOH, VOL)
Bias Current
−10
−1.5
−8.0
+5
+10
+6.5
+8.0
μA
V
V
VOH and VOL = −1.5 V to +6.5 V
Voltage Range
Differential Voltage
Rev. 0 | Page 5 of 16
ADATE205
Parameter
Min
Typ
Max
Unit
mV
ꢀ FSR
mV
Test Conditions/Comments
Common mode = 0 V
VIN = −1.5 V to +6.5 V
Offset
Gain Error
Linearity Error
−15
+15
1
3
VIN = −1.5 V to +6.5 V
Single-Ended Logic Input Characteristics
Threshold Voltage (CLLM)
Voltage Range
CMOS_VDD/2
V
V
0
5.5
Bias Current
Bias Current
−10
+160
260
+200
μA
μA
VIN = 0 V, 3.3 V
VIN = 5.5 V
Digital Output Characteristics
(VOH, VOL Levels)
Logic 1
Logic 0
Differential Levels
3.1
2.7
350
3.26
2.86
400
3.4
3.1
450
V
V
mV
Terminated 50 Ω to 3.3 V
Terminated 50 Ω to 3.3 V
Terminated 50 Ω to 3.3 V
COMPARATOR AC SPECIFICATIONS
Propagation Delay
Input to Output
500
1.0
ps
ps/°C
VIN = 3 V p-p, 2 V/ns
VIN = 3 V p-p, 2 V/ns
Propagation Delay Tempco
Propagation Delay Change with Respect to
PD vs. Duty Cycle
40
30
ps
ps
ps
ps
ps
VIN = 0 V to 3 V, 2 V/ns, driver in
VTERM, VIT = 0 V, period = 10 ns;
dc = 1 ns, 5 ns, 9 ns
VIN = 0 V to 3 V, driver in VTERM,
VIT = 0 V; slew rates = 1 V/ns,
2 V/ns, 3 V/ns
VIN = 0 V to 500 mV, 0 V to 1 V, 0 V
to 3 V, 2 V/ns, driver in VTERM,
VIT = 0 V
VIN = 0 V to 1 V, <50 ps, 20ꢀ to
80ꢀ rise time, driver in VTERM =
0 V
Slew Rate: 1 V/ns, 2 V/ns, 3 V/ns
Amplitude: 500 mV, 1.0 V, 3.0 V
Equivalent Input Rise Time
Pulse-Width Linearity
30
225
20
VIN = 0 V to 3 V, 2 V/ns; pulse
width = 3 ns, 4 ns, 5 ns, 10 ns;
driver in VTERM, VIT = 0 V
Settling Time
5.5
1
ns
ns
Settling to 8 mV, VIN = 0 V to
3 V, driver in VTERM, VIT = 0 V
2 V terminated, 1 V at the
comparator, driver in VTERM,
VIT = 0 V, 1 μs period, pulse
width = 50 ns to 1 ns
Minimum Pulse Width
Hysteresis
6
mV
ps
VIN = 100 mV, sweep CVL and
CVH
HCOMP rise to LCOMP rise,
HCOMP fall to LCOMP fall
Comparator Propagation Delay Matching,
HCOMP to LCOMP
50
LOAD DC SPECIFICATIONS
Single-Ended Logic Input Characteristics
Threshold Voltage (LDEN)
Voltage Range
CMOS_VDD/2
V
V
0
5.5
Bias Current
−10
+10
μA
VIN = 0 V, 3.3 V
Input Characteristics
VIOL Current Program Range
0.0
3.5
V
VDUT = −1.5 V, +6.5 V
IOL = 0 mA to 35 mA
VIOH Current Program Range
VIOH, VIOL Input Bias Current
0.0
3.5
V
VDUT = −1.5 V, +6.5 V,
IOH = 0 mA to 35 mA
VIOL = 0 V, 3.5 V; VIOH = 0 V,
3.5 V
−10
+10
μA
Rev. 0 | Page 6 of 16
ADATE205
Parameter
VDUT Range
Min
−1.5
−1.5
Typ
Max
+6.5
+6.5
Unit
V
V
Test Conditions/Comments
|VDUT − VCOM| > 1.0 V
VDUT − VCOM > 1.0 V,
IOH = 0 mA to 35 mA
VDUT Range
VDUT Range
−1.5
+6.5
V
VCOM − VDUT > 1.0 V,
IOL = 0 mA to 35 mA
Output characteristics
Gain
9.5
10
10.5
+200
+50
mA/V
μA
Slope of line between 5 mA and
30 mA
IOH and IOL programmed at
20 mV (200 μA)
Relative to a line from 5 mA to
30 mA; IOL, IOH from 200 μA to
35 mA
Load Offset, IOH, IOLT
−200
−50
Load Nonlinearity, IOH, IOLT
μA
Output Current Tempco, IOH, IOLT
VCOM Buffer (Through Bridge)
VCOM Buffer Offset
VCOM Buffer Bias Current
VCOM Buffer Gain
3
μA/C
Measured at IOH, IOL = 30 mA
10
−10
0.99
3
10
+10
1.01
mV
μA
V/V
IOL, IOH = 20 mA, VCOM = 0 V
VCOM = −1.5 V to +6.5 V
IOL, IOH = 20 mA,
+1
1
VCOM = −1.5 V to +6.5 V
VCOM Buffer Linearity Error
−10
+1
+10
mV
IOL, IOH = 20 mA,
VCOM = −1.5 V to +6.5 V, relative
to a line at 0 V and 5 V
Dynamic Performance
Propagation Delay—IMAX to INHIBIT
2.3
2.3
ns
ns
VTT = 2 V, VCOM = 4 V/0 V,
IOL = 20 mA, IOH = 20 mA
VTT = 2 V, VCOM = 4 V/0 V,
IOL = 20 mA, IOH = 20 mA
INHIBIT to IMAX
TOTAL FUNCTION
Output Leakage Current
−1.5
+0.28
+10
2
+1.5
μA
nA
pF
Driver = INH, VDUT swept from
−1.5 V to +6.5 V
Driver = INH, VDUT swept from
−1.5 V to +6.5 V
Output Leakage Current, Low Leakage Mode
−200
+200
Output Capacitance
Power Supplies5
Total Supply Range
Positive Supply, VCC
Negative Supply, VEE
Positive Supply Current, VCC
15.5
V
V
V
mA
9.75
−5.25
160
10.0
−5.0
180
10.25
−4.75
205
Load enabled at 20 mA, driver is
set to VIL = 0 V
Negative Supply Current, VEE
210
2
240
3
270
4
mA
W
Load enabled at 20 mA, driver is
set to VIL = 0 V
Load enabled at 20 mA, driver is
set to VIL = 0 V
Total Power Dissipation
Positive Supply Current Load Disabled, VCC
115
135
190
2.3
10
170
220
2.8
mA
mA
W
Load enabled at 0 mA, driver is
set to VIL = 0 V
Load enabled at 0 mA, driver is
set to VIL = 0 V
Load enabled at 0 mA, driver is
set to VIL = 0 V
Five diodes in series
Negative Supply Current Load Disabled, VEE 160
Total Power Dissipation
1.3
Temperature Sensor Gain Factor
mV/°C
1 1 μs period, pulse width = 50 ns to 500 ps, pulse width measured when amplitude drops 10ꢀ.
2 Measured at 50ꢀ of input amp to 50ꢀ of output amp.
3 tPD measured from the 50ꢀ of enable signal to 50ꢀ of output.
4 The low leakage mode of the comparator, controlled by VLLM input, reduces the leakage due to the comparator input. The comparator operates in this mode, but its
bandwidth is compromised and is not guaranteed.
5 Under no circumstances should the input voltages exceed the supply voltages.
Rev. 0 | Page 7 of 16
ADATE205
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Maximum Current for VCC
205 mA
Maximum Current for VEE
270 mA
Positive Supply Voltage (VCC to GND)
Negative Supply Voltage (VEE to GND)
Operating Temperature (Junction)
Storage Temperature Range
ESD (Human Body Model)
+10.5 V
−5.5 V
+150°C
−65°C to +150°C
1500 V
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 8 of 16
ADATE205
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VCOM_1
GNDREF_1
VIOH_1
VCOM_2
GNDREF_2
VIOH_2
PIN 1
2
3
4
VIOL_1
VIOL_2
5
GND
GND
6
D_INV_1
VIT_1
D_INV_2
VIT_2
7
8
VIL_1
VIL_2
9
VIH_1
VIH_2
ADATE205
TOP VIEW
(Not to Scale)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CLAMPL_1
CLAMPH_1
GND
CLAMPH_2
CLAMPL_2
GND
CLLM_1
LDEN_1
VTEN_1
VEE
CLLM_2
LDEN_2
VTEN_2
VEE
VEE
VEE
VCC
VCC
VCC
VCC
GND
GND
GND
GND
DR_DATA_P_1
DR_DATA_P_T_1
DR_DATA_N_T_1
DR_DATA_N_1
DR_DATA_P_2
DR_DATA_P_T_2
DR_DATA_N_T_2
DR_DATA_N_2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Figure 2. Pin Configuration
Rev. 0 | Page 9 of 16
ADATE205
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
VCOM_1
GNDREF_1
VIOH_1
Description
1
2
3
4
Commutation Reference Voltage.
Reference GND for VIOL, VIOH.
Program Voltage for IOH (Sink).
Program Voltage for IOL (Source).
Device Ground.
VIOL_1
5, 12, 20, 21, 36,
40, 55, 56, 64, 71,
76, 79, 83, 93, 97,
100
GND
6
D_INV_1
VIT_1
Driver Invert.
7
Driver Term Voltage Reference.
Driver Low Voltage Reference.
Driver High Voltage Reference.
Low Clamp.
8
VIL_1
9
VIH_1
10
11
13
14
15
CLAMPL_1
CLAMPH_1
CLLM_1
LDEN_1
VTEN_1
High Clamp.
Comparator Low Leakage Mode.
Determines Whether LD Responds to DR_EN_1 or is Disabled (see Table 4).
Low Speed Control Signal. When high, DR_EN_1 forces driver output to VIT. Otherwise, DR_EN_1
forces driver to High Impedance (see Table 4).
16, 17, 33, 43, 59,
60, 84, 87, 92
VEE
Negative Power Supply.
18 19, 57, 58, 77,
78, 89, 98, 99
VCC
Positive Power Supply.
22
23
DR_DATA_P_1
High Speed Data Inputs. Sets high/low state of driver output (see Table 4).
DR_DATA_P_T_1 Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the
appropriate signal.
24
DR_DATA_N_T_1 Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the
appropriate signal.
25
26
DR_DATA_N_1
DR_EN_P_1
Complement of DR_DATA_P_1.
High Speed Enable Inputs. Multifunction depending on status of VTEN_1 and LDEN_1. Causes driver
to enter/leave inhibit; driver to enter/leave termination mode; load to leave/enter inhibit (see
Table 4).
27
28
DR_EN_P_T_1
DR_EN_N_T_1
Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the
appropriate signal.
Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the
appropriate signal.
29
DR_EN_N_1
NC
Complement of DR_EN_P_1.
No Connect.
30, 46
31
COMP_H_P_1
COMP_H_N_1
COMP_L_P_1
COMP_L_N_1
SLEW1, SLEW0
High Comparator Outputs.
Complement of COMP_H_P_1.
Low Comparator Outputs.
Complement of COMP_L_P_1.
32
34
35
37, 39
Logic Signals Controlling Driver Slew Rates for Both Drivers. 00 codes for maximum slew voltage; 11
codes for minimum slew voltage.
38
41
42
44
45
CMOS_VDD
CMOS Supply ( Internal ÷ 2 = Single-Ended Logic Reference).
Complement of COMP_L_P_1.
COMP_L_N_2
COMP_L_P_2
COMP_H_N_2
COMP_H_P_2
Low Comparator Outputs.
Complement of COMP_H_P_1.
High Comparator Outputs.
Rev. 0 | Page 10 of 16
ADATE205
Pin No.
47
Mnemonic
Description
DR_EN_N_2
DR_EN_N_T_2
DR_EN_P_T_2
Complement of DR_EN_P_2.
Complement of DR_EN_N_T_2.
48
49
Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the
appropriate signal.
50
DR_EN_P_2
High Speed Enable Inputs. Multifunction depending on status of VTEN_2 and LDEN_2. Causes driver
to enter/leave inhibit; driver to enter/leave termination mode; load to leave/enter inhibit (see
Table 4).
51
52
53
DR_DATA_N_2
Complement of DR_DATA_P_2.
DR_DATA_N_T_2 Complement of DR_DATA_P_T_2.
DR_DATA_P_T_2 Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the
appropriate signal.
54
61
DR_DATA_P_2
VTEN_2
High Speed Data Inputs. Sets high/low state of driver output (see Table 4).
Low Speed Control Signal. When high, DR_EN_2 forces driver output to VT; otherwise, DR_EN_2
forces driver to high impedance (see Table 4).
62
63
LDEN_2
CLLM_2
Determines Whether LD Responds to DR_EN_2 or is Disabled (see Table 4).
Comp Low Leakage Mode.
65
66
67
68
69
CLAMPL_2
CLAMPH_2
VIH_2
Low Clamp.
High Clamp.
Driver High Voltage Reference.
Driver Low Voltage Reference.
Driver Term Voltage Reference.
VIL_2
VIT_2
70
D_INV_2
VIOL_2
Driver Invert.
72
Program Voltage for IOL (Source).
Program Voltage for IOH (Sink).
Reference GND for VIOL, VIOH.
Commutation Reference Voltage.
Device Ground or Pin Shield.
Output/Input Pin.
73
VIOH_2
GNDREF_2
VCOM_2
GND/SHIELDS
DUT_2
74
75
80, 82, 94, 96
81
85
86
88
90
91
95
CVH_2
Window High Reference Level.
Window Low Reference Level.
Temperature Sense, Five Diode String, Reference to GND.
Window Low Reference Level.
Window High Reference Level.
Output/Input pin.
CVL_2
TEMP
CVL_1
CVH_1
DUT_1
Rev. 0 | Page 11 of 16
ADATE205
TYPICAL PERFORMACE CHARACTERISTICS
2400
5
4
DRIVER = VIH
VIH = 5V
2200
2000
3
2
VIL = 0V
1800
TERMINATION = 50Ω
1600
1
1400
0
VIH = 3V
1200
–1
–2
–3
–4
–5
–6
1000
800
600
400
VIH = 1V
200
0
0
2
4
6
8
10
12
14
16
18
–2
–1
0
1
2
3
4
5
6
7
7
7
2ns/DIV
V
(V)
DUT
Figure 3. Driver Large Signal Response
Figure 6. Driver VIH Linearity vs. Output
240
220
6
5
DRIVER = VIL
VIH = 500mV
200
180
160
140
120
100
4
3
VIL = 0V
TERMINATION = 50Ω
2
1
0
–1
–2
–3
–4
–5
80
60
40
20
0
VIH = 200mV
VIH = 100mV
0
2
4
6
8
10
12
14
16
18
–2
–1
0
1
2
3
4
5
6
2ns/DIV
V
(V)
DUT
Figure 4. Driver Small Signal Response
Figure 7. Driver VIL Linearity vs. Output
10
0
8
6
4
TRAILING FALL EDGE
DRIVER = VTERM
–10
–20
–30
–40
–50
TRAILING RISE EDGE
2
0
–2
–4
–6
–8
–60
–70
–80
–90
–100
2.5
5.0
7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0
2.5ns/DIV
–2
–1
0
1
2
3
4
5
6
V
(V)
DUT
Figure 5. Driver Trailing Edge Timing Error vs. Pulse Width
Figure 8. Driver VTERM Linearity vs. Output
Rev. 0 | Page 12 of 16
ADATE205
1.0004
1.0003
1.0002
1.0001
1.0000
0.9999
0.9998
0.9997
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.9996
0.9995
60
70
80
90
100
110
–2
–1
0
1
2
3
4
5
6
7
TEMPERATURE (°C)
COMMON-MODE VOLTAGE (V)
Figure 9. Driver Gain vs. Temperature
Figure 12. Comparator Offset vs. Common-Mode Voltage
2.0
1.5
1100
1050
1000
950
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
1.0
0.5
0
–0.5
–1.0
–1.5
V
= 0V TO 1V
IN
<50ps
20% TO 80% RISE TIME
DRIVER IN VTERM = 0V
0
–50
–100
60
70
80
90
100
110
TEMPERATURE (°C)
500ps/DIV
Figure 13. Comparator Schmoo at 1 ns Rise and Fall Time
Figure 10. Driver Offset vs. Temperature
240
1100
1050
1000
950
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
V
= 0V TO 1V
IN
220
200
180
160
140
120
100
80
<50ps
20% TO 80% RISE TIME
DRIVER IN VTERM = 0V
60
40
0
–50
–100
20
0
2
4
6
8
10
12
14
16
18
20
tBASE (2ns/DIV)
500ps/DIV
Figure 11. Comparator Differential Output Response
Figure 14. Comparator Schmoo at 600 ps Rise and Fall Time
Rev. 0 | Page 13 of 16
ADATE205
32.0
30.0
18
16
V
= 0V
COM
IOL = 0V
= 2V
27.5
25.0
22.0
20.0
17.5
V
DUT
14
12
10
8
15.0
12.5
10.0
7.5
5.0
2.5
0
6
4
2
0
–2
–4
–3.0
1
2
3
4
5
6
7
8
9
10
0
5
10
15
20
25
30
35
1ns/DIV
IOL (mA)
Figure 15. Comparator tPD vs. Pulse Width
Figure 17. Active Load Linearity vs. IOH
40
30
14
12
V
= 2V
COM
IOH = 0V
= 0V
V
= 1V
COM
IOH = IOL = 35mA
V
DUT
10
8
20
10
6
0
4
2
–10
–20
–30
–40
0
–2
–4
–6
–2
–1
0
1
2
3
4
5
6
7
0
5
10
15
20
25
30
35
V
(V)
IOL (mA)
DUT
Figure 18. Active Load Linearity vs. IOL
Figure 16. Active Load Commutation Region
Rev. 0 | Page 14 of 16
ADATE205
THEORY OF OPERATION
The ADATE205 has two general classes of logic inputs:
differential inputs for controlling functions that generally need
to be operated at high speed, and single-ended CMOS inputs
for setting operating modes or other low speed functions. The
differential inputs have a wide common-mode range that allows
them to be used with a variety of logic families. The differential
inputs can also be used single-ended, with one input from each
pair of inputs tied to a fixed reference, but this makes precise
timing more difficult to achieve.
These differential input pins provide 50 Ω input termination
resistors for use as desired. The single-ended inputs have an
input range compatible with most logic families and are high
impedance to make driving them very easy. The switching
threshold for the single-ended inputs is preset to one-half of the
voltage at the CMOS_VDD pin.
Table 4. Driver and Load Modes
LDEN
(CMOS Single-Ended)
VTEN
(CMOS Single-Ended)
DR_EN
(High Speed Differential)
DR_DATA
(High Speed Differential)
Driver
Status
Load
Status
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
0
1
1
0
1
1
X
0
1
X
0
1
X
0
1
High-Z
VIL
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
ON
VIH
VIT
VIL
VIH
High-Z
VIL
High-Z
High-Z
VIH
Table 5. Comparator Low Leakage Mode
CLLM (CMOS Single-Ended)
Typical DUT Pin Bias Current
0
1
1 μA
10 nA
Table 6. Rise/Fall Time Selection 3 V, 10% to 90%, Unterminated
Slew 1
Slew 0
Tr/Tf (ns)
0
0
1
1
0
1
0
1
1.4
1.9
2.8
5.6
Table 7. Comparator Logic Function
Output States
DUT Pin Voltage
COMP_L_P
COMP_L_N
COMP_H_P
COMP_H_N
>CVL
>CVL
<CVL
<CVL
>CVH
1
1
0
0
0
0
1
1
1
0
1
0
0
1
0
1
<CVH
>CVH
<CVH
Rev. 0 | Page 15 of 16
ADATE205
OUTLINE DIMENSIONS
16.00 BSC SQ
1.20
MAX
0.75
0.60
0.45
14.00 BSC SQ
100
1
76
75
76
75
100
1
PIN 1
TOP VIEW
(PINS DOWN)
BOTTOM
VIEW
(PINS UP)
EXPOSED
PAD
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
50
51
25
25
26
49
50
26
3.5°
0°
6.50
SQ
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
VIEW A
0.15
0.05
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
Figure 19. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADATE205BSV
−40°C to +85°C
100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
SV-100-2
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05737-0-1/06(0)
Rev. 0 | Page 16 of 16
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