ADATE305BSVZ_技术文档

250 MHz Dual Integrated DCL with Level

Setting DACs, Per Pin PMU, and Per Chip VHH

ADATE305

FEATURES

GENERAL DESCRIPTION

Driver

The ADATE305 is a complete, single-chip solution that performs

3-level driver with high-Z mode and built-in clamps

Precision trimmed output resistance

Low leakage mode (typically <10 nA)

Voltage range: up to −2.0 V to +6.0 V

1.6 ns minimum pulse width, 2 V terminated

2.1 ns minimum pulse width, 3 V terminated

Comparator

Window and differential comparator

500 MHz input equivalent bandwidth

Load

the pin electronic functions of the driver, the comparator, and

the active load (DCL), per pin PMU, and dc levels for ATE appli-

cations. The device also contains an HVOUT driver with a VHH

buffer capable of generating up to 13.5 V.

The driver features three active states: data high mode, data low

mode, and term mode, as well as an inhibit state. The inhibit

state, in conjunction with the integrated dynamic clamp, facili-

tates the implementation of a high speed active termination.

The ADATE305 supports two output voltage ranges: −2.0 V

to +6.0 V and −1.5 V to +6.0 V by adjusting the positive and

negative supply voltages.

12 mA maximum current capability

Per pin PMU

The ADATE305 can be used as either a dual single-ended drive/

receive channel or a single differential drive/receive channel.

Each channel of the ADATE305 features a high speed window

comparator per pin for functional testing, as well as a per pin

PMU with FV, or FI and MV, or MI functions. All necessary dc

levels for DCL functions are generated by on-chip 14-bit DACs.

The per pin PMU features an on-chip 16-bit DAC for high

accuracy and contains integrated range resistors to minimize

external component counts.

Force voltage range: up to −2.0 V to +6.0 V

5 current ranges: 32 mA, 2 mA, 200 μA, 20 μA, 2 μA

Levels

14-bit DAC for DCL levels

Typically < 5 mV INL (calibrated)

16-bit DAC for PMU levels

Typically < 1.5 mV INL (calibrated) linearity in FV mode

HVOUT output buffer

0 V to 13.5 V output range

100-lead, 14 mm × 14 mm, TQFP_EP package

900 mW per channel with no load

The ADATE305 uses a serial bus to program all functional blocks

and has an on-board temperature sensor for monitoring the

device temperature.

APPLICATIONS

Automatic test equipment

Semiconductor test systems

Board test systems

Instrumentation and characterization equipment

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADATE305

TABLE OF CONTENTS

Features .............................................................................................. 1

Absolute Maximum Ratings ......................................................... 19

Thermal Resistance.................................................................... 19

Explanation of Test Levels......................................................... 19

ESD Caution................................................................................ 19

Pin Configuration and Function Descriptions........................... 20

Typical Performance Characteristics ........................................... 23

SPI Details ....................................................................................... 34

Definition of SPI Word.............................................................. 35

Write Operation.......................................................................... 36

Read Operation........................................................................... 37

Reset Operation.......................................................................... 38

Register Map ................................................................................... 39

Details of Registers......................................................................... 40

User Information............................................................................ 42

Details of DACs vs. Levels......................................................... 43

Recommended PMU Mode Switching Sequences................. 46

Block Diagrams............................................................................... 49

Outline Dimensions....................................................................... 53

Ordering Guide .......................................................................... 53

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Total Function............................................................................... 4

Driver ............................................................................................. 5

Reflection Clamp.......................................................................... 7

Normal Window Comparator .................................................... 7

Differential Comparator.............................................................. 9

Active Load.................................................................................. 11

PMU............................................................................................. 12

External Sense (PMUS_CHx)................................................... 16

DUTGND Input ......................................................................... 16

Serial Peripheral Interface......................................................... 17

HVOUT Driver........................................................................... 17

Overvoltage Detector (OVD) ................................................... 18

16-Bit DAC Monitor MUX ....................................................... 18

REVISION HISTORY

8/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 56

ADATE305

FUNCTIONAL BLOCK DIAGRAM

CH1

PMU_FLAG

PMU

16-BIT DAC

*

MUX

DAC16_MON

*

OVD

OVD_CH0

MUX

MEASOUT01

PMUS_CH0

CH1

VCLAMPH

VCLAMPL

VH

VT

VL

R

OUT

(TRIMMED)

DATA0P

100Ω

DRV

DUT0

DATA0N

RCV0P

*

100Ω

WINDOW

DIFF.

C

RCV0N

OTHER CHANNEL

DUT1

*

COMP_VTT0

VHH

HVOUT

50Ω

COMP_QH0P

COMP_QH0N

C

VOH

VOL

COMP_QL0P

COMP_QL0N

*

G

IOL

ADATE305

SDIN

*

RST

SCLK

CS

VCOM

*

14-BIT DAC

SPI

TEMPERATURE

SENSOR

TEMPSENSE

IOH

SDOUT

*

ONE PER DEVICE.

Figure 1. One of Two Channels Is Shown

Rev. 0 | Page 3 of 56

ADATE305

SPECIFICATIONS

Characterization and production tests performed using Power Supply Range 1 (see Table 36). V_DD= +10.0 V, V_CC= +3.3 V, V_SS= −5.25 V,

V_PLUS= +16.75 V, V_{COMP_VTT}= +3.3 V, V_REF= +5.0 V, V_{REF_GND}= 0.0 V. All default test conditions are as defined in Table 38. All specified

values are at T_J= 70°C, where T_Jcorresponds to the internal temperature sensor, unless otherwise noted. Temperature coefficients are

measured at T_J= 70°C 20°C, unless otherwise noted. Typical values are based on design, simulation analyses, and/or limited bench

evaluations. Typical values are not tested or guaranteed. Test levels are specified in the Explanation of Test Levels section.

TOTAL FUNCTION

Table 1.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

TOTAL FUNCTION

Output Leakage Current

PE Disable Range E

−20.0 5.3

5.3

+20.0 nA

nA

P

−1.5 V < V_DUTx< +6.0 V; PMU and PE disabled via SPI; PMU

Range E, VCH = 7.0 V, VCL = −2.5 V

PE Disable Range A, B, C, D

High-Z Mode

C_T

−1.5 V < V_DUTx< +6.0 V; PMU and PE disabled via SPI; PMU

Range A, PMU Range B, PMU Range C, and PMU Range D,

VCH = +7.0 V, VCL = −2.5 V

−1.5 V < V_DUTx< +6.0 V; PMU disabled and PE enabled via SPI;

RCV active, VCH = +7.0 V, VCL = −2.5 V

−400 5.4

+400 nA

pF

P

Output Capacitance

DUT Pin Range

4

S

D

VTERM mode operation

−1.5

+6.0

V

POWER SUPPLIES

Total Supply Range, V_PLUSto V_SS

VPLUS Supply, V_PLUS

Positive Supply, V_DD

Negative Supply, V_SS

Logic Supply, V_CC

Comparator Termination, V_{COMP_VTT}

V_PLUSSupply Current, I_PLUS

Logic Supply Current, I_CC

Comparator Termination Current,

I_{COMP_VTT}

22.5

23.25

V

mA

D

P

Defines PSRR conditions

16.25 16.75 17.25

9.5 10.0 10.5

−5.50 −5.25 −5.00

3.1

3.3

−1.0

4.0

1.0

3.3

3.5

5.0

+3.0

17.0

10.0

26.0

+1.3

12.7

2.7

HVOUT disabled

HVOUT enabled, RCV active, no load, VHH = 12 V

Quiescent (SPI is static)

10.0

17

Positive Supply Current, I_DD

Negative Supply Current, I_SS

Total Power Dissipation

Positive Supply Current, I_DD

Negative Supply Current, I_SS

Total Power Dissipation

72

92

105

135

1.9

154

183

2.5

mA

W

mA

W

P

Load power down (IOH = IOL = 0 mA)

Load active off (IOH = IOL = 12 mA)

100

1.0

102

130

1.8

119

1.7

133

158

2.2

TEMPERATURE MONITORS

Temperature Sensor Gain

Temperature Sensor Accuracy

Without Calibration over

25°C to 100°C

10

6

mV/K C_T

°C

C_T

Temperature voltage available on Pin 3 at all times and Pin 28

when selected (see Table 24 and Table 36)

VREF INPUT

Reference Input Voltage Range for

DACs (VREF Pin)

Input Bias Current

4.95

5

5.05

100

V

D

P

Referenced to V_{REF_GND}; not referenced to V_DUTGND

Tested with 5 V applied

0.1

μA

Rev. 0 | Page 4 of 56

ADATE305

DRIVER

VH − VL ≥ 200 mV (to meet dc/ac specifications).

Table 2.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

DC SPECIFICATIONS

High-Speed Differential Logic

Input Characteristics (DATA, RCV)

Input Termination Resistance

92

100

108

Ω

P

Push 6 mA into xP pins, force 1.3 V on xN pins; measure voltage

from xP to xN, calculate resistance (ΔV/ΔI)¹

Input Voltage Differential

Common-Mode Voltage

Input Bias Current

0.2

0.85

−20.0 +2.2

1.0

2.35

+20.0 μA

V

P_F

P

Each pin tested at 2.85 V and 0.35 V, while the other high speed

pin remains open

Pin Output Characteristics

Output High Range, VH

Output Low Range, VL

Output Term Range, VT

−1.4

−1.5

+6.0

+5.9

+6.0

V

D

Functional Amplitude (VH − VL) 0.0

7.5

Amplitude can be programmed to VH = VL, accuracy specs

apply when VH − VL ≥ 200 mV

DC Output Current Limit

Source

75

100

120

mA

P

Driver high, VH = 6.0 V, short DUTx pin to −2.0 V, measure current

DC Output Current Limit Sink

Output Resistance, 50 mA

−120 −100 −75

mA

Ω

P

Driver low, VL = −1.5 V, short DUTx pin to 6.0 V, measure current

Source: driver high, VH = 3.0 V, I_DUTx= 1 mA and 50 mA;

sink: driver low, VL = 0.0 V, I_DUTx= −1 mA and −50 mA; ΔV_DUT/ΔI_DUT

45.0

47.0

49.0

ABSOLUTE ACCURACY

VH tests done with VL = −2.5 V and VT= −2.5 V;

VL tests done with VH = 7.5 V and VT = 7.5 V;

VT tests done with VL = −2.5 V and VH = +7.5 V; unless otherwise

specified

VH, VL, VT Uncalibrated Accuracy

VH, VL, VT Offset Tempco

VH, VL, VT DNL

−250

−10

75

450

1

2.5

+250 mV

P

Error measured at calibration points of 0 V and 5 V

Measured at calibration points

After two-point gain/offset calibration

After two-point gain/offset calibration; measured over driver

output ranges

After two-point gain/offset calibration; range/number of DAC

bits as measured at calibration points of 0 V and 5 V

μV/°C C_T

mV

C_T

P

VH, VL, VT INL

+10

+1

VH, VL, VT Resolution

DUTGND Voltage Accuracy

VH, VL, VT Crosstalk

0.6

mV

P_F

P

−7

1.3

2

+7

Over 0.1 V range; measured at end points of VH, VL, and VT

functional range

C_T

VL = −1.5 V: VH = −1.4 V → 6.0 V, VT = −1.5 V → 6.0 V;

VH = 6.0 V: VL = −1.5 V → 5.9 V, VT = −1.5 V → 6.0 V;

VT = 1.5 V: VL = −1.5 V → 5.9 V, VH = −1.4 V → 6.0 V; dc crosstalk

on VL, VH, VT output level when other driver DACs are varied

Overall Voltage Accuracy

10

15

mV

C_T

Sum of INL, crosstalk, DUTGND, and tempco over 5°C, after

gain/offset calibration

Measured at calibration points

VH, VL, VT DC PSRR

AC SPECIFICATIONS

mV/V C_T

Rise/Fall Times

Toggle DATAxx

0.2 V Programmed Swing

1.0 V Programmed Swing

2.0 V Programmed Swing

3.0 V Programmed Swing

5.0 V Programmed Swing

Rise to Fall Matching

1000

800

950

1175 1500

1650

2350

ps

C_B

P/C_B

C_B

VH = 0.2 V, VL = 0.0 V, terminated; 20% to 80%

VH = 1.0 V, VL = 0.0 V, terminated; 20% to 80%

VH = 2.0 V, VL = 0.0 V, terminated; 20% to 80%

VH = 3.0 V, VL = 0.0 V, terminated; 20% to 80%

VH = 3.0 V, VL = 0.0 V, unterminated; 10% to 90%

VH = 5.0V, VL = 0.0 V, unterminated; 10% to 90%

VH = 3.0 V, VL = 0.0 V, terminated; rise to fall within one channel

1000

C_B

30

Rev. 0 | Page 5 of 56

ADATE305

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

Minimum Pulse Width

1.0 V Programmed Swing

Toggle DATAxx

VH = 1.0 V, VL = 0.0 V, terminated; timing error 75 ps

VH = 1.0 V, VL = 0.0 V, terminated; less than 10% amplitude

degradation

1.4

1.6

ns

C_B

2.0 V Programmed Swing

3.0 V Programmed Swing

1.6

1.8

ns

C_B

VH = 2.0 V, VL = 0.0 V, terminated; timing error 75 ps

VH = 2.0 V, VL = 0.0 V, terminated; less than 10% amplitude

degradation

VH = 3.0 V, VL = 0.0 V, terminated; timing error 75 ps

VH = 3.0 V, VL = 0.0 V, terminated; less than 10% amplitude

degradation

2.1

2.3

ns

C_B

Maximum Toggle Rate

2.0 V Programmed Swing

3.0 V Programmed Swing

Dynamic Performance, Drive

(VH to VL and VL to VH)

250

200

MHz

C_B

VH = 2.0 V, VH = 0.0 V, terminated, 10% amplitude degradation

VH = 3.0 V, VH = 0.0 V, terminated, 10% amplitude degradation

Toggle DATAxx

Propagation Delay Time

Propagation Delay Tempco

Delay Matching

Edge to Edge

Channel to Channel

Delay Change vs. Duty Cycle

Overshoot and Undershoot

Settling Time (VH to VL)

To Within 3% of Final Value

To Within 1% of Final Value

Dynamic Performance, VT

(VH or VL to VT and VT to VH

or VL)

3.0

ns

C_B

VH = 3.0 V, VL = 0.0 V, terminated

Rising vs. falling

Rising vs. rising, falling vs. falling

VH = 3.0 V, VL = 0.0 V, terminated; 5% to 95% duty cycle; 1 MHz

VH = 3.0 V, VL = 0.0 V, terminated

Toggle DATAxx

ps/°C C_T

115

30

ps

mV

C_B

20

5

35

ns

C_B

VH = 3.0 V, VL = 0.0 V, terminated

Toggle RCVx

Propagation Delay Time

Delay Matching, Edge to Edge

Propagation Delay Tempco

3.3

100

4.0

ns

ps

C_B

VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated

VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; rising vs. falling

VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated

ps/°C C_T

Transition Time, Active to VT

and VT to Active

0.85

ns

C_B

VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; 20% to 80%

Dynamic Performance,

Inhibit (VH or VL to/from

Inhibit)

Toggle RCVx

Propagation Delay Time

Active to Inhibit

Inhibit to Active

Transition Time

Active to Inhibit

Inhibit to Active

I/O Spike

VH = +1.0 V, VL = −1.0 V, terminated

4.5

6.9

ns

C_B

VH =+1.0 V, VL = −1.0 V, terminated; 20% to 80%

VH = 0.0 V, VL = 0.0 V, terminated

2.6

0.75

190

ns

mV

C_B

¹The xP pins include DATA0P, DATA1P, RCV0P, and RCV1P; the xN pins include DATA0N, DATA1N, RCV0N, and RCV1N. For example, push 6 mA into the DATA0P pin,

force 1.3 V into DATA0N, and measure the voltage from DATA0P to DATA0N.

Rev. 0 | Page 6 of 56

ADATE305

REFLECTION CLAMP

Clamp accuracy specifications apply when VCH > VCL.

Table 3.

Test

Parameter

VCH

Min

Typ

Max

Unit

Level Conditions/Comments

Range

−1.0

+6.0

V

D

Uncalibrated Accuracy

−200

50

+200

mV

P

Driver high-Z, sinking 1 mA; VCH error measured at the

calibration points of 0.0 V and 5.0 V

Resolution

0.6

0.75

mV

P_F

Driver high-Z, sinking 1 mA; after two-point gain/offset

calibration; range/number of DAC bits as measured at

the calibration points of 0.0 V and 5.0 V

DNL

INL

1

2

mV

C_T

P

Driver high-Z, sinking 1 mA; after two-point gain/offset

calibration

Driver high-Z, sinking 1 mA; after two-point gain/offset

calibration; measured over VCH range of −1.0 V to +6.0 V

−40

+40

mV

Tempco

−0.3

mV/°C

C_T

Measured at calibration points

VCL

Range

Uncalibrated Accuracy

−1.5

−200

+5.0

+200

V

mV

D

P

50

Driver high-Z, sourcing 1 mA; VCL error measured at the

calibration points of 0.0 V and 5.0 V

Resolution

0.6

0.75

mV

P_F

Driver high-Z, sourcing 1 mA; after two-point gain/offset

calibration; range/number of DAC bits as measured at

the calibration points of 0.0 V and 5.0 V

DNL

INL

1

2

mV

C_T

P

Driver high-Z, sourcing 1 mA; after two-point gain/offset

calibration

Driver high-Z, sourcing 1 mA; after two-point gain/offset

calibration; measured over VCL range of −1.5 V to +5 V

−40

+40

mV

Tempco

0.5

mV/°C

C_T

Measured at calibration points

DC CLAMP CURRENT LIMIT

VCH

VCL

−120

60

−85

85

1

−60

120

+7

mA

mV

P

Driver high-Z, VCH = 0 V, VCL = −1.5 V, V_DUTx= +5 V

Driver high-Z, VCH = 6.0 V, VCL= 5.0 V, V_DUTx= 0.0 V

DUTGND VOLTAGE ACCURACY

−7

Over 0.1 V range; measured at the end points of VCH

and VCL functional range

NORMAL WINDOW COMPARATOR

VOH tests done with VOL = −1.5 V; VOL tests done with VOH = 6.0 V, unless otherwise specified.

Table 4.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

DC SPECIFICATIONS

Input Voltage Range

Differential Voltage Range

−1.5

0.1

+6.0

7.5

V

D

Comparator Input Offset Vol-

tage Accuracy, Uncalibrated

−150

30

+150

mV

P

Offset measured at the calibration

points of 0.0 V and 5.0 V

Comparator Threshold

Resolution

0.6

1

mV

P_F

After two-point gain/offset calibration;

range/number of DAC bits as measured

at the calibration points of 0 V and 5 V

Comparator Threshold DNL

Comparator Threshold INL

1

1.3

mV

C_T

P

After two-point gain/offset calibration

−7

+7

After two-point gain/offset calibration;

measured over VOH, VOL range of

−1.5 V to +6.0 V

Comparator Input Offset

Voltage Tempco

DUTGND Voltage Accuracy

100

0.5

ꢀV/°C C_T

mV

Measured at calibration points

+7

P

Over 0.1 V range; measured at end

points of VOH and VOL functional range

Rev. 0 | Page 7 of 56

ADATE305

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

Comparator Uncertainty Range

6.0

mV

C_B

V_DUTx= 0 V, sweep comparator

threshold to determine uncertainty

region

DC Hysteresis

DC PSRR

0.5

5

mV

mV/V C_T

C_B

V_DUTx= 0 V

Measured at calibration points

Digital Output Characteristics

Internal Pull-Up Resistance

to Comparator, COMP_VTT

40

50

60

Ω

P

Pull 1 mA and 10 mA from Logic 1 leg

and measure ΔV to calculate resis-

tance; measured ΔV/9 mA; done for

both comparator logic states

V_{COMP_VTT}Range

Common-Mode Voltage

3.3

5.0

V

D

C_T

V_{COMP_VTT}− 1.88

Measured with 100 Ω differential

termination

V_{COMP_VTT}− 2.075

V_{COMP_VTT}− 1.675

V

P

Measured with no external termination

Differential Voltage

250

mV

C_T

Measured with 100 Ω differential

termination

400

500

450

600

mV

ps

P

C_B

Measured with no external termination

Measured with each comparator leg

terminated 50 Ω to GND

Rise/Fall Time, 20% to 80%

AC SPECIFICATIONS

Input transition time = 800 ps, 10% to

90%; measured with each comparator

leg terminated 50 Ω to GND; unless

otherwise specified

Propagation Delay, Input to

Output

1.75

5

ns

C_B

V_DUTx= 0 V to 1.5 V swing, Driver

VTERM mode, VT = 0.0 V; high-side

measurement: VOH = 0.75 V, VOL =

−1.5 V; low-side measurement: VOH =

6.0 V, VOL = 0.75 V

V_DUTx= 0 V to 1.5 V swing, Driver

VTERM mode, VT = 0.0 V; high-side

measurement: VOH = 0.75 V, VOL =

−1.5 V; low-side measurement: VOH =

6.0 V, VOL = 0.75 V

V_DUTx= 0 V to 1.5 V swing, Driver

VTERM mode, VT = 0.0 V; high-side

measurement: VOH = 0.75 V, VOL =

−1.5 V; low-side measurement: VOH =

6.0 V, VOL = 0.75 V

Propagation Delay Tempco

Propagation Delay Matching

ps/°C C_T

High Transition to Low

Transition

High to Low Comparator

200

50

ps

C_B

Propagation Delay Change

(with Respect To)

Slew Rate, 800 ps, 1 ns, 1.2 ns,

and 2.2 ns (10% to 90%)

50

75

ps

C_B

V_DUTx= 0 V to 1.5 V swing, Driver

VTERM mode, VT = 0.0 V; high-side

measurement: VOH = 0.75 V, VOL =

−1.5 V; low-side measurement: VOH =

6.0 V, VOL = 0.75 V

For 250 mV: V_DUTx= 0 V to 0.5 V swing;

for 1.5 V: V_DUTx= 0 V to 1.75 V swing;

Driver VTERM mode, VT = 0.0 V; high-

side measurement: VOH = 0.25 V,

VOL = −1.5 V; low-side measurement:

VOH = 6.0 V, VOL = 0.25 V

Overdrive, 250 mV and 1.5 V

Pulse Width, Sweep 1.6 ns to

10 ns

75

ps

C_B

V_DUTx= 0 V to 1.5 V swing @ 32.0 MHz,

Driver VTERM mode, VT = 0.0 V; high-

side measurement: VOH = 0.5 V, VOL =

−1.5 V; low-side measurement: VOH =

6.0 V, VOL = 0.5 V

Rev. 0 | Page 8 of 56

ADATE305

Test

Level Conditions/Comments

Parameter

Duty Cycle, 5% to 95%

Min

Typ

Max

Unit

50

ps

C_B

V_DUTx= 0 V to 1.5 V swing @ 1.0 MHz,

Driver VTERM mode, VT =0.0 V; high-

side measurement: VOH = 0.75 V, VOL =

−1.5 V; low-side measurement: VOH =

6.0 V, VOL = 0.75 V

Minimum Pulse Width

2.0

ns

C_B

V_DUTx= 0 V to 1.5 V swing, Driver

VTERM mode, VT = 0.0 V; less than

12% amplitude degradation measured

by shmoo

Input Equivalent Bandwidth,

Terminated

500

2.5

MHz

ns

C_B

V_DUTx= 0 V to 1.5 V swing, Driver

VTERM mode, VT = 0.0 V; as measured

by shmoo

V_DUTx= 0 V to 3.0 V swing, driver high-Z;

as measured by shmoo; input transition

time of ~2000 ps, 10% to 90%

ERT High-Z Mode, 3 V, 20%

to 80%

DIFFERENTIAL COMPARATOR

VOH tests done with VOL = −1.1 V, VOL tests done with VOH = +1.1 V, unless otherwise specified.

Table 5.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

DC SPECIFICATIONS

Input Voltage Range

Operational Differential Voltage

Range

−1.25

0.05

+4.5

1.1

V

D

Maximum Differential Voltage Range

8

V

D

Comparator Input Offset Voltage

Accuracy, Uncalibrated

VOH, VOL Resolution

−150

−15

35

+150

mV

P/C_T

Offset measured at differential calibration points +1.0 V

and −1.0 V, with common mode = 0.0 V

After two-point gain/offset calibration; range/number of

DAC bits as measured at differential calibration points

+1.0 V and −1.0 V, with common mode = 0.0 V

After two-point gain/offset calibration; common

mode = 0.0 V

After two-point gain/offset calibration; measured over VOH,

VOL range of −1.1 V to +1.1 V, common mode = 0.0 V

0.6

1

mV

P_F

VOH, VOL DNL

VOH, VOL INL

1

mV

C_T

P

2.0

+15

VOH, VOL Offset Voltage Tempco

Comparator Uncertainty Range

200

18

ꢀV/°C C_T

Measured at calibration points

V_DUTx= 0 V, sweep comparator threshold to determine

uncertainty region

mV

C_B

DC Hysteresis

CMRR

0.5

0.15

mV

mV/V

C_B

P

V_DUTx= 0 V

1

Offset measured at common-mode voltage points of

−1.5 V and +4.5 V, with differential voltage = 0.0 V

DC PSRR

1.5

1.7

mV/V C_T

Measured at calibration points

AC SPECIFICATIONS

Input transition time = 800 ps, 10% to 90%, measured

with each comparator leg terminated 50 Ω to GND

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, Driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V,

VOL = 0.0 V; repeat for other DUT channel

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, Driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =

0.0 V; repeat for other DUT channel

Propagation Delay, Input to Output

Propagation Delay Tempco

ns

C_B

5

ps/°C C_T

Propagation Delay Matching

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, Driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =

0.0 V; repeat for other DUT channel

High Transition to Low Transition

High-to-Low Comparator

100

50

ps

C_B

Rev. 0 | Page 9 of 56

ADATE305

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

Propagation Delay Change (with

Respect To)

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, Driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =

0.0 V; repeat for other DUT channel

Slew Rate, 800 ps, 1ns, 1.2ns, and

2.2 ns (10% to 90%)

60

ps

ns

C_B

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, Driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =

0.0 V; repeat for other DUT channel

V_DUT0= 0 V, for 250 mV: V_DUT1= 0 V to 0.5 V swing; for

750 mV: V_DUT1= 0 V to 1.0 V swing, Driver VTERM mode,

VT = 0.0 V; VOH = −0.25 V; repeat for other DUT channel

with comparator threshold = +0.25 V

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing @ 32 MHz, Driver

VTERM mode, VT = 0.0 V; high-side measurement: VOH =

0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V,

VOL = 0.0 V; repeat for other DUT channel

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing @ 1 MHz, Driver

VTERM mode, VT = 0.0 V; high-side measurement: VOH =

0.0 V, VOL = −1.1 V; low-side measurement: VOH = 1.1 V,

VOL = 0.0 V; repeat for other DUT channel

Overdrive, 250 mV and 750 mV

100

75

Pulse Width, Sweep from 1.6 ns to

10 ns

Duty Cycle, 5% to 95%

Minimum Pulse Width

60

2.5

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, Driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =

0.0 V; less than 10% amplitude degradation measured by

shmoo; repeat for other DUT channel

Input Equivalent Bandwidth,

Terminated

400

MHz

C_B

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, Driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V, VOL =

0.0 V; less than 22% amplitude degradation measured by

shmoo; repeat for other DUT channel

Rev. 0 | Page 10 of 56

ADATE305

ACTIVE LOAD

See Table 29 for load control information.

Table 6.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

DC SPECIFICATIONS

Input Characteristics

VCOM Voltage Range

V_DUTRange

Load active on, RCV active, unless otherwise noted

−1.25

−1.5

−200

+5.75

+6.0

+200

V

mV

D

P

VCOM Accuracy, Uncalibrated

30

IOH = IOL = 6 mA, VCOM error measured at the calibration

points of 0.0 V and 5.0 V

VCOM Resolution

0.6

1

mV

P_F

IOH = IOL = 6 mA, after two-point gain/offset calibration;

range/number of DAC bits as measured at the calibration

points of 0.0 V and 5.0 V

VCOM DNL

VCOM INL

1

2

mV

C_T

P

IOH = IOL = 6 mA, after two-point gain/offset calibration

IOH = IOL = 6 mA, after two-point gain/offset calibration;

measured over VCOM range of −1.25 V to +5.75 V

Over 0.1 V range; measured at end points of VCOM functional

range

−7

+7

DUTGND Voltage Accuracy

1

mV

P

Output Characteristics

IOL

Maximum Source Current

Uncalibrated Offset

12

−600.0

mA

D

P

100 +600.0 ꢀA

IOH = 0 mA, VCOM = 1.5 V, V_DUTx= 0.0 V, IOL offset calculated

from the calibration points of 1 mA and 11 mA

Uncalibrated Gain

Resolution

−12

4

+12

2

%

P

IOH = 0 mA, VCOM = 1.5 V, V_DUTx= 0.0 V, IOL gain calculated from

the calibration points of 1 mA and 11 mA

IOH = 0 mA, VCOM = 1.5 V, V_DUTx= 0.0 V, after two-point gain/

offset calibration; range/number of DAC bits as measured at the

calibration points of 1 mA and 11 mA

1.5

ꢀA

P_F

DNL

3.0

20

ꢀA

V

C_T

P

IOH = 0 mA, VCOM = 1.5 V, V_DUTx= 0.0 V, after two-point

gain/offset calibration

IOH = 0 mA, VCOM = 1.5 V, V_DUTx= 0.0 V, after two-point gain/

offset calibration; measured over IOL range of 0 mA to 12 mA

IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOL reference at

V_DUTx= −1.0 V, measure IOL current at V_DUTx= 1.75 V, ensure > 90%

of reference current

INL

−80

+80

0.25

90% Commutation Voltage

P

IOH

Maximum Sink Current

Uncalibrated Offset

12

−600.0

mA

D

P

100 +600.0 ꢀA

IOL = 0 mA, VCOM = 1.5 V, V_DUTx= 3.0 V, IOH offset calculated

from the calibration points of 1 mA and 11 mA

Uncalibrated Gain

Resolution

−12

4

+12

2

%

P

IOL = 0 mA, VCOM = 1.5 V, V_DUTx= 3.0 V, IOH gain calculated from

the calibration points of 1 mA and 11 mA

IOL = 0 mA, VCOM = 1.5 V, V_DUTx= 3.0 V, after two-point

gain/offset calibration; range/number of DAC bits as measured

at the calibration points of 1 mA and 11 mA

1.5

ꢀA

P_F

DNL

3.0

ꢀA

V

C_T

P

IOL = 0 mA, VCOM = 1.5 V, V_DUTx= 3.0 V, after two-point

gain/offset calibration

IOL = 0 mA, VCOM = 1.5 V, V_DUTx= 3.0 V, after two-point gain/

offset calibration; measured over IOH range of 0 mA to 12 mA

IOH = IOL =12 mA, VCOM = 2.0 V, measure IOH reference at

V_DUTx= 5.0 V, measure IOH current at V_DUTx= 2.25 V, ensure >

90% of reference current

INL

−80

20

+80

0.25

90% Commutation Voltage

P

Output Current Tempco

1.5

ꢀA/°C C_T

Measured at calibration points

Rev. 0 | Page 11 of 56

ADATE305

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

AC SPECIFICATIONS

Dynamic Performance

Load active on, unless otherwise noted

Propagation Delay, Load Active

On to Load Active Off;

50%, 90%

7.3

ns

C_B

Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,

VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for

IOH; measured from 50% point of RCVxP − RCVxN to 90% point

of final output, repeat for drive low and high

Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,

VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for

IOH; measured from 50% point of RCVxP − RCVxN to 90% point

of final output, repeat for drive low and high

Propagation Delay, Load Active

Off to Load Active On;

50%, 90%

10.3

ns

Propagation Delay Matching

Load Spike

3.0

190

1.9

ns

C_B

Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,

VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for

IOH; active on vs. active off, repeat for drive low and high

Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 0 mA,

VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for

IOH; repeat for drive low and high

Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,

VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for

IOH; measured at 90% of final value

mV

ns

Settling Time to 90%

PMU

FV = force voltage, MV = measure voltage, FI = force current, MI = measure current, FN = force nothing.

Table 7.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

FORCE VOL TAGE (FV)

Current Range A

Current Range B

Current Range C

Current Range D

Current Range E

32

2

200

20

2

−1.5

mA

ꢀA

V

D

Force Input Voltage Range at

Output for All Ranges

+6.0

Force Voltage Uncalibrated

Accuracy for Range C

Force Voltage Uncalibrated

Accuracy for All Ranges

Force Voltage Offset Tempco

for All Ranges

Force Voltage Gain Tempco

for All Ranges

−100

25

10

2

+100 mV

mV

P

PMU enabled, FV, Range C, PE disabled, error measured at

calibration points of 0.0 V and 5.0 V

PMU enabled, FV, PE disabled, error measured at calibration

points of 0.0 V and 5.0 V; repeat for each PMU current range

Measured at calibration points for each PMU current range

C_T

ꢀV/°C

ppm/°C C_T

Measured at calibration points for each PMU current range

Forced Voltage INL

−7

+7

mV

P

PMU enabled, FV, Range C, PE disabled, after two-point gain/offset

calibration; measured over output range of −1.5 V to +6.0 V

Force Voltage Compliance vs.

Current Load

PMU enabled, FV, PE disabled, force −1.5 V, measure voltage

while PMU sinking zero and full-scale current; measure ∆V;

force 6.0 V, measure voltage while PMU sourcing zero and full-

scale current; measure ∆V; repeat for each PMU current range

Range A

Range B to Range E

4

1

mV

C_T

Rev. 0 | Page 12 of 56

ADATE305

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

Current Limit, Source, and Sink

Range A

108

140

180

%FS

P

PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx

to 6.0 V; source: force 2.5 V, short DUTx to −1.0 V; Range A FS =

32 mA, 108% FS = 35 mA, 180% FS = 58 mA

PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx to

6.0 V; source: force 2.5 V, short DUTx to −1.0 V; repeat for each

PMU current range; example: Range B FS = 2 mA, 120 % FS =

2.4 mA, 180% FS = 3.6 mA

Over 0.1 V range; measured at end points of FV functional

range

Range B to Range E

120

−7

145

1

180

+7

%FS

mV

DUTGND Voltage Accuracy

MEASURE CURRENT (MI)

P

V_DUTxexternally forced to 0.0V, unless otherwise specified, ideal

MEASOUT transfer functions: V_MEASOUT01[V] = (I_MEASOUT01× 5/FSR) +

2.5 + V_DUTGNDI(V_MEASOUT01) [A] = (V_MEASOUT01− V_DUTGND− 2.5) × FSR/5

Measure Current, Pin DUTx

Voltage Range for All Ranges

−1.5

+6.0

V

D

Measure Current Uncalibrated

Accuracy

Range A

Range B

Range C

Range D

Range E

500

ꢀA

C_T

P

PMU enabled, FIMI, Range A, PE disabled, error at calibration

points −25 mA and +25 mA, error = (I(V_MEASOUT01) − I_DUTx

PMU enabled, FIMI, Range B, PE disabled, error at calibration

points −1.6 mA and +1.6 mA, error = (I(V_MEASOUT01) − I_DUTx

PMU enabled, FIMI, PE disabled, error at calibration points of

80% FS, error = (I(V_MEASOUT01)₁− I_DUTx

PMU enabled, FIMI, PE disabled, error at calibration points of

80% FS, error = (I(V_MEASOUT01) − I_DUTx

PMU enabled, FIMI, PE disabled, error at calibration points of

)

−400

3.0

+400 ꢀA

)

2.00

0.30

0.08

ꢀA

C_T

)

80% FS, error = (I(V_MEASOUT01) − I_DUTx

)

Measure Current Offset Tempco

Range A

Range B

Range C

Range D and Range E

2

25

5

ꢀA/°C

C_T

Measured at calibration points

nA/°C

1

Measure Current Gain Error,

Nominal Gain = 1

Range A

2.5

2

%

C_T

P

PMU enabled, FIMI, PE disabled, gain error from calibration

points 80% FS

PMU enabled, FIMI, Range B, PE disabled, gain error from

calibration points 1.6 mA

PMU enabled, FIMI, PE disabled, gain error from calibration

points 80% FS

Range B

−20

+20

Range C to Range E

4

C_T

Measure Current Gain Tempco

Range A

Range B to Range E

Measure Current INL

Range A

Measured at calibration points

300

50

ppm/°C C_T

0.05

%FSR

C_T

PMU enabled, FIMI, Range A, PE disabled, after two-point

gain/offset calibration, measured over FSR output of −32 mA

to +32 mA

Range B

−0.02

−0.01

+0.02 %FSR

%FSR

P

PMU enabled, FIM,I Range B, PE disabled, after two-point gain/

offset calibration measured over FSR output of −2 mA to +2 mA

PMU enabled, FIMI, PE disabled, after two-point gain/offset

calibration; measured over FSR output

PMU enabled, FVMI, Range B, PE disabled, force −1 V and +5 V

into load of 1 mA; measure ∆I reported at MEASOUT01

Over 0.1 V range; measured at end points of MI functional range

Range B to Range E

0.01

2.5

C_T

P

FVMI DUT Pin Voltage Rejection

DUTGND Voltage Accuracy

+0.01 %FSR/V

mV

C_T

Rev. 0 | Page 13 of 56

ADATE305

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

FORCE CURRENT (FI)

V_DUTxexternally forced to 0.0V, unless otherwise specified, ideal

force current transfer function: I_FORCE= (PMUDAC − 2.5) × (FSR/5)

Force Current, DUTx Pin Voltage −1.5

Range for All Ranges

+6.0

V

D

Force Current Uncalibrated

Accuracy

Range A

Range B

Range C

Range D

Range E

−5.0

−400

−40

−4

0.5

40

4

+5.0

mA

P

PMU enabled, FIMI, Range A, PE disabled, error at calibration

points of −25 mA and +25 mA

PMU enabled, FIMI, Range B, PE disabled, error at calibration

points of −1.6 mA and 1.6 mA

PMU enabled, FIMI, Range C, PE disabled, error at calibration

points of 80% FS

PMU enabled, FIMI, Range D, PE disabled, error at calibration

points of 80% FS

+400 ꢀA

+40

+4

ꢀA

0.4

75

−400

+400 nA

PMU enabled, FIMI, Range E, PE disabled, error at calibration

points of 80% FS

Force Current Offset Tempco

Range A

Range B

Range C to Range E

Forced Current Gain Error,

Nominal Gain = 1

1

80

4

ꢀA/°C

C_T

P

Measured at calibration points

PMU enabled, FIMI, PE disabled, gain error from calibration

points of 80% FS

nA/°C

%

−20

4

+20

Forced Current Gain Tempco

Range A

Range B to Range E

Force Current INL

Range A

Measured at calibration points

−500

75

ppm/°C C_T

−0.3

−0.2

0.05

+0.3

%FSR

P

PMU enabled, FIMI, Range A, PE disabled, after two-point

gain/offset calibration; measured over FSR output of −32 mA

to +32 mA

PMU enabled, FIMI, PE disabled, after two-point gain/offset

calibration; measured over FSR output

Range B to Range E

0.015 +0.2

Force Current Compliance vs.

Voltage Load

PMU enabled, FIMV, PE disabled; force positive full-scale

current driving −1.5 V and +6.0 V, measure ∆I @ DUTx pin;

force negative full-scale current driving −1.5 V and +6.0 V,

measure ∆I @ DUTx pin

Range A to Range D

Range E

−0.6

−1.0

0.06

0.1

+0.6

+1.0

%FSR

P

MEASURE VOLTAGE

Measure Voltage Range

Measure Voltage Uncalibrated

Accuracy

−1.5

−25

+6.0

+25

V

mV

D

P

2.0

PMU enabled, FVMV, Range B, PE disabled, error at calibration

points 0 V and 5 V, error = (V_MEASOUT01− V_DUTx

)

Measure Voltage Offset Tempco

Measure Voltage Gain Error

10

0.01

ꢀV/°C

%

C_T

P

Measured at calibration points

PMU enabled, FVMV, Range B, PE disabled, gain error from

calibration points 0 V and 5 V

−2

+2

Measure Voltage Gain Tempco

Measure Voltage INL

25

1

ppm/°C C_T

Measured at calibration points

−7

+7

mV

P

PMU enabled, FVMV, Range B, PE disabled, after two-point

gain/offset calibration; measured over output range of −1.5 V

to +6.0 V

Rejection of Measure V vs. I_DUTx

−1.5

0.1

+1.5

mV

P

PMU enabled, FVMV, Range D, PE disabled, force 0 V into load

of −10 ꢀA and +10 ꢀA; measure ∆V reported at MEASOUT01

MEASOUT01 DC CHARACTERISTICS

MEASOUT01 Voltage Range

DC Output Current

MEASOUT01 Pin Output

Impedance

−1.5

+6.0

4

200

V

mA

Ω

D

P

25

PMU enabled, FVMV, PE disabled; source resistance: PMU force

6.0 V and load with 0 mA and 4 mA; sink resistance: PMU force

−1.5 V and load with 0 mA and −4 mA; resistance = ∆V/∆I at

MEASOUT01 pin

Output Leakage Current when

Tristated

−1

+1

ꢀA

P

Tested at −1.5 V and +6.0 V

Rev. 0 | Page 14 of 56

ADATE305

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

Output Short-Circuit Current

−25

+25

mA

P

PMU enabled, FVMV, PE disabled; source: PMU force +6.0 V,

short MEASOUT01 to −1.5 V; sink: PMU force −1.5 V, short

MEASOUT01 to +6.0 V

VOLTAGE CLAMPS

Low Clamp Range (VCL)

High Clamp Range (VCH)

Positive Clamp Voltage Droop

−1.5

0.0

−300 +10

+4.0

6.0

V

D

P

+300 mV

+250 mV

PMU enabled, FIMI, Range A, PE disabled, PMU clamps

enabled, VCH = 5 V,VCL = −1 V, PMU force 2 mA and 32 mA

into open; ∆V seen at DUTx pin

PMU enabled, FIMI, Range A, PE disabled, PMU clamps

enabled, VCH = 5 V,VCL = −1 V, PMU force −2 mA and −32 mA

into open; ∆V seen at DUTx pin

PMU enabled, FIMI, Range B, PE disabled, PMU clamps enabled,

PMU force 1 mA into open; VCH errors at calibration points 0 V

and 5 V; VCL errors at the calibration points 0 V and 4 V

PMU enabled, FIMI, Range B, PE disabled, PMU clamps enabled,

PMU force 1 mA into open; after two-point gain/offset

calibration; measured over PMU clamp range

Negative Clamp Voltage Droop

Uncalibrated Accuracy

INL

−300 −10

P

−250

−70

100

P

5

1

+70

mV

P

DUTGND Voltage Accuracy

SETTLING/SWITCHING TIMES

C_T

Over 0.1 V range; measured at end points of PMU clamp

functional range

SCAP = 330 pF, FFCAP = 220 pF

Voltage Force Settling Time to

0.1% of Final Value:

PMU enabled, FV, PE disabled, program PMUDAC steps of

500 mV and 5.0 V; simulation of worst case, 2000 pF load,

PMUDAC step of 5.0 V

Range A, 200 pF and

2000 pF Load

Range B, 200 pF and

2000 pF Load

Range C, 200 pF and

2000 pF Load

Range D, 200 pF and

2000 pF Load

15

ꢀs

S

20

124

1015

3455

Range E, 200 pF and

2000 pF Load

Voltage Force Settling Time to

1.0% of Final Value:

PMU enabled, FV, PE disabled, start with PMUDAC

programmed to 0.0 V, program PMUDAC to 500 mV

Range A, 200 pF and

2000 pF Load

Range B, 200 pF and

2000 pF Load

Range C, 200 pF and

2000 pF Load

14

ꢀs

C_B

Range D, 200 pF Load

Range D, 2000 pF Load

Range E, 200 pF Load

Range E, 2000 pF Load

45

225

ꢀs

C_B

Voltage Force Settling Time to

1.0% of Final Value:

PMU enabled, FV, PE disabled, start with PMUDAC

programmed to 0.0 V, program PMUDAC to 5.0 V

Range A, 200 pF and

2000 pF Load

4.0

ꢀs

C_B

Range B, 200 pF Load

Range B, 2000 pF Load

Range C, 200 pF Load

Range C, 2000 pF Load

Range D, 200 pF Load

Range D, 2000 pF Load

Range E, 200 pF Load

Range E, 2000 pF Load

4.2

5.8

19

ꢀs

C_B

50

210

360

610

Rev. 0 | Page 15 of 56

ADATE305

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

Current Force Settling Time to

0.1% of Final Value

PMU enabled, FI, PE disabled, start with PMUDAC

programmed to 0 current, program PMUDAC to FS current

Range A, 200 pF in Parallel

with 120 Ω

Range B, 200 pF in Parallel

with 1.5 kΩ

Range C, 200 pF in Parallel

with 15.0 kΩ

Range D, 200 pF in Parallel

with 150 kΩ

8.2

ꢀs

S

9.4

30

281

2668

Range E, 200 pF in Parallel

with 1.5 MΩ

Current Force Settling Time to

1.0% of Final Value:

PMU enabled, FI, PE disabled, start with PMUDAC

programmed to 0 current, program PMUDAC to FS current

Range A, 200 pF in Parallel

with 120 Ω

Range B, 200 pF in Parallel

with 1.5 kΩ

Range C, 200 pF in Parallel

with 15.0 kΩ

Range D, 200 pF in Parallel

with 150 kΩ

4.2

4.3

8.1

205

505

ꢀs

C_B

Range E, 200 pF in Parallel

with 1.5 MΩ

INTERACTION AND CROSSTALK

Measure Voltage Channel-to-

Channel Crosstalk

0.125

%FSR

C_T

PMU enabled, FIMV, PE disabled, Range B, forcing 0 mA into

0 V load; other channel: Range A, forcing a step of 0 mA to 25 mA

into 0 V load; report ∆V of MEASOUT01 pin under test;

0.125% × 8.0 V = 10 mV

PMU enabled, FVMI, PE disabled, Range E, forcing 0 V into

0 mA current load; other channel: Range E, forcing a step of 0 V

to 5 V into 0 mA current load; report ∆V of MEASOUT01 pin

under test; 0.01% × 5.0 V = 0.5 mV

Measure Current Channel-to-

Channel Crosstalk

0.01

EXTERNAL SENSE (PMUS_CHX)

Table 8.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

EXTERNAL SENSE (PMUS_CHX)

Voltage Range

Input Leakage Current

−1.5

−20

+6.0

+20

V

nA

D

P

Tested at −1.5 V and +6.0 V

DUTGND INPUT

Table 9.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

DUTGND INPUT

Input Voltage Range, Referenced to GND

Input Bias Current

−0.1

+0.1

100

V

μA

D

P

1

Tested at −100 mV and +100 mV

Rev. 0 | Page 16 of 56

ADATE305

SERIAL PERIPHERAL INTERFACE

Table 10.

Test

Parameter

Min

Typ Max

Unit

Level Conditions/Comments

SERIAL PERIPHERAL INTERFACE

Serial Input Logic High

Serial Input Logic Low

Input Bias Current

SCLK Clock Rate

SCLK Pulse Width

1.8

0

−10

V_CC

0.7

+10

V

P_F

P

P_F

C_T

C_B

P_F

1

50

9

μA

MHz

ns

mV

V

Tested at 0.0 V and 3.3 V

SCLK Crosstalk on DUTx Pin

Serial Output Logic High

8

PE disabled, PMU FV enabled and forcing 0 V

Sourcing 2 mA

V_CC− 0.4

0

V_CC

0.8

Serial Output Logic Low

Update Time

V

μs

P_F

D

Sinking 2 mA

10

Maximum delay time required for the part to enter a stable state after

a serial bus command is loaded

HVOUT DRIVER

Table 11.

Test

Level

Parameter

Min

Typ

Max

Unit

Conditions/Comments

VHH BUFFER

Voltage Range

VHH = (VT + 1 V) × 2 + DUTGND

V_PLUS= 16.75 V nominal; in this condition, V_HVOUTmax = 13.5

V

VHH mode enabled, RCV active, VHH level = full scale,

sourcing 15 mA

VHH mode enabled, RCV active, VHH level = zero scale,

sinking 15 mA

VHH mode enabled, RCV active, V_HVOUTerror measured at

the calibration points of 7 V and 12 V

Measured at calibration points

VHH mode enabled, RCV active, after two-point gain/offset

calibration; range/number of DAC bits as measured at the

calibration points of 7 V and 12 V

VHH mode enabled, RCV active, after two-point gain/offset

calibration; measured over VHH range of 5.9 V to 13.5 V

5.9

V_PLUS− 3.25

V

D

P

Output High

13.5

V

Output Low

5.9

V

Accuracy Uncalibrated

−500

−30

100

+500

mV

Offset Tempco

Resolution

1

mV/°C

mV

C_T

P_F

1.21

1.5

INL

15

1

+30

mV

Ω

P

DUTGND Voltage Accuracy

Output Resistance

C_T

P

Over 0.1 V range; measured at end points of VHH

functional range

VHH mode enabled, RCV active, source: VHH = 10.0 V,

I_HVOUT= 0 mA and 15 mA; sink: VHH = 6.5 V, I_HVOUT= 0 mA and

−15 mA; ∆V/∆I

1

10

DC Output Current Limit

Source

DC Output Current Limit Sink

60

100

−60

mA

ns

P

VHH mode enabled, RCV active, VHH = 10.0 V, short HVOUT

pin to 5.9 V, measure current

VHH mode enabled, RCV active, VHH = 6.5 V, short HVOUT

pin to 14.1 V, measure current

VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =

3.0 V; 20% to 80%, for DATA = high and DATA = low

VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =

3.0 V; 20% to 80%, for DATA = high and DATA = low

−100

P

Rise Time (From VL or VH to

VHH)

Fall Time (From VHH to VL or

VH)

Preshoot, Overshoot, and

Undershoot

200

26

C_B

ns

125

mV

VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =

3.0 V; for DATA = high and DATA = low

Rev. 0 | Page 17 of 56

ADATE305

Test

Level

Parameter

Min

Typ

Max

Unit

Conditions/Comments

VL/VH BUFFER

Voltage Range

Accuracy Uncalibrated

−0.1

−500

+6.0

+500

V

mV

D

P

100

VHH mode enabled, RCV inactive, error measured at the

calibration points 0 V and 5 V

Offset Tempco

Resolution

1

0.61

mV/°C

mV

C_T

P_F

Measured at calibration points

0.75

+20

VHH mode enabled, RCV inactive, after two-point

gain/offset calibration; range/number of DAC bits as

measured at the calibration points 0 V and 5 V

VHH mode enabled, RCV inactive, after two-point

gain/offset calibration; measured over range of −0.1 V to

+6.0 V

Over 0.1 V range; measured at end points of VH and VL,

functional range

VHH mode enabled, RCV inactive, source: VH = 3.0 V, I_HVOUT

= 1 mA and 50 mA; sink: VL = 2.0 V, I_HVOUT= −1 mA and −50

mA; ∆V/∆I

INL

−20

46

4

mV

P

DUTGND Voltage Accuracy

Output Resistance

2

mV

Ω

C_T

P

48

50

DC Output Current Limit

Source

DC Output Current Limit Sink

60

100

−60

mA

ns

P

VHH mode enabled, RCV inactive, VH = 6.0 V, short HVOUT

pin to −0.1 V, DATA high, measure current

VHH mode enabled, RCV inactive, VL = −0.1 V, short HVOUT

pin to 6.0 V, DATA low, measure current

VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,

toggle DATA; 20% to 80%

VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,

toggle DATA; 20% to 80%

−100

P

Rise Time (VL to VH)

10.0

11.3

54

C_B

Fall Time (VH to VL)

ns

Preshoot, Overshoot, and

Undershoot

mV

VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,

toggle DATA

OVERVOLTAGE DETECTOR (OVD)

Table 12.

Test

Level

Parameter

Min

Typ

Max

Unit

Conditions/Comments

DC CHARACTERISTICS

Programmable Voltage Range

Accuracy Uncalibrated

−3.0

−200

+7.0

+200

V

mV

D

P

OVD offset errors measured at programmed levels of +7.0 V

and −3.0 V

Hysteresis

112

mV

C_B

LOGIC OUTPUT CHARACTERISTICS

Off State Leakage

10

1000

0.7

nA

V

P

Disable OVD alarm, apply 3.3 V to OVD pin, measure

leakage current

Activate alarm, force 100 μA into OVD pin, measure active

alarm voltage

For OVD high: DUTx = 0 V to 6 V swing, OVD high = 3.0 V,

OVD low = −3.0 V; for OVD low: DUTx = 0 V to 6 V swing,

OVD high = 7.0 V, OVD low = 3.0 V

Max On Voltage @ 100 μA

Propagation Delay

0.2

1.6

P

μs

C_B

16-BIT DAC MONITOR MUX

Table 13.

Test

Level

Parameter

Min

Typ

Max

Unit

Conditions/Comments

DC CHARACTERISTICS

Programmable Voltage Range

Output Resistance

−2.5

+7.5

V

kΩ

D

C_T

16

PMUDAC = 0.0 V, FV, I = 0, 200 μA; ∆V/∆I

Rev. 0 | Page 18 of 56

ADATE305

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 14.

For liquid cooled applications, θ_JC= 1.1°C/W.

Parameter

Rating

Supply Voltages

Table 15. Thermal Resistance

Airflow

Positive Supply Voltage (V_DDto GND)

Positive V_CCSupply Voltage (V_CCto GND)

Negative Supply Voltage (V_SSto GND)

Supply Voltage Difference (V_DDto V_SS)

Reference Ground (DUTGND to GND)

AGND to DGND

VPLUS Supply Voltage (V_PLUSto GND)

Input Voltages

Input Common-Mode Voltage

Short-Circuit Voltage¹

−0.5 V to +11.0 V

−0.5 V to +4.0 V

−6.25 V to +0.5 V

−1.0 V to +16.5 V

−0.5 V to +0.5 V

−0.5 V to +17.5 V

θ_JA

33

30

Unit

°C/W

Natural Convection

1 meter per second

2 meters per second

28.5

EXPLANATION OF TEST LEVELS

D

Definition

V_SSto V_DD

−3.0 V to +8.0 V

0.0 V to V_CC

−0.5 V to +5.5 V

S

Design verification simulation

100% production tested

High Speed Input Voltage²

High Speed Differential Input Voltage³

VREF

P

P_F

Functionally checked during production test

DUTx I/O Pin Current

C_TCharacterized on tester

C_BCharacterized on bench

DCL Maximum Short-Circuit Current⁴

140 mA

Temperature

Operating Temperature, Junction

Storage Temperature Range

125°C

−65°C to +150°C

ESD CAUTION

¹R_L= 0 Ω, V_DUTcontinuous short-circuit condition, (VH, VL, VT, high-Z, VCOM,

clamp modes).

²DATAxP, DATAxN, RCVxP, RCVxN, under source R = 0 Ω.

³DATAxP to DATAxN, RCVxP, RCVxN.

⁴RL = 0 Ω, VDUTx = –3 V to +8 V; DCL current limit. Continuous short-circuit

condition. ADATE305 must current limit and survive continuous short circuit.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 19 of 56

ADATE305

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

75

74

NC

1

NC

PIN 1

2

73 HVOUT

TEMPSENSE

VDD/VDD_TMPSNS

SCAP1

3

72

VPLUS

4

71

SCAP0

5

70

FFCAP_0B

6

FFCAP_1B

VDD

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VDD

7

OVD_CH0

DATA0N

8

OVD_CH1

DATA1N

9

DATA0P

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

DATA1P

FFCAP_1A

VSS

FFCAP_0A

VSS

ADATE305

TOP VIEW

(Not to Scale)

RCV0N

RCV1N

RCV0P

RCV1P

AGND

COMP_QL0P

COMP_QL0N

COMP_VTT0

COMP_QH0P

COMP_QH0N

COMP_QL1P

COMP_QL1N

COMP_VTT1

COMP_QH1P

COMP_QH1N

AGND

NC

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NOTES

1. NC = NO CONNECT.

2. EXPOSED PAD IS CONNEC TED TO V

.

SS

Figure 2. Pin Configuration

Table 16. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

3

4

5

6

7

NC

No Connect. No physical connection to die.

Temperature Sense Output.

TEMPSENSE

VDD/VDD_TMPSNS

SCAP1

FFCAP_1B

VDD

Temperature Sense Supply +10.0 V.

PMU Stability Capacitor Connection Channel 1 (330 pF).

PMU Feed Forward Capacitor Connection B Channel 1 (220 pF).

Supply +10.0 V.

8

9

10

11

12

OVD_CH1

DATA1N

DATA1P

FFCAP_1A

VSS

Overvoltage Detection Flag Output Channel 1.

Driver Data Input (Negative) Channel 1.

Driver Data Input (Positive) Channel 1.

PMU Feedforward Capacitor Connection A Channel 1 (220 pF).

Supply −5.75 V.

Rev. 0 | Page 20 of 56

ADATE305

Pin No.

13

14

Mnemonic

RCV1N

RCV1P

Description

Receive Data Input (Negative) Channel 1.

Receive Data Input (Positive) Channel 1.

Analog Ground.

15

AGND

16

17

18

19

20

21

COMP_QL1P

COMP_QL1N

COMP_VTT1

COMP_QH1P

COMP_QH1N

AGND

Low-Side Comparator Output (Positive) Channel 1.

Low-Side Comparator Output (Negative) Channel 1.

Comparator Supply Channel 1.

High-Side Comparator Output (Positive) Channel 1.

High-Side Comparator Output (Negative) Channel 1.

Analog Ground.

22

AGND

Analog Ground.

23

AGND

Analog Ground.

24

25

26

27

NC

No Connect. No physical connection to die.

28

MEASOUT01/TEMP SENSE

Shared Muxed Output. Muxed output shared by PMU MEASOUT Channel 0, PMU

MEASOUT Channel 1, and the temperature sense and temperature sense GND

reference.

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

DUTGND

AGND

CS

Device Under Test Ground Reference.

Analog Ground.

Serial Peripheral Interface (SPI®) Chip Select.

16-Bit DAC Monitor Mux Output.

Supply −5.75 V.

Supply +10.0 V.

Digital Ground.

Serial Programmable Interface (SPI) Data Output.

Serial Programmable Interface (SPI) Clock.

Serial Programmable Interface (SPI) Data Input.

Supply +10.0 V.

Supply +3.3 V.

Supply −5.75 V.

Serial Peripheral Interface (SPI) Reset.

Analog Ground.

+5 V DAC Reference Voltage.

DAC Ground Reference.

No Connect. No physical connection to die.

Analog Ground.

DAC16_MON

VSS

VDD

DGND

SDOUT

SCLK

SDIN

VDD

VCC

VSS

RST

AGND

VREF

VREF_GND

NC

AGND

Comp_QH0N

Comp_QH0P

Comp_VTT0

Comp_QL0N

Comp_QL0P

AGND

RCV0P

Analog Ground.

High-Side Comparator Output (Negative) Channel 0.

High-Side Comparator Output (Positive) Channel 0.

Comparator Supply Channel 0.

Low-Side Comparator Output (Negative) Channel 0.

Low-Side Comparator Output (Positive) Channel 0.

Analog Ground.

Receive Data Input (Positive) Channel 0.

Rev. 0 | Page 21 of 56

ADATE305

Pin No.

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

EP

Mnemonic

RCV0N

VSS

FFCAP_0A

DATA0P

DATA0N

OVD_CH0

VDD

FFCAP_0B

SCAP0

VPLUS

HVOUT

NC

PMUS_CH0

VSS

VDD

VSSO_0 (DRIVE)

DUT0

VDDO_0 (DRIVE)

AGND

VSS

VDD

AGND

VDD

VSS

AGND

VDDO_1 (DRIVE)

DUT1

VSSO_1 (DRIVE)

VDD

VSS

PMUS_CH1

NC

Description

Receive Data Input (Negative) Channel 0.

Supply −5.75 V.

PMU Feedforward Capacitor Connection A Channel 0 (220 pF).

Driver Data Input (Positive) Channel 0.

Driver Data Input (Negative) Channel 0.

Overvoltage Detection Flag Output Channel 0.

Supply +10.0 V.

PMU Feedforward Capacitor Connection B Channel 0 (220 pF).

PMU Stability Capacitor Connection Channel 0 (330 pF).

Supply +16.75 V.

High Voltage Driver Output.

No Connect. No physical connection to die.

PMU External Sense Path Channel 0.

Supply −5.75 V.

Supply +10.0 V.

Driver Output Supply −5.75 V Channel 0.

Device Under Test Channel 0.

Driver Output Supply +10.0 V Channel 0.

Analog Ground.

Supply −5.75 V.

Supply +10.0 V.

Analog Ground.

Supply +10.0 V.

Supply −5.75 V.

Analog Ground.

Driver Output Supply +10.0 V Channel 1.

Device Under Test Channel 1.

Driver Output Supply −5.75 V Channel 1.

Supply +10.0 V.

Supply −5.75 V.

PMU External Sense Path Channel 1.

No Connect. No physical connection to die.

Exposed Pad. The exposed pad is connected to V_SS.

Rev. 0 | Page 22 of 56

ADATE305

TYPICAL PERFORMANCE CHARACTERISTICS

0.30

1.6

1.4

1.2

3V

0.5V

0.25

0.20

0.15

1.0

0.8

0.6

0.4

0.2

2V

1V

0.2V

0.10

0.05

0

–0.2

–0.05

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

0

2

4

6

8

10

12

14

16

18

TIME (ns)

Figure 3. Driver Small Signal Response; VH = 0.2 V, 0.5 V;

VL = 0.0 V; 50 Ω Termination

Figure 6. 50 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V;

VL = 0.0 V, 50 Ω Termination

1.6

1.8

3V

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

3V

2V

1V

2V

1V

–0.2

0

2

4

6

8

10

12

14

16

18

0

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

TIME (ns)

Figure 4. Driver Large Signal Response; VH = 1.0 V, 2.0 V, 3.0 V;

VL = 0.0 V; 50 Ω Termination

Figure 7. 100 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V;

VL = 0.0 V; 50 Ω Termination

1.6

6

3V

5V

1.4

1.2

1.0

0.8

5

4

2V

3V

3

2

0.6

0.4

0.2

0

1V

1

0

–1

0

1

2

3

4

5

6

7

8

9

10

0

2

4

6

8

10

12

14

16

18

TIME (ns)

Figure 5. Driver Large Signal Response; VH = 1.0 V, 3.0 V, 5.0 V;

VL = 0 .0 V; 500 Ω Termination

Figure 8. Response at 200 MH; VH = 1.0 V, 2.0 V, 3.0 V;

VL = 0.0 V; 50 Ω Termination

Rev. 0 | Page 23 of 56

ADATE305

0.6

0.5

1.6

1.4

1.2

3V

0.4

0.3

0.2

0.1

0

1.0

0.8

0.6

0.4

0.2

0

2V

1V

0.5V

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

TIME (ns)

Figure 12. Driver Active (VH and VL) to and from VTERM Transition;

VH = 1.0 V, VT = 0.5 V, VL = 0.0 V

Figure 9. 300 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V;

VL = 0.0 V; 50 Ω Termination

1.2

0.9

3V

0.8

1.0

0.7

2V

0.8

0.6

0.4

0.2

0

0.6

0.5

1V

0.4

0.3

0.5V

0.2

0.1

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

TIME (ns)

Figure 10. 400 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V;

VL = 0.0 V; 50 Ω Termination

Figure 13. Driver Active (VH and VL) to and from VTERM Transition;

VH = 2.0 V, VT = 1.0 V, VL = 0.0 V

1.2

1.6

1.4

1.2

1.0

0.8

0.6

0.8

0.6

0.4

0.2

0

0.2

0

–0.2

0

2

4

6

8

10

12

14

16

18

20

200

250

300

350

400

450

500

550

600

FREQUENCY (MHz)

TIME (ns)

Figure 11. Driver Toggle Rate, VH = 2.0 V, VL = 0.0 V, 50 Ω Termination

Figure 14. Driver Active (VH and VL) to and from VTERM Transition;

VH = 3.0 V, VT = 1.5 V, VL = 0.0 V

Rev. 0 | Page 24 of 56

ADATE305

20

40

20

2V NEG

0

0.2V NEG

0.2V POS

0

–20

2V POS

–40

–60

–40

–60

–80

–100

1

2

3

4

5

6

7

8 9 10

1

2

3

4

5

6

7

8 9 10

PULSEWIDTH (ns)

Figure 15. Driver Minimum Pulse Width; VH = 0.2 V, VL = 0.0 V

Figure 18. Driver Minimum Pulse Width; VH = 2.0 V, VL = 0.0 V

20

40

20

3V POS

3V NEG

0

0.5V NEG

0.5V POS

0

–20

–40

–60

–40

–60

–80

–100

1

2

3

4

5

6

7

8

9 10

1

2

3

4

5

6

7

8 9 10

PULSEWIDTH (ns)

PULSE WIDTH (ns)

Figure 19. Driver Minimum Pulse Width; VH = 3.0 V, VL = 0.0 V

Figure 16. Driver Minimum Pulse Width; VH = 0.5 V, VL = 0.0 V

1.5

1.0

10

1V NEG

0

0.5

–10

1V POS

0

–20

–0.5

–1.0

–1.5

–2.0

–30

–40

–50

–60

–2

–1

0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

8 9 10

DRIVER OUTPUT VOLTAGE (V)

PULSEWIDTH (ns)

Figure 20. Driver VH Linearity Error

Figure 17. Driver Minimum Pulse Width; VH = 1.0 V, VL = 0.0 V

Rev. 0 | Page 25 of 56

ADATE305

1.5

1.0

0.5

0

100

90

80

70

60

50

40

30

20

–0.5

–1.0

–1.5

10

0

–10

–2

–1

0

1

2

3

4

5

6

–1

0

1

2

3

4

5

6

DRIVER OUTPUT VOLTAGE (V)

V

(V)

DUTx

Figure 21. Driver VL Linearity Error

Figure 24. Driver Output Current Limit; Driver Programmed to −2.0 V;

V_DUTxSwept from −2.0 V to +6.0 V

0

1.5

–10

1.0

0.5

–20

–30

–40

–50

–60

–70

–80

0

–0.5

–1.0

–1.5

–2.0

–90

–100

–2

–1

0

1

2

3

4

5

6

–2

–1

0

1

2

3

4

5

6

V

(V)

DUTx

DRIVER OUTPUT VOLTAGE (V)

Figure 22. Driver VT Linearity Error

Figure 25. Driver Output Current Limit; Driver Programmed to 6.0 V;

V_DUTxSwept from −2.0 V to +6.0 V

48.5

48.0

47.5

47.0

46.5

46.0

–722

–723

–724

–725

–726

–727

–728

–729

–730

–60

–40

–20

0

20

40

60

–1

0

1

2

3

4

5

6

DRIVER OUTPUT CURRENT (mA)

VL PROGRAMMED VOLTAGE (V)

Figure 26. HVOUT VL Linearity Error

Figure 23. Driver Output Resistance vs. Output Current

Rev. 0 | Page 26 of 56

ADATE305

1.0

0.8

0.6

6

4

RISE INPUT

2

RISE SHMOO

0

–2

–4

–6

–8

0.4

0.2

0

FALL SHMOO

FALL INPUT

–10

–12

0

0.6

1.2

1.8

2.4

3.0

5

6

7

8

9

10

11

12

13

14

TIME (ns)

VL PROGRAMMED VOLTAGE (V)

Figure 30. Comparator Shmoo, 1.0 V Input, 1.0 ns (10% to 90%) Input,

50 Ω Terminated

Figure 27. HVOUT VHH Linearity Error

1.6

80

70

60

50

40

30

20

10

0

RISE INPUT

1.2

RISE SHMOO

0.8

FALL SHMOO

0.4

FALL INPUT

0

–10

–1

0

1

2

3

4

5

6

0

0.6

1.2

TIME (ns)

1.8

2.4

3.0

V

(V)

HVOUT

Figure 28. HVOUT VH Current Limit; VH = −0.1 V;

V_HVOUTSwept from −0.1 V to +6.0 V

Figure 31. Comparator Shmoo, 1.5 V Input, 1.5 ns (10% to 90%) Input,

50 Ω Terminated

80

1.6

RISE INPUT

60

40

20

0

1.2

RISE SHMOO

0.8

–20

–40

–60

–80

FALL SHMOO

0.4

0

FALL INPUT

2.4

5

6

7

8

9

10

11

(V)

12

13

14

15

0

0.6

1.2

TIME (ns)

1.8

3.0

V

HVOUT

Figure 32. Comparator Shmoo, 1.5 V Input, 1.2 ns (10% to 90%) Input,

50 Ω Terminated

Figure 29. HVOUT VHH Current Limit; VHH = 10.0 V;

V_HVOUTSwept from −5.9 V to +14.1 V

Rev. 0 | Page 27 of 56

ADATE305

100

75

1.6

RISE INPUT

TOTAL

1.2

0.8

0.4

50

RISE SHMOO

25

0

RISING

FALLING

FALL SHMOO

FALL INPUT

2.4

–25

0

–50

0.5

0.6

1.2

TIME (ns)

1.8

3.0

1.0

1.5

2.0

2.5

INPUT SLEW RATE (10%-90%) (ns)

Figure 33. Comparator Shmoo, 1.5 V Input, 1.0 ns (10% to 90%) Input,

50 Ω Terminated

Figure 36. Comparator Slew Rate Dispersion, Input Swing = 1.5 V,

Comparator Threshold = 0.75 V

1.6

COMP_QH0P

RISE INPUT

1.4

COMP_QH0N

1.2

1.0

0.8

0.6

1.2

RISE SHMOO

0.8

0.4

0.2

FALL SHMOO

FALL INPUT

0

5

10

15

20

25

30

35

40

45

50

0

0.6

1.2

1.8

2.4

3.0

TIME (ns)

Figure 34. Comparator Shmoo, 1.5 V Input, 0.625 ns (10% to 90%) Input,

50 Ω Terminated

Figure 37. Comparator Output Waveform, COMP_QH0P, COMP_QH0N

10

0.8

0.6

0.4

0.2

0

–10

–20

0

–0.2

–0.4

–30

1V POS

–40

–0.6

–0.8

–50

1V NEG

–60

–1.0

–1.2

–1.4

–70

–80

1

2

3

4

5

6

7

8

9 10

–2

–1

0

1

2

3

4

5

6

PULSEWIDTH (ns)

PROGRAMMED THRESHOLD VOLTAGE (V)

Figure 35. Comparator Minimum Pulse Width, 1.0 V

Figure 38. Comparator Threshold Linearity

Rev. 0 | Page 28 of 56

ADATE305

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

–2

–1

0

1

2

3

4

5

6

–2

–1

0

1

2

3

4

5

VCOM VOLTAGE (V)

INPUT COMMON-MODE VOLTAGE (V)

Figure 39. Differential Comparator CMRR

Figure 42. Active Load VCOM Linearity

15

10

5

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

0

–5

–10

–15

–2

–1

0

1

2

3

4

5

6

–2

–1

0

1

2

3

4

5

6

V

(V)

V

(V)

DUTx

Figure 40. Active Load Commutation Response; VCOM = 2.0 V;

IOH = IOL = 12 mA

Figure 43. DUTx Pin Leakage in Low Leakage Mode

6

4

2

0

3.0

2.5

2.0

1.5

1.0

0.5

0

–2

–4

–6

–8

–0.5

–2

–1

0

1

2

3

4

5

6

0

2

4

6

8

10

12

V

(V)

ACTIVE LOAD CURRENT (mA)

DUTx

Figure 41. Active Load Current Linearity

Figure 44. DUTx Pin Leakage in High-Z Mode

Rev. 0 | Page 29 of 56

ADATE305

40

0.008

0.006

0.004

0.002

0

20

0

–20

–40

–60

–80

–0.002

–0.004

–0.006

–100

–120

–140

–0.020 –0.015 –0.010 –0.005

0

0.005 0.010 0.015 0.020

–40

–30

–20

–10

0

10

20

30

40

PMU OUTPUT CURRENT (mA)

Figure 48. PMU Force Current Range D Linearity

Figure 45. PMU Force Current Range A Linearity

0.0005

0.0004

0.0003

0.0002

0.8

0.6

0.4

0.2

0

0.0001

0

–0.0001

–0.2

–0.4

–0.0002

–0.0003

–0.0004

–0.0005

–0.0006

–0.6

–0.8

–0.0020 –0.0015 –0.0010 –0.0050

0

0.0050 0.0010 0.0015 0.0020

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

PMU OUTPUT CURRENT (mA)

Figure 49. PMU Force Current Range E Linearity

Figure 46. PMU Force Current Range B Linearity

5

4

0.08

0.06

0.04

0.02

0

3

2

1

0

–1

–0.02

–0.04

–0.06

–2

–3

–4

–40

–30

–20

–10

0

10

20

30

40

–0.20 –0.15 –0.10 –0.05

0

0.05

0.10

0.15

0.20

I

(mA)

PMU OUTPUT CURRENT (mA)

DUTx

Figure 47. PMU Force Current Range C Linearity

Figure 50. PMU Force Voltage Range A Output Voltage Error at 6.0 V vs.

Output Current

Rev. 0 | Page 30 of 56

ADATE305

5

4

10

0

3

–10

–20

–30

–40

–50

–60

2

1

0

–1

–2

–3

–4

–40

–30

–20

–10

0

10

20

30

40

–2

–1

0

1

2

3

4

5

6

I

(mA)

V

(V)

DUTx

Figure 51. PMU FV Range A Output Voltage Error at −1.5 V vs. Output Current

Figure 54. PMU FI Range A Output Current Error at −32 mA vs. Output

Voltage; Output Voltage Is Pulled Externally

10

0.6

0.4

0

–10

–20

–30

–40

–50

–60

0.2

0

–0.2

–0.4

–0.6

–0.8

–2

–1

0

1

2

3

4

5

6

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

V

(V)

I

(mA)

DUTx

Figure 52. PMU FV Range B Output Voltage Error at 6.0 V vs. Output Current

Figure 55. PMU FI Range A Output Current Error at +32 mA vs. Output

Voltage; Output Voltage Is Pulled Externally

0.6

0.4

0.5

0.4

0.3

0.2

0.1

0

0.2

0

–0.2

–0.4

–0.6

–0.8

–0.1

–0.2

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

–2

–1

0

1

2

3

4

5

6

I

(mA)

V

(V)

DUTx

Figure 53. PMU FV Range B Output Voltage Error at −1.5 V vs. Output Current

Figure 56. PMU FI Range B Output Current Error at −2 mA vs. Output Voltage;

Output Voltage Is Pulled Externally

Rev. 0 | Page 31 of 56

ADATE305

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

–0.1

–0.2

–2

–1

0

1

2

3

4

5

6

–2

–1

0

1

2

3

4

5

V

(V)

V

(V)

DUTx

Figure 57. PMU FI Range B Output Current Error at +2 mA vs. Output Voltage;

Output Voltage Is Pulled Externally

Figure 60. PMU Measure Current CMRR, Externally Pulling 1 mA, FVMI; Error

of MI vs. External 1 mA

0.0015

0.0010

0.0005

0

–0.0005

–0.0010

–2

–1

0

1

2

3

4

5

6

960ps/DIV

V

(V)

DUTx

Figure 58. PMU FI Range E Output Current Error at −2 μA vs. Output Voltage;

Output Voltage Is Pulled Externally

Figure 61. Eye Diagram, 200 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V

0.0016

0.0014

0.0012

0.0010

0.0008

0.0006

0.0004

0.0002

0

–0.0002

–2

–1

0

1

2

3

4

5

6

400ps/DIV

V

(V)

DUTx

Figure 59. PMU FI Range E Output Current Error at +2 μA vs. Output Voltage;

Output Voltage Is Pulled Externally

Figure 62. Eye Diagram, 400 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V

Rev. 0 | Page 32 of 56

ADATE305

250ps/DIV

400ps/DIV

Figure 63. Eye Diagram, 600 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V

Figure 65. Eye Diagram, 400 Mbps, PRBS31; VH = 2.0 V, VL = 0.0 V

200ps/DIV

250ps/DIV

Figure 66. Eye Diagram, 600 Mbps, PRBS31; VH = 2.0 V, VL = 0.0 V

Figure 64. Eye Diagram, 800 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V

Rev. 0 | Page 33 of 56

ADATE305

SPI DETAILS

t_CH

SCLK

t_CL

t_CSSA

t_CSSD

t_CSHA

t_CSHD

CS

t_CSW

t_DH

t_DS

DATA[15]

DATA[14]

ADDR[1]

ADDR[0]

CH[1]

R/W

LAST

SDIN

DO_15

DO_14

DO_13

DO_12

DO_2

DO_1

DO_0

LAST

SDOUT

LAST

t

DO

Figure 67. SPI Timing Diagram

Table 17. Serial Peripheral Interface Timing Requirements

Symbol

Parameter

Min

9.0

3.0

Max

Unit

t_CH

t_CL

SCLK minimum high

SCLK minimum low

ns

t_CSHA

t_CSSA

t_CSHD

t_CSSD

t_DH

CS

assert hold

ns

assert setup

deassert hold

deassert setup

ns

SDIN hold

SDIN setup

ns

t_DS

t_DO

SDOUT Data Out

15.0

ns

1

t_CSW

CS

2

SCLK cycles

minimum between assertions

minimum directly after a read request

3

t_CSTP

CS

16

Minimum delay after is deasserted before SCLK can be

stopped (not shown in Figure 67); this allows any internal

operations to complete

¹An extra cycle is needed after a read request to prime the read data into the SPI shift register.

Rev. 0 | Page 34 of 56

ADATE305

DEFINITION OF SPI WORD

Table 18. Channel Selection

The SPI can accept variable length words, depending on the

operation. At most, the word length equals 24 bits: 16 bits of

data, two channel selects, one R/W selector, and a 5-bit address.

Channel 1 Channel 0 Channel Selected

0

NOP (no channel selected, no register

changes)

0

1

0

1

Channel 0 selected

Channel 1 selected

Channel 0 and Channel 1 selected

Depending on the operation, the data can be smaller or, in the

case of a read operation, nonexistent.

Table 19. R/W Definition

R/W

Description

0

Current register specified by address shifts out of

SDOUT on next shift operation

1

Current data is written to the register specified by

address and channel select

Example 1: 16-Bit Write

Write 16 bits of data to a register or DAC; ignore unused MSBs. For example, Bit 15 and Bit 14 are ignored, and Bit 13 through Bit 0 are

applied to the 14-bit DAC.

DATA[15:0]

DATA[13:0]

DATA[1:0]

CH[1:0]

R/W

ADDR[4:0]

Figure 68. 16-Bit Write

Example 2: 14-Bit Write

Write 14 bits of data to the DAC.

CH[1:0]

R/W

ADDR[4:0]

Figure 69. 14-Bit Write

Example 3a: 2-Bit Write

Write two bits of data to the 2-bit register.

CH[1:0]

R/W

ADDR[4:0]

Figure 70. 2-Bit Write

Example 3b: 2-Bit Write

Write two bits of data to the 2-bit register. Bit 15 through Bit 2 are ignored and Bit 1 through Bit 0 are applied to the register.

DATA[15:0]

CH[1:0]

R/W

ADDR[4:0]

Figure 71. 2-Bit Write

Example 4: Read Request

Read request and follow with a second instruction (could be NOP) to clock out the data.

CH[1:0]

R/W = 0

R/W

ADDR[4:0]

DATA[15:0]

Figure 72. Read Request

Rev. 0 | Page 35 of 56

ADATE305

WRITE OPERATION

CS

INPUT

SCLK

INPUT

DATA[15] DATA[14] DATA[13]

DATA[2] DATA[1] DATA[0] CH[1]

CH[0]

17

R/W

18

ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]

X

SDIN

INPUT

0

1

2

13

14

15

16

19

20

21

22

23

24

25

SDOUT

OUTPUT

X

NOTES

1. R/W = 1.

2. X = DON’T CARE.

Figure 73. 16-Bit SPI Write

CS

INPUT

SCLK

INPUT

DATA[1] DATA[0] CH[1]

CH[0]

3

R/W

4

ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]

X

SDIN

INPUT

0

1

2

5

6

7

8

9

10

11

SDOUT

OUTPUT

X

NOTES

1. R/W = 1.

2. X = DON’T CARE.

Figure 74. 2-Bit SPI Write

Rev. 0 | Page 36 of 56

ADATE305

back the previous specified data. The NOP address can be used

for this read if there is no need to write/read another register. To

maintain the clarity of the operation, it is strongly recommended

that the NOP address be used for all reads.

READ OPERATION

The read operation is a two-stage operation. First, a word is

shifted in, specifying which register to read.

for three clock cycles, and then a second word is shifted in to

obtain the readback data. This second word can be either

another operation or an NOP address. If another operation is

shifted in, it needs to shift in at least eight bits of data to read

CS

is deasserted

Any register read that is fewer than 16 bits has zeroes filled in

the top bits to make it a 16-bit word.

CS

INPUT

SCLK

INPUT

SDIN

INPUT

READ INSTRUCTION

X

NOP

X

SDOUT

OUTPUT

X

READ DATA

X

NOTES

1. X = DON’T CARE.

Figure 75. SPI Read Overview

CS

INPUT

SCLK

INPUT

SDIN

INPUT

ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]

19 20 21 22 23

DATA[15:0], VALUE IS A DON’T CARE

13 14

CH[1]

16

CH[0]

17

R/W

18

X

0

1

2

15

24

25

SDOUT

OUTPUT

X

NOTES

1. X = DON’T CARE.

Figure 76. SPI Read—Details of Read Request

CS

INPUT

SCLK

INPUT

SDIN

DATA[15:0], VALUE IS A DON’T CARE

13 14

CH[1]

16

CH[0]

17

R/W = 1

18

ADDR[4:0] = 0x00 (NOP)

X

INPUT

0

1

2

15

19

20

21

X

22

23

24

25

SDOUT

OUTPUT

RDATA[2] RDATA[1] RDATA[0]

RDATA[15] RDATA[14]

NOTES

1. RDATA IS THE REGISTER VALUE BEING READ.

2. X = DON’T CARE.

Figure 77. SPI Read—Details of Read Out

Rev. 0 | Page 37 of 56

ADATE305

RST

by utilizing the

pin. To initiate the reset operation, deassert

RESET OPERATION

RST

CS

the

pin for a minimum of 100 ns and deassert the

The ADATE305 contains an asynchronous reset feature. The

ADATE305 can be reset to the default values shown in Table 20

for a minimum of two SCLK cycles.

100ns

MINIMUM

RST

CS

SCLK

MINIMUM OF TWO SCLK EDGES AFTER ASSERTING RST BEFORE RESUMING NORMAL OPERATION.

Figure 78. Reset Operation

Rev. 0 | Page 38 of 56

ADATE305

REGISTER MAP

The ADDR[4:0] bits determine the destination register of the data being written to the ADATE305.

Table 20. Register Selection

DATA[15:0]

N/A¹

CH[1:0]

R/W

N/A

R/W

R

ADDR[4:0]

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

Register Selected

NOP

VH DAC level

VL DAC level

VT/VCOM DAC level

VOL DAC level

VOH DAC level

VCH DAC level

VCL DAC level

V(IOH ) DAC level

V(IOL ) DAC level

OVD high level

OVD low level

Reset State

N/A

DATA[13:0]

DATA[15:0]

DATA[2:0]

DATA[9:0]

DATA[2:0]

DATA[0]

CH[1:0]

CH[1]

4096d

16384d

000b

0d

CH[0]

CH[1:0]

N/A

PMUDAC level

PE/PMU enable

Channel state

PMU state

PMU measure enable

Differential comparator enable

16-bit DAC monitor

OVD_CHx alarm mask

OVD_CHx alarm state

Reserved

000b

0b

00b

01b

N/A

DATA[1:0]

DATA[2:0]

N/A

0x11

0x12

0x13

0x14 to 0x1F

N/A

¹N/A means not applicable.

Rev. 0 | Page 39 of 56

ADATE305

DETAILS OF REGISTERS

Table 21. PE/PMU Enable (ADDR[4:0] = 0x0C)

Bit

Name

Description

DATA[2]

PMU enable

0 = disable PMU force output and clamps, place PMU in MV mode

1 = enable PMU force output

When set to 0, the PMU state bits are ignored, except for PMU sense path (Data[7])

0 = normal driver operation

1 = force driver to V_T

See Table 29 for complete functionality of this bit

0 = enable driver functions

DATA[1]

DATA[0]

Force VT

PE disable

1 = disable driver (low leakage)

See Table 29 for complete functionality of this bit

Table 22. Channel State (ADDR[4:0] = 0x0D)

Bit

Name

Description

DATA[2]

HV mode select

0 = HV driver in low impedance.

1 = enable HV driver.

This bit affects Channel 0 only. Ensure that the Channel 0 bit in SPI write is active.

Channel 1 bit in SPI write is don’t care.

DATA[1]

DATA[0]

Load enable

0 = disable load.

1 = enable load.

See Table 29 for complete functionality of this bit.

0 = enable Driver high-Z function.

1 = enable Driver VTERM function.

See Table 29 for complete functionality of this bit.

Driver high-Z or VT

Table 23. PMU State (ADDR[4:0] = 0x0E)^{1, 2}

Bit

Name

Description

DATA[9:8]

PMU input selection

00 = V_DUTGND(calibrated for 0.0 V voltage reference)

01 = 2.5 V + V_DUTGND(calibrated for 0.0 A current reference)

1X = PMUDAC

DATA[7]

PMU sense path

0 = internal sense

1 = external sense

DATA[6]

DATA[5]

Reserved

PMU clamp enable

0 = disable clamps

1 = enable clamps

DATA[4]

DATA[3]

DATA[2:0]

PMU measure voltage or current

PMU force voltage or current

PMU range

0 = measure voltage mode

1 = measure current mode

0 = force voltage mode

1 = force current mode

0XX = 2 μA range

100 = 20 μA range

101 = 200 μA range

110 = 2 mA range

111 = 32 mA range

¹Note that when ADDR[4:0] = 0x0C, the PMU enable bit (DATA[2]) = 0, PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage mode.

PMU State DATA[9:8] and DATA[6:0] are ignored, and only the DATA[7] PMU sense path is valid.

²X = don’t care.

Rev. 0 | Page 40 of 56

ADATE305

Table 24. PMU Measure Enable (ADDR[4:0] = 0x0F)¹

Bit

Name

Description

DATA[2:1]

MEASOUT01 select

00 = PMU MEASOUT Channel 0

01 = PMU MEASOUT Channel 1

10 = Temp sensor ground reference

11 = Temp sensor

DATA[0]

MEASOUT01 output enable

0 = MEASOUT01 is tristated

1 = MEASOUT01 is enabled

¹This register is written to or read from when either of the CH[1:0] bits is 1.

Table 25. Differential Comparator Enable (ADDR[4:0] = 0x10)¹

Bit

Name

Description

DATA[0]

Differential Comparator Enable

0 = differential comparator is disabled; the Channel 0 normal window

comparator (NWC) outputs are located on Channel 0

1 = differential comparator is enabled; the differential comparator outputs

are located on Channel 0

¹This register is written to or read from when either of the CH[1:0] bits is 1.

Table 26. DAC16_MON (16-Bit DAC Monitor) (ADDR[4:0] = 0x11)¹

Bit

Name

Description

DATA[1]

16-Bit DAC mux enable

0 = 16-bit DAC mux is tristated

1 = 16-bit DAC mux is enabled

0 = 16-bit DAC Channel 0

1 = 16-bit DAC Channel 1

DATA[0]

16-Bit DAC mux select

¹This register is written to or read from when either of the CH[1:0] bits is 1.

Table 27. OVD_CHx Alarm Mask (ADDR[4:0] = 0x12)

Bit

Name

Description

DATA[1]

PMU mask

0 = disable PMU alarm flag

1 = enable PMU alarm flag

0 = disable OVD alarm flag

1 = enable OVD alarm flag

DATA[0]

OVD mask

Table 28. OVD_CHx Alarm State (ADDR[4:0] = 0x13)¹

Bit

Name

Description

DATA[2]

PMU clamp flag

0 = PMU is not clamped

1 = PMU is clamped

DATA[1]

DATA[0]

OVD high flag

OVD low flag

0 = DUT voltage < OVD high voltage

1 = DUT voltage > OVD high voltage

0 = DUT voltage > OVD low voltage

1 = DUT voltage < OVD low voltage

¹This register is a read-only register.

Rev. 0 | Page 41 of 56

ADATE305

USER INFORMATION

Table 29. Driver and Load Truth Table¹

Registers

Load Enable

DATA[1]

Signals

PE Disable

DATA[0]

Force VT

DATA[1]

Driver High-Z/VT

DATA[0]

ADDR[4:0] = 0x0C ADDR[4:0] = 0x0C ADDR[4:0] = 0x0D ADDR[4:0] = 0x0D DATAx RCVx Driver State

Load State

1

0

X

1

0

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

High-Z without clamps Power-down

VT

Power-down

Active off

VL

High-Z with clamps

VH

High-Z with clamps

VL

VT

VH

VT

VL

High-Z with clamps

Active on

VH

Active off

High-Z with clamps

VL

Active on

High-Z with clamps

VH

Active on

High-Z with clamps

Active on

¹X = don’t care.

Table 30. HVOUT Truth Table¹

HVOUT Mode Select

DATA[2]

ADDR[4:0] =0x0D

Channel 0

RCV

Channel 0

DATA

HVOUT Driver Output

1

0

1

0

X

0

1

X

VHH mode; VHH = (VT + 1 V) × 2 + DUTGND (Channel 0 VT DAC)

VL (Channel 0 VL DAC)

VH (Channel 0 VH DAC)

Disabled (HVOUT pin set to 0 V low impedance)

¹X = don’t care.

Table 31. Comparator Truth Table

Differential

Comparator Enable

DATA[0]

ADDR[4:0] = 0x10

COMP_QH0

COMP_QL0

COMP_QH1

COMP_QL1

0

Normal window mode

Logic high: VOH0 < V_DUT0

Logic low: VOH0 > V_DUT0

Normal window mode

Logic high: VOL0 < V_DUT0

Logic low: VOL0 > V_DUT0

Normal window mode

Logic high: VOH1 < V_DUT1Logic high: VOL1 < V_DUT1

Logic low: VOH1 > V_DUT1Logic low: VOL1 > V_DUT1

1

Differential comparator mode Differential comparator mode Normal window mode

Normal window mode

Logic high: VOH0 < V_DUT0− V_DUT1Logic high: VOL0 < V_DUT0− V_DUT1Logic high: VOH1 < V_DUT1Logic high: VOL1 < V_DUT1

Logic low: VOH0 > V_DUT0− V_DUT1

Logic low: VOL0 > V_DUT0− V_DUT1

Logic low: VOH1 > V_DUT1Logic low: VOL1 > V_DUT1

Rev. 0 | Page 42 of 56

ADATE305

•

−3.0 V to +7.0 V and tracks DUTGND. Controls the

OVD levels.

−2.5 V to +7.5 V and does not track DUTGND. Controls

the IOH and IOL levels.

DETAILS OF DACS vs. LEVELS

There are ten 14-bit DACs per channel. These DACs provide

levels for the driver, comparator, load currents, VHH buffer, OVD,

and clamp levels. There are three versions of output levels as

follows:

There is one 16-bit DAC per channel. This DAC provides the

levels for the PMU. The output level is as follows:

•

−2.5 V to +7.5 V and tracks DUTGND. Controls the VH,

VL, VT/VCOM/VHH, VOH, VOL, VCH, and VCL levels.

•

−2.5 V to +7.5 V and tracks DUTGND; controls the

PMU levels.

Table 32. Level Transfer Functions

Programmable Range¹

DAC Transfer Function

(All 0s to All 1s)

Levels

V_OUT= 2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁴)) – 0.5 × (V_REF− V_{REF_GND}) + V_DUTGND

−2.5 V to +7.5 V

VH, VL, VT/VCOM,

VOL, VOH, VCH, VCL

Code = [V_OUT− V_DUTGND+ 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁴)/(2.0 × (V_REF− V_{REF_GND}))]

V_OUT= 4.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁴)) − 1.0 × (V_REF− V_{REF_GND}) + 2.0 + V_DUTGND

Code = [V_OUT− V_DUTGND− 2.0 + 1.0 × (V_REF− V_{REF_GND})] × [(2¹⁴)/(4.0 × (V_REF− V_{REF_GND}))]

−3.0 V to +17.0 V

−3.0 V to +7.0 V

VHH

V_OUT= 2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁴)) − 0.6 × (V_REF− V_{REF_GND}) + V_DUTGND

OVD

Code = [V_OUT− V_DUTGND+ 0.6 × (V_REF− V_{REF_GND})] × [(2¹⁴)/(2.0 × (V_REF− V_{REF_GND}))]

I_OUT= [2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁴)) − 0.5 × (V_REF− V_{REF_GND})] × (0.012/5.0)

Code = [(I_OUT× (5.0/0.012)) + 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁴)/(2.0 × (V_REF− V_{REF_GND}))]

−6 mA to +18 mA

−2.5 V to +7.5 V

IOH, IOL

PMUDAC

V_OUT= 2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁶)) – 0.5 × (V_REF− V_{REF_GND}) + V_DUTGND

Code = [V_OUT− V_DUTGND+ 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁶)/(2.0 × (V_REF− V_{REF_GND}))]

I_OUT= [2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁶)) – 0.5 × (V_REF− V_{REF_GND}) − 2.5] × (0.050/5.0)

Code = [(I_OUT× (5.0/0.050)) + 2.5 + 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁶)/(2.0 × (V_REF− V_{REF_GND}))]

−50 mA to +50 mA

−4 mA to +4 mA

−400 μA to +400 μA

−40 μA to +40 μA

−4 μA to +4 μA

PMUDAC

(PMU FI Range A)

PMUDAC

(PMU FI Range B)

PMUDAC

(PMU FI Range C)

PMUDAC

(PMU FI Range D)

I_OUT= [2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁶)) – 0.5 × (V_REF− V_{REF_GND}) − 2.5] × (0.004/5.0)

Code = [(I_OUT× (5.0/0.004)) + 2.5 + 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁶)/(2.0 × (V_REF− V_{REF_GND}))]

I_OUT= [2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁶)) – 0.5 × (V_REF− V_{REF_GND}) − 2.5] × (0.0004/5.0)

Code = [(I_OUT× (5.0/0.0004)) + 2.5 + 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁶)/(2.0 × (V_REF− V_{REF_GND}))]

I_OUT= [2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁶)) – 0.5 × (V_REF− V_{REF_GND}) − 2.5] × (0.00004/5.0)

Code = [(I_OUT× (5.0/0.00004)) + 2.5 + 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁶)/(2.0 × (V_REF− V_{REF_GND}))]

I_OUT= [2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁶)) – 0.5 × (V_REF− V_{REF_GND}) − 2.5] × (0.000004/5.0)

Code = [(I_OUT× (5.0/0.000004)) + 2.5 + 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁶)/(2.0 × (V_REF− V_{REF_GND}))]

PMUDAC

(PMU FI Range E)

¹Programmable range includes a margin outside of the specified part performance, allowing for offset/gain calibration.

Table 33. Load Transfer Functions

Load Level

Transfer Function¹

V(IOL)/5 V × 12 mA

V(IOH)/5 V × 12 mA

IOL

IOH

¹V(IOH), V(IOL) DAC levels are not referenced to DUTGND.

Table 34. PMU Transfer Functions

PMU Mode

Transfer Functions

Force Voltage

V_OUT= PMUDAC

Measure Voltage

Force Current

V_MEASOUT01= V_DUTx(internal sense) or V_MEASOUT01= V_{PMUS_CHx}(external sense)

I_OUT= [PMUDAC − (V_REF/2)]/(R¹× 5)

V_MEASOUT01= (V_REF/2) + V_DUTGND+ (I_DUTx× 5 × R¹)

Measure Current

¹R = 15.5 Ω for Range A; 250 Ω for Range B; 2.5 kΩ for Range C; 25 kΩ for Range D; 250 kΩ for Range E.

Rev. 0 | Page 43 of 56

ADATE305

Table 35. PMU User Required Capacitors

Table 36. Temperature Sensor

Capacitor Location

Temperature

Output

220 pF

330 pF

Across Pin 70 (FFCAP_0B) and Pin 65 (FFCAP_0A)

0 K

0 V

Across Pin 6 (FFCAP_1B) and Pin 11 (FFCAP_1A)

Between GND and Pin 71 (SCAP0)

300 K

x K

3 V

(x K) × 10 mV/K

Between GND and Pin 5 (SCAP1)

Table 37. Power Supply Ranges

Parameter

Range 1

+10.0 V

−5.25 V

Range 2

+10.0 V

−5.75 V

Nominal VDD

Nominal VSS

Driver

VH range

−1.4 V to +6.0 V

−1.5 V to +5.9 V

−1.5 V to +6.0 V

7.5 V

−1.9 V to +6.0 V

VL range

−2.0 V to +5.9 V

−2.0 V to +6.0 V

8.0 V

VT range

Functional Amplitude

Reflection Clamp

VCH Range

−1.0 V to +6.0 V

−1.5 V to +5.0 V

−1.5 V to +6.0 V

−1.25 V to +5.75 V

−1.5 V to +6.0 V

−2.0 V to +5.0 V

−2.0 V to +6.0 V

−1.75 V to +5.75 V

VCL Range

Comparator Input Voltage Range

Active Load VCOM Range

PMU

Force Voltage Range

Measure Voltage Range

Force Current Voltage Range

Measure Current Voltage Range

Low Clamp Range

High Clamp Range

−1.5 V to +6.0 V

−1.5 V to +4.0 V

0.0 V to +6.0 V

−2.0 V to +6.0 V

−2.0 V to +4.0 V

0.0 V to +6.0 V

Rev. 0 | Page 44 of 56

ADATE305

Table 38. Default Test Conditions (Range 1)

Name

Default Test Condition

VH DAC Level

+2.0 V

VL DAC Level

+0.0 V

VT/VCOM DAC Level

VOL DAC Level

VOH DAC Level

VCH DAC Level

VCL DAC Level

+1.0 V

−1.0 V

+6.0 V

+7.5 V

−2.5 V

IOH DAC Level

0.0 A

IOL DAC Level

0.0 A

OVD Low DAC Level

OVD High DAC Level

PMUDAC DAC Level

PE/PMU Enable

Channel State

−2.5 V

+6.5 V

0.0 V

0x0000: PMU disabled, VT not forced through driver, PE enabled

0x0000: HV mode disabled, load disabled, VTERM inactive

0x0000: Input of DUTGND, internal sense, clamps disabled, FVMV, Range E

0x0000: MEASOUT01 pin tristated

0x0000: Normal window comparator mode

0x0000: DAC16_MON tristated

PMU State

PMU Measure Enable

Differential Comparator Enable

16-Bit DAC Monitor

OVD_CHx Alarm Mask

Data Input

0x0000: disable alarm functions

Logic low

Receive Input

Logic low

DUTx Pin

Unterminated

Comparator Output

Unterminated

Rev. 0 | Page 45 of 56

ADATE305

•

PMU disable to PMU enable.

PMU force voltage mode to PMU force current mode.

PMU force current mode to PMU force voltage mode.

RECOMMENDED PMU MODE SWITCHING

SEQUENCES

To minimize any possible aberrations and voltage spikes on the

DUT output, specific mode switching sequences are

recommended for the following transitions:

PMU Disable to PMU Enable

Note that in Table 39 through Table 49, X indicates the don’t care bit.

Step 1. Table 39 lists the state of the registers in PMU disabled mode.

Table 39.

Register

Bits

Setting

PE/PMU Enable Register, ADDR[4:0] = 0x0C

PMU State Register, ADDR[4:0] = 0x0E

DATA[2]

DATA[9:8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2:0]

0

XX

X

XXX

Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 40).

Table 40.

Register

Bits

Setting

Comments

PMU State Register, ADDR[4:0] = 0x0E

DATA[9:8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

1X or 00

Set desired input selection

X

0

This bit must be set to force voltage mode to reduce

aberrations

DATA[2:0]

XXX

Set desired range

Step 3. Write to Register ADDR[4:0] = 0x0C (see Table 41).

Table 41.

Register

Bits

Setting

Comments

PE/PMU Enable Register, ADDR[4:0] = 0x0C

DATA[2]

1

PMU is now enabled in force voltage mode

PMU Force Voltage Mode to PMU Force Current Mode

Step 1. Table 42 lists the state of registers in force voltage mode.

Table 42.

Register

Bits

Setting

PE/PMU Enable Register, ADDR[4:0] = 0x0C

PMU State Register, ADDR[4:0] = 0x0E

DATA[2]

DATA[9:8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2:0]

1

XX

X

0

XXX

Rev. 0 | Page 46 of 56

ADATE305

Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 43).

Table 43.

Register

Bits

Setting

Comments

PMU State Register, ADDR[4:0] = 0x0E

DATA[9:8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2:0]

01

X

Set 2.5 V + DUTGND input selection

X

1

Set to force current mode

0XX

2 μA range has the minimum offset current

Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 44).

Table 44.

Register

Bits

DATA[15:0]

Setting

Comments

VIN 16-Bit DAC, ADDR[4:0] = 0x0B

X

Update the VIN 16-Bit DAC register to the

desired value

Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 45).

Table 45.

Register

Bits

Setting

Comments

PMU State Register, ADDR[4:0] = 0x0E

DATA[9:8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2:0]

1X

X

Set VIN input selection

1

XXX

Set to the desired current range

Transition from PMU Force Current Mode to PMU Force Voltage Mode

Step 1. Table 46 lists the state of the registers in force current mode.

Table 46.

Register

Bits

Setting

PE/PMU Enable Register, ADDR[4:0] = 0x0C

PMU State Register, ADDR[4:0] = 0x0E

DATA[2]

DATA[9:8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2:0]

1

XX

X

1

XXX

Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 47).

Table 47.

Register

Bits

Setting

Comments

PMU State Register, ADDR[4:0] = 0x0E

DATA[9:8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2:0]

00

X

Set DUTGND input selection

0

XXX

Set to force voltage mode

Set to the desired current range

Rev. 0 | Page 47 of 56

ADATE305

Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 48).

Table 48.

Register

Bits

Setting

Comments

VIN 16-Bit DAC, ADDR[4:0] = 0x0B

DATA[15:0]

X

Update the VIN 16-Bit DAC register to the desired value

Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 49).

Table 49.

Register

Bits

Setting

Comments

PMU State Register, ADDR[4:0] = 0x0E

DATA[9:8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2:0]

1X

X

Set VIN input selection

0

XXX

Force voltage mode

Rev. 0 | Page 48 of 56

ADATE305

BLOCK DIAGRAMS

VCL VCH

PE DISABLE DATA[0] (ADDR[4:0] = 0x0C)

FORCES SWITCH OPEN WHEN 1

VH

VL

R

= 47ꢀ

OUT

(TRIMMED)

DUT

DRIVER

DATA

VT

DRIVER HIGH-Z/VT DATA[0]

(ADDR[4:0] = 0x0D)

VT BUFFER WHEN 1

HIGH-Z BUFFER WHEN 0

V(IOH)

RCV

VCOM

FORCE VT DATA[1] (ADDR[4:0] = 0x0C)

OVERRIDES THE RCV PIN AND FORCES

VTERM MODE ON THE DRIVER AND LOAD

POWER-DOWN MODE

V(IOL)

LOAD ENABLE DATA[1] (ADDR[4:0] = 0x0D)

FORCES SWITCHES OPEN AND POWERS

DOWN LOAD WHEN 0

Figure 79. Driver and Load Block Diagram

~5ꢀ

VHH = (VT + 1V) × 2 + DUTGND

HVOUT

VH

VL

48ꢀ

DATA

RCV (SHOWN IN

RCV = 0 STATE)

HV MODE SELECT DATA[2]

(ADDR [4:0] = 0x0D) DISABLES

HV DRIVER AND FORCES

0V ON HVOUT WHEN 0

Figure 80. HVOUT Driver Output Stage

Rev. 0 | Page 49 of 56

ADATE305

VOH0

–

VOH

NWC

+

DUT0

COMP_QH0

2:1

MUX

+

VOL

NWC

VOL0

VOH0

–

DIFFERENTIAL

COMPARATOR ENABLE

DATA[0] (ADDR[4:0] = 0x10)

–

VOH

DMC

COMP_QL0

2:1

MUX

+

DU T0 –

DUT0–

DU T1

DUT1

DIFFERENTIAL

BUFFER

+

VOL

DMC

VOL0

–

NOTES

1. DIFFERENTIAL COMPARATOR ONLY ON CHANNEL 0.

Figure 81. Comparator Block Diagram

COMPARATOR

OUTPUT (AB)

VTT = 3.3V

RECEIVER

OUT HIGH = 1.55V

OUT CM = 1.42V

OUT LOW = 1.30V

50ꢀ

100ꢀ

GND

Figure 82. Comparator Output Scheme

Rev. 0 | Page 50 of 56

ADATE305

PMU SENSE PATH DATA[7]

(ADDR[4:0] = 0x0E)

PMU MEASURE V/I DATA[4]

(ADDR[4:0] = 0x0E)

EXTERNAL DUT

SENSE PIN

MEASURE V

MEASURE I

MEASOUT01 SELECT DATA[2:1]

(ADDR[4:0] = 0x0F)

MUX

PMU FORCE V/I DATA[3]

(ADDR[4:0] = 0x0E)

MEASURE

OUT

CH[1] PMU V/I

IN-AMP G = 5

10kꢀ

TEMP SENSE

GND REF

TEMP SENSE

REF

2.5 + DUTGND

MUX

MEASOUT01 OUTPUT

ENABLE DATA[0]

(ADDR[4:0] = 0x0F)

ONE PER DEVICE

DUTx

225kꢀ

22.5kꢀ

2.25kꢀ

250ꢀ

15.5ꢀ

2µA

20µA

200µA

32mA BUFFER

32mA

2mA

PMU INPUT SELECTION DATA[9:8]

(ADDR[4:0] = 0x0E)

MV

VIN

2.5V + DUTGND

DUTGND

FFCAP_xA

FFCAP_xB

330pF

SCAPx

(EXTERNAL)

MUX

PMU CLAMP ENABLE DATA[5]

(ADDR[4:0] = 0x0E)

CRA = 220pF

VCH

MEASURE V

(AT OUTPUT OF

SENSE MUX)

VCL

NOTES

1. SWITCHES CONNECTED WITH DOTTED LINES REPRESENT PMU RANGE DATA[2:0] (ADDR[4:0] = 0x0E); WHEN PMU ENABLE DATA[2] = 0 (ADDR[4:0] = 0x0C), ALL

SWITCHES OPEN AND PMU POWERS DOWN.

2. THE EXTERNAL SENSE PATH MUST CLOSE THE LOOP TO ENABLE THE CLAMPS TO OPERATE CORRECTLY.

3. 32mA RANGE HAS ITS OWN OUTPUT BUFFER.

4. 32mA BUFFER TRISTATES WHEN NOT IN USE.

Figure 83. PMU Block Diagram

Rev. 0 | Page 51 of 56

ADATE305

(ADDR[4:0] = 0x12) DATA[0]

OVD MASK ENABLES OVD

FLAGS TO ALARM OVD_CHx PIN

1

6.5V

OVD HIGH LEVEL

DAC (ADDR[4:0] = 0x0A, CH[1])

OVD_CHx

SHORT-CIRCUIT

CURRENT = 100µA

DUT

ADATE305

1

–2.5V

OVD LOW LEVEL

DAC (ADDR[4:0] = 0x0A, CH[0])

PMU

V/I CLAMP

FLAG

(ADDR[4:0] = 0x12) DATA[1]

PMU MASK ENABLES PMU V/I

FLAG TO ALARM OVD_CHx PIN

2

(ADDR[4:0] = 0x13) DATA[2] DATA[1] DATA[0]

1

THE OVD HIGH/LOW LEVEL DAC IS SHARED BY EACH CHANNEL; THEREFORE, ONLY ONE OVD HIGH/LOW VOLTAGE

LEVEL CAN BE SET PER CHIP. THE OVD DACs PROVIDE A VOLTAGE RANGE OF –3V TO +7V. THE RECOMMENDED

HIGH/LOW SETTINGS ARE +6.5V/–2.5V. (THESE VALUES NEED TO BE PROGRAMMED BY THE USER UPON STARTUP/RESET.)

THIS IS A READ ONLY REGISTER THAT ALLOWS THE USER TO DETERMINE THE CAUSE OF THE ACTIVE OVD FLAG.

2

Figure 84. OVD Block Diagram

Rev. 0 | Page 52 of 56

ADATE305

OUTLINE DIMENSIONS

16.00 BSC SQ

1.20

MAX

0.75

0.60

0.45

14.00 BSC SQ

76

100

1

75

PIN 1

8.00

BSC SQ

EXPOSED

PAD

0° MIN

1.05

1.00

0.95

0.20

0.09

TOP VIEW

(PINS DOWN)

51

25

26

7°

50

3.5°

0.15

0.05

0°

0.50 BSC

LEAD PITCH

VIEW A

0.27

0.22

0.17

SEATING

PLANE

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.08 MAX

COPLANARITY

SECTION OF THIS DATA SHEET.

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-AED-HU

Figure 85. 100-Lead, Thin Quad Flatpack, Exposed Pad [TQFP_EP]

(SV-100-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADATE305BSVZ¹

Temperature Range

Package Description

Package Option

−40°C to +85°C

100-Lead, Thin Quad Flatpack, Exposed Pad [TQFP_EP]

SV-100-7

¹Z = RoHS Compliant Part.

Rev. 0 | Page 53 of 56

ADATE305

NOTES

Rev. 0 | Page 54 of 56

ADATE305

NOTES

Rev. 0 | Page 55 of 56

ADATE305

NOTES

registered trademarks are the property of their respective owners.

D07280-0-8/08(0)

Rev. 0 | Page 56 of 56


型号：	ADATE305BSVZ
厂家：	ADI
描述：	250 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH 250 MHz双通道集成DCL与电平设置的DAC ，每个引脚PMU和每个芯片VHH 模拟IC 信号电路
文件：	总56页 (文件大小：1088K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADATE305BSVZ [ADI]

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