ADAU1463WBCPZ150_技术文档

SigmaDSP Digital Audio Processor

ADAU1463/ADAU1467

Data Sheet

Clock oscillator for generating master clock from crystal

Integer PLL and flexible clock generators

Integrated die temperature sensor

I²C and SPI control interfaces (both slave and master)

Standalone operation

FEATURES

Qualified for automotive applications

Fully programmable audio DSP for enhanced sound processing

Features SigmaStudio, a proprietary graphical programming

tool for the development of custom signal flows

Up to 294.912 MHz, 32-bit SigmaDSP core at 1.2 V

Up to 24 kWords of program memory

Up to 80 kWords of parameter/data RAM

Up to 6144 SIMD instructions per sample at 48 kHz

Up to 1600 ms digital audio delay pool at 48 kHz

Audio I/O and routing

4 serial input ports, 4 serial output ports

48-channel, 32-bit digital I/O up to a sample rate of 192 kHz

Flexible configuration for TDM, I²S, left and right justified

formats, and PCM

8 stereo ASRCs from 1:8 up to 7.75:1 ratio and

139 dB dynamic range

Self boot from serial EEPROM

8-channel, 10-bit SAR auxiliary control ADC

26 multipurpose pins for digital controls and outputs

On-chip regulator for generating 1.2 V from 3.3 V supply

88-lead, 12 mm × 12 mm LFCSP package with 5.3 mm

exposed pad

Temperature range: −40°C to +105°C

APPLICATIONS

Automotive audio processing

Head units

Distributed amplifiers

Rear seat entertainment systems

Trunk amplifiers

Commercial and professional audio processing

Stereo S/PDIF input and output at 192 kHz

4 PDM microphone input channels

Multichannel, byte addressable TDM serial ports

FUNCTIONAL BLOCK DIAGRAM

2

SPI/I C* SPI/I C*

PLLFILT

ADAU1467/

ADAU1463

VDRIVE

REGULATOR

2

GPIO/

AUX ADC

CLOCK

OSCILLATOR

I C/SPI

SLAVE

I C/SPI

CLKOUT

PLL

MASTER

THD_P

THD_M

TEMPERATURE

SENSOR

INPUT AUDIO

ROUTING MATRIX

OUTPUT AUDIO

ROUTING MATRIX

S/PDIF

RECEIVER

S/PDIF

TRANSMITTER

SPDIFIN

SPDIFOUT

2

294.912MHz PROGRAMMABLE

AUDIO PROCESSING CORE

DIGITAL

(48-CHANNEL

DIGITAL AUDIO

INPUTS)

MIC INPUT

RAM, ROM, WATCHDOG,

MEMORY PARITY CHECK

SERIAL DATA

OUTPUT PORTS

(×4)

(48-CHANNEL

DIGITAL AUDIO

INPUTS)

SERIAL DATA

INPUT PORTS

(×4)

SDATA_OUT3 TO SDATA_OUT0

8 × 2-CHANNEL ASYNCHRONOUS

SAMPLE RATE CONVERTERS

SERIAL DATA PORTS, SELECTABLE INPUT/OUTPUT (x8)

SDATAIO7 TO SDATAIO0

INPUT

CLOCK

DOMAINS

(×4)

OUTPUT

CLOCK

DOMAINS

(×4)

BCLK_OUT3 TO BCLK_OUT0/

LRCLK_OUT3 TO LRCLK_OUT0

(OUTPUT CLOCK PAIRS)

BCLK_IN3 TO BCLK_IN0/

LRCLK_IN3 TO LRCLK_IN0

(INPUT CLOCK PAIRS)

DEJITTER AND

CLOCK GENERATOR

2

*SPI/I C INCLUDES THE FOLLOWING PIN FUNCTIONS: SS_M, MOSI_M, SCL_M, SCLK_M, SDA_M, MISO_M, MISO, SDA,

SCLK, SCL, MOSI, ADDR1, SS, AND ADDR0 PINS.

Figure 1.

Rev. A

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ADAU1463/ADAU1467

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Random Access Memory .......................................................... 90

Control Registers........................................................................ 93

Control Register Details ................................................................ 99

PLL Configuration Registers .................................................... 99

Clock Generator Registers ...................................................... 103

Power Reduction Registers ..................................................... 109

Slave Control Port Memory Page Setting Register .............. 111

Audio Signal Routing Registers.............................................. 112

Serial Port Configuration Registers....................................... 120

SDATA Port Routing Register ................................................ 123

Flexible TDM Interface Registers........................................... 125

DSP Core Control Registers.................................................... 128

Debug and Reliability Registers.............................................. 133

DSP Program Execution Registers......................................... 141

Panic Mask Registers ............................................................... 144

Multipurpose Pin Configuration Registers........................... 157

ASRC Status and Control Registers ....................................... 162

Auxiliary ADC Registers......................................................... 166

Secondary I²C Master Register............................................... 166

S/PDIF Interface Registers ...................................................... 167

S/PDIF Receiver MCLK Speed Selection Register............... 170

S/PDIF Transmitter MCLK Speed Selection Register......... 171

Hardware Interfacing Registers.............................................. 179

MP14 Pin Drive Strength and Slew Rate Register ............... 197

MP15 Pin Drive Strength and Slew Rate Register ............... 198

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description......................................................................... 4

Differences Between the ADAU1463 and ADAU1467 ........... 4

Specifications..................................................................................... 5

Electrical Characteristics............................................................. 7

Timing Specifications .................................................................. 9

Absolute Maximum Ratings.......................................................... 17

Thermal Considerations............................................................ 17

ESD Caution................................................................................ 17

Pin Configuration and Function Descriptions........................... 18

Theory of Operation ...................................................................... 24

System Block Diagram............................................................... 24

Overview...................................................................................... 24

Initialization ................................................................................ 26

Master Clock, PLL, and Clock Generators.............................. 30

Power Supplies, Voltage Regulator, and Hardware Reset...... 35

Temperature Sensor Diode........................................................ 36

Slave Control Ports..................................................................... 36

Slave Control Port Addressing.................................................. 37

Slave Port to DSP Core Address Mapping .............................. 37

Master Control Ports.................................................................. 44

Self Boot....................................................................................... 45

Serial Data Input/Output........................................................... 46

SDATAIOx Pins.......................................................................... 53

Serial Clock Domains ................................................................ 54

Asynchronous Sample Rate Converters .................................. 63

Audio Signal Routing................................................................. 67

Flexible TDM Interface.............................................................. 69

S/PDIF Interface ......................................................................... 74

Digital PDM Microphone Interface......................................... 77

Multipurpose Pins ...................................................................... 78

Auxiliary ADC............................................................................ 82

SigmaDSP Core .......................................................................... 82

Software Features........................................................................ 87

Pin Drive Strength, Slew Rate, and Pull Configuration ........ 88

Global RAM and Control Register Map...................................... 90

SDATA In/Out Pins Drive Strength and Slew Rate Registers

..................................................................................................... 199

MP24 Pin Drive Strength and Slew Rate Register ............... 200

MP25 Pin Drive Strength and Slew Rate Register ............... 201

Soft Reset Register.................................................................... 202

Applications Information............................................................ 203

PCB Design Considerations ................................................... 203

Typical Applications Block Diagram ..................................... 204

Example PCB Layout ............................................................... 205

PCB Manufacturing Guidelines ............................................. 206

Outline Dimensions..................................................................... 207

Ordering Guide ........................................................................ 207

Automotive Products............................................................... 207

Rev. A | Page 2 of 207

Data Sheet

ADAU1463/ADAU1467

REVISION HISTORY

6/2018—Rev. 0 to Rev. A

Change to IOVDD Range ............................................ Throughout

Specifications Section .......................................................................4

Changes to Table 1 ............................................................................4

Changes to Table 2 ............................................................................5

Changes to Table 3 ............................................................................6

Changes to Figure 5 ........................................................................11

Changes to Table 18 ........................................................................18

Changes to Figure 13 ......................................................................27

Changes to Table 20 ........................................................................31

Changes to the PLL Filter Section and Table 21 .........................32

Changes to Voltage Regulator Section..........................................35

Changes to Table 28 ........................................................................42

Changes to Table 37 and Table 38.................................................53

Added Configuring Input Channel Count with SDATAIOx

Section and Table 39, Renumbered Sequentially........................54

Moved Figure 25, Renumbered Sequentially...............................91

Moved Figure 26..............................................................................92

Changes to Table 60 ........................................................................98

Changes to ASRC Output Rate Selector Register Section .......115

Added Table 80 ..............................................................................115

Changes to Table 143 ....................................................................172

Changes to Figure 88 ....................................................................206

Changes to Example PCB Layout Section and Figure 90 ........207

Changes to the Ordering Guide Section ....................................209

10/2017—Revision 0: Initial Version

Rev. A | Page 3 of 207

ADAU1463/ADAU1467

Data Sheet

GENERAL DESCRIPTION

The ADAU1463/ADAU1467 are automotive qualified audio

processors that far exceed the digital signal processing

capabilities of earlier SigmaDSP® devices. They are pin and

register compatible with each other, as well as with the

ADAU1450/ADAU1451/ADAU1452 SigmaDSP processors.

The restructured hardware architecture is optimized for

efficient audio processing. The audio processing algorithms

support a seamless combination of stream processing (sample

by sample), multirate processing, and block processing paradigms.

The SigmaStudio® graphical programming tool enables the

creation of signal processing flows that are interactive, intuitive,

and powerful. The enhanced digital signal processor (DSP) core

architecture enables some types of audio processing algorithms

to be executed using significantly fewer instructions than were

required on previous SigmaDSP generations, leading to vastly

improved code efficiency.

run serial ports at high speed, and enables systems with additional

serial audio peripherals. These expanded serial audio ports, along

with the clock generators, the on-board asynchronous sample rate

converters (ASRCs), and a flexible hardware audio routing matrix

make the ADAU1463/ ADAU1467 ideal audio hubs that greatly

simplify the design of complex, multirate audio systems.

The ADAU1463/ADAU1467 interface with a wide range of

analog-to-digital converters (ADCs), digital-to-analog converters

(DACs), digital audio devices, amplifiers, and control circuitry

with highly configurable serial ports, I²C, serial peripheral

interface (SPI), Sony/Philips Digital Interconnect Format

(S/PDIF) interfaces, and multipurpose I/O pins. Dedicated

decimation filters can decode the pulse density modulation

(PDM) output of up to four MEMS microphones.

Independent slave and master I²C/SPI control ports allow the

ADAU1463/ADAU1467 to be programmed and controlled by

an external master device such as a microcontroller, and to

program and control slave peripherals directly. Self boot

functionality and the master control port enable complex

standalone systems.

The 1.2 V, 32-bit DSP core can run at frequencies of up to

294.912 MHz and execute up to 6144 single instruction, multiple

data (SIMD) instructions per sample at the standard sample rate

of 48 kHz. Powerful clock generator hardware, including a flexible

phase-locked loop (PLL) with multiple fractional integer outputs,

supports all industry standard audio sample rates. Nonstandard

rates over a wide range can generate up to 15 sample rates simul-

taneously. These clock generators, along with the on-board

asynchronous sample rate converters (ASRCs) and a flexible

hardware audio routing matrix, make the ADAU1463/ADAU1467

ideal audio hubs that greatly simplify the design of complex

multirate audio systems.

Note that throughout this data sheet, multifunction pins, such

as SDATAIO4/MP20, are referred to either by the entire pin

name or by a single function of the pin, for example, MP20,

when only that function is relevant.

DIFFERENCES BETWEEN THE ADAU1463 AND

ADAU1467

The two variants of this device are differentiated by memory

and DSP core frequency. A detailed summary of the differences

is listed in Table 1.

The ADAU1463/ADAU1467 have four input serial ports and

four output serial ports. Each device has an asynchronous clock

domain capable of operating as either a bit clock and frame sync

master or slave. Each of the serial ports supports multiple data

lines. The eight SDATAIOx pins each can be associated with any

of the four input or four output serial ports. The use of assignable

data pins allows a serial port to transmit or receive additional

channels of audio data using a single bit clock and frame clock.

Each of the supplemental data pins can carry from two to eight

channels of serial audio. This flexible configuration provides

more channels of audio input/output (I/O) without the need to

Table 1. Product Selection Table

Data

Memory

(kWords)

Program

Memory

(kWords)

DSP Core

Frequency

(MHz)

Device

ADAU1463WBCPZ300

ADAU1463WBCPZ150

ADAU1467WBCPZ300

48

80

16

24

294.912

147.456

294.912

Rev. A | Page 4 of 207

Data Sheet

ADAU1463/ADAU1467

SPECIFICATIONS

AVDD = 3.3 V 10%, DVDD = 1.2 V 5%, PVDD = 3.3 V 10%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, T_A= 25°C, master clock input =

12.288 MHz, core clock (f_CORE) = 294.912 MHz, I/O pins set to low drive setting, unless otherwise noted.

Table 2.

Parameter

Min Typ Max

Unit Test Conditions/Comments

POWER

Supply Voltage

Analog Voltage (AVDD)

Digital Voltage (DVDD)

2.97 3.3

1.14 1.2

3.63

1.26

V

Supply for analog circuitry, including auxiliary ADCs

Supply for digital circuitry, including the DSP core, ASRCs, and signal

routing

PLL Voltage (PVDD)

I/O Supply Voltage (IOVDD)

Supply Current

2.97 3.3

1.71 3.3

3.63

V

Supply for PLL circuitry

Supply for input/output circuitry, including pads and level shifters

Analog Current (AVDD)

Idle State

Reset State

1.36 1.66

1.00 1.10 40

2

mA

µA

mA

µA

Power applied, chip not programmed

RESET

held low

Power applied,

PLL Current (PVDD)

Idle State

Reset State

8.3

10.1 12.9

12.288 MHz MCLK with default PLL settings

Power applied, PLL not configured

18.3 18.7 40

RESET

held low

Power applied,

I/O Current (IOVDD)

Dependent on the number of active serial ports, clock pins, and

characteristics of external loads

Operation State

53

22

4.1

mA

IOVDD = 3.3 V; all serial ports are clock masters

IOVDD = 1.8 V; all serial ports are clock masters

IOVDD = 1.8 V − 5% to 3.3 V + 10%

Power-Down State

Digital Current (DVDD)

ADAU1467 Operation State

Maximum Program

4.2

233

220

495

mA

Typical Program

Test program includes 16-channel I/O, 10-band equalizer (EQ) per channel,

all ASRCs active

Minimal Program

ADAU1463 Operation State

f_CORE= 294.912 MHz

Maximum Program

Typical Program

213

mA

Test program includes 2-channel I/O, 10-band EQ per channel

233

220

495

420

mA

Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs

active

Test program includes 2-channel I/O, 10-band EQ per channel

Minimal Program

f_CORE= 147.456 MHz

Maximum Program

Typical Program

Minimal Program

Idle State

213

mA

270

110

90

mA

Test program includes 16-channel I/O, 10-band EQ per channel

Test program includes 2-channel I/O, 10-band EQ per channel

Power applied, DSP not enabled

18.3 18.7 19.9

Reset State

RESET

held low

Power applied,

ASYNCHRONOUS SAMPLE RATE

CONVERTERS

Dynamic Range

139

dB

A weighted, 20 Hz to 20 kHz

I/O Sample Rate

6

192

kHz

I/O Sample Rate Ratio

Total Harmonic Distortion Plus Noise

(THD + N)

1:8

7.75:1

−120

dB

CRYSTAL OSCILLATOR

Transconductance

REGULATOR

8.3

10.6 13.4

mS

V

DVDD Voltage

1.14 1.2

Regulator maintains typical output voltage up to a maximum 800 mA load;

IOVDD = 1.8 V − 5% to 3.3 V + 10%

Rev. A | Page 5 of 207

ADAU1463/ADAU1467

Data Sheet

AVDD = 3.3 V 10%, DVDD = 1.2 V 5%, PVDD = 3.3 V 10%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, T_A= −40°C to +105°C,

master clock input = 12.288 MHz, f_CORE= 294.912 MHz, I/O pins set to low drive setting, unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit Test Conditions/Comments

POWER

Supply Voltage

Analog Voltage (AVDD)

Digital Voltage (DVDD)

2.97

1.14

3.3

1.2

3.63

1.26

V

Supply for analog circuitry, including auxiliary ADCs

Supply for digital circuitry, including the DSP core, ASRCs, and

signal routing

PLL Voltage (PVDD)

IOVDD Voltage (IOVDD)

2.97

1.71

3.3

3.63

V

Supply for PLL circuitry

Supply for input/output circuitry, including pads and level

shifters

Supply Current

Analog Current (AVDD)

Idle State

Reset State

PLL Current (PVDD)

Idle State

1.36

1.0

8.3

18.4

1.66

1.1

10.2

18.7

2

mA

µA

mA

µA

40

15

40

12.288 MHz master clock; default PLL settings

Power applied, PLL not configured

Reset State

RESET

held low

Power applied,

I/O Current (IOVDD)

Dependent on the number of active serial ports, clock pins, and

characteristics of external loads

Operation State

53

22

4.1

mA

IOVDD = 3.3 V; all serial ports are clock masters

IOVDD = 1.8 V; all serial ports are clock masters

IOVDD = 1.8 V − 5% to 3.3 V + 10%

Power-Down State

Digital Current (DVDD)

ADAU1467 Operation State

Maximum Program

4.3

485

330

940

mA

Typical Program

Test program includes 16-channel I/O, 10-band EQ per channel,

all ASRCs active

Minimal Program

ADAU1463 Operation State

f_CORE= 294.912 MHz

Maximum Program

Typical Program

213

mA

Test program includes 2-channel I/O, 10-band EQ per channel

485

330

940

420

mA

Test program includes 16-channel I/O, 10-band EQ per channel,

all ASRCs active

Test program includes 2-channel I/O, 10-band EQ per channel

Minimal Program

f_CORE= 147.456 MHz

Maximum Program

Typical Program

213

mA

270

110

mA

Test program includes 16-channel I/O, 10-band EQ per channel,

all ASRCs active

Minimal Program

90

mA

Test program includes 2-channel I/O, 10-band EQ per channel

Idle State

Reset State

5.9

15.7

559

mA

ASYNCHRONOUS SAMPLE RATE CONVERTERS

Dynamic Range

139

dB

A weighted, 20 Hz to 20 kHz

I/O Sample Rate

6

192

kHz

I/O Sample Rate Ratio

THD + N

CRYSTAL OSCILLATOR

Transconductance

REGULATOR

1:8

7.75:1

−120

dB

mS

V

7.4

10.6

1.2

14.6

DVDD Voltage

1.14

Regulator maintains typical output voltage up to a maximum

800 mA load; IOVDD = 1.8 V − 5% to 3.3 V + 10%

Rev. A | Page 6 of 207

Data Sheet

ADAU1463/ADAU1467

ELECTRICAL CHARACTERISTICS

Digital Input/Output

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL INPUT

Input Voltage

IOVDD = 3.3 V

High Level (V_IH)

Low Level (V_IL)

IOVDD = 1.8 V

High Level (V_IH)

Low Level (V_IL)

Input Leakage

High Level (I_IH)

Excluding SPDIFIN, which is not a standard digital input

1.71

0

3.3

1.71

V

0.92

0

1.8

0.89

V

2

14

2

8

120

µA

pF

Digital input pins with pull-up resistor

Digital input pins with pull-down resistor

Digital input pins with no pull resistor

MCLK

SPDIFIN

Low Level (I_IL) at 0 V

−14

−2

−8

−120

Digital input pins with pull-up resistor

Digital input pins with pull-down resistor

Digital input pins with no pull resistor

MCLK

SPDIFIN

Input Capacitance (C_I)

DIGITAL OUTPUT

Output Voltage

2

IOVDD = 3.3 V

High Level (V_OH

)

3.09

0

3.3

0.26

V

I_OH= 1 mA

I_OL= 1 mA

Low Level (V_OL

)

IOVDD = 1.8 V

High Level (V_OH

Low Level (V_OL

)

1.45

0

1.8

0.33

V

)

Digital Output Pins, Output Drive

The digital output pins are driving low impedance PCB traces to a

high impedance digital input buffer

IOVDD = 1.8 V

Drive Strength Setting

Lowest

1

2

3

5

mA

The digital output pins are not designed for static current draw;

do not use these pins to drive LEDs directly

The digital output pins are not designed for static current draw;

do not use these pins to drive LEDs directly

The digital output pins are not designed for static current draw;

do not use these pins to drive LEDs directly

The digital output pins are not designed for static current draw;

do not use these pins to drive LEDs directly

Low

High

Highest

IOVDD = 3.3 V

Drive Strength Setting

Lowest

2

mA

The digital output pins are not designed for static current draw;

do not use these pins to drive LEDs directly

The digital output pins are not designed for static current draw;

do not use these pins to drive LEDs directly

The digital output pins are not designed for static current draw;

do not use these pins to drive LEDs directly

The digital output pins are not designed for static current draw;

do not use these pins to drive LEDs directly

Low

5

High

10

15

Highest

Rev. A | Page 7 of 207

ADAU1463/ADAU1467

Data Sheet

Auxiliary ADC

T_A= −40°C to +105°C, DVDD = 1.2 V 5%, AVDD = 3.3 V 10%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, unless otherwise noted.

Table 5.

Parameter

Min

Typ

10

Max

Unit

Bits

V

RESOLUTION

FULL-SCALE ANALOG INPUT

NONLINEARITY

AVDD

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

GAIN ERROR

−2.5

+2.5

LSB

kΩ

INPUT IMPEDANCE

SAMPLE RATE

200

f_CORE/6144

Hz

Rev. A | Page 8 of 207

Data Sheet

ADAU1463/ADAU1467

TIMING SPECIFICATIONS

Master Clock Input

T_A= −40°C to +105°C, DVDD = 1.2 V 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, unless otherwise noted.

Table 6.

Parameter

Min

Typ

Max

Unit Description

MASTER CLOCK INPUT (MCLK)

f_MCLK

t_MCLK

t_MCLKD

t_MCLKH

t_MCLKL

CLKOUT Jitter

CORE CLOCK

f_CORE

2.375

27.8

25

0.25 × t_MCLK

12

36

421

75

MHz MCLK frequency

ns

%

MCLK period

1

MCLK duty cycle

MCLK width high

MCLK width low

0.75 × t_MCLKns

106

ps

Cycle to cycle rms average

152

294.912

MHz System (DSP core) clock frequency; PLL feedback divider

ranges from 64 to 108

1

t_CORE

3.39

ns

System (DSP core) clock period

¹Not shown in Figure 2.

t_MCLK

MCLK

t_MCLKH

t_MCLKL

Figure 2. Master Clock Input Timing Specifications

RESET

T_A= −40°C to +105°C, DVDD = 1.2 V 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%.

Table 7.

Parameter

Min

Typ

Max

Unit

Description

t_WRST

10

ns

Reset pulse width low

t_WRST

RESET

Figure 3. Reset Timing Specification

Rev. A | Page 9 of 207

ADAU1463/ADAU1467

Data Sheet

Serial Ports

T_A= −40°C to +105°C, DVDD = 1.2 V 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, unless otherwise noted. BCLK in Table 8 refers to BCLK_

OUT3 to BCLK_OUT0 and BCLK_IN3 to BCLK_IN0. LRCLK refers to LRCLK_OUT3 to LRCLK_OUT0 and LRCLK_IN3 to LRCLK_IN0.

Table 8.

Parameter Min Typ

Max

Unit Description

f_LRCLK

192

kHz

µs

LRCLK frequency

LRCLK period

t_LRCLK

f_BCLK

t_BCLK

t_BIL

t_BIH

t_LIS

t_LIH

t_SIS

t_SIH

t_TS

5.21

24.576 MHz BCLK frequency, sample rate ranging from 6 kHz to 192 kHz

40.7

10

14.5

20

5

ns

BCLK period

BCLK low pulse width, slave mode; BCLK frequency = 24.576 MHz; BCLK period = 40.6 ns

BCLK high pulse width, slave mode; BCLK frequency = 24.576 MHz; BCLK period = 40.6 ns

LRCLK setup to BCLK_INx input rising edge, slave mode; LRCLK frequency = 192 kHz

LRCLK hold from BCLK_INx input rising edge, slave mode; LRCLK frequency = 192 kHz

SDATA_INx setup to BCLK_INx input rising edge

SDATA_INx hold from BCLK_INx input rising edge

BCLK_OUTx output falling edge to LRCLK_OUTx output timing skew, slave mode

SDATA_OUTx delay in slave mode from BCLK_OUTx output falling edge; serial outputs

function in slave mode at all valid sample rates, provided that the external circuit design

provides sufficient electrical signal integrity

5

10

35

t_SODS

t_SODM

t_TM

10

5

ns

SDATA_OUTx delay in master mode from BCLK_OUTx output falling edge

BCLK falling edge to LRCLK timing skew, master mode

t_LIH

t_BIH

t_BCLK

BCLK_INx

t_BIL

t_LIS

t_TM

LRCLK_INx

SDATA_INx

t_LRCLK

t_SIS

LEFT JUSTIFIED MODE

MSB – 1

MSB

t_SIH

(SERIAL_BYTE_x_0[4:3], (DATA_FMT) = 0b01)

t_SIS

SDATA_INx

2

I S MODE

MSB

t_SIH

(SERIAL_BYTE_x_0[4:3], (DATA_FMT) = 0b00)

SDATA_INx

RIGHT JUSTIFIED MODES

(SERIAL_BYTE_x_0[4:3], (DATA_FMT) = 0b10

OR

t_SIS

SERIAL_BYTE_x_0[4:3], (DATA_FMT) = 0b11)

t

SIH

Figure 4. Serial Input Port Timing Specifications

Rev. A | Page 10 of 207

Data Sheet

ADAU1463/ADAU1467

t_BIH

t_BCLK

t_TS

BCLK_OUTx

t_BIL

LRCLK_OUTx

SDATA_OUTx

t_LRCLK

LEFT JUSTIFIED MODE

(SERIAL_BYTE_x_0 [4:3] (DATA_FMT) = 0b01)

MSB

MSB – 1

SDATA_OUTx

2

I S MODE

MSB

(SERIAL_BYTE_x_0 [4:3] (DATA_FMT) = 0b00)

t_SODS

t_SODM

SDATA_OUTx

ALL MODES

SDATA_OUTx

RIGHT JUSTIFIED MODES

(SERIAL_BYTE_x_0 [4:3] (DATA_FMT) = 0b10

OR

SERIAL_BYTE_x_0 [4:3] (DATA_FMT) = 0b11)

LSB

MSB

Figure 5. Serial Output Port Timing Specifications

Multipurpose Pins (MPx)

T_A= −40°C to +105°C, DVDD = 1.2 V 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%.

Table 9.

Parameter

Min

Typ

Max

Unit Description

f_MP

24.576

MHz MPx maximum switching rate when pin is configured as a general-

purpose input or general-purpose output

t_MPIL

10 × t_CORE

6144 × t_CORE

sec

MPx pin input latency until high/low value is read by core; the duration

in the Max column is equal to the period of one audio sample when

the DSP is processing 6144 instructions per sample

S/PDIF Transmitter and Receiver

T_A= −40°C to +105°C, DVDD = 1.2 V 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%.

Table 10.

Parameter

Min

Typ

Max

Unit

Description

AUDIO SAMPLE RATE

Transmitter

Receiver

18

192

kHz

Audio sample rate of data output from S/PDIF transmitter

Audio sample rate of data input to S/PDIF receiver

Rev. A | Page 11 of 207

ADAU1463/ADAU1467

Data Sheet

I²C Interface—Slave

T_A= −40°C to +105°C, DVDD = 1.2 V 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%.

Table 11.

Parameter

Min

Typ

Max

Unit

kHz

µs

Description

f_SCL

1000

SCL clock frequency

SCL pulse width high

SCL pulse width low

Start and repeated start condition setup time

Start condition hold time

Data setup time

t_SCLH

t_SCLL

t_SCS

t_SCH

t_DS

0.26

0.5

0.26

50

µs

ns

t_DH

0.45

120

µs

ns

Data hold time

SCL rise time

SCL fall time

SDA rise time

t_SCLR

t_SCLF

t_SDR

t_SDF

ns

SDA fall time

t_BFT

t_SUSTO

0.5

0.26

µs

Bus free time between stop and start

Stop condition setup time

t_SCH

STOP

START

t_DS

t_SCH

t_SDR

SDA

t_SDF

t_SCLH

t_BFT

t_SCLR

SCL

t_SCS

t_SUSTO

t_SCLL

t_SCLF

t_DH

Figure 6. I²C Slave Port Timing Specifications

Rev. A | Page 12 of 207

Data Sheet

ADAU1463/ADAU1467

I²C Interface—Master

T_A= −40°C to +105°C, DVDD = 1.2 V 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%.

Table 12.

Parameter

Min

Typ

Max

Unit

kHz

µs

Description

f_SCL

1000

SCL clock frequency

SCL pulse width high

SCL pulse width low

Start and repeated start condition setup time

Start condition hold time

Data setup time

t_SCLH

t_SCLL

t_SCS

t_SCH

t_DS

0.26

0.5

0.26

50

µs

ns

t_DH

0.45

120

µs

ns

Data hold time

SCL rise time

SCL fall time

SDA rise time

t_SCLR

t_SCLF

t_SDR

t_SDF

ns

SDA fall time

t_BFT

t_SUSTO

0.5

0.26

µs

Bus free time between stop and start

Stop condition setup time

t_SCH

STOP

START

t_DS

t_SCH

t_SDR

SDA_M

t_SDF

t_BFT

t_SCLH

t_SCLR

SCL_M

t_SCS

t_SUSTO

t_SCLL

t_SCLF

t_DH

Figure 7. I²C Master Port Timing Specifications

Rev. A | Page 13 of 207

ADAU1463/ADAU1467

Data Sheet

SPI Interface—Slave

T_A= −40°C to +105°C, DVDD = 1.2 V 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%.

Table 13.

Parameter

f_{SCLK_WRITE}

f_{SCLK_READ}

t_SCLKPWL

t_SCLKPWH

t_SSS

t_SSH

t_SSPWH

t_MOSIS

t_MOSIH

Min

Typ

Max

20

Unit Description

MHz SCLK write frequency

MHz SCLK read frequency

6

21

1

2

10

1

ns

SCLK pulse width low, SCLK = 20 MHz

SCLK pulse width high, SCLK = 20 MHz

SS setup to SCLK rising edge

SS hold from SCLK rising edge

SS pulse width high

MOSI setup to SCLK rising edge

MOSI hold from SCLK rising edge

2

t_MISOD

39

MISO valid output delay from SCLK falling edge

t_SSH

t_SSS

t_SSPWH

t_SCLKPWL

t_SCLKPWH

SS

SCLK

MOSI

t_MOSIH

t_MOSIS

MISO

t_MISOD

Figure 8. SPI Slave Port Timing Specifications

Rev. A | Page 14 of 207

Data Sheet

ADAU1463/ADAU1467

SPI Interface—Master

T_A= −40°C to +105°C, DVDD = 1.2 V 5%, IOVDD = 1.8 V −5% to 3.3 V + 10%.

Table 14.

Parameter

Min

Typ

Max

Unit

Description

TIMING REQUIREMENTS

15

5

t_SSPIDM

t_HSPIDM

ns

MISO_M data input valid to SCLK_M edge (data input setup time)

SCLK_M last sampling edge to data input not valid (data input hold time)

SWITCHING CHARACTERISTICS

41.7

t_SPICLKM

f_{SCLK_M}

t_SPICHM

t_SPICLM

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

t_HDSM

ns

MHz

ns

SPI master clock cycle period

SPI master clock frequency

SCLK_M high period (f_{SCLK_M}= 24 MHz)

SCLK_M low period (f_{SCLK_M}= 24 MHz)

SCLK_M edge to data out valid (data out delay time) (f_{SCLK_M}= 24 MHz)

SCLK_M edge to data out not valid (data out hold time) (f_{SCLK_M}= 24 MHz)

SS_M (SPI device select) low to first SCLK_M edge (f_{SCLK_M}= 24 MHz)

Last SCLK_M edge to SS_M high (f_{SCLK_M}= 24 MHz)

24

17

16.9

21

36

95

SS_M

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLKM

t_HDSM

SCLK_M

(CPOL = 0)

(OUTPUT)

t_SPICLM

t

SPICHM

SCLK_M

(CPOL = 1)

(OUTPUT)

t_HDSPIDM

t_DDSPIDM

MOSI_M

(OUTPUT)

MSB

LSB

t_SSPIDM

CPHA = 1

t_HSPIDM

MISO_M

(INPUT)

MSB

VALID

LSB VALID

t

t_HDSPIDM

DDSPIDM

MOSI_M

(OUTPUT)

MSB

LSB

t_SSPIDM

t

HSPIDM

CPHA = 0

MISO_M

(INPUT)

MSB VALID

LSB VALID

Figure 9. SPI Master Port Timing Specifications

Rev. A | Page 15 of 207

ADAU1463/ADAU1467

Data Sheet

PDM Inputs

T_A= −40°C to +105°C, DVDD = 1.2 V 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%. PDM data is latched on both edges of the clock

(see Figure 10).

Table 15.

Parameter

t_MIN

10

5

t_MAX

Unit

ns

Description

t_SETUP

t_HOLD

Data setup time

Data hold time

t_SETUP

t_HOLD

Figure 10. PDM Timing Diagram

Rev. A | Page 16 of 207

Data Sheet

ADAU1463/ADAU1467

ABSOLUTE MAXIMUM RATINGS

Table 16.

While all of the following thermal coefficients can be used to

analyze the thermal performance of ADAU1463/ADAU1467,

Parameter

Rating

ψ

_JTis the most reflective of real-world applications and is

DVDD to Ground

AVDD to Ground

IOVDD to Ground

PVDD to Ground

Digital Inputs

0 V to 1.4 V

0 V to 4.0 V

DGND − 0.3 V to

IOVDD + 0.3 V

recommended as the primary approach for thermal qualification.

Table 17. Thermal Coefficients for ADAU1463/ADAU1467

Thermal Coefficient

Value

Unit

°C/W

1

ψ_JT

0.15

1

θ_JA

θ_JB

29.15

10.59

0.04

2

Maximum Ambient Temperature Range

Maximum Junction Temperature

Storage Temperature Range

Soldering (10 sec)

−40°C to +105°C

125°C

−65°C to +150°C

300°C

3

θ_JCT

4

θ_JCB

3.39

¹Based on simulation using a JEDEC 2s2p thermal test PCB with 25 thermal vias in a

JEDEC natural convection environment, as per JESD51.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

²Based on simulation using a JEDEC 2s2p thermal test PCB with 25 thermal vias in a

JEDEC junction to board environment, as per JESD51.

³Based on simulation using a cold plate attached directly to the exposed pad.

To employ the ψ_JT-based approach to thermal analysis,

1. Configure the ADAU1463/ADAU1467 in the highest power

mode of operation to be used in the application and record

the power dissipated in the device.

2. Compute the maximum allowable surface temperature,

THERMAL CONSIDERATIONS

T_{S_MAX}

:

The capabilities of the ADAU1463/ADAU1467 are such that it

is possible to configure the device in a mode where its power

dissipation can risk exceeding the absolute maximum junction

temperature. The junction temperature reached in a device is

influenced by several factors, for example, the power dissipated

in the device; the thermal efficiency of the printed circuit board

(PCB) design; and the maximum ambient temperature

supported in the application.

T_{S_MAX}= T_{J_MAX}− (Power × ψ_JT)

3. Measure the case temperature at the center of the

ADAU1463/ADAU1467 package (T_S) at the maximum

ambient temperature supported in the application and

compare to T_{S_MAX}

.

4. For safe operation, use T_S< T_{S_MAX}in the highest power

mode of operation in the application.

To ensure that the ADAU1463/ADAU1467 do not exceed the

absolute maximum junction temperature in an application,

thermal considerations must be taken from the start of the design

(for example, likely modes of operation, thermal considerations

in the PCB design (see the AN-772 Application Note), and

thermal simulations) to its finish (qualification at the maximum

ambient temperature supported in the application).

For more information, see the PCB Design Considerations

section and the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP).

ESD CAUTION

Rev. A | Page 17 of 207

ADAU1463/ADAU1467

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DGND

IOVDD

VDRIVE

SPDIFIN

SPDIFOUT

MP14

1

2

3

4

5

6

7

8

9

66 DGND

65 DVDD

64 SDATAIO4/MP20

63 SDATAIO5/MP21

62 SDATAIO6/MP22

61 SDATAIO7/MP23

60 SDATA_OUT3

59 BCLK_OUT3

58 LRCLK_OUT3/MP9

57 SDATA_OUT2

56 BCLK_OUT2

55 LRCLK_OUT2/MP8

54 MP7

MP15

AGND

AVDD

ADAU1467/

ADAU1463

AUXADC0 10

AUXADC1 11

AUXADC2 12

AUXADC3 13

AUXADC4 14

AUXADC5 15

AUXADC6 16

AUXADC7 17

PGND 18

TOP VIEW

(Not to Scale)

53 MP6

52 SDATA_OUT1

51 BCLK_OUT1

50 LRCLK_OUT1/MP5

49 SDATA_OUT0

48 BCLK_OUT0

47 LRCLK_OUT0/MP4

46 IOVDD

PVDD 19

PLLFILT 20

DGND 21

IOVDD 22

45 DGND

NOTES

1. THE EXPOSED PAD MUST BE GROUNDED BY SOLDERING IT TO A COPPER SQUARE

OF EQUIVALENT SIZE ON THE PCB. IDENTICAL COPPER SQUARES MUST EXIST ON

ALL LAYERS OF THE BOARD, CONNECTED BY VIAS, AND THEY MUST BE CONNECTED

TO A DEDICATED COPPER GROUND LAYER WITHIN THE PCB.

Figure 11. Pin Configuration

Table 18. Pin Function Descriptions

No.

Internal Pull

Resistor

Mnemonic

Description

1

DGND

None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane. See the Power Supply Bypass Capacitors section and the

Grounding section.

2

3

IOVDD

VDRIVE

None

Input/Output Supply, 1.8 V − 5% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to

Pin 1 (DGND). See the Power Supply Bypass Capacitors section and the Grounding section.

Positive Negative Positive (PNP) Bipolar Junction Transistor Base Drive Bias Pin for the Digital

Supply Regulator. Connect VDRIVE to the base of an external PNP pass transistor (ON Semi

NSS1C300ET4G is recommended). If an external supply is provided directly to DVDD, connect

the VDRIVE pin to ground.

4

5

SPDIFIN

None

Input to the Integrated Sony/PDIF Receiver. Disconnect this pin when not in use. This pin is

biased internally to IOVDD/2.

Output from the Integrated Sony/PDIF Transmitter. Disconnect this pin when not in use. This

pin is biased internally to IOVDD/2.

SPDIFOUT

Configurable

6

7

8

MP14

MP15

AGND

Configurable

None

Multipurpose, General-Purpose Input/Output (GPIO) 14. Disconnect this pin when not in use.

Multipurpose, GPIO 15. Disconnect this pin when not in use.

Analog Ground Reference for the Auxiliary ADC. Tie all DGND, AGND, and PGND pins directly

together in a common ground plane. See the Power Supply Bypass Capacitors section and

the Grounding section.

9

AVDD

None

Analog Supply for the Auxiliary ADC. This supply muust be 3.3 V 10%. Bypass this pin with

decoupling capacitors to Pin 8 (AGND). See the Power Supply Bypass Capacitors section and

the Grounding section.

Rev. A | Page 18 of 207

Data Sheet

ADAU1463/ADAU1467

No.

Internal Pull

Resistor

Mnemonic

Description

10

AUXADC0

None

Auxiliary ADC Input Channel 0. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

Auxiliary ADC Input Channel 1. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

Auxiliary ADC Input Channel 2. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

Auxiliary ADC Input Channel 3. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

Auxiliary ADC Input Channel 4. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

Auxiliary ADC Input Channel 5. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

Auxiliary ADC Input Channel 6. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

Auxiliary ADC Input Channel 7. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

PLL Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common

ground plane. See the Power Supply Bypass Capacitors section and the Grounding section.

PLL Supply. This supply must be 3.3 V 10%. Bypass this pin with decoupling capacitors to

Pin 18 (PGND). See the Power Supply Bypass Capacitors section and the Grounding section.

PLL Filter. The voltage on the PLLFILT pin, which is internally generated, is typically between

1.65 V and 2.10 V.

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane. See the Power Supply Bypass Capacitors section and the

Grounding section.

11

12

13

14

15

16

17

18

19

20

21

AUXADC1

AUXADC2

AUXADC3

AUXADC4

AUXADC5

AUXADC6

AUXADC7

PGND

PVDD

PLLFILT

DGND

22

23

IOVDD

DGND

None

Input/Output Supply, 1.8 V − 5% to 3.3 V + 10%. Bypass this pin to Pin 21 (DGND) with decoupling

capacitors. See the Power Supply Bypass Capacitors section and the Grounding section.

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane. See the Power Supply Bypass Capacitors section and the

Grounding section.

24

25

DVDD

None

Digital Supply. This supply must be 1.2 V 5%. This pin can be supplied externally or by using

the internal regulator and external pass transistor. Bypass this pin to Pin 23 (DGND) with

decoupling capacitors. See the Power Supply Bypass Capacitors section and the

Grounding section.

Crystal Oscillator Input (XTALIN)/Master Clock Input to the PLL (MCLK). This pin can be

supplied directly or generated by driving a crystal with the internal crystal oscillator via Pin 26

(XTALOUT). If a crystal is used, refer to the circuit shown in Figure 14.

XTALIN/MCLK

26

27

XTALOUT

CLKOUT

None

Crystal Oscillator Output for Driving an External Crystal. If a crystal is used, refer to the circuit

shown in Figure 14. Disconnect this pin when not in use.

Master Clock Output. This pin drives a master clock signal to other ICs in the system. CLKOUT

can be configured to output a clock signal with a frequency of 1×, 2×, 4×, or 8× the frequency of

the divided clock signal being input to the PLL. Disconnect this pin when not in use.

Configurable

28

29

RESET

DGND

Pull-down

None

Active Low Reset Input. A reset is triggered on a high to low edge and exited on a low to high

edge. A reset event sets all RAMs and registers to their default values.

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane. See the Power Supply Bypass Capacitors section and the

Grounding section.

30

31

SCL2_M/

MP24

Pull-up; can be

disabled by a

write to control

register

I²C Master 2 Serial Clock Port (SCL2_M)/Multipurpose, GPIO24 (MP24). When in I²C master

mode, this pin functions as an open-collector output and drives a serial clock to slave devices

on the I²C bus. When in I²C master mode, this pin must have a 2.0 kΩ pull-up resistor to IOVDD.

When the second master control port is not being used and this pin is not needed as a GPIO,

leave it disconnected.

I²C Master 2 Serial Data Port (SCL2_M)/Multipurpose, GPIO25 (MP25). When in I²C master

mode, this pin functions as a bidirectional, open-collector data line between the I²C master

port and slave devices on the I²C bus. Use a 2.0 kΩ pull-up resistor to IOVDD on the line

connected to this pin. Disconnect this pin when not in use.

SDA2_M/

MP25

Pull-up; can be

disabled by a

write to control

register

Rev. A | Page 19 of 207

ADAU1463/ADAU1467

Data Sheet

No.

Internal Pull

Resistor

Mnemonic

Description

32

SS_M/MP0

Pull-up;

nominally

250 kΩ; can be

disabled by a

write to control

register

SPI Master/Slave Select Port (SS_M)/Multipurpose, GPIO0 (MP0). When in SPI master mode,

this pin acts as the slave select signal to slave devices on the SPI bus. The pin must go low at

the beginning of a master SPI transaction and high at the end of a transaction. This pin has an

internal pull-up resistor that is nominally 250 kΩ. When the SELFBOOT pin is held high and

the RESET pin transitions from low to high, Pin 32 sets the communications protocol for self

boot operation. If this pin is left floating, the SPI communications protocol is used for self

boot operation. If this pin has a 10 kΩ pull-down resistor to DGND, the I²C communications

protocol is used for self boot operation. When self boot operation is not used and this pin is

not needed as a GPIO, leave it disconnected.

33

34

MOSI_M/MP1

Pull-up; can be

disabled by a

write to control

register

Pull-up; can be

disabled by a

write to control

register

SPI Master Data Output Port (MOSI_M)/Multipurpose, GPIO1 (MP1). When in SPI master

mode, this pin sends data from the SPI master port to slave devices on the SPI bus.

Disconnect this pin when not in use.

SCL_M/

SCLK_M/MP2

I²C Master Serial Clock Port (SCL_M)/SPI Master Mode Serial Clock (SCLK_M)/Multipurpose,

GPIO2 (MP2). When in I²C master mode, this pin functions as an open-collector output and

drives a serial clock to slave devices on the I²C bus. Use a 2.0 kΩ pull-up resistor to IOVDD on

the line connected to this pin. When in SPI master mode, this pin drives the clock signal to

slave devices on the SPI bus. Disconnect this pin when not in use.

35

SDA_M/

MISO_M/MP3

Pull-up; can be

disabled by a

write to control

register

I²C Master Port Serial Data (SDA_M)/SPI Master Mode Data Input (MISO_M)/Multipurpose,

GPIO3 (MP3). When in I²C master mode, this pin functions as a bidirectional open-collector

data line between the I²C master port and slave devices on the I²C bus; use a 2.0 kΩ pull-up

resistor to IOVDD on the line connected to this pin. When in SPI master mode, this pin receives

data from slave devices on the SPI bus. Disconnect this pin when not in use.

36

37

38

DGND

None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane. See the Power Supply Bypass Capacitors section and the

Grounding section.

Input/Output Supply, 1.8 V − 5% to 3.3 V + 10%. Bypass this pin to Pin 36 (DGND) with

decoupling capacitors. See the Power Supply Bypass Capacitors section and the

Grounding section.

SPI Slave Data Output Port (MISO)/I²C Slave Serial Data Port (SDA). In SPI slave mode, this pin

outputs data to the master device on the SPI bus. In I²C slave mode, this pin functions as a

bidirectional open-collector data line between the I²C slave port and the master device on

the I²C bus. Use a 2.0 kΩ pull-up resistor to IOVDD on the line connected to this pin. When

this pin is not in use, connect it to IOVDD with a 10.0 kΩ pull-up resistor.

IOVDD

MISO/SDA

Pull-up; can be

disabled by a

write to control

register

39

SCLK/SCL

Pull-up; can be

disabled by a

write to control

register

SPI Slave Port Serial Clock (SCLK)/I²C Slave Port Serial Clock (SCL). In SPI slave mode, this pin

receives the serial clock signal from the master device on the SPI bus. In I²C slave mode, this

pin receives the serial clock signal from the master device on the I²C bus. Use a 2.0 kΩ pull-up

resistor to IOVDD on the line connected to this pin. When this pin is not in use, connect it to

IOVDD with a 10.0 kΩ pull-up resistor.

40

41

MOSI/ADDR1

SS/ADDR0

Pull-up; can be

disabled by a

write to control

register

SPI Slave Port Data Input (MOSI)/I²C Slave Port Address MSB (ADDR1). In SPI slave mode, this pin

receives a data signal from the master device on the SPI bus. In I²C slave mode, this pin acts

as an input and sets the chip address of the I²C slave port, in conjunction with Pin 41 (SS/ADDR0).

Pull-up, nomi-

SPI Slave Port Slave Select (SS)/I²C Slave Port Address LSB (ADDR0). In SPI slave mode, this pin

nally 250 kΩ; can receives the slave select signal from the master device on the SPI bus. In I²C slave mode, this pin

be disabled by a

write to control

register

acts as an input and sets the chip address of the I²C slave port in conjunction with Pin 40

(MOSI/ADDR1).

42

43

SELFBOOT

DVDD

Pull-up

None

Self Boot Select. This pin allows the device to perform a self boot, in which it loads its RAM

and register settings from an external EEPROM. Connecting Pin 37 to logic high (IOVDD)

initiates a self boot operation the next time there is a rising edge on Pin 24 (RESET). When this

pin is connected to ground, no self boot operation is initiated. This pin can be connected to

IOVDD or to ground either directly or pulled up or down with a 1.0 kΩ or larger resistor.

Digital Supply. This supply must be 1.2 V 5%. This pin can be supplied externally or by using

the internal regulator and external pass transistor. Bypass this pin to Pin 36 (DGND) with

decoupling capacitors. See the Power Supply Bypass Capacitors section and the

Grounding section.

Rev. A | Page 20 of 207

Data Sheet

ADAU1463/ADAU1467

No.

Internal Pull

Resistor

Mnemonic

Description

44

DGND

None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane. See the Power Supply Bypass Capacitors section and the

Grounding section.

45

DGND

IOVDD

None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane. See the Power Supply Bypass Capacitors section and the

Grounding section.

Input/Output Supply, 1.8 V − 5% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to

Pin 45 (DGND). See the Power Supply Bypass Capacitors section and the Grounding section.

Frame Clock, Serial Output Port 0 (LRCLK_OUT0)/Multipurpose, GPIO4 (MP4). This pin is

bidirectional, with the direction depending on whether Serial Output Port 0 is a master or

slave. Disconnect this pin when not in use.

46

47

None

LRCLK_OUT0/

MP4

Configurable

48

49

50

BCLK_OUT0

Configurable

Bit Clock, Serial Output Port 0. This pin is bidirectional, with the direction depending on

whether the Serial Output Port 0 is a master or slave. Disconnect this pin when not in use.

Serial Data Output Port 0 (Channel 0 to Channel 15). Capable of 2-channel, 4-channel, 8-channel,

and 16-channel modes. Disconnect this pin when not in use.

Frame Clock, Serial Output Port 1 (LRCLK_OUT1)/Multipurpose, GPIO5 (MP5). This pin is

bidirectional, with the direction depending on whether Serial Output Port 1 is a master or

slave. Disconnect this pin when not in use.

SDATA_OUT0

LRCLK_OUT1/

MP5

51

52

BCLK_OUT1

Configurable

Bit Clock, Serial Output Port 1. This pin is bidirectional, with the direction depending on

whether Output Serial Port 1 is a master or slave. Disconnect this pin when not in use.

Serial Data Output Port 1 (Channel 16 to Channel 31). Capable of 2-channel, 4-channel, 8-channel,

and 16-channel modes. Disconnect this pin when not in use.

SDATA_OUT1

53

54

55

MP6

MP7

LRCLK_OUT2/

MP8

Configurable

Multipurpose, GPIO 6. Disconnect this pin when not in use.

Multipurpose, GPIO 7. Disconnect this pin when not in use.

Frame Clock, Serial Output Port 2 (LRCLK_OUT2)/Multipurpose, GPIO8 (MP8). This pin is

bidirectional, with the direction depending on whether Serial Output Port 2 is a master or

slave. Disconnect this pin when not in use.

56

57

58

BCLK_OUT2

Configurable

Bit Clock, Serial Output Port 2. This pin is bidirectional, with the direction depending on

whether Serial Output Port 2 is a master or slave. Disconnect this pin when not in use.

Serial Data Output Port 2 (Channel 32 to Channel 39). Capable of 2-channel, 4-channel, 8-channel,

and flexible TDM modes. Disconnect this pin when not in use.

Frame Clock, Serial Output Port 3 (LRCLK_OUT3)/Multipurpose, GPIO9 (MP9). This pin is

bidirectional, with the direction depending on whether Serial Output Port 3 is a master or

slave. Disconnect this pin when not in use.

SDATA_OUT2

LRCLK_OUT3/

MP9

59

60

61

BCLK_OUT3

Configurable

Bit Clock, Serial Output Port 3. This pin is bidirectional, with the direction depending on

whether Serial Output Port 3 is a master or slave. Disconnect this pin when not in use.

Serial Data Output Port 3 (Channel 40 to Channel 47). Capable of 2-channel, 4-channel,

8-channel, and flexible TDM modes. Disconnect this pin when not in use.

Serial Data Assignable Input/Output Port 7. Capable of 2-channel, 4-channel, 8-channel, or

16-channel mode, synchronous with a serial input or serial output port. Disconnect this pin

when not in use.

SDATA_OUT3

SDATAIO7/

MP23

62

63

64

65

66

SDATAIO6/

MP22

Configurable

None

Serial Data Assignable Input/Output Port 6. Capable of 2-channel, 4-channel, 8-channel, or

16-channel mode, synchronous with a serial input or serial output port. Disconnect this pin

when not in use.

Serial Data Assignable Input/Output Port 5. Capable of 2-channel, 4-channel, 8-channel, or

16-channel mode, synchronous with a serial input or serial output port. Disconnect this pin

when not in use.

Serial Data Assignable Input/Output Port 4. Capable of 2-channel, 4-channel, 8-channel, or

16-channel mode, synchronous with a serial input or serial output port. Disconnect this pin

when not in use.

Digital Supply. This supply must be 1.2 V 5%. This pin can be supplied externally or by using

the internal regulator and external pass transistor. Bypass Pin 65 with decoupling capacitors to

Pin 66 (DGND). See the Power Supply Bypass Capacitors section and the Grounding section.

SDATAIO5/

MP21

SDATAIO4/

MP20

DVDD

DGND

None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane. See the Power Supply Bypass Capacitors section and the

Grounding section.

Rev. A | Page 21 of 207

ADAU1463/ADAU1467

Data Sheet

No.

Internal Pull

Resistor

Mnemonic

Description

67

DGND

None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane. See the Power Supply Bypass Capacitors section and the

Grounding section.

68

69

IOVDD

None

Input/Output Supply, 1.8 V − 5% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to

Pin 67 (DGND). See the Power Supply Bypass Capacitors section and the Grounding section.

Serial Data Assignable Input/Output Port 3. Capable of 2-channel, 4-channel, 8-channel, or

16-channel mode, synchronous with a serial input or serial output port. Disconnect this pin

when not in use.

SDATAIO3/

MP19

Configurable

70

71

72

SDATAIO2/

MP18

Configurable

Serial Data Assignable Input/Output Port 2. Capable of 2-channel, 4-channel, 8-channel, or

16-channel mode, synchronous with a serial input or serial output port. Disconnect this pin

when not in use.

Serial Data Assignable Input/Output Port 1. Capable of 2-channel, 4-channel, 8-channel, or

16-channel mode, synchronous with a serial input or serial output port. Disconnect this pin

when not in use.

Serial Data Assignable Input/Output Port 1. Capable of 2-channel, 4-channel, 8-channel, or

16-channel mode, synchronous with a serial input or serial output port. Disconnect this pin

when not in use.

SDATAIO1/

MP17

SDATAIO0/

MP16

73

74

BCLK_IN0

Configurable

Bit Clock, Serial Input Port 0. This pin is bidirectional, with the direction depending on

whether Serial Input Port 0 is a master or slave. Disconnect this pin when not in use.

Frame Clock, Serial Input Port 0 (LRCLK_IN0)/Multipurpose, GPIO10 (MP10). This pin is

bidirectional, with the direction depending on whether Serial Input Port 0 is a master or

slave. Disconnect this pin when not in use.

LRCLK_IN0/

MP10

75

76

77

SDATA_IN0

BCLK_IN1

Configurable

Serial Data Input Port 0 (Channel 0 to Channel 15). Capable of 2-channel, 4-channel, 8-channel, or

16-channel mode. Disconnect this pin when not in use.

Bit Clock, Serial Input Port 1. This pin is bidirectional, with the direction depending on

whether the Serial Input Port 1 is a master or slave. Disconnect this pin when not in use.

Frame Clock, Serial Input Port 1 (LRCLK_IN1)/Multipurpose, GPIO11 (MP11). This pin is

bidirectional, with the direction depending on whether the Serial Input Port 1 is a master or

slave. Disconnect this pin when not in use.

LRCLK_IN1/

MP11

78

79

80

81

82

SDATA_IN1

THD_M

Configurable

None

Serial Data Input Port 1 (Channel 16 to Channel 31). Capable of 2-channel, 4-channel,

8-channel, or 16-channel mode. Disconnect this pin when not in use.

Thermal Diode Negative Input. Connect this pin to the negative diode (D− pin) of an external

temperature sensor IC. Disconnect this pin when not in use.

Thermal Diode Positive Input. Connect this pin to the positive diode (D+ pin) of an external

temperature sensor IC. Disconnect this pin when not in use.

Bit Clock, Serial Input Port 2. This pin is bidirectional, with the direction depending on

whether the Serial Input Port 2 is a master or slave. Disconnect this pin when not in use.

THD_P

None

BCLK_IN2

Configurable

LRCLK_IN2/

MP12

Frame Clock, Input Serial Port 2 (LRCLK_IN2)/Multipurpose, GPIO12 (MP12). This pin is

bidirectional, with the direction depending on whether Serial Input Port 2 is a master or

slave. Disconnect this pin when not in use.

83

84

85

SDATA_IN2

BCLK_IN3

Configurable

Serial Data Input Port 2 (Channel 32 to Channel 39). Capable of 2-channel, 4-channel,

8-channel, or flexible TDM mode. Disconnect this pin when not in use.

Bit Clock, Input Serial Port 3. This pin is bidirectional, with the direction depending on

whether Input Serial Port 3 is a master or slave. Disconnect this pin when not in use.

Frame Clock, Serial Input Port 3 (LRCLK_IN3)/Multipurpose, GPIO13 (MP13). This pin is

bidirectional, with the direction depending on whether Serial Input Port 3 is a master or

slave. Disconnect this pin when not in use.

LRCLK_IN3/

MP13

86

87

SDATA_IN3

DVDD

Configurable

None

Serial Data Input Port 3 (Channel 40 to Channel 47). Capable of 2-channel, 4-channel,

8-channel, or flexible TDM mode. Disconnect this pin when not in use.

Digital Supply. This supply must be 1.2 V 5%. This pin can be supplied externally or by using

the internal regulator and external pass transistor. Bypass with decoupling capacitors to Pin 88

(DGND). See the Power Supply Bypass Capacitors section and the Grounding section.

88

DGND

None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane. See the Power Supply Bypass Capacitors section and the

Grounding section.

Rev. A | Page 22 of 207

Data Sheet

ADAU1463/ADAU1467

No.

Internal Pull

Resistor

Mnemonic

Description

EP

None

Exposed Pad. The exposed pad must be grounded by soldering it to a copper square of equivalent

size on the PCB. Identical copper squares must exist on all layers of the board, connected by vias,

and they must be connected to a dedicated copper ground layer within the PCB. See Figure 86

and Figure 87.

Rev. A | Page 23 of 207

ADAU1463/ADAU1467

Data Sheet

THEORY OF OPERATION

SYSTEM BLOCK DIAGRAM

CONTROL CIRCUITRY

(PUSH BUTTONS,

ROTARY

ENCODERS,

POTENTIOMETERS)

SYSTEM HOST

CONTROLLER

(MICROCONTROLLER,

MICROPROCESSOR)

CRYSTAL

RESONATOR

PLL

SELF BOOT

MEMORY

LOOP

FILTER

ADAU1463/

ADAU1467

POWER

SUPPLY

REGULATOR

2

I C/SPI

GPIO/

AUX ADC

CLOCK

OSCILLATOR

SLAVE

MASTER

PLL

TEMPERATURE

SENSOR

CONTROLLER

TEMPERATURE

SENSOR

INPUT AUDIO

ROUTING MATRIX

OUTPUT AUDIO

ROUTING MATRIX

AUDIO SOURCES

AUDIO SINKS

S/PDIF

S/PDIF OPTICAL

TRANSMITTER

S/PDIF OPTICAL

RECEIVER

TRANSMITTER

294.912MHz

PROGRAMMABLE AUDIO

PROCESSING CORE

AUDIO

ADCS

AUDIO

DACS

SERIAL DATA

INPUT PORTS

(×4)

RAM, ROM, WATCHDOG,

MEMORY PARITY CHECK

SERIAL DATA

OUTPUT PORTS

(×4)

LPF

MEMS

DIGITAL

AUDIO

SINKS

DIGITAL

MICROPHONES

8× 2-CHANNEL

ASYNCHRONOUS

SAMPLE RATE

CONVERTERS

MIC INPUT

INPUT

CLOCK

DOMAINS

(×4)

OUTPUT

CLOCK

DOMAINS

(×4)

DIGITAL

AUDIO

SOURCES

DEJITTER AND

CLOCK GENERATOR

Figure 12. System Block Diagram with Example Connections to External Components

The input audio routing matrix and output audio routing matrix

allow the user to multiplex inputs from multiple sources that are

running at various sample rates to or from the SigmaDSP core,

and then to pass them on to the desired hardware outputs. This

multiplexing drastically reduces the complexity of signal routing

and clocking issues in the audio system. The audio subsystem

includes eight stereo ASRCs, S/PDIF input and output, and serial

audio data ports supporting two to 16 channels in formats such

as I²S and time division multiplexing (TDM). Any of the inputs

can be routed to the SigmaDSP core or to any of the ASRCs.

Similarly, the output signals can be taken from the SigmaDSP core,

any of the ASRC outputs, the serial inputs, the PDM microphones,

or the S/PDIF receiver. This routing scheme, which can be

modified at any time using control registers, allows maximum

system flexibility without requiring hardware design changes.

OVERVIEW

The ADAU1463/ADAU1467 are enhanced audio processors with

48 channels of input and output. They include options for the

hardware routing of audio signals between the various inputs,

outputs, SigmaDSP core, and integrated sample rate converters.

The SigmaDSP core features full 32-bit processing (that is, 64-bit

processing in double precision mode) with an 80-bit arithmetic

logic unit (ALU). By using a quadruple multiply accumulator

(MAC) data path, the ADAU1463/ADAU1467 can execute more

than 1.2 billion MAC operations per second, which allows

processing power that far exceeds predecessors in the SigmaDSP

family of products. The powerful DSP core can process over

3000 double precision biquad filters or 24,000 FIR filter taps per

sample at the standard 48 kHz audio sampling rate. Other

features, including synchronous parameter loading for ensuring

filter stability and 100% code efficiency with the SigmaStudio

tools, reduce complexity in audio system development. The

SigmaStudio library of audio processing algorithms allows

system designers to compensate for real-world limitations of

speakers, amplifiers, and listening environments, through

speaker equalization, multiband compression, limiting, and

third party branded algorithms.

Two serial input ports and two serial output ports can operate

as pairs in a special flexible TDM mode, allowing the user to

assign byte specific locations independently to audio streams at

varying bit depths. This mode ensures compatibility with

codecs that use similar flexible TDM streams.

The DSP core is optimized for audio processing, and it can

process audio at sample rates of up to 192 kHz. The program

Rev. A | Page 24 of 207

Data Sheet

ADAU1463/ADAU1467

and parameter/data RAMs can be loaded with a custom audio

processing signal flow built with the SigmaStudio graphical

programming software from Analog Devices, Inc., which is

available for download at www.analog.com. The values that are

stored in the parameter RAM can control individual signal

processing blocks, such as infinite impulse response (IIR) and

finite impulse response (FIR) equalization filters, dynamics

processors, audio delays, and mixer levels. A software safeload

feature allows transparent parameter updates and prevents

clicks on the output signals.

Algorithms are created in SigmaStudio by dragging and

dropping signal processing cells from the library, connecting

them together in a flow, compiling the design, and downloading

the executable program and parameters to the SigmaDSP

memory through the control port. The tasks of linking,

compiling, and downloading the project are all handled

automatically by the software.

The signal processing cells included in the library range from

primitive operations, such as addition and gain, to large and

highly optimized building blocks. For example, the libraries

include the following:

Reliability features, such as memory parity checking and a

program counter watchdog, help ensure that the system can

detect and recover from any errors related to memory corruption.

•

Single and double precision biquad filter

Single-channel and multichannel dynamics processors with

peak or rms detection

On the ADAU1463/ADAU1467, the audio data in an S/PDIF

stream can be routed through an ASRC for processing in the

DSP or can be sent directly to a serial audio output. Other

components of the stream, including status and user bits, are

not lost and can be used in algorithm or output on the MPx

pins. The user can also independently program the nonaudio

data that is embedded in the output signal of the S/PDIF

transmitter.

•

Mixer and splitter

Tone and noise generator

Fixed and variable gain

Loudness

Delay

Stereo enhancement

Dynamic bass boost

Noise and tone source

Level detector

The 26 MPx pins are available to provide a simple user interface

without the need for an external microcontroller. These multi-

purpose pins are available to input external control signals and

output flags or controls to other devices in the system. As inputs,

the MPx pins can be connected to push buttons, switches,

rotary encoders, or other external control circuitry to control

the internal signal processing program. When configured as

outputs, these pins can drive LEDs (with a buffer), output flags

to a microcontroller, control other ICs, or connect to other

external circuitry in an application. In addition to the

MPx pin control and conditioning

FFT and frequency domain processing algorithms

Analog Devices continuously develops new processing

algorithms and provides proprietary and third party algorithms

for applications such as matrix decoding, bass enhancement,

and surround virtualizers.

Several power saving mechanisms are available, including

programmable pad strength for digital I/O pins and the ability

to power down unused subsystems.

multipurpose pins, eight dedicated input pins (AUXADC7 to

AUXADC0) are connected to an auxiliary ADC for use with

analog controls such as potentiometers or system voltages.

Fabricated on a single monolithic integrated circuit for

operation over the −40°C to +105°C temperature range, the

device is housed in an 88-lead LFCSP package with an exposed

pad to assist in heat dissipation.

The SigmaStudio software programs and controls the device

through the control port. In addition to designing and tuning a

signal flow, the software can configure all of the DSP registers in

real time and download a new program and parameters into the

external self boot EEPROM. The SigmaStudio graphical

interface allows anyone with audio processing knowledge to

design a DSP signal flow and export production quality code

without the need for writing text code. The software provides

enough flexibility and programmability to allow an experienced

DSP programmer to have in depth control of the design.

The device can be controlled in one of two operational modes,

as follows:

•

Executable code and parameters can be loaded and

dynamically updated through the SPI/I²

C port via

SigmaStudio or a microcontroller in the system.

The DSP can self boot from an external EEPROM in

a system with no microcontroller.

•

Rev. A | Page 25 of 207

ADAU1463/ADAU1467

Data Sheet

When all four POR circuits signal that the power-on conditions

are met, a reset synchronizer circuit releases the internal digital

circuitry from reset, provided that the following conditions

are met:

INITIALIZATION

Power-Up Sequence

The first step in the initialization sequence is to power up the

device. First, apply voltage to the power pins. All the power pins

can be supplied simultaneously. If the power pins are not supplied

simultaneously, supply IOVDD first because the internal ESD

protection diodes are referenced to the IOVDD voltage. AVDD,

DVDD, and PVDD can be supplied at the same time as IOVDD

or after, but they must not be supplied prior to IOVDD. The

order in which AVDD, DVDD, and PVDD are supplied does

not matter.

•

A valid MCLK signal is provided to the digital circuitry

and the PLL.

RESET

•

The

pin is high.

When the internal digital circuitry becomes active, the DSP

core runs eight lines of initialization code stored in read only

memory (ROM), requiring eight cycles of the MCLK signal. For

a 12.288 MHz MCLK input, this process takes 650 ns.

DVDD, the power supply for the internal digital logic, can be

regulated externally and supplied directly, or it can by generated

from IOVDD using an internal voltage regulator. When the

internal regulator is not used and DVDD is directly supplied,

no special sequence is required when providing the proper

voltages to AVDD, DVDD, and PVDD.

After the ROM program completes its execution, the PLL is

ready to be configured using register writes to Register 0xF000

(PLL_CTRL0), Register 0xF001 (PLL_CTRL1), Register 0xF002

(PLL_CLK_SRC), and Register 0xF003 (PLL_ENABLE).

When the PLL is configured and enabled, the PLL starts to lock

to the incoming master clock signal. The absolute maximum

PLL lock time is 32 × 1024 = 32,768 clock cycles on the clock

signal (after the input prescaler), which is fed to the input of the

PLL. In a standard 48 kHz use case, the PLL input clock

frequency after the prescaler is 3.072 MHz; therefore, the

maximum PLL lock time is 10.666 ms.

When the internal regulator is used, DVDD is derived from

IOVDD in combination with an external pass transistor, after

AVDD, IOVDD, and PVDD are supplied. See the Power

Supplies section for more information.

Each power supply domain has its own power-on reset (POR)

circuits (also known as power OK circuits) to ensure that the

level shifters attached to each power domain can be initialized

properly. AVDD and PVDD must reach their nominal level

before the auxiliary ADC and PLL can be used, respectively.

Typically, the PLL locks much faster than 10.666 ms. In most

systems, the PLL locks within about 3.5 ms. The PLL_LOCK

register (Address 0xF004) can be polled via the control port

until Bit 0 (PLL_LOCK) goes high, signifying that the PLL lock

is complete.

While the PLL is attempting to lock to the input clock, the I²C

slave and SPI slave control ports are inactive; therefore, no other

registers are accessible over the control port. While the PLL is

attempting to lock, all attempts to write to the control port fail.

However, the AVDD and PVDD supplies have no role in the rest

of the power-up sequence. After the AVDD power reaches its

nominal threshold, the regulator becomes active and begins to

charge up the DVDD supply. The DVDD supply also has a POR

circuit to ensure that the level shifters initialize during power-up.

The POR signals are combined into three global level shifter

resets that properly initialize the signal crossings between each

separate power domain and DVDD.

Figure 13 shows an example power-up sequence with all relevant

signals labeled. If possible, apply the required voltage to all four

power supply domains (IOVDD, AVDD, PVDD, and DVDD)

simultaneously. If the power supplies are separate, IOVDD, which

is the reference for the ESD protection diodes that are situated

inside the input and output pins, must be applied first to avoid

stressing these diodes. PVDD, AVDD, and DVDD can then be

supplied in any order (see the System Initialization Sequence

section for more information). Note that the gray areas in

Figure 13 represent clock signals.

The digital circuits remain in reset until the IOVDD to DVDD

level shifter reset is released. At that point, the digital circuits

exit reset.

When a crystal is in use, the crystal oscillator circuit must provide

a stable master clock to the XTALIN/MCLK pin by the time the

PVDD supply reaches its nominal level. The XTALIN/MCLK pin is

restricted from passing into the PLL circuitry until the DVDD

POR signal becomes active and the PVDD to DVDD level

shifter is initialized.

Rev. A | Page 26 of 207

Data Sheet

ADAU1463/ADAU1467

STEP

IOVDD PINS

PVDD PIN

1

2

3

4

5

6

7

8

9

10

11

12

AVDD PIN

DVDD PINS

IOVDD TO DVDD LEVEL SHIFTER ENABLE

(INTERNAL)

PVDD TO DVDD LEVEL SHIFTER ENABLE

(INTERNAL)

AVDD TO DVDD LEVEL SHIFTER ENABLE

(INTERNAL)

RESET PIN

RESET

(INTERNAL)

MASTER POWER-ON RESET

(INTERNAL)

XTALIN/MCLK PIN

CLOCK INPUT TO THE PLL

PLL OUTPUT CLOCK

DESCRIPTION

Figure 13. Power Sequencing and POR Timing Diagram for a System with Separate Power Supplies

Rev. A | Page 27 of 207

ADAU1463/ADAU1467

Data Sheet

Table 19 contains an example series of register writes used to

configure the system at startup. The contents of the data

column may vary depending on the system configuration. The

configuration that is listed in Table 19 represents the default

initialization sequence for project files generated in SigmaStudio.

System Initialization Sequence

Before the IC can process the audio in the DSP, the following

initialization sequence must be completed.

1. If possible, apply the required voltage to all four power

supply domains (IOVDD, AVDD, PVDD, and DVDD)

simultaneously. If simultaneous application is not possible,

supply IOVDD first to prevent damage or reduced

operating lifetime. If using the on-board regulator, AVDD

and PVDD can be supplied in any order, and DVDD is

then generated automatically. If not using the on-board

regulator, AVDD, PVDD, and DVDD can be supplied in

any order following IOVDD.

2. Start providing a master clock signal to the XTALIN/MCLK

pin, or, if using the crystal oscillator, let the crystal oscillator

start generating a master clock signal. The master clock

signal must be valid when the DVDD supply stabilizes.

3. If the SELFBOOT pin is pulled high, a self boot sequence

initiates on the master control port. Wait until the self boot

operation is complete.

Recommended Program/Parameter Loading Procedure

When writing large amounts of data to the program or parameter

RAM in direct write mode (such as when downloading the

initial contents of the RAMs from an external memory), use the

hibernate register (Address 0xF400) to disable the processor

core, thus preventing unpleasant noises from appearing at the

audio output. When small amounts of data are transmitted

during real-time operation of the DSP (such as when updating

individual parameters), the software safeload mechanism can be

used (see the Software Safeload section).

4. If SPI slave control mode is desired, toggle the SS/ADDR0 pin

three times. Ensure that each toggle lasts at least the duration

of one cycle of the master clock being input to the XTALIN/

MCLK pin. When the SS/ADDR0 line rises for the third

time, the slave control port is then in SPI mode.

5. Execute the register and memory write sequence that is

required to configure the device in the proper operating

mode.

Rev. A | Page 28 of 207

Data Sheet

ADAU1463/ADAU1467

Table 19. Example System Initialization Register Write Sequence¹

Address

Data

Register/Memory

Description

N/A

Toggle SS/ADDR0 three times to enable SPI slave mode, if necessary.

Enter soft reset.

Exit soft reset.

Set feedback divider to 96 (this is the default power-on setting).

Set PLL input clock divider to 4.

Set clock source to PLL clock.

Enable MCLK output (12.288 MHz).

Enable PLL.

0xF890

0xF000

0xF001

0xF002

0xF005

0xF003

N/A

0x00, 0x00

0x00, 0x01

0x00, 0x60

0x00, 0x02

0x00, 0x01

0x00, 0x05

0x00, 0x01

N/A

SOFT_RESET

PLL_CTRL0

PLL_CTRL1

PLL_CLK_SRC

MCLK_OUT

PLL_ENABLE

N/A

Wait for PLL lock (see the Power-Up Sequence section); the maximum PLL lock

time is 10.666 ms.

0xF050

0xF051

0x4F, 0xFF

0x00, 0x00

POWER_ENABLE0

POWER_ENABLE1

SECONDPAGE_ENABLE

Enable power for all major systems except Clock Generator 3 (Clock Generator 3 is

rarely used in most systems).

Disable power for subsystems like PDM microphones, S/PDIF, and the ADC if they

are not being used in the system.

Toggle the SECONDPAGE_ENABLE to point at host port memory, Page 1.

Download the lower half of program RAM contents using a block write (data

provided by SigmaStudio compiler).

0xF899

0xC000

Data generated Program RAM data

by SigmaStudio (Page 1)

0x0000

0x6000

Data generated DM0 RAM data (Page 1)

by SigmaStudio

Data generated DM1 RAM data (Page 1)

by SigmaStudio

Download the lower half of Data Memory 0 (DM0) using a block write (data

provided by SigmaStudio compiler).

Download the lower half of Data Memory 1 (DM1) using a block write (data

provided by SigmaStudio compiler).

0xF899

0xC000

0x00,0x01

Data generated Program RAM data

by SigmaStudio (Page 2)

SECONDPAGE_ENABLE

Toggle the SECONDPAGE_ENABLE to point at host port memory Page 1.

Download the upper half of Program RAM contents using a block write (data

provided by SigmaStudio compiler).

0x0000

0x6000

Data generated DM0 RAM data (Page 2)

by SigmaStudio

Data generated DM1 RAM data (Page 2)

by SigmaStudio

Download the upper half of DM0 using a block write (data provided by

SigmaStudio compiler).

Download the upper half of DM1 using a block write (data provided by

SigmaStudio compiler).

0xF404

0xF401

N/A

0xF402

N/A

0x00, 0x00

0x00, 0x02

N/A

0x00, 0x00

0x00, 0x01

N/A

START_ADDRESS

START_PULSE

N/A

START_CORE

N/A

Set program start address as defined by the SigmaStudio compiler.

Set DSP core start pulse to internally generated pulse.

Configure any other registers that require nondefault values.

Stop the core.

Start the core.

Wait 50 µs for initialization program to execute.

¹N/A means not applicable.

Rev. A | Page 29 of 207

ADAU1463/ADAU1467

Data Sheet

On the EVAL-ADAU1467Z evaluation board, the crystal

oscillator load capacitors, C8 and C10, are 22 pF.

MASTER CLOCK, PLL, AND CLOCK GENERATORS

Clocking Overview

Do not directly drive another IC using the crystal signal on

XTALOUT. This signal is an analog sine wave with low drive

capability and, therefore, is not appropriate to drive an external

digital input. A separate pin, CLKOUT, is provided for this

purpose. The CLKOUT pin is set up using the MCLK_OUT

register (Address 0xF005). For a more detailed explanation of

CLKOUT, refer to the Master Clock Output section or the

register map description of the MCLK_OUT register (see the

CLKOUT Control Register section).

Connect the clock source directly to the XTALIN/MCLK pin to

externally supply the master clock. Alternatively, use the internal

clock oscillator to drive an external crystal.

Using the Oscillator

The ADAU1463/ADAU1467 can use an on-board oscillator to

generate its master clock. However, to complete the oscillator

circuit, an external crystal must be attached. The on-board

oscillator is designed to work with a crystal that is tuned to

resonate at a frequency of the nominal system clock divided by

12 or 24. For a system in which the nominal system clock is

147.456 MHz or 294.912 MHz, this frequency is 12.288 MHz.

If a clock signal is provided from elsewhere in the system directly

to the XTALIN/MCLK pin, the crystal resonator circuit is not

necessary, and the XTALOUT pin can remain disconnected.

The fundamental frequency of the crystal can be up to 30 MHz.

In most systems, the fundamental frequency of the crystal is most

easily sourced and simplest to work with when it is in a range from

3.072 MHz to 24.576 MHz.

Setting the Master Clock and PLL Mode

An integer PLL is available to generate the core system clock

from the master clock input signal. The PLL generates the

nominal 294.912 MHz core system clock to run the DSP core.

The flexible clock generator circuitry enables this nominal core

clock frequency to generate a wide range of audio sample rates.

An integer prescaler takes the clock signal from the MCLK pin

and divides its frequency by 1, 2, 4, or 8 to meet the appropriate

frequency range requirements for the PLL itself. The nominal

input frequency to the PLL is 3.072 MHz. For systems with

an 11.2896 MHz input master clock, the input to the PLL is

2.8224 MHz.

For the external crystal in the circuit, use an AT cut parallel

resonance device operating at its fundamental frequency. Do not

use ceramic resonators, which have poor jitter performance.

Quartz crystals are ideal for audio applications. Figure 14 shows

the crystal oscillator circuit that is recommended for proper

operation.

22pF

XTALIN/MCLK

12.288MHz

1, 2, 4, (DEFAULT)

100Ω

OR 8

96

XTALOUT

XTALIN/

MCLK

294.912MHz

SYSTEM CLOCK

×

÷

22pF

NOMINALLY

3.072MHz

Figure 14. Crystal Resonator Circuit

Figure 15. PLL Functional Block Diagram

The 100 Ω damping resistor on XTALOUT provides the oscillator

with a voltage swing of approximately 3.1 V at the XTALIN/

MCLK pin. The optimal crystal shunt capacitance is 7 pF.

Its optimal load capacitance, specified by the manufacturer,

is commonly approximately 20 pF, although the circuit supports

values of up to 25 pF. Ensure that the equivalent series resistance is

as small as possible. Calculate the necessary values of the two load

capacitors in the circuit from the crystal load capacitance, using

the following equation:

The master clock input signal ranges in frequency from 2.375 MHz

to 36 MHz. For systems that are intended to operate at a 48 kHz,

96 kHz, or 192 kHz audio sample rate, the typical master clock

input frequencies are 3.072 MHz, 6.144 MHz, 12.288 MHz, and

24.576 MHz. The flexibility of the PLL allows a large range of

other clock frequencies as well.

The PLL in the ADAU1463 and ADAU1467 has a nominal (and

maximum) output frequency of 294.912 MHz.

C1×C2

C1+ C2

The PLL is configured by setting Register 0xF000 (PLL_CTRL0),

Register 0xF001 (PLL_CTRL1), and Register 0xF002 (PLL_CLK_

SRC). After these registers are modified, set Register 0xF003, Bit 0

(PLL_ENABLE), forcing the PLL to reset itself and attempt to

relock to the incoming clock signal. Typically, the PLL locks

within 3.5 ms. When the PLL locks to an input clock and creates

a stable output clock, a lock flag is set in Register 0xF004, Bit 0

(PLL_LOCK).

C_L

=

+ C_STRAY

where:

C1 and C2 are the load capacitors.

_STRAYis the stray capacitance in the circuit. C_STRAYis usually

assumed to be approximately 2 pF to 5 pF, but it varies

depending on the PCB design.

C

Short trace lengths in the oscillator circuit decrease stray

capacitance, thereby increasing the loop gain of the circuit and

helping to avoid crystal start-up problems. Therefore, place the

crystal as near to the XTALOUT pin as possible and on the

same side of the PCB.

Rev. A | Page 30 of 207

Data Sheet

ADAU1463/ADAU1467

Example PLL Settings

clock allows fewer instructions to be executed and lowers overall

power consumption of the device. Table 20 shows several example

MCLK frequencies and the corresponding PLL settings that allow

the highest number of program instructions to be executed for

each audio frame. The settings provide the highest possible

system clock without exceeding the 294.912 MHz upper limit.

Depending on the input clock frequency, there are several possible

configurations for the PLL. Setting the PLL to generate the highest

possible system clock, without exceeding the maximum, allows the

execution of more DSP program instructions for each audio frame.

Alternatively, setting the PLL to generate a lower frequency system

Table 20. Optimal Predivider and Feedback Divider Settings for Varying Input MCLK Frequencies

Input MCLK

Frequency (MHz)

Predivider

Setting

PLL Input

Clock (MHz)

Feedback

Divider Setting

ADAU1463/ADAU1467 Fast

Grade System Clock (MHz)

ADAU1463 Slow Grade

System Clock (MHz)

2.8224

3

3.072

3.5

4

4.5

5

5.5

5.6448

6

6.144

6.5

7

7.5

8

8.5

9

9.5

10

10.5

11

11.2896

11.5

12

12.288

12.5

13

13.5

14

14.5

15

15.5

16

16.5

17

17.5

18

18.5

19

1

2

4

8

2.8224

3

3.072

3.5

4

4.5

104

98

96

84

73

293.5296

294

294.912

294

292

292.5

146.7648

147

147.456

147

146

65

146.25

147.125

146.7648

147

147.456

146.25

147

2.5

117

107

104

98

96

90

84

78

73

69

292.5

2.75

2.8224

3

3.072

3.25

3.5

3.75

4

4.25

4.5

294.25

293.5296

294

294.912

292.5

294

292.5

292

293.25

292.5

146.25

146

146.625

146.25

147.25

146.25

147

147.125

146.7648

146.625

147

147.456

146.875

146.25

146.8125

147

146.8125

146.25

147.25

146

146.4375

146.625

146.5625

146.25

146.84375

147.25

146.25

147.34375

147

65

2.375

2.5

124

117

112

107

104

102

98

96

94

90

87

84

81

78

76

73

71

69

67

294.5

292.5

294

2.625

2.75

2.8224

2.875

3

3.072

3.125

3.25

3.375

3.5

3.625

3.75

3.875

4

4.125

4.25

4.375

4.5

294.25

293.5296

293.25

294

294.912

293.75

292.5

293.625

294

293.625

292.5

294.5

292

292.875

293.25

293.125

292.5

293.6875

294.5

292.5

294.6875

294

292.9375

65

2.3125

2.375

2.4375

2.5

2.5625

2.625

2.6875

127

124

120

117

115

112

109

19.5

20

20.5

21

21.5

146.46875

Rev. A | Page 31 of 207

ADAU1463/ADAU1467

Data Sheet

Input MCLK

Frequency (MHz)

Predivider

Setting

PLL Input

Clock (MHz)

Feedback

Divider Setting

ADAU1463/ADAU1467 Fast

Grade System Clock (MHz)

ADAU1463 Slow Grade

System Clock (MHz)

147.125

146.25

146.7648

146.625

146.875

147

147.456

146.875

22

8

2.75

107

104

102

100

98

96

94

294.25

292.5

293.5296

293.25

293.75

294

294.912

293.75

22.5

22.5792

23

23.5

24

24.5

24.576

25

2.8125

2.8224

2.875

2.9375

3

3.0625

3.072

3.125

Relationship Between System Clock and Number of

Instructions per Sample

Table 21. Maximum Instructions/Sample

System

DSP Core

Maximum Instructions

Clock (MHz)

Sample Rate (kHz) per Sample

The DSP core executes only a limited number of instructions

within the span of each audio sample. The number of instructions

that can be executed is a function of the system clock and the DSP

core sample rate. The core sample rate is set by Register 0xF401

(START_PULSE), Bits[4:0] (START_PULSE).

294.912

293.5296

147.456

146.7648

1

8

12

16

24

36,864¹

24,576¹

18,432¹

12,288

9216

32

The number of instructions that can be executed per sample is

equal to the system clock frequency divided by the DSP core

sample rate. However, the program RAM size is 8192 words;

therefore, where the maximum instructions per sample exceeds

8192, subroutines and loops must be used to make use of all

available instructions (see Table 21).

48

6144

64

4608

96

3072

128

192

11.025

22.05

44.1

88.2

176.4

8

12

16

24

32

2304

1536

26,624¹

13,312

6656

PLL Filter

An external PLL filter is required to help the PLL maintain

stability and to limit the amount of ripple appearing on the phase

detector output of the PLL. For a nominal 3.072 MHz PLL input

and a 294.912 MHz system clock output (or 147.456 MHz), the

recommended filter configuration is shown in Figure 16. This

filter works for the full frequency range of the PLL.

3328

1664

184320¹

122880¹

92160¹

61440¹

46080¹

3072

5.6nF

PVDD

150pF

4.3kΩ

48

PLLFILT

64

2304

96

1536

Figure 16. PLL Filter

128

192

11.025

22.05

44.1

88.2

176.4

1152

768

133120¹

66560¹

3328

Because the center frequency and bandwidth of the loop filter

is determined by the values of the included components, use high

accuracy (low tolerance) components. Components that are

valued within 10% of the recommended component values and

with a 15% or lower tolerance are suitable for use in the loop

filter circuit.

1664

832

The voltage on the PLLFILT pin, which is internally generated,

is typically between 1.65 V and 2.10 V.

The instructions per sample in these cases exceed the program memory

size of 16,384 words on ADAU1463 or 24,576 words on the ADAU1467.

Therefore, to utilize the full number of instructions, subroutines or branches

are required in the SigmaStudio program.

Rev. A | Page 32 of 207

Data Sheet

ADAU1463/ADAU1467

For Clock Generator 1 and Clock Generator 2, the integer numera-

tor (N) and the integer denominator (M) are each nine bits long.

For Clock Generator 3, N and M are each 16 bits long, allowing

a higher precision when generating arbitrary clock frequencies.

Clock Generators

Three clock generators are available to generate audio clocks for

the serial ports, DSP, ASRCs, and other audio related functional

blocks in the system. Each clock generator can be configured to

generate a base frequency and several fractions or multiples of that

base frequency, creating a total of 15 clock domains available for

use in the system. Each of the 15 clock domains can create the

appropriate frame clock (LRCLK) and bit clock (BCLK) signals for

the serial ports. Five BCLK signals are generated at frequencies of

32 BCLK/sample, 64 BCLK/sample, 128 BCLK/sample, 256 BCLK/

sample, and 512 BCLK/sample to process TDM data. Therefore,

with a single master clock input frequency, 15 different frame clock

frequencies and 75 different bit clock frequencies can be generated

for use in the system.

Figure 17 shows a basic block diagram of the PLL and clock

generators. Each division operator symbolizes that the frequency

of the clock is divided when passing through that block. Each

multiplication operator symbolizes that the frequency of the

clock is multiplied when passing through that block.

Figure 18 shows an example where the master clock input has a

frequency of 12.288 MHz, and the default settings are used for

the PLL predivider, feedback divider, and Clock Generator 1

and Clock Generator 2. The resulting system clock is

12.288 MHz ÷ 4 × 96 = 294.912 MHz

The base output of Clock Generator 1 is

294.912 MHz ÷ 1024 × 1 ÷ 6 = 48 kHz

The base output of Clock Generator 2 is

294.912 MHz ÷ 1024 × 1 ÷ 9 = 32 kHz

The nominal output of each clock generator is determined by

the following formula:

Output Frequency = (Input Frequency × N)/(1024 × M)

where:

Output Frequency is the frame clock output frequency.

Input Frequency is the PLL output (nominally 294.912 MHz).

N and M are integers that are configured by writing to the clock

generator configuration registers.

In this example, Clock Generator 3 is configured with N = 49

and M = 320; therefore, the resulting base output of Clock

Generator 3 is

In addition to the nominal output, four additional output signals

are generated at double, quadruple, half, and a quarter of the

frequency of the nominal output frequency.

294.912 MHz ÷ 1024 × 49 ÷ 320 = 44.1 kHz

1, 2, 4, PROGRAMMABLE

OR 8

TYPICALLY 96

XTALIN/

MCLK

×

SYSTEM CLOCK

÷

(Default)

N = 1,

DIVIDER

FEEDBACK

DIVIDER

×4

×2

×1

÷2

÷4

M = 6

CLKGEN 1

× N ÷ M

÷1024

(Default)

N = 1,

M = 9

×4

×2

×1

÷2

÷4

CLKGEN 2

× N ÷ M

÷1024

×4

×2

×1

÷2

÷4

CLKGEN 3

× N ÷ M

Figure 17. PLL and Clock Generators Block Diagram

4

÷

96

×

12.288MHz

CLOCK

SOURCE

294.912MHz

SYSTEM CLOCK

DIVIDER

FEEDBACK

DIVIDER

N = 1,

M = 6

192kHz

96kHz

48kHz

24kHz

12kHz

CLKGEN 1

× N ÷ M

÷1024

N = 1,

M = 9

128kHz

64kHz

32kHz

16kHz

8kHz

CLKGEN 2

× N ÷ M

N = 49,

M = 320

176.4kHz

88.2kHz

44.1kHz

22.05kHz

11.025kHz

CLKGEN 3

× N ÷ M

Figure 18. PLL and Audio Clock Generators with Default Settings and Resulting Clock Frequencies Labeled, XTALIN/MCLK = 12.288 MHz

Rev. A | Page 33 of 207

ADAU1463/ADAU1467

Data Sheet

4

÷

96

×

11.2896MHz

270.9504MHz

CLOCK

SYSTEM CLOCK

SOURCE

DIVIDER

FEEDBACK

DIVIDER

N = 1,

M = 6

176.4kHz

88.2kHz

44.1kHz

22.05kHz

11.025kHz

CLKGEN 1

× N ÷ M

÷1024

N = 1,

M = 9

117.6kHz

58.8kHz

29.4kHz

14.7kHz

7.35kHz

CLKGEN 2

× N ÷ M

N = 80,

M = 441

192kHz

96kHz

48kHz

24kHz

12kHz

CLKGEN 3

× N ÷ M

Figure 19. PLL and Audio Clock Generators with Default Settings and Resulting Clock Frequencies Labeled, XTALIN/MCLK = 11.2896 MHz

1, 2, 4,

Figure 19 shows an example where the master clock input has a

OR 8

×

frequency of 11.2896 MHz, and the default settings are used for

the PLL predivider, feedback divider, and Clock Generator 1 and

Clock Generator 2. The resulting system clock is

CLKOUT

1, 2, 4,

OR 8

TYPICALLY 96

×

MCLK

SYSTEM CLOCK

÷

DIVIDER

FEEDBACK

DIVIDER

CLKGEN 1

CLKGEN 2

CLKGEN 3

11.2896 MHz ÷ 4 × 96 = 270.9504 MHz

The base output of Clock Generator 1 is

270.9504 MHz ÷ 1024 × 1 ÷ 6 = 44.1 kHz

The base output of Clock Generator 2 is

270.9504 MHz ÷ 1024 × 1 ÷ 9 = 29.4 kHz

Figure 20. Clock Output Generator

The CLKOUT pin can drive more than one external slave IC if

the drive strength is sufficient to drive the traces and external

receiver circuitry. The ability to drive external ICs varies greatly,

depending on the application and the characteristics of the PCB

and the slave ICs. The drive strength and slew rate of the

CLKOUT pin is configurable in the CLKOUT_PIN register

(Address 0xF7A3); therefore, its performance can be tuned to

match the specific application. The CLKOUT pin is not designed to

drive long cables or other high impedance transmission lines.

Use the CLKOUT pin only to drive signals to other integrated

circuits on the same PCB. When changing the settings for the pre-

divider, disable and then reenable the PLL using Register 0xF003

(PLL_ENABLE), allowing the frequency of the CLKOUT signal

to update.

In this example, Clock Generator 3 is configured with N = 80

and M = 441; therefore, the resulting base output of Clock

Generator 3 is

270.9504 MHz ÷ 1024 × 80 ÷ 441 = 48 kHz

Master Clock Output

The master clock output pin (CLKOUT) is useful in cases where

a master clock must be fed to other ICs in the system, such as

audio codecs. The master clock output frequency is determined

by the setting of the MCLK_OUT register (Address 0xF005).

Four frequencies are possible: 1×, 2×, 4×, or 8× the frequency

of the predivider output.

•

The predivider output × 1 generates a 3.072 MHz output

for a nominal system clock of 294.912 MHz.

The predivider output × 2 generates a 6.144 MHz output for

a nominal system clock of 294.912 MHz.

The predivider output × 4 generates a 12.288 MHz output

for a nominal system clock of 294.912 MHz.

The predivider output × 8 generates a 24.576 MHz output for

a nominal system clock of 294.912 MHz.

Dejitter Circuitry

To account for jitter between ICs in the system and to handle

interfacing safely between internal and external clocks, dejitter

circuits are included to guarantee that jitter related clocking errors

are avoided. The dejitter circuitry is automated and does not

require interaction or control from the user.

Rev. A | Page 34 of 207

Data Sheet

ADAU1463/ADAU1467

Table 23. Power Supply Details

Master Clock, PLL, and Clock Generators Registers

Externally

Supplied

An overview of the registers related to the master clock, PLL,

and clock generators is listed in Table 22. For a more detailed

description, see the PLL Configuration Registers section and the

Clock Generator Registers section.

Supply

Voltage

Description

IOVDD (Input/

Output)

DVDD (Digital)

1.8 V − 5% to

3.3 V + 10%

1.2 V 5%

Yes

Optional

Can be derived

from IOVDD using

an internal LDO

regulator

Table 22. Master Clock, PLL, and Clock Generator Registers

Address Register

Description

AVDD (Analog)

PVDD (PLL)

3.3 V 10%

Yes

0xF000

0xF001

0xF002

0xF003

0xF004

0xF005

0xF006

0xF020

0xF021

0xF022

0xF023

0xF024

0xF025

0xF026

0xF027

PLL_CTRL0

PLL_CTRL1

PLL_CLK_SRC

PLL_ENABLE

PLL_LOCK

PLL feedback divider

PLL prescale divider

PLL clock source

PLL enable

PLL lock

CLKOUT control

Voltage Regulator

The ADAU1463/ADAU1467 include a linear regulator that can

generate the 1.2 V supply required by the DSP core and other

internal digital circuitry from the I/O supply (IOVDD), which

can range from 1.8 V − 5% to 3.3 V + 10%. A simplified block

diagram of the internal structure of the regulator is shown in

Figure 22.

MCLK_OUT

PLL_WATCHDOG Analog PLL watchdog control

CLK_GEN1_M

CLK_GEN1_N

CLK_GEN2_M

CLK_GEN2_N

CLK_GEN3_M

CLK_GEN3_N

CLK_GEN3_SRC

Denominator (M) for Clock Generator 1

Numerator (N) for Clock Generator 1

Denominator (M) for Clock Generator 2

Numerator (N) for Clock Generator 2

Denominator (M) for Clock Generator 3

Numerator (N) for Clock Generator 3

Input reference for Clock Generator 3

For proper operation, the linear regulator requires several

external components. A PNP bipolar junction transistor acts

as an external pass device to bring the higher IOVDD voltage

down to the lower DVDD voltage, thus externally dissipating

the power of the IC package. Ensure that the transistor is able to

dissipate at least 1 W in the worst case. Place a 1 kΩ resistor

between the transistor emitter and base to help stabilize the

regulator for varying loads. This resistor placement also guarantees

that current is always flowing into the VDRIVE pin, even for

minimal regulator loads. Figure 21 shows the connection of the

external components.

CLK_GEN3_LOCK Lock bit for Clock Generator 3 input

reference

POWER SUPPLIES, VOLTAGE REGULATOR, AND

HARDWARE RESET

Power Supplies

The ADAU1463/ADAU1467 are supplied by four power

supplies: IOVDD, DVDD, AVDD, and PVDD.

10µF

•

IOVDD (input/output supply) sets the reference voltage

for all digital input and output pins. It can be any value

ranging from 1.8 V − 5% to 3.3 V + 10%. To use the I²C/SPI

control ports or any of the digital input or output pins, the

IOVDD supply must be present.

1kΩ

100nF

•

DVDD (digital supply) powers the DSP core and supporting

digital logic circuitry. It must be 1.2 V 5%.

AVDD (analog supply) powers the analog auxiliary ADC

circuitry. It must be supplied even if the auxiliary ADCs are

not in use.

DVDD

VDRIVE

IOVDD

Figure 21. External Components Required for Voltage Regulator Circuit

If an external supply is provided to DVDD, ground the

VDRIVE pin. The regulator continues to draw a small amount

of current (approximately 100 µA) from the IOVDD supply. Do

not use the regulator to provide a voltage supply to external ICs.

There are no control registers associated with the regulator.

•

PVDD (PLL supply) powers the PLL and acts as a reference

for the voltage controlled oscillator (VCO). It must be supplied

even if the PLL is not in use.

Rev. A | Page 35 of 207

ADAU1463/ADAU1467

Data Sheet

IOVDD

EXTERNAL

STABILITY

RESISTOR

IOVDD

VDRIVE

EXTERNAL

PNP BIPOLAR

INTERNAL

1.2V

PASS TRANSISTOR

REFERENCE

PMOS DEVICE

GND

DVDD

Figure 22. Simplified Block Diagram of Regulator Internal Structure, Including External Components

circuit with a push-button connected, providing a method for

RESET

Power Reduction Modes

manually generating a clean

on the application level, place a weak pull-down resistor on the

RESET

signal. For reliability purposes

All sections of the IC have clock gating functionality that allows

individual functional blocks to be disabled for power savings.

Functional blocks that can optionally be powered down include

the following:

line to guarantee that the device is held in reset in the

event that the reset supervisory circuitry fails.

3.3V

ADM811

100nF

•

Clock Generator 1, Clock Generator 2, and Clock

Generator 3

RESET

1

4

GND RESET

2

3

•

S/PDIF receiver

S/PDIF transmitter

Serial data input and output ports

Auxiliary ADC

ASRCs (in two banks of eight channels each)

PDM microphone inputs and decimation filters

MR

V

CC

Figure 23. Example Manual Reset Generation Circuit

If the hardware reset function is not required in a system, pull

RESET

the

resistor (in the range of several kΩ). The device is designed to boot

RESET

pin high to the IOVDD supply using a weak pull-up

Overview of Power Reduction Registers

properly even when the

pin is permanently pulled high.

An overview of the registers related to power reduction is shown

in Table 24. For a more detailed description, see the Power

Reduction Registers section.

TEMPERATURE SENSOR DIODE

The chip includes an on-board temperature sensor diode with

an approximate range of 0°C to 120°C. The temperature sensor

function is enabled by the two sides of a diode connected to the

THD_P and THD_M pins. Value processing (calculating the

actual temperature based on the current through the diode) is

handled off chip by an external controller IC. The temperature

value is not stored in an internal register; it is available only in

the external controller IC. The temperature sensor requires an

external IC to operate properly. See the Engineer-to-Engineer

Note EE-346 for more information and instructions for using the

temperature sensor diode.

Table 24. Power Reduction Registers

Address Register

Description

0xF050

POWER_ENABLE0 Disables clock generators, serial

ports, and ASRCs

0xF051

POWER_ENABLE1 Disables PDM microphone inputs,

S/PDIF interfaces, and auxiliary

ADCs

Hardware Reset

RESET

An active low hardware reset pin (

) is available for

ADAU1463/

ADAU1467

externally triggering a reset of the device. When this pin is tied

to ground, all functional blocks in the device are disabled, and

the current consumption decreases dramatically. The amount of

current drawn depends on the leakage current of the silicon, which

depends greatly on the ambient temperature and the properties

THERMAL

80

D+

D–

THD_P

DIODE

79

THD_M

MONITOR

Figure 24. Example External Temperature Sensor Circuit

RESET

of the die. When the

pin is connected to IOVDD, all control

SLAVE CONTROL PORTS

registers are reset to their power-on default values. The state of

the RAM is not guaranteed to be cleared after a reset; therefore,

the memory must be manually cleared by the DSP program.

A total of four control ports are available: two slave ports and

two master ports. The slave I²C port and slave SPI port allow an

external master device to modify the contents of the memory

and registers. The master I²C port and master SPI port allow the

device to self boot and to send control messages to slave devices

on the same bus.

The default program generated by SigmaStudio includes code

that automatically clears the memory. To ensure that no chatter

RESET

exists on the

signal line, implement an external reset

generation circuit in the system hardware design. Figure 23

shows an example of the ADM811 microprocessor supervisory

Rev. A | Page 36 of 207

Data Sheet

ADAU1463/ADAU1467

for updating signal processing parameters in real time without

causing pops or clicks.

Slave Control Port Overview

To program the DSP and configure the control registers, a slave

port is available that can communicate using either the I²C or

SPI protocols. Any external device that controls the ADAU1463/

ADAU1467, including a hardware interface used with SigmaStudio

for development or a microcontroller in a large running system,

uses the slave control port to communicate with the DSP. This

port is unrelated to the master communications port that also uses

the I²C or SPI protocols. The master port enables applications

without an external microcontroller and can read from an

external EEPROM to self boot and control external ICs.

When updating a signal processing parameter while the DSP

core is running, use the software safeload function. This

function allows atomic writes to memory and prevents updates

to parameters across the boundary of an audio frame, which

can lead to an audio artifact such as a click or pop sound. For

more information, see the Software Safeload section.

The slave control port supports either I²C or SPI, but not

simultaneously. The function of each pin is described in

Table 25 for the two modes.

The slave communications port defaults to I²C mode; however, it

can be put into SPI mode by toggling SS (SS/ADDR0), the slave

select pin, from high to low three times. The slave select pin

must be held low for at least one master clock period (that is,

one period of the clock on the XTALIN/MCLK input pin). Only

the PLL configuration registers (0xF000 to 0xF004) are accessible

before the PLL locks. For this reason, always write to the PLL

registers first after the chip powers up. After the PLL locks, the

remaining registers and the RAM become accessible. See the

System Initialization Sequence section for more information.

Burst Mode Writing and Reading

Burst write and read modes are available for convenience when

writing large amounts of data to contiguous registers. In these

modes, the chip and memory addresses are written once, and

then a large amount of data can follow uninterrupted. The sub-

addresses are automatically incremented at the word boundaries.

This increment happens automatically after a single word write

or read unless a stop condition is encountered (I²C mode) or the

slave select is disabled and brought high (SPI mode). A burst write

starts like a single word write, but, following the first data-word,

the data-word for the next address can be written immediately

without sending its 2-byte address. The control registers in the

ADAU1463/ADAU1467 are two bytes wide, and the memories

are four bytes wide. The auto-increment feature knows the word

length at each subaddress; therefore, it is not necessary to manually

specify the subaddress for each address in a burst write.

SLAVE CONTROL PORT ADDRESSING

Unlike earlier SigmaDSP processors, the ADAU1463/ADAU1467

slave control port 16-bit addressing cannot provide direct access

to the total amount of memory available to the DSP core on its

wider internal busses. Full read/write access to all memory and

addressable registers is possible, but it must be accessed as two

pages of memory in the slave control port address space. Page 0

is referred to as lower memory and Page 1 as upper memory.

The single-bit register SECONDPAGE_ENABLE (0xF899)

selects the active page.

The subaddresses are automatically incremented by one address,

following each read or write of a data-word, regardless of whether

there is a valid register or RAM word at that address.

SLAVE PORT TO DSP CORE ADDRESS MAPPING

Within a page, all addresses are accessible using both single

address mode and burst mode. The first byte (Byte 0) of a

The DSP core architecture use of three separate areas of memory,

program memory (PM), DM0, and DM1. To maintain backward

compatibility with the ADAU1450/ADAU1451/ADAU1452

family of processors, slave port access to this memory is divided

into two pages, Page 1 and Page 2. The single-bit register

SECONDPAGE_ENABLE (0xF899) selects the active page.

Figure 81 shows the mapping between slave port addresses and

the native address space of the core for ADAU1463. Figure 82

shows the mapping between slave port addresses and the native

address space of the core for ADAU1467.

W

control port write contains the 7-bit chip address plus the R/

bit. The next two bytes (Byte 1 and Byte 2) together form the

subaddress of the register location within the memory maps of

the ADAU1463/ADAU1467. This subaddress must be two bytes

long because the memory locations within the devices are

directly addressable, and their sizes exceed the range of single

byte addressing. The third byte to the end of the sequence

contain the data, such as control port data, program data, or

parameter data. The number of bytes written per word depends

on the type of data. For more information, see the Burst Mode

Writing and Reading section. The ADAU1463/ADAU1467 must

have a valid master clock to write to the slave control port, with

the exception of the PLL configuration registers, 0xF000 to 0xF004.

Note that the lower and upper halves of program memory, DM0

and DM1, map to the same slave control port addresses. The

value of register SECONDPAGE_ENABLE (Address 0xF899)

determines whether a slave control port address points to the

lower or upper areas of PM, DM0, and DM1.

If large blocks of data must be downloaded, halt the output of

the DSP core (using Register 0xF400, hibernate), load new data,

and then restart the device (using Register 0xF402, START_

CORE). This process is most common during the booting

sequence at startup or when loading a new program into RAM

because the ADAU1463/ADAU1467 have several mechanisms

Although the slave port accesses memory in pages, the

addressing is contiguous and seamless to the DSP core.

Rev. A | Page 37 of 207

ADAU1463/ADAU1467

Data Sheet

Note that there is only one set of control registers at

Address 0xF000 to Address 0xFBFF. The value of

SECONDPAGE_ENABLE has no effect on these registers.

For example,

•

A write on the slave port to Address 0x6000 while

SECONDPAGE_ENABLE is set to 0 (on Page 1) changes

the value of Address 0x0000 in DM1 memory.

A write on the slave port to Address 0xAFFF while

SECONDPAGE_ENABLE is set to 0 (on Page 1) changes

the value of Address 0x4FFF in DM1 memory.

A write on the slave port to Address 0x6000 while

SECONDPAGE_ENABLE is set to 1 (on Page 2) changes

the value of Address 0x5000 in DM1 memory.

A write on the slave port to Address 0xAFFF while

SECONDPAGE_ENABLE is set to 1 (on Page 2) changes

the value of Address 0x9FFF in DM1 memory.

Table 25. Control Port Pin Functions

Pin Name

I²C Slave Mode

SPI Slave Mode

SS/ADDR0

Address 0 (Bit 1 of the address word, input to the

ADAU1463/ADAU1467)

Slave select (input to the ADAU1463/ADAU1467)

SCLK/SCL

Clock (input to the ADAU1463/ADAU1467)

MOSI/ADDR1 Address 1 (Bit 2 of the address word, input to the

ADAU1463/ADAU1467)

Data; master out, slave in (input to the

ADAU1463/ADAU1467)

MISO/SDA

Data (bidirectional, open-collector)

Data; master in, slave out (output from the

ADAU1463/ADAU1467)

Rev. A | Page 38 of 207

Data Sheet

ADAU1463/ADAU1467

I²C Slave Control Port

Addressing

The ADAU1463/ADAU1467 support a 2-wire serial (I²C com-

patible) microprocessor bus driving multiple peripherals. The

maximum clock frequency on the I²C slave port is 1 MHz. Two

pins, serial data (SDA) and serial clock (SCL), carry information

between the ADAU1463/ADAU1467 and the system I²C master

controller. In I²C mode, the ADAU1463/ADAU1467 are always

slaves on the bus, meaning that they cannot initiate a data transfer.

Each slave device is recognized by a unique address. The address

resides in the first seven bits of the I²C write.

Initially, each device on the I²C bus is in an idle state and monitors

the SDA and SCL lines for a start condition and the proper address.

The I²C master initiates a data transfer by establishing a start condi-

tion, defined by a high to low transition on SDA while SCL remains

high. This start condition indicates that an address/ data stream

follows. All devices on the bus respond to the start condition and

W

shift the next eight bits (the 7-bit address plus the R/ bit), MSB

first. The device that recognizes the transmitted address responds

by pulling the data line low during the ninth clock pulse. This ninth

bit is known as an acknowledge bit. All other devices withdraw

from the bus at this point and return to the idle condition.

Table 26 describes the relationship between the state of the address

pins (0 represents logic low and 1 represents logic high) and the

I²C slave address. Ensure that the address pins (SS/ADDR0 and

MOSI/ADDR1) are hardwired in the design; do not allow these

pins to change states while the device is operating.

W

The R/ bit determines the direction of the data. A Logic 0 on

the LSB of the first byte means that the master writes information

to the peripheral, whereas a Logic 1 means that the master reads

information from the peripheral after writing the subaddress and

repeating the start address. A data transfer occurs until a stop

condition is encountered. A stop condition occurs when SDA

transitions from low to high while SCL is held high.

Figure 25 shows the timing of an I²C single word write operation,

Figure 26 shows the timing of an I²C burst mode write operation,

and Figure 27 shows an I²C burst mode read operation.

Place a 2 kΩ pull-up resistor on each line connected to the SDA

and SCL pins. Ensure that the voltage on these signal lines does

not exceed IOVDD (1.8 V − 5% to 3.3 V + 10%).

The two address bits that follow can be set to assign the I²C slave

address of the device. Set Bit 1 by pulling the SS/ADDR0 pin

either to IOVDD (by setting it to 1) or to ground (by setting it to

0). Set Bit 2 by pulling the MOSI/ADDR1 pin either to IOVDD

(by setting it to 1) or to ground (by setting it to 0). The LSB of the

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of

sequence with normal read and write operations, the slave I²C

port of the ADAU1463/ADAU1467 immediately transitions to

the idle condition. During a given SCL high period, issue only

one start condition and one stop condition, or a single stop

condition followed by a single start condition. If the user issues

an invalid subaddress, the ADAU1463/ADAU1467 do not issue

an acknowledge and return to the idle condition.

W

address (the R/ bit) specifies a read or write operation. Logic

Level 1 corresponds to a read operation and Logic Level 0

corresponds to a write operation. Table 26 describes the sequence

of eight bits that define the I²C device address byte.

Table 27 describes the relationship between the state of the address

pins (0 represents logic low and 1 represents logic high) and the

I²C slave address. Ensure that the address pins (SS/ADDR0 and

MOSI/ADDR1) are hardwired in the design. Do not allow these

pins to change states while the device is operating.

Note the following conditions:

•

Do not issue an auto-increment (burst) write command

that exceeds the highest subaddress in the memory.

Do not issue an auto-increment (burst) write command

that writes to subaddresses that are not defined in the

Global RAM and Control Register Map section.

Place a 2 kΩ pull-up resistor on each line connected to the SDA

and SCL pins. Ensure that the voltage on these signal lines does

not exceed IOVDD (1.8 V − 5% to 3.3 V + 10%).

•

Table 26. Address Bit Sequence

Bit 5

Bit 4

Bit 3

Bit 2

ADDR1 (set by the MOSI/ADDR1 pin)

Bit 1

Bit 7

Bit 6

Bit 0

0

1

0

ADDR0 (set by the SS/ADDR0 pin)

W

R/

Table 27. I²C Slave Addresses

Slave Address (Eight Bits,

Including R/W Bit)

Slave Address (Seven Bits,

Excluding R/W Bit)

Read/Write¹

MOSI/ADDR1

SS/ADDR0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x38

0x39

0x3A

0x3B

¹0 means write, 1 means read.

Rev. A | Page 39 of 207

ADAU1463/ADAU1467

Data Sheet

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

SCLK/SCL

DEVICE ADDRESS BYTE

SUBADDRESS BYTE 1

[5] [4] [3] [2]

SUBADDRESS BYTE 2

[5] [4] [3] [2]

MISO/SDA

[7]

[6]

[1]

[0]

[7]

[6]

[1]

[0]

0

1

0

R/W

START

ACK

(SLAVE)

ACK

(SLAVE)

ACK

(SLAVE)

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

SCLK/SCL

MISO/SDA

DATA BYTE 1

[4] [3]

DATA BYTE 2

[4] [3] [2]

[7]

[6]

[5]

[2]

[1]

[0]

[7]

[6]

[5]

[1]

[0]

ACK STOP

(SLAVE)

ACK

(SLAVE)

Figure 25. I²C Slave Single Word Write Operation (Two Bytes)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

SCLK/SCL

MISO/SDA

DEVICE ADDRESS BYTE

SUBADDRESS BYTE 1

[7] [6] [5] [4] [3] [2] [1] [0]

SUBADDRESS BYTE 2

[7] [6] [5] [4] [3] [2] [1] [0]

R/W

0

1

0

START

ACK

(SLAVE)

ACK

(SLAVE)

ACK

(SLAVE)

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

SCLK/SCL

MISO/SDA

DATA BYTE N

[7] [6] [5] [4] [3] [2] [1] [0]

DATA BYTE 1

[7] [6] [5] [4] [3] [2] [1] [0]

DATA BYTE 2

[7] [6] [5] [4] [3] [2] [1] [0]

ACK

(SLAVE)

STOP

ACK

(SLAVE)

ACK

(SLAVE)

Figure 26. I²C Slave Burst Mode Write Operation (N Bytes)

0

1

2

3

4

5

6

7

8

9

10 11

12 13

14 15

16 17

18 19

20 21

22 23

24 25

26

SCLK/SCL

MISO/SDA

DEVICE ADDRESS BYTE

SUBADDRESS BYTE 1

[7] [6] [5] [4] [3] [2] [1] [0]

SUBADDRESS BYTE 2

[7] [6] [5] [4] [3] [2] [1] [0]

R/W

0

1

0

START

ACK

(SLAVE)

ACK

(SLAVE)

ACK

(SLAVE)

27

28 29

30 31

32 33

34 35

36

37

38 39

40 41

42 43

44

SCLK/SCL

MISO/SDA

DATA BYTE 1 FROM SLAVE

[7] [6] [5] [4] [3] [2] [1] [0]

DATA BYTE N FROM SLAVE

[7] [6] [5] [4] [3] [2] [1] [0]

CHIP ADDRESS BYTE

R/W

0

1

0

ACK

(SLAVE)

STOP

REPEATED

START

ACK

(SLAVE)

ACK

(SLAVE)

Figure 27. I²C Slave Burst Mode Read Operation (N Bytes)

Rev. A | Page 40 of 207

Data Sheet

ADAU1463/ADAU1467

I²C Read and Write Operations

to reverse and begin driving data back to the master. The master

then responds every ninth pulse with an acknowledge pulse to

the device.

Figure 28 shows the simplified format of a single word write

operation. Every ninth clock pulse, the ADAU1463/ADAU1467

issue an acknowledge by pulling SDA low.

Figure 31 shows the simplified format of a burst mode read

sequence. This figure shows an example of a read from sequential

single byte registers. The ADAU1463/ADAU1467 increment

the subaddress register after every byte because the requested

subaddress corresponds to a register or memory area with a

1-byte word length. The ADAU1463/ADAU1467 always decode

the subaddress and set the auto-increment circuit such that the

address increments after the appropriate number of bytes.

Figure 29 shows the simplified format of a burst mode write

sequence. This figure shows an example of a write to sequential

single byte registers. The ADAU1463/ADAU1467 increment the

subaddress register after every byte because the requested

subaddress corresponds to a register or memory area with a

1-byte word length.

Figure 30 shows the simplified format of a single word read

Figure 28 to Figure 31 use the following abbreviations:

W

operation. The first R/ bit is 0, indicating a write operation,

•

S means start bit.

P means stop bit.

AM means acknowledge by master.

AS means acknowledge by slave.

because the subaddress must still be written to set up the internal

address. After the ADAU1463/ADAU1467 acknowledge the

receipt of the subaddress, the master must issue a repeated start

W

command followed by the chip address byte with the R/ bit set

to 1 (read). The start command causes the SDA pin of the device

CHIP ADDRESS,

SUBADDRESS,

HIGH

SUBADDRESS,

LOW

DATA

BYTE 1

DATA

BYTE 2

DATA

BYTE N

AS

...

AS

P

S

R/W = 0

S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE.

SHOWS A ONE-WORD WRITE, WHERE EACH WORD HAS N BYTES.

Figure 28. Simplified Single Word I²C Write Sequence

CHIP

ADDRESS,

R/W = 0

SUBADDRESS,

HIGH

SUBADDRESS,

LOW

...

P

S

AS

DATA-WORD 1, DATA-WORD 1, DATA-WORD 2, DATA-WORD 2,

BYTE 1 BYTE 2 BYTE 1 BYTE 2

DATA-WORD N, DATA-WORD N,

BYTE 1 BYTE 2

S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE.

SHOWS AN N-WORD WRITE, WHERE EACH WORD HAS TWO BYTES. (OTHER WORD LENGTHS ARE POSSIBLE, RANGING FROM ONE TO FIVE BYTES.)

Figure 29. Simplified Burst Mode I²C Write Sequence

CHIP ADDRESS,

R/W = 0

SUBADDRESS,

HIGH

SUBADDRESS,

LOW

CHIP ADDRESS,

R/W = 1

DATA

BYTE 1

DATA

BYTE 2

DATA

BYTE N

...

AS

S

AS

AM

P

S

S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE.

SHOWS A ONE-WORD WRITE, WHERE EACH WORD HAS N BYTES.

Figure 30. Simplified Single Word I²C Read Sequence

CHIP

ADDRESS,

R/W = 0

CHIP

ADDRESS,

R/W = 1

SUBADDRESS,

HIGH

SUBADDRESS,

LOW

...

P

S

AS

AM

DATA-WORD 1,

BYTE 1

DATA-WORD 1,

BYTE 2

DATA-WORD N, DATA-WORD N,

BYTE 1 BYTE 2

S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE.

SHOWS AN N-WORD WRITE, WHERE EACH WORD HAS TWO BYTES. (OTHER WORD LENGTHS ARE POSSIBLE, RANGING FROM ONE TO FIVE BYTES.)

Figure 31. Simplified Burst Mode I²C Read Sequence

Rev. A | Page 41 of 207

ADAU1463/ADAU1467

Data Sheet

the same basic format shown in Table 29. A timing diagram is

shown in Figure 8. Write all data MSB first.

SPI Slave Control Port

By default, the slave port is in I²C mode. However, the slave port

can be placed into SPI control mode by pulling SS/ADDR0 low

three times, either by

Only one chip address is available in SPI mode. The 7-bit

chip address is 0b0000000. The LSB of the first byte of an SPI

W

transaction is an R/ bit. This bit determines whether the

•

Toggling the SS/ADDR0 successively between logic high

and logic low states. After toggling SS/ADDR0 three times,

data can be written to or read from the IC.

communication is a read (Logic Level 1) or a write (Logic Level 0).

The SPI byte format is shown in Table 28.

•

Performing three dummy writes to the SPI port, writing

any arbitrary data to any arbitrary subaddress (the slave

port does not acknowledge these three writes). An example

of dummy writing is shown in Figure 32.

Write

Bit 3

0

Table 28. SPI Address and Read/

Byte Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 2

Bit 1

Bit 0

0

R/W

The 16-bit subaddress word is decoded into a location in one of

the registers. This subaddress is the location of the appropriate

register. The MSBs of the subaddress are zero padded to bring

the word to a full 2-byte length.

After setting the slave port in SPI slave mode, the only way to

revert to I²C slave mode is by executing a full hardware reset

RESET

using the

pin or by power cycling the power supplies.

The SPI port uses a 4-wire interface, consisting of the SS, MOSI,

MISO, and SCLK signals, and it is always a slave port. The SS signal

goes low at the beginning of a transaction and high at the end of

a transaction. The SCLK signal latches MOSI on a low to high

transition. MISO data is shifted out of the device on the falling

edge of SCLK and must be clocked into a receiving device, such

as a microcontroller, on the SCLK rising edge. The MOSI signal

carries the serial input data, and the MISO signal carries the

serial output data. The MISO signal remains three-state until a

read operation is requested, which allows other SPI-compatible

peripherals to share the same MISO line. All SPI transactions have

The format for the SPI communications slave port is commonly

known as SPI Mode 3, where clock polarity (CPOL) = 1 and

clock phase (CPHA) = 1 (see Figure 33). The base value of the

clock is 1. Data is captured on the rising edge of the clock, and

data is propagated on the falling edge.

The maximum read and write speed for the SPI slave port is

22 MHz, but this speed is valid only after the PLL is locked.

Before the PLL locks, the maximum clock rate in the chip is

limited to the frequency of the input clock to the PLL, which is

nominally 3.072 MHz. Therefore, the SPI clock must not exceed

3.072 MHz until the PLL lock completes.

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

SS/ADDR0

SCLK/SCL

MOSI/ADDR1

Figure 32. Example of SPI Slave Mode Initialization Sequence Using Dummy Writes

Table 29. Generic Control Word Sequence

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4 and Subsequent Bytes

Chip Address[6:0], R/W

Subaddress[15:8]

Subaddress[7:0]

Data

CPOL = 0

CPOL = 1

SCLK

SS

1

2

1

3

2

4

1

5

2

6

1

7

2

8

CYCLE #

Z

MISO

MOSI

CPHA = 0

CPHA = 1

1

2

3

4

5

6

7

8

CYCLE #

MISO

Z

MOSI

Figure 33. Clock Polarity and Phase for SPI Slave Port

Rev. A | Page 42 of 207

Data Sheet

ADAU1463/ADAU1467

timing diagram of a single word SPI read operation is shown in

Figure 35. The MISO/SDA pin transitions from being three-state

Figure 34 to Figure 36, rising edges on SCLK/SCL are indicated

with an arrow, signifying that the data lines are sampled on the

rising edge.

A sample timing diagram for a multiple word SPI write operation

(burst write) to a register is shown in Figure 34. A sample

to being driven at the beginning of Byte 3. In this example, Byte 0

W

to Byte 2 contain the addresses and the R/ bit, and subsequent

bytes carry the data. A sample timing diagram of a multiple

word SPI read operation (burst read) is shown in Figure 36. In

0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SS/ADDR0

SCLK/SCL

CHIP ADDRESS[6:0] SUBADDRESS BYTE 1 SUBADDRESS BYTE 2

R/W

DATA BYTE 1

DATA BYTE 2

DATA BYTE N

MOSI/ADDR1

Figure 34. SPI Slave Write Clocking (Burst Write Mode, N Bytes)

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

SS/ADDR0

SCLK/SCL

CHIP ADDRESS[6:0]

SUBADDRESS BYTE 1

SUBADDRESS BYTE 2

MOSI/ADDR1

MISO/SDA

R/W

DATA BYTE 2

DATA BYTE 1

Figure 35. SPI Slave Read Clocking (Single Word Mode, Two Bytes)

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SS/ADDR0

SCLK/SCL

CHIP ADDRESS[6:0]

SUBADDRESS BYTE 1

SUBADDRESS BYTE 2

MOSI/ADDR1

MISO/SDA

R/W

DATA BYTE 1

DATA BYTE 2

DATA BYTE N

Figure 36. SPI Slave Read Clocking (Burst Read Mode, N Bytes)

Rev. A | Page 43 of 207

ADAU1463/ADAU1467

Data Sheet

8-bit aligned. By default, the SPI master port is in Mode 3

MASTER CONTROL PORTS

(CPOL = 1, CPHA = 1), which matches the mode of the SPI slave

port. The SPI master port can be configured to operate in Mode 0

(CPOL = 0, CPHA = 0) in the DSP program. No error detection

or handling is implemented. Single master operation is assumed;

therefore, no other master devices can exist on the same SPI bus.

The device contains a combined I²C and SPI master control port

that is accessible through a common interface. The master port

can be enabled through a self boot operation or directly from

the DSP core. The master control port can buffer up to 128 bits

of data per single interrupt period. The smallest data transfer

unit for both bus interfaces is one byte, and all transfers are 8-bit

aligned. No error detection is supported, and single master

operation is assumed. Only one bus interface protocol (I²C or

SPI) can be used at a time.

The SPI master interface was tested with EEPROM, flash, and

serial RAM devices and was confirmed to work in all cases.

When the data rate is very high on the SPI master interface (at

10 MHz or higher), a condition may arise where there is a high

level of current draw on the IOVDD supply, which can lead to

sagging of the internal IOVDD supply. To avoid potential issues,

design the PCB such that the traces connecting the SPI master

interface to external devices are kept as short as possible, and the

slew rate and drive strength for SPI master interface pins are kept

to a minimum to keep current draw as low as possible. Keeping

IOVDD low (2.5 V or 1.8 V) also reduces the IOVDD current

draw.

The master control port can be used for several purposes:

•

Self boot the ADAU1463/ADAU1467 from an external

serial EEPROM.

Boot and control external slave devices such as codecs and

amplifiers.

Read from and write to an external SPI RAM or flash

memory.

SPI Master Control Port

SigmaStudio generates EEPROM images for self boot systems,

requiring no manual SPI master port configuration or program-

ming on the part of the user.

I²C Master Control Port

The I²C master control port is 7-bit addressable and supports

standard and fast mode operation with speeds between 20 kHz

and 400 kHz. The serial camera control bus (SCCB) and power

management bus (PMBus) protocols are not supported. Data

transfers are 8-bit aligned. No error detection or correction is

implemented. The I²C master interface uses two general-purpose

input/output pins, MP2 and MP3. See Table 31 for more

information.

The SPI master control port supports up to seven slave devices

(via the MPx pins) and speeds between 2.3 kHz and 20 MHz.

SPI Mode 0 (CPOL = 0, CPHA = 0) and SPI Mode 3 (CPOL =

1, CPHA = 1) are supported. Communication is assumed to be

half duplex, and the SPI master control port does not support a

3-wire interface. There is no JTAG or SGPIO support. The SPI

interface uses a minimum of four general-purpose input/output

(GPIO) pins of the processor and up to six additional MPx pins

for additional slave select signals (SS). See Table 30 for more

information.

The SPI master clock frequency can range between 2.3 kHz and

20 MHz. JTAG and SGPIO are not supported. Data transfers are

Table 30. SPI Master Interface Pin Functionality

SPI Master

Function

Pin Name

Description

MOSI_M/MP1

MOSI

SPI master port data output. This pin sends data from the SPI master port to slave devices on the SPI

master bus.

SCL_M/SCLK_M/MP2

SDA_M/MISO_M/MP3 MISO

SCLK

SPI master port serial clock. This pin drives the clock signal to slave devices on the SPI master bus.

SPI master port data input. This pin receives data from slave devices on the SPI master bus.

SS_M/MP0

SS

SPI master port slave select. This pin acts as the primary slave select signal to slave device on the SPI

master bus.

MP4 to MP13

SS

SPI master port slave select. These additional multipurpose pins can be configured to act as secondary

slave select signals to additional slave devices on the SPI master bus. Up to seven slave devices, one

per pin, are supported.

Table 31. I²C Master Interface Pin Functionality

I²C Master

Function

Pin Name

Description

SCL_M/SCLK_M/MP2

SCL

I²C master port serial clock. This pin functions as an open collector output and drives a serial clock to

slave devices on the I²C bus. The line connected to this pin must have a 2 kΩ pull-up resistor to IOVDD.

SDA_M/MISO_M/MP3 SDA

I²C master port serial data. This pin functions as a bidirectional open collector data line between the

I²C master port and slave devices on the I²C bus. The line connected to this pin must have a 2 kΩ

pull-up resistor to IOVDD.

Rev. A | Page 44 of 207

Data Sheet

ADAU1463/ADAU1467

self boot failure is by reading back the status of Register 0xF427

(PANIC_FLAG) and Register 0xF428 (PANIC_CODE). The

contents of Register 0xF428 indicate the nature of the failure.

See the Reliability Features section for more information.

SELF BOOT

The master control port is capable of booting the device from a

single EEPROM by connecting the SELFBOOT pin to logic high

(IOVDD) and powering up the power supplies while the

pin is pulled high, which initiates a self boot operation. In self boot

operation, the master control port downloads all required memory

and register settings and automatically starts executing the DSP

program without requiring external intervention or supervision.

A self boot operation can also be triggered while the device is

RESET

EEPROM Self Boot Data Format

The self boot EEPROM image is generated using the SigmaStudio

software; thus, the user does not need to manually create the data

that is stored in the EEPROM. However, for reference, the details

of the data format are described in this section.

RESET

already in operation by initiating a rising edge of the

The EEPROM self boot format consists of a fixed header, an arbi-

trary number of variable length blocks, and a fixed footer. The

blocks themselves consist of a fixed header and a block of data

with a variable length. Each data block can be placed anywhere in

the DSP memory through configuration of the block header.

while the SELFBOOT pin is held high. When the self boot oper-

ation begins, the state of the SS_M/MP0 pin determines whether

the SPI master or the I²C master carries out the self boot operation.

If the SS_M/MP0 pin is connected to logic low, the I²C master

port carries out the self boot operation. Otherwise, connect this

pin to the slave select pin of the external slave device. The SPI

master port then carries out the self boot operation.

Header Format

The self boot EEPROM header consists of 16 bytes of data, starting

at the beginning of the internal memory of the slave EEPROM

(Address 0). The header format (see Figure 37) consists of the

following:

When self booting from SPI, the chip assumes the following:

•

The slave EEPROM is selected via the SS_M/MP0 pin.

The slave EEPROM has 16- or 24-bit addressing, giving it

a total memory size of between 4 kb and 64 Mb.

The slave EEPROM supports serial clock frequencies down

to 1 MHz or lower (a majority of the self boot operation uses

a much higher clock frequency, but the initial transactions

are performed at a slower frequency).

•

8-bit Sentinel 0xAA (shown in Figure 37 as 0b10101010)

24-bit address indicating the byte address of the header of

the first block (normally this is 0x000010, which is the

address immediately following the header)

•

64-bit PLL configuration (PLL_CHECKSUM =

PLL_FB_DIV + MCLK_OUT + PLL_DIV)

•

The data stored in the slave EEPROM follows the format

described in the EEPROM Self Boot Data Format section.

The data is stored in the slave EEPROM with the MSB first.

The slave EEPROM supports SPI Mode 3.

The slave EEPROM sequential read operation has the

command of 0x03.

Data Block Format

•

Following the header, several data blocks are stored in the

EEPROM memory (see Figure 38). Each data block consists of

eight bytes that configure the length and address of the data,

followed by a series of 4-byte data packets.

•

The slave EEPROM can be accessed immediately after it is

powered up, with no manual configuration required.

Each block consists of the following:

•

One LST bit, which signals the last block before the footer.

LST = 0b1 indicates the last block; LST = 0b0 indicates that

additional blocks are still to follow.

13 bits that are reserved for future use. Set these bits to 0b0.

Two MEM bits that select the target data memory bank

(0x0 = Data Memory 0, 0x1 = Data Memory 1, 0x2 =

program memory).

A 16-bit base address that sets the memory address at

which the master port starts writing when loading data

from the block into memory.

A 16-bit data length that defines the number of 4-byte

data-words to be written.

A 16-bit jump address that tells the DSP core at which

address in program memory it should begin execution

when the self boot operation is complete. The jump

address bits are ignored unless the LST bit is set to 0b1.

An arbitrary number of packets of 32-bit data. The number

of packets is defined by the 16-bit data length.

When self booting from I²C, the chip assumes the following:

•

The slave EEPROM has I²C Address 0x50.

The slave EEPROM has 16-bit addressing, giving it a size of

between 16 kb and 512 kb.

•

The slave EEPROM supports standard mode clock

frequencies of 100 kHz and lower (a majority of the self boot

operation uses a much higher clock frequency, but the

initial transactions are performed at a slower frequency).

The data stored in the slave EEPROM follows the format

described in the EEPROM Self Boot Data Format section.

The slave EEPROM can be accessed immediately after it is

powered, with no manual configuration required.

•

Self Boot Failure

The SPI or I²C master port attempts to self boot from the EEPROM

three times. If all three self boot attempts fail, the SigmaDSP core

issues a software panic and then enters a sleep state. During a

self boot operation, the panic manager is unable to output a panic

flag on a multipurpose pin. Therefore, the only way to debug a

•

Rev. A | Page 45 of 207

ADAU1463/ADAU1467

Data Sheet

When the EEPROM memory is divided, the memory portion that

resides at a different chip address must be handled as though it

exists in a separate EEPROM.

Footer Format

After all the data blocks, a footer signifies the end of the self boot

EEPROM memory (see Figure 39). The footer consists of a 64-bit

checksum, which is the sum of the header and all blocks and all

data as 32-bit words.

Considerations When Using Multiple EEPROMs on the SPI

Master Bus

When multiple EEPROMs are connected on the same SPI master

bus, the self boot mechanism works only with the first EEPROM.

After the self boot operation completes, the checksum of the

downloaded data is calculated and the panic manager signals if

it does not match the checksum in the EEPROM. If the checksum

is set to 0 (decimal), the checksum checking is disabled.

SERIAL DATA INPUT/OUTPUT

There are four serial data input pins (SDATA_IN3 to SDATA_IN0)

and four serial data output pins (SDATA_OUT3 to SDATA_

OUT0). Each pin is capable of 2-channel, 4-channel, or 8-channel

mode. In addition, SDATA_IN0, SDATA_IN1, SDATA_OUT0,

and SDATA_OUT1 are capable of 16-channel mode.

Considerations When Using a 1 Mb I²C Self Boot EEPROM

Because of the way I²C addressing works, 1 Mb of I²C EEPROM

memory can be divided, with a portion of its address space at

Chip Address 0x50; another portion of the memory can be located

at a different address (for example, Chip Address 0x51). The

memory allocation varies, depending on the EEPROM design.

The serial ports have a very flexible configuration scheme that

allows completely independent and orthogonal configuration of

clock pin assignment, clock waveform type, clock polarity, channel

count, position of the data bits within the stream, audio word

length, slave or master operation, and sample rate. A detailed

description of all possible serial port settings is included in the

Serial Port Configuration Registers section.

BYTE 0

BYTE 1

BYTE 2

BYTE 3

1

0

1

0

1

0

1

0

ADDRESS OF FIRST BOOT BLOCK

BYTE 4

0x00

BYTE 5

BYTE 6

0x00

BYTE 7

PLL_DIV

PLL_FB_DIV

BYTE 8

0x00

BYTE 9

BYTE 10

0x00

BYTE 11

PLL_CHECKSUM

MCLK_OUT

BYTE 12

BYTE 13

BYTE 14

BYTE 15

EEPROM SPEED CONFIGURATION

Figure 37. Self Boot EEPROM Header Format

BYTE 0

BYTE 4

BYTE 8

BYTE 12

BYTE 1

MEM

BYTE 2

BYTE 3

LST

RESERVED

BASE ADDRESS

BYTE 5

BYTE 6

BYTE 7

BYTE 11

BYTE 15

DATA LENGTH

JUMP ADDRESS

BYTE 9

BYTE 10

BYTE 14

DATA-WORD 1

BYTE 13

DATA-WORD 2

CONTINUED UNTIL LAST WORD IS REACHED…

FOURTH TO LAST BYTE

THIRD TO LAST BYTE

DATA-WORD N

SECOND TO LAST BYTE

LAST BYTE

Figure 38. Self Boot EEPROM Data Block Format

BYTE 0

BYTE 4

BYTE 1

BYTE 2

BYTE 3

FIRST FOUR BYTES OF CHECKSUM

BYTE 5 BYTE 6

LAST FOUR BYTES OF CHECKSUM

BYTE 7

Figure 39. Self Boot EEPROM Footer Format

Rev. A | Page 46 of 207

Data Sheet

ADAU1463/ADAU1467

The physical serial data input and output pins are connected to

functional blocks called serial ports, which handle the audio

data and clocks as they pass in and out of the device. Table 32

describes this relationship. These primary serial data pins are

augmented by the SDATAIOx pins. See the SDATAIOx Pins

section for more information.

In 32-bit mode (see Figure 40), the 32 bits received on the serial

input are mapped directly to a 32-bit word in the DSP core.

MSB

AUDIO MSB

24-BIT

AUDIO

SAMPLE

24-BIT

AUDIO

SAMPLE

24-BIT

AUDIO

SAMPLE

ROUTING

MATRIX

Table 32. Relationship Between Hardware Serial Data Pins

and Serial Input/Output Ports

Serial Data Pin

Serial Port

8-BIT DATA

AUDIO LSB

8-BIT DATA

AUDIO LSB

8-BIT DATA

AUDIO LSB

SDATA_IN0

SDATA_IN1

SDATA_IN2

SDATA_IN3

SDATA_OUT0

SDATA_OUT1

SDATA_OUT2

SDATA_OUT3

Serial Input Port 0

Serial Input Port 1

Serial Input Port 2

Serial Input Port 3

Serial Output Port 0

Serial Output Port 1

Serial Output Port 2

Serial Output Port 3

LSB

32-BIT

SERIAL AUDIO

INPUT STREAM

32-BIT

INPUT PORT

DSP CORE

Figure 40. 32-Bit Serial Input Example

There are 48 channels of serial audio data inputs and 48 channels

of serial audio data outputs. The 48 audio input channels and

48 audio output channels are distributed among the four serial

data input pins and the four serial data output pins. This

distribution is described in Table 43.

The maximum sample rate for the serial audio data on the serial

ports is 192 kHz. The minimum sample rate is 6 kHz.

SDATA_IN2, SDATA_IN3, SDATA_OUT2, and SDATA_OUT3

are capable of operating in a special mode called flexible TDM

mode, which allows custom byte addressable configuration,

where the data for each channel is located in the serial data stream.

Flexible TDM mode is not a standard audio interface. Use it only

in cases where a customized serial data format is desired. See the

Flexible TDM Interface section for more information.

Figure 41. Selecting 32-Bit Serial Input Mode in SigmaStudio

If a serial input port is configured using the SERIAL_BYTE_x_0

registers, Bits[2:0] (TDM_MODE) for a number of channels that

is less than its maximum channel count, the unused channels are

zero data streams unless the serial data is input on an SDATAIOx

pin. For example, if Serial Input 0 is set in 8-channel (TDM8)

mode, the first eight channels (Channel 0 to Channel 7) carry data;

and the unused channels (Channel 8 to Channel 15) carry no data

unless one of the SDATAIOx pins is configured to input, and

properly receiving, the upper eight channels. See the SDATAIOx

Pins section for more information.

Serial Audio Data Format

The serial data input and output ports are designed to work with

audio data that is encoded in a linear pulse code modulation

(PCM) format, including the common I²S standard. Audio data-

words can be 16, 24, or 32 bits in length. The serial ports can

handle time division multiplexed (TDM) formats with channel

counts ranging from two channels to 16 channels on a single

data line.

Almost every aspect of the serial audio data format can be con-

figured using the SERIAL_BYTE_x_0 and SERIAL_BYTE_x_1

registers, and every setting can be configured independently. As a

result, there are more than 70,000 valid configurations for each

serial audio port.

In the default 24-bit mode (see Figure 45), the 24-bit audio

sample (in 1.23 format) is padded with eight zeros below its LSB

(in 1.31 format) as it is input to the routing matrix. Then, the

audio data is shifted such that the audio sample has seven sign

extended zeros on top, one padded zero on the bottom, and

24 bits of data in the middle (8.24 format).

Serial Input Ports

There are four options for the word length of each serial input port:

24 bits, 16 bits, 32 bits, or flexible TDM. The flexible TDM option is

described in the Flexible TDM Input section. The data is received

and processed by the core in its native 32-bit format in all cases.

Whereas 16-bit mode is similar to 24-bit mode, the 16-bit audio

data has 16 zeros below its LSB instead of just eight zeros (in the

24-bit case). The resulting 8.24 sample, therefore, has seven sign

extended zeros on top, nine padded zeros on the bottom, and

16 bits of data in the middle (8.24 format).

Rev. A | Page 47 of 207

ADAU1463/ADAU1467

Data Sheet

MSB

AUDIO MSB

Serial Output Ports

There is a one-to-one mapping between the serial output ports

and the output audio channels in the DSP (see Table 33).

32-BIT

WORD

ROUTING

MATRIX

32-BIT

WORD

32-BIT

WORD

Table 33. Relationship Between Serial Input Port and

Corresponding DSP Output Channel Numbers

Serial Input Port Audio Output Channels from the DSP

Serial Output 0

Serial Output 1

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,

28, 29, 30, 31

32, 33, 34, 35, 36, 37, 38, 39

40, 41, 42, 43, 44, 45, 46, 47

AUDIO LSB

32-BIT

AUDIO LSB

32-BIT

LSB

OUTPUT PORT SERIAL AUDIO

OUTPUT STREAM

Serial Output 2

Serial Output 3

Figure 42. 32-Bit Serial Output Example

If a serial output port is configured using the SERIAL_BYTE_x_0

registers, Bits[2:0] (TDM_MODE), for a number of channels that

is less than its maximum channel count, the unused channels

are ignored unless the serial data is output on an SDATAIOx pin.

For example, if Serial Output Port 0 is set in 8-channel (TDM8)

mode, and data is routed to it from the DSP, the first eight DSP

output channels (Channel 0 through Channel 7) are output on

SDATA_OUT0. The remaining channels (Channel 8 through

Channel 15) are only output from the device if one of the

SDATAIOx pins is configured to output the upper eight channels.

See the SDATAIOx Pins section for more information.

There are four options for the word length of each serial output

port: 24 bits, 16 bits, 32 bits, or flexible TDM. See the Flexible

TDM Output section for more information.

Figure 43. Selecting 32-Bit Serial Output Mode in SigmaStudio

In 32-bit mode (see Figure 42), all 32 bits from the 8.24 word in

the DSP core are copied directly to the serial output. To use 32-bit

mode, the special 32-bit output cells must be used in SigmaStudio.

In 16-bit mode, the top seven MSBs of the 8.24 audio word in

the DSP core are saturated, and the resulting 1.23 word is then

truncated to a 1.15 word by removing the eight LSBs. The

resulting 1.15 word is then zero padded with 16 zeros under the

LSB and output from the serial port.

Figure 44. Packing and Unpacking the 16-Bit Audio in SigmaStudio

MSB

AUDIO MSB

SIGN

EXTENDED

AUDIO MSB

1.23

AUDIO

SAMPLE

1.23

AUDIO

SAMPLE

ROUTING

MATRIX

1.23

AUDIO

SAMPLE

AUDIO LSB

ZEROS

LSB

24-BIT SERIAL

AUDIO INPUT

STREAM

AUDIO LSB

LSB

ZERO

LSB

DSP CORE

24-BIT

INPUT PORT

Figure 45. 24-Bit Serial Input Example

Rev. A | Page 48 of 207

Data Sheet

ADAU1463/ADAU1467

+1

–1

+127.999...

MSB

–1

+1

–128

x: DSP CORE OUTPUT

y: SERIAL PORT OUTPUT

MSB

AUDIO MSB

7 MSBs

SATURATED

TO ±1 IF

AUDIO MSB

OUTPUT IS >1

1.23

AUDIO

SAMPLE

1.23

AUDIO

SAMPLE

SATURATOR/

CLIPPER

ROUTING

MATRIX

24-BITS

AUDIO LSB

8 ZEROS

LSB

24-BIT

SERIAL AUDIO

OUTPUT STREAM

1 LSB

TRUNCATED

AUDIO LSB

DSP CORE

LSB

24-BIT

OUTPUT PORT

Figure 46. 24-Bit Serial Output Example

16 CH

SERIAL

INPUT 0 TO INPUT 15

INPUT 16 TO INPUT 31

SDATA_IN0

(2 CH TO 16 CH)

INPUT

PORT 0

SERIAL

INPUT

PORT 1

16 CH

8 CH

SDATA_IN1

(2 CH TO 16 CH)

SERIAL

INPUT

PORT 2

INPUT 32 TO INPUT 39

INPUT 40 TO INPUT 47

SDATA_IN2

(2 CH TO 8 CH)

SERIAL

INPUT

PORT 3

SDATA_IN3

(2 CH TO 8 CH)

Figure 47. Serial Port Audio Input Mapping to DSP in SigmaStudio

Figure 47 shows how the input pins map to the input cells in

SigmaStudio, including their graphical appearance in the software.

Serial Audio Inputs to DSP Core

The 48 serial input channels are mapped to four audio input

cells in SigmaStudio. Each input cell corresponds to one of the

serial input pins (see Table 34).

Table 34. Serial Input Pin Mapping to SigmaStudio Input Cells

Serial Input Pin

SDATA_IN0

SDATA_IN1

SDATA_IN2

SDATA_IN3

Channels in SigmaStudio

0 to 15

16 to 31

32 to 39

40 to 47

Depending on whether the serial port is configured in 2-channel,

4-channel, 8-channel, or 16-channel mode, the available channels

in SigmaStudio change. The channel count for each serial port

is configured in the SERIAL_BYTE_x_0 registers, Bits[2:0]

(TDM_MODE), at Address 0xF200 to Address 0xF21C (in

increments of 0x4).

Rev. A | Page 49 of 207

ADAU1463/ADAU1467

Data Sheet

Table 35. Detailed Serial Input Mapping to SigmaStudio Input Channels¹

Input Channel

in SigmaStudio

Serial Input

Position in I²S

Stream (2-Channel)

Position in

TDM4 Stream

Position in

TDM8 Stream

Position in

TDM16 Stream

SDATA_IN0

SDATA_IN1

SDATA_IN2

SDATA_IN3

Left

Right

0

1

2

3

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

0

1

2

3

4

5

6

7

Not applicable

First SDATAIOx left

First SDATAIOx right

Not applicable

Second SDATAIOx left

Second SDATAIOx right

Not applicable

Third SDATAIOx left

Third SDATAIOx right

Not applicable

Left

First SDATAIOx

Second SDATAIOx

Third SDATAIOx

0

First SDATAIOx

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Right

1

2

3

Not applicable

First SDATAIOx left

First SDATAIOx right

Not applicable

Second SDATAIOx left

Second SDATAIOx right

Not applicable

Third SDATAIOx left

Third SDATAIOx right

Not applicable

Left

First SDATAIOx

Second SDATAIOx

Third SDATAIOx

0

First SDATAIOx

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

Not applicable

Right

1

2

3

Not applicable

SDATAIOx left

SDATAIOx right

Not applicable

Left

First SDATAIOx

0

1

2

3

First SDATAIOx

Right

Not applicable

SDATAIOx left

SDATAIOx right

Not applicable

¹Any of the eight SDATAIOx pins can be assigned to any input.

Rev. A | Page 50 of 207

Data Sheet

ADAU1463/ADAU1467

the SDATA_OUT0 pin. The next 16 channels are mapped to the

SDATA_OUT1 pin. The following eight channels are mapped to

the SDATA_OUT2 pin. The last eight channels are mapped to

the SDATA_OUT3 pin (see Table 36 and Figure 48).

Serial Audio Outputs from DSP Core

The 48 serial output channels are mapped to 48 separate audio

output cells in SigmaStudio. Each audio output cell corresponds

to a single output channel. The first 16 channels are mapped to

OUTPUT 0 TO

OUTPUT 15

16 CH

SERIAL

OUTPUT

PORT 0

SDATA_OUT0

(2 CH TO 16 CH)

OUTPUT 16 TO

OUTPUT 31

16 CH

SERIAL

OUTPUT

PORT 1

SDATA_OUT1

(2 CH TO 16 CH)

OUTPUT 32 TO

OUTPUT 39

8 CH

SERIAL

OUTPUT

PORT 2

SDATA_OUT2

(2 CH TO 8 CH)

OUTPUT 40 TO

OUTPUT 47

8 CH

SERIAL

OUTPUT

PORT 3

SDATA_OUT3

(2 CH TO 8 CH)

FROM SERIAL INPUTS, PDM MICS,

S/PDIF RECEIVER, AND ASRCS

Figure 48. DSP to Serial Output Mapping in SigmaStudio

Rev. A | Page 51 of 207

ADAU1463/ADAU1467

Data Sheet

Table 36. Serial Output Pin Mapping from SigmaStudio Channels¹

Position in I²S Stream

(2-Channel)

Position in

TDM4 Stream

Position in

TDM8 Stream

Position in

TDM16 Stream

Output Channel

in SigmaStudio

Serial Output

0

1

2

3

4

5

6

7

SDATA_OUT0

SDATA_OUT1

SDATA_OUT2

SDATA_OUT3

Left

Right

0

1

2

3

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Not applicable

First SDATAIOx left

First SDATAIOx right

Not applicable

Second SDATAIOx left

Second SDATAIOx right

Not applicable

Third SDATAIOx left

Third SDATAIOx right

Not applicable

Left

First SDATAIOx

Second SDATAIOx

Third SDATAIOx

0

8

9

First SDATAIOx

0

1

2

3

4

5

6

7

First SDATAIOx

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

Right

1

2

3

Not applicable

First SDATAIOx left

First SDATAIOx right

Not applicable

Second SDATAIOx left

Second SDATAIOx right

Not applicable

Third SDATAIOx left

Third SDATAIOx right

Not applicable

Left

First SDATAIOx

Second SDATAIOx

Third SDATAIOx

0

Not applicable

Right

1

2

3

Not applicable

SDATAIOx left

SDATAIOx right

Not applicable

Left

First SDATAIOx

0

1

2

3

First SDATAIOx

Right

Not applicable

SDATAIOx left

SDATAIOx right

Not applicable

¹Any of the eight SDATAIOx pins can be assigned to any output.

Rev. A | Page 52 of 207

Data Sheet

ADAU1463/ADAU1467

For example, Serial Output Port 0 is capable of transmitting

16 channels of audio data. However, this transmission requires

that Serial Output Port 0 operate in TDM16 mode, which relatively

few ICs are able to receive. More importantly, it reduces system

flexibility. Applications typically require the SigmaDSP to transmit

multiple stereo or TDM4 streams. These streams typically are

synchronous, and share a bit clock and frame sync.

SDATAIOx PINS

The eight SDATAIOx pins supplement the four input and four

output serial ports by providing additional data pins. They are

not additional, independent serial ports. Each pin can be con-

figured for use with any serial input port or serial output port.

The ADAU1463/ADAU1467 serial audio input and output ports

are capable of receiving and transmitting 48 channels, respectively.

However, this maximum number of input/output channels is only

possible when Serial Port 0 and Serial Port 1 run in TDM16 mode

and Serial Port 2 and Serial Port 3 run in TDM8 mode. This

configuration is not the case in most applications. I²S (2-channel)

and TDM4 (4-channel) modes are commonly used in applications.

In these modes with lower bit rates, the upper channels cannot be

received or transmitted on the SDATA pin of the serial audio port.

The SDATAIOx pins enable this system architecture. Instead

of all 16 channels being transmitted on a single pin, as in the

preceding example, the 16 channels of audio data can be trans-

mitted in TDM4 mode on four data pins, the primary serial

port data pin with three of the SDATAIOx pins. These TDM4

streams can be sent to different receivers, but they must share

the bit clock and frame sync of Serial Output Port 0.

Note that the bit clock and frame sync signals retain the same

flexibility. They can be clock master or slave and retain all of the

normal possible formatting combinations. The SDATAIOx pins

use the same signal format as the primary serial data pin. Their

format cannot be configured independently. See Table 36, Table 37,

and Table 38 for more information about SDATAIOx pin

format and channels.

The SDATAIOx pins provide a solution to this problem. By adding

additional serial data pins, the serial ports can run at less than

their maximum rates and transmit or receive more channels of

audio data than is otherwise possible. These additional pins use

the same format, bit clock, and frame clock as the primary serial

port data pin, but they can carry the upper channels, which is

otherwise unusable.

Table 37. SDATAIOx Channels for Serial Audio Data Inputs

Primary Serial Data Pin

Serial Data Pin Format Serial Data Pin Channels

SDATAIOx Pin Format SDATAIOx Pin Channel Options

SDATA_IN0

SDATA_IN1

SDATA_IN2

Stereo

TDM4

TDM8

Stereo

TDM4

TDM8

Stereo

TDM4

Stereo

TDM4

0 and 1

0 to 3

0 to 7

16 and 17

16 to 19

16 to 23

32 and 33

32 to 36

40 and 41

40 to 43

Stereo

TDM4

TDM8

Stereo

TDM4

TDM8

Stereo

TDM4

Stereo

TDM4

4 and 5, 8 and 9, 12 and 13

4 to 7, 8 to 11, 12 to 15

8 to 15

20 and 21, 24 and 25, 28 and 29

20 to 23, 24 to 27, 28 to 31

24 to 31

36 and 37

37 to 40

44 and 45

44 to 47

SDATA_IN3

Table 38. SDATAIOx Channels for Serial Audio Data Outputs

Primary Serial Data Pin

SDATA_OUT0

SDATA_OUT1

SDATA_OUT2

SDATA_OUT3

Serial Data Pin Format

Serial Data Pin Channels SDATAIOx Pin Format

SDATAIOx Pin Channel Options

4 and 5, 8 and 9, 12 and 13

4 to 7, 8 to 11, 12 to 15

8 to 15

20 and 21, 24 and 25, 28 and 29

20 to 23, 24 to 27, 28 to 31

24 to 31

36 and 37

37 to 40

44 and 45

44 to 47

Stereo

TDM4

TDM8

Stereo

TDM4

TDM8

Stereo

TDM4

Stereo

TDM4

0 and 1

0 to 3

Stereo

TDM4

TDM8

Stereo

TDM4

TDM8

Stereo

TDM4

Stereo

TDM4

0 to 7

16 and 17

16 to 19

16 to 23

32 and 33

32 to 36

40 and 41

40 to 43

Rev. A | Page 53 of 207

ADAU1463/ADAU1467

Data Sheet

Configuring Input Channel Count with SDATAIOx

Serial Audio Data Timing Diagrams

Serial data input ports and serial data output ports are config-

ured slightly differently when used together with SDATAIOx

pins. If two or more stereo streams are received by an input

port, the received format must be configured as four channels

(TDM4) rather than two channels. For output streams, the

configuration must match the true channel count as shown in

Table 39.

Because it is impractical to show timing diagrams for each

possible combination, timing diagrams for the more common

configurations are shown in Figure 49 to Figure 54. Explanatory

text accompanies each figure.

Figure 49 shows timing diagrams for possible serial port con-

figurations in 2-channel mode, with 32 cycles of the bit clock

signal per channel, for a total of 64 bit clock cycles per frame

(see the SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE) =

0b000). Different bit clock polarities are illustrated in Figure 49

(SERIAL_BYTE_x_0, Bit 7 (BCLK_POL)) as well as different

frame clock waveforms and polarities (SERIAL_BYTE_x_0, Bit 9

(LRCLK_MODE) and Bit 8 (LRCLK_POL)). Excluding flexible

TDM mode, there are 12 possible combinations of settings for the

audio word length (SERIAL_BYTE_x_0, Bits[6:5] (WORD_LEN))

and MSB position (SERIAL_BYTE_x_0, Bits[4:3] (DATA_FMT)),

all of which are shown in Figure 49.

Table 39. SERIAL_BYTE_n_0 with SDATAIOx Pins

Configuration

Port Direction

Input

Channel Count

In SERIAL_BYTE_n_0

2

4

Input

4

Input

8

Input

16

2

4

8

16

2

4

8

16

Output

Figure 50 shows timing diagrams for possible serial port

configurations in 4-channel mode, with 32 bit clock cycles per

channel, for a total of 128 bit clock cycles per frame (refer to the

SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE) = 0b001).

The bit clock signal is omitted from Figure 50.

SERIAL CLOCK DOMAINS

There are four input clock domains and four output clock

domains. A clock domain consists of a pair of LRCLK_OUTx

and LRCLK_INx (frame clock) and BCLK_OUTx and BCLK_INx

(bit clock) pins that ynchronize the transmission of audio data

to and from the device. There are eight total clock domains.

Four of them are input domains and four of them are output

domains. In master mode (refer to the SERIAL_BYTE_x_0

registers, Register 0xF200 to Register 0xF21C, Bits[15:13] (LRCLK_

SRC) = 0b100 and Bits[12:10] (BCLK_SRC) = 0b100), each clock

domain corresponds to exactly one serial data pin, one frame clock

pin, and one bit clock pin. Any serial data input can be clocked

by any input clock domains when it is configured in slave mode

(refer to the SERIAL_BYTE_x_0 registers, Bits[15:13] (LRCLK_

SRC), which can be set to 0b000, 0b001, 0b010, or 0b011; and

Bits[12:10] (BCLK_SRC), which can be set to 0b000, 0b001, 0b010,

or 0b011). Any serial data output can be clocked by any output

clock domain when it is configured in slave mode (see the

SERIAL_BYTE_x_0 registers, Bits[15:13] (LRCLK_SRC), which

can be set to 0b000, 0b001, 0b010, or 0b011; and Bits[12:10]

(BCLK_SRC), which can be set to 0b000, 0b001, 0b010, or 0b011).

Excluding flexible TDM mode, there are 12 possible combinations

of settings for the audio word length (SERIAL_BYTE_x_0, Bits[6:5]

(WORD_LEN)) and MSB position (SERIAL_BYTE_x_0, Bits[4:3]

(DATA_FMT)), all of which are shown in Figure 50.

Figure 51 shows timing diagrams for possible serial port con-

figurations in 8-channel mode, with 32 bit clock cycles per

channel, for a total of 256 bit clock cycles per frame (refer to the

SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE) = 0b010).

The bit clock signal is omitted from Figure 51.

Excluding flexible TDM mode, there are 12 possible combinations

of settings for the audio word length (SERIAL_BYTE_x_0, Bits[6:5]

(WORD_LEN)) and MSB position (SERIAL_BYTE_x_0, Bits[4:3]

(DATA_FMT)), all of which are shown in Figure 51.

Figure 52 shows some timing diagrams for possible serial port

configurations in 16-channel mode, with 32 bit clock cycles per

channel, for a total of 512 bit clock cycles per frame (refer to the

SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE) = 0b011).

The bit clock signal is omitted from Figure 52.

Excluding flexible TDM mode, there are 12 possible combinations

of settings for the audio word length (SERIAL_BYTE_x_0, Bits[6:5]

(WORD_LEN)) and MSB position (SERIAL_BYTE_x_0, Bits[4:3]

(DATA_FMT)), all of which are shown in Figure 52

Rev. A | Page 54 of 207

Data Sheet

ADAU1463/ADAU1467

Table 40. Relationship Between Serial Data Pins and Clock Pins in Master or Slave Mode

Serial Data Pin

Corresponding Clock Pins in Master Mode

Corresponding Clock Pins in Slave Mode

SDATA_IN0

BCLK_IN0, LRCLK_IN0 (LRCLK_IN0/MP10)

BCLK_IN0, LRCLK_IN0, BCLK_IN1, LRCLK_IN1, BCLK_IN2, LRCLK_IN2,

BCLK_IN3, or LRCLK_IN3

SDATA_IN1

BCLK_IN1, LRCLK_IN1 (LRCLK_IN1/MP11)

BCLK_IN2, LRCLK_IN2 (LRCLK_IN2/MP12)

BCLK_IN3, LRCLK_IN3 (LRCLK_IN3/MP13)

BCLK_IN0, LRCLK_IN0, BCLK_IN1, LRCLK_IN1, BCLK_IN2, LRCLK_IN2,

BCLK_IN3, or LRCLK_IN3

SDATA_IN2

BCLK_IN0, LRCLK_IN0, BCLK_IN1, LRCLK_IN1, BCLK_IN2, LRCLK_IN2,

BCLK_IN3, or LRCLK_IN3

SDATA_IN3

BCLK_IN0, LRCLK_IN0, BCLK_IN1, LRCLK_IN1, BCLK_IN2, LRCLK_IN2,

BCLK_IN3, or LRCLK_IN3

SDATA_OUT0

SDATA_OUT1

SDATA_OUT2

SDATA_OUT3

BCLK_OUT0, LRCLK_OUT0 (LRCLK_OUT0/MP4) BCLK_OUT0, LRCLK_OUT0, BCLK_OUT1, LRCLK_OUT1, BCLK_OUT2,

LRCLK_OUT2, BCLK_OUT3, or LRCLK_OUT3

BCLK_OUT1, LRCLK_OUT1 (LRCLK_OUT1/MP5) BCLK_OUT0, LRCLK_OUT0, BCLK_OUT1, LRCLK_OUT1, BCLK_OUT2,

LRCLK_OUT2, BCLK_OUT3, or LRCLK_OUT3

BCLK_OUT2, LRCLK_OUT2 (LRCLK_OUT2/MP8) BCLK_OUT0, LRCLK_OUT0, BCLK_OUT1, LRCLK_OUT1, BCLK_OUT2,

LRCLK_OUT2, BCLK_OUT3, or LRCLK_OUT3

BCLK_OUT3, LRCLK_OUT3 (LRCLK_OUT3/MP9) BCLK_OUT0, LRCLK_OUT0, BCLK_OUT1, LRCLK_OUT1, BCLK_OUT2,

LRCLK_OUT2, BCLK_OUT3, or LRCLK_OUT3

Rev. A | Page 55 of 207

ADAU1463/ADAU1467

Data Sheet

0 5 9 1 4

Figure 49. Serial Audio Formats; Two Channels, 32 Bits per Channel

Rev. A | Page 56 of 207

Data Sheet

ADAU1463/ADAU1467

0 6 0 1 4

Figure 50. Serial Audio Data Formats; Four Channels, 32 Bits per Channel

Rev. A | Page 57 of 207

ADAU1463/ADAU1467

Data Sheet

0 6 1 1 4

Figure 51. Serial Audio Data Formats; Eight Channels, 32 Bits per Channel

Rev. A | Page 58 of 207

Data Sheet

ADAU1463/ADAU1467

0 6 2 1 4

Figure 52. Serial Audio Data Formats; 16 Channels, 32 Bits per Channel

Rev. A | Page 59 of 207

ADAU1463/ADAU1467

Data Sheet

Figure 53 shows timing diagrams for possible serial port

configurations in 4-channel mode, with 16 bit clock cycles per

channel, for a total of 64 bit clock cycles per frame (refer to the

SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE) = 0b100).

Different bit clock polarities are shown (refer to the SERIAL_

BYTE_x_0 registers, Bit 7 (BCLK_POL)). The audio word length

is fixed at 16 bits (refer to the SERIAL_BYTE_x_0 registers,

Bits[6:5] (WORD_LEN) = 0b01), and there are four possible

configurations for MSB position (SERIAL_BYTE_x_0, Bits[4:3]

(DATA_FMT)), all of which are shown in Figure 53.

0 6 3 1 4

Figure 53. Serial Audio Data Formats; Four Channels, 16 Bits per Channel

Rev. A | Page 60 of 207

Data Sheet

ADAU1463/ADAU1467

Figure 54 shows some timing diagrams for possible serial port

configurations in 2-channel mode, with 16 bit clock cycles per

channel, for a total of 32 bit clock cycles per frame (refer to the

SERIAL_BYTE_x_0 registers, Register 0xF200 to Register 0xF21C,

Bits[2:0] (TDM_MODE) = 0b101).

Different bit clock polarities are illustrated (SERIAL_BYTE_x_0,

Bit 7 (BCLK_POL)). The audio word length is fixed at 16 bits

(SERIAL_BYTE_x_0, Bits[6:5] (WORD_LEN) = 0b01), and

there are four possible configurations for MSB position (SERIAL_

BYTE_x_0, Bits[4:3] (DATA_FMT)), all of which are shown in

Figure 54.

0 6 4 1 4

Figure 54. Serial Audio Data Formats; Two Channels, 16 Bits per Channel

Rev. A | Page 61 of 207

ADAU1463/ADAU1467

Data Sheet

Serial Port Registers

An overview of the registers related to the serial ports is shown

in Table 41. For a more detailed description, see the Serial Port

Configuration Registers section.

Table 41. Serial Port Registers

Address

0xF200

0xF201

0xF204

0xF205

0xF208

0xF209

0xF20C

0xF20D

0xF210

0xF211

0xF214

0xF215

0xF218

0xF219

0xF21C

0xF21D

0xF240

0xF241

0xF242

0xF243

0xF245

0xF246

0xF247

Register

Description

SERIAL_BYTE_0_0

SERIAL_BYTE_0_1

SERIAL_BYTE_1_0

SERIAL_BYTE_1_1

SERIAL_BYTE_2_0

SERIAL_BYTE_2_1

SERIAL_BYTE_3_0

SERIAL_BYTE_3_1

SERIAL_BYTE_4_0

SERIAL_BYTE_4_1

SERIAL_BYTE_5_0

SERIAL_BYTE_5_1

SERIAL_BYTE_6_0

SERIAL_BYTE_6_1

SERIAL_BYTE_7_0

SERIAL_BYTE_7_1

SDATA_0_ROUTE

SDATA_1_ROUTE

SDATA_2_ROUTE

SDATA_3_ROUTE

SDATA_4_ROUTE

SDATA_5_ROUTE

SDATA_6_ROUTE

SDATA_7_ROUTE

Serial Port Control 0 (SDATA_IN0 pin)

Serial Port Control 1 (SDATA_IN0 pin)

Serial Port Control 0 (SDATA_IN1 pin)

Serial Port Control 1 (SDATA_IN1 pin)

Serial Port Control 0 (SDATA_IN2 pin)

Serial Port Control 1 (SDATA_IN2 pin)

Serial Port Control 0 (SDATA_IN3 pin)

Serial Port Control 1 (SDATA_IN3 pin)

Serial Port Control 0 (SDATA_OUT0 pin)

Serial Port Control 1 (SDATA_OUT0 pin)

Serial Port Control 0 (SDATA_OUT1 pin)

Serial Port Control 1 (SDATA_OUT1 pin)

Serial Port Control 0 (SDATA_OUT2 pin)

Serial Port Control 1 (SDATA_OUT2 pin)

Serial Port Control 0 (SDATA_OUT3 pin)

Serial Port Control 1 (SDATA_OUT3 pin)

Configuration for SDATAIO0

Configuration for SDATAIO1

Configuration for SDATAIO2

Configuration for SDATAIO3

Configuration for SDATAIO4

Configuration for SDATAIO5

Configuration for SDATAIO6

Configuration for SDATAIO7

Rev. A | Page 62 of 207

Data Sheet

ADAU1463/ADAU1467

ASRC Muting

ASYNCHRONOUS SAMPLE RATE CONVERTERS

The ASRC outputs can be manually muted at any time using the

corresponding bits in Register 0xF581 (ASRC_MUTE). However,

for creating a smooth volume ramp when muting audio signals,

more options are available in the DSP core; therefore, in most

cases, using the DSP program to manually mute signals is

preferable to using Register 0xF581.

Sixteen channels of integrated asynchronous sample rate converters

are available in the ADAU1463/ADAU1467. These sample rate

converters are capable of receiving audio data input signals,

along with their corresponding clocks, and resynchronizing the

data stream to an arbitrary target sample rate. The sample rate

converters use some filtering to accomplish this task; therefore,

the data output from the sample rate converter is not a bit

accurate representation of the data input.

Asynchronous Sample Rate Converters Registers

An overview of the registers related to the ASRCs is shown in

Table 42. For a more detailed description, refer to the ASRC

Status and Control Registers section.

The 16 channels of sample rate converters are grouped into eight

stereo sets. These eight stereo sample rate converters are indivi-

dually configurable and are referred to as ASRC 0 through ASRC 7,

as follows:.

Table 42. Asynchronous Sample Rate Converters Registers

Address Register

Description

ASRC lock status

ASRC mute

•

Channel 0 and Channel 1 belong to ASRC 0

Channel 2 and Channel 3 belong to ASRC 1

Channel 4 and Channel 5 belong to ASRC 2

Channel 6 and Channel 7 belong to ASRC 3

Channel 8 and Channel 9 belong to ASRC 4

Channel 10 and Channel 11 belong to ASRC 5

Channel 12 and Channel 13 belong to ASRC 6

Channel 14 and Channel 15 belong to ASRC 7

0xF580

0xF581

0xF582

ASRC_LOCK

ASRC_MUTE

ASRC0_RATIO

ASRC ratio (ASRC 0,

Channel 0 and Channel 1)

0xF583

0xF584

0xF585

0xF586

0xF587

0xF588

0xF589

ASRC1_RATIO

ASRC2_RATIO

ASRC3_RATIO

ASRC4_RATIO

ASRC5_RATIO

ASRC6_RATIO

ASRC7_RATIO

ASRC ratio (ASRC 1,

Channel 2 and Channel 3)

ASRC ratio (ASRC 2,

Channel 4 and Channel 5)

ASRC ratio (ASRC 3,

Channel 6 and Channel 7)

ASRC ratio (ASRC 4,

Channel 8 and Channel 9)

ASRC ratio (ASRC 5,

Channel 10 and Channel 11)

ASRC ratio (ASRC 6,

Channel 12 and Channel 13)

Audio is routed to the sample rate converters using the

ASRC_INPUTx registers, and the target sample rate of each

ASRC is configured using the ASRC_OUT_RATEx registers.

A complete description of audio routing is included in the

Audio Signal Routing section.

Asynchronous Sample Rate Converter Group Delay

ASRC ratio (ASRC 7,

The group delay of the sample rate converter is dependent on

the input and output sampling frequencies as described in the

following equations:

Channel 14 and Channel 15)

0xF590

0xF591

0xF592

0xF593

0xF594

0xF595

0xF596

0xF597

0xF598

ASRC_RAMPMAX_OVR Master gain for all ASRCs

ASRC0_RAMPMAX

ASRC2_RAMPMAX

ASRC3_RAMPMAX

ASRC4_RAMPMAX

ASRC5_RAMPMAX

ASRC6_RAMPMAX

ASRC7_RAMPMAX

Gain for ASRC0

Gain for ASRC1

Gain for ASRC2

Gain for ASRC3

Gain for ASRC4

Gain for ASRC5

Gain for ASRC6

Gain for ASRC7

For output frequency (f_{S_OUT}) > input frequency (f_{S_IN}),

16

32

GDS =

+

f_{S _ IN}f_{S _ IN}

For f_{S_OUT}< f_{S_IN}

,







 







f_{S _ IN}

16

f_{S _ IN}

32

f_{S _ IN}

 

×

GDS =

+

 

f_{S _ OUT}

 

where GDS is the group delay in seconds.

ASRC Lock

Each ASRC monitors the incoming signal and attempts to lock

onto the clock and data signals. When a valid signal is detected

and several consecutive valid samples are received, and there is

a valid output target sample rate, the corresponding bit in

Register 0xF580 (ASRC_LOCK) signifies that the ASRC

locked to the incoming signal.

Rev. A | Page 63 of 207

ADAU1463/ADAU1467

Data Sheet

Asynchronous Sample Rate Converter Input Routing

When the outputs of the ASRCs are required for processing in

the SigmaDSP core, the ASRC input block must be selected in

SigmaStudio (see Figure 57 and Figure 58).

Any asynchronous input can be routed to the ASRCs to be

resynchronized to a desired target sample rate (see Figure 55).

The source signals for any ASRC can come from any of the

serial inputs, any of the DSP to ASRC channels, the S/PDIF

receiver, or the digital PDM microphone inputs. There are eight

ASRCs, each with two input channels and two output channels.

This means a total of 16 channels can pass through the ASRCs.

Asynchronous input signals (either serial inputs, PDM microphone

inputs, or the S/PDIF input) typically need to be routed to an ASRC

and then synchronized to the DSP core rate. They are then available

for input to the DSP core for processing.

DSP CORE

Figure 57. Location of ASRC to DSP Input Cell in SigmaStudio Toolbox

ASRCs

ASRC OUT 0

INPUT 0 TO INPUT 15

16 CH

ASRC0

INPUT 16 TO INPUT 31

16 CH

8 CH

ASRC OUTPUTS

(16 CHANNELS)

ASRC OUT 1

ASRC OUT 2

INPUT 32 TO INPUT 39

INPUT 40 TO INPUT 47

(×8)

ASRC1

16 CH

(2 CH × 8 ASRCS)

ASRC OUT3

ASRC OUT4

PDM MICROPHONE

INPUTS

4 CH

2 CH

ADAU1463/

ADAU1467

ASRC2

S/PDIF RECEIVER

ASRC OUT 5

ASRC OUT 6

ASRC3

Figure 55. Channel Routing to ASRC Inputs

ASRC OUT 7

ASRC OUT 8

In the example shown in Figure 56, the two channels from the

S/PDIF receiver are routed to one of the ASRCs and then to the

DSP core. For this example, the corresponding ASRC input selector

register (Register 0xF100 to Register 0xF107, ASRC_INPUTx),

Bits[2:0] (ASRC_SOURCE) is set to 0b011 to take the accept from

the S/PDIF receiver. Likewise, the corresponding ASRC output rate

selector register (Register 0xF140 to Register 0xF147, ASRC_OUT_

RATEx, Bits[3:0] (ASRC_RATE)) is set to 0b0101 to synchronize

the ASRC output data to the DSP core sample rate.

ASRC4

ASRC OUT 9

ASRC OUT 10

ASRC5

ASRC OUT 11

ASRC OUT 12

ASRC6

ASRC OUT 13

ASRC OUT 14

ASRC7

ASRC OUT 15

Figure 58. Routing of ASRC Outputs to ASRC to DSP Input Cell in SigmaStudio

DSP CORE

Asynchronous output signals (for example, serial outputs that

are slaves to an external, asynchronous device) typically are routed

from the DSP core into the ASRCs, where they are synchronized

to the serial output port that is acting as a slave to the external

asynchronous master device.

ASRCs

(×8)

2 CH

S/PDIF RECEIVER

Figure 56. Example ASRC Routing for Asynchronous Input to the DSP Core

Rev. A | Page 64 of 207

Data Sheet

ADAU1463/ADAU1467

In the example shown in Figure 59, two (or more) audio channels

from the DSP core are routed to one (or more) of the ASRCs

and then to the serial outputs. For this example, the corresponding

ASRC input selector register (Address 0xF100 to Address 0xF107

(ASRC_INPUTx), Bits[2:0] (ASRC_SOURCE)) is set to 0b010 to

receive the data from the DSP core, and the corresponding ASRC

output rate selector register (Address 0xF140 to Address 0xF147

(ASRC_OUT_RATEx), Bits[3:0] (ASRC_RATE)) is set to one of

the following:

•

0b0001 to synchronize the ASRC output data to SDATA_OUT0

0b0010 to synchronize the ASRC output data to SDATA_OUT1

0b0011 to synchronize the ASRC output data to SDATA_OUT2

0b0100 to synchronize the ASRC output data to SDATA_OUT3

Next, the corresponding serial output port data source register

(Address 0xF180 to Address 0xF197 (SOUT_SOURCEx), Bits[2:0]

(SOUT_SOURCE)) must be set to 0b011 to receive the data

from the ASRC outputs, and Bits[5:3] (SOUT_ASRC_SELECT)

must be configured to select the correct ASRC from which to

receive the output data.

Figure 61. Routing of DSP to ASRC Output Cells in SigmaStudio to

ASRC Inputs

The ASRCs can also be used to receive asynchronous inputs and

convert them to a different sample rate without performing any

processing in the DSP core.

DSP CORE

ASRCs

INPUT 0 TO INPUT 15

16 CH

ASRCs

ASRC OUTPUTS

(16 CHANNELS)

(×8)

16 CH

(2 CH × 8 ASRCs)

(×8)

ASRC OUTPUTS

(16 CHANNELS)

Figure 62. Example ASRC Routing, Bypassing DSP Core

16 CH

(2 CH × 8 ASRCS)

Configure the ASRC routing registers using a simple graphical

interface in the SigmaStudio software (see Figure 64).

Figure 59. Example ASRC Routing for Asynchronous Serial Output from

the DSP Core

Asynchronous Sample Rate Converter Output Routing

When signals must route from the DSP core to the ASRCs, use

the DSP to ASRC output cell in SigmaStudio (see Figure 60).

The outputs of the ASRCs are always available at both the DSP

core and the serial outputs. No manual routing is necessary. To

route ASRC output data to serial output channels, configure

Register 0xF180 to Register 0xF197 (SOUT_SOURCEx)

accordingly. For more information, see Figure 63 and Table 44.

DSP CORE

16 CH

ASRCs

ASRC OUTPUTS

(16 CHANNELS)

(×8)

16 CH

(2 CH × 8 ASRCs)

Figure 60. Location of DSP-to-ASRC Output Cell in SigmaStudio Toolbox

Figure 63. ASRC Outputs

Rev. A | Page 65 of 207

ADAU1463/ADAU1467

Data Sheet

Figure 64. Configuring the ASRC Input Source and Target Rate in SigmaStudio

Table 43. Relationship Between Data Pin, Audio Channels, Clock Pins, and TDM Options

Corresponding Clock Pins

in Master Mode

Maximum

TDM Channels

Flexible

TDM Mode

Serial Data Pin

SDATA_IN0

SDATA_IN1

SDATA_IN2

SDATA_IN3

SDATA_OUT0

SDATA_OUT1

SDATA_OUT2

SDATA_OUT3

Channel Numbering

Channel 0 to Channel 15

Channel 16 to Channel 31

Channel 32 to Channel 39

Channel 40 to Channel 47

Channel 0 to Channel 15

Channel 16 to Channel 31

Channel 32 to Channel 39

Channel 40 to Channel 47

BCLK_IN0, LRCLK_IN0

BCLK_IN1, LRCLK_IN1

BCLK_IN2, LRCLK_IN2

BCLK_IN3, LRCLK_IN3

BCLK_OUT0, LRCLK_OUT0

BCLK_OUT1, LRCLK_OUT1

BCLK_OUT2, LRCLK_OUT2

BCLK_OUT3, LRCLK_OUT3

16 channels

8 channels

16 channels

8 channels

No

Yes

No

Yes

Rev. A | Page 66 of 207

Data Sheet

ADAU1463/ADAU1467

data from a number of sources, including the DSP core, ASRCs,

PDM microphones, S/PDIF receiver, or directly from the serial

inputs.

AUDIO SIGNAL ROUTING

A large number of audio inputs and outputs are available in the

device, and control registers are available for configuring how

the audio is routed between different functional blocks.

See Figure 65 for an overview of the audio routing matrix with

its available audio data connections.

All input channels are accessible by both the DSP core and the

ASRCs. Each ASRC can connect to a pair of audio channels

from any of the input sources or from the DSP to ASRC

channels of the DSP core. The serial outputs can obtain their

To route audio to and from the DSP core, select the appropriate

input and output cells in SigmaStudio. These cells can be found

in the IO folder of the SigmaStudio algorithm toolbox.

DSP CORE

S/PDIF OUT

ADAU1463/ADAU1467

2 CH

DSP CORE

S/PDIF

INPUT 0 TO

SPDIFOUT

Tx

16 CH

8 CH

4 CH

SERIAL

INPUT

PORT 0

INPUT 15

SDATA_IN0

(2 CH TO 16 CH)

OUTPUT 0 TO

OUTPUT 15

16 CH

8 CH

INPUT 16 TO

INPUT 31

SERIAL

INPUT

PORT 1

SDATA_IN1

(2 CH TO 16 CH)

SERIAL

OUTPUT

PORT 0

SDATA_OUT0

(2 CH TO 16 CH)

INPUT 32 TO

INPUT 39

OUTPUT 16 TO

OUTPUT 31

SERIAL

INPUT

PORT 2

SDATA_IN2

(2 CH TO 8 CH)

SERIAL

OUTPUT

PORT 1

SDATA_OUT1

(2 CH TO 16 CH)

INPUT 40 TO

INPUT 47

SERIAL

INPUT

PORT 3

SDATA_IN3

(2 CH TO 8 CH)

OUTPUT 32 TO

OUTPUT 39

SERIAL

OUTPUT

PORT 2

SDATA_OUT2

(2 CH TO 8 CH)

MP6

MP7

PDM

MIC

INPUT

OUTPUT 40 TO

OUTPUT 47

8 CH

2 CH

SERIAL

OUTPUT

PORT 3

S/PDIF

Rx

SDATA_OUT3

(2 CH TO 8 CH)

SPDIFIN

ASRCs

(×8)

INPUT 0 TO INPUT 15

INPUT 16 TO INPUT 31

INPUT 32 TO INPUT 39

INPUT 40 TO INPUT 47

16 CH

8 CH

ASRC OUTPUTS

(16 CHANNELS)

16 CH

(2 CH × 8 ASRCS)

PDM MICROPHONE

INPUTS

4 CH

2 CH

S/PDIF RECEIVER

Figure 65. Audio Routing Overview

Rev. A | Page 67 of 207

ADAU1463/ADAU1467

Data Sheet

The data that is output from each serial output pin is also

configurable, via the SOUT_SOURCEx registers, to originate

from one of the following sources: the DSP, the serial inputs, the

PDM microphone inputs, the S/PDIF receiver, or the ASRCs.

These registers can be configured graphically in SigmaStudio, as

shown in Figure 66.

S/PDIF Audio Outputs from DSP Core to S/PDIF Transmitter

The output signal of the S/PDIF transmitter can come from the

DSP core or directly from the S/PDIF receiver. The selection is

controlled by Register 0xF1C0 (SPDIFTX_INPUT).

When the signal comes from the DSP core, use the S/PDIF

output cells in SigmaStudio.

SERIAL OUTPUT PORT 0

Audio Signal Routing Registers

SOUT_SOURCE0

SOUT_SOURCE1

SOUT_SOURCE2

SOUT_SOURCE3

SOUT_SOURCE4

SOUT_SOURCE5

SOUT_SOURCE6

SOUT_SOURCE7

An overview of the registers related to audio routing is listed in

Table 44. For more detailed information, see the Audio Signal

Routing section.

SDATA_OUT0

Figure 66. Configuring the Serial Output Data Channels (SOUT_SOURCEx

Registers) Graphically in SigmaStudio

Table 44. Audio Routing Matrix Registers

Address

0xF100

0xF101

0xF102

0xF103

0xF104

0xF105

0xF106

0xF107

0xF140

0xF141

0xF142

0xF143

0xF144

0xF145

0xF146

0xF147

0xF180

0xF181

0xF182

0xF183

0xF184

0xF185

0xF186

0xF187

0xF188

0xF189

0xF18A

0xF18B

0xF18C

0xF18D

Register

Description

ASRC_INPUT0

ASRC_INPUT1

ASRC_INPUT2

ASRC_INPUT3

ASRC_INPUT4

ASRC_INPUT5

ASRC_INPUT6

ASRC_INPUT7

ASRC input selector (ASRC 0, Channel 0 and Channel 1)

ASRC input selector (ASRC 1, Channel 2 and Channel 3)

ASRC input selector (ASRC 2, Channel 4 and Channel 5)

ASRC input selector (ASRC 3, Channel 6 and Channel 7)

ASRC input selector (ASRC 4, Channel 8 and Channel 9)

ASRC input selector (ASRC 5, Channel 10 and Channel 11)

ASRC input selector (ASRC 6, Channel 12 and Channel 13)

ASRC input selector (ASRC 7, Channel 14 and Channel 15)

ASRC output rate (ASRC 0, Channel 0 and Channel 1)

ASRC output rate (ASRC 1, Channel 2 and Channel 3)

ASRC output rate (ASRC 2, Channel 4 and Channel 5)

ASRC output rate (ASRC 3, Channel 6 and Channel 7)

ASRC output rate (ASRC 4, Channel 8 and Channel 9)

ASRC output rate (ASRC 5, Channel 10 and Channel 11)

ASRC output rate (ASRC 6, Channel 12 and Channel 13)

ASRC output rate (ASRC 7, Channel 14 and Channel 15)

Source of data for serial output port (Channel 0 and Channel 1)

Source of data for serial output port (Channel 2 and Channel 3)

Source of data for serial output port (Channel 4 and Channel 5)

Source of data for serial output port (Channel 6 and Channel 7)

Source of data for serial output port (Channel 8 and Channel 9)

Source of data for serial output port (Channel 10 and Channel 11)

Source of data for serial output port (Channel 12 and Channel 13)

Source of data for serial output port (Channel 14 and Channel 15)

Source of data for serial output port (Channel 16 and Channel 17)

Source of data for serial output port (Channel 18 and Channel 19)

Source of data for serial output port (Channel 20 and Channel 21)

Source of data for serial output port (Channel 22 and Channel 23)

Source of data for serial output port (Channel 24 and Channel 25)

Source of data for serial output port (Channel 26 and Channel 27)

ASRC_OUT_RATE0

ASRC_OUT_RATE1

ASRC_OUT_RATE2

ASRC_OUT_RATE3

ASRC_OUT_RATE4

ASRC_OUT_RATE5

ASRC_OUT_RATE6

ASRC_OUT_RATE7

SOUT_SOURCE0

SOUT_SOURCE1

SOUT_SOURCE2

SOUT_SOURCE3

SOUT_SOURCE4

SOUT_SOURCE5

SOUT_SOURCE6

SOUT_SOURCE7

SOUT_SOURCE8

SOUT_SOURCE9

SOUT_SOURCE10

SOUT_SOURCE11

SOUT_SOURCE12

SOUT_SOURCE13

Rev. A | Page 68 of 207

Data Sheet

ADAU1463/ADAU1467

Address

0xF18E

0xF18F

0xF190

0xF191

0xF192

0xF193

0xF194

0xF195

0xF196

0xF197

0xF1C0

Register

Description

SOUT_SOURCE14

SOUT_SOURCE15

SOUT_SOURCE16

SOUT_SOURCE17

SOUT_SOURCE18

SOUT_SOURCE19

SOUT_SOURCE20

SOUT_SOURCE21

SOUT_SOURCE22

SOUT_SOURCE23

SPDIFTX_INPUT

Source of data for serial output port (Channel 28 and Channel 29)

Source of data for serial output port (Channel 30 and Channel 31)

Source of data for serial output port (Channel 32 and Channel 33)

Source of data for serial output port (Channel 34 and Channel 35)

Source of data for serial output port (Channel 36 and Channel 37)

Source of data for serial output port (Channel 38 and Channel 39)

Source of data for serial output port (Channel 40 and Channel 41)

Source of data for serial output port (Channel 42 and Channel 43)

Source of data for serial output port (Channel 44 and Channel 45)

Source of data for serial output port (Channel 46 and Channel 47)

S/PDIF transmitter data selector

A total of 64 control registers (FTDM_INx) can be configured

FLEXIBLE TDM INTERFACE

to set up the mapping of input data bytes to the corresponding

bytes in the serial input channels. Each byte in each serial input

channel has a corresponding control register that selects the

incoming data byte on the serial input pins that must be mapped to

it. Figure 67 shows, from left to right, the data streams entering

the serial input pins, the serial input channels, and the registers

(see FTDM_INx, Register 0xF300 to Register 0xF33F) that

correspond to each byte in the serial input channels.

The flexible TDM interface is available as an optional mode of

operation on the SDATA_IN2 and SDATA_IN3 serial input ports,

as well as on the SDATA_OUT2 and SDATA_OUT3 serial output

ports. To use flexible TDM mode, the corresponding serial ports

must be set in flexible TDM mode (SERIAL_BYTE_x_0 register,

Bits[6:5] (WORD_LEN) = 0b11 and SERIAL_BYTE_x_0 register,

Bits[2:0] = 0b010). Flexible TDM input mode requires that both

SDATA_IN2 and SDATA_IN3 be configured for flexible TDM

mode. Likewise, flexible TDM output mode requires that both

SDATA_OUT2 and SDATA_OUT3 pins be configured for

flexible TDM mode.

Flexible TDM Output

In flexible TDM output mode, two 256-bit data streams are output

from the SDATA_OUT2 and SDATA_OUT3 pins. These 256 bits

of data compose eight channels of four bytes each, for a total of

32 bytes on each pin, and a total of 64 bytes when both input

pins are combined. The flexible TDM output functional block

routes the desired byte from the desired serial output channel to

a given byte in the output streams. The serial output channels

originate from the audio routing matrix, which is configured

using the SOUT_SOURCEx control registers.

The flexible TDM interface provides byte addressable data place-

ment in the input and output data streams on the corresponding

serial data input/output pins. Each data stream is configured

like a standard 8-channel TDM interface, with a total of 256 data

bits (or 32 bytes) in the span of an audio frame. Because flexible

TDM mode runs on two pins simultaneously, and each pin has

32 bytes of data, this means that there are a total of 64 data bytes. In

flexible TDM input mode, each input channel inside the device can

select its source data from any of the 64 input data bytes. In flexible

TDM output mode, any serial output channel can be routed to any

of the 64 output data bytes.

There are a total of 64 control registers (see FTDM_OUTx,

Register 0xF380 to Register 0xF3BF) that can be configured

to set up the mapping of the bytes in the serial output channels

and the bytes in the data streams exiting the serial output pins.

Each byte in the data streams being output from the serial output

pins has a corresponding control register, which selects the

desired byte from the desired serial output channel. Figure 68

shows, from left to right, the serial output channels originating

from the routing matrix, the serial output pins and data streams,

and the control registers (FTDM_OUTx) that correspond to

each byte in the serial output data streams.

Flexible TDM Input

In flexible TDM input mode, two 256-bit data streams are input

to the SDATA_IN2 and SDATA_IN3 pins. These 256 bits of data

compose eight channels of four bytes each, for a total of 32 bytes

on each pin, and a total of 64 bytes when both input pins are

combined. The flexible TDM input functional block routes the

desired input byte to a given byte in the serial input channels.

Those serial input channels are then available as normal audio

data in the audio routing matrix. The data can be passed to the

DSP core, the ASRC inputs, or the serial outputs as needed.

Rev. A | Page 69 of 207

ADAU1463/ADAU1467

Data Sheet

0 6 9

1

K

L O B C M T D L E I B X F L E

Figure 67. Flexible TDM Input Mapping

Rev. A | Page 70 of 207

Data Sheet

ADAU1463/ADAU1467

0 7 0

1

1 3 T U O _ M D F T

0 3 T U O _ M D F T

9 2 T U O _ M D F T

8 2 T U O _ M D F T

7 2 T U O _ M D F T

6 2 T U O _ M D F T

5 2 T U O _ M D F T

4 2 T U O _ M D F T

3 2 T U O _ M D F T

2 2 T U O _ M D F T

1 2 T U O _ M D F T

0 2 T U O _ M D F T

9 1 T U O _ M D F T

8 1 T U O _ M D F T

7 1 T U O _ M D F T

6 1 T U O _ M D F T

5 1 T U O _ M D F T

4 1 T U O _ M D F T

3 1 T U O _ M D F T

2 1 T U O _ M D F T

1 1 T U O _ M D F T

0 1 T U O _ M D F T

9 T U O _ M D F T

8 T U O _ M D F T

7 T U O _ M D F T

6 T U O _ M D F T

5 T U O _ M D F T

4 T U O _ M D F T

3 T U O _ M D F T

2 T U O _ M D F T

1 T U O _ M D F T

0 T U O _ M D F T

3 6 T U O _ M D F T

2 6 T U O _ M D F T

1 6 T U O _ M D F T

0 6 T U O _ M D F T

9 5 T U O _ M D F T

8 5 T U O _ M D F T

7 5 T U O _ M D F T

6 5 T U O _ M D F T

5 5 T U O _ M D F T

4 5 T U O _ M D F T

3 5 T U O _ M D F T

2 5 T U O _ M D F T

1 5 T U O _ M D F T

0 5 T U O _ M D F T

9 4 T U O _ M D F T

8 4 T U O _ M D F T

7 4 T U O _ M D F T

6 4 T U O _ M D F T

5 4 T U O _ M D F T

4 4 T U O _ M D F T

3 4 T U O _ M D F T

2 4 T U O _ M D F T

1 4 T U O _ M D F T

0 4 T U O _ M D F T

9 3 T U O _ M D F T

8 3 T U O _ M D F T

7 3 T U O _ M D F T

6 3 T U O _ M D F T

5 3 T U O _ M D F T

4 3 T U O _ M D F T

3 3 T U O _ M D F T

2 3 T U O _ M D F T

K

L O B C M T D L E I B X F L E

Figure 68. Flexible TDM Output Mapping

Rev. A | Page 71 of 207

ADAU1463/ADAU1467

Data Sheet

Flexible TDM Registers

An overview of the registers related to the flexible TDM interface is shown in Table 45. For a more detailed description, see the Flexible

TDM Interface Registers section.

Table 45. Flexible TDM Registers

Address

0xF300

0xF301

0xF302

0xF303

0xF304

0xF305

0xF306

0xF307

0xF308

0xF309

0xF30A

0xF30B

0xF30C

0xF30D

0xF30E

0xF30F

0xF310

0xF311

0xF312

0xF313

0xF314

0xF315

0xF316

0xF317

0xF318

0xF319

0xF31A

0xF31B

0xF31C

0xF31D

0xF31E

0xF31F

0xF320

0xF321

0xF322

0xF323

0xF324

0xF325

0xF326

0xF327

0xF328

0xF329

0xF32A

0xF32B

0xF32C

0xF32D

0xF32E

0xF32F

Register

Description

FTDM_IN0

FTDM_IN1

FTDM_IN2

FTDM_IN3

FTDM_IN4

FTDM_IN5

FTDM_IN6

FTDM_IN7

FTDM_IN8

FTDM_IN9

FTDM_IN10

FTDM_IN11

FTDM_IN12

FTDM_IN13

FTDM_IN14

FTDM_IN15

FTDM_IN16

FTDM_IN17

FTDM_IN18

FTDM_IN19

FTDM_IN20

FTDM_IN21

FTDM_IN22

FTDM_IN23

FTDM_IN24

FTDM_IN25

FTDM_IN26

FTDM_IN27

FTDM_IN28

FTDM_IN29

FTDM_IN30

FTDM_IN31

FTDM_IN32

FTDM_IN33

FTDM_IN34

FTDM_IN35

FTDM_IN36

FTDM_IN37

FTDM_IN38

FTDM_IN39

FTDM_IN40

FTDM_IN41

FTDM_IN42

FTDM_IN43

FTDM_IN44

FTDM_IN45

FTDM_IN46

FTDM_IN47

FTDM mapping for the serial inputs (Channel 32, Bits[31:24])

FTDM mapping for the serial inputs (Channel 32, Bits[23:16])

FTDM mapping for the serial inputs (Channel 32, Bits[15:8])

FTDM mapping for the serial inputs (Channel 32, Bits[7:0])

FTDM mapping for the serial inputs (Channel 33, Bits[31:24])

FTDM mapping for the serial inputs (Channel 33, Bits[23:16])

FTDM mapping for the serial inputs (Channel 33, Bits[15:8])

FTDM mapping for the serial inputs Channel 33, Bits[7:0])

FTDM mapping for the serial inputs (Channel 34, Bits[31:24])

FTDM mapping for the serial inputs (Channel 34, Bits[23:16])

FTDM mapping for the serial inputs (Channel 34, Bits[15:8])

FTDM mapping for the serial inputs (Channel 34, Bits[7:0])

FTDM mapping for the serial inputs (Channel 35, Bits[31:24])

FTDM mapping for the serial inputs (Channel 35, Bits[23:16])

FTDM mapping for the serial inputs (Channel 35, Bits[15:8])

FTDM mapping for the serial inputs (Channel 35, Bits[7:0])

FTDM mapping for the serial inputs (Channel 36, Bits[31:24])

FTDM mapping for the serial inputs (Channel 36, Bits[23:16])

FTDM mapping for the serial inputs (Channel 36, Bits[15:8])

FTDM mapping for the serial inputs (Channel 36, Bits[7:0])

FTDM mapping for the serial inputs (Channel 37, Bits[31:24])

FTDM mapping for the serial inputs (Channel 37, Bits[23:16])

FTDM mapping for the serial inputs (Channel 37, Bits[15:8])

FTDM mapping for the serial inputs (Channel 37, Bits[7:0])

FTDM mapping for the serial inputs (Channel 38, Bits[31:24])

FTDM mapping for the serial inputs (Channel 38, Bits[23:16])

FTDM mapping for the serial inputs (Channel 38, Bits[15:8])

FTDM mapping for the serial inputs (Channel 38, Bits[7:0])

FTDM mapping for the serial inputs (Channel 39, Bits[31:24])

FTDM mapping for the serial inputs (Channel 39, Bits[23:16])

FTDM mapping for the serial inputs (Channel 39, Bits[15:8])

FTDM mapping for the serial inputs (Channel 39, Bits[7:0])

FTDM mapping for the serial inputs (Channel 40, Bits[31:24])

FTDM mapping for the serial inputs (Channel 40, Bits[23:16])

FTDM mapping for the serial inputs (Channel 40, Bits[15:8])

FTDM mapping for the serial inputs (Channel 40, Bits[7:0])

FTDM mapping for the serial inputs (Channel 41, Bits[31:24])

FTDM mapping for the serial inputs (Channel 41, Bits[23:16])

FTDM mapping for the serial inputs (Channel 41, Bits[15:8])

FTDM mapping for the serial inputs (Channel 41, Bits[7:0])

FTDM mapping for the serial inputs (Channel 42, Bits[31:24])

FTDM mapping for the serial inputs (Channel 42, Bits[23:16])

FTDM mapping for the serial inputs (Channel 42, Bits[15:8])

FTDM mapping for the serial inputs (Channel 42, Bits[7:0])

FTDM mapping for the serial inputs (Channel 43, Bits[31:24])

FTDM mapping for the serial inputs (Channel 43, Bits[23:16])

FTDM mapping for the serial inputs (Channel 43, Bits[15:8])

FTDM mapping for the serial inputs (Channel 43, Bits[7:0])

Rev. A | Page 72 of 207

Data Sheet

ADAU1463/ADAU1467

Address

0xF330

0xF331

0xF332

0xF333

0xF334

0xF335

0xF336

0xF337

0xF338

0xF339

0xF33A

0xF33B

0xF33C

0xF33D

0xF33E

0xF33F

0xF380

0xF381

0xF382

0xF383

0xF384

0xF385

0xF386

0xF387

0xF388

0xF389

0xF38A

0xF38B

0xF38C

0xF38D

0xF38E

0xF38F

0xF390

0xF391

0xF392

0xF393

0xF394

0xF395

0xF396

0xF397

0xF398

0xF399

0xF39A

0xF39B

0xF39C

0xF39D

0xF39E

0xF39F

0xF3A0

0xF3A1

0xF3A2

0xF3A3

0xF3A4

Register

Description

FTDM_IN48

FTDM_IN49

FTDM_IN50

FTDM_IN51

FTDM_IN52

FTDM_IN53

FTDM_IN54

FTDM_IN55

FTDM_IN56

FTDM_IN57

FTDM_IN58

FTDM_IN59

FTDM_IN60

FTDM_IN61

FTDM_IN62

FTDM_IN63

FTDM_OUT0

FTDM_OUT1

FTDM_OUT2

FTDM_OUT3

FTDM_OUT4

FTDM_OUT5

FTDM_OUT6

FTDM_OUT7

FTDM_OUT8

FTDM_OUT9

FTDM_OUT10

FTDM_OUT11

FTDM_OUT12

FTDM_OUT13

FTDM_OUT14

FTDM_OUT15

FTDM_OUT16

FTDM_OUT17

FTDM_OUT18

FTDM_OUT19

FTDM_OUT20

FTDM_OUT21

FTDM_OUT22

FTDM_OUT23

FTDM_OUT24

FTDM_OUT25

FTDM_OUT26

FTDM_OUT27

FTDM_OUT28

FTDM_OUT29

FTDM_OUT30

FTDM_OUT31

FTDM_OUT32

FTDM_OUT33

FTDM_OUT34

FTDM_OUT35

FTDM_OUT36

FTDM mapping for the serial inputs (Channel 44, Bits[31:24])

FTDM mapping for the serial inputs (Channel 44, Bits[23:16])

FTDM mapping for the serial inputs (Channel 44, Bits[15:8])

FTDM mapping for the serial inputs (Channel 44, Bits[7:0])

FTDM mapping for the serial inputs (Channel 45, Bits[31:24])

FTDM mapping for the serial inputs (Channel 45, Bits[23:16])

FTDM mapping for the serial inputs (Channel 45, Bits[15:8])

FTDM mapping for the serial inputs (Channel 45, Bits[7:0])

FTDM mapping for the serial inputs (Channel 46, Bits[31:24])

FTDM mapping for the serial inputs (Channel 46, Bits[23:16])

FTDM mapping for the serial inputs (Channel 46, Bits[15:8])

FTDM mapping for the serial inputs (Channel 46, Bits[7:0])

FTDM mapping for the serial inputs (Channel 47, Bits[31:24])

FTDM mapping for the serial inputs (Channel 47, Bits[23:16])

FTDM mapping for the serial inputs (Channel 47, Bits[15:8])

FTDM mapping for the serial inputs (Channel 47, Bits[7:0])

FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[31:24])

FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[23:16])

FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[15:8])

FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[7:0])

FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[31:24])

FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[23:16])

FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[15:8])

FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[7:0])

FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[31:24])

FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[23:16])

FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[15:8])

FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[7:0])

FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[31:24])

FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[23:16])

FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[15:8])

FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[7:0])

FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[31:24])

FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[23:16])

FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[15:8])

FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[7:0])

FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[31:24])

FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[23:16])

FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[15:8])

FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[7:0])

FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[31:24])

FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[23:16])

FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[15:8])

FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[7:0])

FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[31:24])

FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[23:16])

FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[15:8])

FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[7:0])

FTDM mapping for the serial outputs (Port 3, Channel 0, Bits[31:24])

FTDM mapping for the serial outputs (Port 3, Channel 0, Bits[23:16])

FTDM mapping for the serial outputs (Port 3, Channel 0, Bits[15:8])

FTDM mapping for the serial outputs (Port 3, Channel 0, Bits[7:0])

FTDM mapping for the serial outputs (Port 3, Channel 1, Bits[31:24])

Rev. A | Page 73 of 207

ADAU1463/ADAU1467

Data Sheet

Address

0xF3A5

0xF3A6

0xF3A7

0xF3A8

0xF3A9

0xF3AA

0xF3AB

0xF3AC

0xF3AD

0xF3AE

0xF3AF

0xF3B0

0xF3B1

0xF3B2

0xF3B3

0xF3B4

0xF3B5

0xF3B6

0xF3B7

0xF3B8

0xF3B9

0xF3BA

0xF3BB

0xF3BC

0xF3BD

0xF3BE

0xF3BF

Register

Description

FTDM_OUT37

FTDM_OUT38

FTDM_OUT39

FTDM_OUT40

FTDM_OUT41

FTDM_OUT42

FTDM_OUT43

FTDM_OUT44

FTDM_OUT45

FTDM_OUT46

FTDM_OUT47

FTDM_OUT48

FTDM_OUT49

FTDM_OUT50

FTDM_OUT51

FTDM_OUT52

FTDM_OUT53

FTDM_OUT54

FTDM_OUT55

FTDM_OUT56

FTDM_OUT57

FTDM_OUT58

FTDM_OUT59

FTDM_OUT60

FTDM_OUT61

FTDM_OUT62

FTDM_OUT63

FTDM mapping for the serial outputs (Port 3, Channel 1, Bits[23:16])

FTDM mapping for the serial outputs (Port 3, Channel 1, Bits[15:8])

FTDM mapping for the serial outputs (Port 3, Channel 1, Bits[7:0])

FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[31:24])

FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[23:16])

FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[15:8])

FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[7:0])

FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[31:24])

FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[23:16])

FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[15:8])

FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[7:0])

FTDM mapping for the serial outputs (Port 3, Channel 4, Bits[31:24])

FTDM mapping for the serial outputs (Port 3, Channel 4, Bits[23:16])

FTDM mapping for the serial outputs (Port 3, Channel 4, Bits[15:8])

FTDM mapping for the serial outputs (Port 3, Channel 4, Bits[7:0])

FTDM mapping for the serial outputs (Port 3, Channel 5, Bits[31:24])

FTDM mapping for the serial outputs (Port 3, Channel 5, Bits[23:16])

FTDM mapping for the serial outputs (Port 3, Channel 5, Bits[15:8])

FTDM mapping for the serial outputs (Port 3, Channel 5, Bits[7:0])

FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[31:24])

FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[23:16])

FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[15:8])

FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[7:0])

FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[31:24])

FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[23:16])

FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[15:8])

FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[7:0])

set in the SPDIF_TX_MCLKSPEED register for receive and

transmit rates greater than 96 kHz, respectively.

S/PDIF INTERFACE

To simplify interfacing at the system level, wire the on-chip S/PDIF

receiver and transmitter data ports directly to other S/PDIF-

compatible equipment. The S/PDIF receiver consists of two

audio channels input on one hardware pin (SPDIFIN). The

clock signal is embedded in the data using biphase mark code.

The S/PDIF transmitter consists of two audio channels output

on one hardware pin (SPDIFOUT). The clock signal is embedded

in the data using biphase mark code. The S/PDIF input and output

word lengths can be independently set to 16, 20, or 24 bits.

The S/PDIF receiver input is a comparator that is centered at

IOVDD/2 and requires an input signal level of at least 200 mV p-p

to operate properly.

In addition to audio data, S/PDIF streams contain user data,

channel status, validity bit, virtual LRCLK, and block start

information. The receiver decodes audio data and sends it to

the corresponding registers in the control register map, where

the information can be read over the I²C or SPI slave port.

The S/PDIF interface meets the S/PDIF consumer performance

specification. It does not meet the AES3 professional specification.

For improved jitter performance, the S/PDIF clock recovery

implementation is completely digital. The S/PDIF ports are

designed to meet the following Audio Engineering Society

(AES) and European Broadcasting Union (EBU) specifications:

a jitter of 0.25 UI p-p at 8 kHz and above, a jitter of 10 UI p-p

below 200 Hz, and a minimum signal voltage of 200 mV.

S/PDIF Receiver

The S/PDIF input port is designed to accept both transistor to

transistor logic (TTL) and bipolar signals, provided there is an ac

coupling capacitor on the input pin of the chip. Because the S/PDIF

input data is most likely asynchronous to the DSP core, it must be

routed through an ASRC.

S/PDIF Transmitter

The S/PDIF transmitter outputs two channels of audio data directly

from the DSP core at the core rate. The extra nonaudio data bits

on the transmitted signal can be copied directly from the S/PDIF

receiver or programmed manually, using the corresponding

registers in the control register map.

The S/PDIF receiver works over a wide range of sampling

frequencies between 18 kHz and 192 kHz. Note that the

RX_MCLKSPEED bit must be set in the SPDIF_RX_

MCLKSPEED register and the TX_MCLKSPEED bit must be

Rev. A | Page 74 of 207

Data Sheet

ADAU1463/ADAU1467

Auxiliary Output Mode

S/PDIF Receiver Inputs to DSP Core

The received data on the S/PDIF receiver can be converted

to a TDM8 stream, bypass the SigmaDSP core, and be output

directly on a serial data output pin. This mode of operation

is called auxiliary output mode. Configure this mode using

Register 0xF608 (SPDIF_AUX_EN). The TDM8 output from

the S/PDIF receiver regroups the recovered data in a TDM like

format, as shown in Table 46.

The S/PDIF receiver input must pass through an ASRC to

guarantee that it is synchronous to the DSP core. The two

channels from the S/PDIF receiver can be selected as the audio

source to ASRCs in the routing matrix. When the source is the

S/PDIF receiver, the serial input channel that is specified is

ignored.

Table 47. S/PDIF Input Mapping to SigmaStudio Channels

The S/PDIF receiver, when operating in auxiliary output mode,

also recovers the embedded BCLK_OUTx and LRCLK_OUTx

signals in the S/PDIF stream and outputs them on the

corresponding BCLK_OUTx and LRCLK_OUTx pins in master

mode when Register 0xF608 (SPDIF_AUX_EN), Bits[3:0]

(TDMOUT) are configured to enable auxiliary output mode.

The selected BCLK_OUTx signal has a frequency of 256× the

recovered sample rate, and the LRCLK_OUTx signal is a 50%

duty cycle square wave that has the same frequency as the audio

sample rate (see Table 144).

Channel in S/PDIF Receiver

Data Stream

S/PDIF Input Channels in

SigmaStudio

Left

Right

0

1

S/PDIF Audio Outputs from DSP Core to S/PDIF Transmitter

The output signal of the S/PDIF transmitter can come from the

DSP core or directly from the S/PDIF receiver. The selection is

controlled by Register 0xF1C0 (SPDIFTX_INPUT). When the

signal comes from the DSP core, use the S/PDIF output cells in

SigmaStudio.

Table 46. S/PDIF Auxiliary Output Mode, TDM8 Data Format

TDM8

DSP S/PDIF OUT 0

Channel

Description of Data Format

DSP S/PDIF OUT 1

S/PDIF Tx 0

0

8 zero bits followed by 24 audio bits, recovered

from the left audio channel of the S/PDIF stream

28 zero bits followed by the left parity bit, left

validity bit, left user data, and left channel status

30 zero bits followed by the compression type bit

(COMPR_TYPE) (0b0 = AC3, 0b1 = DTS) and the audio

type bit (AUDIO_TYPE) (0 = PCM, 1 = compressed)

S/PDIF

SPDIFOUT

S/PDIF Tx 1

Tx

S/PDIF Rx 0

S/PDIF Rx 1

1

2

Figure 69. S/PDIF Transmitter Source Selection

Table 48. S/PDIF Output Mapping from SigmaStudio Channels

Channel in S/PDIF Transmitter S/PDIF Output Channel in

Data Stream

3

4

No data

SigmaStudio

8 zero bits followed by 24 audio bits, recovered

from the right audio channel of the S/PDIF stream

28 zero bits followed by the right parity bit, right

validity bit, right user data, and right channel status

Left

Right

0

1

5

S/PDIF Interface Registers

6

7

No data

An overview of the registers related to the S/PDIF interface is

shown in Table 49. For a more detailed description, refer to the

S/PDIF Interface Registers section.

31 zero bits followed by the block start signal

Rev. A | Page 75 of 207

ADAU1463/ADAU1467

Data Sheet

Table 49. S/PDIF Interface Registers

Address

Register

Description

0xF600

SPDIF_LOCK_DET

S/PDIF receiver lock bit detection

0xF601

SPDIF_RX_CTRL

S/PDIF receiver control

0xF602

0xF603

0xF604

0xF605

0xF606

0xF607

0xF608

0xF60F

0xF610 to 0xF61B

0xF620 to 0xF62B

0xF630 to 0xF63B

0xF640 to 0xF64B

0xF650 to 0xF65B

0xF660 to 0xF66B

0xF670 to 0xF67B

0xF680 to 0xF68B

0xF690

SPDIF_RX_DECODE

SPDIF_RX_COMPRMODE

SPDIF_RESTART

SPDIF_LOSS_OF_LOCK

SPDIF_RX_MCLKSPEED

SPDIF_TX_MCLKSPEED

SPDIF_AUX_EN

SPDIF_RX_AUXBIT_READY

SPDIF_RX_CS_LEFT_x

SPDIF_RX_CS_RIGHT_x

SPDIF_RX_UD_LEFT_x

SPDIF_RX_UD_RIGHT_x

SPDIF_RX_VB_LEFT_x

SPDIF_RX_VB_RIGHT_x

SPDIF_RX_PB_LEFT_x

SPDIF_RX_PB_RIGHT_x

SPDIF_TX_EN

Decoded signals from the S/PDIF receiver

Compression mode from the S/PDIF receiver

Automatically resume S/PDIF receiver audio input

S/PDIF receiver loss of lock detection

Enables the receiver to operate between 96 kHz and 192 kHz

Enables the transmitter to operate between 96 kHz and 192 kHz

S/PDIF receiver auxiliary outputs enable

S/PDIF receiver auxiliary bits ready flag

S/PDIF receiver channel status bits (left)

S/PDIF receiver channel status bits (right)

S/PDIF receiver user data bits (left)

S/PDIF receiver user data bits (right)

S/PDIF receiver validity bits (left)

S/PDIF receiver validity bits (right)

S/PDIF receiver parity bits (left)

S/PDIF receiver parity bits (right)

S/PDIF transmitter enable

0xF691

SPDIF_TX_CTRL

S/PDIF transmitter control

0xF69F

SPDIF_TX_AUXBIT_SOURCE

SPDIF_TX_CS_LEFT_x

SPDIF_TX_CS_RIGHT_x

SPDIF_TX_UD_LEFT_x

SPDIF_TX_UD_RIGHT_x

SPDIF_TX_VB_LEFT_x

SPDIF_TX_VB_RIGHT_x

SPDIF_TX_PB_LEFT_x

SPDIF_TX_PB_RIGHT_x

S/PDIF transmitter auxiliary bits source select

S/PDIF transmitter channel status bits (left)

S/PDIF transmitter channel status bits (right)

S/PDIF transmitter user data bits (left)

S/PDIF transmitter user data bits (right)

S/PDIF transmitter validity bits (left)

S/PDIF transmitter validity bits (right)

S/PDIF transmitter parity bits (left)

0xF6A0 to 0xF6AB

0xF6B0 to 0xF6BB

0xF6C0 to 0xF6CB

0xF6D0 to 0xF6DB

0xF6E0 to 0xF6EB

0xF6F0 to 0xF6FB

0xF700 to 0xF70B

0xF710 to 0xF71B

S/PDIF transmitter parity bits (right)

Rev. A | Page 76 of 207

Data Sheet

ADAU1463/ADAU1467

Digital PDM Microphone Interface Registers

DIGITAL PDM MICROPHONE INTERFACE

An overview of the registers related to the digital microphone

interface is shown in Table 51. For a more detailed description,

see the Digital PDM Microphone Interface Registers section.

Up to four PDM microphones can be connected as audio

inputs. Each pair of microphones can share a single data line;

therefore, using four PDM microphones requires two GPIO

pins. Any multipurpose pin can be used as a microphone data

input, with up to two microphones connected to each pin. This

configuration is set up using the corresponding MPx_MODE

and DMIC_CTRLx registers.

PDM Microphone Inputs to DSP Core

The PDM microphone inputs are mapped to a single digital micro-

phone input cell in SigmaStudio. The corresponding hardware

pins are configured in Register 0xF560 (DMIC_CTRL0) and

Register 0xF561 (DMIC_CTRL1).

A bit clock pin from one of the serial input clock domains

(BCLK_INx) or one of the serial output clock domains (BCLK_

OUTx) must be a master clock source, and its output signal

must be connected to the PDM microphones to provide them

with a clock.

Table 50. PDM Microphone Input Mapping to SigmaStudio

Channels

PDM Microphone Input Channel in

SigmaStudio

PDM Data Channel

Left (DMIC_CTRL0)

Right (DMIC_CTRL0)

Left (DMIC_CTRL1)

Right (DMIC_CTRL1)

PDM microphones, such as the ICS-41350 from InvenSense,

typically require a bit clock frequency in the range of 1 MHz to

3.3 MHz, corresponding to audio sample rates of 15.625 kHz

to 51.5625 kHz. This requirement means that the serial port

corresponding to the BCLK_INx pin or BCLK_OUTx pin driving

the PDM microphones must operate in 2-channel mode at a

sample rate between 16 kHz and 48 kHz.

0

1

2

3

4 CH

MP6

MP7

PDM

MIC

INPUT

PDM microphone inputs are automatically routed through

decimation filters and then are available for use at the DSP core,

the ASRCs, and the serial output ports.

Figure 71. PDM Microphone Input Mapping to DSP in SigmaStudio

Figure 70 shows an example circuit with two ICS-41350 PDM

output MEMS microphones connected to the ADAU1463/

ADAU1467. Use any of the BCLK_INx pins or BCLK_OUTx pins

to provide a clock signal to the microphones, and connect the

data output of the microphones to any MPx pin configured as a

PDM microphone data input.

DSP CORE

S/PDIF OUT

2 CH

S/PDIF

SPDIFOUT

Tx

FROM S/PDIF RECEIVER

1.8V TO 3.3V

Figure 72. DSP to S/PDIF Transmitter Output Mapping in SigmaStudio

Table 51. Digital PDM Microphone Interface Registers

IOVDD

Address Register

Description

CLK

ICS-41350

0xF560

DMIC_CTRL0 Digital PDM microphone control

(Channel 0 and Channel 1)

ADAU1463/

ADAU1467

0xF561

DMIC_CTRL1 Digital PDM microphone control

(Channel 2 and Channel 3)

V

DATA

GND

DD

0.1µF

L/R SELECT

BCLK_INx

OR

BCLK_OUTx

CLK

ICS-41350

MPx

GND

V

DATA

GND

DD

0.1µF

L/R SELECT

Figure 70. Example Stereo PDM Microphone Input Circuit

Rev. A | Page 77 of 207

ADAU1463/ADAU1467

Data Sheet

MULTIPURPOSE PINS

A total of 25 pins are available for use as GPIOs that are

multiplexed with other functions, such as clock inputs/outputs.

Because these pins have multiple functions, they are referred to as

multipurpose pins, or MPx pins.

Multipurpose pins can be configured in several modes using the

MPx_MODE registers:

•

Hardware input from pin

Software input (written via I²C or SPI slave control port)

Hardware output with internal pull-up resistor

Hardware output without internal pull-up resistor

PDM microphone data input

Flag output from panic manager

Slave select line for master SPI port

When configured in hardware input mode, a debounce circuit

is available to avoid data glitches.

Figure 73. General-Purpose Input in the SigmaStudio Toolbox

General-Purpose Outputs from the DSP Core

When operating in GPIO mode, the pin status is updated once

per sample, which means that the state of a GPIO (MPx pin)

cannot change more than once in a sample period.

When a multipurpose pin is configured as a general-purpose

output, a Boolean value is output from the DSP program to the

corresponding multipurpose pin. Figure 74 shows the location

of the general-purpose input cell within the SigmaStudio toolbox.

General-Purpose Inputs to the DSP Core

When a multipurpose pin is configured as a general-purpose

input, its value can be used as a control logic signal in the DSP

program, which is configured using SigmaStudio. Figure 73

shows the location of the general-purpose input cell within the

SigmaStudio toolbox.

The 26 available general-purpose inputs in SigmaStudio map

to the corresponding 26 multipurpose pins; however, their data

is valid only if the corresponding multipurpose pin is configured as

an input using the MPx_MODE registers. Figure 75 shows all of

the general-purpose inputs as they appear in the SigmaStudio

signal flow.

Figure 74. General-Purpose Output in the SigmaStudio Toolbox

Rev. A | Page 78 of 207

Data Sheet

ADAU1463/ADAU1467

Figure 75. Complete Set of General-Purpose Inputs in SigmaStudio

Rev. A | Page 79 of 207

ADAU1463/ADAU1467

Data Sheet

The 26 available general-purpose outputs in SigmaStudio map

to the corresponding 26 multipurpose pins; however, their data

is output to the pin only if the corresponding multipurpose pin

is configured as an output using the MPx_MODE registers.

Figure 76 shows all of the general-purpose inputs as they appear

in the SigmaStudio signal flow.

Multipurpose Pin Registers

An overview of the registers related to GPIO is shown in Table 52.

For a more detailed description, refer to the Multipurpose Pin

Configuration Registers section.

Figure 76. Complete Set of General-Purpose Outputs in SigmaStudio

Table 52. Multipurpose Pins Registers

Address

0xF510

0xF511

0xF512

0xF513

0xF514

0xF515

0xF516

0xF517

0xF518

0xF519

0xF51A

0xF51B

0xF51C

0xF51D

0xF5C0

0xF5C1

0xF5C2

0xF5C3

0xF5C4

Register

Description

MP0_MODE

MP1_MODE

MP2_MODE

MP3_MODE

MP4_MODE

MP5_MODE

MP6_MODE

MP7_MODE

MP8_MODE

MP9_MODE

MP10_MODE

MP11_MODE

MP12_MODE

MP13_MODE

MP14_MODE

MP15_MODE

MP16_MODE

MP17_MODE

MP18_MODE

Multipurpose pin mode (SS_M/MP0)

Multipurpose pin mode (MOSI_M/MP1)

Multipurpose pin mode (SCL_M/SCLK_M/MP2)

Multipurpose pin mode (SDA_M/MISO_M/MP3)

Multipurpose pin mode (LRCLK_OUT0/MP4)

Multipurpose pin mode (LRCLK_OUT1/MP5)

Multipurpose pin mode (MP6)

Multipurpose pin mode (MP7)

Multipurpose pin mode (LRCLK_OUT2/MP8)

Multipurpose pin mode (LRCLK_OUT3/MP9)

Multipurpose pin mode (LRCLK_IN0/MP10)

Multipurpose pin mode (LRCLK_IN1/MP11)

Multipurpose pin mode (LRCLK_IN2/MP12)

Multipurpose pin mode (LRCLK_IN3/MP13)

Multipurpose pin mode (MP14)

Multipurpose pin mode (MP15)

Multipurpose pin mode (SDATAIO0/MP16)

Multipurpose pin mode (SDATAIO1/MP17)

Multipurpose pin mode (SDATAIO2/MP18)

Rev. A | Page 80 of 207

Data Sheet

ADAU1463/ADAU1467

Address

0xF5C5

0xF5C6

0xF5C7

0xF5C8

0xF5C9

0xF5CA

0xF51D

0xF520

0xF521

0xF522

0xF523

0xF524

0xF525

0xF526

0xF527

0xF528

0xF529

0xF52A

0xF52B

0xF52C

0xF52D

0xF5D0

0xF5D1

0xF5D2

0xF5D3

0xF5D4

0xF5D5

0xF5D6

0xF5D7

0xF5D8

0xF5D9

0xF5DA

0xF52D

0xF530

0xF531

0xF532

0xF533

0xF534

0xF535

0xF536

0xF537

0xF538

0xF539

0xF53A

0xF53B

0xF53C

0xF53D

Register

Description

MP19_MODE

MP20_MODE

MP21_MODE

MP22_MODE

MP23_MODE

MP24_MODE

MP25_MODE

MP0_WRITE

MP1_WRITE

MP2_WRITE

MP3_WRITE

MP4_WRITE

MP5_WRITE

MP6_WRITE

MP7_WRITE

MP8_WRITE

MP9_WRITE

MP10_WRITE

MP11_WRITE

MP12_WRITE

MP13_WRITE

MP14_WRITE

MP15_WRITE

MP16_WRITE

MP17_WRITE

MP18_WRITE

MP19_WRITE

MP20_WRITE

MP21_WRITE

MP22_WRITE

MP23_WRITE

MP24_WRITE

MP25_WRITE

MP0_READ

Multipurpose pin mode (SDATAIO3/MP19)

Multipurpose pin mode (SDATAIO4/MP20)

Multipurpose pin mode (SDATAIO5/MP21)

Multipurpose pin mode (SDATAIO6/MP22)

Multipurpose pin mode (SDATAIO7/MP23)

Multipurpose pin mode (SCL2_M/MP24)

Multipurpose pin mode (SDA2_M/MP25)

Multipurpose pin write value (SS_M/MP0)

Multipurpose pin write value (MOSI_M/MP1)

Multipurpose pin write value (SCL_M/SCLK_M/MP2)

Multipurpose pin write value (SDA_M/MISO_M/MP3)

Multipurpose pin write value (LRCLK_OUT0/MP4)

Multipurpose pin write value (LRCLK_OUT1/MP5)

Multipurpose pin write value (MP6)

Multipurpose pin write value (MP7)

Multipurpose pin write value (LRCLK_OUT2/MP8)

Multipurpose pin write value (LRCLK_OUT3/MP9)

Multipurpose pin write value (LRCLK_IN0/MP10)

Multipurpose pin write value (LRCLK_IN1/MP11)

Multipurpose pin write value (LRCLK_IN2/MP12)

Multipurpose pin write value (LRCLK_IN3/MP13)

Multipurpose pin write value (MP14)

Multipurpose pin write value (MP15)

Multipurpose pin write value (SDATAIO0/MP16)

Multipurpose pin write value (SDATAIO1/MP17)

Multipurpose pin write value (SDATAIO2/MP18)

Multipurpose pin write value (SDATAIO3/MP19)

Multipurpose pin write value (SDATAIO4/MP20)

Multipurpose pin write value (SDATAIO5/MP21)

Multipurpose pin write value (SDATAIO6/MP22)

Multipurpose pin write value (SDATAIO7/MP23)

Multipurpose pin write value (SCL2_M/MP24)

Multipurpose pin write value (SDA2_M/MP25)

Multipurpose pin read value (SS_M/MP0)

Multipurpose pin read value (MOSI_M/MP1)

Multipurpose pin read value (SCL_M/SCLK_M/MP2)

Multipurpose pin read value (SDA_M/MISO_M/MP3)

Multipurpose pin read value (LRCLK_OUT0/MP4)

Multipurpose pin read value (LRCLK_OUT1/MP5)

Multipurpose pin read value (MP6)

MP1_READ

MP2_READ

MP3_READ

MP4_READ

MP5_READ

MP6_READ

MP7_READ

MP8_READ

Multipurpose pin read value (MP7)

Multipurpose pin read value (LRCLK_OUT2/MP8)

Multipurpose pin read value (LRCLK_OUT3/MP9)

Multipurpose pin read value (LRCLK_IN0/MP10)

Multipurpose pin read value (LRCLK_IN1/MP11)

Multipurpose pin read value (LRCLK_IN2/MP12)

Multipurpose pin read value (LRCLK_IN3/MP13)

MP9_READ

MP10_READ

MP11_READ

MP12_READ

MP13_READ

Rev. A | Page 81 of 207

ADAU1463/ADAU1467

Data Sheet

AUXILIARY ADC

The ADAU1463/ADAU1467 have eight auxiliary ADC inputs with

10 bits of accuracy. They are intended to be used as control signal

inputs, such as potentiometer outputs or battery monitor signals.

The auxiliary ADC samples each channel at a frequency of the

core system clock divided by 6144. In the case of a default clocking

scheme, the system clock is 294.912 MHz; therefore, the auxiliary

ADC sample rate is 48 kHz. If the system clock is scaled down

by configuring the PLL to generate a lower output frequency,

the auxiliary ADC sample rate is scaled down proportionately.

Figure 78. Complete Set of Auxiliary ADC Inputs in SigmaStudio

The auxiliary ADC is referenced so that a full-scale input is

achieved when the input voltage is equal to AVDD, and an input

of zero is achieved when the input is connected to ground.

Auxiliary ADC Registers

An overview of the registers related to the auxiliary ADC is

shown in Table 53. For a more detailed description, see the

Auxiliary ADC Registers section.

The input impedance of the auxiliary ADC is approximately

200 kΩ at dc (0 Hz).

Auxiliary ADC inputs can be used directly in the DSP program

(as configured in the SigmaStudio software). The instantaneous

value of each ADC is also available in the ADC_READx registers,

which are accessible via the I²C or SPI slave control port.

Table 53. Auxiliary ADC Registers

Address Register

Description

0xF5A0

0xF5A1

0xF5A2

0xF5A3

0xF5A4

0xF5A5

0xF5A6

0xF5A7

ADC_READ0

Auxiliary ADC read value (AUXADC0)

Auxiliary ADC read value (AUXADC1)

Auxiliary ADC read value (AUXADC2)

Auxiliary ADC read value (AUXADC3)

Auxiliary ADC read value (AUXADC4)

Auxiliary ADC read value (AUXADC5)

Auxiliary ADC read value (AUXADC6)

Auxiliary ADC read value (AUXADC7)

ADC_READ1

ADC_READ2

ADC_READ3

ADC_READ4

ADC_READ5

ADC_READ6

ADC_READ7

Auxiliary ADC Inputs to the DSP Core

Auxiliary ADC inputs can be used as control signals in the DSP

program as configured by SigmaStudio. Figure 77 shows the

location of the auxiliary ADC input cell in the SigmaStudio

toolbox.

SigmaDSP CORE

The SigmaDSP core operates at a maximum frequency of

294.912 MHz (or 147.456 MHz), which is equivalent to

6144 clock cycles per sample at a sample rate of 48 kHz. For

a sample rate of 48 kHz, the largest program possible consists of

6144 program instructions per sample (or 3072 clock cycles per

sample in the nominal 150 MHz speed grade). If the system

clock remains at 294.912 MHz but the audio frame rate of the DSP

core is decreased, programs consisting of more clock cycles per

sample are possible.

The core consists of four multipliers and two accumulators.

At an operating frequency of 294.912 MHz, the core performs

1.2 billion MAC operations per second. At maximum efficiency,

the core processes 3072 IIR biquad filters (single or double

precision) per sample at a sample rate of 48 kHz. At maximum

efficiency, the core processes approximately 24,000 FIR filter

taps per sample at a sample rate of 48 kHz. The instruction set is

an SIMD computing model. The DSP core is 32-bit fixed point,

with an 8.24 data format for audio.

Figure 77. Auxiliary ADC Input Cell in the SigmaStudio Toolbox

The eight auxiliary input pins map to the corresponding eight

auxiliary ADC input cells. Figure 78 shows the complete set of

auxiliary ADC input cells in SigmaStudio.

Rev. A | Page 82 of 207

Data Sheet

ADAU1463/ADAU1467

The four multipliers are 64-bit double precision, capable of

multiplying an 8.56 format number by an 8.24 number. The

multiply accumulators consist of 16 registers, with a depth of

80 bits. The core can access RAM with a load/store width of

256 bits (eight 32-bit words per frame). The two ALUs have an

80-bit width and operate on numbers in 24.56 format. The

24.56-bit format provides more than 42 dB of headroom.

Numeric Formats

DSP systems commonly use a standard numeric format.

Fractional number systems are specified by an A.B format,

where A is the number of bits to the left of the decimal point

and B is the number of bits to the right of the decimal point.

The same numeric format is used for both the parameter and

data values.

It is possible to create combinations of time domain and

frequency domain processing, using block and sample frame

interrupts. Sixteen data address generator (DAG) registers are

available, and circular buffer addressing is possible.

A digital clipper circuit is used within the DSP core before

outputting to the serial port outputs, ASRCs, and S/PDIF. This

circuit clips the top seven bits (and the least significant bit) of the

signal to produce a 24-bit output with a range of +1.0 (minus

1 LSB) to −1.0. Figure 79 shows the maximum signal levels at

each point in the data flow in both binary and decibel levels.

Many of the signal processing functions are coded using full,

64-bit, double precision arithmetic. The serial port input and

output word lengths are 24 bits; however, eight extra headroom

bits are used in the processor to allow internal gains of up to

48 dB without clipping. Additional gains can be achieved by

initially scaling down the input signal in the DSP signal flow.

DSP CORE

8.24 FORMAT

42dB OF HEADROOM

DYNAMIC RANGE = 192dB

SERIAL INPUT PORT

1.23 FORMAT

SERIAL OUTPUT PORT

1.23 FORMAT

(HEADROOM)

MAXIMUM 0dBFS

DYNAMIC RANGE = 144dB

24-BITS

32-BITS

24-BITS

(HEADROOM)

Figure 79. Signal Range for 1.23 Format (Serial Ports, ASRCs) and 8.24 Format (DSP Core)

Rev. A | Page 83 of 207

ADAU1463/ADAU1467

Data Sheet

Numerical Format: 8.24

The linear range for the 8.24 format is −128.0 to (+128.0 − 1 LSB). The dynamic range (ratio of the largest possible signal level to the

smallest possible nonzero signal level) is 192 dB.

The following is an example of this numerical format:

0b 1000 0000 0000 0000 0000 0000 0000 0000 = 0x80000000 = −128.0

0b 1110 0000 0000 0000 0000 0000 0000 0000 = 0xE0000000 = −32.0

0b 1111 1000 0000 0000 0000 0000 0000 0000 = 0xF8000000 = −8.0

0b 1111 1110 0000 0000 0000 0000 0000 0000 = 0xFE000000 = −2

0b 1111 1111 0000 0000 0000 0000 0000 0000 = 0xFF000000 = −1

0b 1111 1111 1000 0000 0000 0000 0000 0000 = 0xFF800000 = −0.5

0b 1111 1111 1110 0110 0110 0110 0110 0110 = 0xFFE66666 = −0.1

0b 1111 1111 1111 1111 1111 1111 1111 1111 = 0xFFFFFFFF = −0.00000005 (1 LSB below 0.0)

0b 0000 0000 0000 0000 0000 0000 0000 0000 = 0x00000000 = 0.0

0b 0000 0000 0000 0000 0000 0000 0000 0001 = 0x00000001 = 0.00000005 (1 LSB above 0.0)

0b 0000 0000 0001 1001 1001 1001 1001 1001 = 0x00199999 = 0.1

0b 0000 0000 0100 0000 0000 0000 0000 0000 = 0x00400000 = 0.25

0b 0000 0000 1000 0000 0000 0000 0000 0000 = 0x00800000 = 0.5

0b 0000 0001 0000 0000 0000 0000 0000 0000 = 0x01000000 = 1.0

0b 0000 0010 0000 0000 0000 0000 0000 0000 = 0x02000000 = 2.0

0b 0111 1111 1111 1111 1111 1111 1111 1111 = 0x7FFFFFFF = 127.99999994 (1 LSB below 128.0)

Numerical Format: 32.0

The 32.0 format is used for logic signals in the DSP program flow that are integers. The linear range is −2,147,483,648 to +2,147,483,647.

The dynamic range (ratio of the largest possible signal level to the smallest possible nonzero signal level) is 192 dB.

The following is an example of this numerical format:

0b 1000 0000 0000 0000 0000 0000 0000 0000 = 0x80000000 = −2147483648

0b 1000 0000 0000 0000 0000 0000 0000 0001 = 0x80000001 = −2147483647

0b 1000 0000 0000 0000 0000 0000 0000 0010 = 0x80000002 = −2147483646

0b 1100 0000 0000 0000 0000 0000 0000 0000 = 0xC0000000 = −1073741824

0b 1110 0000 0000 0000 0000 0000 0000 0000 = 0xE0000000 = −536870912

0b 1111 1111 1111 1111 1111 1111 1111 1100 = 0xFFFFFFFC = −4

0b 1111 1111 1111 1111 1111 1111 1111 1110 = 0xFFFFFFFE = −2

0b 1111 1111 1111 1111 1111 1111 1111 1111 = 0xFFFFFFFF = −1

0b 0000 0000 0000 0000 0000 0000 0000 0000 = 0x00000000 = 0

0b 0000 0000 0000 0000 0000 0000 0000 0001 = 0x00000001 = 1

0b 0000 0000 0000 0000 0000 0000 0000 0010 = 0x00000002 = 2

0b 0000 0000 0000 0000 0000 0000 0000 0011 = 0x00000003 = 3

0b 0000 0000 0000 0000 0000 0000 0000 0100 = 0x00000004 = 4

0b 0111 1111 1111 1111 1111 1111 1111 1110 = 0x7FFFFFFE = 2147483646

0b 0111 1111 1111 1111 1111 1111 1111 1111 = 0x7FFFFFFF = 2147483647

Rev. A | Page 84 of 207

Data Sheet

ADAU1463/ADAU1467

of one block. For example, at a sample rate of 48 kHz, with

a block size of 256 samples, one block is 256/48,000 sec, or

53.3 ms.

Hardware Accelerators

The core includes accelerators like division, square root, barrel

shifters, Base 2 logarithm, Base 2 exponential, slew, and a

pseudorandom number generator. These hardware accelerators

reduce the number of instructions required for complex audio

processing algorithms.

3. After waiting the appropriate amount of time, as defined in

Step 2, download the new program and data memory contents

to the corresponding memory locations using the I²C/SPI

slave control port.

The division accelerator enables efficient processing for audio

algorithms like compression and limiting. The square root

accelerator enables efficient processing for audio algorithms

such as loudness, rms envelopes, and filter coefficient

calculations. The logarithm and exponent accelerators enable

efficient processing for audio algorithms involving decibel

conversion. The slew accelerators provide click free updates of

parameters that must change slowly over time, allowing audio

processing algorithms such as mixers, crossfaders, dynamic

filters, and dynamic volume controls. The pseudorandom

number generator can efficiently produce white noise, pink

noise, and dither.

4. Start the DSP core (Register 0xF402 (START_CORE), Bit 0

(START_CORE) = 0b1).

5. Wait at least two audio samples for the DSP initialization to

execute. For example, at a sample rate of 48 kHz, two samples

are equal to 2/48,000 sec, or 41.66 µs.

Reliability Features

Several reliability features are controlled by a panic manager

subsystem that monitors the state of the SigmaDSP core and

memories and generates alerts if error conditions are encountered.

The panic manager indicates error conditions to the user via

register flags and GPIO outputs. The origin of the error can be

traced to different functional blocks such as the watchdog,

memory, stack, software program, and core op codes.

Programming the SigmaDSP Core

The SigmaDSP is programmable via the SigmaStudio graphical

development tools.

Although designed mostly as an aid for software development,

the panic manager is also useful in monitoring the state of the

memories over long periods of time, such as in applications

where the system operates unattended for an extended period,

and resets are infrequent. The memories in the device have a

built in self test feature that runs automatically while the device

is in operation. If a memory corruption is detected, the appropriate

flag is signaled in the panic manager. The program running in

the DSP core can monitor the state of the panic manager and

can mute the audio outputs if an error is encountered, and external

devices, such as microcontrollers, can poll the panic manager

registers or monitor the multipurpose pins to perform some

preprogrammed action, if necessary.

When the SigmaDSP core is running a program and the user needs

to reprogram the program and data memories during operation

of the device, the core must be stopped while the memory is

being updated to avoid undesired noises on the DSP outputs.

The following sequence of steps is appropriate for programming

the memories at boot time, or reprogramming the memories

during operation:

1. Enable soft reset (Register 0xF890 (SOFT_RESET), Bit 0

(SOFT_RESET) = 0b0), then disable soft reset (Register 0xF890

(SOFT_RESET), Bit 0 (SOFT_RESET) = 0b1).

2. If the DSP is in the process of executing a program, wait for

the current sample or block to finish processing. For programs

with no block processing elements in the signal flow, use the

length of one sample. For example, at a sample rate of 48 kHz,

one sample is 1/48000 sec, or 20.83 µs. For programs with

block processing elements in the signal flow, use the length

DSP Core and Reliability Registers

An overview of the registers related to the DSP core is shown in

Table 54. For a more detailed description, see the DSP Core

Control Registers section and Debug and Reliability Registers

section.

Rev. A | Page 85 of 207

ADAU1463/ADAU1467

Data Sheet

Table 54. DSP Core and Reliability Registers

Address

0xF400

0xF401

0xF402

0xF403

0xF404

0xF405

0xF421

0xF422

0xF423

0xF424

0xF425

0xF426

0xF427

0xF428

0xF432

0xF443

0xF444

0xF450

0xF451

0xF460

0xF461

0xF462

0xF463

0xF464

0xF465

Register

Description

Hibernate

START_PULSE

START_CORE

KILL_CORE

START_ADDRESS

CORE_STATUS

PANIC_CLEAR

PANIC_PARITY_MASK

PANIC_SOFTWARE_MASK

PANIC_WD_MASK

PANIC_STACK_MASK

PANIC_LOOP_MASK

PANIC_FLAG

Hibernate setting

Start pulse selection

Instruction to start the core

Instruction to stop the core

Start address of the program

Core status

Clear the panic manager

Panic parity

Panic Mask 0

Panic Mask 1

Panic Mask 2

Panic Mask 3

Panic flag

Panic code

Execute stage error program count

Watchdog maximum count

Watchdog prescale

Enable block interrupts

Value for the block interrupt counter

Program counter, Bits[23:16]

Program counter, Bits[15:0]

Program counter clear

Program counter length, Bits[23:16]

Program counter length, Bits[15:0]

Program counter maximum length, Bits[23:16]

PANIC_CODE

EXECUTE_COUNT

WATCHDOG_MAXCOUNT

WATCHDOG_PRESCALE

BLOCKINT_EN

BLOCKINT_VALUE

PROG_CNTR0

PROG_CNTR1

PROG_CNTR_CLEAR

PROG_CNTR_LENGTH0

PROG_CNTR_LENGTH1

PROG_CNTR_MAXLENGTH0

Rev. A | Page 86 of 207

Data Sheet

ADAU1463/ADAU1467

written is one. This parameter also serves as the trigger; when it

is written, a safeload write is triggered on the next frame.

SOFTWARE FEATURES

Software Safeload

Because the slave port cannot access all of the core data memory

from a single 16-bit address space, the safeload subroutine

needs to know whether to write to the lower (Page 1) or upper

(Page 2) section of memory. If the first parameter is to be place

on Page 1 (lower memory), write the number of parameters to

be automatically written (1 to 5) to num_SafeLoad_Lower and

write 0 to num_SafeLoad_Upper. Conversely, if the first

parameter is to be placed on Page 2 (upper memory), write 0 to

num_SafeLoad_Lower and write the number of parameters to

be automatically written (1 to 5) to num_SafeLoad_Upper. One

of these values passed must always be a number between one

and five inclusive, and the other value must be zero. The second

write triggers the safeload operation.

To prevent making the filter unstable during coefficient

transitions, the SigmaStudio compiler implements a software

safeload mechanism that is enabled by default. The safeload

mechanism is also helpful for reducing pops and clicks during

parameter updates. SigmaStudio automatically sets up the

necessary code and parameters for all new projects. The safeload

code, together with other initialization code, fills the beginning

section of program RAM. Several data memory locations are

reserved by the compiler for use with the software safeload

feature. The exact parameter addresses are not fixed; therefore,

the addresses must be obtained by reading the log file generated

by the compiler. In most cases, the addresses for software safeload

parameters match the defaults shown in Table 55.

The safeload mechanism is software based and executes once

per audio frame. Therefore, system designers must take care when

designing the communication protocol. A delay that is equal to or

greater than the sampling period (the inverse of the sampling

frequency) is required between each safeload write. At a sample

rate of 48 kHz, the delay is equal to ≥20.83 µs. Not observing this

delay corrupts the downloaded data.

Table 55. Default Software Safeload Memory Addresses

Address

(Hex)

Parameter

Function

0x6000

0x6001

0x6002

0x6003

0x6004

0x6005

data_SafeLoad[0]

data_SafeLoad[1]

data_SafeLoad[2]

data_SafeLoad[3]

data_SafeLoad[4]

address_SafeLoad

Safeload Data Slot 0

Safeload Data Slot 1

Safeload Data Slot 2

Safeload Data Slot 3

Safeload Data Slot 4

Because the compiler has control over the addresses used for soft-

ware safeload, the addresses assigned to each parameter may

differ from the default values in Table 55. The compiler generates

a file named compiler_output.log in the project folder where the

SigmaStudio project is stored on the hard drive. In this file, the

addresses assigned to the software safeload parameters can be

confirmed.

Target address for safeload

transfer

0x6006

0x6007

num_SafeLoad_Lower Number of words to

write/safeload trigger

if on Page 1 lower memory

num_SafeLoad_Upper Number of words to

write/safeload trigger

if on Page 2 upper memory

Figure 80 shows an example of the software safeload parameter

definitions in an excerpt from the compiler_output.log file.

The first five addresses in Table 55 are the five data_SafeLoad[x]

parameters, which are slots for storing the data to be transferred

into another target memory location. The safeload parameter space

contains five data slots, by default, because most standard signal

processing algorithms have five parameters or fewer.

The following steps are necessary for executing a software safeload:

1. Confirm that no safeload operation has been executed in

the span of the last audio sample.

2. Write the desired data to the data_SafeLoad[x], Bit x

parameters, starting at data_SafeLoad[x], Bit 0, and

incrementing, as needed, up to a maximum of five

parameters.

The address_SafeLoad parameter is the target address in parameter

RAM. This target address designates the first address to be written

in the safeload transfer. If more than one word is written, the

address increments automatically for each data-word.

3. Write the desired starting target address to the

address_SafeLoad parameter.

The num_SafeLoad_Lower and num_SafeLoad_Upper

parameters designate the number of words to be written. For a

biquad filter algorithm, the number of words to be written is five

because there are five coefficients in a biquad IIR filter. For a

simple, single-gain algorithm, the number of words to be

4. Write the number of words to be transferred to the num_

SafeLoad_Lower and num_SafeLoad_Upper parameters. The

minimum write length is one word, and the maximum

write length is five words.

5. Wait one audio frame for the safeload operation to complete.

Rev. A | Page 87 of 207

ADAU1463/ADAU1467

Data Sheet

Figure 80. Compiler Log Output Excerpt with SafeLoad Module Definitions

Soft Reset Function

PIN DRIVE STRENGTH, SLEW RATE, AND PULL

CONFIGURATION

The soft reset function allows the device to enter a state similar to

RESET

when the hardware

pin is connected to ground. All control

Every digital output pin has configurable drive strength and

slew rate. This feature allows the current sourcing ability of the

driver to be modified to fit the application circuit. In general,

higher drive strength is needed to improve signal integrity when

driving high frequency clocks over long distances. Use lower

drive strength for lower frequency clock signals, shorter traces,

or when reduced system electromagnetic interference (EMI) is

desired. Increase the slew rate if the edges of the clock signal

have rise or fall times that are too long. To achieve adequate signal

integrity and minimize electromagnetic emissions, use the drive

strength and slew rate settings in combination with good

mixed-signal PCB design practices.

registers are reset to their default values, except the PLL registers,

as follows: Register 0xF000 (PLL_CTRL0), Register 0xF001

(PLL_CTRL1), Register 0xF002 (PLL_CLK_SRC), Register 0xF003

(PLL_ENABLE), Register 0xF004 (PLL_LOCK), Register 0xF005

(MCLK_OUT), and Register 0xF006 (PLL_WATCHDOG), as

well as the registers related to the panic manager.

Table 56 shows an overview of the register related to the soft reset

function. For more details, see the Soft Reset Register section.

Table 56. Soft Reset Register

Address

Register

Description

0xF890

SOFT_RESET

Software reset

Pin Drive Strength, Slew Rate, and Pull Configuration

Registers

An overview of the registers related to pin drive strength, slew rate,

and pull configuration is shown in Table 57. For a more detailed

description, see the Hardware Interfacing Registers section.

Rev. A | Page 88 of 207

Data Sheet

ADAU1463/ADAU1467

Table 57. Pin Drive Strength, Slew Rate, and Pull Configuration Registers

Address

0xF780

0xF781

0xF782

0xF783

0xF784

0xF785

0xF786

0xF787

0xF788

0xF789

0xF78A

0xF78B

0xF78C

0xF78D

0xF78E

0xF78F

0xF790

0xF791

0xF792

0xF793

0xF794

0xF795

0xF796

0xF797

0xF798

0xF799

0xF79A

0xF79B

0xF79C

0xF79D

0xF79E

0xF79F

0xF7A0

0xF7A1

0xF7A2

0xF7A3

Register

Description

BCLK_IN0_PIN

BCLK_IN1_PIN

BCLK_IN2_PIN

BCLK_IN3_PIN

BCLK_OUT0_PIN

BCLK_OUT1_PIN

BCLK_OUT2_PIN

BCLK_OUT3_PIN

LRCLK_IN0_PIN

LRCLK_IN1_PIN

LRCLK_IN2_PIN

LRCLK_IN3_PIN

LRCLK_OUT0_PIN

LRCLK_OUT1_PIN

LRCLK_OUT2_PIN

LRCLK_OUT3_PIN

SDATA_IN0_PIN

SDATA_IN1_PIN

SDATA_IN2_PIN

SDATA_IN3_PIN

SDATA_OUT0_PIN

SDATA_OUT1_PIN

SDATA_OUT2_PIN

SDATA_OUT3_PIN

SPDIF_TX_PIN

SCLK_SCL_PIN

MISO_SDA_PIN

SS_PIN

BCLK input pin drive strength and slew rate (BCLK_IN0)

BCLK input pin drive strength and slew rate (BCLK_IN1)

BCLK input pin drive strength and slew rate (BCLK_IN2)

BCLK input pin drive strength and slew rate (BCLK_IN3)

BCLK output pin drive strength and slew rate (BCLK_OUT0)

BCLK output pin drive strength and slew rate (BCLK_OUT1)

BCLK output pin drive strength and slew rate (BCLK_OUT2)

BCLK output pin drive strength and slew rate (BCLK_OUT3)

LRCLK input pin drive strength and slew rate (LRCLK_IN0)

LRCLK input pin drive strength and slew rate (LRCLK_IN1)

LRCLK input pin drive strength and slew rate (LRCLK_IN2)

LRCLK input pin drive strength and slew rate (LRCLK_IN3)

LRCLK output pin drive strength and slew rate (LRCLK_OUT0)

LRCLK output pin drive strength and slew rate (LRCLK_OUT1)

LRCLK output pin drive strength and slew rate (LRCLK_OUT2)

LRCLK output pin drive strength and slew rate (LRCLK_OUT3)

SDATA input pin drive strength and slew rate (SDATA_IN0)

SDATA input pin drive strength and slew rate (SDATA_IN1)

SDATA input pin drive strength and slew rate (SDATA_IN2)

SDATA input pin drive strength and slew rate (SDATA_IN3)

SDATA output pin drive strength and slew rate (SDATA_OUT0)

SDATA output pin drive strength and slew rate (SDATA_OUT1)

SDATA output pin drive strength and slew rate (SDATA_OUT2)

SDATA output pin drive strength and slew rate (SDATA_OUT3)

S/PDIF transmitter pin drive strength and slew rate

SCLK/SCL pin drive strength and slew rate

MISO/SDA pin drive strength and slew rate

SS/ADDR0 pin drive strength and slew rate

MOSI/ADDR1 pin drive strength and slew rate

SCL_M/SCLK_M/MP2 pin drive strength and slew rate

SDA_M/MISO_M/MP3 pin drive strength and slew rate

SS_M/MP0 pin drive strength and slew rate

MOSI_M/MP1 pin drive strength and slew rate

MP6 pin drive strength and slew rate

MOSI_ADDR1_PIN

SCLK_SCL_M_PIN

MISO_SDA_M_PIN

SS_M_PIN

MOSI_M_PIN

MP6_PIN

MP7_PIN

CLKOUT_PIN

MP7 pin drive strength and slew rate

CLKOUT pin drive strength and slew rate

Rev. A | Page 89 of 207

ADAU1463/ADAU1467

Data Sheet

GLOBAL RAM AND CONTROL REGISTER MAP

The complete set of addresses accessible via the slave I²C/SPI

control port is described in this section. The addresses are

divided into two main parts: memory and registers.

has parity bit protection. The panic manager flags parity errors

when they are detected. Modulo memory addressing is used in

several audio processing algorithms. The boundaries between

the fixed and rotating memories are set in SigmaStudio by the

compiler, and they require no action on the part of the user.

RANDOM ACCESS MEMORY

The ADAU1467 has 1.28 Mb of data memory (40 kWords

storing 32-bit data). The ADAU1463 has 512 kb of data

(16 kWords storing 32-bit data).

Data and parameters assignment to the different memory spaces

are handled in software. The modulo boundary locations are

flexible.

The ADAU1463/ADAU1467 have 8 kWords of program memory.

Program memory consists of 32-bit words. Op codes for the DSP

core are either 32 bits or 64 bits; therefore, program instructions

can take up one or two addresses in memory. The program

memory has parity bit protection. The panic manager flags

parity errors when they are detected.

A ROM table (of over 7 kWords), containing a set of commonly

used constants, can be accessed by the DSP core. This memory

increases the efficiency of audio processing algorithm development.

The table includes information such as trigonometric tables,

including sine, cosine, tangent, and hyperbolic tangent, twiddle

factors for frequency domain processing, real mathematical

constants, such as pi and factors of 2, and complex constants.

The ROM table is not accessible from the I²C or SPI slave

control port.

Program memory can only be written or read when the core is

stopped. The program memory is hardware protected so that it

cannot be accidentally overwritten or corrupted at run time.

The DSP core is able to access directly all memory and registers.

All memory addresses store 32 bits (4 bytes) of data. The

memory spaces for the ADAU1467 are defined in Table 58. The

memory spaces for the ADAU1463 are defined in Table 59.

Data memory acts as a storage area for both audio data and signal

processing parameters, such as filter coefficients. The data memory

Table 58. ADAU1467 Memory Map

Address Range

0x0000 to 0x4FFF

0x6000 to 0xAFFF

0xC000 to 0xEFFF

Length

Memory

Data-Word Size

20,480 words

12,288 words

DM0 (Data Memory 0)—lower (Page 1)

DM0 (Data Memory 0)—upper (Page 2)

DM1 (Data Memory 1)—lower (Page 1)

DM1 (Data Memory 1)—upper (Page 2)

Program memory—lower (Page 1)

Program memory—upper (Page 2)

32 bits

Table 59. ADAU1463 Memory Map

Address Range

0x0000 to 0x2FFF

0x6000 to 0x8FFF

0xC000 to 0xDFFF

Length

Memory

Data-Word Size

32 bits

12,288 words

8192 words

DM0 (Data Memory 0)—lower (Page 1)

DM0 (Data Memory 0)—upper (Page 2)

DM1 (Data Memory 1)—lower (Page 1)

DM1 (Data Memory 1)—lower (Page 2)

Program memory—lower (Page 1)

Program memory—lower (Page 2)

32 bits

Rev. A | Page 90 of 207

Data Sheet

ADAU1463/ADAU1467

PM BUS

DM0 BUS

DM1 BUS

CORE

ADDRESS

SLAVE CONTROL PORT

ADDRESS/MAPPING

CORE

ADDRESS

SLAVE CONTROL PORT

ADDRESS/MAPPING

CORE

ADDRESS

SLAVE CONTROL PORT

ADDRESS/MAPPING

0x0000

0xC000

0x0000

0x6000

PM LOWER

(PAGE 1)

DM1 LOWER

(PAGE 1)

DM0 LOWER

(PAGE 1)

0x1FFF

0x2000

0xDFFF

0xC000

0x2FFF

0x3000

0x2FFF 0x2FFF

0x8FFF

0x6000

PM UPPER

(PAGE 2)

0x3000

0x0000

0x3FFF

0x4000

0xDFFF

DM0 UPPER

(PAGE 2)

DM1 UPPER

(PAGE 2)

0x5FFF 0x2FFF

0x6000

0x5FFF

0x6000

0x8FFF

0xBFFF

0xC000

0xBFFF

0xC000

0xBFFF

0xC000

BOOT

ROM

DATA

ROM 0

DATA

ROM 1

0xEFFF

0xF000

0xEFFF

0xF000

REGISTERS

0xFBFF 0xFBFF

0xF000

REGISTERS

0xFBFF

0xFBFF 0xFBFF

Figure 81. ADAU1463 Slave Port Address to DSP Core Address Mapping

Rev. A | Page 91 of 207

ADAU1463/ADAU1467

Data Sheet

PM BUS

DM0 BUS

DM1 BUS

CORE

SLAVE CONTROL PORT

CORE

SLAVE CONTROL PORT

CORE

SLAVE CONTROL PORT

ADDRESS ADDRESS/MAPPING

0x0000

0xC000

0x0000

0x6000

PM LOWER

(PAGE 1)

DM0 LOWER

(PAGE 1)

DM1 LOWER

(PAGE 1)

0x2FFF 0xEFFF

0x3000

0xC000

PM UPPER

(PAGE 2)

0x4FFF

0x5000

0x4FFF

0x0000

0x4FFF

0x5000

0xAFFF

0x6000

0x5FFF 0xEFFF

0x6000

DM0 UPPER

(PAGE 2)

DM1 UPPER

(PAGE 2)

0x9FFF

0xA000

0x4FFF

0x9FFF

0xA000

0xAFFF

0xBFFF

0xC000

0xBFFF

0xC000

0xBFFF

0xC000

BOOT

ROM

DATA

ROM 0

DATA

ROM 1

0xEFFF

0xF000

0xEFFF

0xF000

0xEFFF

0xF000

REGISTERS

0xFBFF 0xFBFF

0xF000

REGISTERS

0xFBFF

Figure 82. ADAU1467 Slave Port Address to DSP Core Address Mapping

Rev. A | Page 92 of 207

Data Sheet

ADAU1463/ADAU1467

CONTROL REGISTERS

All control registers store 16 bits (two bytes) of data. The register map is defined in Table 60.

Table 60. Control Register Summary

Reg

Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0xF000 PLL_CTRL0

[15:8]

RESERVED

0x0060 RW

0x0000 RW

[7:0]

[15:8]

[7:0]

RESERVED

PLL_FBDIVIDER

0xF001 PLL_CTRL1

RESERVED

PLL_DIV

0xF002 PLL_CLK_SRC [15:8]

RESERVED

[7:0]

0xF003 PLL_ENABLE [15:8]

[7:0]

RESERVED

CLKSRC

PLL_ENABLE

PLL_LOCK

0xF004 PLL_LOCK

[15:8]

[7:0]

0x0000

R

0xF005 MCLK_OUT

[15:8]

[7:0]

RESERVED

CLKOUT_RATE

CLKOUT_

ENABLE

0xF006 PLL_

WATCHDOG

[15:8]

[7:0]

RESERVED

0x0001

R

RESERVED

PLL_

WATCHDOG

0xF020 CLK_GEN1_M [15:8]

CLOCKGEN1_

M[8]

0x0006 RW

0x0001 RW

0x0009 RW

0x0001 RW

[7:0]

CLOCKGEN1_M[7:0]

RESERVED

0xF021 CLK_GEN1_N [15:8]

CLOCKGEN1_

N[8]

[7:0]

CLOCKGEN1_N[7:0]

RESERVED

0xF022 CLK_GEN2_M [15:8]

CLOCKGEN2_

M[8]

[7:0]

CLOCKGEN2_M[7:0]

RESERVED

0xF023 CLK_GEN2_N [15:8]

CLOCKGEN2_

N[8]

[7:0]

0xF024 CLK_GEN3_M [15:8]

[7:0]

CLOCKGEN2_N[7:0]

CLOCKGEN3_M[15:8]

CLOCKGEN3_M[7:0]

CLOCKGEN3_N[15:8]

CLOCKGEN3_N[7:0]

RESERVED

0x0000 RW

0x000E RW

0xF025 CLK_GEN3_N [15:8]

[7:0]

0xF026 CLK_GEN3_

SRC

[15:8]

[7:0]

RESERVED

CLK_GEN3_SRC

FREF_PIN

0xF027 CLK_GEN3_

LOCK

[15:8]

RESERVED

0x0000

R

[7:0]

RESERVED

CLK_GEN3_PWR

GEN3_LOCK

0xF050 POWER_

ENABLE0

[15:8]

CLK_GEN2_PWR

SIN3_PWR

CLK_GEN1_

PWR

ASRCBANK1_ ASRCBANK0_

PWR

0x0000 RW

PWR

[7:0] SOUT3_PWR SOUT2_

PWR

SOUT1_PWR SOUT0_PWR

SIN2_PWR

SIN1_PWR

SIN0_PWR

0xF051 POWER_

ENABLE1

[15:8]

RESERVED

[7:0]

RESERVED

PDM1_PWR

PDM0_PWR

RESERVED

TX_PWR

RX_PWR

ADC_PWR

0xF100 ASRC_INPUTx [15:8]

0x0000 RW

to

0xF107

[7:0]

ASRC_SIN_CHANNEL

ASRC_SOURCE

0xF140 ASRC_OUT_

to

[15:8]

RESERVED

RATEx

0xF147

[7:0]

RESERVED

ASRC_RATE

0xF180 SOUT_

[15:8]

RESERVED

0x0000 RW

to

SOURCEx

0xF197

[7:0]

RESERVED

SOUT_ASRC_SELECT

RESERVED

SOUT_SOURCE

0xF1C0 SPDIFTX_

INPUT

[15:8]

[7:0]

RESERVED

SPDIFTX_SOURCE

0xF200 SERIAL_

[15:8]

LRCLK_SRC

WORD_LEN

BCLK_SRC

DATA_FMT

LRCLK_MODE LRCLK_POL

to

BYTE_x_0

0xF21C

[7:0] BCLK_POL

TDM_MODE

Rev. A | Page 93 of 207

ADAU1463/ADAU1467

Data Sheet

Reg

Name

Bits Bit 7

Bit 6

RESERVED[1:0]

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0xF201 SERIAL_

to

0xF21D

[15:8]

RESERVED

0x0002 RW

0x0000 RW

BYTE_x_1

[7:0]

TRISTATE

ENBL

CLK_DOMAIN

FS

0xF240 SDATA_x_

to

0xF247

[15:8]

RESERVED

ROUTE

[7:0]

DIR

PORT_SEL

CHAN

0xF300 FTDM_INx

to

0xF33F

[15:8]

[7:0] SLOT_

REVERSE_ SERIAL_IN_

IN_BYTE SEL

CHANNEL_IN_POS

BYTE_IN_POS

ENABLE_IN

0xF380 FTDM_OUTx [15:8]

to

0xF3BF

RESERVED

[7:0] SLOT_

REVERSE_ SERIAL_

CHANNEL_OUT_POS

BYTE_OUT_POS

ENABLE_OUT OUT_BYTE OUT_SEL

0xF400 HIBERNATE

[15:8]

[7:0]

RESERVED

0x0000 RW

0x0002 RW

0x0000 RW

RESERVED[

HIBERNATE

0xF401 START_PULSE [15:8]

RESERVED

[7:0]

0xF402 START_CORE [15:8]

[7:0]

RESERVED

START_PULSE

RESERVED

START_CORE

KILL_CORE

0xF403 KILL_CORE

[15:8]

[7:0]

0xF404 START_

ADDRESS

[15:8]

START_ADDRESS[15:8]

[7:0]

START_ADDRESS[7:0]

RESERVED

0xF405 CORE_ STATUS [15:8]

0x0000

R

[7:0]

0xF421 PANIC_CLEAR [15:8]

[7:0]

RESERVED

CORE_STATUS

RESERVED

0x0000 RW

RESERVED

PANIC_CLEAR

0xF422 PANIC_

PARITY_MASK

[15:8]

RESERVED

DM1_BANK3_

MASK

DM1_BANK2_

MASK

DM1_BANK1_ DM1_BANK0_ 0x0003 RW

MASK MASK

[7:0] DM0_BANK3_ DM0_

DM0_BANK1_ DM0_BANK0_MASK PM1_MASK

MASK

PM0_MASK

ASRC1_MASK ASRC0_MASK

MASK

BANK2_

MASK

0xF423 PANIC_

SOFTWARE_

MASK

[15:8]

[7:0]

RESERVED

0x0000 RW

RESERVED

PANIC_

SOFTWARE

0xF424 PANIC_WD_ [15:8]

MASK

0x0000 RW

[7:0]

RESERVED

PANIC_WD

0xF425 PANIC_

STACK_MASK

[15:8]

[7:0]

RESERVED

PANIC_STACK

0xF426 PANIC_LOOP_ [15:8]

MASK

[7:0]

0xF427 PANIC_FLAG [15:8]

[7:0]

RESERVED

PANIC_LOOP

PANIC_FLAG

0x0000

R

0xF428 PANIC_CODE [15:8] ERR_SOFT

ERR_LOOP ERR_STACK ERR_WATCHDOG

ERR_DM1B3

ERR_PM1

ERR_DM1B2

ERR_PM0

ERR_DM1B1

ERR_ASRC1

ERR_DM1B0

ERR_ASRC0

[7:0] ERR_DM0B3 ERR_DM0B2 ERR_DM0B1 ERR_DM0B0

[15:8]

0xF432 EXECUTE_

COUNT

EXECUTE_COUNT[15:8]

[7:0]

EXECUTE_COUNT[7:0]

0xF443 WATCHDOG_ [15:8]

RESERVED

WD_MAXCOUNT[12:8]

0x0000 RW

MAXCOUNT

[7:0]

WD_MAXCOUNT[7:0]

RESERVED

0xF444 WATCHDOG_ [15:8]

PRESCALE

[7:0]

RESERVED

WD_PRESCALE

0xF450 BLOCKINT_EN [15:8]

[7:0]

RESERVED

BLOCKINT_EN

0xF451 BLOCKINT_

VALUE

[15:8]

BLOCKINT_VALUE[15:8]

[7:0]

BLOCKINT_VALUE[7:0]

RESERVED

0xF460 PROG_CNTR0 [15:8]

0x0000

R

[7:0]

0xF461 PROG_CNTR1 [15:8]

[7:0]

PROG_CNTR_MSB

PROG_CNTR_LSB[15:8]

PROG_CNTR_LSB[7:0]

Rev. A | Page 94 of 207

Data Sheet

ADAU1463/ADAU1467

Reg

Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0xF462 PROG_CNTR_ [15:8]

CLEAR

RESERVED

0x0000 RW

[7:0]

RESERVED

PROG_CNTR_

CLEAR

0xF463 PROG_CNTR_ [15:8]

LENGTH0

RESERVED

0x0000

R

[7:0]

PROG_LENGTH_MSB

0xF464 PROG_CNTR_ [15:8]

LENGTH1

PROG_LENGTH_LSB[15:8]

[7:0]

PROG_LENGTH_LSB[7:0]

RESERVED

0xF465 PROG_CNTR_ [15:8]

0x0000

R

MAXLENGTH0

[7:0]

PROG_MAXLENGTH_MSB

PROG_MAXLENGTH_LSB[15:8]

PROG_MAXLENGTH_LSB[7:0]

0xF466 PROG_CNTR_ [15:8]

MAXLENGTH1

[7:0]

0xF467 PANIC_

PARITY_

[15:8]

[7:0]

RESERVED

DM0_BANK1_

SUBBANK4_MASK

DM0_BANK1_

SUBBANK3_MASK SUBBANK2_

MASK

DM0_BANK1_

DM0_BANK1_ DM0_BANK1_ 0x0000 RW

SUBBANK1_

MASK

SUBBANK0_

MASK

MASK1

DM0_BANK0_

SUBBANK4_MASK

DM0_BANK0_

SUBBANK3_MASK SUBBANK2_

MASK

DM0_BANK0_

DM0_BANK0_ DM0_BANK0_

SUBBANK1_

MASK

SUBBANK0_

MASK

0xF468 PANIC_

PARITY_

[15:8]

[7:0]

DM0_BANK3_

SUBBANK4_MASK

DM0_BANK3_

SUBBANK3_MASK SUBBANK2_

MASK

DM0_BANK3_

DM0_BANK3_S DM0_BANK3_ 0x0000 RW

UBBANK1_

MASK

SUBBANK0_

MASK

MASK2

DM0_BANK2_

SUBBANK4_MASK

DM0_BANK2_

SUBBANK3_MASK SUBBANK2_

MASK

DM0_BANK2_

DM0_BANK2_S DM0_BANK2_

UBBANK1_

MASK

SUBBANK0_

MASK

0xF469 PANIC_

PARITY_

[15:8]

[7:0]

DM1_BANK1_

SUBBANK4_MASK

DM1_BANK1_

SUBBANK3_MASK SUBBANK2_

MASK

DM1_BANK1_

DM1_BANK1_S DM1_BANK1_ 0x0000 RW

UBBANK1_

MASK

SUBBANK0_

MASK

MASK3

DM1_BANK0_

SUBBANK4_MASK

DM1_BANK0_

SUBBANK3_MASK SUBBANK2_

MASK

DM1_BANK0_

DM1_BANK0_S DM1_BANK0_

UBBANK1_

MASK

SUBBANK0_

MASK

0xF46A PANIC_

PARITY_

[15:8]

[7:0]

DM1_BANK3_

SUBBANK4_MASK

DM1_BANK3_

SUBBANK3_MASK SUBBANK2_

MASK

DM1_BANK3_

DM1_BANK3_S DM1_BANK3_ 0x0000 RW

UBBANK1_

MASK

SUBBANK0_

MASK

MASK4

DM1_BANK2_

DM1_BANK2_S DM1_BANK2_

SUBBANK4_MASK

SUBBANK3_MASK SUBBANK2_

MASK

UBBANK1_

MASK

SUBBANK0_

MASK

0xF46B PANIC_

PARITY_

[15:8]

[7:0]

RESERVED

PM_BANK1_ PM_BANK1_

SUBBANK5_ SUBBANK4_

PM_BANK1_

SUBBANK3_

MASK

PM_BANK1_

SUBBANK2_

MASK

PM_BANK1_

SUBBANK1_

MASK

PM_BANK1_

SUBBANK0_

MASK

0x0000 RW

MASK5

MASK

RESERVED

PM_BANK0_ PM_BANK0_

SUBBANK5_ SUBBANK4_MASK

MASK

PM_BANK0_

SUBBANK3_

MASK

PM_BANK0_

SUBBANK2_

MASK

PM_BANK0_

SUBBANK1_

MASK

PM_BANK0_

SUBBANK0_

MASK

0xF46C PANIC_CODE1 [15:8]

RESERVED

ERR_DM0B1SB4

ERR_DM0B0SB4

ERR_DM0B3SB4

ERR_DM0B2SB4

ERR_DM1B1SB4

ERR_DM1B0SB4

ERR_DM1B3SB4

ERR_DM1B2SB4

ERR_DM0B1SB3

ERR_DM0B0SB3

ERR_DM0B3SB3

ERR_DM0B2SB3

ERR_DM1B1SB3

ERR_DM1B0SB3

ERR_DM1B3SB3

ERR_DM1B2SB3

ERR_PM_B1SB3

ERR_PM_B0SB3

ERR_DM0B1SB2 ERR_

DM0B1SB1

ERR_DM0B0SB2 ERR_

DM0B0SB1

ERR_DM0B3SB2 ERR_

DM0B3SB1

ERR_DM0B2SB2 ERR_

DM0B2SB1

ERR_DM1B1SB2 ERR_

DM1B1SB1

ERR_DM1B0SB2 ERR_

DM1B0SB1

ERR_DM1B3SB2 ERR_

DM1B3SB1

ERR_DM1B2SB2 ERR_

DM1B2SB1

ERR_

DM0B1SB0

0x0000

R

[7:0]

RESERVED

ERR_

DM0B0SB0

0xF46D PANIC_CODE2 [15:8]

ERR_

DM0B3SB0

[7:0]

ERR_

DM0B2SB0

0xF46E PANIC_CODE3 [15:8]

ERR_

DM1B1SB0

[7:0]

0xF46F PANIC_CODE4 [15:8]

[7:0]

ERR_

DM1B0SB0

ERR_

DM1B3SB0

ERR_

DM1B2SB0

0xF470 PANIC_CODE5 [15:8]

[7:0]

RESERVED

ERR_PM_

B1SB5

ERR_PM_B1SB4

ERR_PM_B0SB4

ERR_PM_B1SB2 ERR_PM_

B1SB1

ERR_PM_

B1SB0

ERR_PM_

B0SB5

ERR_PM_B0SB2 ERR_PM_

B0SB1

ERR_PM_

B0SB0

0xF510 MPx_MODE

to

0xF51D

[15:8]

[7:0]

RESERVED

SS_SELECT

0x0000 RW

DEBOUNCE_VALUE

MP_MODE

MP_ENABLE

0xF520 MPx_WRITE

to

0xF52D

[15:8]

[7:0]

RESERVED

MP_REG_ WRITE

MP_REG_READ

0xF530 MPx_READ

to

0xF53D

[15:8]

[7:0]

RESERVED

0x0000

R

Rev. A | Page 95 of 207

ADAU1463/ADAU1467

Data Sheet

Reg

Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

CUTOFF

DMIC_CLK

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0xF560 DMIC_CTRLx [15:8] RESERVED

to

0xF561

MIC_DATA_SRC

0x4000 RW

[7:0] RESERVED

HPF

DMPOL

DMSW

DMIC_EN

0xF580 ASRC_LOCK

[15:8]

RESERVED

ASRC3L

0x0000

0x0000 RW

0x0000

R

[7:0] ASRC7L

ASRC6L

ASRC5L

ASRC4L

RESERVED

ASRC4M

ASRC2L

ASRC1L

ASRC0L

0xF581 ASRC_MUTE [15:8]

[7:0] ASRC7M

LOCKMUTE

ASRC2M

ASRC_RAMP1 ASRC_RAMP0

ASRC1M ASRC0M

ASRC6M

ASRC5M

ASRC3M

0xF582 ASRCx_RATIO [15:8]

to

0xF589

ASRC_RATIO[15:8]

ASRC_RATIO[7:0]

R

[7:0]

0xF590 ASRC_RAMP- [15:8]

MAX_OVR

RESERVED

OVERRIDE

OVR_RAMPMAX_VALUE[10:8]

RAMPMAX_VALUE[10:8]

0x07FF RW

[7:0]

OVR_RAMPMAX_VALUE[7:0]

0xF591 ASRCx_

[15:8]

RESERVED

to

RAMPMAX

0xF598

[7:0]

RAMPMAX_VALUE[7:0]

ADC_VALUE[15:8]

ADC_VALUE[7:0]

0xF5A0 ADC_READx [15:8]

to

0xF5A7

0x0000

R

[7:0]

0xF5C0 MPx_MODE

to

0xF5CB

[15:8]

[7:0]

RESERVED

SS_SELECT

DEBOUNCE_VALUE

MP_MODE

MP_ENABLE

0xF5D0 MPx_WRITE

to

0xF5DB

[15:8]

[7:0]

RESERVED

MP_REG_

WRITE

0xF5E0 MPx_READ

to

0xF5EB

[15:8]

[7:0]

RESERVED

MP_REG_

READ

0xF5F0 SECONDARY_ [15:8]

I2C

RESERVED

0x0000 RW

[7:0]

SECNDARY_I2C_

ENBL

0xF600 SPDIF_LOCK_ [15:8]

DET

0x0000

R

[7:0]

LOCK

0xF601 SPDIF_RX_

CTRL

[15:8]

RESERVED

0x0000 RW

[7:0]

RESERVED

FASTLOCK

FSOUTSTRENGTH

RX_LENGTHCTRL

0xF602 SPDIF_RX_

DECODE

[15:8]

RESERVED

RX_WORDLENGTH_R[3:2]

0x0000

R

[7:0] RX_WORDLENGTH_R[1:0]

RX_WORDLENGTH_L

COMPR_MODE[15:8]

COMPR_MODE[7:0]

RESERVED

COMPR_TYPE AUDIO_TYPE

0xF603 SPDIF_RX_

COMPRMODE

[15:8]

[7:0]

0xF604 SPDIF_

RESTART

[15:8]

0x0000 RW

[7:0]

RESERVED

RESTART_

AUDIO

0xF605 SPDIF_LOSS_ [15:8]

OF_LOCK

0x0000

R

[7:0]

RESERVED

LOSS_OF_LOCK

RX_MCLKSPEED

TX_MCLKSPEED

0xF606 SPDIF_RX_

MCLKSPEED

[15:8]

0x0001 RW

0x0000 RW

[7:0]

RESERVED

0xF607 SPDIF_TX_

MCLKSPEED

[15:8]

[7:0]

RESERVED

0xF608 SPDIF_AUX_ [15:8]

EN

[7:0]

RESERVED

TDMOUT_CLK

TDMOUT

0xF60F SPDIF_RX_

AUXBIT_

[15:8]

[7:0]

RESERVED

0x0000

R

AUXBITS_READY

READY

0xF610 SPDIF_RX_CS_ [15:8]

SPDIF_RX_CS_LEFT[15:8]

to

LEFT_x

0xF61B

[7:0]

SPDIF_RX_CS_LEFT[7:0]

0xF620 SPDIF_RX_CS_ [15:8]

SPDIF_RX_CS_RIGHT[15:8]

0x0000

R

to

RIGHT_x

0xF62B

[7:0]

SPDIF_RX_CS_RIGHT[7:0]

Rev. A | Page 96 of 207

Data Sheet

ADAU1463/ADAU1467

Reg

Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0xF630 SPDIF_RX_

[15:8]

SPDIF_RX_UD_LEFT[15:8]

0x0000

R

to

UD_LEFT_x

0xF63B

[7:0]

SPDIF_RX_UD_LEFT[7:0]

0xF640 SPDIF_RX_

[15:8]

SPDIF_RX_UD_RIGHT[15:8]

0x0000

R

to

UD_RIGHT_x

0xF64B

[7:0]

SPDIF_RX_UD_RIGHT[7:0]

SPDIF_RX_VB_LEFT[15:8]

0xF650 SPDIF_RX_VB_ [15:8]

to

LEFT_x

0xF65B

[7:0]

SPDIF_RX_VB_LEFT[7:0]

0xF660 SPDIF_RX_VB_ [15:8]

SPDIF_RX_VB_RIGHT[15:8]

to

RIGHT_x

0xF66B

[7:0]

SPDIF_RX_VB_RIGHT[7:0]

SPDIF_RX_PB_LEFT[15:8]

0xF670 SPDIF_RX_PB_ [15:8]

to

LEFT_x

0xF67B

[7:0]

SPDIF_RX_PB_LEFT[7:0]

0xF680 SPDIF_RX_PB_ [15:8]

SPDIF_RX_PB_RIGHT[15:8]

to

RIGHT_x

0xF68B

[7:0]

SPDIF_RX_PB_RIGHT[7:0]

RESERVED

0xF690 SPDIF_TX_EN [15:8]

[7:0]

0x0000 RW

RESERVED

TXEN

0xF691 SPDIF_TX_

CTRL

[15:8]

RESERVED

[7:0]

[15:8]

[7:0]

RESERVED

TX_LENGTHCTRL

0xF69F SPDIF_TX_

AUXBIT_

RESERVED

0x0000 RW

TX_AUXBITS_

SOURCE

0xF6A0 SPDIF_TX_CS_ [15:8]

SPDIF_TX_CS_LEFT[15:8]

to

LEFT_x

0xF6AB

[7:0]

SPDIF_TX_CS_LEFT[7:0]

0xF6B0 SPDIF_TX_CS_ [15:8]

SPDIF_TX_CS_RIGHT[15:8]

to

RIGHT_x

0xF6BB

[7:0]

SPDIF_TX_CS_RIGHT[7:0]

SPDIF_TX_UD_LEFT[15:8]

0xF6C0 SPDIF_TX_UD_ [15:8]

to

LEFT_x

0xF6CB

[7:0]

SPDIF_TX_UD_LEFT[7:0]

0xF6D0 SPDIF_TX_UD_ [15:8]

SPDIF_TX_UD_RIGHT[15:8]

to

RIGHT_x

0xF6DB

[7:0]

SPDIF_TX_UD_RIGHT[7:0]

SPDIF_TX_VB_LEFT[15:8]

0xF6E0 SPDIF_TX_VB_ [15:8]

to

LEFT_x

0xF6EB

[7:0]

SPDIF_TX_VB_LEFT[7:0]

0xF6F0 SPDIF_TX_VB_ [15:8]

SPDIF_TX_VB_RIGHT[15:8]

to

RIGHT_x

0xF6FB

[7:0]

SPDIF_TX_VB_RIGHT[7:0]

SPDIF_TX_PB_LEFT[15:8]

0xF700 SPDIF_TX_PB_ [15:8]

to

LEFT_x

0xF70B

[7:0]

SPDIF_TX_PB_LEFT[7:0]

0xF710 SPDIF_TX_PB_ [15:8]

SPDIF_TX_PB_RIGHT[15:8]

to

RIGHT_x

0xF71B

[7:0]

SPDIF_TX_PB_RIGHT[7:0]

RESERVED

0xF780 BCLK_INx_PIN [15:8]

0x0018 RW

to

0xF783

[7:0]

RESERVED

BCLK_IN_PULL

BCLK_IN_SLEW

BCLK_IN_DRIVE

0xF784 BCLK_OUTx_ [15:8]

to

0xF787

RESERVED

[7:0]

RESERVED

BCLK_OUT_PULL

LRCLK_IN_PULL

LRCLK_OUT_PULL

SDATA_IN_PULL

SDATA_OUT_PULL

BCLK_OUT_SLEW

LRCLK_IN_SLEW

LRCLK_OUT_SLEW

SDATA_IN_SLEW

SDATA_OUT_SLEW

BCLK_OUT_DRIVE

LRCLK_IN_DRIVE

LRCLK_OUT_DRIVE

SDATA_IN_DRIVE

SDATA_OUT_DRIVE

0xF788 LRCLK_INx_

to

0xF78B

[15:8]

0x0018 RW

0x0008 RW

[7:0]

0xF78C LRCLK_OUTx_ [15:8]

to

0xF78F

[7:0]

0xF790 SDATA_INx_ [15:8]

to

0xF793

[7:0]

0xF794 SDATA_OUTx_ [15:8]

to

0xF797

[7:0]

Rev. A | Page 97 of 207

ADAU1463/ADAU1467

Data Sheet

Reg

Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

SPDIF_TX_SLEW

SCLK_SCL_SLEW

Bit 1

Bit 0

Reset

RW

0xF798 SPDIF_TX_PIN [15:8]

RESERVED

0x0008 RW

[7:0]

0xF799 SCLK_SCL_PIN [15:8]

[7:0]

RESERVED

SPDIF_TX_PULL

SCLK_SCL_PULL

SPDIF_TX_DRIVE

SCLK_SCL_DRIVE

RESERVED

0xF79A MISO_SDA_

[15:8]

[7:0]

[15:8]

[7:0]

RESERVED

MISO_SDA_PULL

SS_PULL

MISO_SDA_SLEW

SS_SLEW

MISO_SDA_DRIVE

SS_DRIVE

0xF79B SS_PIN

RESERVED

0x0018 RW

0xF79C MOSI_ADDR1_ [15:8]

[7:0]

RESERVED

MOSI_ADDR1_PULL

SCLK_SCL_M_PULL

MOSI_ADDR1_SLEW

SCLK_SCL_M_SLEW

MOSI_ADDR1_DRIVE

SCLK_SCL_M_DRIVE

0xF79D SCLK_SCL_M_ [15:8]

RESERVED

0x0008 RW

[7:0]

0xF79E MISO_SDA_

M_PIN

[15:8]

[7:0]

[15:8]

[7:0]

RESERVED

MISO_SDA_M_PULL

SS_M_PULL

MISO_SDA_M_SLEW

SS_M_SLEW

MISO_SDA_M_DRIVE

SS_M_DRIVE

MOSI_M_DRIVE

MP6_DRIVE

0xF79F SS_M_PIN

RESERVED

0x0018 RW

0x0008 RW

0x0018 RW

0x0000 RW

0xF7A0 MOSI_M_PIN [15:8]

[7:0]

MOSI_M_PULL

MP6_PULL

MOSI_M_SLEW

MP6_SLEW

0xF7A1 MP6_PIN

[15:8]

[7:0]

0xF7A2 MP7_PIN

[15:8]

[7:0]

MP7_PULL

MP7_SLEW

MP7_DRIVE

0xF7A3 CLKOUT_PIN [15:8]

[7:0]

CLKOUT_PULL

MP14_PULL

MP15_PULL

SDATAIO0_PULL

SDATAIO1_PULL

MP24_PULL

MP25_PULL

CLKOUT_SLEW

MP14_SLEW

MP15_SLEW

SDATAIO0_SLEW

SDATAIO1_SLEW

MP24_SLEW

MP25_SLEW

CLKOUT_DRIVE

MP14_DRIVE

MP15_DRIVE

SDATAIO0_DRIVE

SDATAIO1_DRIVE

MP24_DRIVE

MP25_DRIVE

SOFT_RESET

0xF7A8 M14_PIN

[15:8]

[7:0]

0xF7A9 MP15_PIN

[15:8]

[7:0]

0xF7B0 SDATAIO0_PIN [15:8]

[7:0]

0xF7B1 SDATAIO1_PIN [15:8]

[7:0]

0xF7B2 SDATAIO2_PIN [15:8]

[7:0]

0xF7B3 SDATAIO3_PIN [15:8]

[7:0]

0xF7B4 SDATAIO4_PIN [15:8]

[7:0]

0xF7B5 SDATAIO5_PIN [15:8]

[7:0]

0xF7B6 SDATAIO6_PIN [15:8]

[7:0]

0xF7B7 SDATAIO7_PIN [15:8]

[7:0]

0xF7B8 M24_PIN

[15:8]

[7:0]

0xF7B9 MP25_PIN

[15:8]

[7:0]

0xF890 SOFT_RESET [15:8]

[7:0]

RESERVED

0xF899 SECOND-

PAGE_ENABLE

[15:8]

[7:0]

RESERVED

PAGE

Rev. A | Page 98 of 207

Data Sheet

ADAU1463/ADAU1467

CONTROL REGISTER DETAILS

PLL CONFIGURATION REGISTERS

PLL Feedback Divider Register

Address: 0xF000, Reset: 0x0060, Name: PLL_CTRL0

This register is the value of the feedback divider in the PLL. This value effectively multiplies the frequency of the input clock to the PLL,

creating the output system clock, which clocks the DSP core and other digital circuit blocks. The format of the value stored in this register

is binary integer in 7.0 format. For example, the default feedback divider value of 96 is stored as 0x60. The value written to this register

does not take effect until Register 0xF003 (PLL_ENABLE), Bit 0 (PLL_ENABLE) changes state from 0b0 to 0b1.

Table 61. Bit Descriptions for PLL_CTRL0

Bits

Bit Name

Settings Description

Reset

0x0

Access

RW

[15:7]

[6:0]

RESERVED

PLL_FBDIVIDER

PLL feedback divider. This is the value of the feedback divider in the PLL, which

0x60

RW

effectively multiplies the frequency of the input clock to the PLL, creating the

output system clock, which clocks the DSP core and other digital circuit

blocks. The format of the value stored in this register is binary integer in 7.0

format. For example, the default feedback divider value of 96 is stored as 0x60.

PLL Prescale Divider Register

Address: 0xF001, Reset: 0x0000, Name: PLL_CTRL1

This register sets the input prescale divider for the PLL. The value written to this register does not take effect until Register 0xF003

(PLL_ENABLE), Bit 0 (PLL_ENABLE) changes state from 0b0 to 0b1.

Table 62. Bit Descriptions for PLL_CTRL1

Bits

Bit Name

RESERVED

PLL_DIV

Settings

Description

Reset

0x0

Access

RW

[15:2]

[1:0]

PLL input clock divider. This prescale clock divider creates the PLL input

clock from the externally input master clock. The nominal frequency of

the PLL input is 3.072 MHz. Therefore, if the input master clock frequency

is 3.072 MHz, set the prescale clock divider to divide by 1. If the input clock is

12.288 MHz, set the prescale clock divider to divide by 4. Make the input

to the PLL as close to 3.072 MHz as possible.

0x0

RW

00 Divide by 1.

01 Divide by 2.

10 Divide by 4.

11 Divide by 8.

Rev. A | Page 99 of 207

ADAU1463/ADAU1467

Data Sheet

PLL Clock Source Register

Address: 0xF002, Reset: 0x0000, Name: PLL_CLK_SRC

This register selects the source of the clock used for input to the core and the clock generators. The clock can either be taken directly from

the signal on the XTALIN/MCLK pin or from the output of the PLL. The value written to this register does not take effect until Register 0xF003

(PLL_ENABLE), Bit 0 (PLL_ENABLE) changes state from 0b0 to 0b1.

Table 63. Bit Descriptions for PLL_CLK_SRC

Bits

[15:1]

0

Bit Name

RESERVED

CLKSRC

Settings

Description

Reset

Access

RW

0x0

Clock source select. The PLL output is nominally 294.912 MHz, which is the 0x0

nominal operating frequency of the core and the clock generator inputs.

In most use cases, do not use the direct XTALIN/MCLK input option because

the range of allowable frequencies on the XTALIN/MCLK pin has an upper

limit that is significantly lower in frequency than the nominal system clock

frequency.

RW

0

1

Direct from XTALIN/MCLK pin.

PLL clock.

PLL Enable Register

Address: 0xF003, Reset: 0x0000, Name: PLL_ENABLE

This register enables or disables the PLL. The PLL does not attempt to lock to an incoming clock until Bit 0 (PLL_ENABLE) is enabled. When

Bit 0 (PLL_ENABLE) is set to 0b0, the PLL does not output a clock signal, causing all other clock circuits in the device that rely on the PLL to

become idle. When Bit 0 (PLL_ENABLE) transitions from 0b0 to 0b1, the settings in Register 0xF000 (PLL_CTRL0), Register 0xF001

(PLL_CTRL1), Register 0xF002 (PLL_CLK_SRC), and Register 0xF005 (MCLK_OUT) are activated.

Table 64. Bit Descriptions for PLL_ENABLE

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

PLL_ENABLE

PLL enable. Load the values of Register 0xF000, Register 0xF001,

Register 0xF002, and Register 0xF005 when this bit transitions from

0b0 to 0b1.

0x0

RW

0

1

PLL disabled.

PLL enabled.

Rev. A | Page 100 of 207

Data Sheet

ADAU1463/ADAU1467

PLL Lock Register

Address: 0xF004, Reset: 0x0000, Name: PLL_LOCK

This register contains a flag that represents the lock status of the PLL. Lock status has four prerequisites: a stable input clock is routed to

the PLL, the related PLL registers (Register 0xF000 (PLL_CTRL0), Register 0xF001 (PLL_CTRL1), and Register 0xF002 (PLL_CLK_SRC)) are

set appropriately, the PLL is enabled (Register 0xF003 (PLL_ENABLE), Bit 0 (PLL_ENABLE) = 0b1), and the PLL has adequate time to

adjust its feedback path and provide a stable output clock to the rest of the device. The amount of time required to achieve lock to a new

input clock signal varies based on system conditions, so Bit 0 (PLL_LOCK) provides a clear indication of when lock is achieved.

Table 65. Bit Descriptions for PLL_LOCK

Bits

[15:1]

0

Bit Name

RESERVED

PLL_LOCK

Settings

Description

Reset

0x0

Access

RW

PLL lock flag (read only).

PLL unlocked.

PLL locked.

0x0

R

0

1

Rev. A | Page 101 of 207

ADAU1463/ADAU1467

Data Sheet

CLKOUT Control Register

Address: 0xF005, Reset: 0x0000, Name: MCLK_OUT

This register enables and configures the signal output from the CLKOUT pin. The value written to this register does not take effect until

Register 0xF003 (PLL_ENABLE), Bit 0 (PLL_ENABLE), changes state from 0b0 to 0b1.

Table 66. Bit Descriptions for MCLK_OUT

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:3]

[2:1]

RESERVED

CLKOUT_RATE

Frequency of CLKOUT. Frequency of the signal output from the CLKOUT pin.

These bits set the frequency of the signal on the CLKOUT pin. The frequencies

documented in Table 66 are examples that are valid for a master clock input

that is a binary multiple of 3.072 MHz. In this case, the options for output

rates are 3.072 MHz, 6.144 MHz, 12.288 MHz, or 24.576 MHz. If the input

master clock is scaled down (for example, to a binary multiple of 2.8224 MHz),

the possible output rates are 2.8224 MHz, 5.6448 MHz, 11.2896 MHz, or

22.5792 MHz).

0x0

RW

00 Predivider output. This is 3.072 MHz for a nominal system clock of

294.912 MHz.

01 Double the predivider output. This is 6.144 MHz for a nominal system

clock of 294.912 MHz.

10 Four times the predivider output. This is 12.288 MHz for a nominal system

clock of 294.912 MHz.

11 Eight times the predivider output. This is 24.576 MHz for a nominal system

clock of 294.912 MHz.

0

CLKOUT_ENABLE

CLKOUT enable. When this bit is enabled, a clock signal is output from the

CLKOUT pin of the device. When disabled, the CLKOUT pin is high impedance.

0x0

RW

0

1

CLKOUT pin disabled.

CLKOUT pin enabled.

Rev. A | Page 102 of 207

Data Sheet

ADAU1463/ADAU1467

Analog PLL Watchdog Control Register

Address: 0xF006, Reset: 0x0001, Name: PLL_WATCHDOG

The PLL watchdog is a feature that monitors and automatically resets the PLL in the event that it reaches an unstable condition. The PLL

resets itself and automatically attempts to lock to the incoming clock signal again, with the same settings as before. This functionality

requires no interaction from the user. Ensure that the PLL watchdog is enabled at all times.

Table 67. Bit Descriptions for PLL_WATCHDOG

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

PLL_WATCHDOG

PLL watchdog.

0x1

RW

0

1

PLL watchdog disabled.

PLL watchdog enabled.

CLOCK GENERATOR REGISTERS

Denominator (M) for Clock Generator 1 Register

Address: 0xF020, Reset: 0x0006, Name: CLK_GEN1_M

This register contains the denominator (M) for Clock Generator 1.

Table 68. Bit Descriptions for CLK_GEN1_M

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:9]

[8:0]

RESERVED

CLOCKGEN1_M

Clock Generator 1 M (denominator). Format is binary integer.

0x006

RW

Numerator (N) for Clock Generator 1 Register

Address: 0xF021, Reset: 0x0001, Name: CLK_GEN1_N

This register contains the numerator (N) for Clock Generator 1.

Table 69. Bit Descriptions for CLK_GEN1_N

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:9]

[8:0]

RESERVED

CLOCKGEN1_N

Clock Generator 1 N (numerator). Format is binary integer.

0x001

RW

Rev. A | Page 103 of 207

ADAU1463/ADAU1467

Data Sheet

Denominator (M) for Clock Generator 2 Register

Address: 0xF022, Reset: 0x0009, Name: CLK_GEN2_M

This register contains the denominator (M) for Clock Generator 2.

Table 70. Bit Descriptions for CLK_GEN2_M

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:9]

[8:0]

RESERVED

CLOCKGEN2_M

Clock Generator 2 M (denominator). Format is binary integer.

0x009

RW

Numerator (N) for Clock Generator 2 Register

Address: 0xF023, Reset: 0x0001, Name: CLK_GEN2_N

This register contains the numerator (N) for Clock Generator 2.

Table 71. Bit Descriptions for CLK_GEN2_N

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:9]

[8:0]

RESERVED

CLOCKGEN2_N

Clock Generator 2 N (numerator). Format is binary integer.

0x001

RW

Denominator (M) for Clock Generator 3 Register

Address: 0xF024, Reset: 0x0000, Name: CLK_GEN3_M

This register contains the denominator (M) for Clock Generator 3.

Table 72. Bit Descriptions for CLK_GEN3_M

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

CLOCKGEN3_M

Clock Generator 3 M (denominator). Format is binary integer.

0x0000 RW

Rev. A | Page 104 of 207

Data Sheet

ADAU1463/ADAU1467

Numerator for (N) Clock Generator 3 Register

Address: 0xF025, Reset: 0x0000, Name: CLK_GEN3_N

This register contains the numerator (N) for Clock Generator 3.

Table 73. Bit Descriptions for CLK_GEN3_N

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

CLOCKGEN3_N

Clock Generator 3 N (numerator). Format is binary integer.

0x0000 RW

Rev. A | Page 105 of 207

ADAU1463/ADAU1467

Data Sheet

Input Reference for Clock Generator 3 Register

Address: 0xF026, Reset: 0x000E, Name: CLK_GEN3_SRC

Clock Generator 3 can generate audio clocks using the PLL output (system clock) as a reference, or it can optionally use a reference clock

entering the device from an external source either on a multipurpose pin (MPx) or the S/PDIF receiver. This register determines the source of

the reference signal.

Rev. A | Page 106 of 207

Data Sheet

ADAU1463/ADAU1467

Table 74. Bit Descriptions for CLK_GEN3_SRC

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

CLK_GEN3_SRC

Reference source for Clock Generator 3. This bit selects the reference of

Clock Generator 3. If set to use an external reference clock, Bits[3:0] define

the source pin. Otherwise, the PLL output is used as the reference clock.

When an external reference clock is used for Clock Generator 3, the resulting

base output frequency of Clock Generator 3 is the frequency of the input

reference clock multiplied by the Clock Generator 3 numerator, divided by

1024. For example: if Bit 4 (CLK_GEN3_SRC) = 0b1 (an external reference

clock is used); Bits[3:0] (FREF_PIN) = 0b1110 (the input signal of the S/PDIF

receiver is used as the reference source); the sample rate of the S/PDIF input

signal = 48 kHz; and the numerator of Clock Generator 3 = 2048; the resulting

base output sample rate of Clock Generator 3 is 48 kHz × 2048/1024 = 96 kHz.

0x0

RW

0

1

Reference signal provided by PLL output; multiply the frequency of that

signal by N and divide it by M.

Reference signal provided by the signal input to the hardware pin defined

by Bits[3:0] (FREF_PIN); multiply the frequency of that signal by N (and

then divide by 1024) to get the resulting sample rate. M is ignored.

[3:0]

FREF_PIN

Input reference for Clock Generator 3. If Clock Generator 3 is set up to lock 0xE

to an external reference clock (Bit 4 (CLK_GEN3_SRC) = 0b1), these bits

allow the user to specify which pin is receiving the reference clock. The

signal input to the corresponding pin must be a 50% duty cycle square

wave clock representing the reference sample rate.

RW

0000 Input reference source is SS_M/MP0.

0001 Input reference source is MOSI_M/MP1.

0010 Input reference source is SCL_M/SCLK_M/MP2.

0011 Input reference source is SDA_M/MISO_M/MP3.

0100 Input reference source is LRCLK_OUT0/MP4.

0101 Input reference source is LRCLK_OUT1/MP5.

0110 Input reference source is MP6.

0111 Input reference source is MP7.

1000 Input reference source is LRCLK_OUT2/MP8.

1001 Input reference source is LRCLK_OUT3/MP9.

1010 Input reference source is LRCLK_IN0/MP10.

1011 Input reference source is LRCLK_IN1/MP11.

1100 Input reference source is LRCLK_IN2/MP12.

1101 Input reference source is LRCLK_IN3/MP13.

1110 Input reference source is S/PDIF receiver (recovered frame clock).

Rev. A | Page 107 of 207

ADAU1463/ADAU1467

Data Sheet

Lock Bit for Clock Generator 3 Input Reference Register

Address: 0xF027, Reset: 0x0000, Name: CLK_GEN3_LOCK

This register monitors whether or not Clock Generator 3 has locked to its reference clock source, regardless of whether it is coming from

the PLL output or from an external reference signal, which is configured in Register 0xF026, Bit 4 (CLK_GEN3_SRC).

Table 75. Bit Descriptions for CLK_GEN3_LOCK

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

GEN3_LOCK

Lock bit.

Not locked.

Locked.

0x0

R

0

1

Rev. A | Page 108 of 207

Data Sheet

ADAU1463/ADAU1467

POWER REDUCTION REGISTERS

Power Enable 0 Register

Address: 0xF050, Reset: 0x0000, Name: POWER_ENABLE0

For the purpose of power savings, this register allows the clock generators, ASRCs, and serial ports to be disabled when not in use. When

these functional blocks are disabled, the current draw on the corresponding supply pins decreases.

Table 76. Bit Descriptions for POWER_ENABLE0

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:13] RESERVED

12

CLK_GEN3_PWR

High precision clock generator (Clock Generator 3) power enable. When

this bit is disabled, Clock Generator 3 is disabled and ceases to output

audio clocks. Any functional block in hardware, including the DSP core,

that is configured to be clocked by Clock Generator 3 ceases to function

while this bit is disabled.

0x0

RW

0

1

Power disabled.

Power enabled.

11

CLK_GEN2_PWR

Clock Generator 2 power enable. When this bit is disabled, Clock Generator 2

is disabled and ceases to output audio clocks. Any LRCLK_OUTx, LRCLK_INx,

BCLK_OUTx, or BCLK_INx pin configured to output clocks generated by

Clock Generator 2 outputs a logic low signal while Clock Generator 2 is

disabled. Any functional block in hardware, including the DSP core, that is

configured to be clocked by Clock Generator 2 ceases to function while

this bit is disabled.

0x0

RW

0

1

Power disabled.

Power enabled.

Rev. A | Page 109 of 207

ADAU1463/ADAU1467

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

10

CLK_GEN1_PWR

Clock Generator 1 power enable. When this bit is disabled, Clock Generator 1

is disabled and ceases to output audio clocks. Any LRCLK_OUTx, LRCLK_INx,

BCLK_OUTx, or BCLK_INx pin configured to output clocks generated by

Clock Generator 1 outputs a logic low signal while Clock Generator 1 is

disabled. Any functional block in hardware, including the DSP core, that is

configured to be clocked by Clock Generator 1 ceases to function when this

bit is disabled.

0x0

RW

0

1

Power disabled.

Power enabled.

9

8

7

ASRCBANK1_PWR

ASRCBANK0_PWR

SOUT3_PWR

ASRC 4, ASRC 5, ASRC 6, ASRC 7 power enable. When this bit is disabled, ASRC 0x0

Channel 8 to Channel 15 are disabled, and their output data streams cease.

Power disabled.

Power enabled.

RW

0

1

ASRC 0, ASRC 1, ASRC 2, ASRC 3 power enable. When this bit is disabled, ASRC 0x0

Channel 0 to Channel 7 are disabled, and their output data streams cease.

Power disabled.

Power enabled.

0

1

SDATA_OUT3 power enable. When this bit is disabled, the SDATA_OUT3

pin and associated serial port circuitry are also disabled. LRCLK_OUT3 and

BCLK_OUT3 are not affected.

Power disabled.

Power enabled.

0x0

0

1

6

5

4

3

2

1

0

SOUT2_PWR

SOUT1_PWR

SOUT0_PWR

SIN3_PWR

SIN2_PWR

SIN1_PWR

SIN0_PWR

SDATA_OUT2 power enable. When this bit is disabled, the SDATA_OUT2 pin

and associated serial port circuitry is disabled. LRCLK_OUT2 and

BCLK_OUT2 are not affected.

Power disabled.

Power enabled.

RW

0

1

SDATA_OUT1 power enable. When this bit is disabled, the SDATA_OUT1 pin

and associated serial port circuitry are also disabled. LRCLK_OUT1 and

BCLK_OUT1 are not affected.

Power disabled.

Power enabled.

0

1

SDATA_OUT0 power enable. When this bit is disabled, the SDATA_OUT0 pin

and associated serial port circuitry are disabled. LRCLK_OUT0 and

BCLK_OUT0 are not affected.

Power disabled.

Power enabled.

0

1

SDATA_IN3 power enable. When this bit is disabled, the SDATA_IN3 pin

and associated serial port circuitry are disabled. LRCLK_IN3 and BCLK_IN3

are not affected.

Power disabled.

Power enabled.

0

1

SDATA_IN2 power enable. When this bit is disabled, the SDATA_IN2 pin

and associated serial port circuitry are disabled. LRCLK_IN2 and BCLK_IN2

are not affected.

Power disabled.

Power enabled.

0

1

SDATA_IN1 power enable. When this bit is disabled, the SDATA_IN1 pin

and associated serial port circuitry are disabled. The LRCLK_IN1 and

BCLK_IN1 pins are not affected.

Power disabled.

Power enabled.

0

1

SDATA_IN0 power enable. When this bit is disabled, the SDATA_IN0 pin

and associated serial port circuitry are disabled. The LRCLK_IN0 and

BCLK_IN0 pins are not affected.

0

1

Power disabled.

Power enabled.

Rev. A | Page 110 of 207

Data Sheet

ADAU1463/ADAU1467

Power Enable 1 Register

Address: 0xF051, Reset: 0x0000, Name: POWER_ENABLE1

For the purpose of power savings, this register allows the PDM microphone interfaces, S/PDIF interfaces, and auxiliary ADCs to be disabled

when not in use. When these functional blocks are disabled, the current draw on the corresponding supply pins decreases.

Table 77. Bit Descriptions for POWER_ENABLE1

Bits

[15:5]

4

Bit Name

RESERVED

PDM1_PWR

Settings

Description

Reset

0x0

Access

RW

PDM Microphone Channel 2 and PDM Microphone Channel 3 power enable.

When this bit is disabled, PDM Microphone Channel 2 and PDM Microphone

Channel 3 and their associated circuitry are disabled, and their data values

cease to update.

0x0

RW

0

1

Power disabled.

Power enabled.

3

PDM0_PWR

PDM Microphone Channel 0 and PDM Microphone Channel 1 power enable.

When this bit is disabled, PDM Microphone Channel 0 and PDM Microphone

Channel 1 and their associated circuitry are disabled, and their data values

cease to update.

0x0

RW

0

1

Power disabled.

Power enabled.

2

1

0

TX_PWR

RX_PWR

ADC_PWR

S/PDIF transmitter power enable. This bit disables the S/PDIF transmitter

circuit. Clock and data ceases to output from the S/PDIF transmitter pin,

and the output is held at logic low as long as this bit is disabled.

Power disabled.

Power enabled.

0x0

RW

0

1

S/PDIF receiver power enable. This bit disables the S/PDIF receiver circuit.

Clock and data recovery from the S/PDIF input stream ceases until this bit

is reenabled.

Power disabled.

Power enabled.

0

1

Auxiliary ADC power enable. When this bit is disabled, the auxiliary ADCs are

powered down, their outputs cease to update, and they hold their last value.

0

1

Power disabled.

Power enabled.

Rev. A | Page 111 of 207

ADAU1463/ADAU1467

Data Sheet

SLAVE CONTROL PORT MEMORY PAGE SETTING REGISTER

Address: 0xF899, Reset: 0x0000, Name: SECONDPAGE_ENABLE

Determines the memory page to which the slave control port addresses refer. When the PAGE bit is cleared, the slave control port

memory addresses refer to Page 1 of program Memory and data memory. When the PAGE bit is set, the slave control port memory

addresses refer to Page 2 of program Memory and data memory.

Table 78. Bit Descriptions for SECONDPAGE_ENABLE

Bits

[15:1]

0

Bit Name

RESERVED

PAGE

Settings

Description

Reset

0x0

Access

RW

Slave control port address page.

0x0

RW

0

1

Page 1.

Page 2.

Rev. A | Page 112 of 207

Data Sheet

ADAU1463/ADAU1467

AUDIO SIGNAL ROUTING REGISTERS

ASRC Input Selector Register

Address: 0xF100 to Address 0xF107 (Increments of 0x1), Reset: 0x0000, Name: ASRC_INPUTx

These eight registers configure the input signal to the corresponding eight stereo ASRCs on the ADAU1467 and ADAU1463.

ASRC_INPUT0 configures ASRC Channel 0 and ASRC Channel 1, ASRC_INPUT1 configures ASRC Channel 2 and ASRC Channel 3,

and so on. Valid input signals to the ASRCs include Serial Input Channel 0 to Serial Input Channel 47, the PDM Microphone Input

Channel 0 to PDM Microphone Input Channel 3, and the S/PDIF Receiver Channel 0 to S/PDIF Receiver Channel 1.

Rev. A | Page 113 of 207

ADAU1463/ADAU1467

Data Sheet

Table 79. Bit Descriptions for ASRC_INPUTx

Bits

[15:8] RESERVED

[7:3] ASRC_SIN_CHANNEL

Bit Name

Settings Description

Reset

0x0

Access

RW

If Bits[2:0] (ASRC_SOURCE) = 0b001, these bits select which serial input

0x00

RW

channel is routed to the ASRC.

00000 Serial Input Channel 0 and Serial Input Channel 1.

00001 Serial Input Channel 2 and Serial Input Channel 3.

00010 Serial Input Channel 4 and Serial Input Channel 5.

00011 Serial Input Channel 6 and Serial Input Channel 7.

00100 Serial Input Channel 8 and Serial Input Channel 9.

00101 Serial Input Channel 10 and Serial Input Channel 11.

00110 Serial Input Channel 12 and Serial Input Channel 13.

00111 Serial Input Channel 14 and Serial Input Channel 15.

01000 Serial Input Channel 16 and Serial Input Channel 17.

01001 Serial Input Channel 18 and Serial Input Channel 19.

01010 Serial Input Channel 20 and Serial Input Channel 21.

01011 Serial Input Channel 22 and Serial Input Channel 23.

01100 Serial Input Channel 24 and Serial Input Channel 25.

01101 Serial Input Channel 26 and Serial Input Channel 27.

01110 Serial Input Channel 28 and Serial Input Channel 29.

01111 Serial Input Channel 30 and Serial Input Channel 31.

10000 Serial Input Channel 32 and Serial Input Channel 33.

10001 Serial Input Channel 34 and Serial Input Channel 35.

10010 Serial Input Channel 36 and Serial Input Channel 37.

10011 Serial Input Channel 38 and Serial Input Channel 39.

10100 Serial Input Channel 40 and Serial Input Channel 41.

10101 Serial Input Channel 42 and Serial Input Channel 43.

10110 Serial Input Channel 44 and Serial Input Channel 45.

10111 Serial Input Channel 46 and Serial Input Channel 47.

ASRC source select.

[2:0]

ASRC_SOURCE

0x0

RW

000 Not used.

001 From serial input ports; select channels using Bits[7:3] (ASRC_SIN_CHANNEL).

010 From DSP core outputs.

011 From S/PDIF receiver.

100 From digital PDM Microphone Input Channel 0 and PDM Microphone Input

Channel 1.

101 From digital PDM Microphone Input Channel 2 and PDM Microphone Input

Channel 3.

Rev. A | Page 114 of 207

Data Sheet

ADAU1463/ADAU1467

ASRC Output Rate Selector Register

Address: 0xF140 to Address 0xF147 (Increments of 0x1), Reset: 0x0000, Name: ASRC_OUT_RATEx

These eight registers configure the target output sample rates of the corresponding eight stereo ASRCs on the ADAU1463 and ADAU1467

The ASRC takes any arbitrary input sample rate and automatically attempts to resample the data in that signal and output it at the target

sample rate as configured by these registers. Each of the eight registers corresponds to one of the eight stereo ASRCs, as listed in Table 80. The

ASRCs lock their output frequencies to the audio sample rates of any of the serial output ports, the DSP start pulse rate of the core, or one

of several internally generated sample rates coming from the clock generators.

Table 80. ASRC Channel Configuration

Register

Configures ASRC Channel

Channel 0 and Channel 1

Channel 2 and Channel 3

Channel 4 and Channel 5

Channel 6 and Channel 7

Channel 8 and Channel 9

Channel 10 and Channel 11

Channel 12 and Channel 13

Channel 14 and Channel 15

ASRC_OUT_RATE0

ASRC_OUT_RATE1

ASRC_OUT_RATE2

ASRC_OUT_RATE3

ASRC_OUT_RATE4

ASRC_OUT_RATE5

ASRC_OUT_RATE6

ASRC_OUT_RATE7

Rev. A | Page 115 of 207

ADAU1463/ADAU1467

Data Sheet

Table 81. Bit Descriptions for ASRC_OUT_RATEx

Bits

[15:4] RESERVED

[3:0] ASRC_RATE

Bit Name

Settings

Description

Reset

Access

RW

0x0

ASRC target audio output sample rate. The corresponding ASRC can lock its output 0x0

to a serial output port, the DSP core, or an internally generated rate.

RW

0000 No output rate selected.

0001 Use sample rate of SDATA_OUT0 (Register 0xF211 (SERIAL_BYTE_4_1), Bits[4:0]).

0010 Use sample rate of SDATA_OUT1 (Register 0xF215 (SERIAL_BYTE_5_1), Bits[4:0]).

0011 Use sample rate of SDATA_OUT2 (Register 0xF219 (SERIAL_BYTE_6_1), Bits[4:0]).

0100 Use sample rate of SDATA_OUT3 (Register 0xF21D (SERIAL_BYTE_7_1), Bits[4:0]).

0101 Use DSP core audio sampling rate (Register 0xF401 (START_PULSE), Bits[4:0]).

Rev. A | Page 116 of 207

Data Sheet

ADAU1463/ADAU1467

Bits

Bit Name

Settings

Description

Reset

Access

0110 Internal rate (the base output rate of Clock Generator 1); see Register 0xF020

(CLK_GEN1_M) and Register 0xF021 (CLK_GEN1_N).

0111 Internal rate × 2 (the doubled output rate of Clock Generator 1); see Register 0xF020

(CLK_GEN1_M) and Register 0xF021 (CLK_GEN1_N).

1000 Internal rate × 4 (the quadrupled output rate of Clock Generator 1); see Register 0xF020

(CLK_GEN1_M) and Register 0xF021 (CLK_GEN1_N).

1001 Internal rate × (1/2) the halved output rate of Clock Generator 1); see Register 0xF020

(CLK_GEN1_M) and Register 0xF021 (CLK_GEN1_N).

1010 Internal rate × (1/3) (one-third output of Clock Generator 2); see Register 0xF022

(CLK_GEN2_M) and Register 0xF023 (CLK_GEN2_N).

1011 Internal rate × (1/4) (quartered output of Clock Generator 1); see Register 0xF020

(CLK_GEN1_M) and Register 0xF021 (CLK_GEN1_N).

1100 Internal rate × (1/6) (one-sixth output of Clock Generator 2); see Register 0xF022

(CLK_GEN2_M) and Register 0xF023 (CLK_GEN2_N).

Rev. A | Page 117 of 207

ADAU1463/ADAU1467

Data Sheet

Source of Data for Serial Output Ports Register

Address: 0xF180 to 0xF197 (Increments of 0x1), Reset: 0x0000, Name: SOUT_SOURCEx

These 24 registers correspond to the 24 pairs of output channels used by the serial output ports. Each register corresponds to two audio channels.

SOUT_SOURCE0 corresponds to Channel 0 and Channel 1, SOUT_SOURCE1 corresponds to Channel 2 and Channel 3, and so on.

SOUT_SOURCE0 to SOUT_SOURCE7 map to the 16 total channels (Channel 0 to Channel 15) that are fed to SDATA_OUT0.

SOUT_SOURCE8 to SOUT_SOURCE15 map to the 16 total channels (Channel 16 to Channel 31) that are fed to SDATA_OUT1.

SOUT_SOURCE16 to SOUT_SOURCE19 map to the eight total channels (Channel 32 to Channel 39) that are fed to SDATA_OUT2.

SOUT_SOURCE20 to SOUT_SOURCE23 map to the eight total channels (Channel 40 to Channel 47) that are fed to SDATA_OUT3.

Data originates from several places, including directly from the corresponding input audio channels from the serial input ports, from the

corresponding audio output channels of the DSP core, from an ASRC output pair, or directly from the PDM microphone inputs.

Table 82. Bit Descriptions for SOUT_SOURCEx

Bits

[15:6] RESERVED

[5:3] SOUT_ASRC_SELECT

Bit Name

Settings

Description

Reset

0x000 RW

0x0 RW

Access

ASRC output channels. If Bits[2:0] (SOUT_SOURCE) are set to 0b011, these bits

select which ASRC channels are routed to the serial output channels.

000 ASRC 0 (Channel 0 and Channel 1).

001 ASRC 1 (Channel 2 and Channel 3).

010 ASRC 2 (Channel 4 and Channel 5).

011 ASRC 3 (Channel 6 and Channel 7).

100 ASRC 4 (Channel 8 and Channel 9).

101 ASRC 5 (Channel 10 and Channel 11).

110 ASRC 6 (Channel 12 and Channel 13).

111 ASRC 7 (Channel 14 and Channel 15).

Rev. A | Page 118 of 207

Data Sheet

ADAU1463/ADAU1467

Bits

Bit Name

Settings

Description

Reset

Access

[2:0]

SOUT_SOURCE

Audio data source for these serial audio output channels. If these bits are set to 0x0

0b001, the corresponding output channels output a copy of the data from the

corresponding input channels. For example, if Address 0xF180, Bits[2:0] are set

to 0b001, Serial Input Channel 0 and Serial Input Channel 1 copy to Serial Out-

put Channel 0 and Serial Output Channel 1, respectively. If these bits are set to

0b010, DSP Output Channel 0 and DSP Output Channel 1 copy to Serial Out-

put Channel 0 and Serial Output Channel 1, respectively. If these bits are set to

0b011, Bits[5:3] (SOUT_ASRC_SELECT) must be configured to select the

desired ASRC output.

RW

000 Disabled; these output channels are not used.

001 Direct copy of data from corresponding serial input channels.

010 Data from corresponding DSP core output channels.

011 From ASRC (select channel using Bits[5:3], SOUT_ASRC_SELECT) .

100 Digital PDM Microphone Input Channel 0 and Digital PDM Microphone

Input Channel 1.

101 Digital PDM Microphone Input Channel 2 and Digital PDM Microphone

Input Channel 3.

S/PDIF Transmitter Data Selector Register

Address: 0xF1C0, Reset: 0x0000, Name: SPDIFTX_INPUT

This register configures which data source feeds the S/PDIF transmitter on the ADAU1463 and ADAU1467. Data can originate from the

S/PDIF outputs of the DSP core or directly from the S/PDIF receiver.

Table 83. Bit Descriptions for SPDIFTX_INPUT

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:2]

[1:0]

RESERVED

SPDIFTX_SOURCE

S/PDIF transmitter source.

0x0

RW

00 Disables S/PDIF transmitter.

01 Data originates from S/PDIF Output Channel 0 and S/PDIF Output Channel 1

of the DSP core, as configured in the DSP program.

10 Data copied directly from S/PDIF Receiver Channel 0 and S/PDIF Receiver

Channel 1 to S/PDIF Transmitter Channel 0 and S/PDIF Transmitter Channel 1,

respectively.

Rev. A | Page 119 of 207

ADAU1463/ADAU1467

Data Sheet

SERIAL PORT CONFIGURATION REGISTERS

Serial Port Control 0 Register

Address: 0xF200 to 0xF21C (Increments of 0x4), Reset: 0x0000, Name: SERIAL_BYTE_x_0

These eight registers configure several settings for the corresponding serial input and serial output ports. Channel count, MSB position,

data-word length, clock polarity, clock sources, and clock type are configured using these registers. On the input side, Register 0xF200

(SERIAL_BYTE_0_0) corresponds to SDATA_IN0; Register 0xF204 (SERIAL_BYTE_1_0) corresponds to SDATA_IN1; Register 0xF208

(SERIAL_BYTE_2_0) corresponds to SDATA_IN2; and Register 0xF20C (SERIAL_BYTE_3_0) corresponds to SDATA_IN3. On the output

side, Register 0xF210 (SERIAL_BYTE_4_0) corresponds to SDATA_OUT0; Register 0xF214 (SERIAL_BYTE_5_0) corresponds to

SDATA_OUT1; Register 0xF218 (SERIAL_BYTE_6_0) corresponds to SDATA_OUT2; and Register 0xF21C (SERIAL_BYTE_7_0)

corresponds to SDATA_OUT3.

Rev. A | Page 120 of 207

Data Sheet

ADAU1463/ADAU1467

Table 84. Bit Descriptions for SERIAL_BYTE_x_0

Bits

Bit Name

Settings

Description

Reset

Access

[15:13] LRCLK_SRC

LRCLK pin selection. These bits configure whether the corresponding

serial port is a frame clock master or slave. When configured as a master,

the corresponding LRCLK pin (LRCLK_INx for SDATA_INx pins and

LRCLK_OUTx for SDATA_OUTx pins) with the same number as the serial

port (for example, LRCLK_OUT0 for SDATA_OUT0) actively drives out a

clock signal. When configured as a slave, the serial port can receive its

clock signal from any of the four corresponding LRCLK pins (LRCLK_INx

pins for SDATA_INx pins or LRCLK_OUTx pins for SDATA_OUTx pins).

0x0

RW

000 Slave from LRCLK_IN0 or LRCLK_OUT0.

001 Slave from LRCLK_IN1 or LRCLK_OUT1.

010 Slave from LRCLK_IN2 or LRCLK_OUT2.

011 Slave from LRCLK_IN3 or LRCLK_OUT3.

100 Master mode; corresponding LRCLK pin actively outputs a clock signal.

[12:10] BCLK_SRC

BCLK pin selection. These bits configure whether the corresponding serial

port is a bit clock master or slave. When configured as a master, the

corresponding BCLK pin (BCLK_INx for SDATA_INx pins and BCLK_OUTx

for SDATA_OUTx pins) with the same number as the serial port (for example,

BCLK_OUT0 for SDATA_OUT0) actively drives out a clock signal. When

configured as a slave, the serial port can receive its clock signal from any

of the four corresponding BCLK pins (BCLK_INx pins for SDATA_INx pins or

BCLK_OUTx pins for SDATA_OUTx pins).

0x0

RW

000 Slave from BCLK_IN0 or BCLK_OUT0.

001 Slave from BCLK_IN1 or BCLK_OUT1.

010 Slave from BCLK_IN2 or BCLK_OUT2.

011 Slave from BCLK_IN3 or BCLK_OUT3.

100 Master mode; corresponding BCLK pin actively outputs a clock signal.

9

8

LRCLK_MODE

LRCLK_POL

LRCLK waveform type. The frame clock can be a 50/50 duty cycle square

wave or a short pulse.

50% duty cycle clock (square wave).

0x0

RW

0

1

Pulse with a width equal to one bit clock cycle.

LRCLK polarity. This bit sets the frame clock polarity on the corresponding

serial port. Negative polarity means that the frame starts on the falling

edge of the frame clock. This conforms to the I²S standard audio format.

0

1

Negative polarity; frame starts on falling edge of frame clock.

Positive polarity; frame starts on rising edge of frame clock.

7

BCLK_POL

BCLK polarity. This bit sets the bit clock polarity on the corresponding

serial port. Negative polarity means that the data signal transitions on the

falling edge of the bit clock. This conforms to the I²S standard audio format.

Negative polarity; data transitions on falling edge of bit clock.

Positive polarity; data transitions on rising edge of bit clock.

0x0

RW

0

1

[6:5]

WORD_LEN

Audio data-word length. These bits set the word length of the audio data

channels on the corresponding serial port. For serial input ports, if the

input data has more words than the length as configured by these bits,

the extra data bits are ignored. For output serial ports, if the word length,

as configured by these bits, is shorter than the data length coming from

the data source (the DSP, ASRCs, S/PDIF receiver, PDM inputs, or serial

inputs), the extra data bits are truncated and output as 0s. If Bits[6:5]

(WORD_LEN) are set to 0b10 for 32-bit mode, the corresponding 32-bit

input or output cells are required in SigmaStudio.

00 24 bits.

01 16 bits.

10 32 bits.

11 Flexible TDM mode (configure using Register 0xF300 to Register 0xF33F,

FTDM_INx, and Register 0xF380 to Register 0xF3BF, FTDM_OUTx).

Rev. A | Page 121 of 207

ADAU1463/ADAU1467

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

[4:3]

DATA_FMT

MSB position. These bits set the positioning of the data in the frame on

the corresponding serial port.

00 I²S (delay data by one BCLK cycle).

0x0

RW

01 Left justified (delay data by zero BCLK cycles).

10 Right justified for 24-bit data (delay data by 8 BCLK cycles).

11 Right justified for 16-bit data (delay data by 16 BCLK cycles).

[2:0]

TDM_MODE

Channels per frame and BCLK cycles per channel. These bits set the number

of channels per frame and the number of bit clock cycles per frame on the

corresponding serial port.

0x0

RW

000 2 channels, 32 bit clock cycles per channel, 64 bit clock cycles per frame.

001 4 channels, 32 bit clock cycles per channel, 128 bit clock cycles per frame.

010 8 channels, 32 bit clock cycles per channel, 256 bit clock cycles per frame.

011 16 channels, 32 bit clock cycles per channel, 512 bit clock cycles per frame.

100 4 channels, 16 bit clock cycles per channel, 64 bit clock cycles per frame.

101 2 channels, 16 bit clock cycles per channel, 32 bit clock cycles per frame.

Serial Port Control 1 Register

Address: 0xF201 to 0xF21D (Increments of 0x4), Reset: 0x0002, Name: SERIAL_BYTE_x_1

These eight registers configure several settings for the corresponding serial input and serial output ports. Clock generator, sample rate,

and behavior during inactive channels are configured with these registers. On the input side, Register 0xF201 (SERIAL_BYTE_0_1)

corresponds to SDATA_IN0; Register 0xF205 (SERIAL_BYTE_1_1) corresponds to SDATA_IN1; Register 0xF209 (SERIAL_BYTE_2_1)

corresponds to SDATA_IN2; and Register 0xF20D (SERIAL_BYTE_3_1) corresponds to SDATA_IN3. On the output side, Register 0xF211

(SERIAL_BYTE_4_1) corresponds to SDATA_OUT0; Register 0xF215 (SERIAL_BYTE_5_1) corresponds to SDATA_OUT1; Register 0xF219

(SERIAL_BYTE_6_1) corresponds to SDATA_OUT2; and Register 0xF21D (SERIAL_BYTE_7_1) corresponds to SDATA_OUT3.

Table 85. Bit Descriptions for SERIAL_BYTE_x_1

Bits

[15:6]

5

Bit Name

RESERVED

TRISTATE

Settings

Description

Reset

0x000

0x0

Access

RW

Tristate unused output channels. This bit has no effect on serial input ports.

RW

1

0

The corresponding serial data output pin is high impedance during

unused output channels.

Drive every output channel.

Rev. A | Page 122 of 207

Data Sheet

ADAU1463/ADAU1467

Bits

Bit Name

Settings

Description

Reset

Access

[4:3]

CLK_DOMAIN

Selects the clock generator to use for the serial port. These bits select the

clock generator to use for this serial port when it is configured as a clock

master. This setting is valid only when Bits[15:13] (LRCLK_SRC) of the

corresponding SERIAL_BYTE_x_0 register are set to 0b100 (master mode)

and Bits[12:10] (BCLK_SRC) are set to 0b100 (master mode).

0x0

RW

00 Clock Generator 1.

01 Clock Generator 2.

10 Clock Generator 3 (high precision clock generator).

[2:0]

FS

Sample rate. These bits set the sample rate to use for the serial port when

it is configured as a clock master. This setting is valid only when Bits[15:13]

(LRCLK_SRC) of the corresponding SERIAL_BYTE_x_0 register are set to

0b100 (master mode) and Bits[12:10] BCLK_SRC are set to 0b100 (master

mode). Bits[4:3] (CLK_DOMAIN) select which clock generator to use, and

Bits[2:0] (FS) select which of the five clock generator outputs to use.

0x2

RW

000 Quarter rate of selected clock generator.

001 Half rate of selected clock generator.

010 Base rate of selected clock generator.

011 Double rate of selected clock generator.

100 Quadruple rate of selected clock generator.

SDATA PORT ROUTING REGISTER

Address: 0xF240 to Address 0xF247 (Increments of 0x1), Reset: 0x0000, Name: SDATA_x_ROUTE

These eight registers configure the functionality of the eight SDATAIOx pins. The value determines whether the pin is used for serial data

or as a multipurpose pin, with which serial input or output port it is associated, and the data channels associated with the port.

Table 86. Bit Descriptions for SDATA_n_ROUTE

Bits

[15:6]

5

Bit Name

RESERVED

ENBL

Settings

Description

Reset

0x000

0x0

Access

RW

Reserved.

Pin routing enable.

Disable pin routing.

Enable pin routing.

Pin routing direction.

From pin to serial input.

From serial output to pin.

Pin serial port select.

RW

0

1

4

DIR

0x0

RW

0

1

[3:2]

PORT_SEL

Rev. A | Page 123 of 207

ADAU1463/ADAU1467

Data Sheet

Bits

Bit Name

Settings

Description

00 Port 0.

Reset

Access

01 Port 1.

10 Port 2.

11 Port 3.

[1:0]

CHAN

For Serial Port 0 in 2-channel mode:

00 Channel 7 to Channel 4.

01 Channel 11 to Channel 8.

10 Channel 15 to Channel 12.

For Serial Port 0 in TDM mode:

0x00

RW

00 Channel 7 to Channel 4 (TDM-4).

01 Channel 11 to Channel 8 (TDM-4).

10 Channel 15 to Channel 12 (TDM-4).

11 Channel 15 to Channel 8 (TDM-8).

For Serial Port 1 in 2-channel mode:

00 Channel 7 and Channel 6.

01 Channel 11 and Channel 10.

10 Channel 15 and Channel 14.

For Serial Port 1 in TDM mode:

0x00

00 Channel 23 to Channel 20 (TDM-4).

01 Channel 27 to Channel 24 (TDM-4).

10 Channel 31 to Channel 28 (TDM-4).

11 Channel 31 to Channel 27 (TDM-8).

For Serial Port 2 in 2-channel mode:

00 Channel 35 and Channel 34.

For Serial Port 2 in TDM4 mode:

00 Channel 39 to Channel 36.

For Serial Port 3 in 2-channel mode:

00 Channel 47 to Channel 46.

For Serial Port 3 in TDM4 mode:

0x00

00 Channel 47 to Channel 44.

0x00

Rev. A | Page 124 of 207

Data Sheet

ADAU1463/ADAU1467

FLEXIBLE TDM INTERFACE REGISTERS

FTDM Mapping for the Serial Inputs Register

Address: 0xF300 to 0xF33F (Increments of 0x1), Reset: 0x0000, Name: FTDM_INx

These 64 registers correspond to the 64 bytes of data that combine to form the 16 audio channels derived from the data streams being

input to the SDATA_IN2 and SDATA_IN3 pins.

Table 87. Bit Descriptions for FTDM_INx

Bits

[15:8]

7

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

SLOT_ENABLE_IN

Selected byte is used. This bit determines whether or not the slot is

active. If active, valid data is input from the corresponding data slot on

the selected channel of the selected input pin. If disabled, input data

from the corresponding data slot on the selected channel of the selected

input pin is ignored.

0x0

RW

0

1

Disable byte.

Enable byte.

6

5

REVERSE_IN_BYTE

SERIAL_IN_SEL

Reverses the bits in the byte. This bit changes the endianness of the data bits

within the byte by optionally reversing the order of the bits from MSB to LSB.

Do not reverse bits (big endian).

Reverse bits (little endian).

0x0

RW

0

1

Serial port source (SDATA_IN2 or SDATA_IN3). If this bit = 0b0, the slot is

mapped to Audio Channel 32 to Audio Channel 39. If this bit = 0b1, the

slot is mapped to Audio Channel 40 to Audio Channel 47. The exact

channel assignment is determined by Bits[4:2] (CHANNEL_IN_POS).

0

1

Select data from the flexible TDM stream on the SDATA_IN2 pin.

Select data from the flexible TDM stream on the SDATA_IN3 pin.

Rev. A | Page 125 of 207

ADAU1463/ADAU1467

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

[4:2]

CHANNEL_IN_POS

Source channel selector. These bits map the slot to an audio input

channel. If Bit 5 (SERIAL_IN_SEL) = 0b0, Position 0 maps to Channel 32,

Position 1 maps to Channel 33, and so on. If Bit 5 (SERIAL_IN_SEL) = 0b1,

Position 0 maps to Channel 40, Position 1 maps to Channel 41, and so on.

0x0

RW

000 Channel 0 (in the TDM8 stream).

001 Channel 1 (in the TDM8 stream).

010 Channel 2 (in the TDM8 stream).

011 Channel 3 (in the TDM8 stream).

100 Channel 4 (in the TDM8 stream).

101 Channel 5 (in the TDM8 stream).

110 Channel 6 (in the TDM8 stream).

111 Channel 7 (in the TDM8 stream).

[1:0]

BYTE_IN_POS

Byte selector for source channel. These bits determine which byte the

slot fills in the channel selected by Bit 5 (SERIAL_IN_SEL) and Bits[4:2]

(CHANNEL_IN_POS). Each channel consists of four bytes that are selectable

by the four options available in this bit field.

0x0

RW

00 Byte 0; Bits[31:24].

01 Byte 1; Bits[23:16].

10 Byte 2; Bits[15:8].

11 Byte 3; Bits[7:0].

FTDM Mapping for the Serial Outputs Register

Address: 0xF380 to 0xF3BF (Increments of 0x1), Reset: 0x0000, Name: FTDM_OUTx

These 64 registers correspond to the 64 data slots for the flexible TDM output modes on the SDATA_OUT2 and SDATA_OUT3 pins. Slot 0

to Slot 31 are available for use on SDATA_OUT2, and Slot 32 to Slot 63 are available for use on SDATA_OUT3. Each slot can potentially

hold one byte of data. Slots are mapped to corresponding audio channels in the serial ports by Bits[5:0] in these registers.

Rev. A | Page 126 of 207

Data Sheet

ADAU1463/ADAU1467

Table 88. Bit Descriptions for FTDM_OUTx

Bits

[15:8]

7

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

SLOT_ENABLE_OUT

Selected byte is used. This bit determines whether or not the slot is active. If

Bit 7 (SLOT_ENABLE_OUT) = 0b0 and Bit 5 (TRISTATE) of the corresponding

serial output port = 0b1, the corresponding output pin is high impedance

during the period in which the corresponding flexible TDM slot is output. If

Bit 7 (SLOT_ENABLE_OUT) = 0b0, and Bit 5 (TRISTATE) of the corresponding

serial output port = 0b0, the corre-sponding output pin drives logic low

during the period in which the corresponding flexible TDM slot is output.

If Bit 7 (SLOT_ENABLE_OUT) = 0b1, the corresponding serial output pin

outputs valid data during the period in which the corresponding flexible

TDM slot is output.

0x0

RW

0

1

Disable byte.

Enable byte.

6

REVERSE_OUT_BYTE

SERIAL_OUT_SEL

Reverses the bits in the byte. This bit changes the endianness of the data

bits within the corresponding flexible TDM slot by optionally reversing

the order of the bits from MSB to LSB.

Do not reverse byte (big endian).

Reverse byte (little endian).

0x0

RW

0

1

5

Serial port source. This bit, together with Bits[4:2] (CHANNEL_OUT_POS), 0x0

selects which serial output channel is the source of data for the

corresponding flexible TDM output slot.

0

1

Serial Output Channel 32 to Serial Output Channel 39.

Serial Output Channel 40 to Serial Output Channel 47.

[4:2]

CHANNEL_OUT_POS

Source channel for the FTDM byte. These bits, along with Bit 5 (SERIAL_OUT_ 0x0

SEL), select which serial output channel is the source of data for the

corresponding flexible TDM output slot. If Bit 5 (SERIAL_OUT_SEL) = 0b0,

Bits[4:2] (CHANNEL_OUT_POS) select serial output channels between Serial

Output Channel 32 and Serial Output Channel 39. If Bit 5 (SERIAL_OUT_

SEL) = 0b1, Bits[4:2] (CHANNEL_OUT_POS) selects serial output channels

between Serial Output Channel 40 and Serial Output Channel 47.

000 Serial Output Channel 32 or Serial Output Channel 40.

001 Serial Output Channel 33 or Serial Output Channel 41.

010 Serial Output Channel 34 or Serial Output Channel 42.

011 Serial Output Channel 35 or Serial Output Channel 43.

100 Serial Output Channel 36 or Serial Output Channel 44.

101 Serial Output Channel 37 or Serial Output Channel 45.

110 Serial Output Channel 38 or Serial Output Channel 46.

111 Serial Output Channel 39 or Serial Output Channel 47.

[1:0]

BYTE_OUT_POS

Byte position from the source channel for the FTDM byte. These bits

determine which data byte is used from the corresponding serial output

channel (selected by setting Bit 5 (SERIAL_OUT_SEL) and Bits[4:2]

(CHANNEL_OUT_POS)). Because there can be up to 32 bits in the data-

word, four bytes are available.

0x0

RW

00 Byte 0; Bits[31:24].

01 Byte 1; Bits[23:16].

10 Byte 2; Bits[15:8].

11 Byte 3; Bits[7:0].

Rev. A | Page 127 of 207

ADAU1463/ADAU1467

Data Sheet

DSP CORE CONTROL REGISTERS

Hibernate Setting Register

Address: 0xF400, Reset: 0x0000, Name: HIBERNATE

When hibernation mode is activated, the DSP core continues processing the current audio sample or block, and then enters a low power

hibernation state. If Bit 0 (HIBERNATE) is set to 0b1 when the DSP core is processing audio, wait at least the duration of one sample before

attempting to modify any other control registers. If Bit 0 (HIBERNATE) is set to 0b1 when the DSP core is processing audio, and block

processing is used in the signal flow, wait at least the duration of one block plus the duration of one sample before attempting to modify

any other control registers. During hibernation, interrupts to the core are disabled. This prevents audio from flowing into or out of the DSP core.

Because DSP processing ceases when hibernation is active, there is a significant drop in the current consumption on the DVDD supply.

Table 89. Bit Descriptions for Hibernate

Bits

[15:1]

0

Bit Name

RESERVED

HIBERNATE

Settings

Description

Reset

Access

RW

0x0

Enter hibernation mode. This bit disables incoming interrupts and tells the 0x0

DSP core to go to a low power sleep mode after the next audio sample or

block finishes processing. It causes the DSP to enter hibernation mode by

masking all interrupts.

RW

0

1

Not hibernating; interrupts enabled.

Enter hibernation; interrupts disabled.

Rev. A | Page 128 of 207

Data Sheet

ADAU1463/ADAU1467

Start Pulse Selection Register

Address: 0xF401, Reset: 0x0002, Name: START_PULSE

This register selects the start pulse that marks the beginning of each audio frame in the DSP core. This effectively sets the sample rate of

the audio going through the DSP. This start pulse can originate from either an internally generated pulse (from Clock Generator 1 or

Clock Generator 2) or from an external clock that is received on one of the LRCLK pins of one of the serial ports. Any audio input or

output from the DSP core that is asynchronous to this DSP start pulse rate must go through an ASRC. If asynchronous audio signals (that

is, signals that are not synchronized to whatever start pulse is selected) are input to the DSP without first going through an ASRC, samples

are skipped or doubled, leading to distortion and audible artifacts in the audio signal.

Rev. A | Page 129 of 207

ADAU1463/ADAU1467

Data Sheet

Table 90. Bit Descriptions for START_PULSE

Bits

[15:5] RESERVED

[4:0] START_PULSE

Bit Name

Settings Description

Reset Access

0x0

RW

Start pulse selection.

0x02

00000 Base sample rate ÷ 4 (12 kHz for 48 kHz base sample rate) (1/4 output of Clock

Generator 1).

00001 Base sample rate ÷ 2 (24 kHz for 48 kHz base sample rate) (1/2 output of Clock

Generator 1).

00010 Base sample rate (48 kHz for 48 kHz base sample rate) (×1 output of Clock Generator 1).

00011 Base sample rate × 2 (96 kHz for 48 kHz base sample rate) (×2 output of Clock Generator 1).

00100 Base sample rate × 4 (192 kHz for 48 kHz base sample rate) (×4 output of Clock

Generator 1).

00101 Base sample rate ÷ 6 (8 kHz for 48 kHz base sample rate) (1/4 output of Clock Generator 2)

00110 Base sample rate ÷ 3 (16 kHz for 48 kHz base sample rate) (1/2 output of Clock Generator 2)

00111 2× base sample rate ÷ 3 (32 kHz for 48 kHz base sample rate) (×1 output of Clock

Generator 2).

01000 Serial Input Port 0 sample rate (Register 0xF201 (SERIAL_BYTE_0_1), Bits[4:0]).

01001 Serial Input Port 1 sample rate (Register 0xF205 (SERIAL_BYTE_1_1), Bits[4:0]).

01010 Serial Input Port 2 sample rate (Register 0xF209 (SERIAL_BYTE_2_1), Bits[4:0]).

01011 Serial Input Port 3 sample rate (Register 0xF20D (SERIAL_BYTE_3_1), Bits[4:0]).

01100 Serial Output Port 0 sample rate (Register 0xF211 (SERIAL_BYTE_4_1), Bits[4:0]).

01101 Serial Output Port 1 sample rate (Register 0xF215 (SERIAL_BYTE_5_1), Bits[4:0]).

01110 Serial Output Port 2 sample rate (Register 0xF219 (SERIAL_BYTE_6_1), Bits[4:0]).

01111 Serial Output Port 3 sample rate (Register 0xF21D (SERIAL_BYTE_7_1), Bits[4:0]).

10000 S/PDIF receiver sample rate (derived from the S/PDIF input stream).

Instruction to Start the Core Register

Address: 0xF402, Reset: 0x0000, Name: START_CORE

Enables the DSP core and initiates the program counter, which then begins incrementing through the program memory and executing

instruction codes. This register is edge triggered, meaning that a rising edge on Bit 0 (START_CORE), that is, a transition from 0b0 to 0b1,

initiates the program counter. A falling edge on Bit 0 (START_CORE), that is, a transition from 0b1 to 0b0, has no effect. To stop the DSP

core, use Register 0xF400 (HIBERNATE), Bit 0 (HIBERNATE).

Table 91. Bit Descriptions for START_CORE

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

START_CORE

Start DSP core. A transition of this bit from 0b0 to 0b1 enables the DSP core to

start executing its program. A transition from 0b1 to 0b0 does not affect the DSP

core.

0x0

RW

0

1

A transition from 0b0 to 0b1 enables the DSP core to start program execution.

A transition from 0b1 to 0b0 does not affect the DSP core.

Rev. A | Page 130 of 207

Data Sheet

ADAU1463/ADAU1467

Instruction to Stop the Core Register

Address: 0xF403, Reset: 0x0000, Name: KILL_CORE

Bit 0 (KILL_CORE) halts the DSP core immediately, even when it is in an undefined state. Because halting the DSP core immediately can

lead to memory corruption, and it must be used only in debugging situations. This register is edge triggered, meaning that a rising edge

on Bit 0 (KILL_CORE), that is, a transition from 0b0 to 0b1, halts the core. A falling edge on Bit 0 (KILL_CORE), that is, a transition

from 0b1 to 0b0, has no effect. To stop the DSP core after the next audio frame or block, use Register 0xF400 (HIBERNATE), Bit 0

(HIBERNATE).

Table 92. Bit Descriptions for KILL_CORE

Bits

[15:1]

0

Bit Name

RESERVED

KILL_CORE

Settings

Description

Reset

0x0

Access

RW

Immediately halts the core. When this bit transitions from 0b0 to 0b1, the

core immediately halts. This can bring about undesired effects and, therefore,

must be used only in debugging. To stop the core while it is running, use

Register 0xF400 (HIBERNATE) to halt the core in a controlled manner.

0x0

RW

0

1

A transition from 0b0 to 0b1 immediately halts the core.

A transition from 0b1 to 0b0 has no effect.

Start Address of the Program Register

Address: 0xF404, Reset: 0x0000, Name: START_ADDRESS

This register sets the program address where the program counter begins after the DSP core is enabled, using Register 0xF402, Bit 0

(START_CORE). The SigmaStudio compiler automatically sets the program start address; therefore, the user is not required to manually

modify the value of this register.

Table 93. Bit Descriptions for START_ADDRESS

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

START_ADDRESS

Program start address.

0x0000 RW

Rev. A | Page 131 of 207

ADAU1463/ADAU1467

Data Sheet

Core Status Register

Address: 0xF405, Reset: 0x0000, Name: CORE_STATUS

This read only register allows the user to check the status of the DSP core. To manually modify the core status, use Register 0xF400

(HIBERNATE), Register 0xF402 (START_CORE), and Register 0xF403 (KILL_CORE).

Table 94. Bit Descriptions for CORE_STATUS

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:3]

[2:0]

RESERVED

CORE_STATUS

DSP core status. These bits display the status of the DSP core at the

moment the value is read.

0x0

RW

000 Core is not running. This is the default state when the device boots. When

the core is manually stopped using Register 0xF403 (KILL_CORE), the core

returns to this state.

001 Core is running normally.

010 Core is paused. The clock signal is cut off from the core, preserving its state

until the clock resumes. This state occurs only if a pause instruction is

explicitly defined in the DSP program.

011 Core is in sleep mode (the core may be actively running a program, but it

finishes executing instructions and waits in an idle state for the next audio

sample to arrive). This state occurs only if a sleep instruction is explicitly

called in the DSP program.

100 Core is stalled. This occurs when the DSP core is attempting to service

more than one request, and it must stop execution for a few cycles to do

so in a timely manner. The core continues execution immediately after the

requests are serviced.

Rev. A | Page 132 of 207

Data Sheet

ADAU1463/ADAU1467

DEBUG AND RELIABILITY REGISTERS

Clear the Panic Manager Register

Address: 0xF421, Reset: 0x0000, Name: PANIC_CLEAR

When Register 0xF427 (PANIC_FLAG) signals that an error has occurred, use Register 0xF421 (PANIC_CLEAR) to reset it. Toggle Bit 0

(PANIC_CLEAR) of this register from 0b0 to 0b1 and then back to 0b0 again to clear the flag and reset the state of the panic manager.

Table 95. Bit Descriptions for PANIC_CLEAR

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

PANIC_CLEAR

Clear the panic manager. To reset the PANIC_FLAG register (Register 0xF427),

toggle this bit on and then off again.

0x0

RW

0

1

Panic manager is not cleared.

Clear panic manager (on a rising edge of this bit).

Panic Parity Register

Address: 0xF422, Reset: 0x0003, Name: PANIC_PARITY_MASK

The panic manager checks and reports memory parity mask errors. Register 0xF422 (PANIC_PARITY_MASK) allows the user to

configure which memories, if any, are subject to error reporting.

Rev. A | Page 133 of 207

ADAU1463/ADAU1467

Data Sheet

Table 96. Bit Descriptions for PANIC_PARITY_MASK

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:12] RESERVED

11

10

9

DM1_BANK3_MASK

DM1 Bank 3 mask.

0x0

RW

0

1

Report DM1_BANK3 parity mask errors.

Do not report DM1_BANK3 parity mask errors.

DM1 Bank 2 mask.

Report DM1_BANK2 parity mask errors.

Do not report DM1_BANK2 parity mask errors.

DM1 Bank 1 mask.

Report DM1_BANK1 parity mask errors.

Do not report DM1_BANK1 parity mask errors.

DM1 Bank 0 mask.

Report DM1_BANK0 parity mask errors.

Do not report DM1_BANK0 parity mask errors.

DM0 Bank 3 mask.

Report DM0_BANK3 parity mask errors.

Do not report DM0_BANK3 parity mask errors.

DM0 Bank 2 mask.

Report DM0_BANK2 parity mask errors.

Do not report DM0_BANK2 parity mask errors.

DM0 Bank 1 mask.

Report DM0_BANK1 parity mask errors.

Do not report DM0_BANK1 parity mask errors.

DM0 Bank 0 mask.

Report DM0_BANK0 parity mask errors.

Do not report DM0_BANK0 parity mask errors.

PM1 parity mask.

DM1_BANK2_MASK

DM1_BANK1_MASK

DM1_BANK0_MASK

DM0_BANK3_MASK

DM0_BANK2_MASK

DM0_BANK1_MASK

DM0_BANK0_MASK

PM1_MASK

0x0

0x1

RW

0

1

0

1

8

0

1

7

0

1

6

0

1

5

0

1

4

0

1

3

0

1

Report PM1 parity mask errors.

Do not report PM1 parity mask errors.

PM0 parity mask.

Report PM0 parity mask errors.

Do not report PM0 parity mask errors.

ASRC 1 parity mask.

Report ASRC 1 parity mask errors.

Do not report ASRC 1 parity mask errors.

ASRC 0 parity mask.

2

PM0_MASK

0

1

ASRC1_MASK

0

1

0

ASRC0_MASK

0

1

Report ASRC 0 parity mask errors.

Do not report ASRC 0 parity mask errors.

Rev. A | Page 134 of 207

Data Sheet

ADAU1463/ADAU1467

Panic Mask 0 Register

Address: 0xF423, Reset: 0x0000, Name: PANIC_SOFTWARE_MASK

The panic manager checks and reports software errors. Register 0xF423 (PANIC_SOFTWARE_MASK) allows the user to configure

whether software errors are reported to the panic manager or ignored.

Table 97. Bit Descriptions for PANIC_SOFTWARE_MASK

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

PANIC_SOFTWARE

Software mask.

0x0

RW

0

1

Report parity errors.

Do not report parity errors.

Rev. A | Page 135 of 207

ADAU1463/ADAU1467

Data Sheet

Panic Mask 1 Register

Address: 0xF424, Reset: 0x0000, Name: PANIC_WD_MASK

The panic manager checks and reports watchdog errors. Register 0xF424 (PANIC_WD_MASK) allows the user to configure whether

watchdog errors are reported to the panic manager or ignored.

Table 98. Bit Descriptions for PANIC_WD_MASK

Bits

[15:1]

0

Bit Name

RESERVED

PANIC_WD

Settings

Description

Reset

0x0

Access

RW

Watchdog mask.

0x0

RW

0

1

Report watchdog errors.

Do not report watchdog errors.

Panic Mask 2 Register

Address: 0xF425, Reset: 0x0000, Name: PANIC_STACK_MASK

The panic manager checks and reports stack errors. Register 0xF425 (PANIC_STACK_MASK) allows the user to configure whether stack

errors are reported to the panic manager or ignored.

Table 99. Bit Descriptions for PANIC_STACK_MASK

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

PANIC_STACK

Stack mask.

0x0

RW

0

1

Report stack errors.

Do not report stack errors.

Rev. A | Page 136 of 207

Data Sheet

ADAU1463/ADAU1467

Panic Mask 3 Register

Address: 0xF426, Reset: 0x0000, Name: PANIC_LOOP_MASK

The panic manager checks and reports software errors related to looping code sections. Register 0xF426 (PANIC_LOOP_MASK) allows

the user to configure whether loop errors are reported to the panic manager or ignored.

Table 100. Bit Descriptions for PANIC_LOOP_MASK

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

PANIC_LOOP

Loop mask.

0x0

RW

0

1

Report loop errors.

Do not report loop errors.

Panic Flag Register

Address: 0xF427, Reset: 0x0000, Name: PANIC_FLAG

This register acts as the master error flag for the panic manager. If any error is encountered in any functional block whose panic manager

mask is disabled, this register logs that an error has occurred. Individual functional block masks are configured using Register 0xF422

(PANIC_PARITY_MASK), Register 0xF423 (PANIC_SOFTWARE_MASK), Register 0xF424 (PANIC_WD_MASK), Register 0xF425

(PANIC_STACK_MASK), and Register 0xF426 (PANIC_LOOP_MASK).

Table 101. Bit Descriptions for PANIC_FLAG

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

PANIC_FLAG

Error flag from panic manager. This error flag bit is sticky. When an error is

reported, this bit goes high, and it stays high until the user resets it using

Register 0xF421 (PANIC_CLEAR).

0x0

R

0

1

No error.

Error.

Rev. A | Page 137 of 207

ADAU1463/ADAU1467

Data Sheet

Panic Code Register

Address: 0xF428, Reset: 0x0000, Name: PANIC_CODE

When Register 0xF427 (PANIC_FLAG) indicates that an error has occurred, this register provides details revealing which subsystem is

reporting an error. If several errors occur, this register reports only the first error that occurs. Subsequent errors are ignored until the

register is cleared by toggling Register 0xF421 (PANIC_CLEAR).

Table 102. Bit Descriptions for PANIC_CODE

Bits

Bit Name

Settings

Description

Reset

Access

15

ERR_SOFT

Error from software panic.

No error from the software panic.

Error from the software panic.

Error from loop overrun.

No error from the loop overrun.

Error from the loop overrun.

Error from stack overrun.

No error from the stack overrun.

Error from the stack overrun.

Error from the watchdog counter.

No error from the watchdog counter.

Error from the watchdog counter.

Error in DM1 Bank 3.

0x0

R

0

1

14

13

12

11

ERR_LOOP

0x0

R

0

1

ERR_STACK

0

1

ERR_WATCHDOG

ERR_DM1B3

0

1

0

1

No error in DM1 Bank 3.

Error in DM1 Bank 3.

Rev. A | Page 138 of 207

Data Sheet

ADAU1463/ADAU1467

Bits

Bit Name

Settings

Description

Reset

Access

10

ERR_DM1B2

Error in DM1 Bank 2.

No error in DM1 Bank 2.

Error in DM1 Bank 2.

Error in DM1 Bank 1.

No error in DM1 Bank 1.

Error in DM1 Bank 1.

Error in DM1 Bank 0.

No error in DM1 Bank 0.

Error in DM1 Bank 0.

Error in DM0 Bank 3.

No error in DM0 Bank 3.

Error in DM0 Bank 3.

Error in DM0 Bank 2.

No error in DM0 Bank 2.

Error in DM0 Bank 2.

Error in DM0 Bank 1.

No error in DM0 Bank 1.

Error in DM0 Bank 1.

Error in DM0 Bank 0.

No error in DM0 Bank 0.

Error in DM0 Bank 0.

Error in PM1.

0x0

R

0

1

9

8

7

6

5

4

3

2

1

0

ERR_DM1B1

ERR_DM1B0

ERR_DM0B3

ERR_DM0B2

ERR_DM0B1

ERR_DM0B0

ERR_PM1

0x0

R

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No error in PM1.

Error in PM1.

ERR_PM0

Error in PM0.

No error in PM0.

Error in PM0.

0

1

ERR_ASRC1

ERR_ASRC0

Error in ASRC 1.

No error in ASRC 1.

Error in ASRC 1.

0

1

Error in ASRC 0.

0

1

No error in ASRC 0.

Error in ASRC 0.

Execute Stage Error Program Count Register

Address: 0xF432, Reset: 0x0000, Name: EXECUTE_COUNT

When a software error occurs, this register logs the program instruction count at the time when the error occurred for software

debugging purposes.

Table 103. Bit Descriptions for EXECUTE_COUNT

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

EXECUTE_COUNT

Program count in the execute stage when the error occurred.

0x0000 RW

Rev. A | Page 139 of 207

ADAU1463/ADAU1467

Data Sheet

Watchdog Maximum Count Register

Address: 0xF443, Reset: 0x0000, Name: WATCHDOG_MAXCOUNT

This register is designed to start counting at a specified number and decrement by 1 for each clock cycle of the system clock in the core.

The counter is reset to the maximum value each time the program counter jumps to the beginning of the program to begin processing another

audio frame (this is implemented in the DSP program code generated by SigmaStudio). If the counter reaches 0, a watchdog error flag is

raised in the panic manager. The watchdog is typically set to begin counting from a number slightly larger than the maximum number of

instructions expected to execute in the program, such that an error occurs if the program does not finish in time for the next incoming sample.

Table 104. Bit Descriptions for WATCHDOG_MAXCOUNT

Bits

[15:13] RESERVED

[12:0] WD_MAXCOUNT

Bit Name

Settings

Description

Reset

Access

0x0

RW

Value from which the watchdog counter begins counting down.

0x0000 RW

Watchdog Prescale Register

Address: 0xF444, Reset: 0x0000, Name: WATCHDOG_PRESCALE

The watchdog prescaler is a number that is multiplied by the setting in Register 0xF443 (WATCHDOG_MAXCOUNT) to achieve very

large counts for the watchdog, if necessary. Using the largest prescale factor of 128 × 1024 and the largest watchdog maximum count of 64 ×

1024, a very large watchdog counter, on the order of 8.5 billion clock cycles, can be achieved.

Table 105. Bit Descriptions for WATCHDOG_PRESCALE

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:4]

[3:0]

RESERVED

WD_PRESCALE

Watchdog counter prescale setting.

0x0

RW

0000 Increment every 64 clock cycles.

0001 Increment every 128 clock cycles.

0010 Increment every 256 clock cycles.

0011 Increment every 512 clock cycles.

0100 Increment every 1024 clock cycles.

0101 Increment every 2048 clock cycles.

0110 Increment every 4096 clock cycles.

0111 Increment every 8192 clock cycles.

1000 Increment every 16,384 clock cycles.

Rev. A | Page 140 of 207

Data Sheet

ADAU1463/ADAU1467

Bits

Bit Name

Settings

Description

Reset

Access

1001 Increment every 32,768 clock cycles.

1010 Increment every 65,536 clock cycles.

1011 Increment every 131,072 clock cycles.

DSP PROGRAM EXECUTION REGISTERS

Enable Block Interrupts Register

Address: 0xF450, Reset: 0x0000, Name: BLOCKINT_EN

This register enables block interrupts, which are necessary when frequency domain processing is required in the audio processing program.

If block processing algorithms are used in SigmaStudio, SigmaStudio automatically sets this register accordingly. The user does not need

to manually change the value of this register after SigmaStudio configures it.

Table 106. Bit Descriptions for BLOCKINT_EN

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

BLOCKINT_EN

Enable block interrupts.

Disable block interrupts.

Enable block interrupts.

0x0

RW

0

1

Value for the Block Interrupt Counter Register

Address: 0xF451, Reset: 0x0000, Name: BLOCKINT_VALUE

This 16-bit register controls the duration in audio frames of a block. A counter increments each time a new frame start pulse is received

by the DSP core. When the counter reaches the value determined by this register, a block interrupt is generated and the counter is reset.

If block processing algorithms are used in SigmaStudio, SigmaStudio automatically sets this register accordingly. The user does not need

to manually change the value of this register after SigmaStudio configures it.

Table 107. Bit Descriptions for BLOCKINT_VALUE

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

BLOCKINT_VALUE

Value for the block interrupt counter.

0x0000 RW

Rev. A | Page 141 of 207

ADAU1463/ADAU1467

Data Sheet

Program Counter, Bits[23:16] Register

Address: 0xF460, Reset: 0x0000, Name: PROG_CNTR0

This register, in combination with Register 0xF461 (PROG_CNTR1), stores the current value of the program counter.

Table 108. Bit Descriptions for PROG_CNTR0

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:8]

[7:0]

RESERVED

PROG_CNTR_MSB

Program counter, Bits[23:16].

0x00

R

Program Counter, Bits[15:0] Register

Address: 0xF461, Reset: 0x0000, Name: PROG_CNTR1

This register, in combination with Register 0xF460 (PROG_CNTR0), stores the current value of the program counter.

Table 109. Bit Descriptions for PROG_CNTR1

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

PROG_CNTR_LSB

Program counter, Bits[15:0].

0x0000

R

Program Counter Clear Register

Address: 0xF462, Reset: 0x0000, Name: PROG_CNTR_CLEAR

Enabling and disabling Bit 0 (PROG_CNTR_CLEAR) resets Register 0xF465 (PROG_CNTR_MAXLENGTH0) and Register 0xF466

(PROG_CNTR_MAXLENGTH1).

Table 110. Bit Descriptions for PROG_CNTR_CLEAR

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

PROG_CNTR_CLEAR

Clears the program counter.

0x0

RW

0

1

Allow the program counter to update itself.

Clear the program counter and disable it from updating itself.

Rev. A | Page 142 of 207

Data Sheet

ADAU1463/ADAU1467

Program Counter Length, Bits[23:16] Register

Address: 0xF463, Reset: 0x0000, Name: PROG_CNTR_LENGTH0

This register, in combination with Register 0xF464 (PROG_CNTR_LENGTH1), keeps track of the peak value reached by the program

counter during the last audio frame or block. It can be cleared using Register 0xF462 (PROG_CNTR_CLEAR).

Table 111. Bit Descriptions for PROG_CNTR_LENGTH0

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:8]

[7:0]

RESERVED

PROG_LENGTH_MSB

Program counter length, Bits[23:16]

0x00

R

Program Counter Length, Bits[15:0] Register

Address: 0xF464, Reset: 0x0000, Name: PROG_CNTR_LENGTH1

This register, in combination with Register 0xF463 (PROG_CNTR_LENGTH0), keeps track of the peak value reached by the program

counter during the last audio frame or block. It can be cleared using Register 0xF462 (PROG_CNTR_CLEAR).

Table 112. Bit Descriptions for PROG_CNTR_LENGTH1

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

PROG_LENGTH_LSB

Program counter length, Bits[15:0]

0x0000

R

Program Counter Maximum Length, Bits[23:16] Register

Address: 0xF465, Reset: 0x0000, Name: PROG_CNTR_MAXLENGTH0

This register, in combination with Register 0xF466 (PROG_CNTR_MAXLENGTH1), keeps track of the highest peak value reached by

the program counter since the DSP core started. It can be cleared using Register 0xF462 (PROG_CNTR_CLEAR).

Table 113. Bit Descriptions for PROG_CNTR_MAXLENGTH0

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:8]

[7:0]

RESERVED

PROG_MAXLENGTH_MSB

Program counter maximum length, Bits[23:16]

0x00

R

Rev. A | Page 143 of 207

ADAU1463/ADAU1467

Data Sheet

Program Counter Maximum Length, Bits[15:0] Register

Address: 0xF466, Reset: 0x0000, Name: PROG_CNTR_MAXLENGTH1

This register, in combination with Register 0xF465 (PROG_CNTR_MAXLENGTH0), keeps track of the highest peak value reached by

the program counter since the DSP core started. It can be cleared using Register 0xF462 (PROG_CNTR_CLEAR).

Table 114. Bit Descriptions for PROG_CNTR_MAXLENGTH1

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

PROG_MAXLENGTH_LSB

Program counter maximum length, Bits[15:0]

0x0000

R

PANIC MASK REGISTERS

Panic Mask Parity DM0 Bank [1:0] Register

Address: 0xF467, Reset: 0x0000, Name: PANIC_PARITY_MASK1

Table 115. Bit Descriptions for PANIC_PARITY_MASK1

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:13] RESERVED

Reserved.

12

11

10

9

DM0_BANK1_SUBBANK4_MASK

Bank 1 Subbank 4 mask.

0x0

RW

0

1

Report Bank 1 Subbank 4 parity errors.

Ignore Bank 1 Subbank 4 parity errors.

Bank 1 Subbank 3 mask.

Report Bank 1 Subbank 3 parity errors.

Ignore Bank 1 Subbank 3 parity errors.

Bank 1 Subbank 2 mask.

Report Bank 1 Subbank 2 parity errors.

Ignore Bank 1 Subbank 2 parity errors.

Bank 1 Subbank 1 mask.

DM0_BANK1_SUBBANK3_MASK

DM0_BANK1_SUBBANK2_MASK

DM0_BANK1_SUBBANK1_MASK

0x0

RW

0

1

0

1

0

1

Report Bank 1 Subbank 1 parity errors.

Ignore Bank 1 Subbank 1 parity errors.

Rev. A | Page 144 of 207

Data Sheet

ADAU1463/ADAU1467

Bits

Bit Name

Settings

Description

Reset

Access

8

DM0_BANK1_SUBBANK0_MASK

Bank 1 Subbank 0 mask.

0x0

RW

0

1

Report Bank 1 Subbank 0 parity errors.

Ignore Bank 1 Subbank 0 parity errors.

Reserved.

[7:5]

4

RESERVED

0x0

RW

DM0_BANK0_SUBBANK4_MASK

Bank 0 Subbank 4 mask.

0

1

Report Bank 0 Subbank 4 parity errors.

Ignore Bank 0 Subbank 4 parity errors.

Bank 0 Subbank 3 mask.

3

2

1

0

DM0_BANK0_SUBBANK3_MASK

DM0_BANK0_SUBBANK2_MASK

DM0_BANK0_SUBBANK1_MASK

DM0_BANK0_SUBBANK0_MASK

0x0

RW

0

1

Report Bank 0 Subbank 3 parity errors.

Ignore Bank 0 Subbank 3 parity errors.

Bank 0 Subbank 2 mask.

Report Bank 0 Subbank 2 parity errors.

Ignore Bank 0 Subbank 2 parity errors.

Bank 0 Subbank 1 mask.

Report Bank 0 Subbank 1 parity errors.

Ignore Bank 0 Subbank 1 parity errors.

Bank 0 Subbank 0 mask.

0

1

0

1

0

1

Report Bank 0 Subbank 0 parity errors.

Ignore Bank 0 Subbank 0 parity errors.

Panic Mask Parity DM0 Bank [3:2] Register

Address: 0xF468, Reset: 0x0000, Name: PANIC_PARITY_MASK2

Table 116. Bit Descriptions for PANIC_PARITY_MASK2

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:13] RESERVED

Reserved.

12

11

10

DM0_BANK3_SUBBANK4_MASK

Bank 3 Subbank 4 mask.

0x0

RW

0

1

Report Bank 3 Subbank 4 parity errors.

Ignore Bank 3 Subbank 4 parity errors.

Bank 3 Subbank 3 mask.

Report Bank 3 Subbank 3 parity errors.

Ignore Bank 3 Subbank 3 parity errors.

Bank 3 subbank 2 mask.

DM0_BANK3_SUBBANK3_MASK

DM0_BANK3_SUBBANK2_MASK

0x0

RW

0

1

0

1

Report Bank 3 Subbank 2 parity errors.

Ignore Bank 3 Subbank 2 parity errors.

Rev. A | Page 145 of 207

ADAU1463/ADAU1467

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

9

DM0_BANK3_SUBBANK1_MASK

Bank 3 Subbank 1 mask.

0x0

RW

0

1

Report Bank 3 Subbank 1 parity errors.

Ignore Bank 3 Subbank 1 parity errors.

Bank 3 Subbank 0 mask.

8

DM0_BANK3_SUBBANK0_MASK

0x0

RW

0

1

Report Bank 3 Subbank 0 parity errors.

Ignore Bank 3 Subbank 0 parity errors.

Reserved.

[7:5]

4

RESERVED

0x0

RW

DM0_BANK2_SUBBANK4_MASK

Bank 2 Subbank 4 mask.

0

1

Report Bank 2 Subbank 4 parity errors.

Ignore Bank 2 Subbank 4 parity errors.

Bank 2 Subbank 3 mask.

3

2

1

0

DM0_BANK2_SUBBANK3_MASK

DM0_BANK2_SUBBANK2_MASK

DM0_BANK2_SUBBANK1_MASK

DM0_BANK2_SUBBANK0_MASK

0x0

RW

0

1

Report Bank 2 Subbank 3 parity errors.

Ignore Bank 2 Subbank 3 parity errors.

Bank 2 Subbank 2 mask.

Report Bank 2 Subbank 2 parity errors.

Ignore Bank 2 Subbank 2 parity errors.

Bank 2 Subbank 1 mask.

Report Bank 2 Subbank 1 parity errors.

Ignore Bank 2 Subbank 1 parity errors.

Bank 2 Subbank 0 mask.

0

1

0

1

0

1

Report Bank 2 Subbank 0 parity errors.

Ignore Bank 2 Subbank 0 parity errors.

Panic Mask Parity DM1 Bank [1:0] Register

Address: 0xF469, Reset: 0x0000, Name: PANIC_PARITY_MASK3

Table 117. Bit Descriptions for PANIC_PARITY_MASK3

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:13] RESERVED

Reserved.

12

11

DM1_BANK1_SUBBANK4_MASK

Bank 1 Subbank 4 mask.

0x0

RW

0

1

Report Bank 1 Subbank 4 parity errors.

Ignore Bank 1 Subbank 4 parity errors.

Bank 1 Subbank 3 mask.

DM1_BANK1_SUBBANK3_MASK

0x0

RW

0

1

Report Bank 1 Subbank 3 parity errors.

Ignore Bank 1 Subbank 3 parity errors.

Rev. A | Page 146 of 207

Data Sheet

ADAU1463/ADAU1467

Bits

Bit Name

Settings

Description

Reset

Access

10

DM1_BANK1_SUBBANK2_MASK

Bank 1 Subbank 2 mask.

0x0

RW

0

1

Report Bank 1 Subbank 2 parity errors.

Ignore Bank 1 Subbank 2 parity errors.

Bank 1 Subbank 1 mask.

9

8

DM1_BANK1_SUBBANK1_MASK

DM1_BANK1_SUBBANK0_MASK

0x0

RW

0

1

Report Bank 1 Subbank 1 parity errors.

Ignore Bank 1 Subbank 1 parity errors.

Bank 1 Subbank 0 mask.

0

1

Report Bank 1 Subbank 0 parity errors.

Ignore Bank 1 Subbank 0 parity errors.

Reserved.

[7:5]

4

RESERVED

0x0

RW

DM1_BANK0_SUBBANK4_MASK

Bank 0 Subbank 4 mask.

0

1

Report Bank 0 Subbank 4 parity errors.

Ignore Bank 0 Subbank 4 parity errors.

Bank 0 Subbank 3 mask.

3

2

1

0

DM1_BANK0_SUBBANK3_MASK

DM1_BANK0_SUBBANK2_MASK

DM1_BANK0_SUBBANK1_MASK

DM1_BANK0_SUBBANK0_MASK

0x0

RW

0

1

Report Bank 0 Subbank 3 parity errors.

Ignore Bank 0 Subbank 3 parity errors.

Bank 0 Subbank 2 mask.

Report Bank 0 Subbank 2 parity errors.

Ignore Bank 0 Subbank 2 parity errors.

Bank 0 Subbank 1 mask.

Report Bank 0 Subbank 1 parity errors.

Ignore Bank 0 Subbank 1 parity errors.

Bank 0 Subbank 0 mask.

0

1

0

1

0

1

Report Bank 0 Subbank 0 parity errors.

Ignore Bank 0 Subbank 0 parity errors.

Panic Mask Parity DM1 Bank [3:2] Register

Address: 0xF46A, Reset: 0x0000, Name: PANIC_PARITY_MASK4

Rev. A | Page 147 of 207

ADAU1463/ADAU1467

Data Sheet

Table 118. Bit Descriptions for PANIC_PARITY_MASK4

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:13] RESERVED

Reserved.

12

11

10

9

DM1_BANK3_SUBBANK4_MASK

Bank 3 Subbank 4 mask.

0x0

RW

0

1

Report Bank 3 Subbank 4 parity errors.

Ignore Bank 3 Subbank 4 parity errors.

Bank 3 Subbank 3 mask.

Report Bank 3 Subbank 3 parity errors.

Ignore Bank 3 Subbank 3 parity errors.

Bank 3 Subbank 2 mask.

Report Bank 3 Subbank 2 parity errors.

Ignore Bank 3 Subbank 2 parity errors.

Bank 3 Subbank 1 mask.

Report Bank 3 Subbank 1 parity errors.

Ignore Bank 3 Subbank 1 parity errors.

Bank 3 Subbank 0 mask.

DM1_BANK3_SUBBANK3_MASK

DM1_BANK3_SUBBANK2_MASK

DM1_BANK3_SUBBANK1_MASK

DM1_BANK3_SUBBANK0_MASK

0x0

RW

0

1

0

1

0

1

8

0

1

Report Bank 3 Subbank 0 parity errors.

Ignore Bank 3 Subbank 0 parity errors.

Reserved.

[7:5]

4

RESERVED

0x0

RW

DM1_BANK2_SUBBANK4_MASK

Bank 2 Subbank 4 mask.

0

1

Report Bank 2 Subbank 4 parity errors.

Ignore Bank 2 Subbank 4 parity errors.

Bank 2 Subbank 3 mask.

3

2

1

0

DM1_BANK2_SUBBANK3_MASK

DM1_BANK2_SUBBANK2_MASK

DM1_BANK2_SUBBANK1_MASK

DM1_BANK2_SUBBANK0_MASK

0x0

RW

0

1

Report Bank 2 Subbank 3 parity errors.

Ignore Bank 2 Subbank 3 parity errors.

Bank 2 Subbank 2 mask.

Report Bank 2 Subbank 2 parity errors.

Ignore Bank 2 Subbank 2 parity errors.

Bank 2 Subbank 1 mask.

Report Bank 2 Subbank 1 parity errors.

Ignore Bank 2 Subbank 1 parity errors.

Bank 2 Subbank 0 mask.

0

1

0

1

0

1

Report Bank 2 Subbank 0 parity errors.

Ignore Bank 2 Subbank 0 parity errors.

Rev. A | Page 148 of 207

Data Sheet

ADAU1463/ADAU1467

Panic Mask Parity PM Bank [1:0] Register

Address: 0xF46B, Reset: 0x0000, Name: PANIC_PARITY_MASK5

Table 119. Bit Descriptions for PANIC_PARITY_MASK5

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:14] RESERVED

Reserved.

13

12

11

10

9

PM_BANK1_SUBBANK5_MASK

Bank 1 Subbank 5 mask.

0x0

RW

0

1

Report Bank 1 Subbank 5 parity errors.

Ignore Bank 1 Subbank 5 parity errors.

Bank 1 Subbank 4 mask.

Report Bank 1 Subbank 4 parity errors.

Ignore Bank 1 Subbank 4 parity errors.

Bank 1 Subbank 3 mask.

Report Bank 1 Subbank 3 parity errors.

Ignore Bank 1 Subbank 3 parity errors.

Bank 1 Subbank 2 mask.

Report Bank 1 Subbank 2 parity errors.

Ignore Bank 1 Subbank 2 parity errors.

Bank 1 Subbank 1 mask.

PM_BANK1_SUBBANK4_MASK

PM_BANK1_SUBBANK3_MASK

PM_BANK1_SUBBANK2_MASK

PM_BANK1_SUBBANK1_MASK

PM_BANK1_SUBBANK0_MASK

0x0

RW

0

1

0

1

0

1

0

1

Report Bank 1 Subbank 1 parity errors.

Ignore Bank 1 Subbank 1 parity errors.

Bank 1 Subbank 0 mask.

8

0

1

Report Bank 1 Subbank 0 parity errors.

Ignore Bank 1 Subbank 0 parity errors.

Reserved.

[7:6]

5

RESERVED

0x0

RW

PM_BANK0_SUBBANK5_MASK

Bank 0 Subbank 5 mask.

0

1

Report Bank 0 Subbank 5 parity errors.

Ignore Bank 0 Subbank 5 parity errors.

Bank 0 Subbank 4 mask.

4

3

PM_BANK0_SUBBANK4_MASK

PM_BANK0_SUBBANK3_MASK

0x0

RW

0

1

Report Bank 0 Subbank 4 parity errors.

Ignore Bank 0 Subbank 4 parity errors.

Bank 0 Subbank 3 mask.

0

1

Report Bank 0 Subbank 3 parity errors.

Ignore Bank 0 Subbank 3 parity errors.

Rev. A | Page 149 of 207

ADAU1463/ADAU1467

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

2

PM_BANK0_SUBBANK2_MASK

Bank 0 Subbank 2 mask.

0x0

RW

0

1

Report Bank 0 Subbank 2 parity errors.

Ignore Bank 0 Subbank 2 parity errors.

Bank 0 Subbank 1 mask.

1

0

PM_BANK0_SUBBANK1_MASK

PM_BANK0_SUBBANK0_MASK

0x0

RW

0

1

Report Bank 0 Subbank 1 parity errors.

Ignore Bank 0 Subbank 1 parity errors.

Bank 0 Subbank 0 mask.

0

1

Report Bank 0 Subbank 0 parity errors.

Ignore Bank 0 Subbank 0 parity errors.

Panic Parity Error DM0 Bank [1:0] Register

Address: 0xF46C, Reset: 0x0000, Name: PANIC_CODE1

Table 120. Bit Descriptions for PANIC_CODE1

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:13] RESERVED

Reserved.

12

11

10

9

ERR_DM0B1SB4

Error in Bank 1 Subbank 4.

No error in Bank 1 Subbank 4.

Error in Bank 1 Subbank 4.

Error in Bank 1 Subbank 3.

No error in Bank 1 Subbank 3.

Error in Bank 1 Subbank 3.

Error in Bank 1 subbank 2.

No error in Bank 1 Subbank 2.

Error in Bank 1 Subbank 2.

Error in Bank 1 Subbank 1.

No error in Bank 1 Subbank 1.

Error in Bank 1 Subbank 1.

Error in Bank 1 Subbank 0.

No error in Bank 1 Subbank 0.

Error in Bank 1 Subbank 0.

0x0

R

0

1

ERR_DM0B1SB3

ERR_DM0B1SB2

ERR_DM0B1SB1

ERR_DM0B1SB0

0x0

R

0

1

0

1

0

1

8

0

1

Rev. A | Page 150 of 207

Data Sheet

ADAU1463/ADAU1467

Bits

[7:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

ERR_DM0B0SB4

Error in Bank 0 Subbank 4.

No error in Bank 0 Subbank 4.

Error in Bank 0 Subbank 4.

Error in Bank 0 Subbank 3.

No error in Bank 0 Subbank 3.

Error in Bank 0 Subbank 3.

Error in Bank 0 Subbank 2.

No error in Bank 0 Subbank 2.

Error in Bank 0 Subbank 2.

Error in Bank 0 Subbank 1.

No error in Bank 0 Subbank 1.

Error in Bank 0 Subbank 1.

Error in Bank 0 Subbank 0.

No error in Bank 0 Subbank 0.

Error in Bank 0 Subbank 0.

0x0

R

0

1

3

2

1

0

ERR_DM0B0SB3

ERR_DM0B0SB2

ERR_DM0B0SB1

ERR_DM0B0SB0

0x0

R

0

1

0

1

0

1

0

1

Panic Parity Error DM0 Bank [3:2] Register

Address: 0xF46D, Reset: 0x0000, Name: PANIC_CODE2

Table 121. Bit Descriptions for PANIC_CODE2

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:13] RESERVED

Reserved.

12

11

10

ERR_DM0B3SB4

Error in Bank 3 Subbank 4.

No error in Bank 3 Subbank 4.

Error in Bank 3 Subbank 4.

Error in Bank 3 Subbank 3.

No error in Bank 3 Subbank 3.

Error in Bank 3 Subbank 3.

Error in Bank 3 Subbank 2.

No error in Bank 3 Subbank 2.

Error in Bank 3 Subbank 2.

0x0

R

0

1

ERR_DM0B3SB3

ERR_DM0B3SB2

0x0

R

0

1

0

1

Rev. A | Page 151 of 207

ADAU1463/ADAU1467

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

9

ERR_DM0B3SB1

Error in Bank 3 Subbank 1.

No error in Bank 3 Subbank 1.

Error in Bank 3 Subbank 1.

Error in Bank 3 Subbank 0.

No error in Bank 3 Subbank 0.

Error in Bank 3 Subbank 0.

Reserved.

0x0

R

0

1

8

ERR_DM0B3SB0

0x0

R

0

1

[7:5]

4

RESERVED

0x0

RW

R

ERR_DM0B2SB4

Error in Bank 2 Subbank 4.

No error in Bank 2 Subbank 4.

Error in Bank 2 Subbank 4.

Error in Bank 2 Subbank 3.

No error in Bank 2 Subbank 3.

Error in Bank 2 Subbank 3.

Error in Bank 2 Subbank 2.

No error in Bank 2 Subbank 2.

Error in Bank 2 Subbank 2.

Error in Bank 2 Subbank 1.

No error in Bank 2 Subbank 1.

Error in Bank 2 Subbank 1.

Error in Bank 2 Subbank 0.

No error in Bank 2 Subbank 0.

Error in Bank 2 Subbank 0.

0

1

3

2

1

0

ERR_DM0B2SB3

ERR_DM0B2SB2

ERR_DM0B2SB1

ERR_DM0B2SB0

0x0

R

0

1

0

1

0

1

0

1

Panic Parity Error DM1 Bank [1:0] Register

Address: 0xF46E, Reset: 0x0000, Name: PANIC_CODE3

Rev. A | Page 152 of 207

Data Sheet

ADAU1463/ADAU1467

Table 122. Bit Descriptions for PANIC_CODE3

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:13] RESERVED

Reserved.

12

11

10

9

ERR_DM1B1SB4

Error in Bank 1 Subbank 4.

No error in Bank 1 Subbank 4.

Error in Bank 1 Subbank 4.

Error in Bank 1 Subbank 3.

No error in Bank 1 Subbank 3.

Error in Bank 1 Subbank 3.

Error in Bank 1 Subbank 2.

No error in Bank 1 Subbank 2.

Error in Bank 1 Subbank 2.

Error in Bank 1 Subbank 1.

No error in Bank 1 Subbank 1.

Error in Bank 1 Subbank 1.

Error in Bank 1 Subbank 0.

No error in Bank 1 Subbank 0.

Error in Bank 1 Subbank 0.

Reserved.

0x0

R

0

1

ERR_DM1B1SB3

ERR_DM1B1SB2

ERR_DM1B1SB1

ERR_DM1B1SB0

0x0

R

0

1

0

1

0

1

8

0

1

[7:5]

4

RESERVED

0x0

RW

R

ERR_DM1B0SB4

Error in Bank 0 Subbank 4.

No error in Bank 0 Subbank 4.

Error in Bank 0 Subbank 4.

Error in Bank 0 Subbank 3.

No error in Bank 0 Subbank 3.

Error in Bank 0 Subbank 3.

Error in Bank 0 Subbank 2.

No error in Bank 0 Subbank 2.

Error in Bank 0 Subbank 2.

Error in Bank 0 Subbank 1.

No error in Bank 0 Subbank 1.

Error in Bank 0 Subbank 1.

Error in Bank 0 Subbank 0.

No error in Bank 0 Subbank 0.

Error in Bank 0 Subbank 0.

0

1

3

2

1

0

ERR_DM1B0SB3

ERR_DM1B0SB2

ERR_DM1B0SB1

ERR_DM1B0SB0

0x0

R

0

1

0

1

0

1

0

1

Rev. A | Page 153 of 207

ADAU1463/ADAU1467

Data Sheet

Panic Parity Error DM1 Bank [3:2] Register

Address: 0xF46F, Reset: 0x0000, Name: PANIC_CODE4

Table 123. Bit Descriptions for PANIC_CODE4

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:13] RESERVED

Reserved.

12

11

10

9

ERR_DM1B3SB4

Error in Bank 3 Subbank 4.

No error in Bank 3 Subbank 4.

Error in Bank 3 Subbank 4.

Error in Bank 3 Subbank 3.

No error in Bank 3 Subbank 3.

Error in Bank 3 Subbank 3.

Error in Bank 3 Subbank 2.

No error in Bank 3 Subbank 2.

Error in Bank 3 Subbank 2.

Error in Bank 3 Subbank 1.

No error in Bank 3 Subbank 1.

Error in Bank 3 Subbank 1.

Error in Bank 3 Subbank 0.

No error in Bank 3 Subbank 0.

Error in Bank 3 Subbank 0.

Reserved.

0x0

R

0

1

ERR_DM1B3SB3

ERR_DM1B3SB2

ERR_DM1B3SB1

ERR_DM1B3SB0

0x0

R

0

1

0

1

0

1

8

0

1

[7:5]

4

RESERVED

0x0

RW

R

ERR_DM1B2SB4

Error in Bank 2 Subbank 4.

No error in Bank 2 Subbank 4.

Error in Bank 2 Subbank 4.

Error in Bank 2 Subbank 3.

No error in Bank 2 Subbank 3.

Error in Bank 2 Subbank 3.

Error in Bank 2 Subbank 2.

No error in Bank 2 Subbank 2.

Error in Bank 2 Subbank 2.

0

1

3

2

ERR_DM1B2SB3

ERR_DM1B2SB2

0x0

R

0

1

0

1

Rev. A | Page 154 of 207

Data Sheet

ADAU1463/ADAU1467

Bits

Bit Name

Settings

Description

Reset

Access

1

ERR_DM1B2SB1

Error in Bank 2 Subbank 1.

No error in Bank 2 Subbank 1.

Error in Bank 2 Subbank 1.

Error in Bank 2 Subbank 0.

No error in Bank 2 Subbank 0.

Error in Bank 2 Subbank 0.

0x0

R

0

1

0

ERR_DM1B2SB0

0x0

R

0

1

Panic Parity Error PM Bank [1:0] Register

Address: 0xF470, Reset: 0x0000, Name: PANIC_CODE5

Table 124. Bit Descriptions for PANIC_CODE5

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:14] RESERVED

Reserved.

13

12

11

10

ERR_PM_B1SB5

Error in Bank 1 Subbank 5.

No error in Bank 0 Subbank 5.

Error in Bank 0 Subbank 5.

Error in Bank 1 Subbank 4.

No error in Bank 1 Subbank 4.

Error in Bank 1 Subbank 4.

Error in Bank 1 Subbank 3.

No error in Bank 1 Subbank 3.

Error in Bank 1 Subbank 3.

Error in Bank 1 Subbank 2.

No error in Bank 1 Subbank 2.

Error in Bank 1 Subbank 2.

0x0

R

0

1

ERR_PM_B1SB4

ERR_PM_B1SB3

ERR_PM_B1SB2

0x0

R

0

1

0

1

0

1

Rev. A | Page 155 of 207

ADAU1463/ADAU1467

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

9

ERR_PM_B1SB1

Error in Bank 1 Subbank 1.

No error in Bank 1 Subbank 1.

Error in Bank 1 Subbank 1.

Error in Bank 1 Subbank 0.

No error in Bank 1 Subbank 0.

Error in Bank 1 Subbank 0.

Reserved.

0x0

R

0

1

8

ERR_PM_B1SB0

0x0

R

0

1

[7:6]

5

RESERVED

0x0

RW

R

ERR_PM_B0SB5

Error in Bank 0 Subbank 5.

No error in Bank 0 Subbank 5.

Error in Bank 0 Subbank 5.

Error in Bank 0 Subbank 4.

No error in Bank 0 Subbank 4.

Error in Bank 0 Subbank 4.

Error in Bank 0 Subbank 3.

No error in Bank 0 Subbank 3.

Error in Bank 0 Subbank 3.

Error in Bank 0 Subbank 2.

No error in Bank 0 Subbank 2.

Error in Bank 0 Subbank 2.

Error in Bank 0 Subbank 1.

No error in Bank 0 Subbank 1.

Error in Bank 0 Subbank 1.

Error in Bank 0 Subbank 0.

No error in Bank 0 Subbank 0.

Error in Bank 0 Subbank 0.

0

1

4

3

2

1

0

ERR_PM_B0SB4

ERR_PM_B0SB3

ERR_PM_B0SB2

ERR_PM_B0SB1

ERR_PM_B0SB0

0x0

R

0

1

0

1

0

1

0

1

0

1

Rev. A | Page 156 of 207

Data Sheet

ADAU1463/ADAU1467

MULTIPURPOSE PIN CONFIGURATION REGISTERS

Multipurpose Pin Mode Register

Address: 0xF510 to 0xF51D and 0xF5C0 to 0xF5CB (Increments of 0x1), Reset: 0x0000, Name: MPx_MODE

These 26 registers configure the multipurpose pins. Certain multipurpose pins can function as audio clock pins, control bus pins, or

GPIO pins (see Table 52).

Table 125. Bit Descriptions for MPx_MODE

Bits

[15:11] RESERVED

[10:8] SS_SELECT

Bit Name

Settings

Description

Reset

0x0

Access

RW

Master port slave select channel selection. If the pin is configured as a slave

select line (Bits[3:1] (MP_MODE) = 0b110), these bits configure which slave

select channel the pin corresponds to. This allows multiple slave devices to

be connected to the SPI master port, all using different slave select lines.

The first slave select signal (Slave Select 0) is always routed to the SS_M/

MP0 pin. The remaining six slave select lines can be routed to any

multipurpose pin configured as a slave select output.

0x0

RW

000 Slave Select Channel 1.

001 Slave Select Channel 2.

010 Slave Select Channel 3.

011 Slave Select Channel 4.

100 Slave Select Channel 5.

101 Slave Select Channel 6.

Rev. A | Page 157 of 207

ADAU1463/ADAU1467

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

DEBOUNCE_VALUE

Debounce circuit setting. These bits configure the duration of the debounce

circuitry when the corresponding pin is configured as an input (Bits[3:1]

(MP_MODE) = 0b000).

0x0

RW

0001 0.3 ms debounce.

0010 0.6 ms debounce.

0011 0.9 ms debounce.

0100 5.0 ms debounce.

0101 10.0 ms debounce.

0110 20.0 ms debounce.

0111 40.0 ms debounce.

0000 No debounce.

[3:1]

MP_MODE

Pin mode (when multipurpose function is enabled). These bits select the

0x0

RW

function of the corresponding pin if it is enabled in multipurpose mode

(Bit 0 (MP_ENABLE) = 0b1).

000 General-purpose digital input.

001 General-purpose input, driven by control port; sends its value to the DSP

core, but that value can be overwritten by a direct register write.

010 General-purpose output with pull-up.

011 General-purpose output without pull-up.

100 PDM microphone data input.

101 Panic manager error flag output .

110 Slave select line for the master SPI port.

0

MP_ENABLE

Function selection (multipurpose or clock/control). This bit selects

whether the corresponding pin is used as a multipurpose pin or as its

primary function (which could be either an audio clock or control bus pin).

0x0

RW

0

1

Audio clock or control port function enabled; the settings of the MPx_MODE,

MPx_WRITE, and MPx_READ registers are ignored.

Multipurpose function enabled.

Rev. A | Page 158 of 207

Data Sheet

ADAU1463/ADAU1467

Multipurpose Pin Write Value Register

Address: 0xF520 to 0xF52D and 0xF5D0 to 0xF5DB (Increments of 0x1), Reset: 0x0000, Name: MPx_WRITE

If a multipurpose pin is configured as an output driven by the control port (the corresponding Bits[3:1] (MP_MODE) = 0b001), the value

that is output from the DSP core can be configured by directly writing to these registers. See Table 52.

Table 126. Bit Descriptions for MPx_WRITE

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

W

RESERVED

MP_REG_WRITE

Multipurpose pin output state when pin is configured as an output written

by the control port. This register configures the value seen by the DSP core

for the corresponding multipurpose pin input. The pin can have two states:

logic low (off) or logic high (on).

0x0

W

0

1

Multipurpose pin output low.

Multipurpose pin output high.

Multipurpose Pin Read Value Registers

Address: 0xF530 to 0xF53D and 0xF5E0 to 0xF5EB (Increments of 0x1), Reset: 0x0000, Name: MPx_READ

These registers log the current state of the multipurpose pins when they are configured as inputs. The pins can have two states: logic low

(off) or logic high (on). See Table 52.

Table 127. Bit Descriptions for MPx_READ

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RESERVED

R

MP_REG_READ

Multipurpose pin read value.

Multipurpose pin input low.

Multipurpose pin input high.

0x0

0

1

Rev. A | Page 159 of 207

ADAU1463/ADAU1467

Data Sheet

Digital PDM Microphone Control Register

Address: 0xF560 to 0xF561 (Increments of 0x1), Reset: 0x4000, Name: DMIC_CTRLx

These registers configure the digital PDM microphone interface. Two registers are used to control up to four PDM microphones:

Register 0xF560 (DMIC_CTRL0) configures PDM Microphone Channel 0 and PDM Microphone Channel 1, and Register 0xF561

(DMIC_CTRL1) configures PDM Microphone Channel 2 and PDM Microphone Channel 3.

Table 128. Bit Descriptions for DMIC_CTRLx

Bits

Bit Name

Settings Description

Reset Access

15

RESERVED

0x0

0x4

RW

[14:12] CUTOFF

High-pass filter cutoff frequency. These bits configure the cutoff frequency of an

optional high-pass filter designed to remove dc components from the

microphone data signal(s). To use these bits, Bit 3 (HPF), must be enabled.

000 59.9 Hz.

001 29.8 Hz.

010 14.9 Hz.

011 7.46 Hz.

100 3.73 Hz.

101 1.86 Hz.

110 0.93 Hz.

[11:8]

MIC_DATA_SRC

Digital PDM microphone data source pin. These bits configure which hardware pin

0x0

RW

acts as a data input from the PDM microphone(s). Up to two microphones can be

connected to a single pin.

0000 SS_M/MP0.

0001 MOSI_M/MP1.

0010 SCL_M/SCLK_M/MP2.

0011 SDA_M/MISO_M/MP3.

0100 LRCLK_OUT0/MP4.

0101 LRCLK_OUT1/MP5.

0110 MP6.

Rev. A | Page 160 of 207

Data Sheet

ADAU1463/ADAU1467

Bits

Bit Name

Settings Description

0111 MP7.

Reset Access

1000 LRCLK_OUT2/MP8.

1001 LRCLK_OUT3/MP9.

1010 LRCLK_IN0/MP10.

1011 LRCLK_IN1/MP11.

1100 LRCLK_IN2/MP12.

1101 LRCLK_IN3/MP13.

7

RESERVED

DMIC_CLK

0x0

RW

[6:4]

Digital PDM microphone clock select. A valid bit clock signal must be assigned to 0x0

the PDM microphones. Any of the four BCLK_INPUTx or four BCLK_OUTPUTx

signals can be used. A trace must connect the selected pin to the clock input pin

on the corresponding PDM microphone(s). If the corresponding BCLK_x pin is not

configured in master mode, use an external clock source, with the BCLK_x pin and

the PDM microphone acting as slaves.

000 BCLK_IN0.

001 BCLK_IN1.

010 BCLK_IN2.

011 BCLK_IN3.

100 BCLK_OUT0.

101 BCLK_OUT1.

110 BCLK_OUT2.

111 BCLK_OUT3.

3

2

HPF

High-pass filter enable. This bit enables or disables a high-pass filter to remove dc 0x0

components from the microphone data signals. The cutoff of the filter is

controlled by Bits[14:12] (CUTOFF).

HPF disabled.

HPF enabled.

RW

0

1

DMPOL

Data polarity swap. When this bit is set to 0b0, a logic high data input is treated as

logic high, and a logic low data input is treated as logic low. When this bit is set to

0b1, the opposite is true: a logic high data input is treated as a logic low, and a

logic low data input is treated as logic high. This effectively inverts the amplitude

of the incoming audio data.

0x0

0

1

Data polarity normal.

Data polarity inverted.

1

0

DMSW

Digital PDM microphone channel swap. In DMIC_CTRL0, this bit swaps PDM

Microphone Channel 0 and PDM Microphone Channel 1. In the DMIC_CTRL1 register,

this bit swaps PDM Microphone Channel 2 and PDM Microphone Channel 3.

Normal.

Swap left and right channels.

0x0

RW

0

1

DMIC_EN

Digital PDM microphone enable. This bit enables or disables the data input from

the PDM microphones.

0

1

Digital PDM microphone disabled.

Digital PDM microphone enabled.

Rev. A | Page 161 of 207

ADAU1463/ADAU1467

Data Sheet

ASRC STATUS AND CONTROL REGISTERS

ASRC Lock Status Register

Address: 0xF580, Reset: 0x0000, Name: ASRC_LOCK

This register contains eight bits that represent the lock status of each ASRC stereo pair on the ADAU1463 and ADAU1467. Lock status

requires three conditions: the output target rate is set, the input rate is steady and is detected, and the ratio between input and output rates

has been calculated. If all of these conditions are true for a given stereo ASRC, the corresponding lock bit is low. If any one of these conditions is

not true, the corresponding lock bit is high.

Table 129. Bit Descriptions for ASRC_LOCK

Bits

[15:8]

7

Bit Name

RESERVED

ASRC7L

Settings

Description

Reset

0x0

Access

RW

ASRC 7 lock status.

Locked.

Unlocked.

0x0

R

0

1

6

5

4

3

2

1

0

ASRC6L

ASRC5L

ASRC4L

ASRC3L

ASRC2L

ASRC1L

ASRC0L

ASRC 6 lock status.

Locked.

Unlocked.

0x0

R

0

1

ASRC 5 lock status.

Locked.

Unlocked.

0

1

ASRC 4 lock status.

Locked.

Unlocked.

0

1

ASRC 3 lock status.

Locked.

Unlocked.

0

1

ASRC 2 lock status.

Locked.

Unlocked.

0

1

ASRC 1 lock status.

Locked.

Unlocked.

0

1

ASRC 0 lock status.

Locked.

Unlocked.

0

1

Rev. A | Page 162 of 207

Data Sheet

ADAU1463/ADAU1467

ASRC Mute Register

Address: 0xF581, Reset: 0x0000, Name: ASRC_MUTE

This register contains controls related to the muting of audio on ASRC channels. Bits[7:0] (ASRCxM) are individual mute controls for

each stereo ASRC on the ADAU1463 and ADAU1467. Bit 8 (ASRC_RAMP0) and Bit 9 (ASRC_RAMP1) enable or disable an optional

volume ramp-up and ramp-down to smoothly transition between muted and unmuted states. The mute and unmute ramps are linear. The

duration of the ramp is determined by the sample rate of the DSP core, which is set by Register 0xF401 (START_PULSE). The ramp takes

exactly 2048 input samples to complete. For example, if the sample rate of audio entering an ASRC channel is 48 kHz, the duration of the

ramp is 2048/48,000 = 42.7 ms. If the sample rate of audio entering an ASRC channel is 6 kHz, the duration of the ramp is 2048/6000 =

341.3 ms. Bit 10 (LOCKMUTE) allows the ASRCs to automatically mute themselves in the event that lock status is lost or not attained.

Table 130. Bit Descriptions for ASRC_MUTE

Bits

[15:11] RESERVED

10 LOCKMUTE

Bit Name

Settings

Description

Reset

0x0

Access

RW

Mutes ASRCs when lock is lost. When this bit is enabled, individual stereo

ASRCs automatically mute on the event that lock status is lost (for example,

if the sample rate of the input suddenly changes and the ASRC needs to

reattain lock), provided that the corresponding ASRC_RAMPx bit is set to

0b0 (enabled). This automatic mute uses a volume ramp instead of an

instantaneous mute to avoid click and pop noises on the output. When

lock status is attained again (and the corresponding ASRC_RAMPx and

ASRCxM bits are set to 0b0 (enabled) and 0b0 (unmuted), respectively),

the ASRC automatically unmutes using a volume ramp. However, because

there is a period of uncertainty when the ASRC is attaining lock, there still

may be noise on the ASRC outputs when the input signal returns. Measures

must be taken in the DSP program to delay the unmuting of the ASRC output

signals if this noise is not desired. The individual ASRCxM mute bits override

the automatic LOCKMUTE behavior.

0x0

RW

0

1

Do not mute when lock is lost.

Mute when lock is lost, and unmute when lock is reattained.

Rev. A | Page 163 of 207

ADAU1463/ADAU1467

Data Sheet

Bits

Bit Name

Settings

Description

Reset

Access

9

ASRC_RAMP1

ASRC 7 to ASRC 4 mute disable. ASRC 7 to ASRC 4 (Channel 15 to Channel 8)

are defined as ASRC Block 1. This bit enables or disables mute ramping for

all ASRCs in Block 1. If this bit is 0b1, Bit 7 (ASRC7M), Bit 6 (ASRC6M), Bit 5

(ASRC5M), and Bit 4 (ASRC4M) are ignored, and the outputs of ASRC 7 to

ASRC 4 are active at all times.

0x0

RW

0

1

Enabled.

Disabled; ASRC 7 to ASRC 4 never mute automatically and cannot be

muted manually.

8

ASRC_RAMP0

ASRC 3 to ASRC 0 mute disable. ASRC 3 to ASRC 0 (Channel 7 to Channel 0)

are defined as ASRC Block 0. This bit enables or disables mute ramping for

all ASRCs in Block 0. If this bit is 0b1, Bit 3 (ASRC3M), Bit 2 (ASRC2M), Bit 1

(ASRC1M), and Bit 0 (ASRC0M) are ignored, and the outputs of ASRC 3 to

ASRC 0 are active at all times.

0x0

RW

0

1

Enabled.

Disabled; ASRC 3 to ASRC 0 never mute automatically and cannot be

muted manually.

7

6

5

4

3

2

1

0

ASRC7M

ASRC6M

ASRC5M

ASRC4M

ASRC3M

ASRC2M

ASRC1M

ASRC0M

ASRC 7 manual mute.

Not muted.

Muted.

0x0

RW

0

1

ASRC 6 manual mute.

Not muted.

Muted.

0

1

ASRC 5 manual mute.

Not muted.

Muted.

0

1

ASRC 4 manual mute.

Not muted.

Muted.

0

1

ASRC 3 manual mute.

Not muted.

Muted.

0

1

ASRC 2 manual mute.

Not muted.

Muted.

0

1

ASRC 1 manual mute.

Not muted.

Muted.

0

1

ASRC 0 manual mute.

Not muted.

Muted.

0

1

Rev. A | Page 164 of 207

Data Sheet

ADAU1463/ADAU1467

ASRC Ratio Registers

Address: 0xF582 to 0xF589 (Increments of 0x1), Reset: 0x0000, Name: ASRCx_RATIO

These eight read only registers contain the sample rate conversion ratio of the corresponding ASRC on the ADAU1463 and ADAU1467,

which is calculated as the ratio between the detected input rate and the selected target output rate. The format of the value stored in these

registers is 4.12 format. For example, a ratio of 1 is shown as 0b0001000000000000 (0x1000). A ratio of 2 is shown as 0b0010000000000000

(0x2000). A ratio of 0.5 is shown as 0b0000100000000000 (0x0800).

Table 131. Bit Descriptions for ASRCx_RATIO

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

ASRC_RATIO

Output rate of the ASRC in 4.12 format. The value of this register represents

the input to output rate of the corresponding ASRC. It is stored in 4.12 format.

0x0000 RW

RAMPMAX Override Register

Address: 0xF590, Reset: 0x07FF, Name: ASRC_RAMPMAX_OVR

Table 132. Bit Descriptions for ASRC_RAMPMAX_OVR

Bits

Bit Name

Settings

Description

Reset

Access

11

OVERRIDE

RAMPMAX override enable.

Disable RAMPMAX override.

Enable RAMPMAX override.

RAMPMAX override value.

0x0

RW

0

1

[10:0]

OVR_RAMPMAX_VALUE

0x7FF

RW

ASRCx RAMPMAX Register

Address: 0xF591 to 0xF598 (Increments of 0x1), Reset: 0x07FF, Name: ASRCx_RAMPMAX

Table 133. Bit Descriptions for ASRCx_RAMPMAX

Bits

Bit Name

Settings

Description

Reset

Access

[10:0]

RAMPMAX_VALUE

RAMPMAX value (per channel).

0x7FF

RW

Rev. A | Page 165 of 207

ADAU1463/ADAU1467

Data Sheet

AUXILIARY ADC REGISTERS

Auxiliary ADC Read Value Register

Address: 0xF5A0 to 0xF5A5 (Increments of 0x1), Reset: 0x0000, Name: ADC_READx

These eight register contains the output data of the auxiliary ADC for the corresponding channel. Each of the eight channels of the ADC are

updated once per audio frame. The format for the value in this register is 6.10 format, but the top six bits are always zero, meaning that the

effective format is 0.10 format. If, for example, the input to the corresponding auxiliary ADC channel is equal to AVDD (the full-scale analog

input voltage), this register reads its maximum value of 0b0000001111111111 (0x3FF). If the input to the auxiliary ADC channel is AVDD/2,

this register reads 0b0000001000000000 (0x200). If the input to the auxiliary ADC channel is AVDD/4, this register reads

0b0000000100000000 (0x100).

Table 134. Bit Descriptions for ADC_READx

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

ADC_VALUE

ADC input value in 0.10 format, as a proportion of AVDD. Instantaneous

value of the sampled data on the ADC input. The top six bits are not used,

and the least significant 10 bits contain the value of the ADC input. The

minimum value of 0 maps to 0 V, and the maximum value of 1023 maps to

3.3 V 10% (equal to the AVDD supply). Values between 0 and 1023 are

linearly mapped to dc voltages between 0 V and AVDD.

0x0000 RW

SECONDARY I²C MASTER REGISTER

Address: 0xF5F0, Reset: 0x0000, Name: SECONDARY_I2C

This register allows the master control port to be split such that the I²C signals appear on different pins than the SPI signals. This allows an

application to use both master port protocols without external switches. Note that only one of the two protocols can be used at a time. The master

port must be reconfigured in software before using a protocol other than the one configured at boot time.

Table 135. Bit Descriptions for SECONDARY_I2C

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

R

RESERVED

SECONDARY_I2C_ENBL

Secondary I²C master enable.

I²C master drives MP24 and MP25.

I²C master drives MP2 and MP3.

0x0

RW

1

0

Rev. A | Page 166 of 207

Data Sheet

ADAU1463/ADAU1467

S/PDIF INTERFACE REGISTERS

S/PDIF Receiver Lock Bit Detection Register

Address: 0xF600, Reset: 0x0000, Name: SPDIF_LOCK_DET

This register contains a flag that monitors the S/PDIF receiver and provides a way to check the validity of the input signal.

Table 136. Bit Descriptions for SPDIF_LOCK_DET

Bits

[15:1]

0

Bit Name

RESERVED

LOCK

Settings

Description

Reset

0x0

Access

RW

S/PDIF input lock.

0x0

R

0

1

No lock acquired; no valid input stream detected.

Successful lock to input stream.

S/PDIF Receiver Control Register

Address: 0xF601, Reset: 0x0000, Name: SPDIF_RX_CTRL

This register provides controls that govern the behavior of the S/PDIF receiver on the ADAU1467 and ADAU1463.

Table 137. Bit Descriptions for SPDIF_RX_CTRL

Bits

[15:4]

3

Bit Name

RESERVED

FASTLOCK

Settings

Description

Reset

0x0

Access

RW

S/PDIF receiver locking speed.

0x0

RW

0

1

Normal (locks after 64 consecutive valid samples).

Fast (locks after eight consecutive valid samples).

2

FSOUTSTRENGTH

RX_LENGTHCTRL

S/PDIF receiver behavior in the event that lock is lost. FSOUTSTRENGTH

applies to the output of the recovered frame clock from the S/PDIF receiver.

Strong; output is continued as well as is possible when the receiver

notices a loss of lock condition, which may result in some data corruption.

Weak; output is interrupted as soon as receiver notices a loss of lock condition.

S/PDIF receiver audio word length.

0x0

RW

0

1

[1:0]

00 24 bits.

01 20 bits.

10 16 bits.

11 Automatic (determined by channel status bits detected in the input stream).

Rev. A | Page 167 of 207

ADAU1463/ADAU1467

Data Sheet

Decoded Signals From the S/PDIF Receiver Register

Address: 0xF602, Reset: 0x0000, Name: SPDIF_RX_DECODE

This register monitors the embedded nonaudio data bits in the incoming S/PDIF stream on the ADAU1463 and ADAU1467 and decodes

them, providing insight into the data format of the S/PDIF input stream.

Table 138. Bit Descriptions for SPDIF_RX_DECODE

Bits

[15:10] RESERVED

RX_WORDLENGTH_R

Bit Name

Settings

Description

Reset

0x0

Access

RW

[9:6]

[5:2]

1

S/PDIF receiver detected word length in the right channel.

0x0

R

0010 16-bit word (maximum 20 bits).

1100 17-bit word (maximum 20 bits).

0100 18-bit word (maximum 20 bits).

1000 19-bit word (maximum 20 bits).

1010 20-bit word (maximum 20 bits).

1101 21-bit word (maximum 24 bits).

0101 22-bit word (maximum 24 bits).

1001 23-bit word (maximum 24 bits).

1011 24-bit word (maximum 24 bits).

0011 20-bit word (maximum 24 bits).

S/PDIF receiver detected word length in the left channel.

0010 16-bit word (maximum 20 bits).

1100 17-bit word (maximum 20 bits).

0100 18-bit word (maximum 20 bits).

1000 19-bit word (maximum 20 bits).

1010 20-bit word (maximum 20 bits).

1101 21-bit word (maximum 24 bits).

0101 22-bit word (maximum 24 bits).

1001 23-bit word (maximum 24 bits).

1011 24-bit word (maximum 24 bits).

0011 20-bit word (maximum 24 bits).

RX_WORDLENGTH_L

0x0

R

COMPR_TYPE

AC3 or DTS compression (valid only if Bit 0 (AUDIO_TYPE) = 0b1

(compressed).

0x0

R

0

1

AC3.

DTS.

Rev. A | Page 168 of 207

Data Sheet

ADAU1463/ADAU1467

Bits

Bit Name

Settings

Description

Reset

Access

0

AUDIO_TYPE

Linear PCM or compressed audio.

Linear PCM.

Compressed.

0x0

R

0

1

Compression Mode From the S/PDIF Receiver Register

Address: 0xF603, Reset: 0x0000, Name: SPDIF_RX_COMPRMODE

If the incoming S/PDIF data on the ADAU1463 and ADAU1467 is encoded using a compression algorithm, this register displays the 16-bit

code that represents the type of compression being used.

Table 139. Bit Descriptions for SPDIF_RX_COMPRMODE

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

COMPR_MODE

Compression mode detected by the S/PDIF receiver.

0x0000

R

Automatically Resume S/PDIF Receiver Audio Input Register

Address: 0xF604, Reset: 0x0000, Name: SPDIF_RESTART

When the S/PDIF receiver on the ADAU1463 and ADAU1467 loses lock on the incoming S/PDIF signal, which can occur due to issues

with signal integrity, the receiver automatically mutes itself. This register determines whether the S/PDIF receiver then automatically

resumes outputting data if the S/PDIF receiver subsequently begins to receive valid data and a lock condition is reattained. By default, the

S/PDIF receiver does not automatically resume audio when lock is lost (Register 0xF604 (SPDIF_RESTART), Bit 0 (RESTART_AUDIO) =

0b0); and, therefore, the user must manually reset the S/PDIF receiver by toggling Register 0xF604 (SPDIF_RESTART), Bit 0

(RESTART_AUDIO), from 0b0 to 0b1 and then back to 0b0 again. To ensure that the S/PDIF receiver always begins outputting data when a

valid input signal is detected, set Register 0xF604 (SPDIF_RESTART), Bit 0 (RESTART_AUDIO), to 0b1 at all times.

Table 140. Bit Descriptions for SPDIF_RESTART

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

RESTART_AUDIO

Allows the S/PDIF receiver to automatically resume outputting audio

when it successfully recovers from a loss of lock.

0x0

RW

0

1

Do not automatically restart the audio when a relock occurs.

Restarts the audio automatically when a relock occurs, and resets

Register 0xF605 (SPDIF_LOSS_OF_LOCK), Bit 0 (LOSS_OF_LOCK).

Rev. A | Page 169 of 207

ADAU1463/ADAU1467

Data Sheet

S/PDIF Receiver Loss of Lock Detection Register

Address: 0xF605, Reset: 0x0000, Name: SPDIF_LOSS_OF_LOCK

This bit monitors the S/PDIF lock status and checks to see if the lock is lost during operation of the S/PDIF receiver on the ADAU1467

and ADAU1463. This condition can arise when, for example, a valid S/PDIF input signal was present for an extended period of time, but

signal integrity worsened for a brief period, causing the receiver to then lose its lock to the input signal. In this case, Bit 0 (LOSS_OF_LOCK)

transitions from 0b0 to 0b1 and remains set at 0b1 indefinitely. This indicates that, at some point during the operation of the device, lock

to the input stream was lost. Bit 0 (LOSS_OF_LOCK) stays high at 0b1 until Register 0xF604 (SPDIF_RESTART), Bit 0 (RESTART_AUDIO), is

set to 0b1, which clears Bit 0 (LOSS_OF_LOCK) back to 0b0. At that point, Register 0xF604 (SPDIF_RESTART), Bit 0 (RESTART_AUDIO), can

be reset to 0b0 if required.

Table 141. Bit Descriptions for SPDIF_LOSS_OF_LOCK

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

LOSS_OF_LOCK

S/PDIF loss of lock detection (sticky bit).

0x0

R

0

1

S/PDIF receiver is locked to the input stream and has not lost lock since

acquiring the input signal.

S/PDIF receiver acquired a lock on the input stream but then subsequently

lost lock.

S/PDIF RECEIVER MCLK SPEED SELECTION REGISTER

Address: 0xF606, Reset: 0x0001, Name: SPDIF_RX_MCLKSPEED

Table 142. Bit Descriptions for SPDIF_RX_MCLKSPEED

Bits

[15:1]

0

Bit Name

Description

Reset

Access

RW

RESERVED

Reserved.

0x0000

0x1

RX_MCLKSPEED

S/PDIF Rx clock speed.

0: SYSCLK (higher rates).

1: SYSCLK 2 (lower rates).

RW

Rev. A | Page 170 of 207

Data Sheet

ADAU1463/ADAU1467

S/PDIF TRANSMITTER MCLK SPEED SELECTION REGISTER

Address: 0xF607, Reset: 0x0001, Name: SPDIF_TX_MCLKSPEED

Table 143. Bit Descriptions for SPDIF_TX_MCLKSPEED

Bits

[15:1]

0

Bit Name

Description

Reset

0x0000

0x1

Access

RW

RESERVED

Reserved.

TX_MCLKSPEED

S/PDIF Rx clock speed.

0: SYSCLK (higher rates).

1: SYSCLK/2 (lower rates).

RW

S/PDIF Receiver Auxiliary Outputs Enable Register

Address: 0xF608, Reset: 0x0000, Name: SPDIF_AUX_EN

The S/PDIF receiver on the ADAU1467 and ADAU1463 decodes embedded nonaudio data bits on the incoming data stream, including

channel status, user data, validity bits, and parity bits. This information, together with the decoded audio data, can optionally be output

on one of the SDATA_OUTx pins using Register 0xF608 (SPDIF_AUX_EN). The serial output port selected by Bits[3:0] (TDMOUT)

outputs an 8-channel TDM stream containing this decoded information.

•

Channel 0 in the TDM8 stream contains the 24 audio bits from the left S/PDIF input channel, followed by eight zero bits.

Channel 1 in the TDM8 stream contains 20 zero bits, the parity bit, validity bit, user data bit, and the channel status bit from the left

S/PDIF input channel, followed by eight zero bits.

•

Channel 2 in the TDM8 stream contains 22 zero bits, followed by the compression type bit (0b0 represents AC3 and 0b1 represents

DTS) and the audio type bit (0b0 represents PCM and 0b1 represents compressed), followed by eight zero bits.

Channel 3 in the TDM8 stream contains 32 zero bits.

Channel 4 in the TDM8 stream contains the 24 audio bits from the right S/PDIF input channel, followed by eight zero bits.

Channel 5 in the TDM8 stream contains 20 zero bits followed by the parity bit, validity bit, user data bit, and channel status bit from

the right S/PDIF input channel, followed by eight zero bits.

•

Channel 6 in the TDM8 stream contains 32 zero bits.

Channel 7 in the TDM8 stream contains 23 zero bits, the block start bit, and eight zero bits.

Rev. A | Page 171 of 207

ADAU1463/ADAU1467

Data Sheet

Table 144. Bit Descriptions for SPDIF_AUX_EN

Bits

Bit Name

Settings

Description

Reset Access

[15:5] RESERVED

Reserved.

0x0

RW

4

TDMOUT_CLK

S/PDIF TDM clock source. When Bits[3:0] (TDMOUT) are configured to output S/PDIF

receiver data on one of the SDATA_OUTx pins, the corresponding serial port must be

set in master mode; and Bit 4 (TDMOUT_CLK) configures which clock signals are used

on the corresponding BCLK_OUTx and LRCLK_OUTx pins. If Bit 4 (TDMOUT_CLK) =

0b0, the clock signals recovered from the S/PDIF input signal are used to clock the

serial output. If Bit 4 (TDMOUT_CLK) = 0b1, the output of Clock Generator 3 is used to

clock serial output; and Register 0xF026 (CLK_GEN3_SRC), Bits[3:0] (FREF_PIN), must be

0b1110, and Register 0xF026 (CLK_GEN3_SRC), Bit 4 (CLK_GEN3_SRC), must be 0b1.

0

1

Use clocks derived from S/PDIF receiver stream.

Use filtered clocks from internal clock generator.

S/PDIF TDM output channel selection.

[3:0]

TDMOUT

0x0

RW

0001 Output on SDATA_OUT0.

0010 Output on SDATA_OUT1.

0100 Output on SDATA_OUT2.

1000 Output on SDATA_OUT3.

0000 Disable S/PDIF TDM output.

S/PDIF Receiver Auxiliary Bits Ready Flag Register

Address: 0xF60F, Reset: 0x0000, Name: SPDIF_RX_AUXBIT_READY

The decoded channel status, user data, validity, and parity bits are recovered from the input signal one frame at a time until a full block of

192 frames is received on the ADAU1463 and ADAU1467. When all of the 192 frames are received and decoded, Bit 0 (AUXBITS_READY),

changes state from 0b0 to 0b1, indicating that the full block of data is recovered and is available to be read from the corresponding registers.

Table 145. Bit Descriptions for SPDIF_RX_AUXBIT_READY

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

AUXBITS_READY

Auxiliary bits are ready flag.

Auxiliary bits are not ready to be output.

Auxiliary bits are ready to be output.

0x0

R

0

1

S/PDIF Receiver Channel Status Bits (Left) Register

Address: 0xF610 to 0xF61B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_CS_LEFT_x

These 12 registers store the 192 channel status bits decoded from the left channel of the S/PDIF input stream on the ADAU1463 and

ADAU1467.

Table 146. Bit Descriptions for SPDIF_RX_CS_LEFT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_RX_CS_LEFT

S/PDIF receiver channel status bits (left).

0x0000

R

Rev. A | Page 172 of 207

Data Sheet

ADAU1463/ADAU1467

S/PDIF Receiver Channel Status Bits (Right) Register

Address: 0xF620 to 0xF62B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_CS_RIGHT_x

These 12 registers store the 192 channel status bits decoded from the right channel of the S/PDIF input stream on the ADAU1463 and

ADAU1467.

Table 147. Bit Descriptions for SPDIF_RX_CS_RIGHT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_RX_CS_RIGHT

S/PDIF receiver channel status bits (right).

0x0000

R

S/PDIF Receiver User Data Bits (Left) Register

Address: 0xF630 to 0xF63B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_UD_LEFT_x

These 12 registers store the 192 user data bits decoded from the left channel of the S/PDIF input stream on the ADAU1463 and

ADAU1467.

Table 148. Bit Descriptions for SPDIF_RX_UD_LEFT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_RX_UD_LEFT

S/PDIF receiver user data bits (left).

0x0000

R

S/PDIF Receiver User Data Bits (Right) Register

Address: 0xF640 to 0xF64B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_UD_RIGHT_x

These 12 registers store the 192 user data bits decoded from the right channel of the S/PDIF input stream on the ADAU1463 and

ADAU1467.

Table 149. Bit Descriptions for SPDIF_RX_UD_RIGHT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_RX_UD_RIGHT

S/PDIF receiver user data bits (right).

0x0000

R

Rev. A | Page 173 of 207

ADAU1463/ADAU1467

Data Sheet

S/PDIF Receiver Validity Bits (Left) Register

Address: 0xF650 to 0xF65B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_VB_LEFT_x

These 12 registers store the 192 validity bits decoded from the left channel of the S/PDIF input stream on the ADAU1463 and ADAU1467.

Table 150. Bit Descriptions for SPDIF_RX_VB_LEFT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_RX_VB_LEFT

S/PDIF receiver validity bits (left).

0x0000

R

S/PDIF Receiver Validity Bits (Right) Register

Address: 0xF660 to 0xF66B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_VB_RIGHT_x

These 12 registers store the 192 validity bits decoded from the left channel of the S/PDIF input stream on the ADAU1463 and ADAU1467.

Table 151. Bit Descriptions for SPDIF_RX_VB_RIGHT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_RX_VB_RIGHT

S/PDIF receiver validity bits (right).

0x0000

R

S/PDIF Receiver Parity Bits (Left) Register

Address: 0xF670 to 0xF67B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_PB_LEFT_x

These 12 registers store the 192 parity bits decoded from the left channel of the S/PDIF input stream on the ADAU1463 and ADAU1467.

Table 152. Bit Descriptions for SPDIF_RX_PB_LEFT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_RX_PB_LEFT

S/PDIF receiver parity bits (left).

0x0000

R

S/PDIF Receiver Parity Bits (Right) Register

Address: 0xF680 to 0xF68B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_PB_RIGHT_x

These 12 registers store the 192 parity bits decoded from the right channel of the S/PDIF input stream on the ADAU1463 and ADAU1467.

Table 153. Bit Descriptions for SPDIF_RX_PB_RIGHT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_RX_PB_RIGHT

S/PDIF receiver parity bits (right).

0x0000

R

Rev. A | Page 174 of 207

Data Sheet

ADAU1463/ADAU1467

S/PDIF Transmitter Enable Register

Address: 0xF690, Reset: 0x0000, Name: SPDIF_TX_EN

This register enables or disables the S/PDIF transmitter on the ADAU1463 and ADAU1467. When the transmitter is disabled, it outputs a

constant stream of zero data. When the S/PDIF transmitter is disabled, it still consumes power. To power down the S/PDIF transmitter for

the purpose of power savings, set Register 0xF051 (POWER_ENABLE1), Bit 2 (TX_PWR) = 0b0.

Table 154. Bit Descriptions for SPDIF_TX_EN

Bits

[15:1]

0

Bit Name

RESERVED

TXEN

Settings

Description

Reset

0x0

Access

RW

S/PDIF transmitter output enable.

0x0

RW

0

1

Disabled.

Enabled.

S/PDIF Transmitter Control Register

Address: 0xF691, Reset: 0x0000, Name: SPDIF_TX_CTRL

This register controls the length of the audio data-words output by the S/PDIF transmitter on the ADAU1467 and ADAU1463. The

maximum word length is 24 bits. If a shorter word length is selected using Bits[1:0] (TX_LENGTHCTRL), the extraneous bits are

truncated, starting with the least significant bit. If Bits[1:0] (TX_LENGTHCTRL) = 0b11, the decoded channel status bits on the input

stream of the S/PDIF receiver automatically set the word length on the S/PDIF transmitter.

Table 155. Bit Descriptions for SPDIF_TX_CTRL

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

[15:2]

[1:0]

RESERVED

TX_LENGTHCTRL

S/PDIF transmitter audio word length.

0x0

RW

00 24 bits.

01 20 bits.

10 16 bits.

11 Automatic (determined by channel status bits detected in the S/PDIF

input stream).

Rev. A | Page 175 of 207

ADAU1463/ADAU1467

Data Sheet

S/PDIF Transmitter Auxiliary Bits Source Select Register

Address: 0xF69F, Reset: 0x0000, Name: SPDIF_TX_AUXBIT_SOURCE

This register configures whether the encoded nonaudio data bits in the output data stream of the S/PDIF transmitter on the ADAU1463

and ADAU1467 are copied directly from the S/PDIF receiver or set manually using the corresponding control registers. If the data is

configured manually, all channel status, parity, user data, and validity bits can be manually set using the following registers: SPDIF_

TX_CS_LEFT_x, SPDIF_TX_CS_RIGHT_x, SPDIF_TX_UD_LEFT_x, SPDIF_TX_UD_RIGHT_x, SPDIF_TX_VB_LEFT_x,

SPDIF_TX_VB_RIGHT_x, SPDIF_TX_PB_LEFT_x, and SPDIF_TX_PB_RIGHT_x.

Table 156. Bit Descriptions for SPDIF_TX_AUXBIT_SOURCE

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

TX_AUXBITS_SOURCE

Auxiliary bits source.

0x0

RW

0

1

Source from register map (user programmable)

Source from S/PDIF receiver (derived from input data stream)

S/PDIF Transmitter Channel Status Bits (Left) Register

Address: 0xF6A0 to 0xF6AB (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_CS_LEFT_x

These 12 registers allow the 192 channel status bits encoded on the left channel of the output data stream of the S/PDIF transmitter on the

ADAU1463 and ADAU1467 to be configured manually. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F

(SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0.

Table 157. Bit Descriptions for SPDIF_TX_CS_LEFT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_TX_CS_LEFT

S/PDIF transmitter channel status bits (left).

0x0000 RW

S/PDIF Transmitter Channel Status Bits (Right) Register

Address: 0xF6B0 to 0xF6BB (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_CS_RIGHT_x

These 12 registers allow the 192 channel status bits encoded on the right channel of the output data stream of the S/PDIF transmitter on the

ADAU1463 and ADAU1467 to be configured manually. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F

(SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0.

Table 158. Bit Descriptions for SPDIF_TX_CS_RIGHT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_TX_CS_RIGHT

S/PDIF receiver channel status bits (right).

0x0000 RW

Rev. A | Page 176 of 207

Data Sheet

ADAU1463/ADAU1467

S/PDIF Transmitter User Data Bits (Left) Register

Address: 0xF6C0 to 0xF6CB (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_UD_LEFT_x

These 12 registers allow the 192 user data bits encoded on the left channel of the output data stream of the S/PDIF transmitter on the ADAU1467

and ADAU1463 to be configured manually. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F

(SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0.

Table 159. Bit Descriptions for SPDIF_TX_UD_LEFT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_TX_UD_LEFT

S/PDIF transmitter user data bits (left).

0x0000 RW

S/PDIF Transmitter User Data Bits (Right) Register

Address: 0xF6D0 to 0xF6DB (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_UD_RIGHT_x

These 12 registers allow the 192 user data bits encoded on the right channel of the output data stream of the S/PDIF transmitter on the

ADAU1463 and ADAU1467 to be configured manually. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F

(SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0.

Table 160. Bit Descriptions for SPDIF_TX_UD_RIGHT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_TX_UD_RIGHT

S/PDIF transmitter user data bits (right).

0x0000 RW

S/PDIF Transmitter Validity Bits (Left) Register

Address: 0xF6E0 to 0xF6EB (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_VB_LEFT_x

These 12 registers allow the 192 validity bits encoded on the left channel of the output data stream of the S/PDIF transmitter on the

ADAU1463 and ADAU1467 to be configured manually. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F

(SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0.

Table 161. Bit Descriptions for SPDIF_TX_VB_LEFT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_TX_VB_LEFT

S/PDIF transmitter validity bits (left).

0x0000 RW

Rev. A | Page 177 of 207

ADAU1463/ADAU1467

Data Sheet

S/PDIF Transmitter Validity Bits (Right) Register

Address: 0xF6F0 to 0xF6FB (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_VB_RIGHT_x

These 12 registers allow the 192 validity bits encoded on the right channel of the output data stream of the S/PDIF transmitter on the

ADAU1463 and ADAU1467 to be configured manually. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F

(SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0.

Table 162. Bit Descriptions for SPDIF_TX_VB_RIGHT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_TX_VB_RIGHT

S/PDIF transmitter validity bits (right).

0x0000 RW

S/PDIF Transmitter Parity Bits (Left) Register

Address: 0xF700 to Address 0xF70B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_PB_LEFT_x

These 12 registers allow the 192 parity bits encoded on the left channel of the output data stream of the S/PDIF transmitter on the

ADAU1463 and ADAU1467 to be configured manually. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F

(SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0.

Table 163. Bit Descriptions for SPDIF_TX_PB_LEFT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_TX_PB_LEFT

S/PDIF transmitter parity bits (left).

0x0000 RW

S/PDIF Transmitter Parity Bits (Right) Register

Address: 0xF710 to Address 0xF71B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_PB_RIGHT_x

These 12 registers allow the 192 parity bits encoded on the right channel of the output data stream of the S/PDIF transmitter on the

ADAU1463 and ADAU1467 to be configured manually. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F

(SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0.

Table 164. Bit Descriptions for SPDIF_TX_PB_RIGHT_x

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

SPDIF_TX_PB_RIGHT

S/PDIF transmitter parity bits (right).

0x0000 RW

Rev. A | Page 178 of 207

Data Sheet

ADAU1463/ADAU1467

HARDWARE INTERFACING REGISTERS

BCLK Input Pins Drive Strength and Slew Rate Register

Address: 0xF780 to 0xF783 (Increments of 0x1), Reset: 0x0018, Name: BCLK_INx_PIN

These registers configure the drive strength, slew rate, and pull resistors for the BCLK_INx pins. Register 0xF780 corresponds to BCLK_IN0,

Register 0xF781 corresponds to BCLK_IN1, Register 0xF782 corresponds to BCLK_IN2, and Register 0xF783 corresponds to BCLK_IN3.

Table 165. Bit Descriptions for BCLK_INx_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

BCLK_IN_PULL

BCLK_INx pull-down.

Pull-down disabled.

Pull-down enabled.

BCLK_INx slew rate.

0x1

RW

0

1

[3:2]

[1:0]

BCLK_IN_SLEW

BCLK_IN_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

BCLK_INx drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 179 of 207

ADAU1463/ADAU1467

Data Sheet

BCLK Output Pins Drive Strength and Slew Rate Register

Address: 0xF784 to 0xF787 (Increments of 0x1), Reset: 0x0018, Name: BCLK_OUTx_PIN

These registers configure the drive strength, slew rate, and pull resistors for the BCLK_OUTx pins. Register 0xF784 corresponds to

BCLK_OUT0, Register 0xF785 corresponds to BCLK_OUT1, Register 0xF786 corresponds to BCLK_OUT2, and Register 0xF787

corresponds to BCLK_OUT3.

Table 166. Bit Descriptions for BCLK_OUTx_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

BCLK_OUT_PULL

BCLK_OUTx pull-down.

Pull-down disabled.

Pull-down enabled.

BCLK_OUTx slew rate.

0x1

RW

0

1

[3:2]

[1:0]

BCLK_OUT_SLEW

BCLK_OUT_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

BCLK_OUTx drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 180 of 207

Data Sheet

ADAU1463/ADAU1467

LRCLK Input Pins Drive Strength and Slew Rate Register

Address: 0xF788 to 0xF78B (Increments of 0x1), Reset: 0x0018, Name: LRCLK_INx_PIN

These registers configure the drive strength, slew rate, and pull resistors for the LRCLK_INx pins. Register 0xF788 corresponds to

LRCLK_IN0/MP10, Register 0xF789 corresponds to LRCLK_IN1/MP11, Register 0xF78A corresponds to LRCLK_IN2/MP12, and

Register 0xF78B corresponds to LRCLK_IN3/MP13.

Table 167. Bit Descriptions for LRCLK_INx_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

LRCLK_IN_PULL

LRCLK_INx pull-down.

Pull-down disabled.

Pull-down enabled.

LRCLK_INx slew rate.

0x1

RW

0

1

[3:2]

[1:0]

LRCLK_IN_SLEW

LRCLK_IN_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

LRCLK_INx drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 181 of 207

ADAU1463/ADAU1467

Data Sheet

LRCLK Output Pins Drive Strength and Slew Rate Register

Address: 0xF78C to 0xF78F (Increments of 0x1), Reset: 0x0018, Name: LRCLK_OUTx_PIN

These registers configure the drive strength, slew rate, and pull resistors for the LRCLK_OUTx pins. Register 0xF78C corresponds to

LRCLK_OUT0/MP4, Register 0xF78D corresponds to LRCLK_OUT1/MP5, Register 0xF78E corresponds to LRCLK_OUT2/MP8, and

Register 0xF78F corresponds to LRCLK_OUT3/MP9.

Table 168. Bit Descriptions for LRCLK_OUTx_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

LRCLK_OUT_PULL

LRCLK_OUTx pull-down.

Pull-down disabled.

Pull-down enabled.

LRCLK_OUTx slew rate.

0x1

RW

0

1

[3:2]

[1:0]

LRCLK_OUT_SLEW

LRCLK_OUT_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

LRCLK_OUTx drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 182 of 207

Data Sheet

ADAU1463/ADAU1467

SDATA Input Pins Drive Strength and Slew Rate Register

Address: 0xF790 to 0xF793 (Increments of 0x1), Reset: 0x0018, Name: SDATA_INx_PIN

These registers configure the drive strength, slew rate, and pull resistors for the SDATA_INx pins. Register 0xF790 corresponds to SDATA_IN0,

Register 0xF791 corresponds to SDATA_IN1, Register 0xF792 corresponds to SDATA_IN2, and Register 0xF793 corresponds to SDATA_IN3.

Table 169. Bit Descriptions for SDATA_INx_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

SDATA_IN_PULL

SDATA_INx pull-down.

Pull-down disabled.

Pull-down enabled.

SDATA_INx slew rate.

0x1

RW

0

1

[3:2]

[1:0]

SDATA_IN_SLEW

SDATA_IN_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

SDATA_INx drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 183 of 207

ADAU1463/ADAU1467

Data Sheet

SDATA Output Pins Drive Strength and Slew Rate Register

Address: 0xF794 to 0xF797 (Increments of 0x1), Reset: 0x0008, Name: SDATA_OUTx_PIN

These registers configure the drive strength, slew rate, and pull resistors for the SDATA_OUTx pins. Register 0xF794 corresponds to

SDATA_OUT0, Register 0xF795 corresponds to SDATA_OUT1, Register 0xF796 corresponds to SDATA_OUT2, and Register 0xF797

corresponds to SDATA_OUT3.

Table 170. Bit Descriptions for SDATA_OUTx_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

SDATA_OUT_PULL

SDATA_OUTx pull-down.

Pull-down disabled.

Pull-down enabled.

SDATA_OUTx slew rate.

0x0

RW

0

1

[3:2]

[1:0]

SDATA_OUT_SLEW

SDATA_OUT_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

SDATA_OUTx drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 184 of 207

Data Sheet

ADAU1463/ADAU1467

S/PDIF Transmitter Pin Drive Strength and Slew Rate Register

Address: 0xF798, Reset: 0x0008, Name: SPDIF_TX_PIN

This register configures the drive strength, slew rate, and pull resistors for the SPDIFOUT pin on the ADAU1467 and ADAU1463.

Table 171. Bit Descriptions for SPDIF_TX_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

SPDIF_TX_PULL

SPDIFOUT pull-down.

Pull-down disabled.

Pull-down enabled.

SPDIFOUT slew rate.

0x0

RW

0

1

[3:2]

[1:0]

SPDIF_TX_SLEW

SPDIF_TX_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

SPDIFOUT drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 185 of 207

ADAU1463/ADAU1467

Data Sheet

SCLK/SCL Pin Drive Strength and Slew Rate Register

Address: 0xF799, Reset: 0x0008, Name: SCLK_SCL_PIN

This register configures the drive strength, slew rate, and pull resistors for the SCLK/SCL pin.

Table 172. Bit Descriptions for SCLK_SCL_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

SCLK_SCL_PULL

SCLK/SCL pull-up.

Pull-up disabled.

Pull-up enabled.

SCLK/SCL slew rate.

0x0

RW

0

1

[3:2]

[1:0]

SCLK_SCL_SLEW

SCLK_SCL_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

SCLK/SCL drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 186 of 207

Data Sheet

ADAU1463/ADAU1467

MISO/SDA Pin Drive Strength and Slew Rate Register

Address: 0xF79A, Reset: 0x0008, Name: MISO_SDA_PIN

This register configures the drive strength, slew rate, and pull resistors for the MISO/SDA pin.

Table 173. Bit Descriptions for MISO_SDA_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

MISO_SDA_PULL

MISO/SDA pull-up.

Pull-up disabled.

Pull-up enabled.

MISO/SDA slew rate.

0x0

RW

0

1

[3:2]

[1:0]

MISO_SDA_SLEW

MISO_SDA_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

MISO/SDA drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 187 of 207

ADAU1463/ADAU1467

Data Sheet

SS/ADDR0 Pin Drive Strength and Slew Rate Register

Address: 0xF79B, Reset: 0x0018, Name: SS_PIN

This register configures the drive strength, slew rate, and pull resistors for the SS/ADDR0 pin.

Table 174. Bit Descriptions for SS_PIN

Bits

[15:5]

4

Bit Name

RESERVED

SS_PULL

Settings

Description

Reset

0x0

Access

RW

Reserved.

SS/ADDR0 pull-up.

Pull-up disabled.

Pull-up enabled.

SS/ADDR0 slew rate.

0x1

RW

0

1

[3:2]

[1:0]

SS_SLEW

SS_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

SS/ADDR0 drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 188 of 207

Data Sheet

ADAU1463/ADAU1467

MOSI/ADDR1 Pin Drive Strength and Slew Rate Register

Address: 0xF79C, Reset: 0x0018, Name: MOSI_ADDR1_PIN

This register configures the drive strength, slew rate, and pull resistors for the MOSI/ADDR1 pin.

Table 175. Bit Descriptions for MOSI_ADDR1_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

MOSI_ADDR1_PULL

MOSI/ADDR1 pull-up.

Pull-up disabled.

Pull-up enabled.

MOSI/ADDR1 slew rate.

0x1

RW

0

1

[3:2]

[1:0]

MOSI_ADDR1_SLEW

MOSI_ADDR1_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

MOSI/ADDR1 drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 189 of 207

ADAU1463/ADAU1467

Data Sheet

SCL_M/SCLK_M/MP2 Pin Drive Strength and Slew Rate Register

Address: 0xF79D, Reset: 0x0008, Name: SCLK_SCL_M_PIN

This register configures the drive strength, slew rate, and pull resistors for the SCL_M/SCLK_M/MP2 pin.

Table 176. Bit Descriptions for SCLK_SCL_M_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

SCLK_SCL_M_PULL

SCL_M/SCLK_M/MP2 pull-up.

Pull-up disabled.

Pull-up enabled.

0x0

RW

0

1

[3:2]

[1:0]

SCLK_SCL_M_SLEW

SCLK_SCL_M_DRIVE

SCL_M/SCLK_M/MP2 slew rate.

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

0x2

0x0

RW

SCL_M/SCLK_M/MP2 drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 190 of 207

Data Sheet

ADAU1463/ADAU1467

SDA_M/MISO_M/MP3 Pin Drive Strength and Slew Rate Register

Address: 0xF79E, Reset: 0x0008, Name: MISO_SDA_M_PIN

This register configures the drive strength, slew rate, and pull resistors for the SDA_M/MISO_M/MP3 pin.

Table 177. Bit Descriptions for MISO_SDA_M_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

MISO_SDA_M_PULL

SDA_M/MISO_M/MP3 pull-up.

Pull-up disabled.

Pull-up enabled.

0x0

RW

0

1

[3:2]

[1:0]

MISO_SDA_M_SLEW

MISO_SDA_M_DRIVE

SDA_M/MISO_M/MP3 slew rate.

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

0x2

0x0

RW

SDA_M/MISO_M/MP3 drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 191 of 207

ADAU1463/ADAU1467

Data Sheet

SS_M/MP0 Pin Drive Strength and Slew Rate Register

Address: 0xF79F, Reset: 0x0018, Name: SS_M_PIN

This register configures the drive strength, slew rate, and pull resistors for the SS_M/MP0 pin.

Table 178. Bit Descriptions for SS_M_PIN

Bits

[15:5]

4

Bit Name

RESERVED

SS_M_PULL

Settings

Description

Reset

0x0

Access

RW

Reserved.

SS_M/MP0 pull-up.

Pull-up disabled.

Pull-up enabled.

SS_M/MP0 slew rate.

0x1

RW

0

1

[3:2]

[1:0]

SS_M_SLEW

SS_M_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

SS_M/MP0 drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 192 of 207

Data Sheet

ADAU1463/ADAU1467

MOSI_M/MP1 Pin Drive Strength and Slew Rate Register

Address: 0xF7A0, Reset: 0x0018, Name: MOSI_M_PIN

This register configures the drive strength, slew rate, and pull resistors for the MOSI_M/MP1 pin.

Table 179. Bit Descriptions for MOSI_M_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

MOSI_M_PULL

MOSI_M/MP1 pull-up.

Pull-up disabled.

Pull-up enabled.

MOSI_M/MP1 slew rate.

0x1

RW

0

1

[3:2]

[1:0]

MOSI_M_SLEW

MOSI_M_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

MOSI_M/MP1 drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 193 of 207

ADAU1463/ADAU1467

Data Sheet

MP6 Pin Drive Strength and Slew Rate Register

Address: 0xF7A1, Reset: 0x0018, Name: MP6_PIN

This register configures the drive strength, slew rate, and pull resistors for the MP6 pin.

Table 180. Bit Descriptions for MP6_PIN

Bits

[15:5]

4

Bit Name

RESERVED

MP6_PULL

Settings

Description

Reset

0x0

Access

RW

Reserved.

MP6 pull-down.

Pull-down disabled.

Pull-down enabled.

MP6 slew rate.

0x1

RW

0

1

[3:2]

[1:0]

MP6_SLEW

MP6_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

MP6 drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 194 of 207

Data Sheet

ADAU1463/ADAU1467

MP7 Pin Drive Strength and Slew Rate Register

Address: 0xF7A2, Reset: 0x0018, Name: MP7_PIN

This register configures the drive strength, slew rate, and pull resistors for the MP7 pin.

Table 181. Bit Descriptions for MP7_PIN

Bits

[15:5]

4

Bit Name

RESERVED

MP7_PULL

Settings

Description

Reset

0x0

Access

RW

Reserved.

MP7 pull-down.

Pull-down disabled.

Pull-down enabled.

MP7 slew rate.

0x1

RW

0

1

[3:2]

[1:0]

MP7_SLEW

MP7_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

MP7 drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 195 of 207

ADAU1463/ADAU1467

Data Sheet

CLKOUT Pin Drive Strength and Slew Rate Register

Address: 0xF7A3, Reset: 0x0008, Name: CLKOUT_PIN

This register configures the drive strength, slew rate, and pull resistors for the CLKOUT pin.

Table 182. Bit Descriptions for CLKOUT_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

Reserved.

CLKOUT_PULL

CLKOUT pull-down.

Pull-down disabled.

Pull-down enabled.

CLKOUT slew rate.

0x0

RW

0

1

[3:2]

[1:0]

CLKOUT_SLEW

CLKOUT_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

CLKOUT drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 196 of 207

Data Sheet

ADAU1463/ADAU1467

MP14 PIN DRIVE STRENGTH AND SLEW RATE REGISTER

Address: 0xF7A8, Reset: 0x0018, Name: MP14_PIN

This register configures the drive strength, slew rate, and pull resistors for the MP14 pin.

Table 183. Bit Descriptions for MP14_PIN

Bits

[15:5]

4

Bit Name

RESERVED

MP14_PULL

Settings

Description

Reset

0x0

Access

R

MP14 pull-down.

Pull-down disabled.

Pull-down enabled.

MP14 slew rate.

0x1

RW

0

1

[3:2]

[1:0]

MP14_SLEW

MP14_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

MP14 drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 197 of 207

ADAU1463/ADAU1467

Data Sheet

MP15 PIN DRIVE STRENGTH AND SLEW RATE REGISTER

Address: 0xF7A9, Reset: 0x0018, Name: MP15_PIN

This register configures the drive strength, slew rate, and pull resistors for the MP15 pin.

Table 184. Bit Descriptions for MP15_PIN

Bits

[15:5]

4

Bit Name

RESERVED

MP15_PULL

Settings

Description

Reset

0x0

Access

R

MP15 pull-down.

Pull-down disabled.

Pull-down enabled.

MP15 slew rate.

0x1

RW

0

1

[3:2]

[1:0]

MP15_SLEW

MP15_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

MP15 drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 198 of 207

Data Sheet

ADAU1463/ADAU1467

SDATA IN/OUT PINS DRIVE STRENGTH AND SLEW RATE REGISTERS

Address: 0xF7B0 to 0xF7B7, Reset: 0x0018, Name: SDATAIOx_PIN

This register configures the drive strength, slew rate, and pull resistors for the SDATIO0 pin.

Table 185. Bit Descriptions for SDATA_IO0_PIN

Bits

[15:5]

4

Bit Name

Settings

Description

Reset

0x0

Access

R

RESERVED

SDATA_IO_PULL

SDATA_IO pull-down.

Pull-down disabled.

Pull-down enabled.

SDATA_IO slew rate.

0x1

RW

0

1

[3:2]

[1:0]

SDATA_IO_SLEW

SDATA_IO_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

SDATA_IO drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 199 of 207

ADAU1463/ADAU1467

Data Sheet

MP24 PIN DRIVE STRENGTH AND SLEW RATE REGISTER

Address: 0xF7B8, Reset: 0x0018, Name: MP24_PIN

This register configures the drive strength, slew rate, and pull resistors for the MP24 pin.

Table 186. Bit Descriptions for MP24_PIN

Bits

[15:5]

4

Bit Name

RESERVED

MP24_PULL

Settings

Description

Reset

0x000

0x0

Access

R

MP24 pull-up.

RW

0

1

Pull-up disabled.

Pull-up enabled.

MP24 slew rate.

[3:2]

[1:0]

MP24_SLEW

MP24_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

MP24 drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 200 of 207

Data Sheet

ADAU1463/ADAU1467

MP25 PIN DRIVE STRENGTH AND SLEW RATE REGISTER

Address: 0xF7B9, Reset: 0x0018, Name: MP25_PIN

This register configures the drive strength, slew rate, and pull resistors for the MP25 pin.

Table 187. Bit Descriptions for MP25_PIN

Bits

[15:5]

4

Bit Name

RESERVED

MP25_PULL

Settings

Description

Reset

0x000

0x0

Access

R

MP25 pull-up.

RW

0

1

Pull-up disabled.

Pull-up enabled.

MP25 slew rate.

[3:2]

[1:0]

MP25_SLEW

MP25_DRIVE

0x2

0x0

RW

00 Slowest.

01 Slow.

10 Fast.

11 Fastest.

MP25 drive strength.

00 Lowest.

01 Low.

10 High.

11 Highest.

Rev. A | Page 201 of 207

ADAU1463/ADAU1467

Data Sheet

SOFT RESET REGISTER

Address: 0xF890, Reset: 0x0001, Name: SOFT_RESET

SOFT_RESET provides the capability to reset all control registers in the device or put it into a state similar to a hardware reset, where the

RESET

pin is pulled low to ground. All control registers are reset to their default values, except for the PLL registers: Register 0xF000

(PLL_CTRL0), Register 0xF001 (PLL_CTRL1), Register 0xF002 (PLL_CLK_SRC), Register 0xF003 (PLL_ENABLE), Register 0xF004

(PLL_LOCK), Register 0xF005 (MCLK_OUT), and Register 0xF006 (PLL_WATCHDOG), as well as registers related to the panic manager.

The I²C and SPI slave ports remain operational, and the user can write new values to the PLL registers while the soft reset is active. If SPI

slave mode is enabled, the device remains in SPI slave mode during and after the soft reset state. To reset the device to I²C slave mode, the

RESET

device must undergo a hardware reset by pulling the

pin low to ground. Bit 0 (SOFT_RESET) is active low, meaning that setting

it to 0b1 enables normal operation and setting it to 0b0 enables the soft reset state.

Table 188. Bit Descriptions for SOFT_RESET

Bits

[15:1]

0

Bit Name

Settings

Description

Reset

0x0

Access

RW

RESERVED

SOFT_RESET

Reserved.

Soft reset.

0x1

RW

0

1

Soft reset enabled.

Soft reset disabled; normal operation.

Rev. A | Page 202 of 207

Data Sheet

ADAU1463/ADAU1467

APPLICATIONS INFORMATION

BULK BYPASS CAPACITORS

AVDD PVDD IOVDD DVDD

PCB DESIGN CONSIDERATIONS

3.3V

A solid ground plane is necessary for maintaining signal

integrity and minimizing EMI radiation. If the PCB has two

ground planes, they can be stitched together using vias that are

spread evenly throughout the PCB.

+

10µF

Figure 85. Bulk Bypass Capacitor Schematic

Power Supply Bypass Capacitors

Component Placement

Bypass each power supply pin to its nearest appropriate ground

pin with a single 100 nF capacitor and, optionally, with an

additional 10 nF capacitor in parallel. Make the connections to

each side of the capacitor as short as possible, and keep the trace

on a single layer with no vias. For maximum effectiveness, place

the capacitor either equidistant from the power and ground pins

or, when equidistant placement is not possible, slightly nearer to

the power pin (see Figure 83). Establish the thermal connections

to the planes on the far side of the capacitor.

Place all 100 nF bypass capacitors, which are recommended

for every analog, digital, and PLL power ground pair, as near as

possible to theADAU1463/ADAU1467. Bypass each of the AVDD,

DVDD, PVDD, and IOVDD supply signals on the PCB with an

additional single bulk capacitor (10 µF to 47 µF).

Keep all traces in the crystal resonator circuit (see Figure 14) as

short as possible to minimize stray capacitance. Do not connect

any long PCB traces to the crystal oscillator circuit components

because such traces may affect crystal startup and operation.

POWER GROUND

Grounding

Use a single ground plane in the application layout. Place all

components in an analog signal path away from digital signals.

CAPACITOR

TO POWER

Exposed Pad PCB Design

The device package includes an exposed pad for improved heat

dissipation. When designing a PCB for such a package, consider

the following:

•

Place a copper layer, equal in size to the exposed pad, on all

layers of the PCB, from top to bottom. Connect the copper

layers to a dedicated copper PCB layer (see Figure 86).

TO GROUND

Figure 83. Recommended Power Supply Bypass Capacitor Layout

Typically, a single 100 nF capacitor for each power ground pin

pair is sufficient. However, if there is excessive high frequency

noise in the system, use an additional 10 nF capacitor in parallel

(see Figure 84). Place the 10 nF capacitor between the devices

and the 100 nF capacitor, and establish the thermal connections

on the far side of the 100 nF capacitor.

TOP

GROUND

POWER

BOTTOM

VIAS

COPPER SQUARES

Figure 86. Exposed Pad Layout Example—Side View

VIA TO

GROUND PLANE

•

Place vias such that all layers of copper are connected,

allowing for efficient heat and energy conductivity. For an

example, see Figure 87, which shows 49 vias arranged in

a 7 × 7 grid in the pad area.

POWER PLANE

100nF

10nF

Figure 84. Layout for Multiple Power Supply Bypass Capacitors

To provide a current reservoir in case of sudden current spikes,

use a 10 µF capacitor for each named supply (DVDD, AVDD,

PVDD, and IOVDD) as shown in Figure 85.

Figure 87. Exposed Pad Layout Example—Top View

For detailed information, see the AN-772 Application Note,

A Design and Manufacturing Guide for the Lead Frame Chip

Scale Package (LFCSP).

Rev. A | Page 203 of 207

ADAU1463/ADAU1467

Data Sheet

PLL Filter

EOS/ESD Protection

To minimize jitter, connect the single resistor and two capacitors

in the PLL filter to the PLLFILT and PVDD pins with short

traces.

Although the ADAU1463/ADAU1467 have robust internal

protection circuitry against overvoltages and electrostatic

discharge, an external transient voltage suppressor (TVS) is

recommended for all systems to prevent damage to the IC. For

examples, see the AN-311 Application Note.

Power Supply Isolation with Ferrite Beads

Ferrite beads can be used for supply isolation. When using

ferrite beads, always place the beads outside the local high

frequency decoupling capacitors, as shown in Figure 88. If the

ferrite beads are placed between the supply pin and the decoupling

capacitor, high frequency noise is reflected back into the IC

because there is no suitable return path to ground. As a result,

EMI increases, creating noisy supplies.

DGND

1

IOVDD VDRIVE DVDD

DGND

2

3

71

72

10nF

(BYPASS)

100nF

(BYPASS)

1kΩ

100nF

(BYPASS)

FERRITE

BEAD

0.5Ω IF 10µF CERAMIC

MAIN

3.3V SUPPLY

10µF

OR 4.7µF

RESERVOIR

10µF

+

RESERVOIR

IOVDD

3.3V

DVDD

1.2V

Figure 88. Ferrite Bead Power Supply Isolation Circuit Example

TYPICAL APPLICATIONS BLOCK DIAGRAM

ANALOG

MICROPHONES

ADAU1977

MICROPHONE

ADC

HEAD

UNIT

CLASS AB/D

4-CHANNEL

AMPLIFIER

2

SPI

I C

SPEAKERS

SIGMA DSP

AD1938/

CAN

TRANSCEIVER

CLASS AB/D

4-CHANNEL

AMPLIFIER

AD1939

CODEC

8-CHANNEL

DAC

MICRO-

CONTROLLER

PDM

MICROPHONES

SPI

PDM

eFLASH

Figure 89. Automotive Infotainment Amplifier Block Diagram

Rev. A | Page 204 of 207

Data Sheet

ADAU1463/ADAU1467

The digital (DVDD) supply pins each have up to three local

bypass capacitors, as follows:

EXAMPLE PCB LAYOUT

Several external components, such as capacitors, resistors, and

a transistor, are required for proper operation of the device.

An example of the connection and layout of these components

is shown in Figure 90. Thick black lines represent traces, gray

rectangles represent components, and white circles with a thick

black ring represent thermal via connections to power or ground

planes. If a 1.2 V supply is available in the system, the transistor

circuit (including the associated 1 kΩ resistor) can be removed,

and 1.2 V can be connected directly to the DVDD power net,

with the VDRIVE pin left floating.

•

The 100 nF bypass capacitor acts as a return path for high

frequency currents from the DSP and other digital circuitry.

The 1 µF bypass capacitor is required to provide a local

current supply for sudden spikes in current that occur at

the beginning of each audio frame when the DSP core

switches from idle mode to operating mode.

•

Of these three bypass capacitors, the most important is the 100 nF

bypass capacitor, which is required for proper power supply

bypassing. The 10 nF and 1 µF capacitors can optionally be used

to improve the EMI/EMC performance of the system.

The analog (AVDD), PLL (PVDD), and interface (IOVDD)

supply pins each have local 100 nF bypass capacitors to provide

high frequency return currents with a short path to ground.

1μF

10μF DVDD 10μF IOVDD

CURRENT CURRENT

RESERVOIR RESERVOIR

1μF

BYPASS

100nF

BYPASS

100nF

BYPASS

10μF

100nF

BYPASS

DGND

IOVDD

DGND

DVDD

VDRIVE

DVDD REGULATOR

AGND

AVDD

ADAU1463/

ADAU1467

(TOP VIEW)

®

10μF PVDD

CURRENT

RESERVOIR

100nF

BYPASS

10μF

100nF

PGND

PVDD

150pF

4.3kΩ

100nF

BYPASS

PLLFILT

DGND

PLL LOOP FILTER

IOVDD

DGND

IOVDD

100nF

BYPASS

100nF

BYPASS

100nF

1μF

100nF

BYPASS

1μF

BYPASS

1μF

BYPASS

Figure 90. Supporting Component Placement and Layout

Rev. A | Page 205 of 207

ADAU1463/ADAU1467

Data Sheet

PCB MANUFACTURING GUIDELINES

The soldering profile in Figure 91 is recommended for the LFCSP package. See the AN-772 Application Note for more information about

PCB manufacturing guidelines.

60 SECONDS

RAMP UP

TO

3°C/SECOND MAX

150 SECONDS

260°C ± 5°C

217°C

150°C TO 200°C

RAMP DOWN

6°C/SECOND MAX

60 SECONDS

TO

180 SECONDS

TIME (Second)

20 SECONDS

TO

40 SECONDS

480 SECONDS MAX

Figure 91. Soldering Profile

12.0mm

ANALOG DEVICES

LFCSP (CP-88-10)

REV A

5.30mm × 5.30mm

0.25mm

0.55mm

0.40mm

0.90mm

0.70mm

10.50mm

Figure 92. PCB Decal Dimensions

Rev. A | Page 206 of 207

Data Sheet

ADAU1463/ADAU1467

OUTLINE DIMENSIONS

12.10

12.00 SQ

11.90

0.30

0.25

0.20

0.60 MAX

0.60

MAX

67

66

88

1

PIN 1

INDICATOR

PIN 1

INDICATOR

11.85

11.75 SQ

11.65

0.50

BSC

5.40

EXPOSED

PAD

5.30 SQ

5.20

0.65

1.00

0.90

0.80

0.55

0.45

22

44

45

23

0.50

0.40

0.30

0.80

0.70

0.60

TOP VIEW

BOTTOM VIEW

10.50

REF

0.70

0.65

0.60

12° MAX

0.90

0.85

0.80

0.045

0.025

0.005

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

COPLANARITY

SEATING

PLANE

0.08

0.190~0.245 REF

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220

Figure 93. 88-Lead Lead Frame Chip Scale Package [LFCSP]

12 mm × 12 mm Body and 0.85 mm Package Height

(CP-88-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model^{1, 2}

Temperature Range

−40°C to +105°C

Package Description

Package Option

CP-88-10

ADAU1463WBCPZ150

ADAU1463WBCPZ150RL

ADAU1463WBCPZ300

ADAU1463WBCPZ300RL

ADAU1467WBCPZ300

ADAU1467WBCPZ300RL

EVAL-ADAU1467Z

88-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

CP-88-10

¹Z = RoHS Compliant Part.

²The EVAL-ADAU1467Z can be used to evaluate both the ADAU1463 and the ADAU1467.

AUTOMOTIVE PRODUCTS

The ADAU1463W/ADAU1467W models are available with controlled manufacturing to support the quality and reliability requirements of

automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,

designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for

use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and

to obtain the specific Automotive Reliability reports for these models.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D14809-0-6/18(A)

Rev. A | Page 207 of 207


型号：	ADAU1463WBCPZ150
厂家：	ADI
描述：	SigmaDSP Digital Audio Processor 商用集成电路
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中文：	中文翻译
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ADAU1463WBCPZ150 [ADI]

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