ADAU1761BCPZ-RL [ADI]
SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL; 的SigmaDSP立体声，低功耗， 96 kHz的24位音频编解码器集成PLL
| 型号： | ADAU1761BCPZ-RL |
| 厂家： | 
ADI |
| 描述： | SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL |
| 文件： | 总92页 (文件大小：1103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SigmaDSP Stereo, Low Power, 96 kHz,
24-Bit Audio Codec with Integrated PLL
ADAU1761
FEATURES
GENERAL DESCRIPTION
SigmaDSP 28-/56-bit, 50 MIPS digital audio processor
Fully programmable with SigmaStudio graphical tool
24-bit stereo audio ADC and DAC: >98 dB SNR
Sampling rates from 8 kHz to 96 kHz
The ADAU1761 is a low power, stereo audio codec with
integrated digital audio processing that supports stereo 48 kHz
record and playback at 14 mW from a 1.8 V analog supply. The
stereo audio ADCs and DACs support sample rates from 8 kHz
Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V
6 analog input pins, configurable for single-ended or
differential inputs
Flexible analog input/output mixers
Stereo digital microphone input
Analog outputs: 2 differential stereo, 2 single-ended stereo,
1 mono headphone output driver
PLL supporting input clocks from 8 MHz to 27 MHz
Analog automatic level control (ALC)
Microphone bias reference voltage
to 96 kHz as well as a digital volume control.
The SigmaDSP® core features 28-bit processing (56-bit double
precision). The processor allows system designers to compensate
for the real-world limitations of microphones, speakers, amplifiers,
and listening environments, resulting in a dramatic improvement
in the perceived audio quality through equalization, multiband
compression, limiting, and third-party branded algorithms.
The SigmaStudio™ graphical development tool is used to program
the ADAU1761. This software includes audio processing blocks
such as filters, dynamics processors, mixers, and low level DSP
functions for fast development of custom signal flows.
Analog and digital I/O: 1.8 V to 3.65 V
I2C and SPI control interfaces
Digital audio serial data I/O: stereo and time-division
multiplexing (TDM) modes
Software-controllable clickless mute
Software power-down
GPIO pins for digital controls and outputs
32-lead, 5 mm × 5 mm LFCSP
−40°C to +85°C operating temperature range
The record path includes an integrated microphone bias circuit
and six inputs. The inputs can be mixed and muxed before the
ADC, or they can be configured to bypass the ADC. The
ADAU1761 includes a stereo digital microphone input.
The ADAU1761 includes five high power output drivers (two
differential and three single-ended), supporting stereo head-
phones, an earpiece, or other output transducer. AC-coupled
or capless configurations are supported. Individual fine level
controls are supported on all analog outputs. The output mixer
stage allows for flexible routing of audio.
APPLICATIONS
Smartphones/multimedia phones
Digital still cameras/digital video cameras
Portable media players/portable audio players
Phone accessories products
FUNCTIONAL BLOCK DIAGRAM
HP JACK
DETECTION
REGULATOR
ADAU1761
JACKDET/MICIN
LAUX
LINP
LINN
LOUTP
LOUTN
LHP
DAC
DAC
ADC
ADC
DAC
INPUT
DIGITAL DIGITAL
FILTERS FILTERS
MIXERS
OUTPUT
MIXERS
MONOOUT
RHP
RINP
RINN
ALC
ADC
ROUTP
ROUTN
RAUX
2
I C/SPI
CONTROL PORT
MICROPHONE
BIAS
SERIAL DATA
INPUT/OUTPUT PORTS
MICBIAS
PLL
MCLK
ADDR0/ ADDR1/ SCL/ SDA/
CDATA CCLK COUT
CLATCH
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.
ADAU1761
TABLE OF CONTENTS
Features .............................................................................................. 1
Playback Signal Path ...................................................................... 35
Output Signal Paths ................................................................... 35
Headphone Output .................................................................... 36
Pop-and-Click Suppression ...................................................... 37
Line Outputs ............................................................................... 37
Control Ports................................................................................... 38
Burst Mode Writing and Reading............................................ 38
I2C Port ........................................................................................ 38
SPI Port........................................................................................ 41
Serial Data Input/Output Ports .................................................... 42
Applications Information.............................................................. 44
Power Supply Bypass Capacitors.............................................. 44
GSM Noise Filter........................................................................ 44
Grounding................................................................................... 44
Exposed Pad PCB Design ......................................................... 44
DSP Core ......................................................................................... 45
Signal Processing........................................................................ 45
Architecture ................................................................................ 45
Program Counter ....................................................................... 45
Features........................................................................................ 45
Startup.......................................................................................... 45
Numeric Formats ....................................................................... 46
Programming.............................................................................. 46
Program RAM, Parameter RAM, and Data RAM..................... 47
Program RAM ............................................................................ 47
Parameter RAM.......................................................................... 47
Data RAM ................................................................................... 47
Read/Write Data Formats ......................................................... 47
Software Safeload ....................................................................... 48
Software Slew.............................................................................. 49
General-Purpose Input/Output.................................................... 50
GPIO Pins Set from the Control Port...................................... 50
Control Registers............................................................................ 51
Control Register Details ............................................................ 52
Outline Dimensions....................................................................... 92
Ordering Guide .......................................................................... 92
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Analog Performance Specifications........................................... 4
Power Supply Specifications........................................................ 7
Typical Current Consumption.................................................... 8
Typical Power Management Measurements ............................. 9
Digital Filters............................................................................... 10
Digital Input/Output Specifications......................................... 10
Digital Timing Specifications ................................................... 11
Digital Timing Diagrams........................................................... 12
Absolute Maximum Ratings.......................................................... 14
Thermal Resistance .................................................................... 14
ESD Caution................................................................................ 14
Pin Configuration and Function Descriptions........................... 15
Typical Performance Characteristics ........................................... 17
System Block Diagrams ................................................................. 20
Theory of Operation ...................................................................... 23
Startup, Initialization, and Power................................................. 24
Power-Up Sequence ................................................................... 24
Power Reduction Modes............................................................ 24
Digital Power Supply.................................................................. 24
Input/Output Power Supply...................................................... 24
Clock Generation and Management........................................ 24
Clocking and Sampling Rates ....................................................... 26
Core Clock................................................................................... 26
Sampling Rates............................................................................ 27
PLL ............................................................................................... 27
Record Signal Path.......................................................................... 29
Input Signal Paths....................................................................... 29
Analog-to-Digital Converters................................................... 31
Automatic Level Control (ALC)................................................... 32
ALC Parameters.......................................................................... 32
Noise Gate Function .................................................................. 33
Rev. C | Page 2 of 92
ADAU1761
REVISION HISTORY
9/10—Rev. B to Rev. C
Changes to Figure 1...........................................................................1
Changes to SPI Port Section ..........................................................41
Changes to Serial Data Input/Output Ports Section
and Table 25 .....................................................................................42
Added Figure 57..............................................................................42
Changes to Architecture Section and Figure 67..........................45
Added Startup Section....................................................................45
Changes to Parameter RAM Section and Data RAM Section ..47
Changes to Table 33 ........................................................................51
Changes to R2: Digital Microphone/Jack Detection Control,
16,392 (0x4008) Section and Table 36..........................................54
Changes to Table 42 ........................................................................58
Changes to Table 43 ........................................................................59
Changes to R15: Serial Port Control 0, 16,405 (0x4015)
5/10—Rev. A to Rev. B
Changes to Burst Mode Writing and Reading Section ..............38
Changes to Table 33 ........................................................................51
Added R67: Dejitter Control, 16,438 (0x4036) Section .............79
12/09—Rev. 0 to Rev. A
Changes to Features Section ............................................................1
Change to General Description Section.........................................1
Changes to Table 1 ............................................................................6
Change to Table 5............................................................................10
Changes to Figure 6.........................................................................13
Changes to Table 10 ........................................................................15
Changes to Captions of Figure 15, Figure 16, Figure 18, and
Figure 19...........................................................................................18
Changes to Captions of Figure 21 and Figure 24........................19
Added Figure 25; Renumbered Sequentially...............................19
Change to Figure 26........................................................................20
Change to Figure 27........................................................................21
Change to Figure 28........................................................................22
Change to Theory of Operation Section......................................23
Changes to Power Reduction Modes Section and
Case 1: PLL Is Bypassed Section ...................................................24
Changes to PLL Lock Acquisition Section...................................25
Changes to Core Clock Section and Figure 30............................26
Change to Sampling Rates Section................................................27
Changes to Input Signal Paths Section and Figure 32................29
Changes to Figure 33 and Figure 34 .............................................30
Changes to ADC Full-Scale Level Section...................................31
Change to Automatic Level Control (ALC) Section...................32
Changes to Output Signal Paths Section......................................35
Changes to Headphone Output Section.......................................36
Changes to Jack Detection Section, Pop-and-Click
Section and Table 49.......................................................................63
Change to Table 50..........................................................................64
Changes to Table 51, R18: Converter Control 1, 16,408
(0x4018) Section, and Table 52 .....................................................65
Changes to Table 60, R27: Playback L/R Mixer Right (Mixer 6)
Line Output Control, 16,417 (0x4021) Section, and Table 61...71
Changes to Table 62, R29: Playback Headphone Left Volume
Control, 16,419 (0x4023) Section, and Table 63 .........................72
Changes to Table 64 ........................................................................73
Changes to R42: Jack Detect Pin Control, 16,433 (0x4031)
Section and Table 76.......................................................................79
Changes to R57: DSP Sampling Rate Setting, 16,619 (0x40EB)
Section and Table 81.......................................................................81
Change to Table 85..........................................................................83
Change to Table 88..........................................................................84
Changes to R66: Clock Enable 1, 16,634 (0x40FA) Section
and Table 90 .....................................................................................85
1/09—Revision 0: Initial Version
Suppression Section, and Line Outputs Section .........................37
Changes to Control Ports Section and I2C Port Section............38
Added Burst Mode Writing and Reading Section ......................38
Rev. C | Page 3 of 92
ADAU1761
SPECIFICATIONS
Supply voltage (AVDD) = 3.3 V, TA = 25°C, master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement
bandwidth = 20 Hz to 20 kHz, word width = 24 bits, CLOAD (digital output) = 20 pF, ILOAD (digital output) = 2 mA, VIH = 2 V, VIL = 0.8 V,
unless otherwise noted. Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase
deviation specifications.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient).
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC performance excludes mixers
and PGA
ADC Resolution
All ADCs
24
0.375
95
Bits
dB
dB
Digital Attenuation Step
Digital Attenuation Range
INPUT RESISTANCE
Single-Ended Line Input
−12 dB gain
0 dB gain
6 dB gain
−12 dB gain
0 dB gain
35.25 dB gain
All gains
83
21
10.5
84.5
53
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
PGA Inverting Inputs
2
105
PGA Noninverting Inputs
SINGLE-ENDED LINE INPUT
Full-Scale Input Voltage (0 dB)
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
V rms
V rms (V p-p)
V rms (V p-p)
Dynamic Range
With A-Weighted Filter (RMS)
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
94
99
91
96
dB
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
No Filter (RMS)
Total Harmonic Distortion + Noise
−1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
−88
−90
dB
dB
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
94
99
91
96
3
dB
dB
dB
dB
dB
dB
dB
dB
mV
%
No Filter (RMS)
Gain per Step
Total Gain Range
Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Power Supply Rejection Ratio
−12
+6
−87
0.005
0
−12
68
dB
CM capacitor = 20 μF
100 mV p-p @ 217 Hz
100 mV p-p @ 1 kHz
65
67
dB
dB
Rev. C | Page 4 of 92
ADAU1761
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
PSEUDO-DIFFERENTIAL PGA INPUT
Full-Scale Input Voltage (0 dB)
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
V rms
V rms (V p-p)
V rms (V p-p)
Dynamic Range
With A-Weighted Filter (RMS)
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
92
98
90
95
dB
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
No Filter (RMS)
Total Harmonic Distortion + Noise
−1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
−88
−89
dB
dB
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
PGA gain
92
98
90
95
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV
%
No Filter (RMS)
Volume Control Step
Volume Control Range
PGA Boost
Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Common-Mode Rejection Ratio
0.75
PGA gain
−12
+35.25
20
−87
0.005
0
−14
83
dB
dB
dB
100 mV rms, 1 kHz
100 mV rms, 20 kHz
Differential PGA inputs
Scales linearly with AVDD
AVDD = 1.8 V
65
65
FULL DIFFERENTIAL PGA INPUT
Full-Scale Input Voltage (0 dB)
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
V rms
V rms (V p-p)
V rms (V p-p)
AVDD = 3.3 V
Dynamic Range
With A-Weighted Filter (RMS)
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
92
98
90
95
dB
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
No Filter (RMS)
Total Harmonic Distortion + Noise
−1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
−70
−78
dB
dB
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
PGA gain
92
98
90
95
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV
%
No Filter (RMS)
Volume Control Step
Volume Control Range
PGA Boost
Mute Attenuation
Interchannel Gain Mismatch
Offset Error
0.75
PGA gain
−12
+35.25
20
−87
0.005
0
Gain Error
−14
Rev. C | Page 5 of 92
ADAU1761
Parameter
Test Conditions/Comments
Min
Typ
83
65
Max
Unit
dB
dB
Interchannel Isolation
Common-Mode Rejection Ratio
100 mV rms, 1 kHz
100 mV rms, 20 kHz
MBIEN = 1
65
dB
MICROPHONE BIAS
Bias Voltage
0.65 × AVDD
AVDD = 1.8 V, MBI = 1
AVDD = 3.3 V, MBI = 1
AVDD = 1.8 V, MBI = 0
AVDD = 3.3 V, MBI = 0
AVDD = 3.3 V, MBI = 0, MPERF = 1
AVDD = 3.3 V, 1 kHz to 20 kHz
MBI = 0, MPERF = 0
MBI = 0, MPERF = 1
MBI = 1, MPERF = 0
MBI = 1, MPERF = 1
1.17
2.145
1.62
2.97
V
V
V
V
0.90 × AVDD
Bias Current Source
Noise in the Signal Bandwidth
3
mA
42
85
25
37
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
DIGITAL-TO-ANALOG CONVERTERS
DAC performance excludes mixers and
headphone amplifier
DAC Resolution
All DACs
24
0.375
95
Bits
dB
dB
Digital Attenuation Step
Digital Attenuation Range
DAC TO LINE OUTPUT
Full-Scale Output Voltage (0 dB)
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
Line output volume control
Line output volume control
AVDD/3.3
0.50 (1.41)
0.92 (2.60)
0.75
1
−87
V rms
V rms (V p-p)
V rms (V p-p)
dB
dB
dB
Analog Volume Control Step
Analog Volume Control Range
Mute Attenuation
−57
+6
Dynamic Range
20 Hz to 20 kHz, −60 dB input, line
output mode
With A-Weighted Filter (RMS)
No Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−1 dBFS, line output mode
AVDD = 1.8 V
AVDD = 3.3 V
96
dB
dB
dB
dB
dB
dB
dB
101
93.5
98
Total Harmonic Distortion + Noise
−90
−92
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
Line output mode
AVDD = 1.8 V
96
dB
dB
dB
dB
AVDD = 3.3 V
101
93.5
98
No Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
Power Supply Rejection Ratio
CM capacitor = 20 μF
100 mV p-p @ 217 Hz
100 mV p-p @ 1 kHz
56
70
3
dB
dB
%
Gain Error
Interchannel Gain Mismatch
Offset Error
Interchannel Isolation
0.005
0
100
dB
mV
dB
1 kHz, 0 dBFS input signal
Rev. C | Page 6 of 92
ADAU1761
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DAC TO HEADPHONE/EARPIECE
OUTPUT
PO = output power per channel
Full-Scale Output Voltage (0 dB)
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
AVDD/3.3
0.50 (1.41)
0.92 (2.60)
V rms
V rms (V p-p)
V rms (V p-p)
Total Harmonic Distortion + Noise
16 Ω load
−4 dBFS
AVDD = 1.8 V, PO = 6.4 mW
AVDD = 3.3 V, PO = 21.1 mW
AVDD = 1.8 V, PO = 3.8 mW
AVDD = 3.3 V, PO = 10.6 mW
CM capacitor = 20 μF
100 mV p-p @ 217 Hz
100 mV p-p @ 1 kHz
−76
−82
−82
−82
dB
dB
dB
dB
32 Ω load
Power Supply Rejection Ratio
56
67
dB
dB
Interchannel Isolation
1 kHz, 0 dBFS input signal, 32 Ω load,
AVDD = 3.3 V
Referred to GND
Referred to CM (capless headphone
mode)
73
50
dB
dB
REFERENCE
Common-Mode Reference Output
CM pin
AVDD/2
V
POWER SUPPLY SPECIFICATIONS
Table 2.
Parameter
SUPPLIES
Voltage
Test Conditions/Comments
Min
Typ
Max
Unit
DVDDOUT
AVDD
IOVDD
1.56
3.3
3.3
V
V
V
1.8
1.63
3.65
3.65
Digital I/O Current (IOVDD = 1.8 V)
Slave Mode
20 pF capacitive load on all digital pins
fS = 48 kHz
fS = 96 kHz
fS = 8 kHz
fS = 48 kHz
fS = 96 kHz
fS = 8 kHz
0.25
0.48
0.07
0.62
1.23
0.11
mA
mA
mA
mA
mA
mA
Master Mode
Digital I/O Current (IOVDD = 3.3 V)
Slave Mode
20 pF capacitive load on all digital pins
fS = 48 kHz
fS = 96 kHz
fS = 8 kHz
fS = 48 kHz
0.48
0.9
0.13
1.51
3
mA
mA
mA
mA
mA
mA
Master Mode
fS = 96 kHz
fS = 8 kHz
0.27
Analog Current (AVDD)
See Table 3
Rev. C | Page 7 of 92
ADAU1761
TYPICAL CURRENT CONSUMPTION
Master clock = 12.288 MHz, input sample rate = 48 kHz, input tone = 1 kHz, normal power management settings, ADC input @ −1 dBFS,
DAC input @ 0 dBFS. For total power consumption, add the IOVDD current listed in Table 2.
Table 3.
Typical AVDD Current
Consumption (mA)
Operating Voltage
Audio Path
Clock Generation
Direct MCLK
Integer PLL
Direct MCLK
Integer PLL
Direct MCLK
Integer PLL
Direct MCLK
Integer PLL
Direct MCLK
Integer PLL
Direct MCLK
Integer PLL
Direct MCLK
Integer PLL
Direct MCLK
Integer PLL
Direct MCLK
Integer PLL
Direct MCLK
Integer PLL
Direct MCLK
Integer PLL
Direct MCLK
Integer PLL
AVDD = IOVDD = 3.3 V
Record stereo differential to ADC
5.24
6.57
5.55
6.90
55.5
56.8
30.9
32.25
56.75
58
DAC stereo playback to line output (10 kΩ)
DAC stereo playback to headphone (16 Ω)
DAC stereo playback to headphone (32 Ω)
DAC stereo playback to capless headphone (32 Ω)
Record aux stereo bypass to line output (10 kΩ)
Record stereo differential to ADC
1.9
3.3
AVDD = IOVDD = 1.8 V
4.25
5.55
4.7
DAC stereo playback to line output (10 kΩ)
DAC stereo playback to headphone (16 Ω)
DAC stereo playback to headphone (32 Ω)
DAC stereo playback to capless headphone (32 Ω)
Record aux stereo bypass to line output (10 kΩ)
5.7
30.81
32
18.3
19.5
32.6
33.7
1.9
3.07
Rev. C | Page 8 of 92
ADAU1761
TYPICAL POWER MANAGEMENT MEASUREMENTS
Master clock = 12.288 MHz, integer PLL, input sample rate = 48 kHz, input tone = 1 kHz. Pseudo-differential input to ADCs, DACs to
line output with 10 kΩ load. ADC input @ −1 dBFS, DAC input @ 0 dBFS. In Table 4, the mixer boost and power management conditions
are set for MXBIAS[1:0], ADCBIAS[1:0], HPBIAS[1:0], and DACBIAS[1:0]. RBIAS[1:0] and PBIAS[1:0] do not have an extreme power
saving mode and are therefore set for power saving mode in the extreme power saving rows in Table 4.
Table 4.
Typical
Power Management
Setting
Mixer Boost
Setting
AVDD Current
Consumption (mA) THD + N (dB)
Typical ADC
Typical Line Output
THD + N (dB)
Operating Voltage
AVDD = IOVDD = 3.3 V Normal (default)
Normal operation 9.6
−91
−92.5
−92.5
−92.5
−92.5
−87
Boost Level 1
Boost Level 2
Boost Level 3
9.75
9.92
−91.5
−91.5
−91.5
−84.5
−84.8
−84.8
−85
10.25
Extreme power saving
Normal operation 7.09
Boost Level 1
Boost Level 2
Boost Level 3
7.19
7.29
7.49
−87.1
−87.1
−87.1
−90
Power saving
Normal operation 7.67
−89.5
−89.5
−89.8
−89.8
−91
Boost Level 1
Boost Level 2
Boost Level 3
7.77
7.86
8.07
−90
−90
−90
Enhanced performance Normal operation 10.55
−93.5
−93.5
−93.5
−93.5
−91.2
−91.2
−91.2
−91.2
−86
Boost Level 1
Boost Level 2
Boost Level 3
10.74
10.93
11.33
−91
−91
−91
AVDD = IOVDD = 1.8 V Normal (default)
Normal operation 8.1
−88
Boost Level 1
Boost Level 2
Boost Level 3
8.26
8.41
8.73
−88
−88
−88
Extreme power saving
Normal operation 5.73
−85
Boost Level 1
Boost Level 2
Boost Level 3
5.82
5.91
6.1
−85.4
−85.5
−85.5
−86
−86
−86
−86
Power saving
Normal operation 6.27
−89.4
−89.5
−89.5
−89.5
−91.5
−91.5
−91.5
−91.5
Boost Level 1
Boost Level 2
Boost Level 3
6.36
6.46
6.65
−86.1
−86.3
−86.3
−88
Enhanced performance Normal operation 9.01
Boost Level 1
Boost Level 2
Boost Level 3
9.2
9.38
9.76
−88
−88
−88
Rev. C | Page 9 of 92
ADAU1761
DIGITAL FILTERS
Table 5.
Parameter
Mode
Factor
Min
Typ
Max
Unit
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
All modes, typ @ 48 kHz
0.4375 fS
21
0.015
24
27
67
479
kHz
dB
kHz
kHz
dB
0.5 fS
0.5625 fS
Stop-Band Attenuation
Group Delay
22.9844/fS
ꢀs
DAC INTERPOLATION FILTER
Pass Band
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
0.4535 fS
0.3646 fS
22
35
kHz
kHz
dB
Pass-Band Ripple
Transition Band
Stop Band
0.01
0.05
dB
0.5 fS
0.5 fS
0.5465 fS
0.6354 fS
24
48
26
61
69
68
521
115
kHz
kHz
kHz
kHz
dB
dB
ꢀs
ꢀs
Stop-Band Attenuation
Group Delay
25/fS
11/fS
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 3.3 V 10ꢀ.
Table 6.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT SPECIFICATIONS
Input Voltage High (VIH)
Input Voltage Low (VIL)
Input Leakage
0.7 × IOVDD
V
V
0.3 × IOVDD
Pull-Ups/Pull-Downs Disabled
IIH @ VIH = 3.3 V
IIL @ VIL = 0 V
IIL @ VIL = 0 V (MCLK pin)
IIH @ VIH = 3.3 V
IIL @ VIL = 0 V
−0.17
−0.17
−13.5
−0.7
−13.5
2.7
+0.17
+0.17
−0.5
+0.7
−0.5
8.3
ꢀA
ꢀA
ꢀA
ꢀA
ꢀA
ꢀA
ꢀA
pF
Pull-Ups Enabled
Pull-Downs Enabled
IIH @ VIH = 3.3 V
IIL @ VIL = 0 V
−0.18
+0.18
5
Input Capacitance
OUTPUT SPECIFICATIONS
Output Voltage High (VOH)
Output Voltage Low (VOL)
IOH = 2 mA @ 3.3 V, 0.85 mA @ 1.8 V
IOL = 2 mA @ 3.3 V, 0.85 mA @ 1.8 V
0.8 × IOVDD
V
V
0.1 × IOVDD
Rev. C | Page 10 of 92
ADAU1761
DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 3.3 V 10ꢀ.
Table 7. Digital Timing
Limit
Parameter
Unit
Description
tMIN
tMAX
MASTER CLOCK
tMP
tMP
tMP
74
37
24.7
18.5
488
244
162.7
122
ns
ns
ns
ns
MCLK period, 256 × fS mode.
MCLK period, 512 × fS mode.
MCLK period, 768 × fS mode.
MCLK period, 1024 × fS mode.
tMP
SERIAL PORT
tBIL
tBIH
tLIS
tLIH
5
5
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
BCLK pulse width low.
BCLK pulse width high.
LRCLK setup. Time to BCLK rising.
LRCLK hold. Time from BCLK rising.
DAC_SDATA setup. Time to BCLK rising.
DAC_SDATA hold. Time from BCLK rising.
tSIS
tSIH
tSODM
SPI PORT
fCCLK
tCCPL
tCCPH
tCLS
50
10
ADC_SDATA delay. Time from BCLK falling in master mode.
MHz
ns
ns
CCLK frequency.
CCLK pulse width low.
CCLK pulse width high.
CLATCH setup. Time to CCLK rising.
CLATCH hold. Time from CCLK rising.
CLATCH pulse width high.
10
10
5
ns
tCLH
10
10
5
ns
tCLPH
tCDS
tCDH
ns
ns
ns
ns
CDATA setup. Time to CCLK rising.
CDATA hold. Time from CCLK rising.
COUT three-stated. Time from CLATCH rising.
5
tCOD
50
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
400
kHz
ꢀs
ꢀs
ꢀs
ꢀs
ns
ns
ns
ns
ns
ꢀs
SCL frequency.
SCL high.
SCL low.
Setup time; relevant for repeated start condition.
Hold time. After this period, the first clock is generated.
Data setup time.
SCL rise time.
SCL fall time.
0.6
1.3
0.6
0.6
100
300
300
300
300
tSDR
tSDF
tBFT
SDA rise time.
SDA fall time.
0.6
Bus-free time. Time between stop and start.
RLOAD = 1 MΩ, CLOAD = 14 pF.
Digital microphone clock fall time.
Digital microphone clock rise time.
Digital microphone delay time for valid data.
Digital microphone delay time for data three-stated.
DIGITAL MICROPHONE
tDCF
tDCR
tDDV
tDDH
10
10
30
12
ns
ns
ns
ns
22
0
Rev. C | Page 11 of 92
ADAU1761
DIGITAL TIMING DIAGRAMS
tLIH
tBIH
BCLK
tBIL
tLIS
LRCLK
tSIS
DAC_SDATA
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
tSIH
tSIS
DAC_SDATA
I S MODE
2
MSB
tSIH
tSIS
tSIS
DAC_SDATA
RIGHT-JUSTIFIED
MODE
LSB
MSB
tSIH
tSIH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Input Port Timing
tBIH
BCLK
tBIL
LRCLK
tSODM
MSB
ADC_SDATA
LEFT-JUSTIFIED
MODE
MSB – 1
tSODM
MSB
ADC_SDATA
I S MODE
2
tSODM
ADC_SDATA
RIGHT-JUSTIFIED
MODE
LSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 3. Serial Output Port Timing
Rev. C | Page 12 of 92
ADAU1761
tCLS
tCLH
tCLPH
tCCPL
tCCPH
CLATCH
CCLK
CDATA
tCDH
tCDS
COUT
tCOD
Figure 4. SPI Port Timing
tDS
tSCH
tSCH
SDA
SCL
tSCR
tSCLH
tSCS
tBFT
tSCLL tSCF
Figure 5. I2C Port Timing
tDCF
tDCR
CLK
tDDH
tDDH
tDDV
tDDV
DATA1/
DATA2
DATA1
DATA2
DATA1
DATA2
Figure 6. Digital Microphone Timing
Rev. C | Page 13 of 92
ADAU1761
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
θJA represents thermal resistance, junction-to-ambient; θJC repre-
sents thermal resistance, junction-to-case. All characteristics are
for a 4-layer board.
Parameter
Rating
Power Supply (AVDD)
−0.3 V to +3.65 V
20 mA
−0.3 V to AVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−40°C to +85°C
−65°C to +150°C
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range
Storage Temperature Range
Table 9. Thermal Resistance
Package Type
θJA
θJC
Unit
32-Lead LFCSP
50.1
17
°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. C | Page 14 of 92
ADAU1761
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IOVDD
MCLK
ADDR0/CLATCH
JACKDET/MICIN
MICBIAS
1
2
3
4
5
6
7
8
24 DVDDOUT
23 AVDD
22 AGND
21 MONOOUT
20 LHP
19 RHP
18 LOUTP
17 LOUTN
PIN 1
INDICATOR
ADAU1761
TOP VIEW
(Not to Scale)
LAUX
CM
AVDD
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE
ADAU1761 GROUNDS. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED TO THE
GROUND PLANE.
Figure 7. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
IOVDD
PWR
Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,
which also sets the highest input voltage that should be seen on the digital input pins.
IOVDD should be set between 1.8 V and 3.3 V. The current draw of this pin is variable because
it is dependent on the loads of the digital outputs. IOVDD should be decoupled to DGND
with a 100 nF capacitor and a 10 μF capacitor.
2
3
MCLK
ADDR0/CLATCH
D_IN
D_IN
External Master Clock Input.
I2C Address Bit 0 (ADDR0).
SPI Latch Signal (CLATCH). Must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction can take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the beginning of the SPI
transaction.
4
JACKDET/MICIN
D_IN
Detect Insertion/Removal of Headphone Plug (JACKDET).
Digital Microphone Stereo Input (MICIN).
5
6
7
MICBIAS
LAUX
CM
A_OUT
A_IN
A_OUT
Bias Voltage for Electret Microphone.
Left Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
AVDD/2 V Common-Mode Reference. A 10 μF to 47 μF standard decoupling capacitor should
be connected between this pin and AGND to reduce crosstalk between the ADCs and DACs.
This pin can be used to bias external analog circuits, as long as they are not drawing current
from CM (for example, the noninverting input of an op amp).
8
9
AVDD
AGND
PWR
PWR
1.8 V to 3.65 V Analog Supply for DAC and Microphone Bias. This pin should be decoupled
locally to AGND with a 100 nF capacitor.
Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.
AGND should be decoupled locally to AVDD with a 100 nF capacitor.
10
11
12
13
14
15
16
17
18
LINP
LINN
RINP
RINN
RAUX
ROUTP
ROUTN
LOUTN
LOUTP
A_IN
A_IN
A_IN
A_IN
Left Channel Noninverting Input or Single-Ended Input 0. Biased at AVDD/2.
Left Channel Inverting Input or Single-Ended Input 1. Biased at AVDD/2.
Right Channel Noninverting Input or Single-Ended Input 2. Biased at AVDD/2.
Right Channel Inverting Input or Single-Ended Input 3. Biased at AVDD/2.
Right Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
Right Line Output, Positive. Biased at AVDD/2.
Right Line Output, Negative. Biased at AVDD/2.
Left Line Output, Negative. Biased at AVDD/2.
Left Line Output, Positive. Biased at AVDD/2.
A_IN
A_OUT
A_OUT
A_OUT
A_OUT
Rev. C | Page 15 of 92
ADAU1761
Pin No.
19
20
Mnemonic
Type1
Description
RHP
LHP
MONOOUT
A_OUT
A_OUT
A_OUT
Right Headphone Output. Biased at AVDD/2.
Left Headphone Output. Biased at AVDD/2.
Mono Output or Virtual Ground for Capless Headphone. Biased at AVDD/2 when set as mono
output.
21
22
23
24
AGND
PWR
PWR
PWR
Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.
AGND should be decoupled locally to AVDD with a 100 nF capacitor.
1.8 V to 3.3 V Analog Supply for ADC, Output Driver, and Input to Digital Supply Regulator.
This pin should be decoupled locally to AGND with a 100 nF capacitor.
Digital Core Supply Decoupling Point. The digital supply is generated from an on-board
regulator and does not require an external supply. DVDDOUT should be decoupled to DGND
with a 100 nF capacitor and a 10 μF capacitor.
AVDD
DVDDOUT
25
DGND
PWR
Digital Ground. The AGND and DGND pins can be tied together on a common ground plane.
DGND should be decoupled to DVDDOUT and to IOVDD with 100 nF capacitors and 10 μF
capacitors.
26
27
28
29
30
31
ADC_SDATA/GPIO1 D_IO
DAC_SDATA/GPIO0 D_IO
ADC Serial Output Data (ADC_SDATA).
General-Purpose Input/Output 1 (GPIO1).
DAC Serial Input Data (DAC_SDATA).
General-Purpose Input/Output 0 (GPIO0).
Serial Data Port Bit Clock (BCLK).
General-Purpose Input/Output 2 (GPIO2).
Serial Data Port Frame Clock (LRCLK).
General-Purpose Input/Output 3 (GPIO3).
I2C Address Bit 1 (ADDR1).
BCLK/GPIO2
LRCLK/GPIO3
ADDR1/CDATA
SDA/COUT
D_IO
D_IO
D_IN
D_IO
SPI Data Input (CDATA).
I2C Data (SDA). This pin is a bidirectional open-collector input/output. The line connected to
this pin should have a 2 kΩ pull-up resistor.
SPI Data Output (COUT). This pin is used for reading back registers and memory locations. It is
three-state when an SPI read is not active.
32
EP
SCL/CCLK
D_IN
I2C Clock (SCL). This pin is always an open-collector input when in I2C control mode. The line
connected to this pin should have a 2 kΩ pull-up resistor.
SPI Clock (CCLK). This pin can run continuously or be gated off between SPI transactions.
Exposed Pad. The exposed pad is connected internally to the ADAU1761 grounds. For
increased reliability of the solder joints and maximum thermal capability, it is recommended
that the pad be soldered to the ground plane. See the Exposed Pad PCB Design section for
more information.
Exposed Pad
1 A_IN = analog input, A_OUT = analog output, D_IN = digital input, D_IO = digital input/output, PWR = power.
Rev. C | Page 16 of 92
ADAU1761
TYPICAL PERFORMANCE CHARACTERISTICS
28
26
24
22
20
18
16
14
12
10
8
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
6
4
2
0
–60
–50
–40
–30
–20
–10
0
–60
–50
–40
–30
–20
–10
0
DIGITAL 1kHz INPUT SIGNAL (dBFS)
DIGITAL 1kHz INPUT SIGNAL (dBFS)
Figure 8. Headphone Amplifier Power vs. Input Level, 16 Ω Load
Figure 11. Headphone Amplifier THD + N vs. Input Level, 16 Ω Load
18
16
14
12
10
8
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
6
4
2
0
–60
–50
–40
–30
–20
–10
0
–60
–50
–40
–30
–20
–10
0
DIGITAL 1kHz INPUT SIGNAL (dBFS)
DIGITAL 1kHz INPUT SIGNAL (dBFS)
Figure 9. Headphone Amplifier Power vs. Input Level, 32 Ω Load
Figure 12. Headphone Amplifier THD + N vs. Input Level, 32 Ω Load
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.04
0.02
0
–0.02
–0.04
–0.06
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
FREQUENCY (NORMALIZED TO fS
FREQUENCY (NORMALIZED TO fS
)
)
Figure 10. ADC Decimation Filter, 64× Oversampling, Normalized to fS
Figure 13. ADC Decimation Filter Pass-Band Ripple, 64× Oversampling,
Normalized to fS
Rev. C | Page 17 of 92
ADAU1761
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (NORMALIZED TO fS
FREQUENCY (NORMALIZED TO fS
)
)
Figure 14. ADC Decimation Filter, 128× Oversampling, Normalized to fS
Figure 17. ADC Decimation Filter Pass-Band Ripple, 128× Oversampling,
Normalized to fS
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.04
0.02
0
−0.02
−0.04
−0.06
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
FREQUENCY (NORMALIZED TO fS
FREQUENCY (NORMALIZED TO fS
)
)
Figure 15. ADC Decimation Filter, 128× Oversampling, Double-Rate Mode,
Normalized to fS
Figure 18. ADC Decimation Filter Pass-Band Ripple, 128× Oversampling,
Double-Rate Mode, Normalized to fS
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
FREQUENCY (NORMALIZED TO fS
)
FREQUENCY (NORMALIZED TO fS
)
Figure 16. DAC Interpolation Filter, 64× Oversampling, Double-Rate Mode,
Normalized to fS
Figure 19. DAC Interpolation Filter Pass-Band Ripple, 64× Oversampling,
Double-Rate Mode, Normalized to fS
Rev. C | Page 18 of 92
ADAU1761
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.05
0.04
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (NORMALIZED TO fS
FREQUENCY (NORMALIZED TO fS
)
)
Figure 20. DAC Interpolation Filter, 128× Oversampling, Normalized to fS
Figure 23. DAC Interpolation Filter Pass-Band Ripple, 128× Oversampling,
Normalized to fS
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
FREQUENCY (NORMALIZED TO fS
)
FREQUENCY (NORMALIZED TO fS
)
Figure 21. DAC Interpolation Filter, 128× Oversampling, Double-Rate Mode,
Normalized to fS
Figure 24. DAC Interpolation Filter Pass-Band Ripple, 128× Oversampling,
Double-Rate Mode, Normalized to fS
12
11
10
9
90
80
70
60
50
40
30
20
10
0
8
7
6
5
4
3
2
1
0
0
100 200 300 400 500 600 700 800 900 1000 1100
INSTRUCTIONS
GAIN (dB)
Figure 22. Typical DSP Current Draw
Figure 25. Input Impedance vs. Gain for Analog Inputs
Rev. C | Page 19 of 92
ADAU1761
SYSTEM BLOCK DIAGRAMS
FROM VOLTAGE
REGULATOR
(1.8V TO 3.3V)
10µF
+
0.1µF
10µF
+
10µF
+
0.1µF
0.1µF
0.1µF
1.2nH
9.1pF
THE INPUT CAPACITOR VALUE DEPENDS ON THE
INPUT IMPEDANCE, WHICH VARIES WITH THE
VOLUME SETTING.
DVDDOUT
IOVDD
AVDD
AVDD
10µF
LOUTP
LOUTN
RHP
EARPIECE
SPEAKER
LINP
LINN
LEFT
MICROPHONE
10µF
CAPLESS
HEADPHONE
OUTPUT
MONOOUT
LHP
2kΩ
ROUTP
ROUTN
ADAU1761
MICBIAS
EARPIECE
SPEAKER
2kΩ
10µF
RINN
RINP
RIGHT
MICROPHONE
10µF
ADC_SDATA/GPIO1
JACK
DETECTION
SIGNAL
JACKDET/MICIN
DAC_SDATA/GPIO0
LRCLK/GPIO3
SERIAL DATA
BCLK/GPIO2
AUX LEFT
10µF
10µF
1kΩ
LAUX
RAUX
ADDR1/CDATA
SDA/COUT
SYSTEM
CONTROLLER
SCL/CCLK
AUX RIGHT
1kΩ
ADDR0/CLATCH
49.9Ω
MCLK
CM
+
CLOCK
SOURCE
0.1µF
10µF
Figure 26. System Block Diagram
Rev. C | Page 20 of 92
ADAU1761
FROM VOLTAGE
REGULATOR
(1.8V TO 3.3V)
10µF
+
0.1µF
10µF
+
10µF
+
0.1µF
0.1µF
0.1µF
1.2nH
9.1pF
THE INPUT CAPACITOR VALUE DEPENDS ON THE
INPUT IMPEDANCE, WHICH VARIES WITH THE
VOLUME SETTING.
DVDDOUT
MICBIAS
IOVDD
AVDD
AVDD
LOUTP
LOUTN
RHP
V
DD
EARPIECE
SPEAKER
SINGLE-ENDED
ANALOG
MICROPHONE
10µF
LINN
LINP
OUTPUT
CAPLESS
HEADPHONE
OUTPUT
CM
MONOOUT
LHP
GND
ADAU1761
ROUTP
ROUTN
EARPIECE
SPEAKER
V
DD
10µF
SINGLE-ENDED
ANALOG
MICROPHONE
RINN
RINP
OUTPUT
CM
GND
ADC_SDATA/GPIO1
JACK
DETECTION
SIGNAL
JACKDET/MICIN
DAC_SDATA/GPIO0
LRCLK/GPIO3
SERIAL DATA
BCLK/GPIO2
10µF
AUX LEFT
1kΩ
LAUX
RAUX
ADDR1/CDATA
SDA/COUT
10µF
SYSTEM
CONTROLLER
SCL/CCLK
AUX RIGHT
1kΩ
ADDR0/CLATCH
49.9Ω
MCLK
CM
+
CLOCK
SOURCE
0.1µF
10µF
Figure 27. System Block Diagram with Analog Microphones
Rev. C | Page 21 of 92
ADAU1761
FROM VOLTAGE
REGULATOR
(1.8V TO 3.3V)
10µF
+
0.1µF
10µF
+
10µF
+
0.1µF
0.1µF
0.1µF
1.2nH
9.1pF
CAPLESS
DVDDOUT
IOVDD
AVDD
AVDD
HEADPHONE
OUTPUT
MICBIAS
RHP
MONOOUT
LHP
BCLK
CM
2.5V TO 5.0V
CLK
LINP
LINN
RINN
0.1µF
10µF
V
DATA
DIGITAL
DD
MICROPHONE
0.1µF
VDD
VDD
22nF
22nF
R
R
EXT
L/R SELECT
GND
RINP
LOUTP
LOUTN
INL+
INL–
ADAU1761
OUTL+
OUTL–
LEFT
SPEAKER
EXT
SSM2306
CLASS-D 2W
BCLK
STEREO SPEAKER
DRIVER
CLK
22nF
22nF
R
R
EXT
ROUTP
ROUTN
INR+
RIGHT
SPEAKER
OUTR+
EXT
OUTR–
INR–
V
DATA
DIGITAL
DD
MICROPHONE
SD GND
GND
0.1µF
L/R SELECT
GND
JACKDET/MICIN
LAUX
ADC_SDATA/GPIO1
DAC_SDATA/GPIO0
LRCLK/GPIO3
10µF
10µF
AUX LEFT
1kΩ
SERIAL DATA
BCLK/GPIO2
RAUX
MCLK
ADDR1/CDATA
SDA/COUT
SYSTEM
CONTROLLER
AUX RIGHT
1kΩ
SCL/CCLK
49.9Ω
ADDR0/CLATCH
CLOCK
SOURCE
CM
+
0.1µF
10µF
Figure 28. System Block Diagram with Digital Microphones and SSM2306 Class-D Speaker Driver
Rev. C | Page 22 of 92
ADAU1761
THEORY OF OPERATION
The ADAU1761 is a low power audio codec with an integrated
stream-oriented DSP core, making it an all-in-one package that
offers high quality audio, low power, small size, and many
advanced features. The stereo ADC and stereo DAC each have
an SNR of at least +98 dB and a THD + N of at least −90 dB.
The serial data port is compatible with I2S, left-justified, right-
justified, and TDM modes for interfacing to digital audio data.
The operating voltage range is 1.8 V to 3.65 V, with an on-board
regulator generating the internal digital supply voltage.
The SigmaStudio software is used to program and control the
SigmaDSP through the control port. Along with designing and
tuning a signal flow, the tools can be used to configure all of the
DSP registers. The SigmaStudio graphical interface allows any-
one with digital or analog audio processing knowledge to easily
design DSP signal flow and port it to a target application. At the
same time, it provides enough flexibility and programmability
for an experienced DSP programmer to have in-depth control
of the design. In SigmaStudio, the user can connect graphical
blocks (such as biquad filters, dynamics processors, mixers, and
delays), compile the design, and load the program and parameter
files into the ADAU1761 memory through the control port.
Signal processing blocks available in the provided libraries
include the following:
The record signal path includes very flexible input configurations
that can accept differential and single-ended analog microphone
inputs as well as a digital microphone input. A microphone bias
pin provides seamless interfacing to electret microphones. Input
configurations can accept up to six single-ended analog signals
or variations of stereo differential or stereo single-ended signals
with two additional auxiliary single-ended inputs. Each input
signal has its own programmable gain amplifier (PGA) for volume
adjustment and can be routed directly to the playback path output
mixers, bypassing the ADCs. An automatic level control (ALC)
can also be implemented to keep the recording volume constant.
•
•
•
•
Enhanced stereo capture
Single- and double-precision biquad filters
FIR filters
Dynamics processors with peak or rms detection for mono
and multichannel dynamics
Mixers and splitters
Tone and noise generators
Fixed and variable gain
Loudness
Delay
Stereo enhancement
Dynamic bass boost
Noise and tone sources
Level detectors
•
•
•
•
•
•
•
•
•
The ADCs and DACs are high quality, 24-bit Σ-Δ converters
that operate at selectable 64× or 128× oversampling ratios. The
base sampling rate of the converters is set by the input clock rate
and can be further scaled with the converter control register
settings. The converters can operate at sampling frequencies
from 8 kHz to 96 kHz. The ADCs and DACs also include very
fine-step digital volume controls.
The playback path allows input signals and DAC outputs to be
mixed into various output configurations. Headphone drivers
are available for a stereo headphone output, and the other output
pins are capable of differentially driving an earpiece speaker.
Capless headphone outputs are possible with the use of the
mono output as a virtual ground connection. The stereo line
outputs can be used as either single-ended or differential
outputs and as an optional mix-down mono output.
Additional processing blocks are always being developed.
Analog Devices also provides proprietary and third-party
algorithms for applications such as matrix decoding, bass
enhancement, and surround virtualizers. Contact Analog
Devices (www.analog.com) for information about licensing
these algorithms.
The ADAU1761 can generate its internal clocks from a wide
range of input clocks by using the on-board fractional PLL.
The PLL accepts inputs from 8 MHz to 27 MHz.
The DSP core introduces many features that make this codec
unique and optimized for audio processing. The program and
parameter RAMs can be loaded with custom audio processing
signal flow built using the SigmaStudio graphical programming
software from Analog Devices, Inc. The values stored in the
parameter RAM control individual signal processing blocks,
such as equalization filters, dynamics processors, audio delays,
and mixer levels.
The ADAU1761 is provided in a small, 32-lead, 5 mm × 5 mm
LFCSP with an exposed bottom pad.
Rev. C | Page 23 of 92
ADAU1761
STARTUP, INITIALIZATION, AND POWER
This section describes the procedure for properly starting up
the ADAU1761. The following sequence provides a high level
approach to the proper initiation of the system.
POWER REDUCTION MODES
Sections of the ADAU1761 chip can be turned on and off as
needed to reduce power consumption. These include the ADCs,
the DACs, the PLL, and the DSP core.
1. Apply power to the ADAU1761.
2. Lock the PLL to the input clock (if using the PLL).
3. Enable the core clock.
In addition, the control registers can be used to configure some
functions for power saving, normal, or enhanced performance
operation. See the Control Registers section for more
information.
4. Load the register settings.
See the Startup section for more information about the proper
start-up sequence.
The digital filters of the ADCs and DACs can each be set to over-
sampling ratios of 64× or 128× (default). Setting the oversampling
ratios to 64× for these filters lowers power consumption with a
minimal impact on performance. See the Digital Filters section
for specifications; see the Typical Performance Characteristics
section for graphs of these filters.
POWER-UP SEQUENCE
The ADAU1761 uses a power-on reset (POR) circuit to
reset the registers upon power-up. The POR monitors the
DVDDOUT pin and generates a reset signal whenever power
is applied to the chip. During the reset, the ADAU1761 is set
to the default values documented in the register map (see the
Control Registers section). Typically, with a 10 μF capacitor on
AVDD, the POR takes approximately 14 ms.
DIGITAL POWER SUPPLY
The digital power supply for the ADAU1761 is generated from
an internal regulator. This regulator generates a 1.5 V supply
internally. The only external connection to this regulator is the
DVDDOUT bypassing point. A 100 nF capacitor and a 10 μF
capacitor should be connected between this pin and DGND.
1.5V
1.35V
DVDDOUT
0.95V
INPUT/OUTPUT POWER SUPPLY
AVDD
The power for the digital output pins is supplied from IOVDD,
and this pin also sets the highest input voltage that should be
seen on the digital input pins. IOVDD should be set between
1.8 V and 3.3 V; no digital input signal should be at a voltage
level higher than the one on IOVDD. The current draw of this
pin is variable because it depends on the loads of the digital
outputs. IOVDD should be decoupled to DGND with a 100 nF
capacitor and a 10 μF capacitor.
PART READY
POR
POR
ACTIVE
POR
FINISHED
POR ACTIVE
Figure 29. Power-On Reset Sequence
CLOCK GENERATION AND MANAGEMENT
The PLL lock time is dependent on the MCLK rate. Typical
lock times are provided in Table 11. The DSP can be enabled
immediately after the PLL is locked.
The ADAU1761 uses a flexible clocking scheme that enables the
use of many different input clock rates. The PLL can be bypassed
or used, resulting in two different approaches to clock manage-
ment. For more information about clocking schemes, PLL
configuration, and sampling rates, see the Clocking and
Sampling Rates section.
Table 11. PLL Lock Times
PLL Mode
Fractional
Fractional
Integer
Fractional
Fractional
Fractional
Fractional
Fractional
Fractional
Integer
MCLK Frequency
Lock Time (Typical)
3.5 ms
3.0 ms
2.96 ms
2.4 ms
2.4 ms
2.98 ms
2.98 ms
2.98 ms
2.95 ms
2.96 ms
2.4 ms
8 MHz
12 MHz
12.288 MHz
13 MHz
14.4 MHz
19.2 MHz
19.68 MHz
19.8 MHz
24 MHz
24.576 MHz
26 MHz
27 MHz
Case 1: PLL Is Bypassed
If the PLL is bypassed, the core clock is derived directly from
the MCLK input. The rate of this clock must be set properly in
Register R0 (clock control register, Address 0x4000) using the
INFREQ[1:0] bits. When the PLL is bypassed, supported external
clock rates are 256 × fS, 512 × fS, 768 × fS, and 1024 × fS, where fS
is the base sampling rate. The core clock of the chip is off until
the core clock enable bit (COREN) is asserted. If a clock slower
than 1024 × fS is directly input to the ADAU1761 (bypassing the
PLL), the number of available SigmaDSP processing cycles is
reduced and the DSPSR bits in Register R57 (Address 0x40EB)
should be adjusted accordingly.
Fractional
Fractional
2.4 ms
Rev. C | Page 24 of 92
ADAU1761
Case 2: PLL Is Used
To program the PLL during initialization or reconfiguration of
the clock setting, the following procedure must be followed:
The core clock to the entire chip is off during the PLL lock
acquisition period. The user can poll the lock bit to determine
when the PLL has locked. After lock is acquired, the ADAU1761
can be started by asserting the core clock enable bit (COREN)
in Register R0 (clock control register, Address 0x4000). This bit
enables the core clock to all the internal blocks of the ADAU1761.
1. Power down the PLL.
2. Reset the PLL control register.
3. Start the PLL.
4. Poll the lock bit.
5. Assert the core clock enable bit after the PLL lock
is acquired.
PLL Lock Acquisition
The PLL control register (Register R1, Address 0x4002) is a
48-bit register where all bits must be written with a single
continuous write to the control port.
During the lock acquisition period, only Register R0 (Address
0x4000) and Register R1 (Address 0x4002) are accessible through
the control port. Because all other registers require a valid master
clock for reading and writing, do not attempt to access any other
register. Any read or write is prohibited until the core clock
enable bit (COREN) and the lock bit are both asserted.
Rev. C | Page 25 of 92
ADAU1761
CLOCKING AND SAMPLING RATES
R57: DSP SAMPLING
RATE SETTING
DSPSR[3:0]
fS/0.5, 1, 1.5, 2, 3, 4, 6
ADCs
DACs
R0: CLOCK
CONTROL REGISTER
R1: PLL CONTROL REGISTER
R17: CONVERTER
SAMPLING RATE
÷ X
MCLK
× (R + N/M)
CORE
CLOCK
INFREQ[1:0]
CONVSR[2:0]
fS/0.5, 1, 1.5, 2, 3, 4, 6
256 × fS, 512 × fS
768 × fS, 1024 × fS
,
CLKSRC
R64: SERIAL PORT
SAMPLING RATE
SERIAL
DATA INPUT/
OUTPUT PORT
SPSR[2:0]
fS/0.5, 1, 1.5, 2, 3, 4, 6
ADC_SDATA/GPIO1
BCLK/GPIO2
LRCLK/GPIO3
DAC_SDATA/GPIO0
Figure 30. Clock Tree Diagram
To utilize the maximum amount of DSP instructions, the core
clock should run at a rate of 1024 × fS.
CORE CLOCK
Clocks for the converters, the serial ports, and the DSP are
derived from the core clock. The core clock can be derived
directly from MCLK or it can be generated by the PLL. The
CLKSRC bit (Bit 3 in Register R0, Address 0x4000) determines
the clock source.
Table 12. Clock Control Register (Register R0, Address 0x4000)
Bits
Bit Name
Settings
3
CLKSRC
0: Direct from MCLK pin (default)
1: PLL clock
[2:1]
0
INFREQ[1:0]
COREN
00: 256 × fS (default)
01: 512 × fS
10: 768 × fS
The INFREQ[1:0] bits should be set according to the expected
input clock rate selected by CLKSRC; this value also determines
the core clock rate and the base sampling frequency, fS.
11: 1024 × fS
For example, if the input to CLKSRC = 49.152 MHz (from
PLL), then
0: Core clock disabled (default)
1: Core clock enabled
INFREQ[1:0] = 1024 × fS
fS = 49.152 MHz/1024 = 48 kHz
The PLL output clock rate is always 1024 × fS, and the clock
control register automatically sets the INFREQ[1:0] bits to
1024 × fS when using the PLL. When using a direct clock, the
INFREQ[1:0] frequency should be set according to the MCLK
pin clock rate and the desired base sampling frequency.
Rev. C | Page 26 of 92
ADAU1761
PLL
SAMPLING RATES
The PLL uses the MCLK as a reference to generate the core
clock. PLL settings are set in Register R1 (PLL control register,
Address 0x4002). Depending on the MCLK frequency, the PLL
must be set for either integer or fractional mode. The PLL can
accept input frequencies in the range of 8 MHz to 27 MHz.
The ADCs, DACs, and serial port share a common sampling
rate that is set in Register R17 (Converter Control 0 register,
Address 0x4017). The CONVSR[2:0] bits set the sampling rate
as a ratio of the base sampling frequency. The DSP sampling
rate is set in Register R57 (DSP sampling rate setting register,
Address 0x40EB) using the DSPSR[3:0] bits, and the serial port
sampling rate is set in Register R64 (serial port sampling rate
register, Address 0x40F8) using the SPSR[2:0] bits.
All six bytes in the PLL control register must be written with a
single continuous write to the control port.
TO PLL
CLOCK DIVIDER
÷ X
MCLK
× (R + N/M)
It is recommended that the sampling rates for the converters,
serial ports, and DSP be set to the same value, unless appropriate
compensation filtering is done within the DSP. Table 13 and
Table 14 list the sampling rate divisions for common base
sampling rates.
Figure 31. PLL Block Diagram
Integer Mode
Integer mode is used when the MCLK is an integer (R) multiple
of the PLL output (1024 × fS).
Table 13. 48 kHz Base Sampling Rate Divisions
For example, if MCLK = 12.288 MHz and fS = 48 kHz, then
PLL required output = 1024 × 48 kHz = 49.152 MHz
R = 49.152 MHz/12.288 MHz = 4
Base Sampling
Frequency
Sampling Rate Scaling Sampling Rate
fS = 48 kHz
fS/1
fS/6
48 kHz
8 kHz
In integer mode, the values set for N and M are ignored.
Fractional Mode
fS/4
fS/3
fS/2
fS/1.5
fS/0.5
12 kHz
16 kHz
24 kHz
32 kHz
96 kHz
Fractional mode is used when the MCLK is a fractional
(R + (N/M)) multiple of the PLL output.
For example, if MCLK = 12 MHz and fS = 48 kHz, then
PLL required output = 1024 × 48 kHz = 49.152 MHz
R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)
Table 14. 44.1 kHz Base Sampling Rate Divisions
Base Sampling
Frequency
Sampling Rate Scaling Sampling Rate
Common fractional PLL parameter settings for 44.1 kHz and
48 kHz sampling rates can be found in Table 16 and Table 17.
fS = 44.1 kHz
fS/1
fS/6
fS/4
fS/3
fS/2
fS/1.5
fS/0.5
44.1 kHz
7.35 kHz
11.025 kHz
14.7 kHz
22.05 kHz
29.4 kHz
88.2 kHz
The PLL outputs a clock in the range of 41 MHz to 54 MHz,
which should be taken into account when calculating PLL
values and MCLK frequencies.
Table 15. PLL Control Register (Register R1, Address 0x4002)
Bits
Bit Name
Description
[47:32]
M[15:0]
Denominator of the fractional PLL: 16-bit binary number
0x00FD: M = 253 (default)
[31:16]
[14:11]
N[15:0]
R[3:0]
Numerator of the fractional PLL: 16-bit binary number
0x000C: N = 12 (default)
Integer part of PLL: four bits, only values 2 to 8 are valid
0010: R = 2 (default)
0011: R = 3
0100: R = 4
0101: R = 5
0110: R = 6
0111: R = 7
1000: R = 8
Rev. C | Page 27 of 92
ADAU1761
Bits
Bit Name
Description
[10:9]
X[1:0]
PLL input clock divider
00: X = 1 (default)
01: X = 2
10: X = 3
11: X = 4
8
1
0
Type
Lock
PLL operation mode
0: Integer (default)
1: Fractional
PLL lock (read-only bit)
0: PLL unlocked (default)
1: PLL locked
PLLEN
PLL enable
0: PLL disabled (default)
1: PLL enabled
Table 16. Fractional PLL Parameter Settings for fS = 44.1 kHz (PLL Output = 45.1584 MHz = 1024 × fS)
MCLK Input (MHz)
Input Divider (X)
Integer (R)
Denominator (M)
Numerator (N)
R2: PLL Control Setting (Hex)
0x0271 0193 2901
0x0271 01DD 1901
0x1FBD 0F09 1901
0x007D 0022 3301
0x007D 0058 2301
0x0401 025C 2301
0x055F 0304 2301
0x0271 01DD 1B01
0x1FBD 0F09 1B01
0x0753 0287 1B01
8
12
13
14.4
19.2
19.68
19.8
24
1
1
1
2
2
2
2
2
2
2
5
3
3
6
4
4
4
3
3
3
625
625
8125
125
125
1025
1375
625
8125
1875
403
477
3849
34
88
604
772
477
3849
647
26
27
Table 17. Fractional PLL Parameter Settings for fS = 48 kHz (PLL Output = 49.152 MHz = 1024 × fS)
MCLK Input (MHz)
Input Divider (X)
Integer (R)
Denominator (M)
Numerator (N)
R2: PLL Control Setting (Hex)
0x007D 0012 3101
0x007D 000C 2101
0x0659 04F5 1901
0x004B 003E 3301
0x0019 0003 2B01
0x00CD 00CC 2301
0x0339 031C 2301
0x007D 000C 2301
0x0659 04F5 1B01
0x0465 02D1 1B01
8
12
13
14.4
19.2
19.68
19.8
24
1
1
1
2
2
2
2
2
2
2
6
4
3
6
5
4
4
4
3
3
125
125
1625
75
18
12
1269
62
3
204
796
12
1269
721
25
205
825
125
1625
1125
26
27
Table 18. Integer PLL Parameter Settings for fS = 48 kHz (PLL Output = 49.152 MHz = 1024 × fS)
MCLK Input (MHz)
Input Divider (X)
Integer (R)
Denominator (M)
Numerator (N)
R2: PLL Control Setting (Hex)1
0xXXXX XXXX 2001
12.288
24.576
1
1
4
2
Don’t care
Don’t care
Don’t care
Don’t care
0xXXXX XXXX 1001
1 X = don’t care.
Rev. C | Page 28 of 92
ADAU1761
RECORD SIGNAL PATH
MICIN LEFT
DIGITAL
MICROPHONE
INTERFACE
JACKDET/MICIN
MICIN RIGHT
LINNG[2:0]
MIXER 1
(LEFT RECORD
MIXER)
–12dB TO +6dB
LDBOOST[1:0]
PGA
LINN
LEFT
ADC
MUTE/0dB/20dB
LINPG[2:0]
–12dB TO
+35.25dB
LINP
–12dB TO +6dB
MIXER 1
INSEL
OUTPUT
(TO PLAYBACK
MIXER)
ALCSEL[2:0]
LDVOL[5:0]
ALC
CONTROL
DECIMATOR/
ALC/
DIGITAL
VOLUME
MX1AUXG[2:0]
LAUX
RAUX
–12dB TO +6dB
AUXILIARY
BYPASS
MX2AUXG[2:0]
–12dB TO +6dB
RINPG[2:0]
MIXER 2
OUTPUT
(TO PLAYBACK
MIXER)
–12dB TO +6dB
RDBOOST[1:0]
PGA
RINP
RINN
RIGHT
ADC
MUTE/0dB/20dB
RINNG[2:0]
MIXER 2
–12dB TO
+35.25dB
(RIGHT RECORD
MIXER)
INSEL
–12dB TO +6dB
ALCSEL[2:0]
RDVOL[5:0]
ALC
CONTROL
Figure 32. Record Signal Path
Signals are inverted through the PGAs and the mixers. The
result of this inversion is that differential signals input through
the PGA are output from the ADCs at the same polarity as they
are input. Single-ended inputs that pass through the mixer but
not through the PGA are inverted. The ADCs are noninverting.
INPUT SIGNAL PATHS
The ADAU1761 can accept both line level and microphone
inputs. The analog inputs can be configured in a single-ended
or differential configuration. There is also an input for a digital
microphone. The analog inputs are biased at AVDD/2. Unused
input pins should be connected to CM.
The input impedance of the analog inputs varies with the gain
of the PGA. This impedance ranges from 1.7 kΩ at the 35.25 dB
gain setting to 80.4 kΩ at the −12 dB setting. This range is shown
in Figure 25.
Each of the six analog inputs has individual gain controls (boost
or cut). The input signals are mixed and routed to an ADC. The
mixed input signals can also bypass the ADCs and be routed
directly to the playback mixers. Left channel inputs are mixed
before the left ADC; however, it is possible to route the mixed
analog signal around the ADC and output it into a left or right
output channel. The same capabilities apply to the right channel
and the right ADC.
Rev. C | Page 29 of 92
ADAU1761
Analog Microphone Inputs
Analog Line Inputs
For microphone inputs, configure the part in either stereo
pseudo-differential mode or stereo full differential mode.
Line input signals can be accepted by any analog input. It is
possible to route signals on the RINN, RINP, LINN, and LINP
pins around the differential amplifier to their own amplifier and
to use these pins as single-ended line inputs by disabling the
LDEN and RDEN bits (Bit 0 in Register R8, Address 0x400E,
and Bit 0 in Register R9, Address 0x400F). Figure 35 depicts a
stereo single-ended line input using the RINN and LINN pins.
The LINN and LINP pins are the inverting and noninverting
inputs for the left channel, respectively. The RINN and RINP
pins are the inverting and noninverting inputs for the right
channel, respectively.
For a differential microphone input, connect the positive signal
to the noninverting input of the PGA and the negative signal to
the inverting input of the PGA, as shown in Figure 33. The PGA
settings are controlled with Register R8 (left differential input
volume control register, Address 0x400E) and Register R9 (right
differential input volume control register, Address 0x400F). The
PGA must first be enabled by setting the RDEN and LDEN bits.
The LAUX and RAUX pins are single-ended line inputs. They
can be used together as a stereo single-ended auxiliary input, as
shown in Figure 35. These inputs can bypass the input gain
control, mixers, and ADCs to directly connect to the output
playback mixers (see auxiliary bypass in Figure 32).
ADAU1761
LINNG[2:0]
ADAU1761
LINN
LEFT LINE
LEFT
INPUT
PGA
LDBOOST[1:0]
LINP
–12dB TO +6dB
LEFT
LINN
LAUX
MICROPHONE
LEFT AUX
INPUT
MUTE/
AUXILIARY
BYPASS
0dB/20dB
–12dB TO
+35.25dB
2kꢀ
2kꢀ
RAUX
RIGHT AUX
MICBIAS
INPUT
RINNG[2:0]
RINN
RIGHT LINE
RIGHT
PGA
INPUT
RDBOOST[1:0]
RINN
RINP
–12dB TO +6dB
RIGHT
MICROPHONE
Figure 35. Stereo Single-Ended Line Input with Stereo Auxiliary Bypass
MUTE/
0dB/20dB
–12dB TO
+35.25dB
Figure 33. Stereo Differential Microphone Configuration
The PGA can also be used for single-ended microphone inputs.
Connect LINP and/or RINP to the CM pin. In this configura-
tion, the signal connects to the inverting input of the PGA,
LINN and/or RINN, as shown in Figure 34.
ADAU1761
LEFT
PGA
LDBOOST[1:0]
LINN
LEFT
MICROPHONE
LINP
MUTE/
0dB/20dB
CM
–12dB TO
+35.25dB
2kꢀ
2kꢀ
MICBIAS
RIGHT
PGA
RDBOOST[1:0]
RINP
RINN
RIGHT
MICROPHONE
MUTE/
0dB/20dB
–12dB TO
+35.25dB
Figure 34. Stereo Single-Ended Microphone Configuration
Rev. C | Page 30 of 92
ADAU1761
Digital Microphone Input
Microphone Bias
When using a digital microphone connected to the JACKDET/
MICIN pin, the JDFUNC[1:0] bits in Register R2 (Address 0x4008)
must be set to 10 to enable the microphone input and disable the
jack detection function. The ADAU1761 must operate in master
mode and source BCLK to the input clock of the digital micro-
phone. The DSPRUN bit must also be asserted in Register R62
(DSP run register, Address 0x40F6) for digital microphone
operation.
The MICBIAS pin provides a voltage reference for electret analog
microphones. The MICBIAS voltage is set in Register R10
(record microphone bias control register, Address 0x4010). In
this register, the MICBIAS output can be enabled or disabled.
Additional options include high performance operation and a
gain boost. The gain boost provides two different voltage biases:
0.65 × AVDD or 0.90 × AVDD. When enabled, the high perfor-
mance bit increases supply current to the microphone bias
circuit to decrease rms input noise.
The digital microphone signal bypasses record path mixers and
ADCs and is routed directly into the decimation filters. The
digital microphone and ADCs share decimation filters and,
therefore, both cannot be used simultaneously. The digital
microphone input select bit, INSEL, can be set in Register R19
(ADC control register, Address 0x4019). Figure 36 depicts the
digital microphone interface and signal routing.
The MICBIAS pin can also be used to cleanly supply voltage
to digital microphones or analog microphones with separate
power supply pins.
ANALOG-TO-DIGITAL CONVERTERS
The ADAU1761 uses two 24-bit Σ-Δ analog-to-digital con-
verters (ADCs) with selectable oversampling ratios of 64× or
128× (selected by Bit 3 in Register R17, Address 0x4017).
JACKDET/MICIN
R2: DIGITAL MICROPHONE/
JACK DETECTION
CONTROL
ADC Full-Scale Level
JDFUNC[1:0]
The full-scale input to the ADCs (0 dBFS) depends on AVDD.
At AVDD = 3.3 V, the full-scale input level is 1.0 V rms. This
full-scale analog input will output a digital signal at −1.38 dBFS.
This gain offset is built into the ADAU1761 to prevent clipping.
The full-scale input level scales linearly with the level of AVDD.
TO JACK
DETECTION
CIRCUIT
DIGITAL MICROPHONE
INTERFACE
RIGHT
ADC
LEFT
RIGHT
CHANNEL CHANNEL
For single-ended and pseudo-differential signals, the full-scale
value corresponds to the signal level at the pins, 0 dBFS.
LEFT
ADC
The full differential full-scale input level is measured after the
differential amplifier, which corresponds to −6 dBFS at each pin.
R19: ADC CONTROL
INSEL
Signal levels above the full-scale value cause the ADCs to clip.
Digital ADC Volume Control
DECIMATORS
The digital ADC volume can be attenuated before DSP pro-
cessing using Register R20 (left input digital volume register,
Address 0x401A) and Register R21 (right input digital volume
register, Address 0x401B).
Figure 36. Digital Microphone Interface Block Diagram
High-Pass Filter
By default, a high-pass filter is used in the ADC path to remove
dc offsets; this filter can be enabled or disabled in Register R19
(ADC control register, Address 0x4019). At fS = 48 kHz, the
corner frequency of this high-pass filter is 2 Hz.
Rev. C | Page 31 of 92
ADAU1761
AUTOMATIC LEVEL CONTROL (ALC)
The ADAU1761 contains a hardware automatic level control
(ALC). The ALC is designed to continuously adjust the PGA
gain to keep the recording volume constant as the input level
varies.
•
ALCATCK[3:0]: The ALC attack time sets how fast the
ALC starts attenuating after a sudden increase in input
level above the ALC target. Although it may seem that
the attack time should be set as fast as possible to avoid
clipping on transients, using a moderate value results in
better overall sound quality. If the value is too fast, the
ALC overreacts to very short transients, causing audible
gain-pumping effects, which sounds worse than using a
moderate value that allows brief periods of clipping on
transients. A typical setting for music recording is 384 ms.
A typical setting for voice recording is 24 ms.
ALCHOLD[3:0]: These bits set the ALC hold time. When
the output signal falls below the target output level, the
gain is not increased unless the output remains below the
target level for the period of time set by the hold time bits.
The hold time is used to prevent the gain from modulating
on a steady low frequency sine wave signal, which would
cause distortion.
ALCDEC[3:0]: The ALC decay time sets how fast the ALC
increases the PGA gain after a sudden decrease in input level
below the ALC target. A very slow setting can be used if the
main function of the ALC is to set a music recording level.
A faster setting can be used if the function of the ALC is to
compress the dynamic range of a voice recording. Using a
very fast decay time can cause audible artifacts such as noise
pumping or distortion. A typical setting for music recording
is 24.58 sec. A typical setting for voice recording is 1.54 sec.
ALCMAX[2:0]: The maximum ALC gain bits are used to
limit the maximum gain that can be programmed into the
ALC. This can be used to prevent excessive noise in the
recording for small input signals. Note that setting this
register to a low value may prevent the ALC from reaching
its target output level, but this behavior is often desirable to
achieve the best overall sound.
For optimal noise performance, the ALC uses the analog PGA
to adjust the gain instead of using a digital method. This ensures
that the ADC noise is not amplified at low signal levels.
Extremely small gain step sizes are used to ensure high audio
quality during gain changes.
To use the ALC function, the inputs must be applied either
differentially or pseudo-differentially to input pins LINN and
LINP, for the left channel, and RINN and RINP, for the right
channel. The ALC function is not available for the auxiliary line
input pins, LAUX and RAUX.
•
•
A block diagram of the ALC block is shown in Figure 37. The
ALC logic receives the ADC output signals and analyzes these
digital signals to set the PGA gain. The ALC control registers
are used to control the time constants and output levels, as
described in this section.
ANALOG
LEFT
INPUT
ADC
LEFT
PGA
SERIAL
PORTS
–12dB TO +35.25dB
0.75dB STEP SIZE
MUTE
ANALOG
INPUT
RIGHT
RIGHT
ADC
2
I C
ALC
DIGITAL
CONTROL
•
Figure 37. ALC Architecture
ALC PARAMETERS
The ALC function is controlled with the ALC control registers
(Address 0x4011 through Address 0x4014) using the following
parameters:
•
ALCSEL[2:0]: The ALC select bits are used to enable the
ALC and set the mode to left only, right only, stereo, or
DSP. In stereo mode, the greater of the left or right inputs
is used to calculate the gain, and the same gain is then
applied to both the left and right channels. In DSP mode,
the PGA gain is controlled by the SigmaDSP core.
ALCTARG[3:0]: The ALC target is the desired input
recording level that the ALC attempts to achieve.
Figure 38 shows the dynamic behavior of the PGA gain for a
tone-burst input. The target output is achieved for three differ-
ent input levels, with the effect of attack, hold, and decay shown
in the figure. Note that for very small signals, the maximum PGA
gain may prevent the ALC from achieving its target level; in the
same way, for very large inputs, the minimum PGA gain may
prevent the ALC from achieving its target level (assuming that
the target output level is set to a very low value). The effects of
the PGA gain limit are shown in the input/output graph of
Figure 39.
•
Rev. C | Page 32 of 92
ADAU1761
the threshold for 250 ms before the noise gate operates.
Hysteresis is used so that the threshold for coming out of the
mute state is 6 dB higher than the threshold for going into the
mute state. There are four operating modes for the noise gate.
INPUT
Noise Gate Mode 0 (see Figure 40) is selected by setting the
NGTYP[1:0] bits to 00. In this mode, the current state of the
PGA gain is held at its current state when the noise gate logic is
activated. This prevents a large increase in background noise
during periods of silence. When using this mode, it is advisable
to use a relatively slow decay time. This is because the noise gate
takes at least 250 ms to activate, and if the PGA gain has already
increased to a large value during this time, the value at which
the gain is held will be large.
GAIN
OUTPUT
THRESHOLD
INPUT
HOLD DECAY
TIME TIME
ATTACK
TIME
Figure 38. Basic ALC Operation
ANALOG
GAIN
MAX GAIN = 30dB
MAX GAIN = 24dB
MAX GAIN = 18dB
250ms
GAIN HELD
INTERNAL
NOISE GATE
ENABLE SIGNAL
MIN PGA
GAIN POINT
DIGITAL
MUTE
TARGET
OUTPUT
INPUT LEVEL (dB)
Figure 39. Effect of Varying the Maximum Gain Parameter
Figure 40. Noise Gate Mode 0 (PGA Gain Hold)
NOISE GATE FUNCTION
When using the ALC, one potential problem is that for small
input signals, the PGA gain can become very large. A side effect
of this is that the noise is amplified along with the signal of
interest. To avoid this situation, the ADAU1761 noise gate can
be used. The noise gate cuts off the ADC output when its signal
level is below a set threshold. The noise gate is controlled using
the following parameters in the ALC Control 3 register
(Address 0x4014):
Noise Gate Mode 1 (see Figure 41) is selected by setting the
NGTYP[1:0] bits to 01. In this mode, the ADAU1761 does a
simple digital mute of the ADC output. Although this mode
completely eliminates any background noise, the effect of an
abrupt mute may not be pleasant to the ear.
THRESHOLD
INPUT
•
•
•
NGTYP[1:0]: The noise gate type is set to one of four
modes by writing to the NGTYP[1:0] bits.
NGEN: The noise gate function is enabled by writing to the
NGEN bit.
NGTHR[4:0]: The threshold for muting the output is set by
writing to the NGTHR[4:0] bits.
ANALOG
GAIN
250ms
INTERNAL
NOISE GATE
ENABLE SIGNAL
DIGITAL
MUTE
One common problem with noise gate functions is chatter,
where a small signal that is close to the noise gate threshold
varies in amplitude, causing the noise gate function to open and
close rapidly. This causes an unpleasant sound.
OUTPUT
To reduce this effect, the noise gate in the ADAU1761 uses a
combination of a timeout period and hysteresis. The timeout
period is set to 250 ms, so the signal must consistently be below
Figure 41. Noise Gate Mode 1 (Digital Mute)
Rev. C | Page 33 of 92
ADAU1761
Noise Gate Mode 2 (see Figure 42) is selected by setting the
NGTYP[1:0] bits to 10. In this mode, the ADAU1761 improves
the sound of the noise gate operation by first fading the PGA
gain over a period of about 100 ms to the minimum PGA gain
value. The ADAU1761 does not do a hard mute after the fade is
complete, so some small background noise will still exist.
Noise Gate Mode 3 (see Figure 43) is selected by setting the
NGTYP[1:0] bits to 11. This mode is the same as Mode 2 except
that at the end of the PGA fade gain interval, a digital mute is
performed. In general, this mode is the best-sounding mode,
because the audible effect of the digital hard mute is reduced by
the fact that the gain has already faded to a low level before the
mute occurs.
THRESHOLD
THRESHOLD
INPUT
INPUT
ANALOG
ANALOG
GAIN
250ms
GAIN
250ms
MIN GAIN
100ms
MIN GAIN
100ms
INTERNAL
NOISE GATE
ENABLE SIGNAL
INTERNAL
NOISE GATE
ENABLE SIGNAL
DIGITAL
MUTE
DIGITAL
MUTE
OUTPUT
OUTPUT
Figure 43. Noise Gate Mode 3 (Analog Fade/Digital Mute)
Figure 42. Noise Gate Mode 2 (Analog Fade)
Rev. C | Page 34 of 92
ADAU1761
PLAYBACK SIGNAL PATH
MX3G1[3:0]
LEFT INPUT MIXER
–15dB TO +6dB
MX3G2[3:0]
RIGHT INPUT MIXER
–15dB TO +6dB
MIXER 3
(LEFT
PLAYBACK
MIXER)
MX3AUXG[3:0]
LHPVOL[5:0]
LAUX
LHP
–15dB TO +6dB
–57dB TO +6dB
LOUTVOL[5:0]
MIXER 5
(LEFT L/R
PLAYBACK
MIXER)
LEFT DAC
LOUTP
MX3LM
MX3RM
–57dB TO +6dB
MX5G3[1:0]
RIGHT DAC
–1
LOUTN
MX6G3[1:0]
MONOVOL[5:0]
MX7[1:0]
MIXER 7
(MONO MIXER)
MONOOUT
ROUTN
–57dB TO +6dB
–1
MX4G1[3:0]
MIXER 6
(RIGHT L/R
PLAYBACK
MIXER)
LEFT INPUT MIXER
–15dB TO +6dB
ROUTVOL[5:0]
MX5G4[1:0]
MX4G2[3:0]
ROUTP
RHP
–57dB TO +6dB
RIGHT INPUT MIXER
–15dB TO +6dB
MX6G4[1:0]
MX4AUXG[3:0]
RHPVOL[5:0]
RAUX
–15dB TO +6dB
–57dB TO +6dB
MIXER 4
(RIGHT
PLAYBACK
MIXER)
LEFT DAC
MX4LM
MX4RM
RIGHT DAC
Figure 44. Playback Signal Path
Routing Flexibility
OUTPUT SIGNAL PATHS
The playback path contains five mixers (Mixer 3 to Mixer 7)
that perform the following functions:
The outputs of the ADAU1761 can be configured as a variety of
differential or single-ended outputs. All analog output pins are
capable of driving headphone or earpiece speakers. There are
selectable output paths for stereo signals or a downmixed mono
output. The line outputs can drive a load of at least 10 kΩ or can
be put into HP mode to drive headphones or earpiece speakers.
The analog output pins are biased at AVDD/2.
•
•
•
Mix signals from the record path and the DACs.
Mix or swap the left and right channels.
Mix a mono signal or generate a common-mode output.
Mixer 3 and Mixer 4 are dedicated to mixing signals from the
record path and the DACs. Each of these two mixers can accept
signals from the left and right DACs, the left and right input
mixers, and the dedicated channel auxiliary input. Signals
coming from the record path can be boosted or cut before the
playback mixer.
With a 0 dBFS digital input and AVDD = 1.8 V, the full-scale
output level is 500 mV rms; when AVDD = 3.3 V, the full-scale
output level is 920 mV rms.
Signals are inverted through the mixers and volume controls.
The result of this inversion is that the polarity of the differential
outputs and the headphone outputs is preserved. The single-
ended mono output is inverted. The DACs are noninverting.
For example, the MX4G2[3:0] bits set the gain from the output
of Mixer 2 (right record channel) to the input of Mixer 4, hence
the naming convention.
Signals coming from the DACs have digital volume attenu-
ation controls set in Register R20 (left input digital volume
register, Address 0x401A) and Register R21 (right input digital
volume register, Address 0x401B).
Rev. C | Page 35 of 92
ADAU1761
Headphone Output Power-Up/Power-Down Sequencing
HEADPHONE OUTPUT
To prevent pops when turning on the headphone outputs, the
user must wait at least 4 ms to unmute these outputs after
enabling the headphone output with the HPMODE bit. This is
because of an internal capacitor that must charge before these
outputs can be used. Figure 46 and Figure 47 illustrate the
headphone power-up/power-down sequencing.
The LHP and RHP pins can be driven by either a line output
driver or a headphone driver by setting the HPMODE bit in
Register R30 (playback headphone right volume control register,
Address 0x4024). The headphone outputs can drive a load of at
least 16 Ω.
Separate volume controls for the left and right channels range
from −57 dB to +6 dB. Slew can be applied to all the playback
volume controls using the ASLEW[1:0] bits in Register R34
(playback pop/click suppression register, Address 0x4028).
For capless headphones, configure the MONOOUT pin before
unmuting the headphone outputs.
USER
DEFINED
4ms
Capless Headphone Configuration
HPMODE
The headphone outputs can be configured in a capless output
configuration with the MONOOUT pin used as a dc virtual
ground reference. Figure 45 depicts a typical playback path in
a capless headphone configuration. Table 19 lists the register
settings for this configuration. As shown in this table, the
MONOOUT pin outputs common mode (AVDD/2), which
is used as the virtual headphone reference.
1 = HEADPHONE
RHPM AND LHPM
1 = UNMUTE
INTERNAL
PRECHARGE
LHPVOL[5:0]
Figure 46. Headphone Output Power-Up Timing
MIXER 3
MX3LM
LEFT
DAC
LHP
MX3EN
USER DEFINED
RHPM AND LHPM
0 = MUTE
MONOM
MIXER 7
MONOOUT
MX7[1:0]
MX7EN
MOMODE
HPMODE
0 = LINE OUTPUT
RHPVOL[5:0]
MIXER 4
MX4EN
MX4RM
RIGHT
DAC
Figure 47. Headphone Output Power-Down Timing
RHP
Ground-Centered Headphone Configuration
The headphone outputs can also be configured as ground-
centered outputs by placing coupling capacitors on the LHP
and RHP pins. Ground-centered headphones should use the
AGND pin as the ground reference.
Figure 45. Capless Headphone Configuration Diagram
Table 19. Capless Headphone Register Settings
Register
Bit Name
DACEN[1:0]
MX3EN
Setting
R36
R22
11 = both DACs on
1 = enable Mixer 3
When the headphone outputs are configured in this manner,
the capacitors create a high-pass filter on the outputs. The
corner frequency of this filter, at which point its attenuation
is 3 dB, is calculated by the following formula:
MX3LM
MX4EN
1 = unmute left DAC input
1 = enable Mixer 4
R24
R28
R33
R29
R30
MX4RM
MX7EN
1 = unmute right DAC input
1 = enable Mixer 7
f
3dB = 1/(2π × R × C)
MX7[1:0]
MONOM
MOMODE
00 = common-mode output
1 = unmute mono output
1 = headphone output
where:
C is the capacitor value.
R is the impedance of the headphones.
LHPVOL[5:0] Desired volume for LHP output
For a typical headphone impedance of 16 Ω and a 47 μF
capacitor, the corner frequency is 211 Hz.
LHPM
HPMODE
1 = unmute left headphone output
1 = headphone output
RHPVOL[5:0] Desired volume for RHP output
RHPM 1 = unmute right headphone output
Rev. C | Page 36 of 92
ADAU1761
Jack Detection
LINE OUTPUTS
When the JACKDET/MICIN pin is set to the jack detect func-
tion, a flag on this pin can be used to mute the line outputs
when headphones are plugged into the jack. This pin can be
configured in Register R2 (digital microphone/jack detection
control register, Address 0x4008). The JDFUNC[1:0] bits set the
functionality of the JACKDET/MICIN pin.
The line output pins (LOUTP, LOUTN, ROUTP, and ROUTN)
can be used to drive both differential and single-ended loads. In
their default settings, these pins can drive typical line loads of
10 kΩ or greater, but they can also be put into headphone mode
by setting the LOMODE bit in Register R31 (playback line output
left volume control register, Address 0x4025) and the ROMODE
bit in Register R32 (playback line output right volume control
register, Address 0x4026). In headphone mode, the line output
pins are capable of driving headphone and earpiece speakers of
16 Ω or greater. The output impedance of the line outputs is
approximately 1 kΩ.
Additional settings for jack detection include debounce time
(JDDB[1:0] bits) and detection polarity (JDPOL bit). Because
the jack detection and digital microphone share a pin, both
functions cannot be used simultaneously.
POP-AND-CLICK SUPPRESSION
When the line output pins are used in single-ended mode,
LOUTP and ROUTP should be used to output the signals, and
LOUTN and ROUTN should be left unconnected.
Upon power-up, precharge circuitry is enabled to suppress pops
and clicks. After power-up, the precharge circuitry can be put
into a low power mode using the POPMODE bit in Register R34
(playback pop/click suppression register, Address 0x4028).
The volume controls for these outputs range from −57 dB to
+6 dB. Slew can be applied to all the playback volume controls
using the ASLEW[1:0] bits in Register R34 (playback pop/click
suppression register, Address 0x4028).
The precharge time depends on the capacitor value on the CM
pin and the RC time constant of the load. For a typical line output
load, the precharge time is between 2 ms and 3 ms. After this
precharge time, the POPMODE bit can be set to low power mode.
The MX5G4[1:0], MX5G3[1:0], MX6G3[1:0], and MX6G4[1:0]
bits can all provide a 6 dB gain boost to the line outputs. This
gain boost allows single-ended output signals to achieve 0 dBV
(1.0 V rms) and differential output signals to achieve up to
6 dBV (2.0 V rms). For more information, see Register R26
(playback L/R mixer left (Mixer 5) line output control register,
Address 0x4020) and Register R27 (playback L/R mixer right
(Mixer 6) line output control register, Address 0x4021).
Changing any register settings that affect the signal path can
cause pops and clicks on the analog outputs. To avoid these pops
and clicks, mute the appropriate outputs using Register R29 to
Register R32 (Address 0x4023 to Address 0x4026). Unmute the
analog outputs after the changes are made.
MX5G3[1:0]
LOUTVOL[5:0]
MIXER 3
MIXER 5
LEFT DAC
LOUTP
–1
–1
LOUTN
ROUTN
MX6G4[1:0]
ROUTVOL[5:0]
MIXER 4
MIXER 6
RIGHT DAC
ROUTP
Figure 48. Differential Line Output Configuration
Rev. C | Page 37 of 92
ADAU1761
CONTROL PORTS
The ADAU1761 can operate in one of two control modes:
The registers in the ADAU1761 are one byte wide with the
exception of the PLL control register, which is six bytes wide.
The autoincrement feature knows the word length at each
subaddress, so the subaddress does not need to be specified
manually for each address in a burst write.
•
•
I2C control
SPI control
The ADAU1761 has both a 4-wire SPI control port and a
2-wire I2C bus control port. Both ports can be used to set the
registers. The part defaults to I2C mode, but it can be put into
The subaddresses are autoincremented by 1 following each read
or write of a data-word, regardless of whether there is a valid regis-
ter or RAM word at that address. Address holes in the register
map can be written to or read from without consequence. In the
ADAU1761, these address holes exist at Address 0x4001, Address
0x4003 to Address 0x4007, Address 0x402E, Address 0x4032 to
Address 0x4035, Address 0x4037 to Address 0x40BF, Address
0x40C5, Address 0x40CA to Address 0x40CF, Address 0x40D5
to Address 0x40EA, and Address 0x40EC to Address 0x40F1. A
single-byte write to these registers is ignored by the ADAU1761,
and a read returns a single byte 0x00.
CLATCH
SPI control mode by pulling the
pin low three times.
The control port is capable of full read/write operation for all
addressable registers. The ADAU1761 must have a valid master
clock in order to write to all registers except for Register R0
(Address 0x4000) and Register R1 (Address 0x4002).
All addresses can be accessed in both a single-address mode
or a burst mode. The first byte (Byte 0) of a control port write
contains the 7-bit chip address plus the R/ bit. The next two
W
bytes (Byte 1 and Byte 2) together form the subaddress of the
register location within the ADAU1761. This subaddress must
be two bytes long because the memory locations within the
ADAU1761 are directly addressable and their sizes exceed the
range of single-byte addressing. All subsequent bytes (starting
with Byte 3) contain the data, such as control port data, program
data, or parameter data. The number of bytes per word depends
on the type of data that is being written.
I2C PORT
The ADAU1761 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAU1761 and the system I2C master controller.
In I2C mode, the ADAU1761 is always a slave on the bus,
meaning that it cannot initiate a data transfer. Each slave device
W
is recognized by a unique address. The address and R/ byte
The ADAU1761 has several mechanisms for updating signal pro-
cessing parameters in real time without causing pops or clicks. If
large blocks of data need to be downloaded, the output of the DSP
core can be halted (using the DSPRUN bit in the DSP run register,
Address 0x40F6), new data can be loaded, and the device can be
restarted. This is typically done during the booting sequence at
start-up or when loading a new program into RAM.
format is shown in Table 21. The address resides in the first
seven bits of the I2C write. Bits[5:6] of the I2C address for the
ADAU1761 are set by the levels on the ADDR1 and ADDR0
pins. The LSB of the address—the R/ bit—specifies either a
read or write operation. Logic Level 1 corresponds to a read
operation, and Logic Level 0 corresponds to a write operation.
W
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 20 describes these
multiple functions.
2
Write
Table 21. ADAU1761 I C Address and Read/
Byte Format
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5
Bit 6 Bit 7
0
1
1
1
0
ADDR1 ADDR0 R/W
Table 20. Control Port Pin Functions
The SDA and SCL pins should each have a 2 kꢁ pull-up resistor
on the line connected to it. The voltage on these signal lines
should not be higher than IOVDD (1.8 V to 3.3 V).
Pin Name
SCL/CCLK
SDA/COUT
I2C Mode
SPI Mode
SCL: input clock
CCLK: input clock
COUT: output
SDA: open-collector
input/output
I2C Address Bit 1: input
Addressing
Initially, each device on the I2C bus is in an idle state and
monitors the SDA and SCL lines for a start condition and
the proper address. The I2C master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address/
data stream follows. All devices on the bus respond to the start
condition and shift the next eight bits (the 7-bit address plus the
ADDR1/CDATA
ADDR0/CLATCH I2C Address Bit 0: input
CDATA: input
CLATCH: input
BURST MODE WRITING AND READING
Burst mode addressing, where the subaddresses are automatically
incremented at word boundaries, can be used for writing large
amounts of data to contiguous registers. This increment happens
automatically after a single-word write or read unless a stop condi-
W
R/ bit) MSB first. The device that recognizes the transmitted
2
CLATCH
tion is encountered (I C) or
is brought high (SPI). A
address responds by pulling the data line low during the ninth
clock pulse. This ninth bit is known as an acknowledge bit. All
other devices withdraw from the bus at this point and return to
the idle condition.
burst write starts like a single-word write, but following the first
data-word, the data-word for the next immediate address can be
written immediately without sending its two-byte address.
Rev. C | Page 38 of 92
ADAU1761
W
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADAU1761 does
not issue an acknowledge and returns to the idle condition.
The R/ bit determines the direction of the data. A Logic 0 on
the LSB of the first byte means that the master will write infor-
mation to the peripheral, whereas a Logic 1 means that the
master will read information from the peripheral after writing
the subaddress and repeating the start address. A data transfer
takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
SCL is held high. Figure 49 shows the timing of an I2C write,
and Figure 50 shows an I2C read.
If the user exceeds the highest subaddress while in autoincrement
mode, one of two actions is taken. In read mode, the ADAU1761
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse on SCL. If the highest subaddress
location is reached while in write mode, the data for the invalid
byte is not loaded into any subaddress register, a no acknowledge
is issued by the ADAU1761, and the part returns to the idle
condition.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the ADAU1761 immediately
jumps to the idle condition. During a given SCL high period,
SCL
0
1
1
1
SDA
R/W
0
ADDR1 ADDR0
ACK BY
ADAU1761
ACK BY
ADAU1761
START BY
MASTER
FRAME 2
SUBADDRESS BYTE 1
FRAME 1
CHIP ADDRESS BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
ACK BY
ADAU1761
ACK BY STOP BY
ADAU1761 MASTER
FRAME 4
DATA BYTE 1
FRAME 3
SUBADDRESS BYTE 2
Figure 49. I2C Write to ADAU1761 Clocking
SCL
SDA
0
1
1
1
0
R/W
ACK BY
ADAU1761
ADDR1 ADDR0
ACK BY
ADAU1761
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
SCL
(CONTINUED)
SDA
(CONTINUED)
0
1
1
1
0
R/W
ACK BY
ADAU1761
ADDR1 ADDR0
ACK BY
ADAU1761
REPEATED
START BY MASTER
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
CHIP ADDRESS BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
ACK BY
STOP BY
MASTER MASTER
FRAME 5
READ DATA BYTE 1
Figure 50. I2C Read from ADAU1761 Clocking
Rev. C | Page 39 of 92
ADAU1761
I2C Read and Write Operations
This causes the ADAU1761 SDA to reverse and begin driving
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1761.
Figure 51 shows the format of a single-word write operation.
Every ninth clock pulse, the ADAU1761 issues an acknowledge
by pulling SDA low.
Figure 54 shows the format of a burst mode read sequence. This
figure shows an example of a read from sequential single-byte
registers. The ADAU1761 increments its subaddress register
after every byte because the requested subaddress corresponds
to a register or memory area with a 1-byte word length. The
ADAU1761 always decodes the subaddress and sets the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
Figure 52 shows the format of a burst mode write sequence. This
figure shows an example of a write to sequential single-byte
registers. The ADAU1761 increments its subaddress register
after every byte because the requested subaddress corresponds
to a register or memory area with a 1-byte word length.
Figure 53 shows the format of a single-word read operation. Note
W
that the first R/ bit is 0, indicating a write operation. This is
Figure 51 to Figure 54 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
because the subaddress still needs to be written to set up the
internal address. After the ADAU1761 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
W
followed by the chip address byte with the R/ bit set to 1 (read).
S
S
S
S
Chip address,
R/W = 0
AS
Subaddress high byte
AS
Subaddress low byte
AS
Data Byte 1
P
Figure 51. Single-Word I2C Write Format
Chip address, AS Subaddress AS Subaddress AS Data
AS Data
Byte 2
AS Data
Byte 3
AS Data
Byte 4
AS
…
P
R/W = 0
high byte
low byte
Byte 1
Figure 52. Burst Mode I2C Write Format
Chip address,
R/W = 0
AS
Subaddress high
byte
AS
Subaddress low
byte
AS
S
Chip address,
R/W = 1
AS
Data
P
Byte 1
Figure 53. Single-Word I2C Read Format
Chip address,
R/W = 0
AS Subaddress AS Subaddress AS
high byte low byte
S
Chip address,
R/W = 1
AS Data
Byte 1
AM Data
Byte 2
AM
…
P
Figure 54. Burst Mode I2C Read Format
Rev. C | Page 40 of 92
ADAU1761
W
Chip Address R/
SPI PORT
By default, the ADAU1761 is in I2C mode, but it can be put into
W
The LSB of the first byte of an SPI transaction is a R/ bit. This bit
determines whether the communication is a read (Logic Level 1)
or a write (Logic Level 0). This format is shown in Table 22.
CLATCH
SPI control mode by pulling
low three times. This is
done by performing three dummy writes to the SPI port (the
ADAU1761 does not acknowledge these three writes). Beginning
with the fourth SPI write, data can be written to or read from
the IC. The ADAU1761 can be taken out of SPI mode only by a
full reset initiated by power-cycling the IC.
Write
Table 22. ADAU1761 SPI Address and Read/
Byte Format
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
0
0
0
0
0
0
R/W
CLATCH
The SPI port uses a 4-wire interface, consisting of the
CCLK, CDATA, and COUT signals, and it is always a slave port.
CLATCH
,
Subaddress
The 16-bit subaddress word is decoded into a location in one of
the registers. This subaddress is the location of the appropriate
register. The MSBs of the subaddress are zero-padded to bring
the word to a full 2-byte length.
The
signal should go low at the beginning of a trans-
action and high at the end of a transaction. The CCLK signal
latches CDATA on a low-to-high transition. COUT data is shifted
out of the ADAU1761 on the falling edge of CCLK and should
be clocked into a receiving device, such as a microcontroller, on
the CCLK rising edge. The CDATA signal carries the serial input
data, and the COUT signal carries the serial output data. The
COUT signal remains three-state until a read operation is requested.
This allows other SPI-compatible peripherals to share the same
readback line. All SPI transactions have the same basic format
shown in Table 23. A timing diagram is shown in Figure 4. All
data should be written MSB first.
Data Bytes
The number of data bytes varies according to the register being
accessed. During a burst mode write, an initial subaddress is
written followed by a continuous sequence of data for consecu-
tive register locations.
A sample timing diagram for a single-word SPI write operation
to a register is shown in Figure 55. A sample timing diagram of
a single-word SPI read operation is shown in Figure 56. The
COUT pin goes from being three-state to being driven at the
beginning of Byte 3. In this example, Byte 0 to Byte 2 contain
W
the addresses and R/ bit, and subsequent bytes carry the data.
Table 23. Generic Control Word Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 41
chip_adr[6:0], R/W
subaddr[15:8]
subaddr[7:0]
data
data
1 Continues to end of data.
CLATCH
CCLK
CDATA
BYTE 0
BYTE 1
BYTE 2
BYTE 3
Figure 55. SPI Write to ADAU1761 Clocking (Single-Word Write Mode)
CLATCH
CCLK
CDATA
COUT
BYTE 1
BYTE 0
BYTE 2
HIGH-Z
HIGH-Z
DATA
Figure 56. SPI Read from ADAU1761 Clocking (Single-Word Read Mode)
Rev. C | Page 41 of 92
ADAU1761
SERIAL DATA INPUT/OUTPUT PORTS
The flexible serial data input and output ports of the ADAU1761
can be set to accept or transmit data in 2-channel format or in
a 4-channel or 8-channel TDM stream to interface to external
ADCs or DACs. Data is processed in twos complement, MSB
first format. The left channel data field always precedes the right
channel data field in 2-channel streams. In TDM mode, Slot 0
to Slot 3 are in the first half of the audio frame, and Slot 4 to
Slot 7 are in the second half of the frame. The serial modes and
the position of the data in the frame are set in Register R15 to
Register R18 (serial port and converter control registers,
Address 0x4015 to Address 0x4018).
The serial port can operate with an arbitrary number of BCLK
transitions in each LRCLK frame. The LRCLK in TDM mode
can be input to the ADAU1761 either as a 50ꢀ duty cycle clock
or as a bit-wide pulse.
When the LRCLK is set as a pulse, a 47 pF capacitor should be
connected between the LRCLK pin and ground (see Figure 57).
This capacitor is necessary in both master and slave modes to
properly align the LRCLK signal to the serial data stream.
ADAU1761
LRCLK
47pF
If the PLL of the ADAU1761 is not used, the serial data clocks
must be synchronous with the ADAU1761 master clock input.
The LRCLK and BCLK pins are used to clock both the serial
input and output ports. The ADAU1761 can be set as the master
or the slave in a system. Because there is only one set of serial
data clocks, the input and output ports must always be both
master or both slave.
BCLK
Figure 57. LRCLK Capacitor Alignment, TDM Pulse Mode
In TDM 8 mode, the ADAU1761 can be a master for fS up to
48 kHz. Table 24 lists the modes in which the serial output port
can function.
Register R15 and Register R16 (serial port control registers,
Address 0x4015 and Address 0x4016) allow control of clock
polarity and data input modes. The valid data formats are I2S,
left-justified, right-justified (24-/20-/18-/16-bit), and TDM. In
all modes except for the right-justified modes, the serial port
inputs an arbitrary number of bits up to a limit of 24. Extra bits
do not cause an error, but they are truncated internally.
Table 24. Serial Output Port Master/Slave Mode Capabilities
2-Channel Modes (I2S, Left-
fS
Justified, Right-Justified)
8-Channel TDM
Master and slave
Slave
48 kHz
96 kHz
Master and slave
Master and slave
Table 25 describes the proper configurations for standard audio
data formats.
Table 25. Data Format Configurations
LRCLK Mode
(LRMOD)
BCLK Polarity
(BPOL)
BCLK Cycles/Audio Data Delay from LRCLK
Format
LRCLK Polarity (LRPOL)
Frame (BPF[2:0])
Edge (LRDEL[1:0])
I2S
Frame begins on falling edge 50% duty cycle Data changes
on falling edge
32 to 64
Delayed from LRCLK edge
by 1 BCLK
(see Figure 58)
Left-Justified (see Frame begins on rising edge
Figure 59)
50% duty cycle Data changes
on falling edge
50% duty cycle Data changes
on falling edge
32 to 64
32 to 64
64 to 256
64 to 256
Aligned with LRCLK edge
Right-Justified
(see Figure 60)
Frame begins on rising edge
Delayed from LRCLK edge
by 8 or 16 BCLKs
Delayed from start of word
clock by 1 BCLK
Delayed from start of word
clock by 1 BCLK
TDM with Clock
(see Figure 61)
Frame begins on falling edge 50% duty cycle Data changes
on falling edge
TDM with Pulse
(see Figure 62)
Frame begins on rising edge
Pulse
Data changes
on falling edge
Rev. C | Page 42 of 92
ADAU1761
LEFT CHANNEL
LRCLK
BCLK
RIGHT CHANNEL
MSB
LSB
LSB
SDATA
MSB
1/fS
Figure 58. I2S Mode—16 Bits to 24 Bits per Channel
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
SDATA
1/fS
Figure 59. Left-Justified Mode—16 Bits to 24 Bits per Channel
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
1/fS
Figure 60. Right-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
256 BCLKs
BCLK
32 BCLKs
SLOT 0
SDATA
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
LRCLK
BCLK
SDATA
MSB
MSB – 1 MSB – 2
Figure 61. TDM 8 Mode
LRCLK
BCLK
MSB TDM
MSB TDM
CH
0
SDATA
CH
8
SLOT 0
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
32
BCLKs
Figure 62. TDM 8 Mode with Pulse Word Clock
Rev. C | Page 43 of 92
ADAU1761
APPLICATIONS INFORMATION
POWER SUPPLY BYPASS CAPACITORS
GROUNDING
Each analog and digital power supply pin should be bypassed to
its nearest appropriate ground pin with a single 100 nF capaci-
tor. The connections to each side of the capacitor should be as
short as possible, and the trace should stay on a single layer with
no vias. For maximum effectiveness, locate the capacitor equi-
distant from the power and ground pins or, when equidistant
placement is not possible, slightly closer to the power pin.
Thermal connections to the ground planes should be made
on the far side of the capacitor.
A single ground plane should be used in the application layout.
Components in an analog signal path should be placed away
from digital signals.
EXPOSED PAD PCB DESIGN
The ADAU1761 has an exposed pad on the underside of the
LFCSP. This pad is used to couple the package to the PCB for
heat dissipation when using the outputs to drive earpiece or
headphone loads. When designing a board for the ADAU1761,
special consideration should be given to the following:
Each supply signal on the board should also be bypassed with a
single bulk capacitor (10 μF to 47 μF).
VDD GND
•
A copper layer equal in size to the exposed pad should be
on all layers of the board, from top to bottom, and should
connect somewhere to a dedicated copper board layer (see
Figure 65).
•
Vias should be placed to connect all layers of copper,
allowing for efficient heat and energy conductivity. For an
example, see Figure 66, which has nine vias arranged in a
3 inch × 3 inch grid in the pad area.
CAPACITOR
TO VDD
TOP
GROUND
POWER
BOTTOM
TO GND
Figure 63. Recommended Power Supply Bypass Capacitor Layout
VIAS
COPPER SQUARES
Figure 65. Exposed Pad Layout Example, Side View
GSM NOISE FILTER
In mobile phone applications, excessive 217 Hz GSM noise on
the analog supply pins can degrade the audio quality. To avoid
this problem, it is recommended that an L-C filter be used in
series with the bypass capacitors for the AVDD pins. This filter
should consist of a 1.2 nH inductor and a 9.1 pF capacitor in
series between AVDD and ground, as shown in Figure 64.
10µF
+
0.1µF
0.1µF
1.2nH 9.1pF
Figure 66. Exposed Pad Layout Example, Top View
AVDD
AVDD
Figure 64. GSM Filter on the Analog Supply Pins
Rev. C | Page 44 of 92
ADAU1761
DSP CORE
SIGNAL PROCESSING
PROGRAM COUNTER
The ADAU1761 is designed to provide all audio signal processing
functions commonly used in stereo or mono low power record
and playback systems. The signal processing flow is designed
using the SigmaStudio software, which allows graphical entry
and real-time control of all signal processing functions.
The execution of instructions in the core is governed by a program
counter, which sequentially steps through the addresses of the
program RAM. The program counter starts every time that a
new audio frame is clocked into the core. SigmaStudio inserts
a jump-to-start command at the end of every program. The
program counter increments sequentially until it reaches this
command and then jumps to the program start address and
waits for the next audio frame to clock into the core.
Many of the signal processing functions are coded using full,
56-bit, double-precision arithmetic data. The input and output
word lengths of the DSP core are 24 bits. Four extra headroom
bits are used in the processor to allow internal gains of up to
24 dB without clipping. Additional gains can be achieved by
initially scaling down the input signal in the DSP signal flow.
FEATURES
The SigmaDSP core was designed specifically for audio processing
and therefore includes several features intended for maximizing
efficiency. These include hardware decibel conversion and audio-
specific ROM constants.
ARCHITECTURE
The DSP core consists of a simple 28-/56-bit multiply-accumulate
(MAC) unit with two sources: a data source and a coefficient
source. The data source can come from the data RAM, a ROM
table of commonly used constant values, or the audio inputs to
the core. The coefficient source can come from the parameter
RAM or from a ROM table of commonly used constant values.
STARTUP
Before the DSPRUN bit is set or any settings are written to the
parameter RAM, the DSP core must be enabled by setting the
DSPEN bit in Register R61 (Address 0x40F5).
The following steps should be performed every time that a new
program is loaded to the SigmaDSP core, or any time that the
DSPRUN bit is disabled and reenabled.
The two sources are multiplied in a 28-bit fixed-point multiplier
and then the signal is input to the 56-bit adder; the result is usually
stored in one of three 56-bit accumulator registers. The accumu-
lators can be output from the core (in 28-bit format) or can
optionally be written back into the data or parameter RAMs.
1. Set the DSPSR[3:0] bits in Register R57 (Address 0x40EB)
to 1111 (none).
2. Set the DSPRUN bit in Register R62 (Address 0x40F6) to 0.
3. Download the rest of the registers, the program RAM, and
the parameter RAM.
4. Set the DSPRUN bit in Register R62 to 1.
5. Set the DSPSR[3:0] bits in Register R57 to the operational
setting (default value is 0001).
DATA SOURCE
(DATA RAM,
ROM CONSTANTS,
AUDIO INPUTS)
COEFFICIENT SOURCE
(PARAMETER RAM,
ROM CONSTANTS)
28
28
28
Changing any register setting or RAM can cause pops and
clicks on the analog outputs. To avoid these pops and clicks,
mute the appropriate outputs using Register R29 to Register R32
(Address 0x4023 to Address 0x4026). Unmute the analog out-
puts after the startup procedure is completed.
56
TRUNCATOR
56
56
DATA OPERATIONS
(ACCUMULATORS (3), dB CONVERSION,
BIT OPERATORS, BIT SHIFTER, ...)
56
TRUNCATOR
28
OUTPUTS
Figure 67. Simplified DSP Core Architecture
Rev. C | Page 45 of 92
ADAU1761
The serial port accepts up to 24 bits on the input and is sign-
extended to the full 28 bits of the DSP core. This allows internal
gains of up to 24 dB without internal clipping.
NUMERIC FORMATS
DSP systems commonly use a standard numeric format.
Fractional numeric systems are specified by an A.B format,
where A is the number of bits to the left of the decimal point
and B is the number of bits to the right of the decimal point.
A digital clipper circuit is used between the output of the DSP
core and the DACs or serial port outputs (see Figure 68). This
circuit clips the top four bits of the signal to produce a 24-bit
output with a range of 1.0 (minus 1 LSB) to −1.0. Figure 68
shows the maximum signal levels at each point in the data flow
in both binary and decibel levels.
The ADAU1761 uses numeric format 5.23 for both the
parameter and data values.
Numeric Format 5.23
Linear range: −16.0 to (+16.0 − 1 LSB)
4-BIT SIGN EXTENSION
Examples:
SIGNAL
DIGITAL
CLIPPER
SERIAL
PORT
PROCESSING
(5.23 FORMAT)
DATA IN
1000 0000 0000 0000 0000 0000 0000 = −16.0
1110 0000 0000 0000 0000 0000 0000 = −4.0
1111 1000 0000 0000 0000 0000 0000 = −1.0
1111 1110 0000 0000 0000 0000 0000 = −0.25
1111 1111 0011 0011 0011 0011 0011 = −0.1
1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0)
0000 0000 0000 0000 0000 0000 0000 = 0
0000 0000 1100 1100 1100 1100 1101 = 0.1
0000 0010 0000 0000 0000 0000 0000 = 0.25
0000 1000 0000 0000 0000 0000 0000 = 1.0
0010 0000 0000 0000 0000 0000 0000 = 4.0
0111 1111 1111 1111 1111 1111 1111 = (16.0 − 1 LSB)
1.23
(0dB)
1.23
(0dB)
1.23
(0dB)
5.23
(24dB)
5.23
(24dB)
Figure 68. Numeric Precision and Clipping Structure
PROGRAMMING
On power-up, the ADAU1761 must be configured with a clock-
ing scheme and then loaded with register settings. After the codec
signal path is set up, the DSP core can be programmed. There
are 1024 instruction cycles per audio sample, resulting in an
internal clock rate of 49.152 MHz when fS = 48 kHz.
The part can be programmed easily using SigmaStudio, a graphical
tool provided by Analog Devices (see Figure 69). No knowledge
of writing line-level DSP code is required. More information
about SigmaStudio can be found at www.analog.com.
Figure 69. SigmaStudio Screen Shot
Rev. C | Page 46 of 92
ADAU1761
PROGRAM RAM, PARAMETER RAM, AND DATA RAM
Table 26. RAM Map and Read/Write Modes
Memory
Size
Address Range
Read
Yes
Yes
Write
Yes
Yes
Write Modes
Direct, safeload
Direct
Parameter RAM
Program RAM
1024 × 32
1024 × 40
0 to 1023 (0x0000 to 0x03FF)
2048 to 3071 (0x0800 to 0x0BFF)
Table 26 shows the RAM map (the ADAU1761 register map is
provided in the Control Registers section). The address space
encompasses a set of registers and three RAMs: program,
parameter, and data. The program RAM and parameter RAM
are not initialized on power-up and are in an unknown state
until written to.
When implementing blocks, such as delays, that require large
amounts of data RAM space, data RAM utilization should be
taken into account. The SigmaDSP core processes delay times
in one-sample increments; therefore, the total pool of delay
available to the user equals 4096 multiplied by the sample
period. For a fS,DSP of 48 kHz, the pool of available delay is a
maximum of about 86 ms, where fS,DSP is the DSP core sampling
rate. In practice, this much data memory is not available to the
user because every block in a design uses a few data memory
locations for its processing. In most DSP programs, this does
not significantly affect the total delay time. The SigmaStudio
compiler manages the data RAM and indicates whether the
number of addresses needed in the design exceeds the maxi-
mum number available.
PROGRAM RAM
The program RAM contains the 40-bit operation codes that
are executed by the core. The SigmaStudio compiler calculates
maximum instructions per frame for a project and generates an
error when the value exceeds the maximum allowable instructions
per frame based on the sample rate of the signals in the core.
Because the end of a program contains a jump-to-start command,
the unused program RAM space does not need to be filled with
no-operation (NOP) commands.
READ/WRITE DATA FORMATS
The read/write formats of the control port are designed to be
byte oriented to allow for easy programming of common micro-
controller chips. To fit into a byte-oriented format, 0s are added
to the data fields before the MSB to extend the data-word to
eight bits. For example, 28-bit words written to the parameter
RAM are preceded by four leading 0s to equal 32 bits (four bytes);
40-bit words written to the program RAM are not preceded by
0s because they are already a full five bytes. These zero-padded
data fields are appended to a 3-byte field consisting of a 7-bit
chip address, a read/write bit, and a 16-bit RAM/register address.
The control port knows how many data bytes to expect based
on the address given in the first three bytes.
PARAMETER RAM
The parameter RAM is 32 bits wide and occupies Address 0
to Address 1023. Each parameter is padded with four 0s before
the MSB to extend the 28-bit word to a full 4-byte width. The
data format of the parameter RAM is twos complement, 5.23.
This means that the coefficients can range from +16.0 (minus
1 LSB) to −16.0, with 1.0 represented by the binary word
0000 1000 0000 0000 0000 0000 0000 or by the hexadecimal
word 0x00 0x80 0x00 0x00.
The parameter RAM can be written to directly or with a safe-
load write. The direct write mode of operation is typically used
during a complete new loading of the RAM using burst mode
addressing to avoid any clicks or pops in the outputs. Note that
this mode can be used during live program execution, but because
there is no handshaking between the core and the control port,
the parameter RAM is unavailable to the DSP core during control
writes, resulting in pops and clicks in the audio stream.
The total number of bytes for a single-location write command
can vary from one byte (for a control register write) to five bytes
(for a program RAM write). Burst mode can be used to fill
contiguous register or RAM locations. A burst mode write begins
by writing the address and data of the first RAM or register location
to be written. Rather than ending the control port transaction
(by issuing a stop command in I2C mode or by bringing the
SigmaStudio automatically assigns the first eight positions to
safeload parameters; therefore, project-specific parameters start
at Address 0x0008.
CLATCH
signal high in SPI mode after the data-word), as
would be done in a single-address write, the next data-word
can be written immediately without specifying its address. The
ADAU1761 control port autoincrements the address of each write
even across the boundaries of the different RAMs and registers.
Table 28 and Table 30 show examples of burst mode writes.
The parameter RAM should not be written to until the DSPEN
bit has been set in Register R61 (Address 0x40F5).
DATA RAM
The ADAU1761 data RAM is used to store audio data-words for
processing, as well as certain run-time parameters. SigmaStudio
provides the data and address information for writing to and
reading from the data RAM.
Rev. C | Page 47 of 92
ADAU1761
Table 27. Parameter RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
Byte 3
Bytes[4:6]
chip_adr[6:0], R/W
param_adr[15:8]
param_adr[7:0]
0000, param[27:24]
param[23:0]
Table 28. Parameter RAM Block Read/Write Format (Burst Mode)
Byte 0
Byte 1
Byte 2
Byte 3
Bytes[4:6]
Bytes[7:10]
param_adr + 1
Bytes[11:14]
chip_adr[6:0], R/W param_adr[15:8]
param_adr[7:0]
0000, param[27:24]
param[23:0]
<—param_adr—>
param_adr + 2
Table 29. Program RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
Bytes[3:7]
chip_adr[6:0], R/W
prog_adr[15:8]
prog_adr[7:0]
prog[39:0]
Table 30. Program RAM Block Read/Write Format (Burst Mode)
Byte 0
Byte 1
Byte 2
Bytes[3:7]
Bytes[8:12]
prog_adr + 1
Bytes[13:17]
prog_adr + 2
chip_adr[6:0], R/W prog_adr[15:8]
prog_adr[7:0]
prog[39:0]
<—prog_adr—>
Parameter RAM Address 0x0001 to Address 0x0005 are the five
data slots for storing the data to be safeloaded. The safeload
parameter space contains five data slots by default because most
standard signal processing algorithms have five parameters or less.
SOFTWARE SAFELOAD
To update parameters in real time while avoiding pop and click
noises on the output, the ADAU1761 uses a software safeload
mechanism. The software safeload mechanism enables the
SigmaDSP core to load new parameters into RAM while guar-
anteeing that the parameters are not in use. This prevents an
undesirable condition where an instruction could execute with
a mix of old and new parameters.
Address 0x0006 is the target address in parameter RAM (with
an offset of −1). This designates the first address to be written.
If more than one word is written, the address increments auto-
matically for each data-word. Up to five sequential parameter
RAM locations can be updated with safeload during each audio
frame. The target address offset of −1 is used because the write
address is calculated relative to the address of the data, which
starts at Address 0x0001. Therefore, to update a parameter at
Address 0x000A, the target address is 0x0009.
SigmaStudio sets up the necessary code and parameters auto-
matically for new projects. The safeload code, along with other
initialization code, fills the first 39 locations in program RAM.
The first eight parameter RAM locations (Address 0x0000 to
Address 0x0007) are configured by default in SigmaStudio as
described in Table 31.
Address 0x0007 designates the number of words to be written
into the parameter RAM during the safeload. A biquad filter
uses all five safeload data addresses. A simple mono gain cell
uses only one safeload data address. Writing to Address 0x0007
also triggers the safeload write to occur in the next audio frame.
Table 31. Software Safeload Parameter RAM Defaults
Address (Hex)
Function
0x0000
Modulo RAM size
0x0001
Safeload Data 1
The safeload mechanism is software based and executes once
per audio frame. Therefore, system designers must take care
when designing the communication protocol. A delay equal to
or greater than the sampling period (the inverse of sampling
frequency) is required between each safeload write. A sample
rate of 48 kHz equates to a delay of at least 21 μs. If this delay
is not observed, the downloaded data is corrupted.
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
Safeload Data 2
Safeload Data 3
Safeload Data 4
Safeload Data 5
Safeload target address (offset of −1)
Number of words to write/safeload trigger
Address 0x0000, which controls the modulo RAM size, is set
by SigmaStudio and is based on the dynamic address generator
mode of the project.
Rev. C | Page 48 of 92
ADAU1761
SOFTWARE SLEW
Because algorithms that use software slew generally require more
RAM than their nonslew equivalents, they should be used only
in situations where a parameter will change during operation of
the device.
When the values of signal processing parameters are changed
abruptly in real time, they sometimes cause pop and click
sounds to appear on the audio outputs. To avoid pops and
clicks, some algorithms in SigmaStudio implement a software
slew functionality. Algorithms using software slew set a target
value for a parameter and continuously update the value of that
parameter until it reaches the target.
Figure 70 shows an example of volume slew applied to a sine wave.
SLEW
CURVE
NEW TARGET
VALUE
INITIAL
VALUE
The target value takes an additional space in parameter RAM,
and the current value of the parameter is updated in the non-
modulo section of data RAM. Assignment of parameters and
nonmodulo data RAM is handled by the SigmaStudio compiler
and does not need to be programmed manually.
Figure 70. Example of Volume Slew
Slew parameters can follow several different curves, including
an RC-type curve and a linear curve. These curve types are
coded into each algorithm and cannot be modified by the user.
Rev. C | Page 49 of 92
ADAU1761
GENERAL-PURPOSE INPUT/OUTPUT
The serial data input/output pins (Pin 26 to Pin 29) are shared
with the general-purpose input/output function. Each of these
four pins can be set to only one of these functions. The function
of these pins is set in the serial data/GPIO pin configuration
register (Register R60, Address 0x40F4).
If many LEDs are required, use an external driver. When the
GPIO pins are configured as open-collector outputs, they
should be pulled up to a maximum voltage equal to the voltage
set on IOVDD.
The configuration of the GPIO functions is set up in the
GPIO pin control registers (Register R48 to Register R51,
Address 0x40C6 to Address 0x40C9).
The GPIOx pins can be used as inputs or outputs. These pins
are readable and can be set through the control port or directly
by the SigmaDSP core. When configured as inputs, the GPIOx
pins can be used with push-button switches or rotary encoders
to control DSP program settings. These pins can also be used
with digital outputs to drive LEDs or external logic to indicate
the status of internal signals and control other devices. Examples
of this use include indicating signal overload, signal present,
and button press confirmation.
GPIO PINS SET FROM THE CONTROL PORT
The GPIO pins can also be configured to be directly controlled
from the I2C/SPI control port. When the pins are set to this
mode, four memory locations are enabled for the GPIO pin
settings. The physical settings on the GPIO pins mirror the
settings of the LSB of these 4-byte-wide memory locations.
When configured as an output, each GPIO pin can typically
drive 2 mA, which is enough current to directly drive some
high efficiency LEDs. Standard LEDs require about 20 mA of
current and can be driven from a GPIO output with an external
transistor or buffer. Because of problems that can arise from
simultaneously driving or sinking a large amount of current on
many pins, avoid connecting high efficiency LEDs directly to
many or all of the GPIO pins when designing the application.
Table 32. GPIOx Pin Memory Settings (Set from Control Port)
Memory Location
Decimal
1568
1569
1570
1571
Hex
Bits[31:1]
Reserved
Reserved
Reserved
Reserved
Bit 0
0x0620
0x0621
0x0622
0x0623
GPIO0SET
GPIO1SET
GPIO2SET
GPIO3SET
Rev. C | Page 50 of 92
ADAU1761
CONTROL REGISTERS
Table 33. Register Map
Reg Address Name
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
R0
R1
0x4000
0x4002
Clock control
PLL control
CLKSRC
INFREQ[1:0]
COREN
00000000
00000000
11111101
00000000
00001100
00010000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00010000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000010
00000010
00000010
00000010
M[15:8]
M[7:0]
N[15:8]
N[7:0]
Reserved
R[3:0]
X[1:0]
Lock
Type
Reserved
PLLEN
JDPOL
Reserved
MX1EN
R2
0x4008
0x4009
0x400A
0x400B
0x400C
0x400D
0x400E
0x400F
0x4010
0x4011
0x4012
0x4013
0x4014
0x4015
0x4016
0x4017
0x4018
0x4019
0x401A
0x401B
0x401C
0x401D
0x401E
0x401F
0x4020
0x4021
0x4022
0x4023
0x4024
0x4025
0x4026
0x4027
0x4028
0x4029
0x402A
0x402B
0x402C
0x402D
0x402F
0x4030
0x4031
0x4036
0x40C0
0x40C1
0x40C2
0x40C3
Dig mic/jack detect
Rec power mgmt
Rec Mixer Left 0
Rec Mixer Left 1
Rec Mixer Right 0
Rec Mixer Right 1
Left diff input vol
Right diff input vol
Record mic bias
ALC 0
JDDB[1:0]
JDFUNC[1:0]
Reserved
RBIAS[1:0]
R3
Reserved
Reserved
MXBIAS[1:0]
LINPG[2:0]
ADCBIAS[1:0]
LDBOOST[1:0]
RDBOOST[1:0]
R4
LINNG[2:0]
R5
Reserved
MX1AUXG[2:0]
R6
Reserved
RINPG[2:0]
RINNG[2:0]
MX2EN
R7
Reserved
MX2AUXG[2:0]
LDMUTE
R8
LDVOL[5:0]
RDVOL[5:0]
LDEN
RDEN
MBIEN
R9
RDMUTE
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R67
R43
R44
R45
R46
Reserved
MPERF
MBI
Reserved
PGASLEW[1:0]
ALCMAX[2:0]
ALCSEL[2:0]
ALC 1
ALCHOLD[3:0]
ALCATCK[3:0]
NGTYP[1:0] NGEN
ALCTARG[3:0]
ALCDEC[3:0]
NGTHR[4:0]
ALC 2
ALC 3
Serial Port 0
Reserved
Reserved
Reserved
SPSRS
LRMOD
BPOL
LRPOL
CHPF[1:0]
MS
Serial Port 1
BPF[2:0]
ADTDM
DAOSR
DATDM
ADOSR
MSBP
INSEL
LRDEL[1:0]
CONVSR[2:0]
Converter 0
DAPAIR[1:0]
Converter 1
Reserved
ADPAIR[1:0]
ADCEN[1:0]
ADC control
ADCPOL
MX3RM
HPF
DMPOL
DMSW
Left digital vol
Right digital vol
Play Mixer Left 0
Play Mixer Left 1
Play Mixer Right 0
Play Mixer Right 1
Play L/R mixer left
Play L/R mixer right
Play L/R mixer mono
Play HP left vol
Play HP right vol
Line output left vol
Line output right vol
Play mono output
Pop/click suppress
Play power mgmt
DAC Control 0
DAC Control 1
DAC Control 2
Serial port pad
Control Port Pad 0
Control Port Pad 1
Jack detect pin
Dejitter control
LADVOL[7:0]
RADVOL[7:0]
Reserved
Reserved
MX3LM
MX4LM
MX3AUXG[3:0]
MX3EN
MX3G2[3:0]
MX3G1[3:0]
MX4RM
MX4AUXG[3:0]
MX4EN
MX4G2[3:0]
MX4G1[3:0]
MX5G3[1:0]
MX6G3[1:0]
MX7[1:0]
LHPM
Reserved
Reserved
MX5G4[1:0]
MX6G4[1:0]
MX5EN
MX6EN
MX7EN
HPEN
Reserved
LHPVOL[5:0]
RHPVOL[5:0]
LOUTVOL[5:0]
ROUTVOL[5:0]
MONOVOL[5:0]
RHPM
HPMODE
LOMODE
ROMODE
LOUTM
ROUTM
MONOM
ASLEW[1:0]
PREN
MOMODE 00000010
Reserved
POPMODE POPLESS
DACBIAS[1:0] PBIAS[1:0]
DACPOL DEMPH
Reserved
PLEN
00000000
00000000
00000000
00000000
00000000
10101010
10101010
00000000
00001000
00000011
00000000
00000000
00000000
00000000
HPBIAS[1:0]
DACMONO[1:0]
Reserved
DACEN[1:0]
LDAVOL[7:0]
RDAVOL[7:0]
ADCSDP[1:0]
CDATP[1:0]
DACSDP[1:0]
CLCHP[1:0]
Reserved
Reserved
DEJIT[7:0]
LRCLKP[1:0]
BCLKP[1:0]
SDAP[1:0]
SCLP[1:0]
SDASTR
Reserved
Reserved
JDSTR
JDP[1:0]
Cyclic redundancy
check
CRC[31:24]
CRC[23:16]
CRC[15:8]
CRC[7:0]
Rev. C | Page 51 of 92
ADAU1761
Reg Address Name
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
0x40C4
0x40C6
0x40C7
0x40C8
0x40C9
0x40D0
0x40D1
0x40D2
0x40D3
0x40D4
0x40EB
CRC enable
Reserved
CRCEN
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
GPIO0 pin control
GPIO1 pin control
GPIO2 pin control
GPIO3 pin control
Watchdog enable
Watchdog value
GPIO0[3:0]
GPIO1[3:0]
GPIO2[3:0]
GPIO3[3:0]
Reserved
Reserved
Reserved
Reserved
DOGEN
DOGER
DOG[23:16]
DOG[15:8]
DOG[7:0]
Watchdog error
Reserved
DSP sampling rate
setting
Reserved
Reserved
Reserved
Reserved
DSPSR[3:0]
SINRT[3:0]
R58
R59
R60
0x40F2
0x40F3
0x40F4
Serial input route
control
00000000
00000000
00000000
Serial output route
control
SOUTRT[3:0]
Serial data/GPIO
pin configuration
LRGP3
BGP2
SDOGP1
SDIGP0
R61
R62
R63
R64
0x40F5
0x40F6
0x40F7
0x40F8
DSP enable
DSP run
Reserved
Reserved
MOSLW
DSPEN
00000000
00000000
00000000
00000000
DSPRUN
LHPSLW
DSP slew modes
Reserved
SLEWPD
ROSLW
LOSLW
INTPD
RHPSLW
SPSR[2:0]
Serial port
sampling rate
Reserved
ALCPD
R65
R66
0x40F9
0x40FA
Clock Enable 0
Clock Enable 1
Reserved
DECPD
SOUTPD
SINPD
CLK1
SPPD
CLK0
00000000
00000000
Reserved
CONTROL REGISTER DETAILS
All registers except for the PLL control register are 1-byte write and read registers.
R0: Clock Control, 16,384 (0x4000)
Bit 7
Bit 6
Bit 5
Reserved
Table 34. Clock Control Register
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
COREN
CLKSRC
INFREQ[1:0]
Bits
Bit Name
Description
3
CLKSRC
Clock source select.
0 = direct from MCLK pin (default).
1 = PLL clock.
[2:1]
INFREQ[1:0]
Input clock frequency. Sets the core clock rate that generates the core clock. If the PLL is used, this value is
automatically set to 1024 × fS.
Setting
00
01
Input Clock Frequency
256 × fS (default)
512 × fS
10
768 × fS
11
1024 × fS
0
COREN
Core clock enable. Only the R0 and R1 registers can be accessed when this bit is set to 0 (core clock disabled).
0 = core clock disabled (default).
1 = core clock enabled.
Rev. C | Page 52 of 92
ADAU1761
R1: PLL Control, 16,386 (0x4002)
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
M[15:8]
Bit 2
Bit 1
Bit 0
0
1
2
3
4
5
M[7:0]
N[15:8]
N[7:0]
Reserved
R[3:0]
Reserved
X[1:0]
Lock
Type
PLLEN
Table 35. PLL Control Register
Byte
Bits
[7:0]
[7:0]
Bit Name
M[15:8]
M[7:0]
Description
0
1
PLL denominator MSB. This value is concatenated with M[7:0] to make up a 16-bit number.
PLL denominator LSB. This value is concatenated with M[15:8] to make up a 16-bit number.
M[15:8] (MSB)
00000000
…
M[7:0] (LSB)
00000000
…
Value of M
0
…
00000000
…
11111101
…
253 (default)
…
11111111
11111111
65,535
2
3
[7:0]
[7:0]
N[15:8]
N[7:0]
PLL numerator MSB. This value is concatenated with N[7:0] to make up a 16-bit number.
PLL numerator LSB. This value is concatenated with N[15:8] to make up a 16-bit number.
N[15:8] (MSB)
N[7:0] (LSB)
00000000
…
Value of N
00000000
…
0
…
00000000
…
00001100
…
12 (default)
…
11111111
11111111
65,535
4
[6:3]
R[3:0]
PLL integer setting.
Setting
Value of R
0010
2 (default)
0011
0100
0101
0110
0111
1000
3
4
5
6
7
8
4
[2:1]
X[1:0]
PLL input clock divider.
Setting
00
Value of X
1 (default)
01
10
11
2
3
4
4
5
5
0
1
0
Type
Lock
Type of PLL. When set to integer mode, the values of M and N are ignored.
0 = integer (default).
1 = fractional.
PLL lock. This read-only bit is flagged when the PLL has finished locking.
0 = PLL unlocked (default).
1 = PLL locked.
PLLEN
PLL enable.
0 = PLL disabled (default).
1 = PLL enabled.
Rev. C | Page 53 of 92
ADAU1761
R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008)
Bit 7
Bit 6
JDDB[1:0]
Bit 5
Bit 4
Bit 3
Bit 2
Reserved
Bit 1
Bit 0
JDFUNC[1:0]
JDPOL
Table 36. Digital Microphone/Jack Detection Control Register
Bits
Bit Name
Description
[7:6]
JDDB[1:0]
Jack detect debounce time.
Setting
00
01
Debounce Time
5 ms (default)
10 ms
10
20 ms
11
40 ms
[5:4]
JDFUNC[1:0]
JACKDET/MICIN pin function. Enables or disables the jack detect function or configures the pin for a digital
microphone input.
Setting
00
01
Pin Function
Jack detect off (default)
Jack detect on
10
11
Digital microphone input
Reserved
0
JDPOL
Jack detect polarity. Detects high or low signal.
0 = detect high signal (default).
1 = detect low signal.
R3: Record Power Management, 16,393 (0x4009)
This register manages the power consumption for the record path. In particular, the current distribution for the mixer boosts, ADCs,
record path mixers, and PGAs can be set to one of four modes. These settings are normal operation, power saving mode, enhanced
performance mode, and extreme power saving mode. Each of these modes draws current from a central bias. Enhanced performance
mode offers the highest performance with the trade-off of higher power consumption.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
MXBIAS[1:0]
ADCBIAS[1:0]
RBIAS[1:0]
Reserved
Table 37. Record Power Management Register
Bits
Bit Name
Description
[6:5]
MXBIAS[1:0]
Mixer amplifier bias boost. Sets the boost level for the bias current of the record path mixers. In some cases,
the boost level enhances the THD + N performance.
Setting
00
01
Boost Level
Normal operation (default)
Boost Level 1
10
Boost Level 2
11
Boost Level 3
[4:3]
[2:1]
ADCBIAS[1:0]
RBIAS[1:0]
ADC bias control. Sets the bias current for the ADCs based on the mode of operation selected.
Setting
00
01
10
11
ADC Bias Control
Normal operation (default)
Extreme power saving
Enhanced performance
Power saving
Record path bias control. Sets the bias current for the PGAs and mixers in the record path.
Setting
00
01
Record Path Bias Control
Normal operation (default)
Reserved
10
11
Enhanced performance
Power saving
Rev. C | Page 54 of 92
ADAU1761
R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A)
This register controls the gain of single-ended inputs for the left channel record path. The left channel record mixer is referred to as Mixer 1.
Bit 7
Bit 6
Bit 5
LINPG[2:0]
Bit 4
Bit 3
Bit 2
LINNG[2:0]
Bit 1
Bit 0
Reserved
MX1EN
Table 38. Record Mixer Left (Mixer 1) Control 0 Register
Bits
Bit Name
Description
[6:4]
LINPG[2:0]
Gain for a left channel single-ended input from the LINP pin, input to Mixer 1.
Setting
000
001
010
011
Gain
Mute (default)
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
100
101
110
3 dB
111
6 dB
[3:1]
LINNG[2:0]
Gain for a left channel single-ended input from the LINN pin, input to Mixer 1.
Setting
000
001
010
011
Gain
Mute (default)
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
100
101
110
3 dB
111
6 dB
0
MX1EN
Left channel mixer enable in the record path. Referred to as Mixer 1.
0 = mixer disabled (default).
1 = mixer enabled.
Rev. C | Page 55 of 92
ADAU1761
R5: Record Mixer Left (Mixer 1) Control 1, 16,395 (0x400B)
This register controls the gain boost of the left channel differential PGA input and the gain for the left channel auxiliary input in the
record path. The left channel record mixer is referred to as Mixer 1.
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LDBOOST[1:0]
MX1AUXG[2:0]
Table 39. Record Mixer Left (Mixer 1) Control 1 Register
Bits
Bit Name
Description
[4:3]
LDBOOST[1:0]
Left channel differential PGA input gain boost, input to Mixer 1. The left differential input uses the LINP (positive
signal) and LINN (negative signal) pins.
Setting
00
01
Gain Boost
Mute (default)
0 dB
10
20 dB
11
Reserved
[2:0]
MX1AUXG[2:0] Left single-ended auxiliary input gain from the LAUX pin in the record path, input to Mixer 1.
Setting
000
001
Auxiliary Input Gain
Mute (default)
−12 dB
−9 dB
010
011
−6 dB
100
−3 dB
101
0 dB
110
3 dB
111
6 dB
Rev. C | Page 56 of 92
ADAU1761
R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C)
This register controls the gain of single-ended inputs for the right channel record path. The right channel record mixer is referred to as
Mixer 2.
Bit 7
Bit 6
Bit 5
RINPG[2:0]
Bit 4
Bit 3
Bit 2
RINNG[2:0]
Bit 1
Bit 0
Reserved
MX2EN
Table 40. Record Mixer Right (Mixer 2) Control 0 Register
Bits
Bit Name
Description
[6:4]
RINPG[2:0]
Gain for a right channel single-ended input from the RINP pin, input to Mixer 2.
Setting
000
001
010
011
Gain
Mute (default)
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
100
101
110
3 dB
111
6 dB
[3:1]
RINNG[2:0]
Gain for a right channel single-ended input from the RINN pin, input to Mixer 2.
Setting
000
001
010
011
Gain
Mute (default)
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
100
101
110
3 dB
111
6 dB
0
MX2EN
Right channel mixer enable in the record path. Referred to as Mixer 2.
0 = mixer disabled (default).
1 = mixer enabled.
Rev. C | Page 57 of 92
ADAU1761
R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D)
This register controls the gain boost of the right channel differential PGA input and the gain for the right channel auxiliary input in the
record path. The right channel record mixer is referred to as Mixer 2.
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDBOOST[1:0]
MX2AUXG[2:0]
Table 41. Record Mixer Right (Mixer 2) Control 1 Register
Bits
Bit Name
Description
[4:3]
RDBOOST[1:0]
Right channel differential PGA input gain boost, input to Mixer 2. The right differential input uses the RINP
(positive signal) and RINN (negative signal) pins.
Setting
00
01
Gain Boost
Mute (default)
0 dB
10
20 dB
11
Reserved
[2:0]
MX2AUXG[2:0] Right single-ended auxiliary input gain from the RAUX pin in the record path, input to Mixer 2.
Setting
000
001
Auxiliary Input Gain
Mute (default)
−12 dB
−9 dB
010
011
−6 dB
100
−3 dB
101
0 dB
110
3 dB
111
6 dB
R8: Left Differential Input Volume Control, 16,398 (0x400E)
This register enables the differential path and sets the volume control for the left differential PGA input.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LDMUTE
LDEN
LDVOL[5:0]
Table 42. Left Differential Input Volume Control Register
Bits
Bit Name
Description
[7:2]
LDVOL[5:0]
Left channel differential PGA input volume control. The left differential input uses the LINP (positive signal) and
LINN (negative signal) pins. Each step corresponds to a 0.75 dB increase in gain. See Table 92 for a complete list
of the volume settings.
Setting
000000
000001
…
Volume
−12 dB (default)
−11.25 dB
…
010000
…
0 dB
…
111110
111111
34.5 dB
35.25 dB
1
0
LDMUTE
LDEN
Left differential input mute control.
0 = mute (default).
1 = unmute.
Left differential PGA enable. When enabled, the LINP and LINN pins are used as a full differential pair. When
disabled, these two pins are configured as two single-ended inputs with the signals routed around the PGA.
0 = disabled (default).
1 = enabled.
Rev. C | Page 58 of 92
ADAU1761
R9: Right Differential Input Volume Control, 16,399 (0x400F)
This register enables the differential path and sets the volume control for the right differential PGA input.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDMUTE
RDEN
RDVOL[5:0]
Table 43. Right Differential Input Volume Control Register
Bits
Bit Name
Description
[7:2]
RDVOL[5:0]
Right channel differential PGA input volume control. The right differential input uses the RINP (positive signal)
and RINN (negative signal) pins. Each step corresponds to a 0.75 dB increase in gain. See Table 92 for a complete
list of the volume settings.
Setting
000000
000001
…
Volume
−12 dB (default)
−11.25 dB
…
010000
…
0 dB
…
111110
111111
34.5 dB
35.25 dB
1
0
RDMUTE
RDEN
Right differential input mute control.
0 = mute (default).
1 = unmute.
Right differential PGA enable. When enabled, the RINP and RINN pins are used as a full differential pair. When
disabled, these two pins are configured as two single-ended inputs with the signals routed around the PGA.
0 = disabled (default).
1 = enabled.
R10: Record Microphone Bias Control, 16,400 (0x4010)
This register controls the MICBIAS pin settings for biasing electret type analog microphones.
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MPERF
MBI
Reserved
MBIEN
Table 44. Record Microphone Bias Control Register
Bits
Bit Name
Description
3
MPERF
Microphone bias is enabled for high performance or normal operation. High performance operation sources
more current to the microphone.
0 = normal operation (default).
1 = high performance.
2
0
MBI
Microphone voltage bias as a fraction of AVDD.
0 = 0.90 × AVDD (default).
1 = 0.65 × AVDD.
MBIEN
Enables the MICBIAS output.
0 = disabled (default).
1 = enabled.
Rev. C | Page 59 of 92
ADAU1761
R11: ALC Control 0, 16,401 (0x4011)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ALCSEL[2:0]
Bit 0
PGASLEW[1:0]
ALCMAX[2:0]
Table 45. ALC Control 0 Register
Bits
Bit Name
Description
[7:6]
PGASLEW[1:0]
PGA volume slew time when the ALC is off. The slew time is the period of time that a volume increase or decrease
takes to ramp up or ramp down to the target volume set in Register R8 (left differential input volume control)
and Register R9 (right differential input volume control).
Setting
00
01
Slew Time
24 ms (default)
48 ms
10
96 ms
11
Off
[5:3]
ALCMAX[2:0]
The maximum ALC gain sets a limit to the amount of gain that the ALC can provide to the input signal. This
protects small signals from excessive amplification.
Setting
000
001
Maximum ALC Gain
−12 dB (default)
−6 dB
010
0 dB
011
6 dB
100
12 dB
101
18 dB
110
24 dB
111
30 dB
[2:0]
ALCSEL[2:0]
ALC select. These bits set the channels that are controlled by the ALC. When set to right only, the ALC responds
only to the right channel input and controls the gain of the right PGA amplifier only. When set to left only, the
ALC responds only to the left channel input and controls the gain of the left PGA amplifier only. When set to
stereo, the ALC responds to the greater of the left or right channel and controls the gain of both the left and
right PGA amplifiers. DSP control allows the PGA gain to be set within the DSP or from external GPIO inputs.
These bits must be off if manual control of the volume is desired.
Setting
000
001
Channels
Off (default)
Right only
Left only
010
011
Stereo
100
101
110
111
DSP control
Reserved
Reserved
Reserved
Rev. C | Page 60 of 92
ADAU1761
R12: ALC Control 1, 16,402 (0x4012)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ALCHOLD[3:0]
ALCTARG[3:0]
Table 46. ALC Control 1 Register
Bits
Bit Name
Description
[7:4]
ALCHOLD[3:0]
ALC hold time. The ALC hold time is the amount of time that the ALC waits after a decrease in input level before
increasing the gain to achieve the target level. The recommended minimum setting is 21 ms (0011) to prevent
distortion of low frequency signals. The hold time doubles with every 1-bit increase.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hold Time
2.67 ms (default)
5.34 ms
10.68 ms
21.36 ms
42.72 ms
85.44 ms
170.88 ms
341.76 ms
683.52 ms
1.367 sec
2.7341 sec
5.4682 sec
10.936 sec
21.873 sec
43.745 sec
87.491 sec
[3:0]
ALCTARG[3:0]
ALC target. The ALC target sets the desired ADC input level. The PGA gain is adjusted by the ALC to reach this
target level. The recommended target level is between −16 dB and −10 dB to accommodate transients without
clipping the ADC.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ALC Target
−28.5 dB (default)
−27 dB
−25.5 dB
−24 dB
−22.5 dB
−21 dB
−19.5 dB
−18 dB
−16.5 dB
−15 dB
−13.5 dB
−12 dB
−10.5 dB
−9 dB
−7.5 dB
−6 dB
Rev. C | Page 61 of 92
ADAU1761
R13: ALC Control 2, 16,403 (0x4013)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ALCATCK[3:0]
ALCDEC[3:0]
Table 47. ALC Control 2 Register
Bits
Bit Name
Description
[7:4]
ALCATCK[3:0]
ALC attack time. The attack time sets how fast the ALC starts attenuating after an increase in input level above
the target. A typical setting for music recording is 384 ms, and a typical setting for voice recording is 24 ms.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Attack Time
6 ms (default)
12 ms
24 ms
48 ms
96 ms
192 ms
384 ms
768 ms
1.54 sec
3.07 sec
6.14 sec
12.29 sec
24.58 sec
49.15 sec
98.30 sec
196.61 sec
[3:0]
ALCDEC[3:0]
ALC decay time. The decay time sets how fast the ALC increases the PGA gain after a decrease in input level
below the target. A typical setting for music recording is 24.58 seconds, and a typical setting for voice recording
is 1.54 seconds.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Decay Time
24 ms
48 ms
96 ms
192 ms
384 ms
768 ms
1.54 sec
3.07 sec
6.14 sec
12.29 sec
24.58 sec
49.15 sec
98.30 sec
196.61 sec
393.22 sec
786.43 sec
Rev. C | Page 62 of 92
ADAU1761
R14: ALC Control 3, 16,404 (0x4014)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
NGTHR[4:0]
Bit 1
Bit 0
NGEN
NGTYP[1:0]
Table 48. ALC Control 3 Register
Bits
Bit Name
Description
[7:6]
NGTYP[1:0]
Noise gate type. When the input signal falls below the threshold for 250 ms, the noise gate can hold a constant
PGA gain, mute the ADC output, fade the PGA gain to the minimum gain value, or fade then mute.
Setting
00
Noise Gate
Hold PGA constant (default)
01
10
11
Mute ADC output (digital mute)
Fade to PGA minimum value (analog fade)
Fade then mute (analog fade/digital mute)
5
NGEN
Noise gate enable.
0 = disabled (default).
1 = enabled.
[4:0]
NGTHR[4:0]
Noise gate threshold. When the input signal falls below the threshold for 250 ms, the noise gate is activated.
A 1 LSB increase corresponds to a −1.5 dB change. See Table 93 for a complete list of the threshold settings.
Setting
00000
00001
…
Threshold
−76.5 dB (default)
−75 dB
…
11110
11111
−31.5 dB
−30 dB
R15: Serial Port Control 0, 16,405 (0x4015)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CHPF[1:0]
Bit 0
Reserved
SPSRS
LRMOD
BPOL
LRPOL
MS
Table 49. Serial Port Control 0 Register
Bits
Bit Name
Description
6
SPSRS
Serial port sampling rate source.
0 = converter rate set in Register R17 (default).
1 = DSP rate set in Register R57.
5
4
LRMOD
BPOL
LRCLK mode sets the LRCLK for either a 50% duty cycle or a pulse. The pulse mode should be at least 1 BCLK wide.
0 = 50% duty cycle (default).
1 = pulse mode.
BCLK polarity sets the BCLK edge that triggers a change in audio data. This can be set for the falling or rising
edge of the BCLK.
0 = falling edge (default).
1 = rising edge.
3
LRPOL
LRCLK polarity sets the LRCLK edge that triggers the beginning of the left channel audio frame. This can be set
for the falling or rising edge of the LRCLK.
0 = falling edge (default).
1 = rising edge.
[2:1]
CHPF[1:0]
Channels per frame sets the number of channels per LRCLK frame.
Setting
00
01
Channels per LRCLK Frame
Stereo (default)
TDM 4
10
TDM 8
11
Reserved
0
MS
Serial data port bus mode. Both LRCLK and BCLK are master of the serial port when set in master mode and are
serial port slave in slave mode.
0 = slave mode (default).
1 = master mode.
Rev. C | Page 63 of 92
ADAU1761
R16: Serial Port Control 1, 16,406 (0x4016)
Bit 7
Bit 6
BPF[2:0]
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADTDM
DATDM
MSBP
LRDEL[1:0]
Table 50. Serial Port Control 1 Register
Bits
Bit Name
Description
[7:5]
BPF[2:0]
Number of bit clock cycles per LRCLK audio frame.
Setting
000
001
Bit Clock Cycles
64 (default)
Reserved
48
010
011
128
100
256
101
110
111
Reserved
Reserved
Reserved
4
ADTDM
DATDM
MSBP
ADC serial audio data channel position in TDM mode.
0 = left first (default).
1 = right first.
3
DAC serial audio data channel position in TDM mode.
0 = left first (default).
1 = right first.
2
MSB position in the LRCLK frame.
0 = MSB first (default).
1 = LSB first.
[1:0]
LRDEL[1:0]
Data delay from LRCLK edge (in BCLK units).
Setting
00
Delay (Bit Clock Cycles)
1 (default)
01
0
10
8
11
16
Rev. C | Page 64 of 92
ADAU1761
R17: Converter Control 0, 16,407 (0x4017)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
DAOSR
ADOSR
DAPAIR[1:0]
CONVSR[2:0]
Table 51. Converter Control 0 Register
Bits
Bit Name
Description
[6:5]
DAPAIR[1:0]
On-chip DAC serial data selection in TDM 4 or TDM 8 mode.
Setting
00
01
Pair
First pair (default)
Second pair
Third pair
10
11
Fourth pair
4
DAOSR
DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
3
ADOSR
ADC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
[2:0]
CONVSR[2:0]
Converter sampling rate. The ADCs and DACs operate at the sampling rate set in this register. The converter rate
selected is a ratio of the base sampling rate, fS. The base sampling rate is determined by the operating frequency
of the core clock.
Setting
000
001
Sampling Rate
Base Sampling Rate (fS = 48 kHz)
fS
fS/6
48 kHz, base (default)
8 kHz
010
fS/4
12 kHz
011
fS/3
16 kHz
100
fS/2
24 kHz
101
110
111
fS/1.5
fS/0.5
Reserved
32 kHz
96 kHz
R18: Converter Control 1, 16,408 (0x4018)
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
ADPAIR[1:0]
Table 52. Converter Control 1 Register
Bits
Bit Name
Description
[1:0]
ADPAIR[1:0]
On-chip ADC serial data selection in TDM 4 or TDM 8 mode.
Setting
00
01
Pair
First pair (default)
Second pair
Third pair
10
11
Fourth pair
Rev. C | Page 65 of 92
ADAU1761
R19: ADC Control, 16,409 (0x4019)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
ADCPOL
HPF
DMPOL
DMSW
INSEL
ADCEN[1:0]
Table 53. ADC Control Register
Bits
Bit Name
Description
6
ADCPOL
Invert input polarity.
0 = normal (default).
1 = inverted.
5
4
3
HPF
ADC high-pass filter select. At 48 kHz, f3dB = 2 Hz.
0 = off (default).
1 = on.
DMPOL
DMSW
Digital microphone data polarity swap.
0 = invert polarity.
1 = normal (default).
Digital microphone channel swap. Normal operation sends the left channel on the rising edge of the clock and
the right channel on the falling edge of the clock.
0 = normal (default).
1 = swap left and right channels.
2
INSEL
Digital microphone input select. When asserted, the on-chip ADCs are off, BCLK is master at 128 × fS, and
ADC_SDATA is expected to have left and right channels interleaved.
0 = digital microphone inputs off, ADCs enabled (default).
1 = digital microphone inputs enabled, ADCs off.
[1:0]
ADCEN[1:0]
ADC enable.
Setting
00
01
ADCs Enabled
Both off (default)
Left on
10
Right on
11
Both on
R20: Left Input Digital Volume, 16,410 (0x401A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LADVOL[7:0]
Table 54. Left Input Digital Volume Register
Bits
Bit Name
Description
[7:0]
LADVOL[7:0]
Controls the digital volume attenuation for left channel inputs from either the left ADC or the left digital
microphone input. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 94 for a
complete list of the volume settings.
Setting
00000000
00000001
00000010
…
Volume Attenuation
0 dB (default)
−0.375 dB
−0.75 dB
…
11111110
11111111
−95.25 dB
−95.625 dB
Rev. C | Page 66 of 92
ADAU1761
R21: Right Input Digital Volume, 16,411 (0x401B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RADVOL[7:0]
Table 55. Right Input Digital Volume Register
Bits
Bit Name
Description
[7:0]
RADVOL[7:0]
Controls the digital volume attenuation for right channel inputs from either the right ADC or the right digital
microphone input. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 94 for a
complete list of the volume settings.
Setting
00000000
00000001
00000010
…
Volume Attenuation
0 dB (default)
−0.375 dB
−0.75 dB
…
11111110
11111111
−95.25 dB
−95.625 dB
R22: Playback Mixer Left (Mixer 3) Control 0, 16,412 (0x401C)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
MX3RM
MX3LM
MX3EN
MX3AUXG[3:0]
Table 56. Playback Mixer Left (Mixer 3) Control 0 Register
Bits
Bit Name
Description
6
MX3RM
Mixer input mute. Mutes the right DAC input to the left channel playback mixer (Mixer 3).
0 = muted (default).
1 = unmuted.
5
MX3LM
Mixer input mute. Mutes the left DAC input to the left channel playback mixer (Mixer 3).
0 = muted (default).
1 = unmuted.
[4:1]
MX3AUXG[3:0] Mixer input gain. Controls the left channel auxiliary input gain to the left channel playback mixer (Mixer 3).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
Gain
Mute (default)
−15 dB
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
3 dB
6 dB
0
MX3EN
Mixer 3 enable.
0 = disabled (default).
1 = enabled.
Rev. C | Page 67 of 92
ADAU1761
R23: Playback Mixer Left (Mixer 3) Control 1, 16,413 (0x401D)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MX3G2[3:0]
MX3G1[3:0]
Table 57. Playback Mixer Left (Mixer 3) Control 1 Register
Bits
Bit Name
Description
[7:4]
MX3G2[3:0]
Bypass gain control. The signal from the right channel record mixer (Mixer 2) bypasses the converters and gain
can be applied before the left playback mixer (Mixer 3).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
Gain
Mute (default)
−15 dB
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
3 dB
6 dB
[3:0]
MX3G1[3:0]
Bypass gain control. The signal from the left channel record mixer (Mixer 1) bypasses the converters and gain
can be applied before the left playback mixer (Mixer 3).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
Gain
Mute (default)
−15 dB
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
3 dB
6 dB
Rev. C | Page 68 of 92
ADAU1761
R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
MX4RM
MX4LM
MX4EN
MX4AUXG[3:0]
Table 58. Playback Mixer Right (Mixer 4) Control 0 Register
Bits
Bit Name
Description
6
MX4RM
Mixer input mute. Mutes the right DAC input to the right channel playback mixer (Mixer 4).
0 = muted (default).
1 = unmuted.
5
MX4LM
Mixer input mute. Mutes the left DAC input to the right channel playback mixer (Mixer 4).
0 = muted (default).
1 = unmuted.
[4:1]
MX4AUXG[3:0] Mixer input gain. Controls the right channel auxiliary input gain to the right channel playback mixer (Mixer 4).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
Gain
Mute (default)
−15 dB
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
3 dB
6 dB
0
MX4EN
Mixer 4 enable.
0 = disabled (default).
1 = enabled.
Rev. C | Page 69 of 92
ADAU1761
R25: Playback Mixer Right (Mixer 4) Control 1, 16,415 (0x401F)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MX4G2[3:0]
MX4G1[3:0]
Table 59. Playback Mixer Right (Mixer 4) Control 1 Register
Bits
Bit Name
Description
[7:4]
MX4G2[3:0]
Bypass gain control. The signal from the right channel record mixer (Mixer 2) bypasses the converters and gain
can be applied before the right playback mixer (Mixer 4).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
Gain
Mute (default)
−15 dB
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
3 dB
6 dB
[3:0]
MX4G1[3:0]
Bypass gain control. The signal from the left channel record mixer (Mixer 1) bypasses the converters and gain
can be applied before the right playback mixer (Mixer 4).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
Gain
Mute (default)
−15 dB
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
3 dB
6 dB
Rev. C | Page 70 of 92
ADAU1761
R26: Playback L/R Mixer Left (Mixer 5) Line Output Control, 16,416 (0x4020)
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MX5EN
MX5G4[1:0]
MX5G3[1:0]
Table 60. Playback L/R Mixer Left (Mixer 5) Line Output Control Register
Bits
Bit Name
Description
[4:3]
MX5G4[1:0]
Mixer input gain boost. The signal from the right channel playback mixer (Mixer 4) can be enabled and boosted
in the playback L/R mixer left (Mixer 5).
Setting
00
Gain Boost
Mute (default)
01
10
11
0 dB output (−6 dB gain on each of the two inputs)
6 dB output (0 dB gain on each of the two inputs)
Reserved
[2:1]
MX5G3[1:0]
Mixer input gain boost. The signal from the left channel playback mixer (Mixer 3) can be enabled and boosted in
the playback L/R mixer left (Mixer 5).
Setting
00
Gain Boost
Mute (default)
01
10
11
0 dB output (−6 dB gain on each of the two inputs)
6 dB output (0 dB gain on each of the two inputs)
Reserved
0
MX5EN
Mixer 5 enable.
0 = disabled (default).
1 = enabled.
R27: Playback L/R Mixer Right (Mixer 6) Line Output Control, 16,417 (0x4021)
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MX6EN
MX6G4[1:0]
MX6G3[1:0]
Table 61. Playback L/R Mixer Right (Mixer 6) Line Output Control Register
Bits
Bit Name
Description
[4:3]
MX6G4[1:0]
Mixer input gain boost. The signal from the right channel playback mixer (Mixer 4) can be enabled and boosted
in the playback L/R mixer right (Mixer 6).
Setting
00
Gain Boost
Mute (default)
01
10
11
0 dB output (−6 dB gain on each of the two inputs)
6 dB output (0 dB gain on each of the two inputs)
Reserved
[2:1]
MX6G3[1:0]
Mixer input gain boost. The signal from the left channel playback mixer (Mixer 3) can be enabled and boosted in
the playback L/R mixer right (Mixer 6).
Setting
00
Gain Boost
Mute (default)
01
10
11
0 dB output (−6 dB gain on each of the two inputs)
6 dB output (0 dB gain on each of the two inputs)
Reserved
0
MX6EN
Mixer 6 enable.
0 = disabled (default).
1 = enabled.
Rev. C | Page 71 of 92
ADAU1761
R28: Playback L/R Mixer Mono Output (Mixer 7) Control, 16,418 (0x4022)
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
MX7[1:0]
Bit 0
MX7EN
Table 62. Playback L/R Mixer Mono Output (Mixer 7) Control Register
Bits
Bit Name
Description
[2:1]
MX7[1:0]
L/R mono playback mixer (Mixer 7). Mixes the left and right playback mixers (Mixer 3 and Mixer 4) with either a
0 dB or 6 dB gain boost. Additionally, this mixer can operate as a common-mode output, which is used as the
virtual ground in a capless headphone configuration.
Setting
00
01
10
11
Gain Boost
Common-mode output (default)
0 dB output (−6 dB gain on each of the two inputs)
6 dB output (0 dB gain on each of the two inputs)
Reserved
0
MX7EN
Mixer 7 enable.
0 = disabled (default).
1 = enabled.
R29: Playback Headphone Left Volume Control, 16,419 (0x4023)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LHPVOL[5:0]
LHPM
HPEN
Table 63. Playback Headphone Left Volume Control Register
Bits
Bit Name
Description
[7:2]
LHPVOL[5:0]
Headphone volume control for left channel, LHP output. Each 1-bit step corresponds to a 1 dB increase in volume.
See Table 95 for a complete list of the volume settings.
Setting
000000
…
Volume
−57 dB (default)
…
111001
…
0 dB
…
111111
6 dB
1
0
LHPM
HPEN
Headphone mute for left channel, LHP output (active low).
0 = mute.
1 = unmute (default).
Headphone volume control enable. Logical OR with the HPMODE bit in Register R30. If either the HPEN bit or
the HPMODE bit is set to 1, the headphone output is enabled.
0 = disabled (default).
1 = enabled.
Rev. C | Page 72 of 92
ADAU1761
R30: Playback Headphone Right Volume Control, 16,420 (0x4024)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HPMODE
RHPVOL[5:0]
RHPM
Table 64. Playback Headphone Right Volume Control Register
Bits
Bit Name
Description
[7:2]
RHPVOL[5:0]
Headphone volume control for right channel, RHP output. Each 1-bit step corresponds to a 1 dB increase in
volume. See Table 95 for a complete list of the volume settings.
Setting
000000
…
Volume
−57 dB (default)
…
111001
…
0 dB
…
111111
6 dB
1
0
RHPM
Headphone mute for right channel, RHP output (active low).
0 = mute.
1 = unmute (default).
HPMODE
RHP and LHP output mode. These pins can be configured for either line outputs or headphone outputs. Logical
OR with the HPEN bit in Register R29. If either the HPMODE bit or the HPEN bit is set to 1, the headphone output
is enabled.
0 = enable line output (default).
1 = enable headphone output.
R31: Playback Line Output Left Volume Control, 16,421 (0x4025)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LOUTM
LOMODE
LOUTVOL[5:0]
Table 65. Playback Line Output Left Volume Control Register
Bits
Bit Name
Description
[7:2]
LOUTVOL[5:0]
Line output volume control for left channel, LOUTN and LOUTP outputs. Each 1-bit step corresponds to a 1 dB
increase in volume. See Table 95 for a complete list of the volume settings.
Setting
000000
…
Volume
−57 dB (default)
…
111001
…
0 dB
…
111111
6 dB
1
0
LOUTM
Line output mute for left channel, LOUTN and LOUTP outputs (active low).
0 = mute.
1 = unmute (default).
LOMODE
Line output mode for left channel, LOUTN and LOUTP outputs. These pins can be configured for either line
outputs or headphone outputs. To drive earpiece speakers, set this bit to 1 (headphone output).
0 = line output (default).
1 = headphone output.
Rev. C | Page 73 of 92
ADAU1761
R32: Playback Line Output Right Volume Control, 16,422 (0x4026)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ROUTM
ROMODE
ROUTVOL[5:0]
Table 66. Playback Line Output Right Volume Control Register
Bits
Bit Name
Description
[7:2]
ROUTVOL[5:0]
Line output volume control for right channel, ROUTN and ROUTP outputs. Each 1-bit step corresponds to a 1 dB
increase in volume. See Table 95 for a complete list of the volume settings.
Setting
000000
…
Volume
−57 dB (default)
…
111001
…
0 dB
…
111111
6 dB
1
0
ROUTM
Line output mute for right channel, ROUTN and ROUTP outputs (active low).
0 = mute.
1 = unmute (default).
ROMODE
Line output mode for right channel, ROUTN and ROUTP outputs. These pins can be configured for either line
outputs or headphone outputs. To drive earpiece speakers, set this bit to 1 (headphone output).
0 = line output (default).
1 = headphone output.
R33: Playback Mono Output Control, 16,423 (0x4027)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MONOM
MOMODE
MONOVOL[5:0]
Table 67. Playback Mono Output Control Register
Bits
Bit Name
Description
[7:2]
MONOVOL[5:0] Mono output volume control. Each 1-bit step corresponds to a 1 dB increase in volume. If MX7[1:0] in Register R28
is set for common-mode output, volume control is disabled. See Table 95 for a complete list of the volume
settings.
Setting
000000
…
Volume
−57 dB (default)
…
111001
…
0 dB
…
111111
6 dB
1
0
MONOM
Mono output mute (active low).
0 = mute.
1 = unmute (default).
MOMODE
Headphone mode enable. If MX7[1:0] in Register R28 is set for common-mode output for a capless headphone
configuration, this bit should be set to 1 ( headphone output).
0 = line output (default).
1 = headphone output.
Rev. C | Page 74 of 92
ADAU1761
R34: Playback Pop/Click Suppression, 16,424 (0x4028)
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POPMODE
POPLESS
Reserved
ASLEW[1:0]
Table 68. Playback Pop/Click Suppression Register
Bits
Bit Name
Description
4
POPMODE
Pop suppression circuit power saving mode. The pop suppression circuits charge faster in normal operation;
however, after they are charged, they can be put into low power operation.
0 = normal (default).
1 = low power.
3
POPLESS
Pop suppression disable. The pop suppression circuits are enabled by default. They can be disabled to save
power; however, disabling the circuits increases the risk of pops and clicks.
0 = enabled (default).
1 = disabled.
[2:1]
ASLEW[1:0]
Analog volume slew rate for playback volume controls.
Setting
00
01
Slew Rate
21.25 ms (default)
42.5 ms
10
85 ms
11
Off
R35: Playback Power Management, 16,425 (0x4029)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HPBIAS[1:0]
PREN
PLEN
DACBIAS[1:0]
PBIAS[1:0]
Table 69. Playback Power Management Register
Bits
Bit Name
Description
[7:6]
HPBIAS[1:0]
Headphone bias control.
Setting
Headphone Bias Control
Normal operation (default)
Extreme power saving
Enhanced performance
Power saving
00
01
10
11
[5:4]
[3:2]
DACBIAS[1:0]
PBIAS[1:0]
DAC bias control.
Setting
00
01
10
11
DAC Bias Control
Normal operation (default)
Extreme power saving
Enhanced performance
Power saving
Playback path channel bias control.
Setting
00
01
Playback Path Bias Control
Normal operation (default)
Reserved
10
11
Enhanced performance
Power saving
1
0
PREN
PLEN
Playback right channel enable.
0 = disabled (default).
1 = enabled.
Playback left channel enable.
0 = disabled (default).
1 = enabled.
Rev. C | Page 75 of 92
ADAU1761
R36: DAC Control 0, 16,426 (0x402A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Reserved
Bit 2
Bit 1
Bit 0
DACPOL
DEMPH
DACMONO[1:0]
DACEN[1:0]
Table 70. DAC Control 0 Register
Bits
Bit Name
Description
[7:6]
DACMONO[1:0]
DAC mono mode. The DAC channels can be set to mono mode within the DAC and output on the left
channel, the right channel, or both channels.
Setting
00
Mono Mode
Stereo (default)
01
10
11
Left channel in mono mode
Right channel in mono mode
Both channels in mono mode
5
DACPOL
DEMPH
Invert input polarity of the DACs.
0 = normal (default).
1 = inverted.
2
DAC de-emphasis filter enable. The de-emphasis filter is designed for use with a sampling rate of 44.1 kHz only.
0 = disabled (default).
1 = enabled.
[1:0]
DACEN[1:0]
DAC enable.
Setting
00
01
DACs Enabled
Both off (default)
Left on
10
Right on
11
Both on
R37: DAC Control 1, 16,427 (0x402B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LDAVOL[7:0]
Table 71. DAC Control 1 Register
Bits
Bit Name
Description
[7:0]
LDAVOL[7:0]
Controls the digital volume attenuation for left channel inputs from the left DAC. Each bit corresponds to a
0.375 dB step with slewing between settings. See Table 94 for a complete list of the volume settings.
Setting
00000000
00000001
00000010
…
Volume Attenuation
0 dB (default)
−0.375 dB
−0.75 dB
…
11111110
11111111
−95.25 dB
−95.625 dB
Rev. C | Page 76 of 92
ADAU1761
R38: DAC Control 2, 16,428 (0x402C)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDAVOL[7:0]
Table 72. DAC Control 2 Register
Bits
Bit Name
Description
[7:0]
RDAVOL[7:0]
Controls the digital volume attenuation for right channel inputs from the right DAC. Each bit corresponds to a
0.375 dB step with slewing between settings. See Table 94 for a complete list of the volume settings.
Setting
00000000
00000001
00000010
…
Volume Attenuation
0 dB (default)
−0.375 dB
−0.75 dB
…
11111110
11111111
−95.25 dB
−95.625 dB
R39: Serial Port Pad Control, 16,429 (0x402D)
The optional pull-up/pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the serial port
signals to a defined state when the signal source becomes three-state.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCSDP[1:0]
DACSDP[1:0]
LRCLKP[1:0]
BCLKP[1:0]
Table 73. Serial Port Pad Control Register
Bits
Bit Name
Description
[7:6]
ADCSDP[1:0]
ADC_SDATA pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
[5:4]
[3:2]
[1:0]
DACSDP[1:0]
LRCLKP[1:0]
BCLKP[1:0]
DAC_SDATA pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
LRCLK pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
BCLK pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
Rev. C | Page 77 of 92
ADAU1761
R40: Control Port Pad Control 0, 16,431 (0x402F)
The optional pull-up/pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the control port
signals to a defined state when the signal source becomes three-state.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SCLP[1:0]
Bit 1
Bit 0
SDAP[1:0]
CDATP[1:0]
CLCHP[1:0]
Table 74. Control Port Pad Control 0 Register
Bits
Bit Name
Description
[7:6]
CDATP[1:0]
CDATA pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
[5:4]
[3:2]
[1:0]
CLCHP[1:0]
SCLP[1:0]
SDAP[1:0]
CLATCH pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
SCL/CCLK pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
SDA/COUT pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
R41: Control Port Pad Control 1, 16,432 (0x4030)
With IOVDD set to 3.3 V, the low and high drive strengths of the SDA/COUT pin are approximately 2.0 mA and 4.0 mA, respectively.
With IOVDD set to 1.8 V, the low and high drive strengths are approximately 0.8 mA and 1.7 mA, respectively. The high drive strength
mode may be useful for generating a stronger ACK pulse in I2C mode, if needed.
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
SDASTR
Table 75. Control Port Pad Control 1 Register
Bits
Bit Name
Description
0
SDASTR
SDA/COUT pin drive strength.
0 = low (default).
1 = high.
Rev. C | Page 78 of 92
ADAU1761
R42: Jack Detect Pin Control, 16,433 (0x4031)
With IOVDD set to 3.3 V, the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively.
With IOVDD set to 1.8 V, the low and high drive strengths are approximately 0.8 mA and 1.7 mA, respectively. The optional pull-up/
pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the input signals to a defined state when
the signal source becomes three-state.
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
JDP[1:0]
Bit 1
Bit 0
Reserved
JDSTR
Reserved
Table 76. Jack Detect Pin Control Register
Bits
Bit Name
Description
5
JDSTR
JACKDET/MICIN pin drive strength.
0 = low (default).
1 = high.
[3:2]
JDP[1:0]
JACKDET/MICIN pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
R67: Dejitter Control, 16,438 (0x4036)
The dejitter control register allows the size of the dejitter window to be set, and also allows all dejitter circuits in the device to be activated or
bypassed. Dejitter circuits protect against duplicate samples or skipped samples due to jitter from the serial ports in slave mode. Disabling
and reenabling certain subsystems in the device—that is, the ADCs, serial ports, SigmaDSP core, and DACs—during operation can cause
the associated dejitter circuits to fail. As a result, audio data fails to be output to the next subsystem in the device.
When the serial ports are in master mode, the dejitter circuit can be bypassed by setting the dejitter window to 0. When the serial ports
are in slave mode, the dejitter circuit can be reinitialized prior to outputting audio from the device, guaranteeing that audio is output to
the next subsystem in the device. Any time that audio must pass through the ADCs, serial port, sound engine/DSP core, or DACs, the
dejitter circuit can be bypassed and reset by setting the dejitter window size to 0. In this way, the dejitter circuit can be immediately
reactivated, without a wait period, by setting the dejitter window size to the default value of 3.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
DEJIT[7:0]
Bit 2
Bit 1
Bit 0
Table 77. Dejitter Control Register
Bits
Bit Name
Description
Dejitter window size.
Window Size
00000000
…
[7:0]
DEJIT[7:0]
Core Clock Cycles
0
…
00000011
…
00000101
3 (default)
…
5
Rev. C | Page 79 of 92
ADAU1761
R43 to R47: Cyclic Redundancy Check Registers, 16,576 to 16,580 (0x40C0 to 0x40C4)
The cyclic redundancy check (CRC) constantly checks the validity of the program RAM contents. SigmaStudio generates a 32-bit hash
sum, which must be written to four consecutive read-only 8-bit register locations. CRC must then be enabled. Every 1024 frames (21 ms
at 48 kHz), the IC generates its own 32-bit code and compares it to the one stored in these registers. If the codes do not match, a GPIO pin
is set high (CRC flag). This output flag must be enabled using the output CRC error sticky setting in the GPIO pin control register (see
Table 79). The 1-bit CRC error flag is reset when the CRCEN bit goes low. For example, a GPIO pin can be connected to an interrupt pin
on an external microcontroller, which triggers a rewrite of the corrupted memory.
By default, CRC is disabled (the CRCEN bit is set to 0). To enable continuous CRC checking, the user can set the CRCEN bit to 1 after
loading a program and sending the correct CRC, which is calculated by SigmaStudio. If an error occurs, it can be cleared by setting the
CRCEN bit low, fixing the error (presumably by reloading the program), and then setting the CRCEN bit high again.
Address
0x40C0
0x40C1
0x40C2
0x40C3
0x40C4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CRC[31:24]
CRC[23:16]
CRC[15:8]
CRC[7:0]
Bit 2
Bit 1
Bit 0
Reserved
CRCEN
Table 78. Cyclic Redundancy Check Registers
Address
Register
R43
R44
R45
R46
Bit Name
CRC[31:24]
CRC[23:16]
CRC[15:8]
CRC[7:0]
Description
Decimal
16,576
16,577
16,578
16,579
16,580
Hex
0x40C0
0x40C1
0x40C2
0x40C3
0x40C4
CRC hash sum, Bits[31:24] (read-only register)
CRC hash sum, Bits[23:16] (read-only register)
CRC hash sum, Bits[15:8] (read-only register)
CRC hash sum, Bits[7:0] (read-only register)
R47
CRCEN
CRC enable
0 = disabled (default)
1 = enabled
Rev. C | Page 80 of 92
ADAU1761
R48 to R51: GPIO Pin Control, 16,582 to 16,585 (0x40C6 to 0x40C9)
The GPIO pin control register sets the functionality of each GPIO pin as shown in Table 79. The GPIO functions use the same pins as the
serial port and must be enabled in the serial data/GPIO pin configuration register (Address 0x40F4). When the GPIO pins are set to
I2C/SPI port control mode, the pins are set through writes to memory locations described in Table 32. The value of the optional internal
pull-up is nominally 250 kΩ.
The output CRC error and output watchdog error settings are sticky, that is, once set, they remain set until the ADAU1761 is reset.
Address
0x40C6
0x40C7
0x40C8
0x40C9
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
GPIO0[3:0]
GPIO1[3:0]
GPIO2[3:0]
GPIO3[3:0]
Bit 0
Reserved
Reserved
Reserved
Table 79. GPIO Pin Functionality Bit Settings
GPIOx[3:0] Bits
GPIO Pin Function
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Input without debounce (default)
Input with debounce (0.3 ms)
Input with debounce (0.6 ms)
Input with debounce (0.9 ms)
Input with debounce (5 ms)
Input with debounce (10 ms)
Input with debounce (20 ms)
Input with debounce (40 ms)
Input controlled by I2C/SPI port
Output set by I2C/SPI port, with pull-up
Output set by I2C/SPI port, no pull-up
Output set by DSP core, with pull-up
Output set by DSP core, no pull-up
Reserved
1110
Output CRC error (sticky)
1111
Output watchdog error (sticky)
Table 80. GPIO Pin Control Registers
Address
Register
R48
R49
R50
R51
Bit Name
GPIO0[3:0]
GPIO1[3:0]
GPIO2[3:0]
GPIO3[3:0]
Description
Decimal
16,582
16,583
16,584
16,585
Hex
0x40C6
0x40C7
0x40C8
0x40C9
GPIO 0 pin function (see Table 79)
GPIO 1 pin function (see Table 79)
GPIO 2 pin function (see Table 79)
GPIO 3 pin function (see Table 79)
Rev. C | Page 81 of 92
ADAU1761
R52 to R56: Watchdog Registers, 16,592 to 16,596 (0x40D0 to 0x40D4)
A program counter watchdog is used when the core does block processing (which can span several samples). The watchdog flags an error
if the program counter reaches a specific 24-bit value (ranging from 0x000000 to 0xFFFFFF) that is set in the register map. This value
consists of three consecutive 8-bit register locations. The error flag sends a high signal to one of the GPIO pins. The watchdog function
must be enabled by setting the DOGEN bit high in Register R52 (Address 0x40D0).
The watchdog error bit (DOGER) is the 1-bit watchdog error flag that can be sent to a GPIO pin, as described in Table 79. This error flag
can connect, for example, to an interrupt pin on a microcontroller in the system. The flag is reset when the DOGEN bit goes low. This
flag can also be read back over the control port from Register R56 (Address 0x40D4).
Address
0x40D0
0x40D1
0x40D2
0x40D3
0x40D4
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
DOGEN
DOG[23:16]
DOG[15:8]
DOG[7:0]
Reserved
DOGER
Table 81. Watchdog Registers
Address
Hex
Register
Bit Name
Description
Decimal
R52
16,592
0x40D0
DOGEN
Watchdog enable bit.
0 = disabled (default).
1 = enabled.
R53
R54
R55
16,593
16,594
16,595
0x40D1
0x40D2
0x40D3
DOG[23:16] Watchdog value, Bits[23:16] (MSB).
DOG[15:8]
DOG[7:0]
Watchdog value, Bits[15:8].
Watchdog value, Bits[7:0].
DOG[23:16]
00000000
…
DOG[15:8]
DOG[7:0]
Hex Value
00000000
…
00000000
…
0x000000 (default)
…
11111111
11111111
11111111
0xFFFFFF
R56
16,596
0x40D4
DOGER
Watchdog error (read-only bit).
0 = no error (default).
1 = error.
R57: DSP Sampling Rate Setting, 16,619 (0x40EB)
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
DSPSR[3:0]
Bit 0
Table 82. DSP Sampling Rate Setting Register
Bits
Bit Name
Description
[3:0]
DSPSR[3:0]
SigmaDSP core sampling rate. The DSP sampling rate is a ratio of the base sampling rate, fS. The base sampling rate
is determined by the operating frequency of the core clock. For most applications, the SigmaDSP core sampling
rate should equal the converter sampling rate (set using the CONVSR[2:0] bits in Register R17) and the serial
port sampling rate (set using the SPSR[2:0] bits in Register R64).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1111
Sampling Rate
Base Sampling Rate (fS = 48 kHz)
fS/0.5
fS
fS/1.5
fS/2
fS/3
fS/4
fS/6
96 kHz, base
48 kHz (default)
32 kHz
24 kHz
16 kHz
12 kHz
8 kHz
Serial input data rate
Serial output data rate
None
Rev. C | Page 82 of 92
ADAU1761
R58: Serial Input Route Control, 16,626 (0x40F2)
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SINRT[3:0]
Table 83. Serial Input Route Control Register
Bits
Bit Name
Description
[3:0]
SINRT[3:0]
Serial data input routing. This register sets the input where the DACs receive serial data. This location can be
from the DSP or from any TDM slot on the serial port.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Routing
DSP to DACs [L, R] (default)
Serial input [L0, R0] to DACs [L, R]
Reserved
Serial input [L1, R1] to DACs [L, R]
Reserved
Serial input [L2, R2] to DACs [L, R]
Reserved
Serial input [L3, R3] to DACs [L, R]
Reserved
Serial input [R0, L0] to DACs [L, R]
Reserved
Serial input [R1, L1] to DACs [L, R]
Reserved
Serial input [R2, L2] to DACs [L, R]
Reserved
Serial input [R3, L3] to DACs [L, R]
R59: Serial Output Route Control, 16,627 (0x40F3)
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SOUTRT[3:0]
Table 84. Serial Output Route Control Register
Bits
Bit Name
Description
[3:0]
SOUTRT[3:0]
Serial data output routing. This register sets the output where the ADCs send serial data. This location can be to
the DSP or to any TDM slot on the serial port.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Routing
ADCs [L, R] to DSP (default)
ADCs [L, R] to serial output [L0, R0]
Reserved
ADCs [L, R] to serial output [L1, R1]
Reserved
ADCs [L, R] to serial output [L2, R2]
Reserved
ADCs [L, R] to serial output [L3, R3]
Reserved
ADCs [L, R] to serial output [R0, L0]
Reserved
ADCs [L, R] to serial output [R1, L1]
Reserved
ADCs [L, R] to serial output [R2, L2]
Reserved
ADCs [L, R] to serial output [R3, L3]
Rev. C | Page 83 of 92
ADAU1761
R60: Serial Data/GPIO Pin Configuration, 16,628 (0x40F4)
The serial data/GPIO pin configuration register controls the functionality of the serial data port pins. If the bits in this register are set to 1,
these pins are configured as GPIO interfaces to the SigmaDSP. If these bits are set to 0, they are configured as serial data I/O port pins.
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LRGP3
SDIGP0
BGP2
SDOGP1
Table 85. Serial Data/GPIO Pin Configuration Register
Bits
Bit Name
Description
3
LRGP3
LRCLK or GPIO3 pin configuration select.
0 = LRCLK enabled (default).
1 = GPIO3 enabled.
2
1
0
BGP2
BCLK or GPIO2 pin configuration select.
0 = BCLK enabled (default).
1 = GPIO2 enabled.
SDOGP1
SDIGP0
ADC_SDATA or GPIO1 pin configuration select.
0 = ADC_SDATA enabled (default).
1 = GPIO1 enabled.
DAC_SDATA or GPIO0 pin configuration select.
0 = DAC_SDATA enabled (default).
1 = GPIO0 enabled.
R61: DSP Enable, 16,629 (0x40F5)
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
DSPEN
Table 86. DSP Enable Register
Bits
Bit Name
Description
0
DSPEN
Enables the DSP. Set this bit before writing to the parameter RAM and before setting the DSPRUN bit in
Register R62 (Address 0x40F6).
0 = DSP disabled (default).
1 = DSP enabled.
R62: DSP Run, 16,630 (0x40F6)
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
DSPRUN
Table 87. DSP Run Register
Bits
Bit Name
Description
0
DSPRUN
Run the DSP. Set the DSPEN bit in Register R61 (Address 0x40F5) before setting this bit.
0 = DSP off (default).
1 = run the DSP.
Rev. C | Page 84 of 92
ADAU1761
R63: DSP Slew Modes, 16,631 (0x40F7)
The DSP slew modes register sets the slew source for each output. The slew source can be either the DSP (digital slew) or the codec (analog
slew). When these bits are set to Logic 0, the codec provides volume slew according to the ASLEW[1:0] bits in Register R34 (playback
pop/click suppression register, Address 0x4028). When these bits are set to Logic 1, the slew is provided and defined by the DSP program,
disabling the codec volume slew.
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MOSLW
RHPSLW
LHPSLW
ROSLW
LOSLW
Table 88. DSP Slew Modes Register
Bits
Bit Name
Description
4
MOSLW
Mono output slew generation.
0 = codec (default).
1 = DSP.
3
2
1
0
ROSLW
LOSLW
Line output right slew generation.
0 = codec (default).
1 = DSP.
Line output left slew generation.
0 = codec (default).
1 = DSP.
RHPSLW
LHPSLW
Headphone right slew generation.
0 = codec (default).
1 = DSP.
Headphone left slew generation.
0 = codec (default).
1 = DSP.
R64: Serial Port Sampling Rate, 16,632 (0x40F8)
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPSR[2:0]
Table 89. Serial Port Sampling Rate Register
Bits
Bit Name
Description
[2:0]
SPSR[2:0]
Serial port sampling rate. The serial port sampling rate is a ratio of the base sampling rate, fS. The base sampling
rate is determined by the operating frequency of the core clock. For most applications, the serial port sampling
rate should equal the converter sampling rate (set using the CONVSR[2:0] bits in Register R17) and the DSP sampling
rate (set using the DSPSR[3:0] bits in Register R57).
Setting
000
001
Sampling Rate
Base Sampling Rate (fS = 48 kHz)
fS
fS/6
48 kHz, base (default)
8 kHz
010
fS/4
12 kHz
011
fS/3
16 kHz
100
fS/2
24 kHz
101
110
111
fS/1.5
fS/0.5
Reserved
32 kHz
96 kHz
Rev. C | Page 85 of 92
ADAU1761
R65: Clock Enable 0, 16,633 (0x40F9)
This register disables or enables the digital clock engine for different blocks within the ADAU1761. For maximum power saving, use this
register to disable blocks that are not being used.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SLEWPD
ALCPD
DECPD
SOUTPD
SPPD
INTPD
SINPD
Table 90. Clock Enable 0 Register
Bits
Bit Name
Description
6
SLEWPD
Codec slew digital clock engine enable. When powered down, the analog playback path volume controls are
disabled and stay set to their current state.
0 = powered down (default).
1 = enabled.
5
4
3
2
1
0
ALCPD
DECPD
SOUTPD
INTPD
SINPD
SPPD
ALC digital clock engine enable.
0 = powered down (default).
1 = enabled.
Decimator resync (dejitter) digital clock engine enable.
0 = powered down (default).
1 = enabled.
Serial routing outputs digital clock engine enable.
0 = powered down (default).
1 = enabled.
Interpolator resync (dejitter) digital clock engine enable.
0 = powered down (default).
1 = enabled.
Serial routing inputs digital clock engine enable.
0 = powered down (default).
1 = enabled.
Serial port digital clock engine enable.
0 = powered down (default).
1 = enabled.
R66: Clock Enable 1, 16,634 (0x40FA)
This register enables Digital Clock Generator 0 and Digital Clock Generator 1. Digital Clock Generator 0 generates sample rates for the
ADCs, DACs, and DSP. Digital Clock Generator 1 generates BCLK and LRCLK for the serial port when the part is in master mode. For
maximum power saving, use this register to disable clocks that are not being used.
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
CLK0
CLK1
Table 91. Clock Enable 1 Register
Bits
Bit Name
Description
1
CLK1
Digital Clock Generator 1.
0 = off (default).
1 = on.
0
CLK0
Digital Clock Generator 0.
0 = off (default).
1 = on.
Rev. C | Page 86 of 92
ADAU1761
Table 92. R8 and R9 Volume Settings
Volume Setting (dB)
Binary Value
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
Binary Value
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Volume Setting (dB)
−12
−11.25
−10.5
−9.75
−9
−8.25
−7.5
−6.75
−6
−5.25
−4.5
−3.75
−3
−2.25
−1.5
−0.75
0
0.75
1.5
2.25
3
3.75
4.5
5.25
6
6.75
7.5
8.25
9
9.75
10.5
11.25
12
12.75
13.5
14.25
15
15.75
16.5
17.25
18
18.75
19.5
20.25
21
21.75
22.5
23.25
24
24.75
25.5
26.25
27
27.75
28.5
29.25
30
30.75
31.5
32.25
33
33.75
34.5
35.25
Table 93. R14 Noise Gate Threshold
Noise Gate Threshold (dB)
Binary Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
−76.5
−75
−73.5
−72
−70.5
−69
−67.5
−66
−64.5
−63
−61.5
−60
−58.5
−57
−55.5
−54
−52.5
−51
−49.5
−48
−46.5
−45
−43.5
−42
−40.5
−39
−37.5
−36
−34.5
−33
−31.5
−30
Rev. C | Page 87 of 92
ADAU1761
Table 94. R20, R21, R37, and R38 Volume Settings
Binary Value
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
Volume Attenuation (dB)
0
Binary Value
00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111
00111000
00111001
00111010
00111011
00111100
00111101
00111110
00111111
01000000
01000001
01000010
01000011
01000100
01000101
01000110
01000111
01001000
01001001
01001010
01001011
01001100
01001101
01001110
01001111
01010000
01010001
01010010
01010011
01010100
01010101
01010110
01010111
01011000
01011001
01011010
01011011
01011100
01011101
01011110
01011111
Volume Attenuation (dB)
−18
−0.375
−0.75
−18.375
−18.75
−19.125
−19.5
−1.125
−1.5
−1.875
−2.25
−19.875
−20.25
−20.625
−21
−2.625
−3
−3.375
−3.75
−21.375
−21.75
−22.125
−22.5
−4.125
−4.5
−4.875
−5.25
−22.875
−23.25
−23.625
−24
−5.625
−6
−6.375
−6.75
−24.375
−24.75
−25.125
−25.5
−7.125
−7.5
−7.875
−8.25
−25.875
−26.25
−26.625
−27
−8.625
−9
−9.375
−9.75
−27.375
−27.75
−28.125
−28.5
−10.125
−10.5
−10.875
−11.25
−11.625
−12
−28.875
−29.25
−29.625
−30
−12.375
−12.75
−13.125
−13.5
−30.375
−30.75
−31.125
−31.5
−13.875
−14.25
−14.625
−15
−31.875
−32.25
−32.625
−33
−15.375
−15.75
−16.125
−16.5
−33.375
−33.75
−34.125
−34.5
−16.875
−17.25
−17.625
−34.875
−35.25
−35.625
Rev. C | Page 88 of 92
ADAU1761
Binary Value
01100000
01100001
01100010
01100011
01100100
01100101
01100110
01100111
01101000
01101001
01101010
01101011
01101100
01101101
01101110
01101111
01110000
01110001
01110010
01110011
01110100
01110101
01110110
01110111
01111000
01111001
01111010
01111011
01111100
01111101
01111110
01111111
10000000
10000001
10000010
10000011
10000100
10000101
10000110
10000111
10001000
10001001
10001010
10001011
10001100
10001101
10001110
10001111
10010000
Volume Attenuation (dB)
−36
Binary Value
10010001
10010010
10010011
10010100
10010101
10010110
10010111
10011000
10011001
10011010
10011011
10011100
10011101
10011110
10011111
10100000
10100001
10100010
10100011
10100100
10100101
10100110
10100111
10101000
10101001
10101010
10101011
10101100
10101101
10101110
10101111
10110000
10110001
10110010
10110011
10110100
10110101
10110110
10110111
10111000
10111001
10111010
10111011
10111100
10111101
10111110
10111111
11000000
11000001
Volume Attenuation (dB)
−54.375
−54.75
−55.125
−55.5
−36.375
−36.75
−37.125
−37.5
−55.875
−56.25
−56.625
−57
−37.875
−38.25
−38.625
−39
−57.375
−57.75
−58.125
−58.5
−39.375
−39.75
−40.125
−40.5
−58.875
−59.25
−59.625
−60
−40.875
−41.25
−41.625
−42
−60.375
−60.75
−61.125
−61.5
−42.375
−42.75
−43.125
−43.5
−61.875
−62.25
−62.625
−63
−43.875
−44.25
−44.625
−45
−63.375
−63.75
−64.125
−64.5
−45.375
−45.75
−46.125
−46.5
−64.875
−65.25
−65.625
−66
−46.875
−47.25
−47.625
−48
−66.375
−66.75
−67.125
−67.5
−48.375
−48.75
−49.125
−49.5
−67.875
−68.25
−68.625
−69
−49.875
−50.25
−50.625
−51
−69.375
−69.75
−70.125
−70.5
−51.375
−51.75
−52.125
−52.5
−70.875
−71.25
−71.625
−72
−52.875
−53.25
−53.625
−54
−72.375
Rev. C | Page 89 of 92
ADAU1761
Binary Value
11000010
11000011
11000100
11000101
11000110
11000111
11001000
11001001
11001010
11001011
11001100
11001101
11001110
11001111
11010000
11010001
11010010
11010011
11010100
11010101
11010110
11010111
11011000
11011001
11011010
11011011
11011100
11011101
11011110
11011111
11100000
11100001
11100010
11100011
11100100
11100101
11100110
11100111
11101000
11101001
11101010
11101011
11101100
11101101
11101110
11101111
11110000
11110001
11110010
Volume Attenuation (dB)
−72.75
−73.125
−73.5
Binary Value
11110011
11110100
11110101
11110110
11110111
11111000
11111001
11111010
11111011
11111100
11111101
11111110
11111111
Volume Attenuation (dB)
−91.125
−91.5
−91.875
−92.25
−73.875
−74.25
−74.625
−75
−92.625
−93
−93.375
−93.75
−75.375
−75.75
−76.125
−76.5
−94.125
−94.5
−94.875
−95.25
−76.875
−77.25
−77.625
−78
−95.625
Table 95. R29 through R33 Volume Settings
−78.375
−78.75
−79.125
−79.5
Binary Value
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
Volume Setting (dB)
−57
−56
−55
−54
−53
−52
−51
−50
−49
−48
−47
−46
−45
−44
−43
−42
−41
−40
−39
−38
−37
−36
−35
−34
−33
−32
−31
−30
−29
−28
−27
−26
−25
−79.875
−80.25
−80.625
−81
−81.375
−81.75
−82.125
−82.5
−82.875
−83.25
−83.625
−84
−84.375
−84.75
−85.125
−85.5
−85.875
−86.25
−86.625
−87
−87.375
−87.75
−88.125
−88.5
−88.875
−89.25
−89.625
−90
−90.375
−90.75
Rev. C | Page 90 of 92
ADAU1761
Binary Value
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Volume Setting (dB)
−24
−23
−22
−21
−20
−19
−18
−17
−16
−15
−14
−13
−12
−11
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
Rev. C | Page 91 of 92
ADAU1761
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
EXPOSED
PAD
(BOTTOM VIEW)
3.65
3.50 SQ
3.35
TOP
VIEW
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
0.80 MAX
0.65 TYP
3.50 REF
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 71. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADAU1761BCPZ
ADAU1761BCPZ-R7
ADAU1761BCPZ-RL
EVAL-ADAU1761Z
Temperature Range Package Description
Package Option
CP-32-4
CP-32-4
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7”Tape and Reel
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 13”Tape and Reel
Evaluation Board
CP-32-4
1 Z = RoHS Compliant Part.
©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07680-0-9/10(C)
Rev. C | Page 92 of 92
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