ADAU1772BCPZ [ADI]
Four ADC, Two DAC Low Power Codec;
| 型号： | ADAU1772BCPZ |
| 厂家： | 
ADI |
| 描述： | Four ADC, Two DAC Low Power Codec 商用集成电路 |
| 文件： | 总117页 (文件大小：6246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Four ADC, Two DAC Low Power Codec
with Audio Processor
ADAU1772
Data Sheet
Low power (15 mW for typical noise cancelling solution)
I2C and SPI control interfaces, self-boot from I2C EEPROM
7 MP pins supporting dual stereo digital microphone inputs,
stereo PDM output, mute, DSP bypass, push-button
volume controls, and parameter bank switching
FEATURES
Programmable audio processing engine
192 kHz processing path
Biquad filters, limiters, volume controls, mixing
Low latency, 24-bit ADCs and DACs
102 dB SNR (signal through PGA and ADC
with A-weighted filter)
107 dB combined SNR (signal through DAC and headphone
with A-weighted filter)
Serial port sample rates from 8 kHz to 192 kHz
38 μs analog-to-analog latency
APPLICATIONS
Noise cancelling handsets, headsets, and headphones
Bluetooth ANC handsets, headsets, and headphones
Personal navigation devices
Digital still and video cameras
4 single-ended analog inputs—configurable as microphone
or line inputs
GENERAL DESCRIPTION
The ADAU1772 is a codec with four inputs and two outputs that
incorporates a digital processing engine to perform filtering,
level control, signal level monitoring, and mixing. The path
from the analog input to the DSP core to the analog output is
optimized for low latency and is ideal for noise cancelling headsets.
With the addition of just a few passive components, a crystal,
and an EEPROM for booting, the ADAU1772 provides a
complete headset solution.
Dual stereo digital microphone inputs
Stereo analog audio output—single-ended or differential,
configurable as either line output or headphone driver
PLL supporting any input clock rate from 8 MHz to 27 MHz
Full-duplex, asynchronous sample rate converters (ASRCs)
Power supplies
Analog and digital I/O of 1.8 V to 3.3 V
Digital signal processing (DSP) core of 1.1 V to 1.8 V
FUNCTIONAL BLOCK DIAGRAM
MICBIAS0
MICBIAS1
MICROPHONE
BIAS GENERATORS
POWER
MANAGEMENT
LDO
REGULATOR
ADAU1772
AIN0REF
AIN0
ADC_SDATA1/CLKOUT/MP6
XTALI/MCLKIN
PGA
CLOCK
OSCILLATOR
ADC
MODULATOR
PLL
ADC
DECIMATOR
XTALO
AIN1REF
AIN1
HPOUTLP/LOUTLP
HPOUTLN/LOUTLN
PGA
DAC
DAC
ADC
MODULATOR
ADC
INPUT/OUTPUT
SIGNAL
DECIMATOR
STEREO PDM
MODULATOR
ROUTING
DMIC0_1/MP4
DMIC2_3/MP5
DIGITAL
MICROPHONE
INPUTS
HPOUTRP/LOUTRP
HPOUTRN/LOUTRN
AIN2REF
AIN2
ADC
DECIMATOR
PGA
DAC_SDATA/MP0
ADC_SDATA0/PDMOUT/MP1
BCLK/MP2
ADC
MODULATOR
SERIAL
INPUT/
OUTPUT
PORT
BIDIRECTIONAL
ASRCS
LRCLK/MP3
DSP CORE:
BIQUAD FILTERS,
LIMITERS,
VOLUME CONTROLS,
MIXING
AIN3REF
AIN3
ADC
DECIMATOR
PGA
2
ADC
MODULATOR
I C/SPI CONTROL
INTERFACE AND SELF-BOOT
CM
Figure 1.
Rev. C
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ADAU1772* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DESIGN RESOURCES
• ADAU1772 Material Declaration
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EVALUATION KITS
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DOCUMENTATION
Data Sheet
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• ADAU1772: Four ADC, Two DAC Low Power Codec with
Audio Processor Data Sheet
User Guides
• UG-477: Evaluating the ADAU1772 Four ADC, Two DAC
Low Power Codec with Audio Processor
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TOOLS AND SIMULATIONS
• ADAU1772 IBIS Model
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ADAU1772
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Control Port .................................................................................... 40
I2C Port ........................................................................................ 40
SPI Port........................................................................................ 43
Self-Boot...................................................................................... 44
Multipurpose Pins.......................................................................... 45
Push-Button Volume Controls................................................. 45
Limiter Compression Enable .................................................... 45
Parameter Bank Switching........................................................ 45
Mute ............................................................................................. 45
DSP Bypass Mode ...................................................................... 46
Serial Data Input/Output Ports .................................................... 47
Tristating Unused Channels...................................................... 47
Applications Information.............................................................. 50
Power Supply Bypass Capacitors.............................................. 50
Layout .......................................................................................... 50
Grounding................................................................................... 50
Exposed Pad PCB Design ......................................................... 50
Register Summary .......................................................................... 51
Register Details ............................................................................... 53
Clock Control Register .............................................................. 53
PLL Denominator MSB Register.............................................. 54
PLL Denominator LSB Register ............................................... 54
PLL Numerator MSB Register.................................................. 54
PLL Numerator LSB Register.................................................... 55
PLL Integer Setting Register ..................................................... 55
PLL Lock Flag Register.............................................................. 56
CLKOUT Setting Selection Register........................................ 56
Regulator Control Register ....................................................... 57
Core Control Register................................................................ 58
Filter Engine and Limiter Control Register............................ 59
DB Value Register 0 Read.......................................................... 60
DB Value Register 1 Read.......................................................... 60
DB Value Register 2 Read.......................................................... 61
Core Channel 0/Core Channel 1 Input Select Register......... 62
Core Channel 2/Core Channel 3 Input Select Register......... 63
DAC Input Select Register ........................................................ 64
PDM Modulator Input Select Register.................................... 65
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Analog Performance Specifications........................................... 4
Crystal Amplifier Specifications................................................. 7
Digital Input/Output Specifications........................................... 8
Power Supply Specifications........................................................ 8
Typical Power Consumption....................................................... 9
Digital Filters................................................................................. 9
Digital Timing Specifications ................................................... 10
Absolute Maximum Ratings.......................................................... 14
Thermal Resistance .................................................................... 14
ESD Caution................................................................................ 14
Pin Configuration and Function Descriptions........................... 15
Typical Performance Characteristics ........................................... 17
System Block Diagrams ................................................................. 28
Theory of Operation ...................................................................... 29
System Clocking and Power-Up................................................... 30
Clock Initialization..................................................................... 30
PLL ............................................................................................... 30
Clock Output............................................................................... 31
Power Sequencing ...................................................................... 31
Signal Routing................................................................................. 32
Input Signal Paths........................................................................... 33
Analog Inputs.............................................................................. 33
Digital Microphone Input ......................................................... 34
Analog-to-Digital Converters................................................... 34
Output Signal Paths........................................................................ 35
Analog Outputs........................................................................... 35
Digital-to-Analog Converters................................................... 35
PDM Output ............................................................................... 35
Asynchronous Sample Rate Converters .................................. 36
Signal Levels................................................................................ 36
Signal Processing ............................................................................ 37
Instructions ................................................................................. 37
Data Memory.............................................................................. 37
Parameters................................................................................... 37
Serial Data Output 0/Serial Data Output 1 Input Select
Register ........................................................................................ 66
Rev. C | Page 2 of 116
Data Sheet
ADAU1772
Serial Data Output 2/Serial Data Output 3 Input Select
Register .........................................................................................67
Headphone Output Mutes Register..........................................89
Serial Port Control 0 Register....................................................90
Serial Port Control 1 Register....................................................91
TDM Output Channel Disable Register ..................................92
PDM Enable Register .................................................................93
PDM Pattern Setting Register ...................................................94
MP0 Function Setting Register .................................................94
MP1 Function Setting Register .................................................95
MP2 Function Setting Register .................................................96
MP3 Function Setting Register .................................................97
MP4 Function Setting Register .................................................98
MP5 Function Setting Register .................................................99
MP6 Function Setting Register ...............................................100
Push-Button Volume Settings Register..................................101
Push-Button Volume Control Assignment Register ............102
Debounce Modes Register.......................................................103
Headphone Line Output Select Register................................103
Decimator Power Control Register ........................................105
Serial Data Output 4/Serial Data Output 5 Input Select
Register .........................................................................................68
Serial Data Output 6/Serial Data Output 7 Input Select
Register .........................................................................................69
ADC_SDATA0/ADC_SDATA1 Channel Select Register......70
Output ASRC0/Output ASRC1 Source Register.....................71
Output ASRC2/Output ASRC3 Source Register.....................72
Input ASRC Channel Select Register........................................73
ADC0/ADC1 Control 0 Register..............................................74
ADC2/ADC3 Control 0 Register..............................................75
ADC0/ADC1 Control 1 Register..............................................76
ADC2/ADC3 Control 1 Register..............................................77
ADC0 Volume Control Register ...............................................78
ADC1 Volume Control Register ...............................................78
ADC2 Volume Control Register ...............................................79
ADC3 Volume Control Register ...............................................79
PGA Control 0 Register..............................................................80
PGA Control 1 Register..............................................................80
PGA Control 2 Register..............................................................81
PGA Control 3 Register..............................................................82
PGA Slew Control Register........................................................83
PGA 10 dB Gain Boost Register................................................84
Input and Output Capacitor Charging Register .....................85
DSP Bypass Path Register ..........................................................86
DSP Bypass Gain for PGA0 Register........................................86
DSP Bypass Gain for PGA1 Register........................................86
MIC_BIAS0_1 Control Register ...............................................87
DAC Control Register ................................................................87
DAC0 Volume Control Register................................................88
DAC1 Volume Control Register................................................88
ASRC Interpolator and DAC Modulator Power Control
Register.......................................................................................106
Analog Bias Control 0 Register...............................................106
Analog Bias Control 1 Register...............................................107
Digital Pin Pull-Up Control 0 Register..................................108
Digital Pin Pull-Up Control 1 Register..................................109
Digital Pin Pull-Down Control 0 Register ............................110
Digital Pin Pull-Down Control 1 Register ............................111
Digital Pin Drive Strength Control 0 Register ......................112
Digital Pin Drive Strength Control 1 Register ......................113
Outline Dimensions......................................................................114
Ordering Guide .........................................................................114
REVISION HISTORY
3/14—Rev. B to Rev. C
8/12—Rev. 0 to Rev. A
Changes to Figure 60 and Figure 62 Captions ............................25
Added Figure 64, Figure 65, Figure 66, Figure 67, Figure 68,
and Figure 69, Renumbered Sequentially ....................................26
Added Figure 70, and Figure 71....................................................27
Changes to Figure 69 ......................................................................31
7/12—Revision 0: Initial Version
12/12—Rev. A to Rev. B
Changes to Figure 90 ......................................................................47
Rev. C | Page 3 of 116
ADAU1772
Data Sheet
SPECIFICATIONS
Master clock = core clock = 12.288 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width =
24 bits, ambient temperature = 25°C, outputs line loaded with 10 kΩ.
ANALOG PERFORMANCE SPECIFICATIONS
Supply voltages AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted. PLL disabled, direct master clock.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Digital Attenuation Step
Digital Attenuation Range
INPUT RESISTANCE
All ADCs
24
0.375
95
Bits
dB
dB
Gain settings do not include 10 dB gain from
PGA_x_BOOST settings; this additional gain does
not affect input impedance; PGA_POP_DISx = 1
Single-Ended Line Input
PGA Inputs
0 dB gain
−12 dB gain
0 dB gain
+35.25 dB gain
14.3
32.0
20
kΩ
kΩ
kΩ
kΩ
0.68
SINGLE-ENDED LINE INPUT
Full-Scale Input Voltage
PGA_ENx = 0, PGA_x_BOOST = 0, PGA_POP_DISx = 1
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 1.8 V, 0 dBFS
AVDD = 3.3 V
AVDD = 3.3 V, 0 dBFS
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD/3.63
0.49
1.38
0.90
2.54
V rms
V rms
V p-p
V rms
V p-p
Dynamic Range1
With A-Weighted Filter (RMS)
97
102
94
dB
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
With Flat 20 Hz to 20 kHz Filter
99
Signal-to-Noise Ratio (SNR)2
With A-Weighted Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
98
103
96
100
40
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
Interchannel Gain Mismatch
mdB
Total Harmonic Distortion + Noise (THD + N)
20 Hz to 20 kHz, −1 dBFS
AVDD = 1.8 V
−90
−94
0.1
0.2
100
dB
dB
mV
dB
dB
AVDD = 3.3 V
Offset Error
Gain Error
Interchannel Isolation
Power Supply Rejection Ratio
CM capacitor = 22 μF
CM capacitor = 22 μF
100 mV p-p at 1 kHz
PGA_ENx = 1, PGA_x_BOOST = 0
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 1.8 V, 0 dBFS
AVDD = 3.3 V
AVDD = 3.3 V, 0 dBFS
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
55
dB
SINGLE-ENDED PGA INPUT
Full-Scale Input Voltage
AVDD/3.63
0.49
1.38
0.90
2.54
V rms
V rms
V p-p
V rms
V p-p
Dynamic Range1
With A-Weighted Filter (RMS)
96
102
94
dB
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
With Flat 20 Hz to 20 kHz Filter
99
Rev. C | Page 4 of 116
Data Sheet
ADAU1772
Parameter
Test Conditions/Comments
20 Hz to 20 kHz, −1 dBFS
AVDD = 1.8 V
Min
Typ
Max
Unit
Total Harmonic Distortion + Noise
−88
−90
dB
dB
AVDD = 3.3 V
Signal-to-Noise Ratio2
With A-Weighted Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
96
102
94
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
99
PGA Gain Variation
With −12 dB Setting
With +35.25 dB Setting
PGA Boost
PGA Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Standard deviation
Standard deviation
PGA_x_BOOST
0.05
0.15
10
−65
0.005
0
0.2
83
63
dB
dB
dB
dB
dB
mV
dB
dB
dB
PGA_MUTEx
Gain Error
Interchannel Isolation
Power Supply Rejection Ratio
MICROPHONE BIAS
Bias Voltage
CM capacitor = 22 μF, 100 mV p-p at 1 kHz
MIC_ENx = 1
0.65 × AVDD
AVDD = 1.8 V, MIC_GAINx = 1
AVDD = 3.3 V, MIC_GAINx = 1
AVDD = 1.8 V, MIC_GAINx = 0
AVDD = 3.3 V, MIC_GAINx = 0
1.16
2.12
1.63
2.97
V
V
V
V
0.90 × AVDD
Bias Current Source
Output Impedance
MICBIASx Isolation
3
mA
Ω
dB
dB
1
95
99
MIC_GAINx = 0
MIC_GAINx = 1
AVDD = 1.8 V, 20 Hz to 20 kHz
MIC_GAINx = 0
MIC_GAINx = 1
Noise in the Signal Bandwidth3
27
16
nV/√Hz
nV/√Hz
AVDD = 3.3 V, 20 Hz to 20 kHz
MIC_GAINx = 0
MIC_GAINx = 1
35
19
nV/√Hz
nV/√Hz
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
Digital Attenuation Step
Digital Attenuation Range
DAC SINGLE-ENDED OUTPUT
All DACs
24
0.375
95
Bits
dB
dB
Single-ended operation, HPOUTLP and
HPOUTRP pins
Full-Scale Output Voltage
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 1.8 V, 0 dBFS
AVDD = 3.3 V
AVDD/3.4
0.53
1.5
0.97
2.74
V rms
V rms
V p-p
V rms
V p-p
dB
AVDD = 3.3 V, 0 dBFS
Mute Attenuation
Dynamic Range1
With A-Weighted Filter (RMS)
−72
Line output mode, 20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Line output mode, 20 Hz to 20 kHz
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
100
104
97
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
101
Signal-to-Noise Ratio2
With A-Weighted Filter (RMS)
100
104
98
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
102
Rev. C | Page 5 of 116
ADAU1772
Data Sheet
Parameter
Test Conditions/Comments
Line output mode
Line output mode, 20 Hz to 20 kHz, −1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
Line output mode
Headphone mode, 20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Min
Typ
Max
Unit
mdB
dB
dB
dB
Interchannel Gain Mismatch
Total Harmonic Distortion + Noise
20
−93
−94
0.1
Gain Error
Dynamic Range1
With A-Weighted Filter (RMS)
dB
100
104
97
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
101
Signal-to-Noise Ratio2
With A-Weighted Filter (RMS)
Headphone mode, 20 Hz to 20 kHz
AVDD = 1.8 V
AVDD = 3.3 V
100
104
98
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
AVDD = 1.8 V
AVDD = 3.3 V
Headphone mode
102
50
dB
mdB
Interchannel Gain Mismatch
Total Harmonic Distortion + Noise
32 Ω load
Headphone mode, 20 Hz to 20 kHz, −1 dBFS
AVDD = 1.8 V, PO = 6.7 mW
AVDD = 3.3 V, PO = 22.4 mW
AVDD = 1.8 V, PO = 8.9 mW
AVDD = 3.3 V, PO = 30 mW
AVDD = 1.8 V, PO = 13 mW
AVDD = 3.3 V, PO = 44 mW
−77
−80
−76
−79
−74
−77
dB
dB
dB
dB
dB
dB
24 Ω load
16 Ω load
Headphone Output Power
32 Ω Load
AVDD = 1.8 V, <0.1% THD + N
AVDD = 3.3 V, <0.1% THD + N
AVDD = 1.8 V, <0.1% THD + N
AVDD = 3.3 V, <0.1% THD + N
AVDD = 1.8 V, <0.1% THD + N
AVDD = 3.3 V, <0.1% THD + N
Headphone mode
8.4
mW
mW
mW
mW
mW
mW
dB
28.1
11.2
37.4
16.25
55.8
0.1
24 Ω Load
16 Ω Load
Gain Error
Offset Error
0.1
100
70
mV
dB
dB
Interchannel Isolation
Power Supply Rejection Ratio
DAC DIFFERENTIAL OUTPUT
Full-Scale Output Voltage
1 kHz, 0 dBFS input signal
CM capacitor = 22 μF, 100 mV p-p at 1 kHz
Differential operation
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 1.8 V, 0 dBFS
AVDD = 3.3 V
AVDD = 3.3 V, 0 dBFS
AVDD/1.8
1.0
2.58
1.83
5.49
V rms
V rms
V p-p
V rms
V p-p
dB
Mute Attenuation
Dynamic Range1
With A-Weighted Filter (RMS)
−72
Line output mode, 20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Line output mode, 20 Hz to 20 kHz
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Line output mode
Line output mode, 20 Hz to 20 kHz, −1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
Line output mode
104
107
101
105
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
Signal-to-Noise Ratio2
With A-Weighted Filter (RMS)
105
108
102
105
20
dB
dB
dB
dB
mdB
dB
dB
dB
%
With Flat 20 Hz to 20 kHz Filter
Interchannel Gain Mismatch
Total Harmonic Distortion + Noise
−96
−96
Gain Error
Rev. C | Page 6 of 116
Data Sheet
ADAU1772
Parameter
Test Conditions/Comments
Headphone mode, 20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Headphone mode, 20 Hz to 20 kHz
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Headphone mode
Headphone mode
−1 dBFS, AVDD = 1.8 V, PO = 27 mW
−1 dBFS, AVDD = 3.3 V, PO = 90 mW
−2 dBFS, AVDD = 1.8 V, PO = 28 mW
−1 dBFS, AVDD = 3.3 V, PO = 118 mW
−3 dBFS, AVDD = 1.8 V, PO = 33 mW
−1 dBFS, AVDD = 3.3 V, PO = 175 mW
Min
Typ
Max
Unit
Dynamic Range1
With A-Weighted Filter (RMS)
104
107
102
104
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
Signal-to-Noise Ratio2
With A-Weighted Filter (RMS)
105
108
103
106
75
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
Interchannel Gain Mismatch
Total Harmonic Distortion + Noise
32 Ω Load
mdB
−75
−83
−75
−77
−75
−83
dB
dB
dB
dB
dB
dB
24 Ω Load
16 Ω Load
Headphone Output Power
32 Ω Load
AVDD = 1.8 V, <0.1% THD + N
AVDD = 3.3 V, <0.1% THD + N
AVDD = 1.8 V, <0.1% THD + N
AVDD = 3.3 V, <0.1% THD + N
AVDD = 1.8 V, <0.1% THD + N
AVDD = 3.3 V, <0.1% THD + N
Headphone mode
32.5
111.8
37.6
148.3
41.5
189.2
0.25
0.1
mW
mW
mW
mW
mW
mW
%
24 Ω Load
16 Ω Load
Gain Error
Offset Error
Interchannel Isolation
Power Supply Rejection Ratio
mV
dB
1 kHz, 0 dBFS input signal
CM capacitor = 22 μF
100 mV p-p at 1 kHz
CM pin
100
73
dB
CM REFERENCE
Common-Mode Reference Output
Common-Mode Source Impedance
REGULATOR
AVDD/2
5
V
kΩ
Line Regulation
Load Regulation
1
6
mV/V
mV/mA
1 Dynamic range is the ratio of the sum of noise and harmonic power in the band of interest with a −60 dBFS signal present to the full-scale power level in decibels.
2 SNR is the ratio of the sum of all noise power in the band of interest with no signal present to the full-scale power level in decibels.
3 These specifications are with 4.7 µF decoupling and 5.0 kΩ load on pin.
CRYSTAL AMPLIFIER SPECIFICATIONS
Supply voltages AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted.
Table 2.
Test Conditions/Comments
Min
Typ
Max
500
27
Unit
ps
MHz
pF
Parameter
Jitter
Frequency Range
Load Capacitance
270
8
20
Rev. C | Page 7 of 116
ADAU1772
Data Sheet
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 3.3 V 10% and 1.8 V − 5%/+10%.
Table 3.
Parameter
Test Conditions/Comments
Min
2.0
Typ
Max
Unit
V
Input Voltage High (VIH)
IOVDD = 3.3 V
IOVDD = 1.8 V
1.1
V
Input Voltage Low (VIL)
Input Leakage
IOVDD = 3.3 V
IOVDD = 1.8 V
0.8
0.45
10
10
10
V
V
IOVDD = 3.3 V, IIH at VIH = 2.0 V
IIL at VIL = 0.8 V
IOVDD = 1.8 V, IIH at VIH = 1.1 V
IIL at VIL = 0.45 V
IOH = 1 mA
IOH = 3 mA
IOL = 1 mA
IOL = 3 mA
µA
µA
µA
µA
V
V
V
V
pF
10
Output Voltage High (VOH) with Low Drive Strength
Output Voltage High (VOH) with High Drive Strength
Output Voltage Low (VOL) with Low Drive Strength
Output Voltage Low (VOL) with High Drive Strength
Input Capacitance
IOVDD − 0.6
IOVDD − 0.6
0.4
0.4
5
POWER SUPPLY SPECIFICATIONS
Supply voltages AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted. PLL disabled, direct master clock.
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SUPPLIES
AVDD Voltage
DVDD Voltage
IOVDD Voltage
Digital I/O Current with IOVDD = 1.8 V
Slave Mode
1.71
1.045
1.71
1.8
1.1
1.8
3.63
1.98
3.63
V
V
V
Crystal oscillator enabled
fS = 48 kHz
fS = 192 kHz
fS = 8 kHz
fS = 48 kHz
fS = 192 kHz
fS = 8 kHz
0.35
0.49
0.32
0.53
1.18
0.35
0
mA
mA
mA
mA
mA
mA
µA
Master Mode
Power-Down
Digital I/O Current with IOVDD = 3.3 V
Slave Mode
Crystal oscillator enabled
fS = 48 kHz
fS = 192 kHz
fS = 8 kHz
fS = 48 kHz
fS = 192 kHz
fS = 8 kHz
2.05
2.28
1.99
2.4
3.62
2.05
7
mA
mA
mA
mA
mA
mA
µA
Master Mode
Power-Down
Analog Current (AVDD)
Power-Down
See Table 5
AVDD = 1.8 V
AVDD = 3.3 V
0.6
13.6
µA
µA
DISSIPATION
Operation
fS = 192 kHz (see conditions in Table 5)
All Supplies
15.5
0.7
14.8
1
mW
mW
mW
µW
Digital I/O Supply
Analog Supply
Power-Down, All Supplies
Includes regulated DVDD current
Rev. C | Page 8 of 116
Data Sheet
ADAU1772
TYPICAL POWER CONSUMPTION
Typical active noise cancelling (ANC) settings. Master clock = 12.288 MHz, fS = 192 kHz. On-board regulator enabled. Two analog-to-
digital converters (ADCs) with PGA enabled and two ADCs configured for line input; no input signal. Two digital-to-analog converters
(DACs) configured for differential headphone operation; DAC outputs unloaded. Both MICBIAS0 and MICBIAS1 enabled. ASRCs and
pulse density modulated (PDM) modulator disabled. Core running 26 out of 32 possible instructions. For total power consumption, add
IOVDD at 8 kHz slave current listed in Table 4.
Table 5.
Typical AVDD Power Consumption Typical ADC THD + N Typical HP Output
Operating Voltage
AVDD = IOVDD = 3.3 V Normal (default)
Extreme power saving
Power Management Setting (mA)
(dB)
THD + N (dB)
−87.5
−86.5
−86.5
−90.5
−91
11.5
9.4
9.8
12.65
9.37
7.40
7.78
10.4
−93
−93
−93
−93
Power saving
Enhanced performance
AVDD = IOVDD = 1.8 V Normal (default)
−86
Extreme power saving
Power saving
Enhanced performance
−84.5
−84.5
−86
−87
−87.5
−94.5
DIGITAL FILTERS
Table 6.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ADC INPUT TO DAC OUTPUT PATH
Pass-Band Ripple
Group Delay
DC to 20 kHz, fS = 192 kHz
fS = 192 kHz
0.02
dB
µs
38
SAMPLE RATE CONVERTER
Pass Band
LRCLK < 63 kHz
63 kHz < LRCLK <130 kHz
LRCLK > 130 kHz
Upsampling, 96 kHz
Upsampling, 192 kHz
Downsampling, 96 kHz
Downsampling, 192 kHz
0
0
0
0.475 × fS
0.4286 × fS
0.4286 × fS
0.05
0.05
0.07
kHz
Pass-Band Ripple
−0.27
−0.06
0
0
8
dB
dB
dB
dB
kHz
dB
dB
ms
0.07
192
Input/Output Frequency Range
Dynamic Range
Total Harmonic Distortion + Noise
Startup Time
100
−90
15
PDM MODULATOR
Dynamic Range (A-Weighted)
Total Harmonic Distortion + Noise
112
−92
dB
dB
Rev. C | Page 9 of 116
ADAU1772
Data Sheet
DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 1.71 V to 3.63 V, DVDD = 1.045 V to 1.98 V.
Table 7. Digital Timing
Limit
Parameter
TMIN
TMAX
Unit
Description
MASTER CLOCK
tMP
tMCLK
SERIAL PORT
tBL
tBH
tLS
tLH
tSS
tSH
tTS
37
77
125
82
ns
ns
MCLKIN period; 8 MHz to 27 MHz input clock using PLL
Internal MCLK period; direct MCLK and PLL output divided by 2
40
40
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BCLK low pulse width (master and slave modes)
BCLK high pulse width (master and slave modes)
LRCLK setup; time to BCLK rising (slave mode)
LRCLK hold; time from BCLK rising (slave mode)
DAC_SDATA setup; time to BCLK rising (master and slave modes)
DAC_SDATA hold; time from BCLK rising (master and slave modes)
BCLK falling to LRCLK timing skew (master mode)
ADC_SDATAx delay; time from BCLK falling (master and slave modes)
BCLK falling to ADC_SDATAx driven in TDM tristate mode
BCLK falling to ADC_SDATAx tristated in TDM tristate mode
5
10
34
30
30
tSOD
0
tSOTD
tSOTX
SPI PORT
fSCLK
tCCPL
tCCPH
tCLS
tCLH
tCLPH
tCDS
tCDH
tCOD
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
6.25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
SCLK frequency
SCLK pulse width low
SCLK pulse width high
SS setup; time to SCLK rising
SS hold; time from SCLK rising
SS pulse width high
MOSI setup; time to SCLK rising
MOSI hold; time from SCLK rising
MISO delay; time from SCLK falling
80
80
5
100
80
10
10
101
400
kHz
µs
µs
SCL frequency
SCL high
SCL low
0.6
1.3
0.6
µs
SCL rise setup time (to SDA falling), relevant for repeated start
condition
tSCR
tSCH
tDS
tSCF
tSDF
tBFT
250
ns
µs
ns
ns
ns
µs
SCL and SDA rise time, CLOAD = 400 pF
SCL fall hold time (from SDA falling), relevant for start condition
SDA setup time (to SCL rising)
SCL fall time; CLOAD = 400 pF
SDA fall time; CLOAD = 400 pF
0.6
100
250
250
0.6
SCL rise setup time (to SDA rising), relevant for stop condition
I2C EEPROM SELF-BOOT
tSCHE
26 × tMP – 70
38 × tMP – 70
ns
ns
SCL fall hold time (from SDA falling), relevant for start condition; tMP
is the input clock on the MCLKIN pin
SCL rise setup time (to SDA falling), relevant for repeated start
condition
tSCSE
tBFTE
tDSE
tBHTE
70 × tMP – 70
6 × tMP – 70
32 × tMP
ns
ns
ns
SCL rise setup time (to SDA rising), relevant for stop condition
Delay from SCL falling to SDA changing
SDA rising in self-boot stop condition to SDA falling edge for
external master start condition
MULTIPURPOSE AND POWER-
DOWN PINS
tGIL
1.5 × 1/fS
µs
ns
MPx input latency; time until high or low value is read by core
PD low pulse width
tRLPW
20
Rev. C | Page 10 of 116
Data Sheet
ADAU1772
Limit
TMAX
Parameter
TMIN
Unit
Description
DIGITAL MICROPHONE
tCF
tCR
tDS
tDE
20
20
ns
ns
Digital microphone clock fall time
Digital microphone clock rise time
Digital microphone valid data start time
Digital microphone valid data end time
40
0
ns
PDM OUTPUT
tDCF
tDCR
tDDV
20
20
30
ns
ns
ns
PDM clock fall time
PDM clock rise time
PDM delay time for valid data
0
Digital Timing Diagrams
tBH
BCLK
tBL
tLS
tLH
LRCLK
tSS
DAC_SDATA
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
tSH
tSS
DAC_SDATA
I S MODE
2
MSB
tSH
tSS
tSS
DAC_SDATA
RIGHT-JUSTIFIED
MODE
LSB
MSB
tSH
tSH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Input Port Timing
Rev. C | Page 11 of 116
ADAU1772
Data Sheet
tLH
tBH
tTS
BCLK
tBL
tLS
LRCLK
tSOD
ADC_SDATAx
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
tSOD
ADC_SDATAx
2
I S MODE
MSB
tSOTX
tSOTD
ADC_SDATAx
W/TRISTATE
HIGH-Z
HIGH-Z
MSB
LSB
tSOD
ADC_SDATAx
RIGHT-JUSTIFIED
MODE
LSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 3. Serial Output Port Timing
tCLS
tCLH
tCLPH
tCCPL
tCCPH
SS
SCLK
MOSI
tCDH
tCDS
MISO
tCOD
Figure 4. SPI Port Timing
tDS
tSCH
tSCH
SDA
SCL
tSCR
tSCLH
tSCS
tBFT
tSCLL tSCF
Figure 5. I2C Port Timing
Rev. C | Page 12 of 116
Data Sheet
ADAU1772
tSCHE
tDSE
SDA
SCL
tBHTE
tSCSE
tBFTE
Figure 6. I2C Self-Boot Timing
CLKOUT
tCF
tCR
tDS
tDS
tDE
tDE
DMIC0_1/DMIC2_3
VALID LEFT SAMPLE
VALID RIGHT SAMPLE
VALID LEFT SAMPLE
Figure 7. Digital Microphone Timing
tDCF
tDCR
CLKOUT
tDDV
tDDV
PDMOUT
RIGHT
LEFT
RIGHT
LEFT
Figure 8. PDM Output Timing
Rev. C | Page 13 of 116
ADAU1772
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
θJA represents the junction-to-ambient thermal resistance; θJC
represents the junction-to-case thermal resistance. Thermal
numbers are simulated on a 4-layer JEDEC PCB with the
exposed pad soldered to the PCB. θJC was simulated at the
exposed pad on the bottom of the package.
Parameter
Rating
Power Supply (AVDD, IOVDD)
Digital Supply (DVDD)
−0.3 V to +3.63 V
−0.3 V to +1.98 V
20 mA
–0.3 V to AVDD + 0.3 V
−0.3 to IOVDD + 0.3 V
−40°C to +85°C
−65°C to +150°C
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Case)
Storage Temperature Range
Table 9. Thermal Resistance
Package Type
θJA
θJC
Unit
40-Lead LFCSP
29
1.8
°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. C | Page 14 of 116
Data Sheet
ADAU1772
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SDA/MISO
SCL/SCLK
ADDR1/MOSI
ADDR0/SS
SELFBOOT
MICBIAS0
MICBIAS1
AIN0REF
1
2
3
4
5
6
7
8
9
30 DGND
29 DVDD
28 REG_OUT
27 PD
26 HPOUTRP/LOUTRP
25 HPOUTRN/LOUTRN
24 AVDD
23 AGND
22 HPOUTLP/LOUTLP
21 HPOUTLN/LOUTLN
ADAU1772
TOP VIEW
(Not to Scale)
AIN0
AVDD 10
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1772
GROUNDS. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD
BE SOLDERED TO THE GROUND PLANE. SEE THE EXPOSED PAD PCB
DESIGN SECTION FOR MORE INFORMATION.
Figure 9. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
SDA/MISO
D_IO
I2C Data (SDA). This pin is a bidirectional open-collector. The line connected to this pin should have
a 2.0 kΩ pull-up resistor.
SPI Data Output (MISO). This SPI data output is used for reading back registers and memory locations.
It is tristated when an SPI read is not active.
2
SCL/SCLK
D_IN
I2C Clock (SCL). This pin is always an open-collector input when the device is in I2C control mode.
When the device is in self-boot mode, this pin is an open-collector output (I2C master). The line
connected to this pin should have a 2.0 kΩ pull-up resistor.
SPI Clock (SCLK). This pin can either run continuously or be gated off between SPI transactions.
3
4
ADDR1/MOSI
D_IN
D_IN
I2C Address 1 (ADDR1).
SPI Data Input (MOSI).
I2C Address 0 (ADDR0).
SS
ADDR0/
SS
SPI Latch Signal ( ). This pin must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction can take a different number of SCLK cycles to complete,
depending on the address and read/write bit that are sent at the beginning of the SPI transaction.
5
SELFBOOT
MICBIAS0
MICBIAS1
AIN0REF
AIN0
D_IN
A_OUT
A_OUT
A_IN
Self-Boot. Pull this pin up to IOVDD at power-up to enable the self-boot mode.
Bias Voltage for Electret Microphone. Decouple with a 1 µF capacitor.
Bias Voltage for Electret Microphone. Decouple with a 1 µF capacitor.
ADC0 Input Reference. This reference pin should be ac-coupled to ground with a 10 µF capacitor.
ADC0 Input.
6
7
8
9
A_IN
10
11
AVDD
PWR
1.8 V to 3.3 V Analog Supply. This pin should be decoupled to AGND with a 0.1 μF capacitor.
AGND
PWR
Analog Ground. The AGND and DGND pins can be tied directly together in a common ground plane.
AGND should be decoupled to AVDD with a 0.1 μF capacitor.
12
CM
A_OUT
AVDD/2 V Common-Mode Reference. A 10 μF to 47 μF decoupling capacitor should be connected
between this pin and ground to reduce crosstalk between the ADCs and DACs. The material of the
capacitors is not critical. This pin can be used to bias external analog circuits, as long as they are
not drawing current from CM (for example, the noninverting input of an op amp).
Rev. C | Page 15 of 116
ADAU1772
Data Sheet
Pin No.
13
Mnemonic
Type1
A_IN
A_IN
A_IN
A_IN
A_IN
A_IN
PWR
Description
AIN1REF
AIN1
ADC1 Input Reference. This reference pin should be ac-coupled to ground with a 10 µF capacitor.
14
ADC1 Input.
15
AIN2REF
AIN2
ADC2 Input Reference. This reference pin should be ac-coupled to ground with a 10 µF capacitor.
16
ADC2 Input.
17
AIN3REF
AIN3
ADC3 Input Reference. This reference pin should be ac-coupled to ground with a 10 µF capacitor.
ADC3 Input.
18
19
AVDD
1.8 V to 3.3 V Analog Supply. This pin should be decoupled to AGND with a 0.1 μF capacitor.
Analog Ground.
20
AGND
PWR
21
HPOUTLN/LOUTLN
A_OUT
Left Headphone Inverted (HPOUTLN).
Line Output Inverted (LOUTLN).
22
HPOUTLP/LOUTLP
A_OUT
Left Headphone Noninverted (HPOUTLP).
Line Output Noninverted, Single-Ended Line Output (LOUTLP).
Headphone Amplifier Ground.
23
24
AGND
AVDD
PWR
PWR
Headphone Amplifier Power, 1.8 V to 3.3 V Analog Supply. This pin should be decoupled to AGND
with a 0.1 μF capacitor. The PCB trace to this pin should be wider to supply the higher current necessary
for driving the headphone outputs.
25
26
27
HPOUTRN/LOUTRN
HPOUTRP/LOUTRP
PD
A_OUT
A_OUT
D_IN
Right Headphone Inverted (HPOUTRN).
Line Output Inverted (LOUTRN).
Right Headphone Noninverted (HPOUTRP).
Line Output Noninverted, Single-Ended Line Output (LOUTRP).
Active Low Power-Down. All digital and analog circuits are powered down. There is an internal
pull-down resistor on this pin; therefore, the ADAU1772 is held in power-down mode if its input
signal is floating while power is applied to the supply pins.
28
29
REG_OUT
DVDD
A_OUT
PWR
Regulator Output Voltage. This pin should be connected to DVDD if the internal voltage regulator
is being used to generate DVDD voltage.
Digital Core Supply. The digital supply can be generated from an on-board regulator or supplied
directly from an external supply. In each case, DVDD should be decoupled to DGND with a 0.1 μF
capacitor.
30
31
DGND
PWR
D_IO
Digital Ground. The AGND and DGND pins can be tied directly together in a common ground plane.
Serial Data Port Frame Clock (LRCLK).
LRCLK/MP3
General-Purpose Input (MP3).
32
33
34
BCLK/MP2
D_IO
D_IO
D_IO
Serial Data Port Bit Clock (BCLK).
General-Purpose Input (MP2).
DAC_SDATA/MP0
ADC_SDATA0/PDMOUT/MP1
DAC Serial Input Data (DAC_SDATA).
General-Purpose Input (MP0).
ADC Serial Data Output 0 (ADC_SDATA0).
Stereo PDM Output to Drive a High Efficiency Class-D Amplifier (PDMOUT).
General-Purpose Input (MP1).
35
ADC_SDATA1/CLKOUT/MP6
D_IO
Serial Data Output 1 (ADC_SDATA1).
Master Clock Output/Clock for the Digital Microphone Input and PDM Output (CLKOUT).
General-Purpose Input (MP6).
36
37
DMIC2_3/MP5
DMIC0_1/MP4
D_IN
D_IN
Digital Microphone Stereo Input 2 and Digital Microphone Stereo Input 3 (DMIC2_3).
General-Purpose Input (MP5).
Digital Microphone Stereo Input 0 and Digital Microphone Stereo Input 1 (DMIC0_1).
General-Purpose Input (MP4).
38
39
XTALO
A_OUT
D_IN
Crystal Clock Output. This pin is the output of the crystal amplifier and should not be used to
provide a clock to other ICs in the system. If a master clock output is needed, use CLKOUT (Pin 35).
XTALI/MCLKIN
Crystal Clock Input (XTALI).
Master Clock Input (MCLKIN)
40
IOVDD
PWR
Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD, and this
sets the highest input voltage that should be seen on the digital input pins. The current draw of
this pin is variable because it is dependent on the loads of the digital outputs. IOVDD should be
decoupled to DGND with a 0.1 μF capacitor.
EP
Exposed Pad. The exposed pad is connected internally to the ADAU1772 grounds. For increased
reliability of the solder joints and maximum thermal capability, it is recommended that the pad be
soldered to the ground plane. See the Exposed Pad PCB Design section for more information.
1 D_IO = digital input/output, D_IN = digital input, A_OUT = analog output, A_IN = analog input, PWR = power, A_IN = analog input.
Rev. C | Page 16 of 116
Data Sheet
ADAU1772
TYPICAL PERFORMANCE CHARACTERISTICS
0.04
0.02
120
110
100
90
80
70
60
50
40
30
20
10
0
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.16
–0.18
–0.20
–0.22
–0.24
100
1k
10k
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 10. Relative Level vs. Frequency,
Figure 13. Group Delay vs. Frequency,
fS = 48 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
fS = 48 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
40
20
6
4
2
0
–2
–4
–6
–8
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
–220
–240
–260
–280
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 14. Phase vs. Frequency, 2 kHz Bandwidth,
Figure 11. Phase vs. Frequency, 20 kHz Bandwidth,
fS = 48 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
fS = 48 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
0.2
0.1
120
110
100
90
80
70
60
50
40
30
20
10
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–1.1
–1.2
–1.3
100
1k
10k
0
4
8
12
16
20
24
28
32
36
40
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 12. Relative Level vs. Frequency,
fS = 96 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
Figure 15. Group Delay vs. Frequency,
fS = 96 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
Rev. C | Page 17 of 116
ADAU1772
Data Sheet
50
0
6
4
2
–50
0
–2
–4
–6
–8
–100
–150
–200
–250
–300
–350
–400
–450
–500
–550
–600
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
4
8
12
16
20
24
28
32
36
40
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 19. Phase vs. Frequency, 2 kHz Bandwidth,
Figure 16. Phase vs. Frequency, 40 kHz Bandwidth,
fS = 96 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
fS = 96 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
1
0
120
110
100
90
80
70
60
50
40
30
20
10
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
100
1k
10k
0
10
20
30
40
50
60
70
80
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 17. Relative Level vs. Frequency,
Figure 20. Group Delay vs. Frequency,
fS = 192 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
fS = 192 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
200
100
6
4
2
0
0
–100
–200
–300
–400
–500
–600
–700
–800
–900
–1000
–1100
–1200
–1300
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
10
20
30
40
50
60
70
80
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 21. Phase vs. Frequency, 2 kHz Bandwidth,
fS = 192 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
Figure 18. Phase vs. Frequency, 80 kHz Bandwidth,
fS = 192 kHz, Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
Rev. C | Page 18 of 116
Data Sheet
ADAU1772
0.04
0.02
300
280
260
240
220
200
180
160
140
120
100
80
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.16
–0.18
–0.20
60
40
20
0
100
1k
10k
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 22. Relative Level vs. Frequency,
fS = 48 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
Figure 25. Group Delay vs. Frequency,
fS = 48 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
10
0
200
100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–100
–200
–300
–400
–500
–600
–700
–800
–900
–1000
–1100
–1200
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 23. Phase vs. Frequency, 20 kHz Bandwidth,
fS = 48 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
Figure 26. Phase vs. Frequency, 2 kHz Bandwidth,
fS = 48 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
0.4
0.2
300
280
260
240
220
200
180
160
140
120
100
80
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
–2.2
60
40
20
0
100
1k
10k
0
4
8
12
16
20
24
28
32
36
40
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 24. Relative Level vs. Frequency,
fS = 96 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
Figure 27. Group Delay vs. Frequency,
fS = 96 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
Rev. C | Page 19 of 116
ADAU1772
Data Sheet
200
100
10
5
0
0
–100
–200
–300
–400
–500
–600
–700
–800
–900
–1000
–1100
–1200
–1300
–1400
–1500
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
4
8
12
16
20
24
28
32
36
40
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 31. Phase vs. Frequency, 2 kHz Bandwidth,
fS = 96 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
Figure 28. Phase vs. Frequency, 40 kHz Bandwidth,
fS = 96 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
2
0
300
280
260
240
220
200
180
160
140
120
100
80
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
–22
60
40
20
0
100
1k
10k
0
10
20
30
40
50
60
70
80
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 29. Relative Level vs. Frequency,
fS = 192 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
Figure 32. Group Delay vs. Frequency,
fS = 192 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
200
10
0
–200
5
0
–5
–400
–10
–15
–20
–25
–30
–35
–40
–600
–800
–1000
–1200
–1400
–1600
–1800
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
10
20
30
40
50
60
70
80
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 30. Phase vs. Frequency, 80 kHz Bandwidth,
fS = 192 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
Figure 33. Phase vs. Frequency, 2 kHz Bandwidth,
fS = 192 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
Rev. C | Page 20 of 116
Data Sheet
ADAU1772
0.02
0.01
300
280
260
240
220
200
180
160
140
120
100
80
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.10
60
40
20
0
100
1k
10k
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 34. Relative Level vs. Frequency,
fS = 48 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
Figure 37. Group Delay vs. Frequency,
fS = 48 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
200
10
100
0
0
–10
–100
–200
–300
–400
–500
–600
–700
–800
–900
–1000
–1100
–1200
–1300
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 38. Phase vs. Frequency, 2 kHz Bandwidth,
fS = 48 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
Figure 35. Phase vs. Frequency, 20 kHz Bandwidth,
fS = 48 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
0.2
300
280
260
240
220
200
180
160
140
120
100
80
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
60
40
20
0
100
1k
10k
0
4
8
12
16
20
24
28
32
36
40
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 36. Relative Level vs. Frequency,
fS = 96 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
Figure 39. Group Delay vs. Frequency,
fS = 96 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
Rev. C | Page 21 of 116
ADAU1772
Data Sheet
200
100
10
5
0
0
–100
–200
–300
–400
–500
–600
–700
–800
–900
–1000
–1100
–1200
–1300
–1400
–1500
–1600
–1700
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
4
8
12
16
20
24
28
32
36
40
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 43. Phase vs. Frequency, 2 kHz Bandwidth,
fS = 96 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
Figure 40. Phase vs. Frequency, 40 kHz Bandwidth,
fS = 96 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
1.0
300
0.5
0
280
260
240
220
200
180
160
140
120
100
80
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
60
40
20
0
100
1k
10k
0
10
20
30
40
50
60
70
80
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 41. Relative Level vs. Frequency,
fS = 192 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
Figure 44. Group Delay vs. Frequency,
fS = 192 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
200
10
0
–200
5
0
–400
–5
–600
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–800
–1000
–1200
–1400
–1600
–1800
–2000
–2200
–2400
–2600
–2800
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
10
20
30
40
50
60
70
80
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 45. Phase vs. Frequency, 2 kHz Bandwidth,
fS = 192 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
Figure 42. Phase vs. Frequency, 80 kHz Bandwidth,
fS = 192 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
Rev. C | Page 22 of 116
Data Sheet
ADAU1772
0.020
0.015
500
450
400
350
300
250
200
150
100
50
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
–0.025
–0.030
–0.035
–0.040
–0.045
–0.050
0
100
1k
10k
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 46. Relative Level vs. Frequency,
Figure 49. Group Delay vs. Frequency,
fS = 48 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing)
to ASRC to ADC_SDATA0
fS = 48 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing)
to ASRC to ADC_SDATA0
200
100
0
10
0
–10
–100
–200
–300
–400
–500
–600
–700
–800
–900
–1000
–1100
–1200
–1300
–1400
–1500
–1600
–1700
–1800
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 50. Phase vs. Frequency, 2 kHz Bandwidth,
Figure 47. Phase vs. Frequency, 20 kHz Bandwidth,
fS = 48 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing)
to ASRC to ADC_SDATA0
fS = 48 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing)
to ASRC to ADC_SDATA0
0.4
0.2
500
450
400
350
300
250
200
150
100
50
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
0
100
1k
10k
0
4
8
12
16
20
24
28
32
36
40
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 48. Relative Level vs. Frequency,
fS = 96 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing)
to ASRC to ADC_SDATA0
Figure 51. Group Delay vs. Frequency,
fS = 96 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing)
to ASRC to ADC_SDATA0
Rev. C | Page 23 of 116
ADAU1772
Data Sheet
10
5
0
200
0
–5
–200
–400
–600
–800
–1000
–1200
–1400
–1600
–1800
–2000
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
4
8
12
16
20
24
28
32
36
40
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 52. Phase vs. Frequency, 40 kHz Bandwidth,
Figure 55. Phase vs. Frequency, 2 kHz Bandwidth,
fS = 96 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing)
to ASRC to ADC_SDATA0
fS = 96 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing)
to ASRC to ADC_SDATA0
2
0
500
450
400
350
300
250
200
150
100
50
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
–22
0
100
1k
10k
0
10
20
30
40
50
60
70
80
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 53. Relative Level vs. Frequency,
fS = 192 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing)
to ASRC to ADC_SDATA0
Figure 56. Group Delay vs. Frequency,
fS = 192 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing)
to ASRC to ADC_SDATA0
10
5
200
0
0
–200
–400
–600
–800
–1000
–1200
–1400
–1600
–1800
–2000
–2200
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
10
20
30
40
50
60
70
80
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 57. Phase vs. Frequency, 2 kHz Bandwidth,
fS = 192 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing)
to ASRC to ADC_SDATA0
Figure 54. Phase vs. Frequency, 80 kHz Bandwidth,
fS = 192 kHz, Signal Path = DAC_SDATA to ASRC to DSP (Without Processing)
to ASRC to ADC_SDATA0
Rev. C | Page 24 of 116
Data Sheet
ADAU1772
35
30
25
20
15
10
5
2
0
–2
–4
–6
–8
–10
0
–12
–6
0
6
12
18
24
30
36
0
5
10
15
20
FREQUENCY (kHz)
PGA GAIN SETTING (dB)
Figure 58. Input Impedance vs. PGA Gain
(see the Input Impedance section)
Figure 61. Decimation Pass-Band Response, fS = 192 kHz
2
0
0
–20
–2
–40
–60
–4
–6
–80
–100
–120
–8
–10
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 59. Decimation Pass-Band Response, fS = 96 kHz
Figure 62. Total Decimation Response, Core fs = 192 kHz,
Serial Port fS = 48 kHz
2
1
0
0
–20
–40
–1
–60
–2
–3
–4
–80
–100
–120
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 60. Total Decimation Response, Core fS = 96 kHz,
Serial Port fS = 48 kHz
Figure 63. Interpolation Pass-Band Response,
fS = 96 kHz
Rev. C | Page 25 of 116
ADAU1772
Data Sheet
3
0
–20
2
1
–40
0
–60
–1
–2
–3
–80
–100
–120
0
20
40
60
80
100
120
140
0
5
10
15
25
30
35
40
45
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 64. Decimation Pass-Band Response, Core fS = 96 kHz,
Serial Port fS = 96 kHz
Figure 67. Total Decimation Response, Core fS = 96 kHz,
Serial Port fS = 192 kHz
3
0
2
1
–20
–40
–60
0
–80
–1
–2
–3
–100
–120
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
25
30
35
40
45
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 65. Total Decimation Response, Core fS = 96 kHz,
Serial Port fS = 96 kHz
Figure 68. Decimation Pass-Band Response, Core fS = 192 kHz,
Serial Port fS = 96 kHz
10
0
8
6
–20
4
–40
–60
2
0
–2
–4
–6
–8
–10
–80
–100
–120
0
10
20
30
40
50
60
80
90
100
0
10
20
30
40
50
60
70
80
90
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 66. Decimation Pass-Band Response, Core fS = 96 kHz,
Serial Port fS = 192 kHz
Figure 69. Total Decimation Response, Core fS = 192 kHz,
Serial Port fS = 96 kHz
Rev. C | Page 26 of 116
Data Sheet
ADAU1772
2
1
10
8
6
4
0
2
0
–1
–2
–3
–4
–2
–4
–6
–8
–10
0
10
20
30
40
50
60
70
80
90
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 70. Decimation Pass-Band Response, Core fS = 192 kHz,
Serial Port fS = 192 kHz
Figure 73. Interpolation Pass-Band Response, fS = 192 kHz
0
0
–20
–20
–40
–60
–40
–60
–80
–80
–100
–120
–100
–120
0
20
40
60
80
100
120
140
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 71. Total Decimation Response, Core fS = 192 kHz,
Serial Port fS = 192 kHz
Figure 74. Total Interpolation Response, fS = 192 kHz
0
–20
–40
–60
–80
–100
–120
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (kHz)
Figure 72. Total Interpolation Response, fS = 96 kHz
Rev. C | Page 27 of 116
ADAU1772
Data Sheet
SYSTEM BLOCK DIAGRAMS
DC VOLTAGE SOURCE:
1.8 V TO 3.3 V
+
10µF
0.10µF
0.10µF
0.10µF
0.10µF
+
10µF
0.10µF
22
21
37
36
1.0µF
DMIC0_1/MP4
DMIC2_3/MP5
HPOUTLP/LOUTLP
LEFT HEADPHONE
2kΩ 2kΩ
LEFT
MICROPHONE
HPOUTLN/LOUTLN
HPOUTRP/LOUTRP
HPOUTRN/LOUTRN
6
7
MICBIAS0
MICBIAS1
26
25
RIGHT HEADPHONE
EEPROM
9
8
AIN0
47µF
AIN0REF
ADAU1772
1
2
3
SDA/MISO
SCL/SCLK
ADDR1/MOSI
14
13
AIN1
47µF
4
5
AIN1REF
ADDR0/SS
SELFBOOT
LEFT_AUDIO
16
15
AIN2
10µF
RIGHT
31
32
33
34
35
AIN2REF
LRCLK/MP3
BCLK/MP2
DAC_SDATA/MP0
MICROPHONE
RIGHT_AUDIO
CONTROL INTERFACE:
SWITCHES AND
POTENTIOMETERS
18
17
AIN3
ADC_SDATA0/PDMOUT/MP1
ADC_SDATA1/CLKOUT/MP6
10µF
AIN3REF
38
39
XTALO
27
12
PD
100Ω
22pF
XTALI/MCLKIN
CM
+
10µF
0.10µF
22pF
Figure 75. ADAU1772 System Block Diagram with Analog Microphones, Self-Boot Mode
Rev. C | Page 28 of 116
Data Sheet
ADAU1772
THEORY OF OPERATION
The ADAU1772 is a low power audio codec with an optimized
audio processing core, making it ideal for noise cancelling
applications that require high quality audio, low power, small
size, and low latency. The four ADC and two DAC channels
each have an SNR of at least +96 dB and a THD + N of at least
−88 dB. The serial data port is compatible with I2S, left justified,
right justified, and TDM modes, with tristating for interfacing
to digital audio data. The operating voltage range is 1.8 V to
3.63 V, w it h a n on -board regulator generating the internal
digital supply voltage. If desired, the regulator can be powered
down and the voltage can be supplied externally.
control individual signal processing blocks. The ADAU1772 also
has a self-boot function that can be used to load the program
and parameter RAM along with the register settings on power-
up using an external EEPROM.
The SigmaStudio software is used to program and control the core
through the control port. Along with designing and tuning a signal
flow, the tools can be used to configure all of the ADAU1772
registers. The SigmaStudio graphical interface allows anyone with
digital or analog audio processing knowledge to easily design the
DSP signal flow and port it to a target application. The interface
also provides enough flexibility and programmability for an
experienced DSP programmer to have in-depth control of the
design. In SigmaStudio, the user can connect graphical blocks
(such as biquad filters, volume controls, and arithmetic operations),
compile the design, and load the program and parameter files into
the ADAU1772 memory through the control port. SigmaStudio
also allows the user to download the design to an external EEPROM
for self-boot operation. Signal processing blocks available in the
provided libraries include the following:
The input signal path includes flexible configurations that can
accept single-ended analog microphone inputs as well as up to
four digital microphone inputs. Two microphone bias pins provide
seamless interfacing to electret microphones. Each input signal
has its own programmable gain amplifier (PGA) for volume
adjustment.
The ADCs and DACs are high quality, 24-bit Σ-Δ converters
that operate at a selectable 192 kHz or 96 kHz sampling rate.
The ADCs have an optional high-pass filter with a cutoff
frequency of 1 Hz, 4 Hz, or 8 Hz. The ADCs and DACs also
include very fine-step digital volume controls.
•
•
•
•
•
Single-precision biquad filters
Second order filters
Absolute value and two-input adder
Volume controls
The stereo DAC output is capable of differentially driving a
headphone earpiece speaker with 16 Ω impedance or higher.
One side of the differential output can be powered down if
single-ended operation is required. There is also the option to
change to line output mode when the output is lightly loaded.
Limiter
The ADAU1772 can generate its internal clocks from a wide range
of input clocks by using the on-board fractional PLL. The PLL
accepts inputs from 8 MHz to 27 MHz. For standalone operation,
the clock can be generated using the on-board crystal oscillator.
The core has a reduced instruction set that optimizes this codec
for noise cancellation. The program and parameter RAMs can
be loaded with custom audio processing signal flow built using
the SigmaStudio™ graphical programming software from
Analog Devices, Inc. The values stored in the parameter RAM
The ADAU1772 is provided in a small, 40-lead, 6 mm × 6 mm
LFCSP with an exposed bottom pad.
Rev. C | Page 29 of 116
ADAU1772
Data Sheet
SYSTEM CLOCKING AND POWER-UP
CLOCK INITIALIZATION
Control Port Access During Initialization
During the lock acquisition period, only Register 0x0000 to
Register 0x0006 are accessible through the control port. A read
or write to any other register is prohibited until the core clock
enable bit and the lock bit are both asserted.
The ADAU1772 can generate its clocks either from an externally
provided clock or from a crystal oscillator. In both cases, the on-
board PLL can be used or the clock can be fed directly to the
core. When a crystal oscillator is used, it is desirable to use a
12.288 MHz crystal, and the crystal oscillator function must be
enabled in the COREN bit (Address 0x0000). If the PLL is used,
it should always be set to output 24.576 MHz. The PLL can be
bypassed if a clock of 12.288 MHz or 24.576 MHz is available in
the system. Bypassing the PLL saves system power.
After the CORE_RUN bit (Address 0x0009) is set high, the
DAC_SOURCE0 and DAC_SOURCE1 register bits should not
be changed. If these bits must be changed after the ADAU1772
is running, the CORE_RUN bit first must be disabled.
PLL
The CC_MDIV and CC_CDIV bits should not be changed after
setup, but the CLKSRC bit can be switched while the core is
running.
The PLL uses the MCLKIN signal as a reference to generate
the core clock. The PLL settings are set in Register 0x0000 to
Register 0x0005. Depending on the MCLK frequency, the PLL
must be set for either integer or fractional mode. The PLL can
accept input frequencies in the range of 8 MHz to 27 MHz.
The CC_MDIV and CC_CDIV bits should be set so that the core
and internal master clock are always 12.288 MHz; for example,
when using a 24.576 MHz external source clock or if using the
PLL, it is necessary to use the internal divide by 2 (see Table 11).
TO PLL
CLOCK DIVIDER
MCLK
÷X
× (R + N/M)
Figure 76. PLL Block Diagram
Table 11. Clock Configuration Settings
CC_MDIV
CC_CDIV
Description
Input Clock Divider
1
1
Divide PLL/external clock by 1. Use these
settings for a 12.288 MHz direct input clock
source.
Before reaching the PLL, the input clock signal goes through an
integer clock divider to ensure that the clock frequency is within
a suitable range for the PLL. The X bits in the PLL_CTRL4 register
(Bits[2:1], Address 0x0005) sets the PLL input clock divide ratio.
0
0
Divide PLL/external clock by 2. Use these
settings for a 24.576 MHz direct input clock
source or if using the PLL.
Integer Mode
PLL Bypass Setup
Integer mode is used when the clock input is an integer multiple
of the PLL output.
On power up, the ADAU1772 comes out of an internal reset
after 12 ms. The rate of the internal master clock must be set
properly using the CC_MDIV bit in the clock control register
(Address 0x0000). When bypassing the PLL, the clock associated
with MCLKIN must be either 12.288 MHz or 24.576 MHz. The
internal master clock of the ADAU1772 is disabled until the
COREN bit is asserted.
For example, if MCLKIN = 12.288 MHz and (X + 1) = 1, and
fS = 48 kHz, then
PLL Required Output = 24.576 MHz
R/2 = 24.576 MHz/12.288 MHz = 2
where R/2 = 2 or R = 4.
PLL Enabled Setup
In integer mode, the values set for N and M are ignored.
Table 12 lists common integer PLL parameter settings for
48 kHz sampling rates.
The core clock of the ADAU1772 is disabled by the default
setting of Bit COREN and should remain disabled during the
PLL lock acquisition period. The user can poll the LOCK bit to
determine when the PLL has locked. After lock is acquired, the
ADAU1772 can be started by asserting the COREN bit. This bit
enables the core clock for all the internal blocks of the ADAU1772.
Fractional Mode
Fractional mode is used when the clock input is a fractional
multiple of the PLL output.
For example, if MCLKIN = 13 MHz, (X + 1) = 1, and
fS = 48 kHz, then
To program the PLL during initialization or reconfiguration of
the codec, the following procedure must be followed:
PLL Required Output = 24.576 MHz
1. Ensure that PLL_EN (Bit 7, Address 0x0000) is set low.
2. Set/reset the PLL control registers (Address 0x0001 to
Address 0x0005).
(1/2) × (R + (N/M)) = 24.576 MHz/13 MHz = (1/2) × (3 +
(1269/1625))
3. Enable the PLL using the PLL_EN bit.
4. Poll the PLL lock bit in Register 0x0006.
5. Set the COREN bit in Register 0x0000 after PLL lock is
acquired.
where:
R = 3.
N = 1269.
M = 1625.
Rev. C | Page 30 of 116
Data Sheet
ADAU1772
Table 13 lists common fractional PLL parameter settings for
48 kHz sampling rates. When the PLL is used in fractional
mode, it is very important that the N/M fraction be kept in
the range of 0.1 to 0.9 to ensure correct operation of the PLL.
On power-up, AVDD must be powered up before or at the same
time as IOVDD. IOVDD should not be powered up when power is
not applied to AVDD.
Enabling the
pin powers down all analog and digital circuits.
PD
The PLL can output a clock in the range of 20.5 MHz to 27 MHz,
which should be taken into account when calculating PLL values
and MCLK frequencies.
Before enabling
(that is, setting it low), be sure to mute the
PD
outputs to avoid any pops when the IC is powered down.
can be tied directly to IOVDD for normal operation.
PD
CLOCK OUTPUT
Power-Down Considerations
The CLKOUT pin can be used as a master clock output to clock
other ICs in the system or as the clock for the digital microphone
inputs and PDM output. This clock can be generated from the
12.288 MHz master clock of the ADAU1772 by factors of 2, 1,
½, ¼, and ⅛. If PDM mode is enabled, only ½, ¼, and ⅛ settings
produce a clock signal on CLKOUT. The factor of 2 multiplier
works properly only if the input clock was previously divided by
2 using the CC_MDIV bit.
When powering down the ADAU1772, be sure to mute the outputs
before AVDD power is removed; otherwise, pops or clicks may
be heard. The easiest way to achieve this is to use a regulator that
has a power good (PGOOD) signal to power the ADAU1772 or
generate a power good signal using additional circuitry external
to the regulator itself. Typically, on such regulators the power good
signal changes state when the regulated voltage drops below ~90%
of its target value. This power good signal can be connected to one
of the ADAU1772 multipurpose pins and used to mute the DAC
outputs by setting the multipurpose pin functionality to mute
both DACs in Register 0x0038 to Register 0x003E. This ensures
that the outputs are muted before power is completely removed.
POWER SEQUENCING
AVDD and IOVDD can each be set to any voltage between 1.8 V
and 3.3 V, and DVDD can be set between 1.1 V and 1.8 V or
between 1.1 V and 1.2 V if using the on-board regulator.
Table 12. Integer PLL Parameter Settings for PLL Output = 24.576 MHz
Input Divider
(X + 1)
PLL_CTRL4 Settings
(Address 0x0005)
MCLK Input (MHz)
12.288
24.576
Integer (R)
Denominator (M)
Don’t care
Don’t care
Numerator (N)
Don’t care
Don’t care
1
1
4
2
0x20
0x10
Table 13. Fractional PLL Parameter Settings for PLL Output = 24.576 MHz
PLL_CTRL[4:0] Settings
(Address 0x0005 to Address 0x0001)
MCLK
Input
(MHz)
Input
Divider
(X + 1)
Integer
(R)
Denominator
(M)
Numerator
(N)
PLL_CTRL4 PLL_CTRL3 PLL_CTRL2 PLL_CTRL1 PLL_CTRL0
(0x0005)
(0x0004)
(0x0003)
(0x0002)
0x7D
0x59
(0x0001)
8
13
14.4
19.2
26
1
1
2
2
2
2
6
3
6
5
3
3
125
1625
75
25
1625
1125
18
1269
62
0x31
0x19
0x33
0x2B
0x1B
0x1B
0x12
0xF5
0x00
0x04
0x00
0x06
0x00
0x00
0x06
0x04
0x3E
0x00
0x4B
3
0x03
0x00
0x19
1269
721
0xF5
0x04
0x59
27
0xD1
0x02
0x65
Rev. C | Page 31 of 116
ADAU1772
Data Sheet
SIGNAL ROUTING
AIN0REF
PGA
ADC
MODULATOR
AIN0
ADC
DECIMATOR
AIN1REF
AIN1
PGA
HPOUTLP/LOUTLP
HPOUTLN/LOUTLN
ADC
MODULATOR
DAC
DAC
ADC
DECIMATOR
DAC
AND
HPOUTRP/LOUTRP
HPOUTRN/LOUTRN
CORE
INPUT
SELECTION
AUDIO
PROCESSING
CORE
DMIC0_1/MP4
DMIC2_3/MP5
DIGITAL
PDM
MICROPHONE
INPUTS
OUTPUT
SELECTION
AIN2REF
AIN2
ADC
DECIMATOR
STEREO PDM
MODULATOR
1
PDMOUT
PGA
ADC
MODULATOR
AIN3REF
AIN3
ADC
DECIMATOR
PGA
ADC
MODULATOR
STEREO INPUT
ASRC
SERIAL
INPUT PORT
DUAL STEREO
OUTPUT ASRCs
DAC_SDATA
1
ADC_SDATA0
SERIAL
OUTPUT PORT
ADC_SDATA1
1
THE ADC_SDATA0 AND PDMOUT FUNCTIONS SHARE A PHYSICAL PIN, SO ONLY ONE OF THESE FUNCTIONS CAN BE USED AT A TIME.
Figure 77. Input and Output Signal Routing
Rev. C | Page 32 of 116
Data Sheet
ADAU1772
INPUT SIGNAL PATHS
There are four input paths, from either an ADC or a digital
microphone, that can be routed to the core. The input sources
(ADC or digital microphone) must be configured in pairs (for
example, 0 and 1, 2 and 3), but each channel can be routed
individually. The core inputs can also be sourced from a stereo
input ASRC.
Analog Line Inputs
Line level signals can be input on the AINx pins of the analog
inputs. Figure 79 shows a single-ended line input using the
AINx pins. The AINxREF pins should be tied to CM. When using
single-ended line input, the PGA should be disabled using the
PGA_ENx bits, and the corresponding PGA pop suppression
bit should be disabled using the POP_SUPPRESS register
(Address 0x0029).
ANALOG INPUTS
The ADAU1772 can accept both line level and microphone inputs.
Each of the four analog input channels can be configured in a
single-ended mode or a single-ended with PGA mode. There
are also inputs for up to four digital microphones. The analog
inputs are biased at AVDD/2. Unused input pins should be
connected to the CM pin or ac-coupled to ground.
ADAU1772
LINE INPUT 0
LINE INPUT 1
LINE INPUT 2
LINE INPUT 3
AIN0
AIN1
AIN2
AIN3
Signal Polarity
Figure 79. Single-Ended Line Inputs
Signals routed through the PGAs are inverted. As a result, signals
input through the PGA are output from the ADCs with a polarity
that is opposite that of the input. Single-ended inputs are not
inverted. The ADCs are noninverting.
Precharging Input Capacitors
Precharge amplifiers are enabled by default to quickly charge
large series capacitors on the inputs and outputs. Precharging
these capacitors helps to prevent pops in the audio signal. The
precharge circuits are powered up by default on startup and can be
disabled in the POP_SUPPRESS register. The precharge amplifiers
are automatically disabled when the PGA or headphone amplifiers
are enabled. For unused PGAs and headphone outputs, these
precharge amplifiers should be disabled using the POP_SUPPRESS
register. The precharging time is dependent on the input/output
series capacitors. The impedance looking into the pin is 500 ꢀ
in this mode. However, at startup, the impedance looking into
the pin is dominated by the time constant of the CM pin because
the precharge amplifiers reference the CM voltage.
Input Impedance
The input impedance of the analog inputs varies with the gain of
the PGA. This impedance ranges from 0.68 kΩ at the 35.25 dB
gain setting to 32.0 kΩ at the −12 dB setting. The input impedance
on each pin can be calculated as follows:
40
RIN
kΩ
10(Gain/20) 1
where Gain is set by PGA_GAINx.
The optional 10 dB PGA boost set in PGA_x_BOOST does not
affect the input impedance. This is an alternative way of increasing
gain without decreasing input impedance; however, it causes some
degradation in performance.
Microphone Bias
The ADAU1772 includes two microphone bias outputs: MICBIAS0
and MICBIAS1. These pins provide a voltage reference for electret
analog microphones. The MICBIASx pins can also be used to
cleanly supply voltage to digital or analog MEMS microphones
with separate power supply pins. The MICBIASx voltage is set
in the microphone bias control register (Address 0x002D). Using
this register, either the MICBIAS0 or MICBIAS1 output can be
enabled and disabled. The gain options provide two possible
voltages: 0.65 × AVDD or 0.90 × AVDD.
Analog Microphone Inputs
For microphone signals, the ADAU1772 analog inputs can be
configured in single-ended with PGA mode.
The PGA settings are controlled in Register 0x0023 to Register
0x0026. The PGA is enabled by setting the PGA_ENx bits.
Connect the AINxREF pins to the CM pin and connect the
microphone signal to the inverting input of the PGAs (AINx),
as shown in Figure 78.
Many applications require enabling only one of the two bias
outputs. The two bias outputs should both be enabled when many
microphones are used in the system or when the positioning of
the microphones on the PCB does not allow one pin to bias all
microphones.
ADAU1772
PGA
AINx
MICROPHONE
AINxREF
–12dB TO
+35.25dB
CM
2kΩ
MICBIASx
Figure 78. Single-Ended Microphone Configuration
Rev. C | Page 33 of 116
ADAU1772
Data Sheet
Figure 80 shows two ADMP421 digital microphones connected
to Pin DMIC0_1 of the ADAU1772. These microphones could
also be connected to DMIC2_3 if that signal path is to be used for
digital microphones. If more than two digital microphones are to
be used in a system, then up to two microphones would be con-
nected to both DMIC0_ 1 and DMIC2_3 and the CLKOUT signal
would be fanned out to the clock input of all of the microphones.
DIGITAL MICROPHONE INPUT
When using a digital microphone connected to the DMIC0_1/MP4
and DMIC2_3/MP5 pins, the DCM_0_1 and DCM_2_3 bits in
Register 0x001D and Register 0x001E must be set to enable the
digital microphone signal paths. The pin functions should also
be set to digital microphone input in the corresponding pin
mode registers (Address 0x003C and Address 0x003D). The
DMIC0/DMIC2 and DMIC1/DMIC3 channels can be swapped
(left/right swap) by writing to the DMIC_SW0 and DMIC_SW1
bits in the ADC_CONTROL2 and ADC_CONTROL3 registers
(Address 0x001D and Address 0x001E). In addition, the micro-
phone polarity can be reversed by setting the DMIC_POLx bit,
which reverses the phase of the incoming audio by 180°.
ANALOG-TO-DIGITAL CONVERTERS
The ADAU1772 includes four 24-bit Σ-Δ analog-to-digital con-
verters (ADCs) with a selectable sample rate of 192 kHz or 96 kHz.
ADC Full-Scale Level
The full-scale input to the ADCs (0 dBFS) scales linearly with
AVDD. At AVDD = 3.3 V, t h e f u ll-scale input level is 1 V rms.
Signal levels above the full-scale value cause the ADCs to clip.
The digital microphone inputs are clocked from the CLKOUT pin.
The digital microphone data stream must be clocked by this pin
and not by a clock from another source, such as another audio
IC, even if the other clock is of the same frequency as CLKOUT.
Digital ADC Volume Control
The volume setting of each ADC can be digitally attenuated in the
ADCx_VOLUME registers (Address 0x001F to Address 0x0022).
The volume can be set between 0 dB and −95.625 dB in 0.375 dB
steps. The ADC volume can also be digitally muted in the
ADC_CONTROLx registers (Address 0x001B to Address 0x001E).
The digital microphone signal bypasses the analog input path
and the ADCs and is routed directly into the decimation filters.
The digital microphone and the ADCs share digital filters and,
therefore, both cannot be used simultaneously. The digital micro-
phone inputs are enabled in pairs. The ADAU1772 inputs can be
set for either four analog inputs, four digital microphone inputs, or
two analog inputs and two digital microphone inputs. Figure 80
depicts the digital microphone interface and signal routing.
1.8V TO 3.3V
High-Pass Filter
A high-pass filter is available on the ADC path to remove dc offsets;
this filter can be enabled or disabled using the HP_x_x_EN bits.
At fS = 192 kHz, the corner frequency of this high-pass filter can
be set to 1 Hz, 4 Hz, or 8 Hz.
CLK
ADAU1772
V
DATA
DD
0.1µF
ADMP421
L/R SELECT GND
CLKOUT
DMIC0_1
CLK
V
DATA
DD
0.1µF
ADMP421
L/R SELECT GND
Figure 80. Digital Microphone Interface Block Diagram
Rev. C | Page 34 of 116
Data Sheet
ADAU1772
OUTPUT SIGNAL PATHS
Data from the serial input port can be routed to the core either
directly or through a sample rate converter. Data can be routed
to the serial output port, the stereo DAC, and the stereo PDM
modulator.
Pop-and-Click Suppression
On power-up, the precharge circuitry is enabled on all four
analog output pins to suppress pops and clicks. After power-
up, the precharge circuitry can be put into a low power mode
using the HP_POP_DISx bits in the POP_SUPRRESS register
(Address 0x0029).
The analog outputs of the ADAU1772 can be configured as
differential or single-ended outputs. The analog output pins are
capable of driving headphone or earpiece speakers. The line
outputs can drive a load of at least 10 kΩ or can be put into
headphone mode to drive headphones or earpiece speakers. The
analog output pins are biased at AVDD/2.
The precharge time depends on the value of the capacitor
connected to the CM pin and the RC time constant of the load
on the output pin. For a typical line output load, the precharge
time is between 2 ms and 3 ms. After this precharge time, the
HP_POP_DISx bit can be set to low power mode.
ANALOG OUTPUTS
To avoid clicks and pops, all analog outputs that are in use should
be muted while changing any register settings that may affect the
signal path. These outputs can then be unmuted after the changes
have been made.
Headphone Output
The output pins can be driven by either a line output driver or a
headphone driver by setting the HP_EN_L and HP_EN_R bits
in the headphone line output select register (Address 0x0043).
The headphone outputs can drive a load of at least 16 Ω.
Line Outputs
The analog output pins (HPOUTLP/LOUTLP, HPOUTLN/
LOUTLN, HPOUTRP/LOUTRP, and HPOUTRN/LOUTRN)
can be used to drive both differential and single-ended loads. In
their default settings, these pins can drive typical line loads of
10 kΩ or greater.
Headphone Output Power-Up Sequencing
To prevent pops when turning on the headphone outputs, the
user must wait at least 6 ms to unmute these outputs after enabling
the headphone output using the HP_EN_x bits. Waiting 6 ms
allows an internal capacitor to charge before these outputs are
used. Figure 81 illustrates the headphone output power-up
sequencing.
When the line output pins are used in single-ended mode, the
HPOUTLP/LOUTLP and HPOUTRP/LOUTRP pins should be
used to output the signals, and the HPOUTLN/LOUTLN and
HPOUTRN/LOUTRN pins should be powered down.
USER
DEFINED
6ms
HP_EN_X
1 = HEADPHONE
DIGITAL-TO-ANALOG CONVERTERS
The ADAU1772 includes two 24-bit Σ-Δ digital-to-analog
converters (DACs).
HP_MUTE_R AND HP_MUTE_L
00 = UNMUTE
DAC Full-Scale Level
The full-scale output from the DACs (0 dBFS) scales linearly with
AVDD. At AVDD = 3.3 V, the full-scale output level is 1.94 V rms
for a differential output or 0.97 V rms for a single-ended output.
INTERNAL
PRECHARGE
Figure 81. Headphone Output Power-Up Timing
Ground-Centered Headphone Configuration
Digital DAC Volume Control
The headphone outputs can also be configured as ground-
centered outputs by connecting coupling capacitors in series
with the output pins. Ground-centered headphones should use
the AGND pin as the ground reference.
The volume of each DAC can be digitally attenuated using the
DACx_VOLUME registers (Address 0x002F and Address 0x0030).
The volume can be set to be between 0 dB and −95.625 dB in
0.375 dB steps.
When the headphone outputs are configured in this manner,
the capacitors create a high-pass filter on the outputs. The
corner frequency of this filter, which has an attenuation of 3 dB
at this point, is calculated by the following formula:
PDM OUTPUT
The ADAU1772 includes a 2-channel pulse density modulated
(PDM) modulator. The PDMOUT pin can be used to drive a PDM
input amplifier, such as the SSM2517 mono 2.4 W amplifier. Two
SSM2517 devices can be connected to the PDMOUT data stream
to enable a stereo output. The PDM output signal is clocked by the
CLKOUT pin output. The PDM output stream must be clocked
by this pin and not by a clock from another source, such as another
audio IC, even if the other clock is of the same frequency as
f
3dB = 1/(2π × R × C)
where :
R is the impedance of the headphones.
C is the capacitor value.
For a typical headphone impedance of 32 Ω and a 220 μF
capacitor, the corner frequency is 23 Hz.
CLKOUT. The PDM output data is clipped at the −6 dB level to
prevent overdriving a connected amplifier like the SSM2517.
Rev. C | Page 35 of 116
ADAU1772
Data Sheet
The ADAU1772 has the ability to output PDM control patterns to
configure devices such as the SSM2517. Each pattern is a byte long
and is written with a user defined pattern in the PDM_PATTERN
register (Address 0x0037). The control pattern is enabled and
the output channel selection is configured in the PDM_OUT
register (Address 0x0036). The PDM pattern should not be
changed while the ADAU1772 is outputting the control pattern
to the external device. After the external device is configured,
the control pattern can be disabled. For the SSM2517, the
control pattern must be repeated a minimum of 128 times to
configure the part. Table 14 describes typical control patterns
for the SSM2517.
The ASRCs can convert serial output data from the core rate of
up to 192 kHz back down to less than 8 kHz. All intermediate
frequencies and ratios are also supported.
SIGNAL LEVELS
The ADCs, DACs, and ASRCs have fixed gain settings that should
be considered when configuring the system. These settings were
chosen to maximize performance of the converters and to ensure
that there is 0 dB gain for any signal path from the input of the
ADAU1772 to its output. Therefore, the full-scale level of a signal
in the processing core will be slightly different from a full-scale
level external to the IC.
Input paths, such as through the ADCs and input ASRCs, are
scaled by 0.75, or about −2.5 dB. Output paths, such as through
the DACs or output ASRCs, are scaled by 1.33, or about 2.5 dB.
This is shown in Figure 82.
Table 14. SSM2517 PDM Control Pattern Descriptions
Pattern Control Description
0xAC
0xD8
0xD4
0xD2
Power-down. All blocks off except for the PDM
interface. Normal start-up time.
Gain optimized for PVDD = 5 V operation. Overrides
GAIN_FS pin setting.
Gain optimized for PVDD = 3.6 V operation. Overrides
GAIN_FS pin setting.
Gain optimized for PVDD = 2.5 V operation. Overrides
GAIN_FS pin setting.
ADC
CORE
DAC
–2.5dB
+2.5dB
0xD1
0xE1
0xE2
0xE4
fS set to opposite value determined by GAIN_FS pin.
Ultralow EMI mode.
Half clock cycle pulse mode for power savings.
Special 32 kHz/128 × fS operation mode.
INPUT
ASRCS
OUTPUT
ASRCS
–2.5dB
+2.5dB
Figure 82. Signal Level Diagram
Because of this input and output scaling, output signals from
the core should be limited to −2.5 dB full scale to prevent the
DACs and ASRCs from clipping.
ASYNCHRONOUS SAMPLE RATE CONVERTERS
The ADAU1772 includes asynchronous sample rate converters
(ASRCs) to enable synchronous full-duplex operation of the
serial ports. Two stereo ASRCs are available for the digital outputs,
and one stereo ASRC is available for the digital input signals.
Rev. C | Page 36 of 116
Data Sheet
ADAU1772
SIGNAL PROCESSING
The ADAU1772 processing core is optimized for active noise
cancelling (ANC) processing. The processing capabilities of the
core include biquad filters, limiters, volume controls, and mixing.
The core has four inputs and four outputs. The core is controlled
with a 10-bit program word, with a maximum of 32 instructions
per frame.
while the codec is running. Bank switching can be achieved by
writing to the CORE_CONTROL register (Address 0x0009) or
by using the multipurpose push-button switches, but not using
a combination of the two. Parameters in the active bank should
not be updated while the core is running; this will likely result
in noises on the outputs.
Parameters are assigned to instructions in the order in which
the instructions are instantiated in the code. The instruction
types that use parameters are the biquad filters and limiters.
INSTRUCTIONS
A complete list of instructions/processing blocks along with
documentation can be found in the SigmaStudio software for
the ADAU1772. The processing blocks available are
Table 17 shows the addresses of each parameter in Bank A that
are associated with each of the 32 instructions, and Table 18 shows
the addresses of each parameter in Bank B. Table 16 shows the
addresses of the LSB aligned, 10-bit program words.
•
•
•
•
•
•
•
•
•
Single-precision biquad/second order filters
Absolute value
Two-input addition
T connection in SigmaStudio
Limiter with/without external detector loop
Linear gain
Volume slider
Mute
DBREG level detection
Table 16. Program Addresses
Instruction
Instruction Address
0x0080
0x0081
0x0082
0x0083
0x0084
0x0085
0x0086
0x0087
0x0088
0x0089
0x008A
0x008B
0x008C
0x008D
0x008E
0x008F
0x0090
0x0091
0x0092
0x0093
0x0094
0x0095
0x0096
0x0097
0x0098
0x0099
0x009A
0x009B
0x009C
0x009D
0x009E
0x009F
0
1
2
3
4
5
6
7
DATA MEMORY
The ADAU1772 data path is 26 bits (5.21 format). The data
memory is 32 words of 2 × 26 bits. The double length memory
enables the core to double precision arithmetic with double
length data and single length coefficients.
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PARAMETERS
Parameters, such as filter coefficients, limiter settings, and volume
control settings, are saved in parameter registers. Each parameter is
a 32-bit number. The format of this number depends on whether it
is controlling a filter or a limiter. The number formats of different
parameters are shown in Table 15. When the parameter formats
use less than the full 32-bit memory space, as with the limiter
parameters, the data is LSB-aligned.
Table 15. Parameter Number Formats
Parameter Type
Filter Coefficient (B0, B1, B2)
Filter Coefficient (A1)
Filter Coefficient (A2)
Maximum Gain
Minimum Gain
Attack Time
Decay Time
Threshold
Format
5.27
2.27 (sign extended)
1.27 (sign extended)
2.23
2.23
24.0
24.0
2.23
There are two parameter banks available. Each bank can hold a
full set of 160 parameters (32 filters × 5 coefficients). Users can
switch between Bank A and Bank B, allowing for two sets of
parameters to be saved in memory and switched on the fly
Rev. C | Page 37 of 116
ADAU1772
Data Sheet
Table 17. Parameter Addresses, Bank A
Assignment Order
B0/Max Gain
B1/Min Gain
0x0100
0x0101
0x0102
0x0103
0x0104
0x0105
0x0106
0x0107
0x0108
0x0109
0x010A
0x010B
0x010C
0x010D
0x010E
0x010F
0x0110
0x0111
0x0112
0x0113
0x0114
0x0115
0x0116
0x0117
0x0118
0x0119
0x011A
0x011B
0x011C
0x011D
0x011E
0x011F
B2/Attack
0x0120
0x0121
0x0122
0x0123
0x0124
0x0125
0x0126
0x0127
0x0128
0x0129
0x012A
0x012B
0x012C
0x012D
0x012E
0x012F
0x0130
0x0131
0x0132
0x0133
0x0134
0x0135
0x0136
0x0137
0x0138
0x0139
0x013A
0x013B
0x013C
0x013D
0x013E
0x013F
A1/Decay
0x0140
0x0141
0x0142
0x0143
0x0144
0x0145
0x0146
0x0147
0x0148
0x0149
0x014A
0x014B
0x014C
0x014D
0x014E
0x014F
0x0150
0x0151
0x0152
0x0153
0x0154
0x0155
0x0156
0x0157
0x0158
0x0159
0x015A
0x015B
0x015C
0x015D
0x015E
0x015F
A2/Threshold
0
1
2
3
4
5
6
7
0x00E0
0x00E1
0x00E2
0x00E3
0x00E4
0x00E5
0x00E6
0x00E7
0x00E8
0x00E9
0x00EA
0x00EB
0x00EC
0x00ED
0x00EE
0x00EF
0x00F0
0x00F1
0x00F2
0x00F3
0x00F4
0x00F5
0x00F6
0x00F7
0x00F8
0x00F9
0x00FA
0x00FB
0x00FC
0x00FD
0x00FE
0x00FF
0x0160
0x0161
0x0162
0x0163
0x0164
0x0165
0x0166
0x0167
0x0168
0x0169
0x016A
0x016B
0x016C
0x016D
0x016E
0x016F
0x0170
0x0171
0x0172
0x0173
0x0174
0x0175
0x0176
0x0177
0x0178
0x0179
0x017A
0x017B
0x017C
0x017D
0x017E
0x017F
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Table 18. Parameter Addresses, Bank B
Assignment Order
B0/Max Gain
B1/Min Gain
0x01A0
0x01A1
0x01A2
0x01A3
0x01A4
0x01A5
0x01A6
0x01A7
0x01A8
0x01A9
0x01AA
0x01AB
0x01AC
0x01AD
0x01AE
0x01AF
B2/Attack
0x01C0
0x01C1
0x01C2
0x01C3
0x01C4
0x01C5
0x01C6
0x01C7
0x01C8
0x01C9
0x01CA
0x01CB
0x01CC
0x01CD
0x01CE
0x01CF
A1/Decay
0x01E0
0x01E1
0x01E2
0x01E3
0x01E4
0x01E5
0x01E6
0x01E7
0x01E8
0x01E9
0x01EA
0x01EB
0x01EC
0x01ED
0x01EE
0x01EF
A2/Threshold
0x0200
0x0201
0x0202
0x0203
0x0204
0x0205
0x0206
0x0207
0x0208
0x0209
0x020A
0x020B
0x020C
0x020D
0x020E
0x020F
0
1
2
3
4
5
6
7
0x0180
0x0181
0x0182
0x0183
0x0184
0x0185
0x0186
0x0187
0x0188
0x0189
0x018A
0x018B
0x018C
0x018D
0x018E
0x018F
8
9
10
11
12
13
14
15
Rev. C | Page 38 of 116
Data Sheet
ADAU1772
Assignment Order
B0/Max Gain
0x0190
0x0191
0x0192
0x0193
0x0194
0x0195
0x0196
0x0197
0x0198
0x0199
0x019A
0x019B
0x019C
0x019D
0x019E
0x019F
B1/Min Gain
0x01B0
0x01B1
0x01B2
0x01B3
0x01B4
0x01B5
0x01B6
0x01B7
0x01B8
0x01B9
0x01BA
0x01BB
0x01BC
0x01BD
0x01BE
0x01BF
B2/Attack
0x01D0
0x01D1
0x01D2
0x01D3
0x01D4
0x01D5
0x01D6
0x01D7
0x01D8
0x01D9
0x01DA
0x01DB
0x01DC
0x01DD
0x01DE
0x01DF
A1/Decay
0x01F0
0x01F1
0x01F2
0x01F3
0x01F4
0x01F5
0x01F6
0x01F7
0x01F8
0x01F9
0x01FA
0x01FB
0x01FC
0x01FD
0x01FE
0x01FF
A2/Threshold
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0x0210
0x0211
0x0212
0x0213
0x0214
0x0215
0x0216
0x0217
0x0218
0x0219
0x021A
0x021B
0x021C
0x021D
0x021E
0x021F
Rev. C | Page 39 of 116
ADAU1772
Data Sheet
CONTROL PORT
large amounts of data to contiguous memory locations. This
increment happens automatically after a single-word write unless
The ADAU1772 has both a 4-wire SPI control port and a 2-wire
I2C bus control port. Each can be used to set the memories and
registers. The IC defaults to I2C mode but can be put into SPI
the control port communication is stopped (that is, a stop
2
SS
condition is issued for I C, or is brought high for SPI). The
SS
control mode by pulling the pin low three times.
registers and RAMs in the ADAU1772 range in width from one
to four bytes, so the auto-increment feature knows the mapping
between subaddresses and the word length of the destination
register (or memory location).
The control port is capable of full read/write operation for all
addressable memories and registers. Most signal processing
parameters are controlled by writing new values to the param-
eter memories using the control port. Other functions, such as
mute and input/output mode control, are programmed through
the registers.
I2C PORT
The ADAU1772 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. I2C uses two
pins—serial data (SDA) and serial clock (SCL)—to carry data
between the ADAU1772 and the system I2C master controller.
In I2C mode, the ADAU1772 is always a slave on the bus, except
when the IC is self-booting. See the Self-Boot section for details
about using the ADAU1772 in self-boot mode.
All addresses can be accessed in either single-address mode or
burst mode. The first byte (Byte 0) of a control port write contains
the 7-bit IC address plus the R/ bit. The next two bytes (Byte 1
and Byte 2) are the 16-bit subaddress of the memory or register
location within the ADAU1772. All subsequent bytes (starting
with Byte 3) contain the data, such as register data, program
data, or parameter data. The number of bytes per word depends
on the type of data that is being written. Table 19 shows the word
length of the ADAU1772’s different data types. The exact formats
for specific types of writes are shown in Figure 85 and Figure 86.
W
Each slave device is recognized by a unique 7-bit address. The
ADAU1772 I2C address format is shown in Table 21. The LSB of
this first byte sent from the I2C master sets either a read or write
operation. Logic Level 1 corresponds to a read operation, and
Logic Level 0 corresponds to a write operation.
Pin ADDR0 and Pin ADDR1 set the LSBs of the I2C address
(Table 22); therefore, each ADAU1772 can be set to one of four
unique addresses. This allows multiple ICs to exist on the same
I2C bus without address contention. The 7-bit I2C addresses are
shown in Table 22.
Table 19. Data Word Sizes
Data Type
Registers
Program
Word Size (bytes)
1
2
4
Parameters
An I2C data transfer is always terminated by a stop condition.
If large blocks of data need to be downloaded to the ADAU1772,
the output of the core can be halted (using the CORE_RUN bit
in the core control register (Address 0x0009)), new data can be
loaded, and then the core can be restarted. This is typically done
during the booting sequence at start-up or when loading a new
program into memory.
Both SDA and SCL should have 2.0 kΩ pull-up resistors on the
lines connected to them. The voltage on these signal lines should
not be higher than IOVDD.
Table 21. I2C Address Format
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Registers and bits shown as reserved in the register map read back
0s. When writing to these registers and bits, such as during a burst
write across a reserved register, or when writing to reserved bits
in a register with other used bits, write 0s.
0
1
1
1
1
ADDR1
ADDR0
Table 22. I2C Addresses
ADDR1
ADDR0
Slave Address
0x3C
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 20 details these
multiple functions.
0
0
1
1
0
1
0
1
0x3D
0x3E
0x3F
Table 20. Control Port Pin Functions
Pin
I2C Mode
SPI Mode
SCL/SCLK
SDA/MISO
ADDR1/MOSI
ADDR0/SS
SCL—input
SDA—open-collector output MISO—output
I2C Address Bit 1—input
I2C Address Bit 0—input
SCLK—input
Addressing
Initially, each device on the I2C bus is in an idle state and
monitoring the SDA and SCL lines for a start condition and
the proper address. The I2C master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address/
data stream follows. All devices on the bus respond to the start
condition and shift the next eight bits (the 7-bit address plus the
MOSI—input
SS—input
BURST MODE COMMUNICATION
Burst mode addressing, in which the subaddresses are automati-
cally incremented at word boundaries, can be used for writing
Rev. C | Page 40 of 116
Data Sheet
ADAU1772
R/ bit) MSB first. The device that recognizes the transmitted
W
jumps to the idle condition. During a given SCL high period,
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADAU1772 does
not issue an acknowledge and returns to the idle condition. If
the user exceeds the highest subaddress while in auto-increment
mode, one of two actions is taken. In read mode, the ADAU1772
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no-acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse on SCL. If the highest subaddress
location is reached while in write mode, the data for the invalid
byte is not loaded into any subaddress register, a no acknowledge
is issued by the ADAU1772, and the part returns to the idle
condition.
address responds by pulling the data line low during the ninth
clock pulse. This ninth bit is known as an acknowledge bit. All
other devices withdraw from the bus at this point and return to
the idle condition. The R/ bit determines the direction of the
W
data. A Logic 0 on the LSB of the first byte indicates that the master
will write information to the peripheral, whereas a Logic 1 indicates
that the master will read information from the peripheral after
writing the subaddress and repeating the start address. A data
transfer takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
SCL is held high. Figure 83 shows the timing of an I2C write,
and Figure 84 shows an I2C read.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the ADAU1772 immediately
SCL
ADDR1 ADDR0
0
1
1
1
SDA
R/W
1
ACKNOWLEDGE
BY ADAU1772
ACKNOWLEDGE
BY ADAU1772
START BY
MASTER
FRAME 2
SUBADDRESS BYTE 1
FRAME 1
CHIP ADDRESS BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
STOP BY
MASTER
ACKNOWLEDGE
BY ADAU1772
ACKNOWLEDGE
BY ADAU1772
FRAME 4
DATA BYTE 1
FRAME 3
SUBADDRESS BYTE 2
Figure 83. I2C Write to ADAU1772 Clocking
SCL
SDA
0
1
1
1
ADDR1 ADDR0
1
R/W
ACKNOWLEDGE
BY ADAU1772
ACKNOWLEDGE
BY ADAU1772
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
SCL
(CONTINUED)
SDA
(CONTINUED)
0
1
1
1
1
ADDR1 ADDR0
R/W
ACKNOWLEDGE
BY ADAU1772
ACKNOWLEDGE
BY ADAU1772
REPEATED
START BY MASTER
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
CHIP ADDRESS BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
ACKNOWLEDGE
BY ADAU1772
ACKNOWLEDGE STOP BY
BY ADAU1772 MASTER
FRAME 5
READ DATA BYTE 1
FRAME 6
READ DATA BYTE 2
Figure 84. I2C Read from ADAU1772 Clocking
Rev. C | Page 41 of 116
ADAU1772
Data Sheet
I2C Read and Write Operations
back to the master. The master then responds every ninth pulse
with an acknowledge pulse to the ADAU1772.
Figure 85 shows the timing of a single-word write operation.
Every ninth clock pulse, the ADAU1772 issues an acknowledge
by pulling SDA low.
Figure 88 shows the timing of a burst mode read sequence. This
figure shows an example where the target read words are two
bytes. The ADAU1772 increments its subaddress every two bytes
because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other address
ranges may have a variety of word lengths, ranging from one to
four bytes. The ADAU1772 always decodes the subaddress and
sets the auto-increment circuit so that the address increments
after the appropriate number of bytes.
Figure 86 shows the timing of a burst mode write sequence. This
figure shows an example where the target destination words are
two bytes, such as the program memory. The ADAU1772 knows
to increment its subaddress register every two bytes because the
requested subaddress corresponds to a register or memory area
with a 2-byte word length.
The timing of a single-word read operation is shown in Figure 87.
Figure 85 to Figure 88 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
Note that the first R/ bit is 0, indicating a write operation. This
W
is because the subaddress still needs to be written to set up the
internal address. After the ADAU1772 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/ set to 1 (read).
W
This causes the ADAU1772 SDA to reverse and begin driving data
2
I C ADDRESS,
S
S
S
S
AS
SUBADDRESS HIGH
AS
SUBADDRESS LOW
AS
DATA BYTE 1
AS
DATA BYTE 2
...
AS
DATA BYTE N
P
R/W = 0
Figure 85. Single-Word I2C Write Format
2
I C ADDRESS,
R/W = 0
SUBADDRESS
SUBADDRESS
LOW
DATAWORD 1,
BYTE 1
DATAWORD 1,
BYTE 2
DATAWORD 2,
BYTE 1
DATAWORD 2,
BYTE 2
AS
AS
AS
AS
AS
AS
AS ...
P
HIGH
Figure 86. Burst Mode I2C Write Format
2
2
I C ADDRESS,
SUBADDRESS
SUBADDRESS
LOW
I C ADDRESS,
R/W = 1
AS
AS
AS
AS
S
AS
DATA BYTE 1 AM DATA BYTE 2
...
AM DATA BYTE N
P
R/W = 0
HIGH
Figure 87. Single-Word I2C Read Format
2
2
I C ADDRESS,
SUBADDRESS
SUBADDRESS
LOW
I C ADDRESS,
R/W = 1
DATAWORD 1,
BYTE 1
DATAWORD 1,
BYTE 2
AS
AS
S
AS
AM
AM
...
P
R/W = 0
HIGH
Figure 88. Burst Mode I2C Read Format
Rev. C | Page 42 of 116
Data Sheet
ADAU1772
Read/
Write
SPI PORT
By default, the ADAU1772 is in I2C mode, but it can be put into
The first byte of an SPI transaction indicates whether the com-
SS
munication is a read or a write with the R/ bit. The LSB of this
SPI control mode by pulling low three times. This can be easily
W
accomplished by issuing three SPI writes, which are in turn ignored
by the ADAU1772. The next (fourth) SPI write is then latched
into the SPI port.
first byte determines whether the SPI transaction is a read (Logic
Level 1) or a write (Logic Level 0).
Subaddress
SS
The SPI port uses a 4-wire interface—consisting of , SCLK,
The 16-bit subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate memory location or register.
SS
MOSI, and MISO signals—and is always a slave port. The
signal should go low at the beginning of a transaction and high
at the end of a transaction. The SCLK signal latches MOSI on a
low-to-high transition. MISO data is shifted out of the ADAU1772
on the falling edge of SCLK and should be clocked into a receiving
device, such as a microcontroller, on the SCLK rising edge. The
MOSI signal carries the serial input data, and the MISO signal
is the serial output data. The MISO signal remains tristated until a
read operation is requested. This allows other SPI-compatible
peripherals to share the same readback line.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. During a burst mode write, an initial
subaddress is written followed by a continuous sequence of data
for consecutive memory/register locations.
A sample timing diagram for a single-write SPI operation to the
parameter RAM is shown in Figure 89. A sample timing diagram
of a single-read SPI operation is shown in Figure 90. The MISO
pin goes from tristate to being driven at the beginning of Byte 3.
In this example, Byte 0 to Byte 2 contain the addresses and the
All SPI transactions have the same basic format shown in Table 23.
A timing diagram is shown in Figure 89 and Figure 90. All data
should be written MSB first. The ADAU1772 can only be taken
W
R/ bit and subsequent bytes carry the data.
out of SPI mode by pulling the
pin low or by powering
PD
down the IC.
Table 23. Generic SPI Word Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 41
data
0000000, R/W
Register/memory address [15:8]
Register/memory address [7:0]
data
1 Continues to end of data.
SS
SCLK
MOSI
BYTE 0
BYTE 1
BYTE 2
BYTE 3
Figure 89. SPI Write to ADAU1772 Clocking (Single-Write Mode)
SS
SCLK
MOSI
BYTE 0
BYTE 1
HIGH-Z
HIGH-Z
MISO
DATA
DATA
DATA
Figure 90. SPI Read from ADAU1772 Clocking (Single-Read Mode)
Rev. C | Page 43 of 116
ADAU1772
Data Sheet
SELF-BOOT
CRC
The ADAU1772 boots up from an EEPROM over the I2C bus
An 8-bit CRC validates the content of the EEPROM. This CRC is
strong enough to detect single error bursts of up to eight bits in size.
when the SELFBOOT pin is set high at power-up and the
PD
pin is set high. The state of the SELFBOOT pin is checked only
when the ADAU1772 comes out of a reset via the pin, and
The terminate self-boot instruction (0x00 instruction byte) must
be followed by a CRC byte. The CRC is generated using all of the
EEPROM bytes from Address 0x0000 to the last 0x00 instruction
byte. The polynomial for the CRC is
PD
the EEPROM is not used after a self-boot is complete. During
booting, ensure that there is a stable DVDD in the system. The
pin should remain high during the self-boot operation. The
PD
x8 x2 x 1
master SCL clock output from the ADAU1772 is derived from
the input clock on XTALI/MCLKIN. A divide-by-64 circuit
ensures that the SCL output frequency during the self-boot
operation is never greater than 400 kHz for most input clock
frequencies. With the external master clock to the ADAU1772
being between 12 MHz and 27 MHz, the SCL frequency ranges
from 176 kHz to 422 kHz. If the self-boot EEPROM is not rated
for operation above 400 kHz, be sure to use a master clock that
is no faster than 25.6 MHz.
If the CRC is incorrect or if an unrecognized instruction byte is
read during self-boot, the boot process is immediately stopped
and restarted after a 250 ms delay (for a 12.288 MHz input clock).
When SigmaStudio is used, the CRC byte is generated auto-
matically when a configuration is downloaded to the EEPROM.
Delay
The delay instruction (0x02 instruction byte) delays by the
16-bit setting × 2048 clock cycles.
Table 25 shows the list of instructions that are possible during
an ADAU1772 self-boot. The 0x01 and 0x05 instruction bytes
are used to load the register, program, and parameter settings.
Boot Time
The time to self-boot the ADAU1772 from an EEPROM can be
calculated using the following equation:
EEPROM Size
Boot Time = 64/MCLK Frequency × Total Bytes + Wait Time
The self-boot circuit is compatible with an EEPROM that has a
2-byte address. For most EEPROM families, a 2-byte address is
used on devices that are 32 kB or larger. The EEPROM must be
set to Address 0x50. Examples of two compatible EEPROMs
include Atmel AT24C32D and STMicroelectronics M24C32-F.
The self-boot operation starts after 16,568 clock cycles are seen on
the XTALI/MCLKIN pin after
clock, this corresponds to approximately a 1.35 ms wait time
from power-up. This delay ensures that the crystal used for
generating the master clock has ramped up to a stable oscillation.
is set high. With a 12.288 MHz
PD
Table 24 lists the maximum necessary EEPROM size, assuming
that there is 100% utilization of the program and parameters
(both banks). There is inherently some overhead for instructions
to control the self-boot procedure.
Table 25. EEPROM Self-Boot Instructions
Instruction
Byte ID
Instruction Byte
Description
Following Bytes
0x00
0x01
End self-boot
CRC
Table 24. Maximum EEPROM Size
Write multibyte length
minus two bytes, starting
at target address
Length (high byte),
length (low byte),
address (high byte),
address (low byte),
data (0), data (1), ...
data (length – 3)
Word Size
(Bytes per
Word)
Total EEPROM
Space Requirement
(Bytes)
ADAU1772
Memory Blocks
Words
32
Program
2
4
4
1
64
Bank 0 Parameters
Bank 1 Parameters
Registers
160 (32 × 5)
160
640
640
65
0x02
Delays by the 16-bit setting
× 2048 clock cycles
Delay (high byte),
delay (low byte)
65
0x03
0x04
0x05
No operation
None
None
Total Bytes
1409
Wait for PLL lock
Write single byte to target
address
Address (high byte),
address (low byte), data
0x02
0x00
0x04
0x01
0x00
0x05
0x00
0x80
DELAY
DELAY
(HIGH BYTE)
DELAY
(LOW BYTE)
WRITE
LENGTH
(HIGH BYTE)
LENGTH
(LOW BYTE)
ADDRESS
(HIGH BYTE)
ADDRESS
(LOW BYTE)
DELAY LENGTH
LENGTH
PROGRAM RAM ADDRESS
0x1A
0x2B
0x3C
0x04
0x03
0x00
END
DATA
(0)
DATA
(1)
DATA
(LENGTH – 3)
PLL LOCK
NO OP
PROGRAM RAM DATA
Figure 91. A List of Example Self-Boot EEPROM Instructions
Rev. C | Page 44 of 116
Data Sheet
ADAU1772
MULTIPURPOSE PINS
The ADAU1772 has seven multipurpose (MP) pins that can be
used for serial data I/O, clock outputs, and control in a system
without a microcontroller. Each pin can be individually set to
either its default or MP setting. The functions include push-
button volume controls, enabling the compressors, parameter
bank switching, DSP bypass mode, and muting the outputs.
When the ADC and/or DAC volumes are controlled with the
push-buttons, the corresponding volume control registers no
longer allow control of the volume from the control port.
Therefore, writing to these volume control registers has no
effect on the codec volume level.
LIMITER COMPRESSION ENABLE
The function of each of these pins is set in Register 0x0038 to
Register 0x003E. By default, each pin is configured as an input.
This function allows a user to enable limiter compression
regardless of the signal level. Setting an MPx pin low when this
function is enabled causes the limiter to compress the incoming
signal by the minimum gain setting. When the MPx pin is released,
the limiter resumes normal behavior.
Table 26. Multipurpose Pin Functions
Pin No. Default Pin Function
Secondary Pin Functions
Multipurpose control inputs
Multipurpose control inputs
Multipurpose control inputs
ADC_SDATA0, PDM output,
multipurpose control inputs
ADC_SDATA1, CLKOUT,
multipurpose control inputs
Multipurpose control inputs
Multipurpose control inputs
31
32
33
34
LRCLK
BCLK
DAC_SDATA
MP1 acting as push-
button volume up
PARAMETER BANK SWITCHING
An MPx pin can be used to switch the active parameter bank
between Bank A and Bank B. When this setting is selected,
Bank A is active when the pin is high and Bank B is active when
the pin is low. Care should be taken to set the BANK_SL bits in
the CORE_CONTROL register (Address 0x0009) to the default
value of 0x00 before enabling MPx pin control over bank
switching. Simultaneous control of bank switching by both
register setting and MPx pin selection is not possible.
35
MP6 acting as push-
button volume down
36
37
DMIC2_3
DMIC0_1
Bit ZERO_STATE selects whether the data memory of the
codec is set to 0 during a bank switch. If the data is not set to 0
when a new set of filter coefficients is enabled via a bank switch,
there may be a pop in the audio as the old data is circulated in
the new filters.
PUSH-BUTTON VOLUME CONTROLS
The ADC and DAC volume controls can be set up to be controlled
with two push-buttons—one for volume up and one for volume
down. The volume setting can either be changed with a click of the
button or be ramped by holding the button. The volume settings
change when the signal on the pin from the button goes from
low to high.
MUTE
The MPx pins can be put into a mode to mute the ADCs or DACs.
When in this mode, mute is enabled when an MPx pin is set low.
The full combination of possible mutes for ADCs and DACs
using MPx pins are set in Register 0x0038 to Register 0x003E.
When in push-button mode, the initial volume level is set with
Bits PB_VOL_INIT_VAL. By default, MP1 acts as the push-
button volume up and MP6 acts as the push-button volume
down; however, any of the MPx pins can be set to act as the
push-button up and push-button down volume controls.
Rev. C | Page 45 of 116
ADAU1772
Data Sheet
is pulled low. Pressing and holding the switch closed enables the
DSP bypass signal path as defined in the TALKTHRU register
(Address 0x002A). The DAC volume control setting is switched
from the default gain setting to the new TALKTHRU_GAINx
register setting (Address 0x002B and Address 0x002C). DSP bypass
is enabled only on ADC0 and ADC1. The DSP bypass signal path
is from the output of ADCx to the input of the DAC(s).
DSP BYPASS MODE
When DSP bypass mode is enabled, a direct path from the ADC
outputs to the DACs is set up to enable bypassing the core pro-
cessing to listen to environmental sounds. This is useful for
listening to someone speaking without having to remove the
noise cancelling headphones. The DSP bypass path is enabled
by setting an MPx pin low. Figure 92 shows the DSP bypass path
disabled, and Figure 93 shows the DSP bypass path enabled by
pressing the push-button switch. The DSP bypass feature works
for both analog and digital microphone inputs.
When DSP bypass is enabled, the current DAC volume setting
is ramped down to −95.625 dB and the DSP bypass volume
setting is ramped up to avoid pops when switching paths.
DSP bypass is enabled when a switch connected to an MPx pin
that is set to DSP bypass mode is closed and the MPx pin signal
MPx
ADAU1772
10kΩ
DAC AND HP
AMPLIFIER
PGA AND ADC
AINxREF
HPOUTxP
HPOUTxN
AINx
CORE
PROCESSING
NORMAL
SETTING
Figure 92. DSP Bypass Path Disabled
MPx
10kΩ
ADAU1772
DAC AND HP
AMPLIFIER
PGA AND ADC
HPOUTxP
HPOUTxN
AINxREF
AINx
CORE
PROCESSING
TALK-THRU
SETTING
Figure 93. DSP Bypass Path Enabled
Rev. C | Page 46 of 116
Data Sheet
ADAU1772
SERIAL DATA INPUT/OUTPUT PORTS
BCLK rate (12.288 MHz), a sample rate of 192 kHz, or a TDM8
mode operating at a sample rate of 48 kHz, it is recommended
to use the high drive settings on the serial port pins. The high
drive strength effectively speeds up the transition times of the
waveforms, thereby improving the signal integrity of the clock
and data lines. These can be set in the PAD_CONTROL4 register
(Address 0x004C).
The serial data input and output ports of the ADAU1772 can be set
to accept or transmit data in a 2-channel format or in a 4-channel
or 8-channel TDM stream to interface to external ADCs, DACs,
DSPs, and SOCs. Data is processed in twos complement, MSB
first format. The left-channel data field always precedes the
right-channel data field in the 2-channel streams. In 8-channel
TDM mode, the data channels are output sequentially, starting
with the channel set by the ADC_SDATA0_ST and
Table 27. Serial In/Out Port Master/Slave Mode Capabilities
ADC_SDATA1_ST bits. The serial modes and the position of
the data in the frame are set in the serial data port (SAI_0,
SAI_1) and serial output control registers
2-Channel Modes
(I2S, Left Justified,
Right Justified)
4-Channel
TDM
8-Channel
TDM
fSSD
(SOUT_SOURCE_x_x, Address 0x0013 to Address 0x0016).
48 kHz
Yes
Yes
Yes
No
Yes
No
No
96 kHz
Yes
The serial data clocks do not need to be synchronous with the
ADAU1772 master clock input, but the LRCLK and BCLK must
be synchronous to each other. The LRCLK and BCLK pins are
used to clock both the serial input and output ports. The
ADAU1772 can be set to be either the master or the slave in a
system. Because there is only one set of serial data clocks, the
input and output ports must always both be either master or
slave.
192 kHz Yes
Table 28 describes the proper serial port settings for standard
audio data formats. More information about the settings in this
table can be found in the Serial Port Control 0 and Serial Port
Control 1 registers (Address 0x0032 and Address 0x0033)
descriptions.
The serial data control registers allow control of the clock polarity
and the data input modes. The valid data formats are I2S, left
justified, right justified (24- or 16-bit), PCM, and TDM. In all
modes except for the right justified modes, the serial port inputs
an arbitrary number of bits up to a limit of 24. Extra bits do not
cause an error, but they are truncated internally. The serial port
can operate with an arbitrary number of BCLK transitions in
each LRCLK frame. The LRCLK in TDM mode can be input to
the ADAU1772 either as a 50% duty cycle clock or as a bit-wide
pulse. Table 27 lists the modes in which the serial input/output
port can function. When using low IOVDD (1.8 V) with a high
TRISTATING UNUSED CHANNELS
Unused outputs can be tristated so that multiple ICs can drive a
single TDM line. This function is available only when the serial
ports of the ADAU1772 are operating in TDM mode. Channels
that are inactive can be set in the SOUT_CONTROL0 register
(Address 0x0034). The tristating of inactive channels is set in
the SAI_1 register (Address 0x0033), which offers the option of
tristating or driving the inactive channel.
In a 32-bit TDM frame with 24-bit data, the eight unused bits
are tristated. Inactive channels are also tristated for the full frame.
Table 28. Serial Port Data Format Settings
LRCLK Polarity
(LR_POL)
LRCLK Type
(LR_MODE)
BCLK Polarity
(BCLKEDGE)1
MSB Position
(SDATA_FMT)
Format
I2S (Figure 94)
0
1
1
1
1
1
0
0
0
0
0
0
0
X
X
00
01
10 or 11
00
00
Left Justified (Figure 95)
Right Justified (Figure 96 and Figure 97)
TDM (Figure 98 and Figure 99)
PCM/DSP Short Frame Sync (Figure 100)
PCM/DSP Long Frame Sync (Figure 101)
0 or 1
1
0
01
1 X = don’t care.
1
2
3
4
24
25
26
32
33
34
35
36
56
57
58
64
LRCLK
BCLK (64 × f
2
)
S
MSB
LSB
MSB
LSB
I S (24-BIT)
LEFT CHANNEL
RIGHT CHANNEL
Figure 94. I2S Mode—16 Bits to 24 Bits per Channel
Rev. C | Page 47 of 116
ADAU1772
Data Sheet
LRCLK
1
2
3
23
24
25
32
33
34
35
55
56
57
64
BCLK (64 × f
)
S
LJ (24-BIT)
MSB
LSB
MSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 95. Left Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK (64 × f
1
2
9
10
11
12
31
32
33
34
41
42
43
44
63
64
)
S
RJ (24-BIT)
MSB
LSB
MSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 96. Right Justified Mode—24 Bits per Channel
LRCLK
BCLK (64 × f
1
2
17
18
19
20
31
32
33
34
49
50
51
52
63
64
)
S
RJ (24-BIT)
MSB
LSB
MSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 97. Right Justified Mode—16 Bits per Channel
LRCLK
BCLK
256 BCLKs
32 BCLKs
DATA
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
SLOT 8
LRCLK
BCLK
MSB
MSB – 1
MSB – 2
DATA
Figure 98. 8-Channel TDM Mode
LRCLK
BCLK
DATA
MSB TDM
MSB TDM
CH
0
8TH
CH
SLOT 0
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
32
BCLKs
Figure 99. 8-Channel TDM Mode, Pulse LRCLK
Rev. C | Page 48 of 116
Data Sheet
ADAU1772
LRCLK
1
2
3
4
16
17
18
19
20
32
33
34
BCLK (64 × f
)
S
PCM (24-BIT)
MSB
LSB
MSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 100. PCM/DSP Mode, 16 Bits per Channel, Short Frame Sync
LRCLK
1
2
3
4
16
17
18
19
20
32
33
34
BCLK (64 × f
)
S
PCM (24-BIT)
MSB
LSB
MSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 101. PCM/DSP Mode, 16 Bits per Channel, Long Frame Sync
Rev. C | Page 49 of 116
ADAU1772
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY BYPASS CAPACITORS
EXPOSED PAD PCB DESIGN
Each analog and digital power supply pin should be bypassed to
its nearest appropriate ground pin with a single 0.1 μF capacitor.
The connections to each side of the capacitor should be as short
as possible, and the trace should be routed on a single layer with no
vias. For maximum effectiveness, locate the capacitor equidistant
from the power and ground pins or slightly closer to the power pin
if equidistant placement is not possible. Thermal connections to
the ground planes should be made on the far side of the capacitor.
The ADAU1772 has an exposed pad on the underside of the
LFCSP. This pad is used to couple the package to the PCB for
heat dissipation. When designing a board for the ADAU1772,
special consideration should be given to the following:
•
A copper layer equal in size to the exposed pad should be
on all layers of the board, from top to bottom, and should
connect somewhere to a dedicated copper board layer (see
Figure 103).
Each supply signal on the board should also be bypassed with a
single bulk capacitor (10 μF to 47 μF).
VDD GND
•
Vias should be placed to connect all layers of copper,
allowing for efficient heat and energy conductivity. For an
example, see Figure 104, which has nine vias arranged in a
3 × 3 grid in the pad area.
TOP
GROUND
POWER
BOTTOM
CAPACITOR
TO VDD
VIAS
COPPER SQUARES
Figure 103. Exposed Pad Layout Example, Side View (Not to Scale)
TO GND
Figure 102. Recommended Power Supply Bypass Capacitor Layout
LAYOUT
Pin 24 is the AVDD supply for the headphone amplifiers. If the
headphone amplifiers are enabled, the PCB trace to this pin should
be wider than traces to other pins to increase the current carrying
capacity. A wider trace should also be used for the headphone
output lines.
GROUNDING
A single ground plane should be used in the application layout.
Components in an analog signal path should be placed away
from digital signals.
Figure 104. Exposed Pad Layout Example, Top View (Not to Scale)
Rev. C | Page 50 of 116
Data Sheet
ADAU1772
REGISTER SUMMARY
Table 29. Low Latency Codec Register Summary
Reg
Name
Bits Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x0000 CLK_CONTROL
0x0001 PLL_CTRL0
0x0002 PLL_CTRL1
0x0003 PLL_CTRL2
0x0004 PLL_CTRL3
0x0005 PLL_CTRL4
0x0006 PLL_CTRL5
0x0007 CLKOUT_SEL
0x0008 REGULATOR
0x0009 CORE_CONTROL
0x000B CORE_ENABLE
0x000C DBREG0
[7:0] PLL_EN
RESERVED
SPK_FLT_DIS XTAL_DIS
CLKSRC
CC_CDIV
CC_MDIV
COREN
[7:0]
M_MSB
[7:0]
M_LSB
N_MSB
N_LSB
[7:0]
[7:0]
[7:0] RESERVED
R
X
PLL_TYPE
LOCK
0x00 RW
0x00
[7:0]
RESERVED
R
[7:0]
RESERVED
RESERVED
CLKOUT_FREQ
0x00 RW
0x00 RW
0x04 RW
[7:0]
REG_PD
REGV
CORE_RUN
[7:0] ZERO_STATE
BANK_SL
RESERVED
CORE_FS
LIM_EN
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
DSP_CLK_EN 0x03 RW
DBVAL0
DBVAL1
DBVAL2
0x00
0x00
0x00
R
R
R
0x000D DBREG1
0x000E DBREG2
0x000F CORE_IN_MUX_0_1 [7:0]
0x0010 CORE_IN_MUX_2_3 [7:0]
0x0011 DAC_SOURCE_0_1 [7:0]
0x0012 PDM_SOURCE_0_1 [7:0]
0x0013 SOUT_SOURCE_0_1 [7:0]
0x0014 SOUT_SOURCE_2_3 [7:0]
0x0015 SOUT_SOURCE_4_5 [7:0]
0x0016 SOUT_SOURCE_6_7 [7:0]
CORE_IN_MUX_SEL_1
CORE_IN_MUX_SEL_3
DAC_SOURCE1
PDM_SOURCE1
SOUT_SOURCE1
SOUT_SOURCE3
SOUT_SOURCE5
SOUT_SOURCE7
RESERVED
CORE_IN_MUX_SEL_0
CORE_IN_MUX_SEL_2
DAC_SOURCE0
0x10 RW
0x32 RW
0x10 RW
0x32 RW
0x54 RW
0x76 RW
0x54 RW
0x76 RW
0x04 RW
0x10 RW
0x32 RW
0x00 RW
0x19 RW
0x19 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x40 RW
0x40 RW
0x40 RW
0x40 RW
0x00 RW
PDM_SOURCE0
SOUT_SOURCE0
SOUT_SOURCE2
SOUT_SOURCE4
SOUT_SOURCE6
0x0017 ADC_SDATA_CH
[7:0]
ADC_SDATA1_ST
ADC_SDATA0_ST
0x0018 ASRCO_SOURCE_0_1 [7:0]
0x0019 ASRCO_SOURCE_2_3 [7:0]
ASRC_OUT_SOURCE1
ASRC_OUT_SOURCE3
RESERVED
ASRC_OUT_SOURCE0
ASRC_OUT_SOURCE2
0x001A ASRC_MODE
[7:0]
ASRC_IN_CH
ASRC_OUT_EN ASRC_IN_EN
0x001B ADC_CONTROL0
0x001C ADC_CONTROL1
0x001D ADC_CONTROL2
0x001E ADC_CONTROL3
0x001F ADC0_VOLUME
0x0020 ADC1_VOLUME
0x0021 ADC2_VOLUME
0x0022 ADC3_VOLUME
[7:0]
RESERVED
RESERVED
RESERVED
ADC1_MUTE ADC0_MUTE
ADC3_MUTE ADC2_MUTE
RESERVED
RESERVED
DCM_0_1
DCM_2_3
ADC_0_1_FS
ADC_2_3_FS
[7:0]
RESERVED
[7:0] RESERVED
HP_0_1_EN
DMIC_POL0
DMIC_POL1
DMIC_SW0
DMIC_SW1
ADC_1_EN
ADC_3_EN
ADC_0_EN
ADC_2_EN
[7:0] RESERVED
HP_2_3_EN
[7:0]
[7:0]
[7:0]
[7:0]
ADC_0_VOL
ADC_1_VOL
ADC_2_VOL
ADC_3_VOL
0x0023 PGA_CONTROL_0 [7:0] PGA_EN0
0x0024 PGA_CONTROL_1 [7:0] PGA_EN1
0x0025 PGA_CONTROL_2 [7:0] PGA_EN2
0x0026 PGA_CONTROL_3 [7:0] PGA_EN3
0x0027 PGA_STEP_CONTROL [7:0]
PGA_MUTE0
PGA_GAIN0
PGA_MUTE1
PGA_MUTE2
PGA_MUTE3
PGA_GAIN1
PGA_GAIN2
PGA_GAIN3
RESERVED
SLEW_RATE
SLEW_PD3
SLEW_PD2
SLEW_PD1
SLEW_PD0
0x0028 PGA_10DB_BOOST [7:0]
RESERVED
HP_POP_DIS1 HP_POP_DIS0 PGA_POP_DIS3 PGA_POP_DIS2 PGA_POP_DIS1 PGA_POP_DIS0 0x3F RW
RESERVED TALKTHRU_PATH
TALKTHRU_GAIN0_VAL
TALKTHRU_GAIN1_VAL
PGA_3_BOOST PGA_2_BOOST PGA_1_BOOST PGA_0_BOOST 0x00 RW
0x0029 POP_SUPPRESS
0x002A TALKTHRU
[7:0]
[7:0]
RESERVED
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x18 RW
0x00 RW
0x00 RW
0x0F RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x10 RW
0x00 RW
0x00 RW
0x00 RW
0x002B TALKTHRU_GAIN0 [7:0]
0x002C TALKTHRU_GAIN1 [7:0]
0x002D MIC_BIAS
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
RESERVED
MIC_EN1
DAC_POL
MIC_EN0
RESERVED
DAC1_MUTE DAC0_MUTE
DAC_0_VOL
RESERVED
RESERVED
MIC_GAIN1
DAC1_EN
MIC_GAIN0
0x002E DAC_CONTROL1
0x002F DAC0_VOLUME
0x0030 DAC1_VOLUME
DAC0_EN
DAC_1_VOL
0x0031 OP_STAGE_MUTES [7:0]
RESERVED
HP_MUTE_R
HP_MUTE_L
0x0032 SAI_0
0x0033 SAI_1
[7:0]
SDATA_FMT
SAI
LR_POL
SER_PORT_FS
[7:0] TDM_TS
BCLK_TDMC
TDM6_DIS
RESERVED
LR_MODE
TDM5_DIS
SAI_MSB
BCLKRATE
TDM2_DIS
BCLKEDGE
TDM1_DIS
SAI_MS
0x0034 SOUT_CONTROL0 [7:0] TDM7_DIS
TDM4_DIS
PDM_CTRL
TDM3_DIS
TDM0_DIS
0x0036 PDM_OUT
0x0037 PDM_PATTERN
0x0038 MODE_MP0
0x0039 MODE_MP1
0x003A MODE_MP2
0x003B MODE_MP3
0x003C MODE_MP4
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
PDM_CH
PDM_EN
PATTERN
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MODE_MP0_VAL
MODE_MP1_VAL
MODE_MP2_VAL
MODE_MP3_VAL
MODE_MP4_VAL
Rev. C | Page 51 of 116
ADAU1772
Data Sheet
Reg
Name
Bits Bit 7
[7:0]
Bit 6
RESERVED
RESERVED
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
0x00 RW
0x11 RW
0x00 RW
0x87 RW
0x05 RW
0x0F RW
0x003D MODE_MP5
0x003E MODE_MP6
0x003F PB_VOL_SET
0x0040 PB_VOL_CONV
MODE_MP5_VAL
MODE_MP6_VAL
[7:0]
[7:0]
PB_VOL_INIT_VAL
HOLD
[7:0]
GAINSTEP
RAMPSPEED
PB_VOL_CONV_VAL
DEBOUNCE
0x0041 DEBOUNCE_MODE [7:0]
0x0043 OP_STAGE_CTRL [7:0]
RESERVED
HP_EN_R
RESERVED
HP_EN_L
HP_PDN_R
HP_PDN_L
SINC_0_EN
INT_0_EN
0x0044 DECIM_PWR_MODES [7:0] DEC_3_EN
0x0045 INTERP_PWR_MODES [7:0]
MOD_1_EN
MOD_0_EN
INT_1_EN
0x00 RW
0x00 RW
0x00 RW
0x00 RW
RESERVED
0x0046 BIAS_CONTROL0
0x0047 BIAS_CONTROL1
0x0048 PAD_CONTROL0
[7:0]
HP_IBIAS
CBIAS_DIS
AFE_IBIAS01
ADC_IBIAS23
MIC_IBIAS
ADC_IBIAS01
DAC_IBIAS
[7:0] RESERVED
[7:0] RESERVED
AFE_IBIAS23
DAC_SDATA_ 0x7F RW
PU
0x0049 PAD_CONTROL1
0x004A PAD_CONTROL2
[7:0]
RESERVED
ADDR0_PU
0x1F RW
[7:0] RESERVED
DAC_SDATA_ 0x00 RW
PD
0x004B PAD_CONTROL3
0x004C PAD_CONTROL4
[7:0]
RESERVED
ADDR0_PD
0x00 RW
0x00 RW
[7:0] RESERVED
RESERVED
0x004D PAD_CONTROL5
[7:0]
RESERVED
RESERVED
SCL_DRV
SDA_DRV
RESERVED
RESERVED
0x00 RW
Rev. C | Page 52 of 116
Data Sheet
ADAU1772
REGISTER DETAILS
CLOCK CONTROL REGISTER
Address: 0x0000, Reset: 0x00, Name: CLK_CONTROL
This register is used to enable the internal clocks.
Table 30. Bit Descriptions for CLK_CONTROL
Bits
Bit Name
Settings
Description
Reset
Access
7
PLL_EN
Enable PLL. When this bit is set to 0, the PLL is powered down and the PLL
output clock is disabled. The PLL should not be enabled until after all the
PLL control settings (Register PLL_CTRL0 to Register PLL_CTRL5) have been
set. The PLL clock output is active when both PLL_EN = 1 and COREN = 1.
0x0
RW
0
1
PLL disabled
PLL enabled
5
SPK_FLT_DIS
Disable I2C spike filter. By default, the SDA and SCL inputs have a 50 ns
spike suppression filter. When the control interface is in SPI mode, this
filter is disabled regardless of this setting.
0x0
RW
0
1
I2C spike filter enabled
I2C spike filter disabled
Disable crystal oscillator.
Crystal oscillator enabled
Crystal oscillator disabled
Main clock source.
4
3
XTAL_DIS
CLKSRC
0x0
0x0
RW
RW
0
1
0
1
External pin drives main clock.
PLL drives main clock. This bit should only be set after LOCK in
Register PLL_CTRL5 has gone high.
2
1
CC_CDIV
CC_MDIV
SCLK divider control. The core clock (SCLK) is used only by the core. It
must run at 12.288 MHz.
Div 2: divide PLL/external clock by 2
Div 1: divide PLL/external clock by 1
0x0
RW
RW
0
1
MCLK divider control. The internal master clock (MCLK) of the IC is used by 0x0
all digital logic except the core. It must run at 12.288 MHz.
0
1
Div 2: divide PLL/external clock by 2
Div 1: divide PLL/external clock by 1
Rev. C | Page 53 of 116
ADAU1772
Data Sheet
Bits
Bit Name
COREN
Settings
Description
Reset
Access
0
Main clock enable. When COREN = 0, it is only possible to write to this
register and the PLL control registers (PLL_CTRL0 to PLL_CTRL5). This
control also enables the PLL clock. If using the PLL, do not set COREN = 1
until LOCK in Register PLL_CTRL5 is 1. Note that after COREN is enabled,
writing to the parameters is disabled until setting DSP_CLK_EN in the
CORE_ENABLE register.
0x0
RW
0
1
Main clock disabled
Main clock enabled
PLL DENOMINATOR MSB REGISTER
Address: 0x0001, Reset: 0x00, Name: PLL_CTRL0
This register should only be written when PLL_EN = 0 in Register CLK_CONTROL.
Table 31. Bit Descriptions for PLL_CTRL0
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
M_MSB
PLL denominator MSB.
0x00
RW
PLL DENOMINATOR LSB REGISTER
Address: 0x0002, Reset: 0x00, Name: PLL_CTRL1
This register should only be written when PLL_EN = 0 in Register CLK_CONTROL.
Table 32. Bit Descriptions for PLL_CTRL1
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
M_LSB
PLL denominator LSB.
0x00
RW
PLL NUMERATOR MSB REGISTER
Address: 0x0003, Reset: 0x00, Name: PLL_CTRL2
This register should only be written when PLL_EN = 0 in Register CLK_CONTROL.
Rev. C | Page 54 of 116
Data Sheet
ADAU1772
Table 33. Bit Descriptions for PLL_CTRL2
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
N_MSB
PLL numerator MSB.
0x00
RW
PLL NUMERATOR LSB REGISTER
Address: 0x0004, Reset: 0x00, Name: PLL_CTRL3
This register should only be written when PLL_EN = 0 in Register CLK_CONTROL.
Table 34. Bit Descriptions for PLL_CTRL3
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
N_LSB
PLL numerator LSB.
0x00
RW
PLL INTEGER SETTING REGISTER
Address: 0x0005, Reset: 0x00, Name: PLL_CTRL4
This register should only be written when PLL_EN = 0 in Register CLK_CONTROL.
Table 35. Bit Descriptions for PLL_CTRL4
Bits
Bit Name
Settings
Description
Reset
Access
[6:3]
R
PLL integer setting.
0x0
RW
0000 Reserved
0001 Reserved
0010
0011
0100
0101
0110
0111
1000
2
3
4
5
6
7
8
Rev. C | Page 55 of 116
ADAU1772
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
[2:1]
X
PLL input clock divide ratio.
00 Pin clock input/1
01 Pin clock input/2
10 Pin clock input/3
11 Pin clock input/4
PLL type.
0x0
RW
0
PLL_TYPE
0x0
RW
0
1
Integer
Fractional
PLL LOCK FLAG REGISTER
Address: 0x0006, Reset: 0x00, Name: PLL_CTRL5
Table 36. Bit Descriptions for PLL_CTRL5
Bits
Bit Name
Settings
Description
Reset
Access
0
LOCK
Flag to indicate if the PLL is locked. This bit is read only.
0x0
R
0
1
PLL unlocked
PLL locked
CLKOUT SETTING SELECTION REGISTER
Address: 0x0007, Reset: 0x00, Name: CLKOUT_SEL
When Pin ADC_SDATA1/CLKOUT/MP6 is set to clock output mode, the frequency of the output clock is set here. CLKOUT can be used
to provide a master clock to another IC, the clock for digital microphones, or as the clock for the PDM output stream. The 12 MHz/24
MHz setting is used when clocking another IC, 3 MHz/6 MHz for PDMOUT, and 1.5 MHz/3 MHz when clocking digital microphones.
The CLKOUT frequency is derived from the master clock frequency, which is assumed to (and always should) be 12.288 MHz. The
12.288 MHz and 24.576 MHz output modes are not functional if PDM is enabled (Register PDM_OUT, Bits[1:0]).
Rev. C | Page 56 of 116
Data Sheet
ADAU1772
Table 37. Bit Descriptions for CLKOUT_SEL
Bits
Bit Name
Settings
Description
Reset
Access
[2:0]
CLKOUT_FREQ
CLKOUT pin frequency.
0x0
RW
000 Master clock × 2 (24.576 MHz)
001 Master clock (12.288 MHz)
010 Master clock/2 (6.144 MHz)
011 Master clock/4 (3.072 MHz)
100 Master clock/8 (1.536 MHz)
111 Clock output off = 0
REGULATOR CONTROL REGISTER
Address: 0x0008, Reset: 0x00, Name: REGULATOR
Table 38. Bit Descriptions for REGULATOR
Bits
Bit Name
Settings
Description
Reset
Access
2
REG_PD
Powers down LDO regulator.
Regulator active
Regulator powered down
Set regulator output voltage.
0x0
RW
0
1
[1:0]
REGV
0x0
RW
00 1.2 V
01 1.1 V
10 Reserved
11 Reserved
Rev. C | Page 57 of 116
ADAU1772
Data Sheet
CORE CONTROL REGISTER
Address: 0x0009, Reset: 0x04, Name: CORE_CONTROL
Table 39. Bit Descriptions for CORE_CONTROL
Bits
Bit Name
Settings
Description
Reset
Access
7
ZERO_STATE
Zeroes the state of the data memory during bank switching. When
switching active parameter banks between two settings, zeroing the state
of the bank prevents the new filter settings from being active on old data
that is recirculating in filters. Zeroing the state may prevent filter
instability or unwanted noises upon bank switching.
0x0
RW
0
1
Do not zero state during bank switch
Zero state during back switch
Selects active filter bank.
[6:5]
[2:1]
BANK_SL
CORE_FS
0x0
RW
00 Bank A active
01 Bank B active
10 Reserved
11 Reserved
This bit sets the core sample rate. This setting should not be changed
while the core is running. CORE_RUN must be set to 0 for this setting to be
updated.
00 Reserved
01 96 kHz
10 192 kHz
11 Reserved
0
CORE_RUN
Run bit for the core. This bit should only be enabled when the program
0x0
RW
and parameters are loaded and the sample rate settings have been set.
CORE_RUN starts and stops the core at the beginning of the program.
0
1
Core off
Core on
Rev. C | Page 58 of 116
Data Sheet
ADAU1772
FILTER ENGINE AND LIMITER CONTROL REGISTER
Address: 0x000B, Reset: 0x03, Name: CORE_ENABLE
Disabling the limiter only disables the attack operation. The decay operation is always active, so a limiter can be safely disabled while it
performs gain adjustments.
Table 40. Bit Descriptions for CORE_ENABLE
Bits
Bit Name
Settings
Description
Reset
Access
1
LIM_EN
Limiter enable. When the limiter function is disabled, a fixed max gain
setting is applied to instructions using the limiters.
0x1
RW
0
1
Disabled
Enabled
0
DSP_CLK_EN
Enable the clock to the core. Directly controls the clock to the core. It should
be set to 0 when the chip is used in a codec-only configuration, in which the
core is not used. Writing to any of the biquad coefficient registers (Parameter
Memory Address 0x0E0 to Address 0x2BF) is blocked until this bit is 1. This
bit should not be used to start or stop the core while it is running, because
it would immediately start or stop the core clock and not allow the program
to finish. Instead, use CORE_RUN in Register CORE_CONTROL to start or
stop the core.
0x1
RW
0
1
Core clock disabled
Core clock enabled
Rev. C | Page 59 of 116
ADAU1772
Data Sheet
DB VALUE REGISTER 0 READ
Address: 0x000C, Reset: 0x00, Name: DBREG0
The core can write data to this register, and the data is automatically converted to a level in dB. The most common usage is to determine
the rms value of a signal by taking the absolute value, and then performing low-pass filtering and moving the result to the DBREG0
register.
Table 41. Bit Descriptions for DBREG0
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DBVAL0
DB Value Register 0 read.
0x00
R
00000000 −96 dB
00010000 −90 dB
00100000 −84 dB
00110000 −78 dB
11100000 −12 dB
11110000 −6 dB
11111111 −0.375 dB
DB VALUE REGISTER 1 READ
Address: 0x000D, Reset: 0x00, Name: DBREG1
The core can write data to this register, and the data is automatically converted to a level in dB. The most common usage is to determine
the rms value of a signal by taking the absolute value, and then performing low-pass filtering and moving the result to the DBREG1
register.
Rev. C | Page 60 of 116
Data Sheet
ADAU1772
Table 42. Bit Descriptions for DBREG1
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DBVAL1
DB Value Register 1 read.
0x00
R
00000000 −96 dB
00010000 −90 dB
00100000 −84 dB
00110000 −78 dB
11100000 −12 dB
11110000 −6 dB
11111111 −0.375 dB
DB VALUE REGISTER 2 READ
Address: 0x000E, Reset: 0x00, Name: DBREG2
The core can write data to this register, and the data is automatically converted to a level in dB. The most common usage is to determine
the rms value of a signal by taking the absolute value, and then performing low-pass filtering and moving the result to the DBREG2
register.
Table 43. Bit Descriptions for DBREG2
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DBVAL2
DB Value Register 2 read.
0x00
R
00000000 −96 dB
00010000 −90 dB
00100000 −84 dB
00110000 −78 dB
11100000 −12 dB
11110000 −6 dB
11111111 −0.375 dB
Rev. C | Page 61 of 116
ADAU1772
Data Sheet
CORE CHANNEL 0/CORE CHANNEL 1 INPUT SELECT REGISTER
Address: 0x000F, Reset: 0x10, Name: CORE_IN_MUX_0_1
Table 44. Bit Descriptions for CORE_IN_MUX_0_1
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
CORE_IN_MUX_SEL_1
Core Input Channel 1 source.
0x1
RW
0000 AIN0/DMIC0
0001 AIN1/DMIC1
0010 AIN2/DMIC2
0011 AIN3/DMIC3
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Input ASRC Channel 0
1101 Input ASRC Channel 1
Core Input Channel 0 source.
0000 AIN0/DMIC0
0001 AIN1/DMIC1
0010 AIN2/DMIC2
0011 AIN3/DMIC3
0100 Reserved
[3:0]
CORE_IN_MUX_SEL_0
0x0
RW
0101 Reserved
0110 Reserved
0111 Reserved
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Input ASRC Channel 0
1101 Input ASRC Channel 1
Rev. C | Page 62 of 116
Data Sheet
ADAU1772
CORE CHANNEL 2/CORE CHANNEL 3 INPUT SELECT REGISTER
Address: 0x0010, Reset: 0x32, Name: CORE_IN_MUX_2_3
Table 45. Bit Descriptions for CORE_IN_MUX_2_3
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
CORE_IN_MUX_SEL_3
Core Input Channel 3 source.
0x3
RW
0000 AIN0/DMIC0
0001 AIN1/DMIC1
0010 AIN2/DMIC2
0011 AIN3/DMIC3
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Input ASRC Channel 0
1101 Input ASRC Channel 1
Core Input Channel 2 source.
0000 AIN0/DMIC0
0001 AIN1/DMIC1
0010 AIN2/DMIC2
0011 AIN3/DMIC3
0100 Reserved
[3:0]
CORE_IN_MUX_SEL_2
0x2
RW
0101 Reserved
0110 Reserved
0111 Reserved
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Input ASRC Channel 0
1101 Input ASRC Channel 1
Rev. C | Page 63 of 116
ADAU1772
Data Sheet
DAC INPUT SELECT REGISTER
Address: 0x0011, Reset: 0x10, Name: DAC_SOURCE_0_1
Table 46. Bit Descriptions for DAC_SOURCE_0_1
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
DAC_SOURCE1
DAC1 input source. This setting should not be changed while the core is
running. CORE_RUN must be set to 0 for this setting to be updated.
0x1
RW
0000 Core Output 0
0001 Core Output 1
0010 Core Output 2
0011 Core Output 3
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Input ASRC Channel 0
1101 Input ASRC Channel 1
[3:0]
DAC_SOURCE0
DAC0 input source. This setting should not be changed while the core is
running. CORE_RUN must be set to 0 for this setting to be updated.
0000 Core Output 0
0x0
RW
0001 Core Output 1
0010 Core Output 2
0011 Core Output 3
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Input ASRC Channel 0
1101 Input ASRC Channel 1
Rev. C | Page 64 of 116
Data Sheet
ADAU1772
PDM MODULATOR INPUT SELECT REGISTER
Address: 0x0012, Reset: 0x32, Name: PDM_SOURCE_0_1
Table 47. Bit Descriptions for PDM_SOURCE_0_1
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
PDM_SOURCE1
PDM Modulator Channel 1 input source.
0x3
RW
0000 Core Output 0
0001 Core Output 1
0010 Core Output 2
0011 Core Output 3
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Input ASRC Channel 0
1101 Input ASRC Channel 1
[3:0]
PDM_SOURCE0
PDM Modulator Channel 0 input source.
0x2
RW
0000 Core Output 0
0001 Core Output 1
0010 Core Output 2
0011 Core Output 3
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Input ASRC Channel 0
1101 Input ASRC Channel 1
Rev. C | Page 65 of 116
ADAU1772
Data Sheet
SERIAL DATA OUTPUT 0/SERIAL DATA OUTPUT 1 INPUT SELECT REGISTER
Address: 0x0013, Reset: 0x54, Name: SOUT_SOURCE_0_1
Table 48. Bit Descriptions for SOUT_SOURCE_0_1
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
SOUT_SOURCE1
Serial Data Output Channel 1 source select.
0x5
RW
0000 Reserved
0001 Reserved
0010 Reserved
0011 Reserved
0100 Output ASRC Channel 0
0101 Output ASRC Channel 1
0110 Output ASRC Channel 2
0111 Output ASRC Channel 3
1000 Serial Input 0
1001 Serial Input 1
1010 Serial Input 2
1011 Serial Input 3
1100 Serial Input 4
1101 Serial Input 5
1110 Serial Input 6
1111 Serial Input 7
[3:0]
SOUT_SOURCE0
Serial Data Output Channel 0 source select.
0000 Reserved
0x4
RW
0001 Reserved
0010 Reserved
0011 Reserved
0100 Output ASRC Channel 0
0101 Output ASRC Channel 1
0110 Output ASRC Channel 2
0111 Output ASRC Channel 3
1000 Serial Input 0
1001 Serial Input 1
1010 Serial Input 2
Rev. C | Page 66 of 116
Data Sheet
ADAU1772
Bits
Bit Name
Settings
Description
Reset
Access
1011 Serial Input 3
1100 Serial Input 4
1101 Serial Input 5
1110 Serial Input 6
1111 Serial Input 7
SERIAL DATA OUTPUT 2/SERIAL DATA OUTPUT 3 INPUT SELECT REGISTER
Address: 0x0014, Reset: 0x76, Name: SOUT_SOURCE_2_3
Table 49. Bit Descriptions for SOUT_SOURCE_2_3
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
SOUT_SOURCE3
Serial Data Output Channel 3 source select.
0x7
RW
0000 Reserved
0001 Reserved
0010 Reserved
0011 Reserved
0100 Output ASRC Channel 0
0101 Output ASRC Channel 1
0110 Output ASRC Channel 2
0111 Output ASRC Channel 3
1000 Serial Input 0
1001 Serial Input 1
1010 Serial Input 2
1011 Serial Input 3
1100 Serial Input 4
1101 Serial Input 5
1110 Serial Input 6
1111 Serial Input 7
[3:0]
SOUT_SOURCE2
Serial Data Output Channel 2 source select.
0000 Reserved
0x6
RW
0001 Reserved
0010 Reserved
Rev. C | Page 67 of 116
ADAU1772
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
0011 Reserved
0100 Output ASRC Channel 0
0101 Output ASRC Channel 1
0110 Output ASRC Channel 2
0111 Output ASRC Channel 3
1000 Serial Input 0
1001 Serial Input 1
1010 Serial Input 2
1011 Serial Input 3
1100 Serial Input 4
1101 Serial Input 5
1110 Serial Input 6
1111 Serial Input 7
SERIAL DATA OUTPUT 4/SERIAL DATA OUTPUT 5 INPUT SELECT REGISTER
Address: 0x0015, Reset: 0x54, Name: SOUT_SOURCE_4_5
Table 50. Bit Descriptions for SOUT_SOURCE_4_5
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
SOUT_SOURCE5
Serial Data Output Channel 5 source select.
0x5
RW
0000 Reserved
0001 Reserved
0010 Reserved
0011 Reserved
0100 Output ASRC Channel 0
0101 Output ASRC Channel 1
0110 Output ASRC Channel 2
0111 Output ASRC Channel 3
1000 Serial Input 0
1001 Serial Input 1
1010 Serial Input 2
1011 Serial Input 3
Rev. C | Page 68 of 116
Data Sheet
ADAU1772
Bits
Bit Name
Settings
Description
Reset
Access
1100 Serial Input 4
1101 Serial Input 5
1110 Serial Input 6
1111 Serial Input 7
[3:0]
SOUT_SOURCE4
Serial Data Output Channel 4 source select.
0x4
RW
0000 Reserved
0001 Reserved
0010 Reserved
0011 Reserved
0100 Output ASRC Channel 0
0101 Output ASRC Channel 1
0110 Output ASRC Channel 2
0111 Output ASRC Channel 3
1000 Serial Input 0
1001 Serial Input 1
1010 Serial Input 2
1011 Serial Input 3
1100 Serial Input 4
1101 Serial Input 5
1110 Serial Input 6
1111 Serial Input 7
SERIAL DATA OUTPUT 6/SERIAL DATA OUTPUT 7 INPUT SELECT REGISTER
Address: 0x0016, Reset: 0x76, Name: SOUT_SOURCE_6_7
Table 51. Bit Descriptions for SOUT_SOURCE_6_7
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
SOUT_SOURCE7
Serial Data Output Channel 7 source select.
0x7
RW
0000 Reserved
0001 Reserved
0010 Reserved
0011 Reserved
Rev. C | Page 69 of 116
ADAU1772
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
0100 Output ASRC Channel 0
0101 Output ASRC Channel 1
0110 Output ASRC Channel 2
0111 Output ASRC Channel 3
1000 Serial Input 0
1001 Serial Input 1
1010 Serial Input 2
1011 Serial Input 3
1100 Serial Input 4
1101 Serial Input 5
1110 Serial Input 6
1111 Serial Input 7
[3:0]
SOUT_SOURCE6
Serial Data Output Channel 6 source select.
0000 Reserved
0x6
RW
0001 Reserved
0010 Reserved
0011 Reserved
0100 Output ASRC Channel 0
0101 Output ASRC Channel 1
0110 Output ASRC Channel 2
0111 Output ASRC Channel 3
1000 Serial Input 0
1001 Serial Input 1
1010 Serial Input 2
1011 Serial Input 3
1100 Serial Input 4
1101 Serial Input 5
1110 Serial Input 6
1111 Serial Input 7
ADC_SDATA0/ADC_SDATA1 CHANNEL SELECT REGISTER
Address: 0x0017, Reset: 0x04, Name: ADC_SDATA_CH
Rev. C | Page 70 of 116
Data Sheet
ADAU1772
Table 52. Bit Descriptions for ADC_SDATA_CH
Bits
Bit Name
Settings
Description
Reset
Access
[3:2]
ADC_SDATA1_ST
SDATA1 output channel output select. Selects the output channel at which
ADC_SDATA1 starts to output data. The output port sequentially outputs
data following this start channel according to the setting of Bit SAI.
0x1
RW
00 Channel 0
01 Channel 2
10 Channel 4
11 Channel 6
[1:0]
ADC_SDATA0_ST
SDATA0 output channel output select. Selects the output channel at which
0x0
RW
ADC_SDATA0 starts to output data. The output port sequentially outputs
data following this start channel according to the setting of Bit SAI.
00 Channel 0
01 Channel 2
10 Channel 4
11 Channel 6
OUTPUT ASRC0/OUTPUT ASRC1 SOURCE REGISTER
Address: 0x0018, Reset: 0x10, Name: ASRCO_SOURCE_0_1
Table 53. Bit Descriptions for ASRCO_SOURCE_0_1
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
ASRC_OUT_SOURCE1
Output ASRC Channel 1 source select.
0x1
RW
0000 Core Output 0
0001 Core Output 1
0010 Core Output 2
0011 Core Output 3
0100 ADC0
0101 ADC1
0110 ADC2
0111 ADC3
1000 Serial Input 0
1001 Serial Input 1
1010 Serial Input 2
Rev. C | Page 71 of 116
ADAU1772
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
1011 Serial Input 3
1100 Serial Input 4
1101 Serial Input 5
1110 Serial Input 6
1111 Serial Input 7
[3:0]
ASRC_OUT_SOURCE0
Output ASRC Channel 0 source select.
0x0
RW
0000 Core Output 0
0001 Core Output 1
0010 Core Output 2
0011 Core Output 3
0100 ADC0
0101 ADC1
0110 ADC2
0111 ADC3
1000 Serial Input 0
1001 Serial Input 1
1010 Serial Input 2
1011 Serial Input 3
1100 Serial Input 4
1101 Serial Input 5
1110 Serial Input 6
1111 Serial Input 7
OUTPUT ASRC2/OUTPUT ASRC3 SOURCE REGISTER
Address: 0x0019, Reset: 0x32, Name: ASRCO_SOURCE_2_3
Table 54. Bit Descriptions for ASRCO_SOURCE_2_3
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
ASRC_OUT_SOURCE3
Output ASRC Channel 3 source select.
0x3
RW
0000 Core Output 0
0001 Core Output 1
0010 Core Output 2
0011 Core Output 3
Rev. C | Page 72 of 116
Data Sheet
ADAU1772
Bits
Bit Name
Settings
Description
Reset
Access
0100 ADC0
0101 ADC1
0110 ADC2
0111 ADC3
1000 Serial Input 0
1001 Serial Input 1
1010 Serial Input 2
1011 Serial Input 3
1100 Serial Input 4
1101 Serial Input 5
1110 Serial Input 6
1111 Serial Input 7
[3:0]
ASRC_OUT_SOURCE2
Output ASRC Channel 2 source select.
0x2
RW
0000 Core Output 0
0001 Core Output 1
0010 Core Output 2
0011 Core Output 3
0100 ADC0
0101 ADC1
0110 ADC2
0111 ADC3
1000 Serial Input 0
1001 Serial Input 1
1010 Serial Input 2
1011 Serial Input 3
1100 Serial Input 4
1101 Serial Input 5
1110 Serial Input 6
1111 Serial Input 7
INPUT ASRC CHANNEL SELECT REGISTER
Address: 0x001A, Reset: 0x00, Name: ASRC_MODE
Table 55. Bit Descriptions for ASRC_MODE
Bits
Bit Name
Settings
Description
Reset
Access
[3:2]
ASRC_IN_CH
Input ASRC channel select.
0x0
RW
00 Serial Input Port Channel 0/Serial Input Port Channel 1
01 Serial Input Port Channel 2/Serial Input Port Channel 3
Rev. C | Page 73 of 116
ADAU1772
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
10 Serial Input Port Channel 4/Serial Input Port Channel 5
11 Serial Input Port Channel 6/Serial Input Port Channel 7
Output ASRC enable.
1
ASRC_OUT_EN
ASRC_IN_EN
0x0
RW
0
1
Disabled
Enabled
0
Input ASRC enable.
Disabled
Enabled
0x0
RW
0
1
ADC0/ADC1 CONTROL 0 REGISTER
Address: 0x001B, Reset: 0x19, Name: ADC_CONTROL0
Table 56. Bit Descriptions for ADC_CONTROL0
Bits
Bit Name
Settings
Description
Reset
Access
4
ADC1_MUTE
Mute ADC1. Muting is accomplished by setting the volume control to
maximum attenuation. This bit has no effect if volume control is bypassed.
0x1
RW
0
1
Unmuted
Muted
3
ADC0_MUTE
ADC_0_1_FS
Mute ADC0. Muting is accomplished by setting the volume control to
maximum attenuation. This bit has no effect if volume control is bypassed.
Unmuted
0x1
0x1
RW
RW
0
1
Muted
[1:0]
Sets ADC sample rate.
00 96 kHz
01 192 kHz
10 Reserved
11 Reserved
Rev. C | Page 74 of 116
Data Sheet
ADAU1772
ADC2/ADC3 CONTROL 0 REGISTER
Address: 0x001C, Reset: 0x19, Name: ADC_CONTROL1
Table 57. Bit Descriptions for ADC_CONTROL1
Bits
Bit Name
Settings
Description
Mute ADC3.
Unmuted
Muted
Reset
Access
4
ADC3_MUTE
0x1
RW
0
1
3
ADC2_MUTE
ADC_2_3_FS
Mute ADC2. Muting is accomplished by setting the volume control to
maximum attenuation. This bit has no effect if volume control is bypassed.
Unmuted
0x1
0x1
RW
RW
0
1
Muted
[1:0]
Sets ADC sample rate.
00 96 kHz
01 192 kHz
10 Reserved
11 Reserved
Rev. C | Page 75 of 116
ADAU1772
Data Sheet
ADC0/ADC1 CONTROL 1 REGISTER
Address: 0x001D, Reset: 0x00, Name: ADC_CONTROL2
Table 58. Bit Descriptions for ADC_CONTROL2
Bits
Bit Name
Settings
Description
Reset
Access
[6:5]
HP_0_1_EN
High-pass filter settings.
0x0
RW
00 Off
01 1 Hz
10 4 Hz
11 8 Hz
4
3
2
1
DMIC_POL0
DMIC_SW0
DCM_0_1
Selects microphone polarity.
0 positive, 1 negative
1 positive, 0 negative
0x0
0x0
0x0
0x0
RW
RW
RW
RW
0
1
Digital microphone swap.
Channel swap off (left channel on rising edge, right channel on falling edge)
Swap left and right
0
1
Sets the input source to ADCs or digital microphones.
Decimator source set to ADC
Decimator source set to digital microphones
0
1
ADC_1_EN
Enable ADC1. This bit must be set in conjunction with the SINC_1_EN bit
in the DECIM_PWR_MODES register to fully enable or disable the ADC.
0
1
Disable
Enable
0
ADC_0_EN
Enable ADC0. This bit must be set in conjunction with the SINC_0_EN bit
in the DECIM_PWR_MODES register to fully enable or disable the ADC.
0x0
RW
0
1
Disable
Enable
Rev. C | Page 76 of 116
Data Sheet
ADAU1772
ADC2/ADC3 CONTROL 1 REGISTER
Address: 0x001E, Reset: 0x00, Name: ADC_CONTROL3
Table 59. Bit Descriptions for ADC_CONTROL3
Bits
Bit Name
Settings
Description
Reset
Access
[6:5]
HP_2_3_EN
High-pass filter settings.
0x0
RW
00 Off
01 1 Hz
10 4 Hz
11 8 Hz
4
3
2
1
DMIC_POL1
DMIC_SW1
DCM_2_3
Microphone polarity.
0 positive, 1 negative
1 positive, 0 negative
0x0
0x0
0x0
0x0
RW
RW
RW
RW
0
1
Digital microphone swap.
Channel swap off (left channel on rising edge, right channel on falling edge)
Swap left and right
0
1
Sets the input source to ADCs or digital microphones.
Decimator source set to ADC
Decimator source set to digital microphone
0
1
ADC_3_EN
Enable ADC3. This bit must be set in conjunction with the SINC_3_EN bit
in the DECIM_PWR_MODES register to fully enable or disable the ADC.
0
1
Disable
Enable
0
ADC_2_EN
Enable ADC2. This bit must be set in conjunction with the SINC_2_EN bit
in the DECIM_PWR_MODES register to fully enable or disable the ADC.
0x0
RW
0
1
Disable
Enable
Rev. C | Page 77 of 116
ADAU1772
Data Sheet
ADC0 VOLUME CONTROL REGISTER
Address: 0x001F, Reset: 0x00, Name: ADC0_VOLUME
When SINC_0_EN is set, the volume starts to ramp from −95.625 dB to the value in this register. The volume ramp time is (number of
steps) × 16/fS, where there are 256 steps between 0 dB and −95.625 dB. For example, with fS = 192 kHz, the volume ramps from −95.625 dB
to 0 dB in 21 ms.
Table 60. Bit Descriptions for ADC0_VOLUME
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
ADC_0_VOL
ADC0 volume setting.
0x00
RW
00000000 0 dB
00000001 −0.375 dB
11111111 −95.625 dB
ADC1 VOLUME CONTROL REGISTER
Address: 0x0020, Reset: 0x00, Name: ADC1_VOLUME
When SINC_1_EN is set, the volume starts to ramp from −95.625 dB to the value in this register. The volume ramp time is (number of
steps) × 16/fS, where there are 256 steps between 0 dB and −95.625 dB. For example, with fS = 192 kHz, the volume ramps from −95.625 dB
to 0 dB in 21 ms.
Table 61. Bit Descriptions for ADC1_VOLUME
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
ADC_1_VOL
ADC1 volume setting.
0x00
RW
00000000 0 dB
00000001 −0.375 dB
11111111 −95.625 dB
Rev. C | Page 78 of 116
Data Sheet
ADAU1772
ADC2 VOLUME CONTROL REGISTER
Address: 0x0021, Reset: 0x00, Name: ADC2_VOLUME
When SINC_2_EN is set, the volume starts to ramp from −95.625 dB to the value in this register. The volume ramp time is (number of
steps) × 16/fS, where there are 256 steps between 0 dB and −95.625 dB. For example, with fS = 192 kHz, the volume ramps from −95.625 dB
to 0 dB in 21 ms.
Table 62. Bit Descriptions for ADC2_VOLUME
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
ADC_2_VOL
ADC2 volume setting.
0x00
RW
00000000 0 dB
00000001 −0.375 dB
11111111 −95.625 dB
ADC3 VOLUME CONTROL REGISTER
Address: 0x0022, Reset: 0x00, Name: ADC3_VOLUME
When SINC_3_EN is set, the volume starts to ramp from −95.625 dB to the value in this register. The volume ramp time is (number of
steps) × 16/fS, where there are 256 steps between 0 dB and −95.625 dB. For example, with fS = 192 kHz, the volume ramps from −95.625 dB
to 0 dB in 21 ms.
Table 63. Bit Descriptions for ADC3_VOLUME
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
ADC_3_VOL
ADC3 volume setting.
0x00
RW
00000000 0 dB
00000001 −0.375 dB
11111111 −95.625 dB
Rev. C | Page 79 of 116
ADAU1772
Data Sheet
PGA CONTROL 0 REGISTER
Address: 0x0023, Reset: 0x40, Name: PGA_CONTROL_0
This register controls the PGA connected to AIN0.
Table 64. Bit Descriptions for PGA_CONTROL_0
Bits
Bit Name
Settings
Description
Reset
Access
7
PGA_EN0
Select line or microphone input. Note that the PGA inverts the signal
going through it.
0x0
RW
0
1
AIN0 used as a single-ended line input. PGA powered down.
AIN0 used as a single-ended microphone input. PGA powered up with
slewing.
6
PGA_MUTE0
PGA_GAIN0
Enable PGA mute. When PGA is muted, PGA_GAIN0 is ignored.
Unmuted
Muted
0x1
0x0
RW
RW
0
1
[5:0]
Set the gain of PGA0.
000000 −12 dB
000001 −11.25 dB
010000 0 dB
111110 +34.5 dB
111111 +35.25 dB
PGA CONTROL 1 REGISTER
Address: 0x0024, Reset: 0x40, Name: PGA_CONTROL_1
This register controls the PGA connected to AIN1.
Rev. C | Page 80 of 116
Data Sheet
ADAU1772
Table 65. Bit Descriptions for PGA_CONTROL_1
Bits
Bit Name
Settings
Description
Reset
Access
7
PGA_EN1
Select line or microphone input. Note that the PGA inverts the signal
going through it.
0x0
RW
0
1
AIN1 used as a single-ended line input. PGA powered down.
AIN1 used as a single-ended microphone input. PGA powered up with
slewing.
6
PGA_MUTE1
PGA_GAIN1
Enable PGA1 mute. When PGA is muted, PGA_GAIN1 is ignored.
Unmuted
Muted
0x1
0x0
RW
RW
0
1
[5:0]
Set the gain of PGA1.
000000 −12 dB
000001 −11.25 dB
010000 0 dB
111110 +34.5 dB
111111 +35.25 dB
PGA CONTROL 2 REGISTER
Address: 0x0025, Reset: 0x40, Name: PGA_CONTROL_2
This register controls the PGA connected to AIN2.
Table 66. Bit Descriptions for PGA_CONTROL_2
Bits
Bit Name
Settings
Description
Reset
Access
7
PGA_EN2
Select line or microphone input. Note that the PGA inverts the signal
going through it.
0x0
RW
0
1
AIN2 used as a single-ended line input. PGA powered down.
AIN2 used as a single-ended microphone input. PGA powered up with
slewing.
6
PGA_MUTE2
PGA_GAIN2
Enable PGA2 mute. When PGA is muted, PGA_GAIN2 is ignored.
Unmuted
Muted
0x1
0x0
RW
RW
0
1
[5:0]
Set the gain of PGA2.
000000 −12 dB
000001 −11.25 dB
010000 0 dB
111110 +34.5 dB
111111 +35.25 dB
Rev. C | Page 81 of 116
ADAU1772
Data Sheet
PGA CONTROL 3 REGISTER
Address: 0x0026, Reset: 0x40, Name: PGA_CONTROL_3
This register controls the PGA connected to AIN3.
Table 67. Bit Descriptions for PGA_CONTROL_3
Bits
Bit Name
Settings
Description
Reset
Access
7
PGA_EN3
Select line or microphone input. Note that the PGA inverts the signal
going through it.
0x0
RW
0
1
AIN3 used as a single-ended line input. PGA powered down.
AIN3 used as a single-ended microphone input. PGA powered up with
slewing.
6
PGA_MUTE3
PGA_GAIN3
Enable PGA3 mute. When PGA is muted, PGA_GAIN3 is ignored.
Unmuted
Muted
0x1
0x0
RW
RW
0
1
[5:0]
Set the gain of PGA3.
000000 −12 dB
000001 −11.25 dB
010000 0 dB
111110 +34.5 dB
111111 +35.25 dB
Rev. C | Page 82 of 116
Data Sheet
ADAU1772
PGA SLEW CONTROL REGISTER
Address: 0x0027, Reset: 0x00, Name: PGA_STEP_CONTROL
If PGA slew is disabled with the SLEW_PDx controls, the SLEW_RATE parameter is ignored for that PGA block.
Table 68. Bit Descriptions for PGA_STEP_CONTROL
Bits
Bit Name
Settings
Description
Reset
Access
[5:4]
SLEW_RATE
Controls how fast the PGA is slewed when changing gain.
0x0
RW
00 21.5 ms
01 42.5 ms
10 85 ms
3
2
1
0
SLEW_PD3
SLEW_PD2
SLEW_PD1
SLEW_PD0
PGA3 slew disable.
0x0
0x0
0x0
0x0
RW
RW
RW
RW
0
1
PGA slew enabled
PGA slew disabled
PGA2 slew disable.
PGA slew enabled
PGA slew disabled
PGA1 slew disable.
PGA slew enabled
PGA slew disabled
PGA0 slew disable.
PGA slew enabled
PGA slew disabled
0
1
0
1
0
1
Rev. C | Page 83 of 116
ADAU1772
Data Sheet
PGA 10 dB GAIN BOOST REGISTER
Address: 0x0028, Reset: 0x00, Name: PGA_10DB_BOOST
Each PGA can have an additional +10 dB gain added, making the PGA gain range −2 dB to +46 dB.
Table 69. Bit Descriptions for PGA_10DB_BOOST
Bits
Bit Name
Settings
Description
Reset
Access
3
PGA_3_BOOST
Boost control for PGA3.
0x0
RW
0
1
Default PGA gain set in Register PGA_CONTROL_3
Additional 10 dB gain above setting in Register PGA_CONTROL_3
Boost control for PGA2.
2
1
0
PGA_2_BOOST
PGA_1_BOOST
PGA_0_BOOST
0x0
0x0
0x0
RW
RW
RW
0
1
Default PGA gain set in Register PGA_CONTROL_2
Additional 10 dB gain above setting in Register PGA_CONTROL_2
Boost control for PGA1.
Default PGA gain set in Register PGA_CONTROL_1
Additional 10 dB gain above setting in Register PGA_CONTROL_1
Boost control for PGA0.
0
1
0
1
Default PGA gain set in Register PGA_CONTROL_0
Additional 10 dB gain above setting in Register PGA_CONTROL_0
Rev. C | Page 84 of 116
Data Sheet
ADAU1772
INPUT AND OUTPUT CAPACITOR CHARGING REGISTER
Address: 0x0029, Reset: 0x3F, Name: POP_SUPPRESS
Table 70. Bit Descriptions for POP_SUPPRESS
Bits
Bit Name
Settings
Description
Reset
Access
5
HP_POP_DIS1
Disable pop suppression on Headphone Output 1.
0x1
RW
0
1
Enabled
Disabled
4
3
2
1
0
HP_POP_DIS0
PGA_POP_DIS3
PGA_POP_DIS2
PGA_POP_DIS1
PGA_POP_DIS0
Disable pop suppression on Headphone Output 0.
Enabled
Disabled
0x1
0x1
0x1
0x1
0x1
RW
RW
RW
RW
RW
0
1
Disable pop suppression on PGA3 input.
Enabled
Disabled
0
1
Disable pop suppression on PGA2 input.
Enabled
Disabled
0
1
Disable pop suppression on PGA1 input.
Enabled
Disabled
0
1
Disable pop suppression on PGA0 input.
0
1
Enabled
Disabled
Rev. C | Page 85 of 116
ADAU1772
Data Sheet
DSP BYPASS PATH REGISTER
Address: 0x002A, Reset: 0x00, Name: TALKTHRU
Table 71. Bit Descriptions for TALKTHRU
Bits
Bit Name
Settings
Description
Reset
Access
[1:0]
TALKTHRU_PATH
Signal path when DSP bypass is enabled.
0x0
RW
00 No DSP bypass
01 ADC0 to DAC0
10 ADC1 to DAC1
11 ADC0 and ADC1 to DAC0 and DAC1
DSP BYPASS GAIN FOR PGA0 REGISTER
Address: 0x002B, Reset: 0x00, Name: TALKTHRU_GAIN0
Table 72. Bit Descriptions for TALKTHRU_GAIN0
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
TALKTHRU_GAIN0_VAL
Sets the DAC0 volume when DSP bypass mode is enabled.
0x00
RW
DSP BYPASS GAIN FOR PGA1 REGISTER
Address: 0x002C, Reset: 0x00, Name: TALKTHRU_GAIN1
Table 73. Bit Descriptions for TALKTHRU_GAIN1
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
TALKTHRU_GAIN1_VAL
Sets the DAC1 volume when DSP bypass mode is enabled.
0x00
RW
Rev. C | Page 86 of 116
Data Sheet
ADAU1772
MIC_BIAS0_1 CONTROL REGISTER
Address: 0x002D, Reset: 0x00, Name: MIC_BIAS
Table 74. Bit Descriptions for MIC_BIAS
Bits
Bit Name
Settings
Description
Reset
Access
5
MIC_EN1
MICBIAS1 output enable.
Disabled
Enabled
0x0
RW
0
1
4
1
0
MIC_EN0
MICBIAS0 output enable.
Disabled
Enabled
0x0
0x0
0x0
RW
RW
RW
0
1
MIC_GAIN1
MIC_GAIN0
Level of the MICBIAS1 output.
0.9 × AVDD
0.65 × AVDD
0
1
Level of the MICBIAS0 output.
0.9 × AVDD
0.65 × AVDD
0
1
DAC CONTROL REGISTER
Address: 0x002E, Reset: 0x18, Name: DAC_CONTROL1
Rev. C | Page 87 of 116
ADAU1772
Data Sheet
Table 75. Bit Descriptions for DAC_CONTROL1
Bits
Bit Name
Settings
Description
Invert input polarity.
Normal
Reset
Access
5
DAC_POL
0x0
RW
0
1
Inverted
4
3
1
0
DAC1_MUTE
DAC0_MUTE
DAC1_EN
Mute DAC1.
Unmuted
Muted
0x1
0x1
0x0
0x0
RW
RW
RW
RW
0
1
Mute DAC0.
Unmuted
Muted
0
1
Enable DAC1.
Disable DAC1
Enable DAC1
Enable DAC0.
Disable DAC0
Enable DAC0
0
1
DAC0_EN
0
1
DAC0 VOLUME CONTROL REGISTER
Address: 0x002F, Reset: 0x00, Name: DAC0_VOLUME
Table 76. Bit Descriptions for DAC0_VOLUME
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC_0_VOL
DAC0 volume setting.
0x00
RW
00000000 0 dB
00000001 −0.375 dB
11111111 −95.625 dB
DAC1 VOLUME CONTROL REGISTER
Address: 0x0030, Reset: 0x00, Name: DAC1_VOLUME
Rev. C | Page 88 of 116
Data Sheet
ADAU1772
Table 77. Bit Descriptions for DAC1_VOLUME
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC_1_VOL
DAC1 volume setting.
0x00
RW
00000000 0 dB
00000001 −0.375 dB
11111111 −95.625 dB
HEADPHONE OUTPUT MUTES REGISTER
Address: 0x0031, Reset: 0x0F, Name: OP_STAGE_MUTES
Table 78. Bit Descriptions for OP_STAGE_MUTES
Bits
Bit Name
Settings
Description
Reset
Access
[3:2]
HP_MUTE_R
Mute the right output pins. When a pin is muted, it can be used as a
common-mode output.
0x3
RW
00 Outputs unmuted
01 HPOUTRP/LOUTRP muted, HPOUTRN/LOUTRN unmuted
10 HPOUTRP/LOUTRP unmuted, HPOUTRN/LOUTRN muted
11 Both output pins muted
[1:0]
HP_MUTE_L
Mute the left output pins. When a pin is muted, it can be used as a
common-mode output.
0x3
RW
00 Outputs unmuted
01 HPOUTLP/LOUTLP muted, HPOUTLN/LOUTLN unmuted
10 HPOUTLP/LOUTLP unmuted, HPOUTLN/LOUTLN muted
11 Both output pins muted
Rev. C | Page 89 of 116
ADAU1772
Data Sheet
SERIAL PORT CONTROL 0 REGISTER
Address: 0x0032, Reset: 0x00, Name: SAI_0
Using 16-bit serial I/O limits device performance.
Table 79. Bit Descriptions for SAI_0
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
SDATA_FMT
Serial data format.
0x0
RW
00 TDM, I2S—data delayed from edge of LRCLK by 1 BCLK cycle
01 TDM, left justified—data synchronized to edge of LRCLK
10 Right justified, 24-bit data
11 Right justified, 16-bit data
Serial port mode.
[5:4]
[3:0]
SAI
0x0
0x0
RW
RW
00 Stereo (I2S, left justified, right justified)
01 TDM2
10 TDM4
11 TDM8
SER_PORT_FS
Sampling rate on the serial ports.
0000 48 kHz
0001 8 kHz
0010 12 kHz
0011 16 kHz
0100 24 kHz
0101 32 kHz
0110 96 kHz
0111 192 kHz
Rev. C | Page 90 of 116
Data Sheet
ADAU1772
SERIAL PORT CONTROL 1 REGISTER
Address: 0x0033, Reset: 0x00, Name: SAI_1
Using 16-bit serial I/O limits device performance.
Table 80. Bit Descriptions for SAI_1
Bits
Bit Name
Settings
Description
Reset
Access
7
TDM_TS
Select whether to tristate unused TDM channels or to actively drive these
data slots.
0x0
RW
0
1
Unused outputs driven
Unused outputs tristated
6
5
4
3
2
1
0
BCLK_TDMC
LR_MODE
LR_POL
Bit width in TDM mode.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
RW
0
1
24-bit data in each TDM channel
16-bit data in each TDM channel
Sets LRCLK mode.
50% duty cycle clock
Pulse—LRCLK is a single BCLK cycle wide pulse
Sets LRCLK polarity.
50%: when LRCLK goes low and then high, pulse mode is short positive pulse
50%: when LRCLK goes high and then low, pulse mode is short negative pulse
Sets data to be input/output either MSB or LSB first.
MSB first data
0
1
0
1
SAI_MSB
BCLKRATE
BCLKEDGE
SAI_MS
0
1
LSB first data
Sets the number of bit clock cycles per data channel.
32 BCLK cycles/channel
16 BCLK cycles/channel
0
1
Sets the bit clock edge on which data changes.
Data changes on falling edge
Data changes on rising edge
0
1
Sets the serial port into master or slave mode.
LRCLK/BCLK slave
LRCLK/BCLK master
0
1
Rev. C | Page 91 of 116
ADAU1772
Data Sheet
TDM OUTPUT CHANNEL DISABLE REGISTER
Address: 0x0034, Reset: 0x00, Name: SOUT_CONTROL0
This register is for use only in TDM mode.
Table 81. Bit Descriptions for SOUT_CONTROL0
Bits
Bit Name
Settings
Description
Reset
Access
7
TDM7_DIS
Disable data in TDM Output Slot 7.
Output channel enabled
Output channel disabled
Disable data in TDM Output Slot 6.
Output channel enabled
Output channel disabled
Disable data in TDM Output Slot 5.
Output channel enabled
Output channel disabled
Disable data in TDM Output Slot 4.
Output channel enabled
Output channel disabled
Disable data in TDM Output Slot 3.
Output channel enabled
Output channel disabled
Disable data in TDM Output Slot 2.
Output channel enabled
Output channel disabled
Disable data in TDM Output Slot 1.
Output channel enabled
Output channel disabled
Disable data in TDM Output Slot 0.
Output channel enabled
0x0
RW
0
1
6
5
4
3
2
1
0
TDM6_DIS
TDM5_DIS
TDM4_DIS
TDM3_DIS
TDM2_DIS
TDM1_DIS
TDM0_DIS
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
RW
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output channel disabled
Rev. C | Page 92 of 116
Data Sheet
ADAU1772
PDM ENABLE REGISTER
Address: 0x0036, Reset: 0x00, Name: PDM_OUT
Table 82. Bit Descriptions for PDM_OUT
Bits
Bit Name
Settings
Description
Reset
Access
4
PDM_CTRL
Enable the control pattern in the PDM data stream.
0x0
RW
0
1
Disabled
Enabled
[3:2]
[1:0]
PDM_CH
PDM_EN
Selects the channel on which the control patterns are written. These
control bits should not be changed while the PDM channel is operating
and transmitting audio.
0x0
RW
00 Both channels
01 Left channel
10 Right channel
11 Reserved
Enable PDM output on Pin PDMOUT.
0x0
RW
00 PDM disabled
01 PDM left signal in both PDM channels
10 PDM right signal in both PDM channels
11 PDM stereo
Rev. C | Page 93 of 116
ADAU1772
Data Sheet
PDM PATTERN SETTING REGISTER
Address: 0x0037, Reset: 0x00, Name: PDM_PATTERN
Table 83. Bit Descriptions for PDM_PATTERN
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PAT TERN
PDM pattern byte. The PDM pattern byte should not be changed while
the PDM channel is operating and transmitting the pattern.
0x00
RW
MP0 FUNCTION SETTING REGISTER
Address: 0x0038, Reset: 0x00, Name: MODE_MP0
Table 84. Bit Descriptions for MODE_MP0
Bits
Bit Name
Settings
Description
Reset
Access
[4:0]
MODE_MP0_VAL
Sets the function of Pin DAC_SDATA/MP0.
0x00
RW
00000 Serial Input 0
00001 Mute ADC0
00010 Mute ADC1
00011 Mute ADC2
00100 Mute ADC3
00101 Mute ADC0 and ADC1
00110 Mute ADC2 and ADC3
00111 Mute all ADCs
01000 Mute DAC0
01001 Mute DAC1
01010 Mute both DACs
Rev. C | Page 94 of 116
Data Sheet
ADAU1772
Bits
Bit Name
Settings
Description
Reset
Access
01011 A/B bank switch
01100 Reserved
01101 Reserved
01110 Enable compression
01111 DSP bypass enable
10000 Push-button volume up
10001 Push-button volume down
MP1 FUNCTION SETTING REGISTER
Address: 0x0039, Reset: 0x10, Name: MODE_MP1
Table 85. Bit Descriptions for MODE_MP1
Bits
Bit Name
Settings
Description
Reset
Access
[4:0]
MODE_MP1_VAL
Sets the function of Pin ADC_SDATA0/PDMOUT/MP1.
0x10
RW
00000 Serial Output 0
00001 Mute ADC0
00010 Mute ADC1
00011 Mute ADC2
00100 Mute ADC3
00101 Mute ADC0 and ADC1
00110 Mute ADC2 and ADC3
00111 Mute all ADCs
01000 Mute DAC0
01001 Mute DAC1
01010 Mute both DACs
01011 A/B bank switch
01100 Reserved
01101 Reserved
01110 Enable compression
01111 DSP bypass enable
Rev. C | Page 95 of 116
ADAU1772
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
10000 Push-button volume up
10001 Push-button volume down
10010 PDM modulator output
MP2 FUNCTION SETTING REGISTER
Address: 0x003A, Reset: 0x00, Name: MODE_MP2
Table 86. Bit Descriptions for MODE_MP2
Bits
Bit Name
Settings
Description
Reset
Access
[4:0]
MODE_MP2_VAL
Sets the function of Pin BCLK/MP2.
0x00
RW
00000 Bit clock
00001 Mute ADC0
00010 Mute ADC1
00011 Mute ADC2
00100 Mute ADC3
00101 Mute ADC0 and ADC1
00110 Mute ADC2 and ADC3
00111 Mute all ADCs
01000 Mute DAC0
01001 Mute DAC1
01010 Mute both DACs
01011 A/B bank switch
01100 Reserved
01101 Reserved
01110 Enable compression
01111 DSP bypass enable
10000 Push-button volume up
10001 Push-button volume down
Rev. C | Page 96 of 116
Data Sheet
ADAU1772
MP3 FUNCTION SETTING REGISTER
Address: 0x003B, Reset: 0x00, Name: MODE_MP3
Table 87. Bit Descriptions for MODE_MP3
Bits
Bit Name
Settings
Description
Reset
Access
[4:0]
MODE_MP3_VAL
Sets the function of Pin LRCLK/MP3.
0x00
RW
00000 Left/right clock
00001 Mute ADC0
00010 Mute ADC1
00011 Mute ADC2
00100 Mute ADC3
00101 Mute ADC0 and ADC1
00110 Mute ADC2 and ADC3
00111 Mute all ADCs
01000 Mute DAC0
01001 Mute DAC1
01010 Mute both DACs
01011 A/B bank switch
01100 Reserved
01101 Reserved
01110 Enable compression
01111 DSP bypass enable
10000 Push-button volume up
10001 Push-button volume down
Rev. C | Page 97 of 116
ADAU1772
Data Sheet
MP4 FUNCTION SETTING REGISTER
Address: 0x003C, Reset: 0x00, Name: MODE_MP4
Table 88. Bit Descriptions for MODE_MP4
Bits
Bit Name
Settings
Description
Reset
Access
[4:0]
MODE_MP4_VAL
Sets the function of Pin DMIC0_1/MP4.
0x00
RW
00000 Digital Microphone Input Channel 0/Digital Microphone Input Channel 1
00001 Mute ADC0
00010 Mute ADC1
00011 Mute ADC2
00100 Mute ADC3
00101 Mute ADC0 and ADC1
00110 Mute ADC2 and ADC3
00111 Mute all ADCs
01000 Mute DAC0
01001 Mute DAC1
01010 Mute both DACs
01011 A/B bank switch
01100 Reserved
01101 Reserved
01110 Enable compression
01111 DSP bypass enable
10000 Push-button volume up
10001 Push-button volume down
Rev. C | Page 98 of 116
Data Sheet
ADAU1772
MP5 FUNCTION SETTING REGISTER
Address: 0x003D, Reset: 0x00, Name: MODE_MP5
Table 89. Bit Descriptions for MODE_MP5
Bits
Bit Name
Settings
Description
Reset
Access
[4:0]
MODE_MP5_VAL
Sets the function of Pin DMIC2_3/MP5.
0x00
RW
00000 Digital Microphone Input Channel 2/Digital Microphone Input Channel 3
00001 Mute ADC0
00010 Mute ADC1
00011 Mute ADC2
00100 Mute ADC3
00101 Mute ADC0 and ADC1
00110 Mute ADC2 and ADC3
00111 Mute all ADCs
01000 Mute DAC0
01001 Mute DAC1
01010 Mute both DACs
01011 A/B bank switch
01100 Reserved
01101 Reserved
01110 Enable compression
01111 DSP bypass enable
10000 Push-button volume up
10001 Push-button volume down
Rev. C | Page 99 of 116
ADAU1772
Data Sheet
MP6 FUNCTION SETTING REGISTER
Address: 0x003E, Reset: 0x11, Name: MODE_MP6
Table 90. Bit Descriptions for MODE_MP6
Bits
Bit Name
Settings
Description
Reset
Access
[4:0]
MODE_MP6_VAL
Sets the function of Pin ADC_SDATA1/CLKOUT/MP6.
0x11
RW
00000 Serial Output 1
00001 Mute ADC0
00010 Mute ADC1
00011 Mute ADC2
00100 Mute ADC3
00101 Mute ADC0 and ADC1
00110 Mute ADC2 and ADC3
00111 Mute all ADCs
01000 Mute DAC0
01001 Mute DAC1
01010 Mute both DACs
01011 A/B bank switch
01100 Reserved
01101 Reserved
01110 Enable compression
01111 DSP bypass enable
10000 Push-button volume up
10001 Push-button volume down
10010 Clock output
Rev. C | Page 100 of 116
Data Sheet
ADAU1772
PUSH-BUTTON VOLUME SETTINGS REGISTER
Address: 0x003F, Reset: 0x00, Name: PB_VOL_SET
This register must be written before Bits PB_VOL_CONV_VAL are set to something other than the default value. Otherwise, the push-
button volume control is initialized to −96 dB.
Table 91. Bit Descriptions for PB_VOL_SET
Bits
Bit Name
Settings
Description
Reset
Access
[7:3]
PB_VOL_INIT_VAL
Sets the initial volume of the push-button volume control. Each increment of
this register attenuates the level by 1.5 dB, from 0 dB to −46.5 dB.
0x00
RW
00000 0.0 dB
00001 −1.5 dB
11111 −46.5 dB
[2:0]
HOLD
Sets the length of time that the button is held before the volume ramp
0x0
RW
begins.
000 150 ms
001 300 ms
010 450 ms
011 600 ms
100 900 ms
101 1200 ms
Rev. C | Page 101 of 116
ADAU1772
Data Sheet
PUSH-BUTTON VOLUME CONTROL ASSIGNMENT REGISTER
Address: 0x0040, Reset: 0x87, Name: PB_VOL_CONV
Table 92. Bit Descriptions for PB_VOL_CONV
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
GAINSTEP
Sets the gain step for each press of the volume control button.
0x2
RW
00 0.375 dB/press
01 1.5 dB/press
10 3.0 dB/press
11 4.5 dB/press
[5:3]
RAMPSPEED
Sets the speed in dB/sec at which the volume control ramps when a
button is pressed.
000 60 dB/sec
0x0
RW
001 48 dB/sec
010 36 dB/sec
011 30 dB/sec
100 24 dB/sec
101 18 dB/sec
110 12 dB/sec
111 6 dB/sec
[2:0]
PB_VOL_CONV_VAL
Converters controlled by push-button volume. The push-button volume 0x7
RW
control is enabled when these bits are set to something other than the
default setting (111). When set to 111, the push-button volume is
disabled and the converter volumes are set by the ADCx_VOLUME and
DACx_VOLUME registers.
000 ADC0 and ADC1
001 ADC2 and ADC3
010 All ADCs
011 DAC0 and DAC1
100 DAC0
101 DAC1
110 Reserved
111 None (default)
Rev. C | Page 102 of 116
Data Sheet
ADAU1772
DEBOUNCE MODES REGISTER
Address: 0x0041, Reset: 0x05, Name: DEBOUNCE_MODE
Table 93. Bit Descriptions for DEBOUNCE_MODE
Bits
Bit Name
Settings
Description
Reset
Access
[2:0]
DEBOUNCE
The debounce time setting for the MPx inputs.
0x5
RW
000 Debounce 300 µs
001 Debounce 600 µs
010 Debounce 900 µs
011 Debounce 5 ms
100 Debounce 10 ms
101 Debounce 20 ms
110 Debounce 40 ms
111 No debounce
HEADPHONE LINE OUTPUT SELECT REGISTER
Address: 0x0043, Reset: 0x0F, Name: OP_STAGE_CTRL
Rev. C | Page 103 of 116
ADAU1772
Data Sheet
Table 94. Bit Descriptions for OP_STAGE_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
5
HP_EN_R
Sets the right channel in line output or headphone mode.
Right output in line output mode
Right output in headphone mode
0x0
RW
0
1
4
HP_EN_L
Sets the left channel in line output or headphone mode.
Left output in line output mode
Left output in headphone output mode
0x0
0x3
RW
RW
0
1
[3:2]
HP_PDN_R
Output stage power control. Powers down the right output stage, regardless
of whether the device is in line output or headphone mode. After enabling
the headphone output, wait at least 6 ms before unmuting the headphone
output by setting HP_MUTE_R in the OP_STAGE_MUTES register to 00.
00 HPOUTRN/LOUTRN and HPOUTRP/LOUTRP outputs enabled
01 HPOUTRN/LOUTRN enabled, HPOUTRP/LOUTRP disabled
10 HPOUTRN/LOUTRN disabled, HPOUTRP/LOUTRP enabled
11 Right output stages powered down
[1:0]
HP_PDN_L
Output stage power control. Powers down the left output stage, regardless
of whether the device is in line output or headphone mode. After enabling
the headphone output, wait at least 6 ms before unmuting the headphone
output by setting HP_MUTE_L in the OP_STAGE_MUTES register to 00.
0x3
RW
00 HPOUTLN/LOUTLN and HPOUTLP/LOUTLP outputs enabled
01 HPOUTLN/LOUTLN enabled, HPOUTLP/LOUTLP disabled
10 HPOUTLN/LOUTLN disabled, HPOUTLP/LOUTLP enabled
11 Left output stages powered down
Rev. C | Page 104 of 116
Data Sheet
ADAU1772
DECIMATOR POWER CONTROL REGISTER
Address: 0x0044, Reset: 0x00, Name: DECIM_PWR_MODES
These bits enable clocks to the digital filters and ASRC decimator filters of the ADCs. These bits must be enabled for all channels that will be used
in the design. To use the ADCs, these SINC_x_EN bits must be enabled along with the appropriate ADC_x_EN bits in the ADC_CONTROL2
and ADC_CONTROL3 registers. If the digital microphone inputs are used, the SINC_x_EN bits can be set without setting ADC_x_EN.
Table 95. Bit Descriptions for DECIM_PWR_MODES
Bits
Bit Name
Settings
Description
Reset
Access
7
DEC_3_EN
Control power to the ASRC3 decimator.
Powered down
Powered up
0x0
RW
0
1
6
5
4
3
2
1
0
DEC_2_EN
DEC_1_EN
DEC_0_EN
SINC_3_EN
SINC_2_EN
SINC_1_EN
SINC_0_EN
Control power to the ASRC2 decimator.
Powered down
Powered up
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
RW
0
1
Control power to the ASRC1 decimator.
Powered down
Powered up
0
1
Control power to the ASRC0 decimator.
Powered down
Powered up
0
1
ADC3 filter power control.
Powered down
Powered up
0
1
ADC2 filter power control.
Powered down
Powered up
0
1
ADC1 filter power control.
Powered down
Powered up
0
1
ADC0 filter power control.
Powered down
Powered up
0
1
Rev. C | Page 105 of 116
ADAU1772
Data Sheet
ASRC INTERPOLATOR AND DAC MODULATOR POWER CONTROL REGISTER
Address: 0x0045, Reset: 0x00, Name: INTERP_PWR_MODES
Table 96. Bit Descriptions for INTERP_PWR_MODES
Bits
Bit Name
Settings
Description
Reset
Access
3
MOD_1_EN
DAC Modulator 1 enable.
Powered down
Powered up
0x0
RW
0
1
2
1
0
MOD_0_EN
INT_1_EN
INT_0_EN
DAC Modulator 0 enable.
Powered down
Powered up
0x0
0x0
0x0
RW
RW
RW
0
1
ASRC Interpolator 1 enable.
Powered down
Powered up
0
1
ASRC Interpolator 0 enable.
Powered down
Powered up
0
1
ANALOG BIAS CONTROL 0 REGISTER
Address: 0x0046, Reset: 0x00, Name: BIAS_CONTROL0
Rev. C | Page 106 of 116
Data Sheet
ADAU1772
Table 97. Bit Descriptions for BIAS_CONTROL0
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
HP_IBIAS
Headphone output bias current setting. Higher bias currents result in
higher performance.
0x0
RW
00 Normal operation (default)
01 Extreme power saving
10 Enhanced performance
11 Power saving
[5:4]
[3:2]
[1:0]
AFE_IBIAS01
ADC_IBIAS23
ADC_IBIAS01
Analog Front-End 0 and Analog Front-End 1 bias current setting. Higher
bias currents result in higher performance.
00 Normal operation (default)
01 Extreme power saving
10 Enhanced performance
11 Power saving
0x0
0x0
0x0
RW
RW
RW
ADC2 and ADC3 bias current setting. Higher bias currents result in higher
performance.
00 Normal operation (default)
01 Reserved
10 Enhanced performance
11 Power saving
ADC0 and ADC1 bias current setting. Higher bias currents result in higher
performance.
00 Normal operation (default)
01 Reserved
10 Enhanced performance
11 Power saving
ANALOG BIAS CONTROL 1 REGISTER
Address: 0x0047, Reset: 0x00, Name: BIAS_CONTROL1
Table 98. Bit Descriptions for BIAS_CONTROL1
Bits
Bit Name
Settings
Description
Reset
Access
6
CBIAS_DIS
Central analog bias circuitry. Higher bias currents result in higher
performance.
0x0
RW
0
1
Powered up
Powered down
Rev. C | Page 107 of 116
ADAU1772
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
[5:4]
AFE_IBIAS23
MIC_IBIAS
DAC_IBIAS
Analog Front-End 2 and Analog Front-End 3 bias current setting. Higher
bias currents result in higher performance.
00 Normal operation (default)
01 Extreme power saving
10 Enhanced performance
11 Power saving
0x0
RW
[3:2]
[1:0]
Microphone input bias current setting. Higher bias currents result in
higher performance.
00 Normal operation (default)
01 Extreme power saving
10 Enhanced performance
11 Power saving
0x0
0x0
RW
RW
DAC bias current setting. Higher bias currents result in higher performance.
00 Normal operation (default)
01 Power saving
10 Superior performance
11 Enhanced performance
DIGITAL PIN PULL-UP CONTROL 0 REGISTER
Address: 0x0048, Reset: 0x7F, Name: PAD_CONTROL0
Controls the behavior of the pad. Possible to enable pull-up.
Table 99. Bit Descriptions for PAD_CONTROL0
Bits
Bit Name
Settings
Description
Reset
Access
6
DMIC2_3_PU
Pull-up disable.
Pull-up enabled
Pull-up disabled
Pull-up disable.
Pull-up enabled
Pull-up disabled
Pull-up disable.
Pull-up enabled
Pull-up disabled
0x1
RW
0
1
5
4
DMIC0_1_PU
LRCLK_PU
0x1
0x1
RW
RW
0
1
0
1
Rev. C | Page 108 of 116
Data Sheet
ADAU1772
Bits
Bit Name
Settings
Description
Reset
Access
3
BCLK_PU
Pull-up disable.
Pull-up enabled
Pull-up disabled
Pull-up disable.
Pull-up enabled
Pull-up disabled
Pull-up disable.
Pull-up enabled
Pull-up disabled
Pull-up disable.
Pull-up enabled
Pull-up disabled
0x1
RW
0
1
2
1
0
ADC_SDATA1_PU
ADC_SDATA0_PU
DAC_SDATA_PU
0x1
0x1
0x1
RW
RW
RW
0
1
0
1
0
1
DIGITAL PIN PULL-UP CONTROL 1 REGISTER
Address: 0x0049, Reset: 0x1F, Name: PAD_CONTROL1
Controls the behavior of the pad. Possible to enable pull-up.
Table 100. Bit Descriptions for PAD_CONTROL1
Bits
Bit Name
Settings
Description
Reset
Access
4
SELFBOOT_PU
Pull-up disable.
Pull-up enabled
Pull-up disabled
Pull-up disable.
Pull-up enabled
Pull-up disabled
Pull-up disable.
Pull-up enabled
Pull-up disabled
Pull-up disable.
Pull-up enabled
Pull-up disabled
Pull-up disable.
Pull-up enabled
Pull-up disabled
0x1
RW
0
1
3
2
1
0
SCL_PU
0x1
0x1
0x1
0x1
RW
RW
RW
RW
0
1
SDA_PU
0
1
ADDR1_PU
ADDR0_PU
0
1
0
1
Rev. C | Page 109 of 116
ADAU1772
Data Sheet
DIGITAL PIN PULL-DOWN CONTROL 0 REGISTER
Address: 0x004A, Reset: 0x00, Name: PAD_CONTROL2
Controls the behavior of the pad. Possible to enable pull-down.
Table 101. Bit Descriptions for PAD_CONTROL2
Bits
Bit Name
Settings
Description
Reset
Access
6
DMIC2_3_PD
Pull-down enable.
Pull-down disabled
Pull-down enabled
Pull-down enable.
Pull-down disabled
Pull-down enabled
Pull-down enable.
Pull-down disabled
Pull-down enabled
Pull-down enable.
Pull-down disabled
Pull-down enabled
Pull-down enable.
Pull-down disabled
Pull-down enabled
Pull-down enable.
Pull-down disabled
Pull-down enabled
Pull-down enable.
Pull-down disabled
Pull-down enabled
0x0
RW
0
1
5
4
3
2
1
0
DMIC0_1_PD
LRCLK_PD
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
0
1
0
1
BCLK_PD
0
1
ADC_SDATA1_PD
ADC_SDATA0_PD
DAC_SDATA_PD
0
1
0
1
0
1
Rev. C | Page 110 of 116
Data Sheet
ADAU1772
DIGITAL PIN PULL-DOWN CONTROL 1 REGISTER
Address: 0x004B, Reset: 0x00, Name: PAD_CONTROL3
Controls the behavior of the pad. Possible to enable pull-down.
Table 102. Bit Descriptions for PAD_CONTROL3
Bits
Bit Name
Settings
Description
Reset
Access
4
SELFBOOT_PD
Pull-down enable.
Pull-down disabled
Pull-down enabled
Pull-down enable.
Pull-down disabled
Pull-down enabled
Pull-down enable.
Pull-down disabled
Pull-down enabled
Pull-down enable.
Pull-down disabled
Pull-down enabled
Pull-down enable.
Pull-down disabled
Pull-down enabled
0x0
RW
0
1
3
2
1
0
SCL_PD
0x0
0x0
0x0
0x0
RW
RW
RW
RW
0
1
SDA_PD
0
1
ADDR1_PD
ADDR0_PD
0
1
0
1
Rev. C | Page 111 of 116
ADAU1772
Data Sheet
DIGITAL PIN DRIVE STRENGTH CONTROL 0 REGISTER
Address: 0x004C, Reset: 0x00, Name: PAD_CONTROL4
Table 103. Bit Descriptions for PAD_CONTROL4
Bits
Bit Name
Settings
Description
Reset
Access
4
LRCLK_DRV
Drive strength control.
Low drive strength
High drive strength
Drive strength control.
Low drive strength
High drive strength
Drive strength control.
Low drive strength
High drive strength
Drive strength control.
Low drive strength
High drive strength
0x0
RW
0
1
3
2
1
BCLK_DRV
0x0
0x0
0x0
RW
RW
RW
0
1
ADC_SDATA1_DRV
ADC_SDATA0_DRV
0
1
0
1
Rev. C | Page 112 of 116
Data Sheet
ADAU1772
DIGITAL PIN DRIVE STRENGTH CONTROL 1 REGISTER
Address: 0x004D, Reset: 0x00, Name: PAD_CONTROL5
Table 104. Bit Descriptions for PAD_CONTROL5
Bits
Bit Name
Settings
Description
Reset
Access
3
SCL_DRV
Drive strength control.
Low drive strength
High drive strength
Drive strength control.
Low drive strength
High drive strength
0x0
RW
0
1
2
SDA_DRV
0x0
RW
0
1
Rev. C | Page 113 of 116
ADAU1772
Data Sheet
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
31
30
40
1
0.50
BSC
4.45
4.30 SQ
4.25
EXPOSED
PAD
21
20
10
11
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 105. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-10)
Dimension shown in millimeters
ORDERING GUIDE
Model1
ADAU1772BCPZ
ADAU1772BCPZ-R7
ADAU1772BCPZ-RL
EVAL-ADAU1772Z
Temperature Range Package Description
Package Option
CP-40-10
CP-40-10
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7”Tape and Reel
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 13”Tape and Reel CP-40-10
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. C | Page 114 of 116
Data Sheet
NOTES
ADAU1772
Rev. C | Page 115 of 116
ADAU1772
NOTES
Data Sheet
©2012–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10804-0-3/14(C)
Rev. C | Page 116 of 116
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