ADAU1777BCBZRL [ADI]
Four-ADC, Two-DAC, Low Power Codec with Audio Processor;
| 型号： | ADAU1777BCBZRL |
| 厂家： | 
ADI |
| 描述： | Four-ADC, Two-DAC, Low Power Codec with Audio Processor 商用集成电路 |
| 文件： | 总109页 (文件大小：1834K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Four-ADC, Two-DAC, Low Power Codec
with Audio Processor
Data Sheet
ADAU1777
FEATURES
APPLICATIONS
Programmable audio processing engine
Fast (up to 768 kHz) and slow processing paths
Biquad filters, limiters, volume controls, and mixing
Low latency, 24-bit ADCs and DACs
Noise canceling handsets, headsets, and headphones
Bluetooth® active noise canceling (ANC) handsets, headsets,
and headphones
Personal navigation devices
102 dB SNR (through PGA and ADC with A weighted filter)
108 dB combined SNR (through DAC and headphone with
A weighted filter)
Serial port sampling rate from 8 kHz to 192 kHz
5 μs analog-to-analog latency
4 single-ended analog inputs, configurable as microphone
or line inputs
Dual stereo digital microphone inputs
Digital still and video cameras
GENERAL DESCRIPTION
The ADAU1777 is a codec with four inputs and two outputs that
incorporates a digital processing engine to perform filtering,
level control, signal level monitoring, and mixing. The path
from the analog input to the DSP core to the analog output is
optimized for low latency and is ideal for noise canceling headsets.
With the addition of just a few passive components, a crystal,
and an EEPROM for booting, the ADAU1777 provides a complete
headset solution.
Stereo analog audio output, single-ended or differential,
configurable as either line output or headphone driver
PLL supporting any input clock rate from 8 MHz to 27 MHz
Full duplex, asynchronous sample rate converters (ASRCs)
Power supplies
Analog and digital input/output of 1.8 V to 3.3 V
Digital signal processing (DSP) core of 1.1 V to 1.8 V
Low power
Note that throughout this data sheet, multifunction pins, such as
SCL/SCLK, are referred to either by the entire pin name or by a
single function of the pin, for example, SCLK, when only that
function is relevant.
I2C and SPI control interfaces, self boot from I2C EEPROM
7 multipurpose (MPx) pins for digital controls and outputs
FUNCTIONAL BLOCK DIAGRAM
MICBIAS0
MICBIAS1
MICROPHONE
BIAS GENERATORS
POWER
MANAGEMENT
LDO
REGULATOR
ADAU1777
ADC_SDATA1/CLKOUT/MP6
XTALI/MCLKIN
PGA
AIN0
CLOCK
OSCILLATOR
PLL
ADC
XTALO
HPOUTLP/LOUTLP
HPOUTLN/LOUTLN
PGA
AIN1
DAC
DAC
ADC
INPUT/OUTPUT
SIGNAL
STEREO PDM
MODULATOR
ROUTING
DMIC0_1/MP4
DMIC2_3/MP5
DIGITAL
MICROPHONE
INPUTS
HPOUTRP/LOUTRP
HPOUTRN/LOUTRN
PGA
AIN2
DAC_SDATA/MP0
ADC_SDATA0/PDMOUT/MP1
BCLK/MP2
SERIAL
INPUT/
OUTPUT
PORT
ADC
BIDIRECTIONAL
ASRCS
LRCLK/MP3
DSP CORE:
BIQUAD FILTERS,
LIMITERS,
VOLUME CONTROLS,
MIXING
PGA
AIN3
CM
2
I C/SPI CONTROL
INTERFACE AND SELF BOOT
ADC
Figure 1.
Rev. 0
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Tel: 781.329.4700
Technical Support
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www.analog.com
ADAU1777* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DOCUMENTATION
Data Sheet
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Audio Processor Data Sheet
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Low Power Codec with Audio Processor
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ADAU1777
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Burst Mode Communication.................................................... 35
I2C Port ........................................................................................ 35
SPI Port ........................................................................................ 38
Self Boot....................................................................................... 39
Multipurpose Pins.......................................................................... 40
Push-Button Volume Controls ................................................. 40
Limiter Compression Enable .................................................... 40
Parameter Bank Switching ........................................................ 40
Mute ............................................................................................. 40
DSP Bypass Mode ...................................................................... 41
Serial Data Input/Output Ports .................................................... 42
Tristating Unused Channels ..................................................... 42
Applications Information .............................................................. 45
Power Supply Bypass Capacitors.............................................. 45
Layout .......................................................................................... 45
Grounding ................................................................................... 45
PCB Stackup................................................................................ 45
Low Latency Register Settings ...................................................... 46
Register Summary .......................................................................... 49
Register Details ............................................................................... 52
Clock Control Register.............................................................. 52
PLL Denominator MSB Register.............................................. 53
PLL Denominator LSB Register ............................................... 53
PLL Numerator MSB Register.................................................. 53
PLL Numerator LSB Register.................................................... 54
PLL Integer Setting Register ..................................................... 54
PLL Lock Flag Register.............................................................. 55
CLKOUT Setting Selection Register........................................ 55
Regulator Control Register ....................................................... 56
Core Control Register................................................................ 56
Sleep on Program Address Count Register............................. 57
Filter Engine and Limiter Control Register............................ 59
DB Value Register 0 Read.......................................................... 59
DB Value Register 1 Read.......................................................... 60
DB Value Register 2 Read.......................................................... 60
Core Channel 0/Core Channel 1 Input Select Register......... 61
Core Channel 2/Core Channel 3 Input Select Register......... 62
DAC Input Select Register ........................................................ 63
PDM Modulator Input Select Register.................................... 64
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Analog Performance Specifications ........................................... 4
Crystal Amplifier Specifications................................................. 8
Digital Input/Output Specifications........................................... 8
Power Supply Specifications........................................................ 8
Typical Power Management Settings ......................................... 9
Digital Filters Specifications ....................................................... 9
Digital Timing Specifications ................................................... 10
Absolute Maximum Ratings.......................................................... 14
Thermal Resistance .................................................................... 14
ESD Caution................................................................................ 14
Pin Configuration and Function Descriptions........................... 15
Typical Performance Characteristics ........................................... 17
Theory of Operation ...................................................................... 24
System Clocking and Power-Up ................................................... 25
Clock Initialization..................................................................... 25
PLL................................................................................................ 25
Clock Output............................................................................... 26
Power Sequencing ...................................................................... 26
Signal Routing................................................................................. 27
Input Signal Paths........................................................................... 28
Analog Inputs.............................................................................. 28
Digital Microphone Input ......................................................... 29
Analog-to-Digital Converters (ADCs).................................... 29
Output Signal Paths........................................................................ 30
Analog Outputs........................................................................... 30
Digital-to-Analog Converters (DACs) .................................... 30
PDM Output ............................................................................... 30
Asynchronous Sample Rate Converters.................................. 31
Signal Levels................................................................................ 31
Signal Processing ............................................................................ 32
Instructions ................................................................................. 32
Data Memory .............................................................................. 32
Parameters................................................................................... 32
Control Port..................................................................................... 35
Rev. 0 | Page 2 of 108
Data Sheet
ADAU1777
Serial Data Output 0/Serial Data Output 1 Input Select
Register.........................................................................................65
Serial Port Control 0 Register....................................................85
Serial Port Control 1 Register....................................................86
TDM Output Channel Disable Register ..................................87
PDM Enable Register .................................................................88
PDM Pattern Setting Register ...................................................89
MP0 Function Setting Register .................................................89
MP1 Function Setting Register .................................................90
MP2 Function Setting Register .................................................91
MP3 Function Setting Register .................................................91
MP4 Function Setting Register .................................................92
MP5 Function Setting Register .................................................93
MP6 Function Setting Register .................................................94
Push-Button Volume Settings Register....................................94
Push-Button Volume Control Assignment Register ..............95
Debounce Modes Register.........................................................96
Headphone Line Output Select Register..................................97
Decimator Power Control Register ..........................................97
Serial Data Output 2/Serial Data Output 3 Input Select
Register.........................................................................................66
Serial Data Output 4/Serial Data Output 5 Input Select
Register.........................................................................................67
Serial Data Output 6/Serial Data Output 7 Input Select
Register.........................................................................................68
ADC_SDATA0/ADC_SDATA1 Channel Select Register......69
Output ASRC0/Output ASRC1 Source Register.....................69
Output ASRC2/Output ASRC3 Source Register.....................70
Input ASRC Channel Select Register........................................71
ADC0/ADC1 Control 0 Register..............................................72
ADC2/ADC3 Control 0 Register..............................................73
ADC0/ADC1 Control 1 Register..............................................74
ADC2/ADC3 Control 1 Register..............................................75
ADC0 Volume Control Register ...............................................75
ADC1 Volume Control Register ...............................................76
ADC2 Volume Control Register ...............................................76
ADC3 Volume Control Register ...............................................77
PGA Control 0 Register..............................................................77
PGA Control 1 Register..............................................................78
PGA Control 2 Register..............................................................78
PGA Control 3 Register..............................................................79
PGA Slew Control Register........................................................80
PGA 10 dB Gain Boost Register................................................80
Input and Output Capacitor Charging Register .....................81
DSP Bypass Path Register ..........................................................82
DSP Bypass Gain for PGA0 Register........................................82
DSP Bypass Gain for PGA1 Register........................................82
MICBIAS0_1 Control Register..................................................83
DAC Control Register ................................................................83
DAC0 Volume Control Register................................................84
DAC1 Volume Control Register................................................84
Headphone Output Mutes Register..........................................85
ASRC Interpolator and DAC Modulator Power Control
Register.........................................................................................99
Analog Bias Control 0 Register.................................................99
Analog Bias Control 1 Register...............................................100
Digital Pin Pull-Up Control 0 Register..................................101
Digital Pin Pull-Up Control 1 Register..................................102
Digital Pin Pull-Down Control 0 Register ............................103
Digital Pin Pull-Down Control 1 Register ............................103
Digital Pin Drive Strength Control 0 Register ......................104
Digital Pin Drive Strength Control 1 Register ......................105
Fast Rate Control Register .......................................................105
DAC Interpolation Control Register......................................106
Volume Control Bypass Register ............................................107
Outline Dimensions......................................................................108
Ordering Guide .........................................................................108
REVISION HISTORY
12/2016—Revision 0: Initial Version
Rev. 0 | Page 3 of 108
ADAU1777
Data Sheet
SPECIFICATIONS
Master clock = 12.288 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits,
TA = 25°C, outputs line loaded with 10 kΩ.
ANALOG PERFORMANCE SPECIFICATIONS
AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted. Phase-locked loop (PLL) disabled, direct master clock.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ANALOG-TO-DIGITAL CONVERTERS (ADCs)
ADC Resolution
Digital Attenuation Step
Digital Attenuation Range
INPUT RESISTANCE
All ADCs
24
0.375
95
Bits
dB
dB
Gain settings do not include 10 dB gain from
PGA_x_BOOST settings; this additional gain does
not affect input impedance; PGA_POP_DISx = 1
Single-Ended Line Input
Programmable Gain Amplifier (PGA) Inputs −12 dB gain
0 dB gain
14.3
32.0
20
kΩ
kΩ
kΩ
kΩ
0 dB gain
+35.25 dB gain
0.68
LINE INPUT
PGA_ENx = 0, PGA_x_BOOST = 0, PGA_POP_DISx = 1
Full-Scale Input Voltage
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 3.3 V
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD/3.3
0.55
1.54
1.00
2.83
V rms
V rms
V p-p
V rms
V p-p
Dynamic Range1
With A-Weighted Filter (RMS)
95
99
92
96
97
102
94
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
99
Signal-to-Noise Ratio (SNR)2
With A-Weighted Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
96
100
92
96
0
98
103
96
100
40
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
Interchannel Gain Mismatch
200
mdB
Total Harmonic Distortion + Noise (THD + N)
20 Hz to 20 kHz, −1 dB from full-scale input
AVDD = 1.8 V
−90
−94
−83
−87
+0.12
+0.2
dB
dB
mV
dB
dB
dB
AVDD = 3.3 V
Offset Error
Gain Error
Interchannel Isolation
Power Supply Rejection Ratio (PSRR)
PGA INPUT
−0.11
−0.4
CM capacitor = 22 μF
CM capacitor = 22 μF, 100 mV p-p at 1 kHz
PGA_ENx = 1, PGA_x_BOOST = 0
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 3.3 V
95
55
Full-Scale Input Voltage
AVDD/3.3
0.55
1.54
1.00
2.83
V rms
V rms
V p-p
V rms
V p-p
Dynamic Range1
With A-Weighted Filter (RMS)
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
94
102
92
dB
dB
dB
dB
AVDD = 3.3 V
With Flat 20 Hz to 20 kHz Filter
AVDD = 1.8 V
AVDD = 3.3 V
98
Rev. 0 | Page 4 of 108
Data Sheet
ADAU1777
Parameter
Test Conditions/Comments
20 Hz to 20 kHz, −1 dB from full-scale input
AVDD = 1.8 V
Min
Typ
Max
Unit
THD + N
−88
−90
dB
dB
AVDD = 3.3 V
SNR2
With A-Weighted Filter (RMS)
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Standard deviation
94
102
93
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
98
PGA Gain Variation
With −12 dB Setting
With +35.25 dB Setting
PGA Boost
PGA Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
PSRR
0.05
0.15
10
−63
0.04
dB
dB
dB
dB
dB
mV
dB
dB
dB
PGA_x_BOOST
PGA_MUTEx
−0.12
+0.12
−0.05
100
63
CM capacitor = 20 μF, 100 mV p-p at 1 kHz
MIC_ENx = 1
MICROPHONE BIAS
Bias Voltage
0.65 × AVDD
AVDD = 1.8 V, MIC_GAINx = 1
AVDD = 3.3 V, MIC_GAINx = 1
AVDD = 1.8 V, MIC_GAINx = 0
AVDD = 3.3 V, MIC_GAINx = 0
1.14
2.10
1.61
2.95
1.16
2.12
1.63
2.97
1.17
2.14
1.65
2.99
3
V
V
V
V
mA
Ω
dB
dB
0.90 × AVDD
Bias Current Source
Output Impedance
MICBIASx Isolation
1
95
99
MIC_GAINx = 0
MIC_GAINx = 1
Noise in the Signal Bandwidth
AVDD = 1.8 V
20 Hz to 20 kHz, 4.7 µF decoupling capacitor,
5.0 kΩ load on the MICBIASx pins
MIC_GAINx = 0
MIC_GAINx = 1
MIC_GAINx = 0
MIC_GAINx = 1
27
16
35
19
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
AVDD = 3.3 V
DIGITAL-TO-ANALOG CONVERTERS (DACs)
Resolution
Digital Attenuation Step
Digital Attenuation Range
DAC SINGLE-ENDED OUTPUT
All DACs
24
0.375
95
Bits
dB
dB
Single-ended operation, HPOUTLP/LOUTLP and
HPOUTRP/LOUTRP pins
Full-Scale Output Voltage
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 3.3 V
AVDD/3.4
0.53
1.5
0.97
2.74
V rms
V rms
V p-p
V rms
V p-p
dB
Mute Attenuation
−72
Line Output Mode
Dynamic Range1
With A-Weighted Filter (RMS)
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
97
102
95
100
104
97
dB
dB
dB
dB
AVDD = 3.3 V
With Flat 20 Hz to 20 kHz Filter
AVDD = 1.8 V
AVDD = 3.3 V
99
101
Rev. 0 | Page 5 of 108
ADAU1777
Data Sheet
Parameter
Test Conditions/Comments
20 Hz to 20 kHz
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
Min
Typ
Max
Unit
SNR2
With A-Weighted Filter (RMS)
98
102
96
99
0
100
104
98
102
50
dB
dB
dB
dB
mdB
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
AVDD = 3.3 V
Interchannel Gain Mismatch
THD + N
200
20 Hz to 20 kHz, −1 dBFS input
AVDD = 1.8 V
AVDD = 3.3 V
−93
−94
−89
−90
+0.13
Gain Error
−0.13
Headphone Mode
Dynamic Range1
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
With A-Weighted Filter (RMS)
97
102
95
100
104
97
dB
dB
dB
dB
AVDD = 3.3 V
With Flat 20 Hz to 20 kHz Filter
AVDD = 1.8 V
AVDD = 3.3 V
20 Hz to 20 kHz
AVDD = 1.8 V
99
101
SNR2
With A-Weighted Filter (RMS)
98
102
96
100
0
100
104
98
102
50
dB
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
With Flat 20 Hz to 20 kHz Filter
Interchannel Gain Mismatch
THD + N
230
mdB
20 Hz to 20 kHz, −1 dBFS input
32 Ω Load
AVDD = 1.8 V, output power = 6.3 mW
AVDD = 3.3 V, output power = 20.5 mW
AVDD = 1.8 V, output power = 8.4 mW
AVDD = 3.3 V, output power = 27 mW
AVDD = 1.8 V, output power = 13 mW
AVDD = 3.3 V, output power = 30 mW
−79
−84
−79
−80
−74
−77
−67
−67
−65
−64
−61
−67
+0.13
dB
dB
dB
dB
dB
dB
dB
24 Ω Load
16 Ω Load
Gain Error
−0.13
Headphone Output Power
32 Ω Load
AVDD = 1.8 V, <0.1% THD + N
AVDD = 3.3 V, <0.1% THD + N
AVDD = 1.8 V, <0.1% THD + N
AVDD = 3.3 V, <0.1% THD + N
AVDD = 1.8 V, <0.1% THD + N
AVDD = 3.3 V, <0.1% THD + N
8.0
mW
mW
mW
mW
mW
mW
mV
dB
28.1
11.1
30.5
16.5
32.7
24 Ω Load
16 Ω Load
Offset Error
Interchannel Isolation
PSRR
−0.11
+0.09
1 kHz, 0 dBFS input signal
CM capacitor = 22 µF, 100 mV p-p at 1 kHz
Differential operation
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 3.3 V
100
70
dB
DAC DIFFERENTIAL OUTPUT
Full-Scale Output Voltage
AVDD/1.7
1.06
3.00
1.94
5.49
V rms
V rms
V p-p
V rms
V p-p
dB
Mute Attenuation
−72
Line Output Mode
Dynamic Range1
With A-Weighted Filter (RMS)
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
102
105
100
102
105
107
102
105
dB
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
With Flat 20 Hz to 20 kHz Filter
Rev. 0 | Page 6 of 108
Data Sheet
ADAU1777
Parameter
Test Conditions/Comments
20 Hz to 20 kHz
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
Min
Typ
Max
Unit
SNR2
With A-Weighted Filter (RMS)
103
106
100
103
0
105
108
102
105
50
dB
dB
dB
dB
mdB
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
AVDD = 3.3 V
Interchannel Gain Mismatch
THD + N
200
20 Hz to 20 kHz, −1 dBFS input
AVDD = 1.8 V
AVDD = 3.3 V
−96
−96
−90
−90
+0.16
Gain Error
−0.1
Headphone Mode
Dynamic Range1
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
With A-Weighted Filter (RMS)
102
105
100
102
105
107
102
104
dB
dB
dB
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
20 Hz to 20 kHz
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
With Flat 20 Hz to 20 kHz Filter
SNR2
With A-Weighted Filter (RMS)
103
106
101
104
0
106
108
103
106
75
dB
dB
dB
dB
With Flat 20 Hz to 20 kHz Filter
Interchannel Gain Mismatch
THD + N
370
mdB
32 Ω Load
−1 dBFS, AVDD = 1.8 V, output power = 26 mW
−1 dBFS, AVDD = 3.3 V, output power = 87 mW
−2 dBFS, AVDD = 1.8 V, output power = 27 mW
−1 dBFS, AVDD = 3.3 V, output power = 115 mW
−3 dBFS, AVDD = 1.8 V, output power = 32 mW
−1 dBFS, AVDD = 3.3 V, output power = 168 mW
Headphone mode
−75
−83
−75
−82
−75
−77
−64
−75
−64
−75
−65
−68
+0.25
dB
dB
dB
dB
dB
dB
dB
24 Ω Load
16 Ω Load
Gain Error
−0.25
Headphone Output Power
32 Ω Load
AVDD = 1.8 V, <0.1% THD + N
AVDD = 3.3 V, <0.1% THD + N
AVDD = 1.8 V, <0.1% THD + N
AVDD = 3.3 V, <0.1% THD + N
AVDD = 1.8 V, <0.1% THD + N
AVDD = 3.3 V, <0.1% THD + N
29.1
111.8
31.8
148.3
32.3
193.0
0
mW
mW
mW
mW
mW
mW
mV
dB
24 Ω Load
16 Ω Load
Offset Error
Interchannel Isolation
PSRR
−0.12
+0.08
1 kHz, 0 dBFS input signal
CM capacitor = 22 μF, 100 mV p-p at 1 kHz
100
73
dB
ANALOG-TO-ANALOG LATENCY
fS = 768 kHz
fS = 192 kHz
CM pin
5
38
µs
µs
CM REFERENCE
Common-Mode Reference Output
Common-Mode Source Impedance
REGULATOR
AVDD/2
5
V
kΩ
Line Regulation
Load Regulation
1
6
mV/V
mV/mA
1 Dynamic range is the ratio of the sum of the noise and harmonic power in the band of interest with a −60 dBFS signal present vs. the full-scale power level in decibels.
2 SNR is the ratio of the sum of all noise power in the band of interest with no signal present vs. the full-scale power level in decibels.
Rev. 0 | Page 7 of 108
ADAU1777
Data Sheet
CRYSTAL AMPLIFIER SPECIFICATIONS
AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
CRYSTAL AMPLIFIER
Jitter
Frequency Range
Load Capacitance
270
500
27
20
ps rms
MHz
pF
8
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 3.3 V 10% and 1.8 V − 5% to 1.8 V + 10%, unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT/OUTPUT
Input Voltage
High (VIH)
IOVDD = 3.3 V
IOVDD = 1.8 V
2.0
1.1
V
V
Low (VIL)
IOVDD = 3.3 V
IOVDD = 1.8 V
IOVDD = 3.3 V, IIH1 at VIH = 2.0 V
IIL1 at VIL = 0.8 V
IOVDD = 1.8 V, IIH1 at VIH = 1.1 V
IIL1 at VIL = 0.45 V
0.8
0.45
10
10
10
V
V
µA
µA
µA
µA
Input Leakage
10
Output Voltage High (VOH)
Low Drive Strength
High Drive Strength
Output Voltage Low (VOL)
Low Drive Strength
High Drive Strength
Input Capacitance
IOH1 = 1 mA
IOH1 = 3 mA
IOVDD − 0.6
IOVDD − 0.6
V
V
IOL1 = 1 mA
IOL1 = 3 mA
0.4
0.4
5
V
V
pF
1 IIH is the current when the input is high; IIL is the current when the input is low; IOH is the current when the output is high; and IOL is the current when the output is low.
POWER SUPPLY SPECIFICATIONS
AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted.
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SUPPLIES
AVDD Voltage
DVDD Voltage
IOVDD Voltage
Analog Current (IAVDD
Normal Operation
Power-Down
Digital Input/Output Current (IIOVDD
Normal Operation
Power-Down
1.71
1.045 1.1
1.71
1.8
3.63
1.98
3.63
V
V
V
1.8
1.6
1.3
1
)
See Table 5
See Table 5
See Table 5
µA
µA
µW
)
POWER CONSUMPTION
All Supplies
Power-Down, All Supplies
Rev. 0 | Page 8 of 108
Data Sheet
ADAU1777
TYPICAL POWER MANAGEMENT SETTINGS
Typical ANC settings, master clock = 12.288 MHz, PLL disabled, crystal oscillator enabled, core fS = DAC = ADC = 768 kHz. On-board
regulator enabled. Two ADCs with PGA enabled and two ADCs configured for line input, no input signal. Two DACs are configured for
differential headphone (HP) operation; DAC outputs are unloaded. Both MICBIAS0 and MICBIAS1 enabled at 0.9 × AVDD. ASRCs and
pulse density modulation (PDM) modulator disabled. Core running 26 out of 32 possible instructions. Serial port set to slave. See
Register 0x46 and Register 0x47 for settings.
Table 5.
Typical AVDD
Current
Consumption (mA)
Typical IOVDD
Current
Consumption (mA)
Typical HP
Output
THD + N (dB)
Total Power
Consumption
(mW)
Power Management
Setting
Typical ADC
THD + N (dB)
Operating Voltage
AVDD = IOVDD = 3.3 V Normal
Extreme power saving
Power saving
9.71
7.55
7.99
2.58
2.57
2.57
2.58
0.37
0.37
0.37
0.37
−91
−86
−87
−91
−87
−81
−81
−87
−97
−96
−96
−98
−95
−89
−90
−95
40.56
33.40
34.85
44.72
13.79
10.35
10.98
16.18
Enhanced performance 10.97
AVDD = IOVDD = 1.8 V Normal
7.29
5.38
5.73
Extreme power saving
Power saving
Enhanced Performance 8.62
DIGITAL FILTERS SPECIFICATIONS
Table 6.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ADC INPUT TO DAC OUTPUT PATH
Pass-Band Ripple
DC to 20 kHz, fS = 768 kHz
DC to 20 kHz, fS = 192 kHz
−0.03
+0.01
0.02
dB
dB
SAMPLE RATE CONVERTER
Pass Band
LRCLK < 63 kHz
63 kHz < LRCLK <130 kHz
LRCLK > 130 kHz
Upsampling, 96 kHz
Upsampling, 192 kHz
Downsampling, 96 kHz
Downsampling, 192 kHz
0
0
0
0.475 × fS
0.4286 × fS
0.4286 × fS
+0.05
+0.05
0.07
kHz
kHz
kHz
dB
dB
dB
dB
kHz
dB
Pass-Band Ripple
−0.27
−0.06
0
0
8
0.07
192
Input/Output Frequency Range
Dynamic Range
THD + N
100
−90
dB
Start-Up Time
15
ms
PDM MODULATOR
Dynamic Range (A-Weighted)
THD + N
112
−92
dB
dB
Rev. 0 | Page 9 of 108
ADAU1777
Data Sheet
DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 1.71 V to 3.63 V, DVDD = 1.045 V to 1.98 V.
Table 7. Digital Timing
Limit
Parameter
tMIN
tMAX
Unit
Description
MASTER CLOCK (MCLK)
tMP
tMCLK
37
77
125
82
ns
ns
MCLKIN period; 8 MHz to 27 MHz input clock using PLL
Internal MCLK period; direct MCLK and PLL output divided by 2
SERIAL PORT
tBL
tBH
tLS
tLH
tSS
tSH
tTS
40
40
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
BCLK low pulse width (master and slave modes)
BCLK high pulse width (master and slave modes)
LRCLK setup; time to BCLK rising (slave mode)
LRCLK hold; time from BCLK rising (slave mode)
DAC_SDATA setup; time to BCLK rising (master and slave modes)
DAC_SDATA hold; time from BCLK rising (master and slave modes)
BCLK falling to LRCLK timing skew (master mode)
ADC_SDATAx delay; time from BCLK falling (master and slave modes)
BCLK falling to ADC_SDATAx driven in time-division multiplexing
(TDM) tristate mode
5
10
34
30
tSOD
tSOTD
0
tSOTX
30
ns
BCLK falling to ADC_SDATAx tristate in TDM tristate mode
SERIRAL PERIPHERAL INTERFACE
(SPI) PORT
fSCLK
tCCPL
tCCPH
tCLS
6.25
MHz
ns
ns
SCLK frequency
SCLK pulse width low
SCLK pulse width high
SS setup; time to SCLK rising
SS hold; time from SCLK rising
SS pulse width high
80
80
5
ns
tCLH
100
80
10
10
ns
tCLPH
tCDS
tCDH
tCOD
I2C PORT
fSCL
tSCLH
tSCLL
ns
ns
ns
ns
MOSI setup; time to SCLK rising
MOSI hold; time from SCLK rising
MISO delay; time from SCLK falling
101
400
kHz
µs
µs
SCL frequency
SCL high
SCL low
0.6
1.3
0.6
tSCS
µs
SCL rise setup time (to SDA falling), relevant for repeated start
condition
tSCR
tSCH
tDS
tSCF
250
250
ns
µs
ns
ns
µs
SCL and SDA rise time, CLOAD = 400 pF
SCL fall hold time (from SDA falling), relevant for start condition
SDA setup time (to SCL rising)
SCL and SDA fall time; CLOAD = 400 pF
SCL rise setup time (to SDA rising), relevant for stop condition
0.6
100
tBFT
0.6
I2C EEPROM SELF BOOT
tSCHE
26 × tMP − 70
38 × tMP − 70
ns
ns
SCL fall hold time (from SDA falling), relevant for start condition; tMP
is the input clock on the MCLKIN pin
SCL rise setup time (to SDA falling), relevant for repeated start
condition
tSCSE
tBFTE
tDSE
tBHTE
70 × tMP − 70
6 × tMP − 70
32 × tMP
ns
ns
ns
SCL rise setup time (to SDA rising), relevant for stop condition
Delay from SCL falling to SDA changing
SDA rising in self boot stop condition to SDA falling edge for
external master start condition
Rev. 0 | Page 10 of 108
Data Sheet
ADAU1777
Limit
Parameter
tMIN
tMAX
Unit
Description
MULTIPURPOSE AND POWER-
DOWN PINS
tGIL
1.5 × 1/fS μs
ns
MPx input latency; time until high or low value is read by core
PD low pulse width
tRLPW
20
DIGITAL MICROPHONE
tCF
tCR
tDS
tDE
20
20
ns
ns
Digital microphone clock fall time
Digital microphone clock rise time
Digital microphone valid data start time
Digital microphone valid data end time
40
0
0
ns
PDM OUTPUT
tDCF
tDCR
tDDV
20
20
30
ns
ns
ns
PDM clock fall time
PDM clock rise time
PDM delay time for valid data
Digital Timing Diagrams
tBH
BCLK
tBL
tLS
tLH
LRCLK
tSS
DAC_SDATA
LEFT JUSTIFIED
MODE
MSB
MSB – 1
tSH
tSS
DAC_SDATA
I S MODE
2
MSB
tSH
tSS
tSS
DAC_SDATA
RIGHT JUSTIFIED
MODE
LSB
MSB
tSH
tSH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Input Port Timing
Rev. 0 | Page 11 of 108
ADAU1777
Data Sheet
tLH
tBH
tTS
BCLK
tBL
tLS
LRCLK
tSOD
ADC_SDATAx
LEFT JUSTIFIED
MODE
MSB
MSB – 1
MSB
tSOD
ADC_SDATAx
2
I S MODE
tSOTX
tSOTD
ADC_SDATAx
WITH TRISTATE
HIGH-Z
HIGH-Z
MSB
LSB
tSOD
ADC_SDATAx
RIGHT JUSTIFIED
MODE
LSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 3. Serial Output Port Timing
tCLS
tCLH
tCLPH
tCCPL
tCCPH
SS
SCLK
MOSI
tCDH
tCDS
MISO
tCOD
Figure 4. SPI Port Timing
tDS
tSCH
tSCH
SDA
SCL
tSCR
tSCLH
tSCS
tBFT
tSCLL tSCF
Figure 5. I2C Port Timing
Rev. 0 | Page 12 of 108
Data Sheet
ADAU1777
tSCHE
tDSE
SDA
SCL
tBHTE
tSCSE
tBFTE
Figure 6. I2C EEPROM Self Boot Timing
CLKOUT
tCF
tCR
tDS
tDS
tDE
tDE
DMIC0_1/DMIC2_3
VALID LEFT SAMPLE
VALID RIGHT SAMPLE
VALID LEFT SAMPLE
Figure 7. Digital Microphone Timing
tDCF
tDCR
CLKOUT
tDDV
tDDV
PDMOUT
RIGHT
LEFT
RIGHT
LEFT
Figure 8. PDM Output Timing
Rev. 0 | Page 13 of 108
ADAU1777
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 8.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required. θJA is the natural convection
junction-to-ambient thermal resistance measured in a one cubic
foot sealed enclosure
Parameter
Rating
Power Supplies (AVDD, IOVDD)
Digital Supply (DVDD)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
−0.3 V to +3.63 V
−0.3 V to +1.98 V
20 mA
−0.3 V to AVDD + 0.3 V
−0.3 to IOVDD + 0.3 V
For more information, see the AN-617 Application Note, Wafer
Level Chip Scale Package.
Operating Temperature Range (Case) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Table 9. Thermal Resistance
Package Type
θJA
Unit
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
CB-36-41
36
°C/W
1 Thermal impedance simulated values are based on a 4-layer PCB with two
signal layers and two power planes using natural convection cooling. See
JEDEC JESD51-9.
ESD CAUTION
Rev. 0 | Page 14 of 108
Data Sheet
ADAU1777
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADAU1777
BALL A1
INDICATOR
TOP VIEW
(BALL SIDE DOWN)
1
2
3
4
5
6
7
ADC_SDATA0/ ADC_SDATA1/
PDMOUT/MP1 CLKOUT/MP6
XTALO
XTALI/MCLKIN
IOVDD
A
B
DGND
BCLK/MP2
DAC_SDATA/
DVDD
LRCLK/MP3
REG_OUT
DMIC2_3/MP5 DMIC0_1/MP4
SDA/MISO
ADDR0/SS
SCL/SCLK
MICBIAS0
MP0
HPOUTRP/
LOUTRP
C
D
HPOUTRN/
LOUTRN
AVDD
AGND
ADDR1/MOSI
MICBIAS1
HPOUTLP/
LOUTLP
E
F
PD
AIN3
AIN2
AIN0
AIN1
SELFBOOT
AVDD
AGND
HPOUTLN/
LOUTLN
AVDD
AGND
CM
Figure 9. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic
Type1
Description
A1
DGND
PWR
Digital Ground. Tie the AGND and DGND pins directly together in a common ground
plane.
A2
BCLK/MP2
D_IO
Serial Data Port Bit Clock (BCLK).
Multipurpose Pin (MP2).
A3
A4
A5
ADC_SDATA0/PDMOUT/MP1 D_IO
ADC Serial Data Output 0 (ADC_SDATA0).
Stereo PDM Output to Drive a High Efficiency Class-D Amplifier (PDMOUT).
Multipurpose Pin (MP1).
Serial Data Output 1 (ADC_SDATA1).
Master Clock Output/Clock for the Digital Microphone Input and PDM Output (CLKOUT).
Multipurpose Pin (MP6).
ADC_SDATA1/CLKOUT/MP6
XTALO
D_IO
A_OUT Crystal Clock Output. This pin is the output of the crystal amplifier; do not use this pin to
provide a clock to other ICs in the system. If a master clock output is needed, use CLKOUT
(Pin A4).
A6
A7
XTALI/MCLKIN
IOVDD
D_IN
Crystal Clock Input (XTALI).
Master Clock Input (MCLKIN).
Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD;
thus, the IOVDD voltage level is the highest input voltage that can be present on the
digital input pins. The current draw of this pin is variable because it is dependent on the
loads of the digital outputs. Decouple IOVDD to DGND with a 0.1 μF capacitor.
PWR
B1
DVDD
PWR
Digital Core Supply. The digital supply can be generated from an on-board regulator or
supplied directly from an external supply. In each case, decouple DVDD to DGND with a
0.1 μF capacitor.
B2
B3
B4
LRCLK/MP3
D_IO
D_IO
D_IN
Serial Data Port Frame Clock (LRCLK).
Multipurpose Pin (MP3).
DAC Serial Input Data (DAC_SDATA).
Multipurpose Pin (MP0).
Digital Microphone Stereo Input 2 and Digital Microphone Stereo Input 3 (DMIC2_3).
DAC_SDATA/MP0
DMIC2_3/MP5
Multipurpose Pin (MP5).
Rev. 0 | Page 15 of 108
ADAU1777
Data Sheet
Pin No. Mnemonic
Type1
Description
B5
DMIC0_1/MP4
D_IN
Digital Microphone Stereo Input 0 and Digital Microphone Stereo Input 1 (DMIC0_1).
Multipurpose Pin (MP4).
B6
SDA/MISO
D_IO
D_IN
I2C Data (SDA). This pin is a bidirectional open-collector. The line connected to this pin
must have a 2.0 kΩ pull-up resistor.
SPI Data Output (MISO). This SPI data output reads back registers and memory locations.
It is tristated when an SPI read is not active.
I2C Clock (SCL). This pin is always an open-collector input when the device is in I2C
control mode. When the device is in self boot mode, this pin is an open-collector output (I2C
master). The line connected to this pin must have a 2.0 kΩ pull-up resistor.
B7
C1
SCL/SCLK
SPI Clock (SCLK). This pin either can run continuously or be gated off between SPI transactions.
HPOUTRP/LOUTRP
A_OUT Right Headphone Output Noninverted (HPOUTRP).
Line Output Noninverted, Single-Ended Line Output (LOUTRP).
C2
C6
REG_OUT
ADDR0/SS
A_OUT Regulator Output Voltage. Connect this pin to DVDD if the internal voltage regulator is
being used to generate the DVDD voltage.
D_IN
I2C Address 0 (ADDR0).
SPI Latch Signal (SS). This pin must go low at the beginning of an SPI transaction and
high at the end of a transaction. Each SPI transaction can take a different number of
SCLK cycles to complete, depending on the address and read/write bit that are sent at
the beginning of the SPI transaction.
C7
D1
MICBIAS0
AVDD
A_OUT Bias Voltage for Electret Microphone. Decouple this pin with a 1 µF capacitor.
PWR
Headphone Amplifier Power, 1.8 V to 3.3 V Analog Supply. Decouple this pin to AGND
with a 0.1 μF capacitor. The PCB trace to this pin must have the capacity to supply the
higher current necessary for driving the headphone outputs.
D2
D6
HPOUTRN/LOUTRN
ADDR1/MOSI
A_OUT Right Headphone Output Inverted (HPOUTRN).
Line Output Inverted (LOUTRN).
D_IN
I2C Address 1 (ADDR1).
SPI Data Input (MOSI).
D7
E1
E2
MICBIAS1
AGND
HPOUTLP/LOUTLP
A_OUT Bias Voltage for Electret Microphone. Decouple this pin with a 1 µF capacitor.
PWR Headphone Amplifier Ground.
A_OUT Left Headphone Output Noninverted (HPOUTLP).
Line Output Noninverted, Single-Ended Line Output (LOUTLP).
E3
PD
D_IN
Active Low Power-Down. All digital and analog circuits are powered down. An internal
pull-down resistor is on this pin; therefore, the ADAU1777 is held in power-down mode if
its input signal is floating while power is applied to the supply pins.
E4
E5
E6
E7
F1
AIN3
AIN0
SELFBOOT
AVDD
HPOUTLN/LOUTLN
A_IN
A_IN
D_IN
PWR
ADC3 Input.
ADC0 Input.
Self Boot Enable. Pull this pin up to IOVDD at power-up to enable the self boot mode.
1.8 V to 3.3 V Analog Supply. Decouple this pin to AGND with a 0.1 μF capacitor.
A_OUT Left Headphone Output Inverted (HPOUTLN).
Line Output Inverted (LOUTLN).
F2
F3
F4
F5
F6
AVDD
AGND
AIN2
AIN1
CM
PWR
PWR
A_IN
A_IN
1.8 V to 3.3 V Analog Supply. Decouple this pin to AGND with a 0.1 μF capacitor.
Analog Ground.
ADC2 Input.
ADC1 Input.
A_OUT AVDD/2 V Common-Mode Reference. Connect a 10 μF to 47 μF decoupling capacitor
between this pin and ground to reduce crosstalk between the ADCs and DACs. The
material of the capacitors is not critical. This pin can bias external analog circuits, as long
as they are not drawing current from CM (for example, the noninverting input of an op amp).
F7
AGND
PWR
Analog Ground. The AGND and DGND pins can be tied directly together in a common
ground plane. Decouple AGND to AVDD with a 0.1 μF capacitor.
1 PWR is power; D_IO is digital input/output; A_OUT is analog output; D_IN is digital input; and A_IN is analog input.
Rev. 0 | Page 16 of 108
Data Sheet
ADAU1777
TYPICAL PERFORMANCE CHARACTERISTICS
0.4
0.2
120
110
100
90
80
70
60
50
40
30
20
10
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
–2.2
–2.4
–2.6
–2.8
–3.0
100
1k
10k
0
4
8
12
16
20
24
28
32
36
40
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 10. Relative Level vs. Frequency, fS = 96 kHz, Signal Path = AIN0 to
DSP (Without Processing) to LOUTLx
Figure 13. Group Delay vs. Frequency, fS = 96 kHz, Signal Path = AIN0 to
DSP (Without Processing) to LOUTLx
–100
–150
–200
–250
–300
–350
–400
–450
–500
–550
–600
–650
–700
–750
–800
–850
–900
–950
–1000
–1050
–1100
–155
–160
–165
–170
–175
–180
–185
–190
–195
–200
–205
–210
–215
–220
–225
0
4
8
12
16
20
24
28
32
36
40
0.1
0.3
0.5
0.9
0.9
1.1
1.3
1.5
1.7
1.9
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 11. Phase vs. Frequency, 40 kHz Bandwidth, fS = 96 kHz,
Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
Figure 14. Phase vs. Frequency, 2 kHz Bandwidth, fS = 96 kHz,
Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
1
0
120
110
100
90
80
70
60
50
40
30
20
10
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
100
1k
10k
0
10
20
30
40
50
60
70
80
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 12. Relative Level vs. Frequency, fS = 192 kHz, Signal Path = AIN0 to
DSP (Without Processing) to LOUTLx
Figure 15. Group Delay vs. Frequency, fS = 192 kHz, Signal Path = AIN0 to
DSP (Without Processing) to LOUTLx
Rev. 0 | Page 17 of 108
ADAU1777
Data Sheet
0
–100
–155
–160
–165
–170
–175
–180
–185
–190
–195
–200
–205
–210
–215
–220
–225
–200
–300
–400
–500
–600
–700
–800
–900
–1000
–1100
–1200
–1300
–1400
0
10
20
30
40
50
60
70
80
0.1
0.3
0.5
0.9
0.9
1.1
1.3
1.5
1.7
1.9
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 16. Phase vs. Frequency, 80 kHz Bandwidth, fS = 192 kHz,
Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
Figure 19. Phase vs. Frequency, 2 kHz Bandwidth, fS = 192 kHz,
Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
120
110
100
90
80
70
60
50
40
30
20
10
0
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
–0.50
100
1k
10k
0
10
20
30
40
50
60
70
80
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 17. Relative Level vs. Frequency, fS =768 kHz, Signal Path = AIN0 to
DSP (Without Processing) to LOUTLx
Figure 20. Group Delay vs. Frequency, fS =768 kHz, Signal Path = AIN0 to
DSP (Without Processing) to LOUTLx
–140
–160
–180
–200
–220
–240
–260
–280
–300
–320
–340
–360
–380
–400
–420
–160
–162
–164
–166
–168
–170
–172
–174
–176
–178
–180
–182
–184
–186
0
10
20
30
40
50
60
70
80
0.1
0.3
0.5
0.9
0.9
1.1
1.3
1.5
1.7
1.9
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 18. Phase vs. Frequency, 80 kHz Bandwidth, fS =768 kHz,
Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
Figure 21. Phase vs. Frequency, 2 kHz Bandwidth, fS =768 kHz,
Signal Path = AIN0 to DSP (Without Processing) to LOUTLx
Rev. 0 | Page 18 of 108
Data Sheet
ADAU1777
1.0
0.5
0
300
280
260
240
220
200
180
160
140
120
100
80
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
60
40
20
0
100
1k
10k
0
4
8
12
16
20
24
28
32
36
40
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 22. Relative Level vs. Frequency, fS = 96 kHz,
Signal Path = AIN0 to ASRC to ADC_SDATA0
Figure 25. Group Delay vs. Frequency, fS = 96 kHz, Signal Path =
AIN0 to ASRC to ADC_SDATA0
200
100
10
5
0
0
–100
–200
–300
–400
–500
–600
–700
–800
–900
–1000
–1100
–1200
–1300
–1400
–1500
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
0
4
8
12
16
20
24
28
32
36
40
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 23. Phase vs. Frequency, 40 kHz Bandwidth, fS = 96 kHz,
Signal Path = AIN0 to ASRC to ADC_SDATA0
Figure 26. Phase vs. Frequency, 2 kHz Bandwidth, fS = 96 kHz,
Signal Path = AIN0 to ASRC to ADC_SDATA0
2
0
300
280
260
240
220
200
180
160
140
120
100
80
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
–22
60
40
20
0
100
1k
10k
0
10
20
30
40
50
60
70
80
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 24. Relative Level vs. Frequency, fS = 192 kHz,
Signal Path = AIN0 to ASRC to ADC_SDATA0
Figure 27. Group Delay vs. Frequency, fS = 192 kHz,
Signal Path = AIN0 to ASRC to ADC_SDATA0
Rev. 0 | Page 19 of 108
ADAU1777
Data Sheet
200
10
5
0
–200
–400
–600
–800
–1000
–1200
–1400
–1600
–1800
0
–5
–10
–15
–20
–25
–30
–35
–40
0
10
20
30
40
50
60
70
80
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 28. Phase vs. Frequency, 80 kHz Bandwidth,
fS = 192 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
Figure 31. Phase vs. Frequency, 2 kHz Bandwidth,
fS = 192 kHz, Signal Path = AIN0 to ASRC to ADC_SDATA0
2
1
0
–1
–2
–3
–4
–5
–6
–7
300
280
260
240
220
200
180
160
140
120
100
80
–8
–9
–10
–11
–12
–13
–14
–15
–16
60
40
20
0
100
1k
10k
0
10
20
30
40
50
60
70
80
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 29. Relative Level vs. Frequency, fS = 786 kHz, Signal Path = AIN0 to
ASRC to ADC_SDATA0
Figure 32. Group Delay vs. Frequency, fS = 786 kHz, Signal Path = AIN0 to
ASRC to ADC_SDATA0
100
0
25
20
–100
–200
–300
–400
–500
–600
–700
–800
–900
–1000
–1100
–1200
–1300
15
10
5
0
–5
–10
–15
–20
–25
–30
0
10
20
30
40
50
60
70
80
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 30. Phase vs. Frequency, 80 kHz Bandwidth, fS = 786 kHz,
Signal Path = AIN0 to ASRC to ADC_SDATA0
Figure 33. Phase vs. Frequency, 2 kHz Bandwidth, fS = 786 kHz,
Signal Path = AIN0 to ASRC to ADC_SDATA0
Rev. 0 | Page 20 of 108
Data Sheet
ADAU1777
0.5
0
300
280
260
240
220
200
180
160
140
120
100
80
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
60
40
20
0
100
1k
10k
0
4
8
12
16
20
24
28
32
36
40
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 34. Relative Level vs. Frequency, fS = 96 kHz,
Signal Path = DAC_SDATA to ASRC to LOUTLx
Figure 37. Group Delay vs. Frequency, fS = 96 kHz,
Signal Path = DAC_SDATA to ASRC to LOUTLx
200
100
0
–150
–155
–160
–165
–170
–175
–180
–185
–190
–195
–200
–205
–210
–215
–220
–225
–230
–235
–240
–245
–250
–100
–200
–300
–400
–500
–600
–700
–800
–900
–1000
–1100
–1200
–1300
–1400
–1500
–1600
–1700
0
4
8
12
16
20
24
28
32
36
40
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 35. Phase vs. Frequency, 40 kHz Bandwidth,
fS = 96 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
Figure 38. Phase vs. Frequency, 2 kHz Bandwidth,
fS = 96 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
1.0
0.5
0
300
280
260
240
220
200
180
160
140
120
100
80
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
60
40
20
0
100
1k
10k
0
10
20
30
40
50
60
70
80
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 36. Relative Level vs. Frequency,
fS = 192 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
Figure 39. Group Delay vs. Frequency,
fS = 192 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
Rev. 0 | Page 21 of 108
ADAU1777
Data Sheet
0
–100
–200
–300
–400
–500
–600
–700
–800
–160
–165
–170
–175
–180
–185
–190
–195
–200
–205
–210
–215
–900
–1000
–1100
–1200
–1300
–1400
–1500
–1600
–1700
–1800
0
10
20
30
40
50
60
70
80
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 40. Phase vs. Frequency, 80 kHz Bandwidth,
fS = 192 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
Figure 43. Phase vs. Frequency, 2 kHz Bandwidth,
fS = 192 kHz, Signal Path = DAC_SDATA to ASRC to LOUTLx
300
0.4
0.2
0
280
260
240
220
200
180
160
140
120
100
80
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
–2.2
–2.4
–2.6
–2.8
–3.0
–3.2
–3.4
60
40
20
0
100
1k
10k
0
10
20
30
40
50
60
70
80
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 41. Relative Level vs. Frequency, fS = 786 kHz, Signal Path =
DAC_SDATA to ASRC to LOUTLx
Figure 44. Group Delay vs. Frequency, fS = 786 kHz, Signal Path =
DAC_SDATA to ASRC to LOUTLx
–100
–150
–200
–250
–300
–350
–400
–450
–500
–550
–600
–650
–700
–750
–800
–850
–900
–950
–1000
–1050
–1100
–160
–165
–164
–166
–168
–170
–172
–174
–176
–178
–180
–182
–184
–186
–188
–190
–192
–194
–196
–198
–200
0
4
8
12
16
20
24
28
32
36
40
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 42. Phase vs. Frequency, 20 kHz Bandwidth, fS = 786 kHz,
Signal Path = DAC_SDATA to ASRC to LOUTLx
Figure 45. Phase vs. Frequency, 2 kHz Bandwidth fS = 786 kHz,
Signal Path = DAC_SDATA to ASRC to LOUTLx
Rev. 0 | Page 22 of 108
Data Sheet
ADAU1777
35
30
25
20
15
10
5
2
0
–2
–4
–6
–8
–10
0
0
5
10
15
20
–12
–6
0
6
12
18
24
30
36
FREQUENCY (kHz)
PGA GAIN SETTING (dB)
Figure 49. Interpolation Pass Band Response, fS = 768 kHz
Figure 46. Input Impedance vs. PGA Gain Setting
(See the Input Impedance Section)
2
0
0
–20
–2
–40
–60
–4
–6
–80
–100
–120
–8
–10
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 50. Total Interpolation Response, fS = 768 kHz
Figure 47. Decimation Pass Band Response, fS = 768 kHz
0
–20
–40
–60
–80
–100
–120
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (kHz)
Figure 48. Total Decimation Response, fS = 768 kHz
Rev. 0 | Page 23 of 108
ADAU1777
Data Sheet
THEORY OF OPERATION
The ADAU1777 is a low power audio codec with a streamlined
audio processing core, making it ideal for noise canceling
applications that require high quality audio, low power, small
size, and low latency. The operating voltage range is 1.71 V to
3.63 V, with an on-board regulator optionally generating the
internal digital supply voltage. By enabling low latency settings,
the ADAU1777 can reach latencies as low as 5 μs.
control individual signal processing blocks. The ADAU1777
also has a self boot function that can load the program RAM,
parameter RAM, and register settings on power-up using an
external EEPROM.
The SigmaStudio software programs and controls the core through
the I2C or SPI control port. Along with aiding in the design and
tuning of a signal flow, SigmaStudio can configure all of the
ADAU1777 registers. The SigmaStudio graphical interface allows
anyone with digital or analog audio processing knowledge to
easily design the DSP signal flow and port it to a target
application. The interface also provides enough flexibility and
programmability for an experienced DSP programmer to have
in-depth control of the design. In SigmaStudio, the user can
connect graphical blocks (such as biquad filters, volume controls,
and arithmetic operations), compile the design, and load the
program and parameter files into the ADAU1777 memory
through the control port. SigmaStudio also allows the user to
download the design to an external EEPROM for self boot
operation. Signal processing blocks available in the provided
libraries include the following:
The ADCs and DACs are high quality, 24-bit, Σ-Δ converters
that operate at a selectable 768 kHz, 192 kHz, or 96 kHz
sampling rate. The ADCs have an optional high-pass filter with
a cutoff frequency of 1 Hz, 4 Hz, or 8 Hz. The ADCs and DACs
also include fine step digital volume controls.
The stereo DAC output can differentially drive a headphone
earpiece speaker with 16 Ω or higher impedance. One side of
the differential output can be powered down if single-ended
operation is required. There is also the option to change to line
output mode when the output has a low load.
The input signal path is flexible and can accept single-ended
analog microphone inputs, serial audio inputs, and digital
microphone inputs. Two microphone bias pins provide seamless
interfacing to electret microphones. Each analog input has an
independent PGA that can be used for volume adjustment. The
serial data port is compatible with I2S, left justified, right
justified, and TDM modes, with tristating for interfacing to
digital audio data streams.
•
•
•
•
•
Single-precision biquad filters
Second-order filters
Absolute value and two-input adder
Volume controls
Limiter
The core has a reduced instruction set that is optimized for
active noise cancellation. The program and parameter RAMs
can be loaded with custom audio processing signal flows built
using the SigmaStudio™ graphical programming software from
Analog Devices, Inc. The values stored in the parameter RAM
The ADAU1777 can generate its internal clocks from a wide range
of input clocks by using the on-board fractional PLL. The PLL
accepts inputs from 8 MHz to 27 MHz. For standalone operation,
the clock can be generated using the on-board crystal oscillator.
Rev. 0 | Page 24 of 108
Data Sheet
ADAU1777
SYSTEM CLOCKING AND POWER-UP
Control Port Access During Initialization
CLOCK INITIALIZATION
During the lock acquisition period, only Register 0x00 to Register
0x06 are accessible through the control port. A read or write to any
other register is prohibited until the core clock enable bit and the
lock bit are both asserted. After the CORE_RUN bit (Address 0x09)
is set high, the following register bits must not be changed:
The ADAU1777 can generate its clocks either from an externally
provided clock or from a crystal oscillator. In both cases, the
on-board PLL can be used or the clock can be fed directly to
the core. When a crystal oscillator is used, it is desirable to use a
12.288 MHz crystal, and the crystal oscillator function must be
enabled in the COREN bit (Address 0x00, Bit 0). If the PLL is
used, it must always be set to output 24.576 MHz. The PLL can
be bypassed if a clock of 12.288 MHz or 24.576 MHz is available
in the system. Bypassing the PLL saves system power.
ADC_0_1_SINC and ADC_2_3_SINC
DAC_SOURCE0 and DAC_SOURCE1
If these bits must be changed after the ADAU1777 is running,
the CORE_RUN bit first must be disabled.
The CC_MDIV and CC_CDIV bits must not be changed after
setup, but the CLKSRC bit can be switched while the core is
running.
PLL
The PLL uses the MCLKIN signal as a reference to generate
the core clock. The PLL settings are set in Register 0x00 to
Register 0x05. Depending on the MCLK frequency, the PLL
must be set for either integer or fractional mode. The PLL can
accept input frequencies in the range of 8 MHz to 27 MHz.
Set the CC_MDIV and CC_CDIV bits so that the core and
internal master clock are always 12.288 MHz; for example,
when using a 24.576 MHz external source clock or if using the
PLL, it is necessary to use the internal divide by 2 (see Table 11).
TO PLL
CLOCK DIVIDER
Table 11. Clock Configuration Settings
MCLK
÷X
× (R + N/M)
CC_MDIV
CC_CDIV
Description
Figure 51. PLL Block Diagram
1
1
Divide the PLL/external clock by 1.
Use these settings for a 12.288 MHz
direct input clock source.
Divide the PLL/external clock by 2. Use
these settings for a 24.576 MHz direct
input clock source or if using the PLL.
Input Clock Divider
Before reaching the PLL, the input clock signal goes through an
integer clock divider to ensure that the clock frequency is within
a suitable range for the PLL. The X bits in the PLL_CTRL4 register
(Address 0x05, Bits[2:1]) set the PLL input clock divide ratio.
0
0
Integer Mode
PLL Bypass Setup
Use integer mode when the clock input is an integer multiple of
the PLL output.
On power-up, the ADAU1777 exits an internal reset after 15 ms.
The rate of the internal master clock must be set properly using
the CC_MDIV bit in the clock control register (Address 0x00).
When bypassing the PLL, the clock associated with MCLKIN must
be either 12.288 MHz or 24.576 MHz. The internal master clock
of the ADAU1777 is disabled until the COREN bit is asserted.
For example, if MCLKIN = 12.288 MHz, (X + 1) = 1, and fS =
48 kHz,
PLL Required Output = 24.576 MHz
R/2 = 24.576 MHz/12.288 MHz = 2
where R/2 = 2 or R = 4.
PLL Enabled Setup
The core clock of the ADAU1777 is disabled by the default
setting of the COREN bit and must remain disabled during the
PLL lock acquisition period. The user can poll the lock bit to
determine when the PLL has locked. After lock is acquired, the
ADAU1777 can be started by asserting the COREN bit. This bit
enables the core clock for all the internal blocks of the ADAU1777.
In integer mode, the values set for N and M are ignored. Table 12
lists common integer PLL parameter settings for 48 kHz
sampling rates.
Fractional Mode
Use fractional mode when the clock input is a fractional
multiple of the PLL output.
To program the PLL during initialization or reconfiguration of
the codec, use the following procedure:
For example, if MCLKIN = 13 MHz, (X + 1) = 1, and fS = 48 kHz,
1. Ensure that PLL_EN (Bit 7, Address 0x00) is set low.
2. Set or reset the PLL control registers (Address 0x01 to
Address 0x05).
3. Enable the PLL using the PLL_EN bit.
4. Poll the PLL lock bit in Register 0x06.
5. Set the COREN bit in Register 0x00 after the PLL lock is
acquired.
PLL Required Output = 24.576 MHz
(1/2) × (R + (N/M)) = 24.576 MHz/13 MHz = (1/2) × (3 +
(1269/1625))
where:
R = 3.
N = 1269.
M = 1625.
Rev. 0 | Page 25 of 108
ADAU1777
Data Sheet
Table 13 lists common fractional PLL parameter settings for
48 kHz sampling rates. When the PLL is used in fractional
mode, the N/M fraction must be kept in the range of 0.1 to 0.9
to ensure correct operation of the PLL.
PD
pin powers down all analog and digital circuits.
Enabling the
Before enabling
(that is, setting it low), be sure to mute the
PD
outputs to avoid any pops when the IC is powered down. Tie
PD
directly to IOVDD for normal operation.
The PLL output clock must be kept in the range of 20.5 MHz to
27 MHz, which must be taken into account when calculating PLL
values and MCLK frequencies.
Power-Down Considerations
When powering down the ADAU1777, mute the outputs before
AVDD power is removed; otherwise, pops or clicks may be
heard. The easiest way to achieve this is to use a regulator that has
a power-good (PGOOD) signal to power the ADAU1777 or to
generate a power-good signal using additional circuitry external
to the regulator itself. Typically, on such regulators, the power-good
signal changes state when the regulated voltage drops below ~90%
of its target value. Connect this power-good signal to one of the
ADAU1777 multipurpose pins and mute the DAC outputs by
setting the multipurpose pin functionality to mute both DACs
in Register 0x38 to Register 0x3E. Taking these precautions
ensures that the outputs are muted before power is completely
removed.
CLOCK OUTPUT
Use the CLKOUT pin as a master clock output to clock other
ICs in the system or as the clock for the digital microphone inputs
and PDM output. This clock can be generated from the 12.288
MHz master clock of the ADAU1777 by factors of 2, 1, ½, ¼,
and ⅛. If PDM mode is enabled, only the ½, ¼, and ⅛ settings
produce a clock signal on CLKOUT. The factor of 2 multiplier
works properly only if the input clock was previously divided by
2 using the CC_MDIV bit.
POWER SEQUENCING
AVDD and IOVDD can each be set to any voltage between 1.8 V
and 3.3 V, and DVDD can be set between 1.1 V and 1.8 V or
between 1.1 V and 1.2 V if using the on-board regulator.
On power-up, AVDD must be powered up before or at the same
time as IOVDD. Do not power up IOVDD when power is not
applied to AVDD.
Table 12. Integer PLL Parameter Settings for PLL Output = 24.576 MHz
MCLK Input (MHz) Input Divider (X + 1) Integer (R) Denominator (M) Numerator (N) PLL_CTRL4 Settings (Address 0x05)
12.288
24.576
1
1
4
2
Don’t care
Don’t care
Don’t care
Don’t care
0x20
0x10
Table 13. Fractional PLL Parameter Settings for PLL Output = 24.576 MHz
PLL Parameter Register Settings (Address 0x05 to Address 0x01)
Divider Integer Denominator Numerator PLL_CTRL4
PLL_CTRL3 PLL_CTRL2 PLL_CTRL1 PLL_CTRL0
(Addr. 0x05) (Addr. 0x04) (Addr. 0x03) (Addr. 0x02) (Addr. 0x01)
MCLK Input
Input
(MHz) (X + 1)
(R)
6
3
6
5
(M)
125
1625
75
25
1625
1125
(N)
18
1269
62
3
1269
721
8
13
14.4
19.2
26
1
1
2
2
2
2
0x31
0x19
0x33
0x2B
0x1B
0x1B
0x12
0xF5
0x3E
0x03
0xF5
0xD1
0x00
0x04
0x00
0x00
0x04
0x02
0x7D
0x59
0x4B
0x19
0x59
0x65
0x00
0x06
0x00
0x00
0x06
0x04
3
3
27
Rev. 0 | Page 26 of 108
Data Sheet
ADAU1777
SIGNAL ROUTING
The ADAU1777 features flexible signal routing. The signal
routing is specified by Register 0x0F through Register 0x1A.
PGA
AIN0
ADC
MODULATOR
ADC
DECIMATOR
AIN1
PGA
HPOUTLP/LOUTLP
HPOUTLN/LOUTLN
ADC
MODULATOR
DAC
DAC
ADC
DECIMATOR
DAC
AND
HPOUTRP/LOUTRP
HPOUTRN/LOUTRN
CORE
INPUT
SELECTION
AUDIO
PROCESSING
CORE
DMIC0_1/MP4
DMIC2_3/MP5
DIGITAL
PDM
MICROPHONE
INPUTS
OUTPUT
SELECTION
ADC
STEREO PDM
MODULATOR
1
PDMOUT
PGA
AIN2
AIN3
DECIMATOR
ADC
MODULATOR
ADC
DECIMATOR
PGA
ADC
MODULATOR
STEREO INPUT
ASRC
SERIAL
INPUT PORT
DUAL STEREO
OUTPUT ASRCs
DAC_SDATA
1
ADC_SDATA0
SERIAL
OUTPUT PORT
ADC_SDATA1
1
THE ADC_SDATA0 AND PDMOUT FUNCTIONS SHARE A PHYSICAL PIN; THEREFORE ONLY ONE OF THESE FUNCTIONS CAN BE USED AT A TIME.
Figure 52. Input and Output Signal Routing
Rev. 0 | Page 27 of 108
ADAU1777
Data Sheet
INPUT SIGNAL PATHS
Four input paths, from either an ADC or a digital microphone,
can be routed to the core. The input sources (ADC or digital
microphone) must be configured in pairs (for example, 0 and 1,
or 2 and 3), but each channel can be routed individually. The
core inputs can also be sourced from a stereo input ASRC.
Analog Line Inputs
Line level signals can be input on the AINx pins of the analog
inputs. Figure 54 shows a single-ended line input using the
AINx pins.
ADAU1777
ANALOG INPUTS
LINE INPUT 0
LINE INPUT 1
LINE INPUT 2
LINE INPUT 3
AIN0
AIN1
AIN2
AIN3
The ADAU1777 can accept both line level and microphone inputs.
Each of the four analog input channels can be configured in
single-ended mode or a single-ended with PGA mode. There
are also inputs for up to four digital microphones. The analog
inputs are biased at AVDD/2 V. Connect unused input pins to
the CM pin or ac-couple them to ground.
Figure 54. Single-Ended Line Inputs
Precharging Input Capacitors
Signal Polarity
Precharge amplifiers are enabled by default to charge large series
capacitors quickly on the inputs and outputs. Precharging these
capacitors prevents pops in the audio signal. The precharge circuits
are powered up by default on startup and can be disabled in the
POP_SUPPRESS register. The precharge amplifiers are automati-
cally disabled when the PGA or headphone amplifiers are enabled.
For unused PGAs and headphone outputs, disable these precharge
amplifiers using the POP_SUPPRESS register. The precharging
time is dependent on the input/output series capacitors. The
impedance looking into the AINx pin is 500 ꢁ in this mode.
However, at startup, the impedance looking into the pin is
dominated by the time constant of the CM pin because the
precharge amplifiers reference the CM voltage.
Signals routed through the PGAs are inverted. As a result, signals
input through the PGA are output from the ADCs with a polarity
that is opposite that of the input. Single-ended inputs are not
inverted. The ADCs are noninverting.
Input Impedance
The input impedance of the analog inputs varies with the gain of
the PGA. This impedance ranges from 0.68 kΩ at the +35.25 dB
gain setting to 32.0 kΩ at the −12 dB setting. The resistors inside
the ADAU1777 are precisely matched to each other, resulting in
very little gain error. However, the exact value of the resistors
depends on various conditions in the silicon manufacturing
process and can vary by as much as 20ꢀ. The input impedance
(RIN) on each pin can be calculated as follows:
Microphone Bias
40
The ADAU1777 includes two microphone bias outputs: MICBIAS0
and MICBIAS1. These pins provide a voltage reference for electret
analog microphones. The MICBIASx pins also cleanly supply
voltage to digital or analog microelectromechanical systems
(MEMS) microphones with separate power supply pins. The
MICBIASx voltage is set in the microphone bias control register
(Address 0x2D). Using this register, the MICBIAS0 or MICBIAS1
output can be enabled or disabled. The gain options provide
two possible voltages: 0.65 × AVDD or 0.90 × AVDD.
RIN
kΩ
10 (Gain / 20 ) 1
where Gain is set by PGA_GAINx.
The optional 10 dB PGA boost, set in the PGA_x_BOOST bits,
does not affect the input impedance. This setting is an alternative
way of increasing gain without decreasing input impedance;
however, it causes some degradation in performance.
Analog Microphone Inputs
For microphone signals, the ADAU1777 analog inputs can be
configured as single-ended with PGA mode.
Many applications require enabling only one of the two bias
outputs. The two bias outputs must both be enabled when many
microphones are used in the system or when the positioning of
the microphones on the PCB does not allow one pin to bias all
microphones.
The PGA settings are controlled in Register 0x23 to Register 0x26.
The PGA is enabled by setting the PGA_ENx bits.
Connect the microphone signal to the inverting inputs of the
PGAs (AINx), as shown in Figure 53.
ADAU1777
PGA
AINx
MICROPHONE
–12dB TO
+35.25dB
2kΩ
MICBIASx
Figure 53. Single-Ended Microphone Configuration
Rev. 0 | Page 28 of 108
Data Sheet
ADAU1777
Figure 55 shows two digital microphones connected to the
DIGITAL MICROPHONE INPUT
DMIC0_1/MP4 pin. These microphones can also be connected
to DMIC2_3/MP5 if that signal path is to be used for digital
microphones. If more than two digital microphones are to be
used in a system, then up to two microphones are connected to
both DMIC0_1/MP4 and DMIC2_3/MP5 and the CLKOUT
signal is fanned out to the clock input of all of the microphones.
When using a digital microphone connected to the DMIC0_1/MP4
and DMIC2_3/MP5 pins, the DCM_0_1 and DCM_2_3 bits in
Register 0x1D and Register 0x1E must be set to enable the
digital microphone signal paths. Set the pin functions to digital
microphone input in the corresponding pin mode registers
(Address 0x3C and Address 0x3D). The DMIC0/DMIC2 and
DMIC1/DMIC3 channels can be swapped (left/right swap) by
writing to the DMIC_SW0 and DMIC_SW1 bits in the ADC_
CONTROL2 and ADC_CONTROL3 registers (Address 0x1D
and Address 0x1E, respectively). In addition, the microphone
polarity can be reversed by setting the DMIC_POLx bits, which
reverses the phase of the incoming audio by 180°.
ANALOG-TO-DIGITAL CONVERTERS (ADCs)
The ADAU1777 includes four 24-bit, Σ-Δ ADCs, each with a
selectable sample rate of 768 kHz, 192 kHz, or 96 kHz.
ADC Full-Scale Level
The full-scale input to the ADCs (0 dBFS) scales linearly with
AVDD. At AVDD = 3.3 V, the full-scale input level is 1 V rms.
Signal levels greater than the full-scale value cause the ADCs to
clip.
The digital microphone inputs are clocked from the CLKOUT pin.
The digital microphone data stream must be clocked by this pin
and not by a clock from another source, such as another audio
IC, even if the other clock is of the same frequency as CLKOUT.
Digital ADC Volume Control
The volume setting of each ADC can be digitally attenuated in the
ADCx_VOLUME registers (Address 0x1F to Address 0x22). The
volume can be set between 0 dB and −95.625 dB in 0.375 dB steps.
The ADC volume can also be digitally muted in the ADC_
CONTROLx registers (Address 0x1B to Address 0x1E).
The digital microphone signal bypasses the analog input path
and the ADCs and is routed directly into the decimation filters.
The digital microphone and the ADCs share digital filters and,
therefore, both cannot be used simultaneously. The digital micro-
phone inputs are enabled in pairs. The ADAU1777 inputs can
be set for either four analog inputs, four digital microphone inputs,
or two analog inputs and two digital microphone inputs. Figure 55
shows the digital microphone interface and signal routing.
1.8V TO 3.3V
High-Pass Filter
A high-pass filter is available on the ADC path to remove dc offsets;
this filter can be enabled or disabled using the HP_x_y_EN bits.
At fS = 192 kHz, the corner frequency of this high-pass filter can
be set to 1 Hz, 4 Hz, or 8 Hz.
CLK
ADAU1777
V
DATA
DIGITAL
MICROPHONE
L/R SELECT GND
DD
0.1µF
CLKOUT
DMIC0_1
CLK
V
DATA
DIGITAL
MICROPHONE
L/R SELECT GND
DD
0.1µF
Figure 55. Digital Microphone Interface Block Diagram
Rev. 0 | Page 29 of 108
ADAU1777
Data Sheet
OUTPUT SIGNAL PATHS
Data from the serial input port can be routed to the core, to the
output selection multiplexer, or directly to the serial output
ports. Data from the core can be routed to the serial output
port, the stereo DAC, and the stereo PDM modulator (see
Figure 52).
Pop and Click Suppression
On power-up, the precharge circuitry is enabled on all four
analog output pins to suppress pops and clicks. After power-
up, the precharge circuitry can be set to a low power mode
using the HP_POP_DISx bits in the POP_SUPRRESS register
(Address 0x29).
The analog outputs of the ADAU1777 can be configured as
differential or single-ended outputs. The analog output pins can
drive headphone or earpiece speakers. The line outputs can
drive a load of at least 10 kΩ or can be set into headphone mode
to drive headphones or earpiece speakers. The analog output
pins are biased at AVDD/2.
The precharge time depends on the value of the capacitor
connected to the CM pin and the RC time constant of the load
on the output pin. For a typical line output load, the precharge
time is between 2 ms and 3 ms. After this precharge time, the
HP_POP_DISx bits can be set to low power mode.
ANALOG OUTPUTS
Headphone Output
To avoid clicks and pops, mute all analog outputs that are in use
while changing any register settings that may affect the signal path.
These outputs can then be unmuted after the changes are made.
The output pins can be driven by either a line output driver or a
headphone driver by setting the HP_EN_L and HP_EN_R bits
in the headphone line output select register (Address 0x43). The
headphone outputs can drive a load of at least 16 Ω.
Line Outputs
The analog output pins (HPOUTLP/LOUTLP, HPOUTLN/
LOUTLN, HPOUTRP/LOUTRP, and HPOUTRN/LOUTRN)
can be used to drive both differential and single-ended loads. In
their default settings, these pins can drive typical line loads of
10 kΩ or greater.
Headphone Output Power-Up Sequencing
To prevent pops when turning on the headphone outputs, wait
at least 6 ms to unmute these outputs after enabling the headphone
output using the HP_EN_x bits. Waiting 6 ms allows an internal
capacitor to charge before these outputs are used. Figure 56
illustrates the headphone output power-up sequencing.
When the line output pins are used in single-ended mode, use
the HPOUTLP/LOUTLP and HPOUTRP/LOUTRP pins to
output the signals, and power down the HPOUTLN/LOUTLN
and HPOUTRN/LOUTRN pins.
USER
DEFINED
6ms
DIGITAL-TO-ANALOG CONVERTERS (DACs)
The ADAU1777 includes two 24-bit, Σ-Δ DACs.
DAC Full-Scale Level
HP_EN_R AND HP_EN_L
1 = HEADPHONE
HP_MUTE_R AND HP_MUTE_L
00 = UNMUTE
The full-scale output from the DACs (0 dBFS) scales linearly with
AVDD. At AVDD = 3.3 V, the full-scale output level is 1.94 V rms
for a differential output or 0.97 V rms for a single-ended output.
INTERNAL
PRECHARGE
Digital DAC Volume Control
Figure 56. Headphone Output Power-Up Sequencing
The volume of each DAC can be digitally attenuated using the
DACx_VOLUME registers (Address 0x2F and Address 0x30). The
volume can be set to be between 0 dB and −95.625 dB in
0.375 dB steps.
Ground Centered Headphone Configuration
The headphone outputs can also be configured as ground
centered outputs by connecting coupling capacitors in series
with the output pins. Ground centered headphones must use
the AGND pin as the ground reference.
PDM OUTPUT
The ADAU1777 includes a 2-channel PDM modulator. The
PDMOUT pin can be used to drive a PDM input amplifier, such as
the SSM2517 mono 2.4 W amplifier. Two SSM2517 devices can be
connected to the PDMOUT data stream to enable a stereo output.
The PDM output signal is clocked by the CLKOUT pin output. The
PDM output stream must be clocked by this pin and not by a clock
from another source, such as another audio IC, even if the other
clock is of the same frequency as CLKOUT. The PDM output data
is clipped at the −6 dB level to prevent overdriving a connected
amplifier like the SSM2517.
When the headphone outputs are configured as ground
centered, the capacitors create a high-pass filter on the outputs.
The corner frequency of this filter (f3 dB), which has an
attenuation of 3 dB, is calculated by the following formula:
f3 dB = 1/(2π × R × C)
where :
R is the impedance of the headphones.
C is the capacitor value.
For a typical headphone impedance of 32 Ω with a 220 μF
capacitor, the corner frequency is 23 Hz.
Rev. 0 | Page 30 of 108
Data Sheet
ADAU1777
The ADAU1777 has the ability to output PDM control patterns to
configure devices such as the SSM2517. Each pattern is a byte long
and is written with a user defined pattern in the PDM_PATTERN
register (Address 0x37). The control pattern is enabled and the
output channel selection is configured in the PDM_OUT
register (Address 0x36). The PDM pattern must not be changed
while the ADAU1777 is outputting the control pattern to the
external device. After the external device is configured, the
control pattern can be disabled. For the SSM2517, the control
pattern must be repeated a minimum of 128 times to configure
the device. Table 14 describes typical control patterns for the
SSM2517.
SIGNAL LEVELS
The ADCs, DACs, and ASRCs have fixed gain settings that must be
considered when configuring the system. These settings are
chosen to maximize performance of the converters and to ensure
that there is 0 dB gain for any signal path from the input of the
ADAU1777 to its output. Therefore, the full-scale level of a signal
in the processing core is slightly different from a full-scale level
external to the IC.
Input paths, such as through the ADCs and input ASRCs, are
scaled by 0.75, or about −2.5 dB. Output paths, such as through
the DACs or output ASRCs, are scaled by 1.33, or about 2.5 dB.
This scaling is shown in Figure 57.
Table 14. SSM2517 PDM Control Pattern Descriptions
ADC
CORE
DAC
Pattern Control Description
–2.5dB
+2.5dB
0xAC
0xD8
0xD4
0xD2
Power-down. All blocks off except for the PDM
interface. Normal start-up time.
Gain optimized for PVDD = 5 V operation. Overrides
GAIN_FS pin setting.
Gain optimized for PVDD = 3.6 V operation. Overrides
GAIN_FS pin setting.
Gain optimized for PVDD = 2.5 V operation. Overrides
GAIN_FS pin setting.
INPUT
ASRCs
OUTPUT
ASRCs
–2.5dB
+2.5dB
0xD1
0xE1
0xE2
0xE4
fS set to opposite value determined by GAIN_FS pin.
Ultralow electromagnetic interference (EMI) mode.
Half clock cycle pulse mode for power savings.
Special 32 kHz,128 × fS operation mode.
Figure 57. Signal Level Diagram
Because of this input and output scaling, output signals from
the core must be limited to −2.5 dB full scale to prevent the
DACs and ASRCs from clipping.
ASYNCHRONOUS SAMPLE RATE CONVERTERS
The ADAU1777 includes ASRCs to enable synchronous, full
duplex operation of the serial ports. Two stereo ASRCs are
available for the digital outputs, and one stereo ASRC is available
for the digital input signals.
The ASRCs can convert serial output data from the core rates to
the serial port rates of 192 kHz down to less than 8 kHz. All
intermediate frequencies and ratios are also supported.
Rev. 0 | Page 31 of 108
ADAU1777
Data Sheet
SIGNAL PROCESSING
The ADAU1777 processing core is optimized for ANC
processing. The processing capabilities of the core include
biquad filters, limiters, volume controls, and mixing. The core has
four inputs and four outputs. The core is controlled with a 10-bit
program word, with a maximum of 32 instructions per frame.
the CORE_CONTROL register (Address 0x09) or by using the
multipurpose push-button switches, but not by using a combi-
nation of the two. Parameters in the active bank must not be
updated while the core is running; doing so may result in noises
on the outputs.
Parameters are assigned to instructions in the order in which
the instructions are instantiated in the code. The instruction
types that use parameters are the biquad filters and limiters.
INSTRUCTIONS
A complete list of instructions/processing blocks along with
documentation can be found in the SigmaStudio software for
the ADAU1777. The processing blocks available are
Table 17 shows the addresses of each parameter in Bank A that
are associated with each of the 32 instructions, and Table 18 shows
the addresses of each parameter in Bank B. Table 16 shows the
addresses of the LSB aligned, 10-bit program words.
•
•
•
•
•
•
•
•
•
Single precision biquad/second-order filters
Absolute value
Two-input addition
T connection in SigmaStudio
Limiter with/without external detector loop
Linear gain
Volume slider
Mute
DBREG level detection
Table 16. Program Addresses
Instruction
Instruction Address
0x0080
0x0081
0x0082
0x0083
0x0084
0x0085
0x0086
0x0087
0x0088
0x0089
0x008A
0x008B
0x008C
0x008D
0x008E
0x008F
0x0090
0x0091
0x0092
0x0093
0x0094
0x0095
0x0096
0x0097
0x0098
0x0099
0x009A
0x009B
0x009C
0x009D
0x009E
0x009F
0
1
2
3
4
5
6
7
DATA MEMORY
The ADAU1777 data path is 26 bits (5.21 format). The data
memory is 32 words of 2 × 26 bits. The double length memory
enables the core to double precision arithmetic with double
length data and single length coefficients.
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PARAMETERS
Parameters, such as filter coefficients, limiter settings, and volume
control settings, are saved in parameter registers. Each parameter is
a 32-bit number. The format of this number depends on whether it
is controlling a filter or a limiter. The number formats of different
parameters are shown in Table 15. When the parameter formats
use less than the full 32-bit memory space, as with the limiter
parameters, the data is LSB aligned.
Table 15. Parameter Number Formats
Parameter Type
Filter Coefficient (B0, B1, B2)
Filter Coefficient (A1)
Filter Coefficient (A2)
Maximum Gain
Minimum Gain
Attack Time
Decay Time
Threshold
Format
5.27
2.27 (sign extended)
1.27 (sign extended)
2.23
2.23
24.0
24.0
2.23
Two parameter banks are available. Each bank can hold a full
set of 160 parameters (32 filters × 5 coefficients). Users can
switch between Bank A and Bank B, allowing two sets of parame-
ters to be saved in memory and switched on-the-fly while the
codec is running. Bank switching can be achieved by writing to
Rev. 0 | Page 32 of 108
Data Sheet
ADAU1777
Table 17. Parameter Addresses, Bank A
Assignment Order
B0/Maximum Gain
B1/Minimum Gain
0x0100
0x0101
0x0102
0x0103
0x0104
0x0105
0x0106
0x0107
0x0108
0x0109
0x010A
0x010B
0x010C
0x010D
0x010E
0x010F
0x0110
0x0111
0x0112
0x0113
0x0114
0x0115
0x0116
0x0117
0x0118
0x0119
0x011A
0x011B
0x011C
0x011D
0x011E
0x011F
B2/Attack
0x0120
0x0121
0x0122
0x0123
0x0124
0x0125
0x0126
0x0127
0x0128
0x0129
0x012A
0x012B
0x012C
0x012D
0x012E
0x012F
0x0130
0x0131
0x0132
0x0133
0x0134
0x0135
0x0136
0x0137
0x0138
0x0139
0x013A
0x013B
0x013C
0x013D
0x013E
0x013F
A1/Decay
0x0140
0x0141
0x0142
0x0143
0x0144
0x0145
0x0146
0x0147
0x0148
0x0149
0x014A
0x014B
0x014C
0x014D
0x014E
0x014F
0x0150
0x0151
0x0152
0x0153
0x0154
0x0155
0x0156
0x0157
0x0158
0x0159
0x015A
0x015B
0x015C
0x015D
0x015E
0x015F
A2/Threshold
0
1
2
3
4
5
6
7
0x00E0
0x00E1
0x00E2
0x00E3
0x00E4
0x00E5
0x00E6
0x00E7
0x00E8
0x00E9
0x00EA
0x00EB
0x00EC
0x00ED
0x00EE
0x00EF
0x00F0
0x00F1
0x00F2
0x00F3
0x00F4
0x00F5
0x00F6
0x00F7
0x00F8
0x00F9
0x00FA
0x00FB
0x00FC
0x00FD
0x00FE
0x00FF
0x0160
0x0161
0x0162
0x0163
0x0164
0x0165
0x0166
0x0167
0x0168
0x0169
0x016A
0x016B
0x016C
0x016D
0x016E
0x016F
0x0170
0x0171
0x0172
0x0173
0x0174
0x0175
0x0176
0x0177
0x0178
0x0179
0x017A
0x017B
0x017C
0x017D
0x017E
0x017F
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Table 18. Parameter Addresses, Bank B
Assignment Order
B0/Maximum Gain
B1/Minimum Gain
0x01A0
0x01A1
0x01A2
0x01A3
0x01A4
0x01A5
0x01A6
0x01A7
0x01A8
0x01A9
0x01AA
0x01AB
0x01AC
0x01AD
0x01AE
B2/Attack
0x01C0
0x01C1
0x01C2
0x01C3
0x01C4
0x01C5
0x01C6
0x01C7
0x01C8
0x01C9
0x01CA
0x01CB
0x01CC
0x01CD
0x01CE
0x01CF
A1/Decay
0x01E0
0x01E1
0x01E2
0x01E3
0x01E4
0x01E5
0x01E6
0x01E7
0x01E8
0x01E9
0x01EA
0x01EB
0x01EC
0x01ED
0x01EE
0x01EF
A2/Threshold
0x0200
0x0201
0x0202
0x0203
0x0204
0x0205
0x0206
0x0207
0x0208
0x0209
0x020A
0x020B
0x020C
0x020D
0x020E
0x020F
0
1
2
3
4
5
6
7
0x0180
0x0181
0x0182
0x0183
0x0184
0x0185
0x0186
0x0187
0x0188
0x0189
0x018A
0x018B
0x018C
0x018D
0x018E
0x018F
8
9
10
11
12
13
14
15
0x01AF
Rev. 0 | Page 33 of 108
ADAU1777
Data Sheet
Assignment Order
B0/Maximum Gain
0x0190
0x0191
0x0192
0x0193
0x0194
0x0195
0x0196
0x0197
B1/Minimum Gain
0x01B0
0x01B1
0x01B2
0x01B3
0x01B4
0x01B5
0x01B6
0x01B7
B2/Attack
0x01D0
0x01D1
0x01D2
0x01D3
0x01D4
0x01D5
0x01D6
0x01D7
0x01D8
0x01D9
0x01DA
0x01DB
0x01DC
0x01DD
0x01DE
0x01DF
A1/Decay
0x01F0
0x01F1
0x01F2
0x01F3
0x01F4
0x01F5
0x01F6
0x01F7
0x01F8
0x01F9
0x01FA
0x01FB
0x01FC
0x01FD
0x01FE
0x01FF
A2/Threshold
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0x0210
0x0211
0x0212
0x0213
0x0214
0x0215
0x0216
0x0217
0x0218
0x0219
0x021A
0x021B
0x021C
0x021D
0x021E
0x021F
0x0198
0x0199
0x01B8
0x01B9
0x019A
0x019B
0x019C
0x019D
0x019E
0x01BA
0x01BB
0x01BC
0x01BD
0x01BE
0x019F
0x01BF
Rev. 0 | Page 34 of 108
Data Sheet
ADAU1777
CONTROL PORT
The ADAU1777 has both a 4-wire SPI control port and a 2-wire
I2C bus control port. Each port can be used to set the memories
and registers. The IC defaults to I2C mode but can be put into
BURST MODE COMMUNICATION
Use burst mode addressing, in which the subaddresses are
automatically incremented at word boundaries, for writing large
amounts of data to contiguous memory locations. This increment
occurs automatically after a single-word write unless the control
SS
SPI control mode by pulling the pin low three times.
The control port is capable of full read/write operation for all
addressable memories and registers. Most signal processing
parameters are controlled by writing new values to the param-
eter memories using the control port. Other functions, such as
mute and input/output mode control, are programmed through
the registers.
port communication is stopped; that is, a stop condition is issued
2
SS
for I C mode, or is brought high for SPI mode. The registers
and RAMs in the ADAU1777 range in width from one to four
bytes; therefore, the auto-increment feature knows the mapping
between subaddresses and the word length of the destination
register (or memory location).
All addresses can be accessed in either single address mode or
burst mode. The first byte (Byte 0) of a control port write contains
the 7-bit IC address plus the R/ bit. The next two bytes (Byte 1
I2C PORT
W
The ADAU1777 supports a 2-wire serial (I2C-compatible) micro-
processor bus driving multiple peripherals. I2C mode uses two
pins—serial data (SDA) and serial clock (SCL)—to carry data
between the ADAU1777 and the system I2C master controller.
In I2C mode, the ADAU1777 is always a slave on the bus, except
when the IC is self booting. See the Self Boot section for details
about using the ADAU1777 in self boot mode.
and Byte 2) are the 16-bit subaddress of the memory or register
location within the ADAU1777. All subsequent bytes (starting
with Byte 3) contain the data, such as register data, program
data, or parameter data. The number of bytes per word depends
on the type of data that is being written. Table 19 shows the word
length of the different data types of the ADAU1777. The exact
formats for specific types of writes are shown in Figure 60 and
Figure 61.
Each slave device is recognized by a unique 7-bit address. The
ADAU1777 I2C address format is shown in Table 21. The LSB of
this first byte sent from the I2C master sets either a read or write
operation. Logic Level 1 corresponds to a read operation, and
Logic Level 0 corresponds to a write operation.
The ADDR0 and ADDR1 pins set the LSBs of the I2C address
(see Table 22); therefore, each ADAU1777 can be set to one of
four unique addresses. This feature allows multiple ICs to exist
on the same I2C bus without address contention. The 7-bit I2C
addresses are shown in Table 22.
Table 19. Data-Word Sizes
Data Type
Registers
Program
Word Size (Bytes)
1
2
4
Parameters
If large blocks of data must be downloaded to the ADAU1777,
halt the output of the core (using the CORE_RUN bit in the
core control register (Address 0x09)), load new data, and then
restart the core. Halting the core is typically done during the
booting sequence at startup or when loading a new program into
memory.
An I2C data transfer is always terminated by a stop condition.
Both SDA and SCL must have 2.0 kΩ pull-up resistors on the
lines connected to them. The voltage on these signal lines must
not be higher than IOVDD.
Registers and bits shown as reserved in the register map read back
0s. When writing to these registers and bits, such as during a burst
write across a reserved register, or when writing to reserved bits
in a register with other used bits, write 0s.
Table 21. I2C Address Format
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
1
1
1
ADDR1
ADDR0
The control port pins are multifunctional, depending on the
mode in which the device is operating. Table 20 details these
multiple functions.
Table 22. I2C Addresses
ADDR1
ADDR0
Slave Address
0x3C
0x3D
0x3E
0x3F
0
0
1
1
0
1
0
1
Table 20. Control Port Pin Functions
Pin
I2C Mode
SPI Mode
SCL/SCLK
SDA/MISO
ADDR1/MOSI
ADDR0/SS
SCL, input
SCLK, input
MISO, output
MOSI, input
SS, input
SDA, open-collector output
I2C Address Bit 1, input
I2C Address Bit 0, input
Rev. 0 | Page 35 of 108
ADAU1777
Data Sheet
Addressing
high. Figure 58 shows the timing of an I2C write, and Figure 59
shows the timing of an I2C read.
Initially, each device on the I2C bus is in an idle state and monitor-
ing the SDA and SCL lines for a start condition and the proper
address. The I2C master initiates a data transfer by establishing a
start condition, defined by a high to low transition on SDA while
SCL remains high. This condition indicates that an address/data
stream follows. All devices on the bus respond to the start condi-
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the ADAU1777 immediately
jumps to the idle condition. During a given SCL high period,
the user must issue only one start condition, one stop condition, or
a single stop condition followed by a single start condition. If
the user issues an invalid subaddress, the ADAU1777 does not
issue an acknowledge and returns to the idle condition. If the
user exceeds the highest subaddress while in auto-increment mode,
one of two actions is taken. In read mode, the ADAU1777 outputs
the highest subaddress register contents until the master device
issues a no acknowledge, indicating the end of a read. A no
acknowledge condition is where the SDA line is not pulled low on
the ninth clock pulse on SCL. If the highest subaddress location
is reached while in write mode, the data for the invalid byte is
not loaded into any subaddress register, a no acknowledge is issued
by the ADAU1777, and the device returns to the idle condition.
W
tion and shift the next eight bits (the 7-bit address plus the R/ bit)
MSB first. The device that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This ninth bit is an acknowledge bit. All other devices
withdraw from the bus at this point and return to the idle condi-
W
tion. The R/ bit determines the direction of the data. A Logic 0
on the LSB of the first byte indicates that the master is writing
information to the peripheral, whereas a Logic 1 indicates that the
master is reading information from the peripheral after writing
the subaddress and repeating the start address. A data transfer
occurs until a stop condition is encountered. A stop condition
occurs when SDA transitions from low to high while SCL is held
SCL
ADDR1 ADDR0
0
1
1
1
SDA
R/W
1
ACKNOWLEDGE
BY ADAU1777
ACKNOWLEDGE
BY ADAU1777
START BY
MASTER
FRAME 2
SUBADDRESS BYTE 1
FRAME 1
CHIP ADDRESS BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
STOP BY
MASTER
ACKNOWLEDGE
BY ADAU1777
ACKNOWLEDGE
BY ADAU1777
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
DATA BYTE 1
Figure 58. I2C Write to ADAU1777 Clocking
SCL
SDA
0
1
1
1
ADDR1 ADDR0
1
R/W
ACKNOWLEDGE
BY ADAU1777
ACKNOWLEDGE
BY ADAU1777
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
SCL
(CONTINUED)
SDA
(CONTINUED)
0
1
1
1
1
ADDR1 ADDR0
R/W
ACKNOWLEDGE
BY ADAU1777
ACKNOWLEDGE
BY ADAU1777
REPEATED
START BY MASTER
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
CHIP ADDRESS BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
ACKNOWLEDGE
BY ADAU1777
ACKNOWLEDGE STOP BY
BY ADAU1777 MASTER
FRAME 5
READ DATA BYTE 1
FRAME 6
READ DATA BYTE 2
Figure 59. I2C Read from ADAU1777 Clocking
Rev. 0 | Page 36 of 108
Data Sheet
ADAU1777
I2C Read and Write Operations
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1777.
Figure 60 shows the format of a single-word write operation.
Every ninth clock pulse, the ADAU1777 issues an acknowledge
by pulling SDA low.
Figure 63 shows the format of a burst mode read sequence. This
figure shows an example where the target read words are two
bytes. The ADAU1777 increments its subaddress every two bytes
because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other address
ranges may have a variety of word lengths, ranging from one to
four bytes. The ADAU1777 always decodes the subaddress and
sets the auto-increment circuit so that the address increments
after the appropriate number of bytes.
Figure 61 shows the format of a burst mode write sequence. This
figure shows an example where the target destination words are
two bytes, such as the program memory. The ADAU1777 knows
to increment its subaddress register every two bytes because the
requested subaddress corresponds to a register or memory area
with a 2-byte word length.
The format of a single-word read operation is shown in Figure 62.
Figure 60 to Figure 63 use the following abbreviations:
W
Note that the first R/ bit is 0, indicating a write operation because
the subaddress still must be written to set up the internal
address. After the ADAU1777 acknowledges the receipt of the
subaddress, the master must issue a repeated start command
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
W
followed by the chip address byte with the R/ set to 1 (read).
This command causes the SDA pin to reverse and begin driving
2
I C ADDRESS,
S
S
S
S
AS
SUBADDRESS HIGH
AS
SUBADDRESS LOW
AS
DATA BYTE 1
AS
DATA BYTE 2
...
AS
DATA BYTE N
P
P
P
P
R/W = 0
Figure 60. Single-Word I2C Write Format
2
I C ADDRESS,
R/W = 0
SUBADDRESS
SUBADDRESS
LOW
DATA-WORD 1,
BYTE 1
DATA-WORD 1,
BYTE 2
DATA-WORD 2,
BYTE 1
DATA-WORD 2,
BYTE 2
AS
AS
AS
AS
AS
AS
AS ...
HIGH
Figure 61. Burst Mode I2C Write Format
2
2
I C ADDRESS,
SUBADDRESS
SUBADDRESS
LOW
I C ADDRESS,
R/W = 1
AS
AS
AS
AS
S
AS
DATA BYTE 1 AM DATA BYTE 2
...
AM DATA BYTE N
R/W = 0
HIGH
Figure 62. Single-Word I2C Read Format
2
2
I C ADDRESS,
SUBADDRESS
SUBADDRESS
LOW
I C ADDRESS,
R/W = 1
DATA-WORD 1,
BYTE 1
DATA-WORD 1,
BYTE 2
AS
AS
S
AS
AM
AM
...
R/W = 0
HIGH
Figure 63. Burst Mode I2C Read Format
Rev. 0 | Page 37 of 108
ADAU1777
Data Sheet
Read/Write
The first byte of an SPI transaction indicates whether the com-
SPI PORT
By default, the ADAU1777 is in I2C mode, but it can be put into
W
munication is a read or a write with the R/ bit. The LSB of this
SS
SPI control mode by pulling low three times. The device can
first byte determines whether the SPI transaction is a read (Logic
Level 1) or a write (Logic Level 0).
be configured for SPI mode by issuing three SPI writes, which are
in turn ignored by the ADAU1777. The next (fourth) SPI write is
then latched into the SPI port.
Subaddress
SS
The SPI port uses a 4-wire interface—consisting of the
,
The 16-bit subaddress word is decoded into a location of one of
the memories or registers. This subaddress is the location of the
appropriate memory location or register.
SCLK, MOSI, and MISO signals—and is always a slave port.
The signal goes low at the beginning of a transaction and
SS
high at the end of a transaction. The SCLK signal latches MOSI
on a low to high transition. MISO data is shifted out of the
ADAU1777 on the falling edge of SCLK and must be clocked into
a receiving device, such as a microcontroller, on the SCLK rising
edge. The MOSI signal carries the serial input data, and the
MISO signal is the serial output data. The MISO signal remains
tristated until a read operation is requested. Tristating allows other
SPI-compatible peripherals to share the same readback line.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. During a burst mode write, an initial
subaddress is written followed by a continuous sequence of data
for consecutive memory/register locations.
A sample clocking diagram for a single write SPI operation to
the parameter RAM is shown in Figure 64. A sample clocking
diagram of a single read SPI operation is shown in Figure 65.
The MISO pin goes from tristate to being driven at the beginning
of Byte 3. In this example, Byte 0 to Byte 2 contain the addresses
All SPI transactions have the same basic format shown in Table 23.
Timing diagrams are shown in Figure 64 and Figure 65. All data
is written MSB first. The ADAU1777 can be taken out of SPI
W
and the R/ bit and the subsequent bytes carry the data.
PD
mode only by pulling the
pin low or by powering down the IC.
Table 23. Generic SPI Word Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 41
0000000, R/W
Register/Memory Address[15:8]
Register/Memory Address[7:0]
Data
Data
1 Continues to the end of data transmission for the burst mode write.
SS
SCLK
MOSI
Figure 64. SPI Write to ADAU1777 Clocking (Single Write Mode)
SS
SCLK
MOSI
BYTE 0
BYTE 1
BYTE 2
HIGH-Z
HIGH-Z
MISO
DATA
DATA
Figure 65. SPI Read from ADAU1777 Clocking (Single Read Mode)
Rev. 0 | Page 38 of 108
Data Sheet
ADAU1777
Cyclic Redundancy Check (CRC)
SELF BOOT
The ADAU1777 boots up from an EEPROM over the I2C bus when
An 8-bit CRC validates the content of the EEPROM. This CRC is
strong enough to detect single error bursts of up to eight bits in size.
The terminate self boot instruction (0x instruction byte) must be
followed by a CRC byte. The CRC is generated using all of the
EEPROM bytes from Address 0x00 to the last 0x00 instruction
byte. The polynomial for the CRC is
PD
the SELFBOOT pin is set high at power-up and the
high. The state of the SELFBOOT pin is checked only when the
PD
pin is set
ADAU1777 exits a reset via the
is not used after a self boot is complete. During booting, ensure
PD
pin, and when the EEPROM
that a stable DVDD voltage is in the system. The
pin remains
x8 + x2 + x + 1
high during the self boot operation. The master SCL clock output
from the ADAU1777 is derived from the input clock on XTALI/
MCLKIN. A divide by 64 circuit ensures that the SCL output
frequency during the self boot operation is never greater than
400 kHz for most input clock frequencies. With the external master
clock to the ADAU1777 between 12 MHz and 27 MHz, the SCL
frequency ranges from 176 kHz to 422 kHz. If the self boot
EEPROM is not rated for operation above 400 kHz, use a master
clock that is no faster than 25.6 MHz.
If the CRC is incorrect or if an unrecognized instruction byte is
read during self boot, the boot process is immediately stopped
and restarted after a 250 ms delay (for a 12.288 MHz input clock).
When SigmaStudio is used, the CRC byte is generated auto-
matically when a configuration is downloaded to the EEPROM.
Delay
The delay instruction (0x02 instruction byte) delays by the
16-bit setting × 2048 clock cycles.
Table 25 shows the list of instructions that are possible during
an ADAU1777 self boot. The 0x01 and 0x05 instruction bytes
load the register, program, and parameter settings.
Boot Time
The time to self boot the ADAU1777 from an EEPROM can be
calculated using the following equation:
EEPROM Size
Boot Time = 64/MCLK Frequency × Total Bytes + Wait Time
The self boot circuit is compatible with an EEPROM that has a
2-byte address. For most EEPROM families, a 2-byte address is
used on devices that are 32 kB or larger. The EEPROM must be
set to Address 0x50. Examples of two compatible EEPROMs
include the Atmel® AT24C32D and STMicroelectronics M24C32-F.
The self boot operation starts after 16,568 clock cycles are seen on
PD
the XTALI/MCLKIN pin after
is set high. With a 12.288 MHz
clock, this number of cycles corresponds to approximately a
1.35 ms wait time from power-up. This delay ensures that the
crystal used for generating the master clock has ramped up to a
stable oscillation.
Table 24 lists the maximum necessary EEPROM size, assuming
that there is 100% utilization of the program and parameters
(both banks). There is inherently some overhead for instructions
to control the self boot procedure.
Table 25. EEPROM Self Boot Instructions
Instruction Instruction Byte
Byte ID
Description
Following Bytes
Table 24. Maximum EEPROM Size
0x00
0x01
End self boot
CRC
Word Size
(Bytes per
Word)
Total EEPROM
Space Require-
ment (Bytes)
ADAU1777
Memory Blocks
Write multibyte
length minus two
bytes, starting at
target address
Length (high byte), length
(low byte), address (high
byte), address (low byte),
data (0), data (1), …, data
(length − 3)
Delay (high byte),
delay (low byte)
Words
Program
2
4
4
1
32
64
Bank A Parameters
Bank B Parameters
Registers
160 (32 × 5) 640
160
65
640
65
2049
0x02
Delays by the 16-bit
setting × 2048 clock
cycles
Total Bytes
0x03
0x04
0x05
No operation
Wait for PLL lock
Write single byte to
target address
None
None
Address (high byte),
address (low byte), data
0x02
0x00
0x04
0x01
0x00
0x05
0x00
0x80
DELAY
DELAY
(HIGH BYTE)
DELAY
(LOW BYTE)
WRITE
LENGTH
(HIGH BYTE)
LENGTH
(LOW BYTE)
ADDRESS
(HIGH BYTE)
ADDRESS
(LOW BYTE)
DELAY LENGTH
LENGTH
PROGRAM RAM ADDRESS
0x1A
0x2B
0x3C
0x04
0x03
0x00
END
DATA
(0)
DATA
(1)
DATA
(LENGTH – 3)
PLL LOCK
NO OP
PROGRAM RAM DATA
Figure 66. Example Self Boot EEPROM Instructions
Rev. 0 | Page 39 of 108
ADAU1777
Data Sheet
MULTIPURPOSE PINS
The ADAU1777 has seven multipurpose (MPx) pins that can be
used for serial data input/output, clock outputs, and control in a
system without a microcontroller. Each pin can be individually
set to either its default or MPx setting. The functions include push-
button volume controls, enabling the compressors, parameter
bank switching, DSP bypass mode, and muting the outputs.
When the ADC and/or DAC volumes are controlled with the
push-buttons, the corresponding volume control registers no
longer allow control of the volume from the control port.
Therefore, writing to these volume control registers has no
effect on the codec volume level.
LIMITER COMPRESSION ENABLE
The function of each of these pins is set in Register 0x38 to
Register 0x3E. By default, each pin is configured as an input.
The limiter compression enable function allows a user to enable
limiter compression regardless of the signal level. Setting an
MPx pin low when this function is enabled causes the limiter to
compress the incoming signal by the minimum gain setting.
When the MPx pin is released, the limiter resumes normal
behavior.
Table 26. Multipurpose Pin Functions
Pin No. Default Pin Function
Secondary Pin Functions
A2
A3
BCLK
Multipurpose control inputs
MP1 acts as push-button ADC_SDATA0, PDM output,
PARAMETER BANK SWITCHING
volume up
multipurpose control inputs
An MPx pin can be used to switch the active parameter bank
between Bank A and Bank B. When one of these settings is
selected, Bank A is active when the MPx pin is high and Bank B
is active when the MPx pin is low. Set the BANK_SL bits in the
CORE_CONTROL register (Address 0x09) to the default value
of 0x00 before enabling MPx pin control over bank switching.
Simultaneous control of bank switching by both register setting
and MPx pin selection is not possible.
A4
MP6 acts as push-
button volume down
LRCLK
DAC_SDATA
DMIC2_3
DMIC0_1
ADC_SDATA1, CLKOUT,
multipurpose control inputs
Multipurpose control inputs
Multipurpose control inputs
Multipurpose control inputs
Multipurpose control inputs
B2
B3
B4
B5
PUSH-BUTTON VOLUME CONTROLS
The ZERO_STATE bit selects whether the data memory of the
codec is set to 0 during a bank switch. If the data is not set to 0
when a new set of filter coefficients is enabled via a bank switch,
there may be a pop in the audio as the old data is circulated in
the new filters.
The ADC and DAC volume controls can be controlled with two
push-buttons: one to increase volume and one to decrease volume.
The volume setting can either be changed with a click of the button
or can be ramped by holding either button but not both at the same
time. The volume settings change when the signal on the pin from
the button goes from low to high.
MUTE
The MPx pins can be put into a mode to mute the ADCs or DACs.
When in this mode, mute is enabled when an MPx pin is set low.
The full combination of possible mutes for the ADCs and DACs
using the MPx pins are set in Register 0x38 to Register 0x3E.
When in push-button mode, the initial volume level is set with
the PB_VOL_INIT_VAL bits. By default, MP1 acts as the push-
button volume up control and MP6 acts as the push-button
volume down control; however, any of the MPx pins can be set
to act as the push-button up and push-button down volume
controls.
Rev. 0 | Page 40 of 108
Data Sheet
ADAU1777
is pulled low. Pressing and holding the switch closed enables the
DSP bypass signal path as defined in the TALKTHRU register
(Address 0x2A). The DAC volume control setting is switched
from the default gain setting to the new TALKTHRU_GAINx
register setting (Address 0x2B and Address 0x2C). DSP bypass is
enabled only on ADC0 and ADC1. The DSP bypass signal path is
from the output of ADCx to the input of the DAC(s).
DSP BYPASS MODE
When DSP bypass mode is enabled, a direct path from the ADC
outputs to the DACs is set up to enable bypassing the core pro-
cessing to listen to environmental sounds. This mode is useful
for listening to someone speaking without having to remove the
noise canceling headphones. The DSP bypass path is enabled by
setting an MPx pin low. Figure 67 shows the DSP bypass path
disabled, and Figure 68 shows the DSP bypass path enabled by
pressing the push-button switch. The DSP bypass feature works
for both analog and digital microphone inputs.
When DSP bypass is enabled, the current DAC volume setting
is ramped down to −95.625 dB and the DSP bypass volume
setting is ramped up to avoid pops when switching paths.
DSP bypass is enabled when a switch connected to an MPx pin
that is set to DSP bypass mode is closed and the MPx pin signal
MPx
ADAU1777
10kΩ
DAC AND HP
AMPLIFIER
PGA AND ADC
AINx
HPOUTxP
HPOUTxN
CORE
PROCESSING
NORMAL
SETTING
Figure 67. DSP Bypass Path Disabled
MPx
10kΩ
ADAU1777
DAC AND HP
AMPLIFIER
PGA AND ADC
HPOUTxP
HPOUTxN
AINx
CORE
PROCESSING
TALKTHRU
SETTING
Figure 68. DSP Bypass Path Enabled
Rev. 0 | Page 41 of 108
ADAU1777
Data Sheet
SERIAL DATA INPUT/OUTPUT PORTS
it is recommended to use the high drive settings on the serial
port pins. The high drive strength effectively speeds up the
transition times of the waveforms, thereby improving the signal
integrity of the clock and data lines. These can be set in the
PAD_CONTROL4 register (Address 0x4C).
The serial data input and output ports of the ADAU1777 can be set
to accept or transmit data in a 2-channel format or in a 4-channel
or 8-channel TDM stream mode to interface to external ADCs,
DACs, DSPs, and systems on chip (SOCs). Data is processed in
twos complement, MSB first format. The left channel data field
always precedes the right channel data field in the 2-channel
streams. In 8-channel TDM mode, the data channels are output
sequentially, starting with the channel set by the ADC_SDATA0_ST
and ADC_SDATA1_ST bits. The serial modes and the position
of the data in the frame are set in the serial data port (SAI_0,
SAI_1) and serial output control registers (SOUT_SOURCE_x_y,
Address 0x13 to Address 0x16).
Table 27. Serial Input/Output Port Master/Slave Mode
Capabilities
Serial Data 2-Channel Modes
Sample
Rate
(I2S, Left Justified,
Right Justified)
4-Channel
TDM
8-Channel
TDM
48 kHz
96 kHz
192 kHz
Yes
Yes
Yes
Yes
Yes
No
Yes
No
No
The serial data clocks do not need to be synchronous with the
ADAU1777 master clock input, but the LRCLK and BCLK pins
must be synchronous to each other. The LRCLK and BCLK pins
both clock the serial input and output ports. The ADAU1777
can be set to be either the master or the slave in a system.
Because there is only one set of serial data clocks, the input and
output ports must always both be either master or slave.
Table 28 describes the proper serial port settings for standard audio
data formats. More information about the settings in Table 28 is
in the Serial Port Control 0 register and the Serial Port Control 1
register (Address 0x32 and Address 0x33) descriptions in Table 87
and Table 88, respectively.
The serial data control registers allow control of the clock polarity
and the data input modes. The valid data formats are I2S, left
justified, right justified (24- or 16-bit), PCM, and TDM. In all
modes except for the right justified modes, the serial port inputs
an arbitrary number of bits up to a limit of 24. Extra bits do not
cause an error, but they are truncated internally.
TRISTATING UNUSED CHANNELS
Unused outputs can be tristated so that multiple ICs can drive a
single TDM line. This function is available only when the serial
ports of the ADAU1777 are operating in TDM mode. Set inactive
channels in the SOUT_CONTROL0 register (Address 0x34).
The tristating of inactive channels is set in the SAI_1 register
(Address 0x33), which offers the option of tristating or driving
the inactive channel.
The serial port can operate with an arbitrary number of BCLK
transitions in each LRCLK frame. The LRCLK in TDM mode can
be input to the ADAU1777 either as a 50% duty cycle clock or as
a 1-bit wide pulse. Table 27 lists the modes in which the serial
input/output port can function. When using low IOVDD (1.8 V)
with a high BCLK rate (12.288 MHz), a sample rate of 192 kHz,
or a 8-channel TDM mode operating at a sample rate of 48 kHz,
In a 32-bit TDM frame with 24-bit data, the eight unused bits
are tristated. Inactive channels are also tristated for the full frame.
Table 28. Serial Port Data Format Settings
LRCLK Polarity
(LR_POL)
LRCLK Type
(LR_MODE)
BCLK Polarity
(BCLKEDGE)1
MSB Position
(SDATA_FMT)
Format
I2S (See Figure 69)
0
1
1
1
1
1
0
0
0
0
0
0
0
X
X
00
01
10 or 11
00
00
Left Justified (See Figure 70)
Right Justified (See Figure 71 and Figure 72)
TDM (See Figure 73 and Figure 74)
PCM/DSP Short Frame Sync (See Figure 75)
PCM/DSP Long Frame Sync (See Figure 76)
0 or 1
1
0
01
1 X means don’t care.
1
2
3
4
24
25
26
32
33
34
35
36
56
57
58
64
LRCLK
BCLK (64 × f
2
)
S
MSB
LSB
MSB
LSB
I S (24-BIT)
LEFT CHANNEL
RIGHT CHANNEL
Figure 69. I2S Mode, 16 Bits to 24 Bits per Channel
Rev. 0 | Page 42 of 108
Data Sheet
ADAU1777
LRCLK
1
2
3
23
24
25
32
33
34
35
55
56
57
64
BCLK (64 × f
)
S
LJ (24-BIT)
MSB
LSB
MSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 70. Left Justified (LJ) Mode, 16 Bits to 24 Bits per Channel
LRCLK
BCLK (64 × f
1
2
9
10
11
12
31
32
33
34
41
42
43
44
63
64
)
S
RJ (24-BIT)
MSB
LSB
MSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 71. Right Justified (RJ) Mode, 24 Bits per Channel
LRCLK
BCLK (64 × f
1
2
17
18
19
20
31
32
33
34
49
50
51
52
63
64
)
S
RJ (24-BIT)
MSB
LSB
MSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 72. Right Justified (RJ) Mode, 16 Bits per Channel
LRCLK
BCLK
256 BCLKs
32 BCLKs
SLOT 1
DATA
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
SLOT 8
LRCLK
BCLK
MSB
MSB – 1
MSB – 2
DATA
Figure 73. 8-Channel TDM Mode
LRCLK
BCLK
DATA
MSB TDM
MSB TDM
CH
0
CH
8
SLOT 0
SLOT 1
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
32
BCLKs
Figure 74. 8-Channel TDM Mode, Pulse LRCLK
Rev. 0 | Page 43 of 108
ADAU1777
Data Sheet
LRCLK
1
2
3
4
16
17
18
19
20
32
33
34
BCLK (64 × f
)
S
PCM (24-BIT)
MSB
LSB
MSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 75. PCM/DSP Mode, 16 Bits per Channel, Short Frame Sync
LRCLK
1
2
3
4
16
17
18
19
20
32
33
34
BCLK (64 × f
)
S
PCM (24-BIT)
MSB
LSB
MSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 76. PCM/DSP Mode, 16 Bits per Channel, Long Frame Sync
Rev. 0 | Page 44 of 108
Data Sheet
ADAU1777
APPLICATIONS INFORMATION
POWER SUPPLY BYPASS CAPACITORS
LAYOUT
Bypass each analog and digital power supply pin to its nearest
appropriate ground pin with a single 0.1 μF capacitor. The
connections to each side of the capacitor must be as short as
possible, and the trace must be routed on a single layer with no vias.
For maximum effectiveness, locate the capacitor equidistant from
the power and ground pins or slightly closer to the power pin if
equidistant placement is not possible. Make thermal connections
to the ground planes on the far side of the capacitor.
Pin D1 and Pin F2 are the AVDD supplies for the headphone
amplifiers. If the headphone amplifiers are enabled, the PCB trace
to these pins must be wider than traces to other pins to increase the
current carrying capacity. A wider trace must also be used for
the headphone output lines where possible.
GROUNDING
A ground plane must be used in the application layout. Place
components in an analog signal path away from digital signals
wherever possible.
Bypass each supply signal on the board with a single bulk
capacitor (10 μF to 47 μF).
PCB STACKUP
AVDD PIN
AGND PIN
The example PCB stackup in Figure 78 is a 4-layer design. Four
is the minimum layer count. The two inner layers are used as
power and ground planes. The outer layers are used as signal
layers and are flooded with the ground plane. It is
recommended to use several 0.1 ꢀF bypass capacitors to
decouple the power and ground plane for EMI concerns. Place
these capacitors around the edges of the ground plane.
CAPACITOR
TO GND
FROM AVDD
Figure 77. Recommended Example Power Supply Bypass Capacitor Layout
4-LAYER CONSTRUCTION DETAIL
SCALE: NONE
SILKSCREEN
SOLDER MASK
LAYER 1 TOP SIDE, 1.5 oz. Cu FINISHED
LAMINATE = 0.010 INCH THICK
LAYER 2 GROUND PLANE, 1.0 oz. Cu
0.062 ± 0.005 INCH
CORE PREPREG = 0.040 INCH THICK
LAYER 3 POWER PLANE, 1.0 oz. Cu
LAMINATE = 0.010 INCH THICK
LAYER 4 BOTTOM SIDE, 1.5 oz. Cu FINISHED
SOLDER MASK
SILKSCREEN
Figure 78. Example PCB Stackup Details
Rev. 0 | Page 45 of 108
ADAU1777
Data Sheet
LOW LATENCY REGISTER SETTINGS
The ADAU1777 utilizes the ADAU1772 architecture and incorporates additional register settings for reductions in latency, as shown in
Table 29 to Table 35.
Table 29. Core Control Register (Register 0x0009)
Bits
Bit Name
Settings Description
[4:3]
FAST_SLOW_RATE
These bits select the speed of the slow rate relative to the fast rate. This setting must not be
changed while the core is running. The CORE_RUN bit must be set to 0 for this setting to be
updated.
00
01
10
Slow rate = fast rate.
Slow rate = fast rate/4.
Slow rate = fast rate/8.
[2:1]
CORE_FS
These bits select the core sample rate. Note that the ADAU1777 supports an additional 768 kHz
sample rate for reduced latency. This setting must not be changed while the core is running. The
CORE_RUN bit must be set to 0 for this setting to be updated.
00
01
10
11
Reserved.
96 kHz.
192 kHz.
768 kHz.
Table 30. Sleep on Program Address Count Register (Register 0x000A)
Bits
Bit Name
Settings Description
[4:0]
SLEEP
The sleep on program address count register controls which registers are executed. Subtract 2
from the SLEEP bit setting to indicate the number of addresses that are affected. For example, if
SLEEP = 7, only instructions at Address 0x0000 to Address 0x0005 are executed. This setting must
not be changed while the core is running. The CORE_RUN bit must be set to 0 for this setting to be
updated.
00000
00001
00010
00011
11111
No sleep, all instructions are executed.
Reserved.
Sleep on 0.
Sleep on 1.
Sleep on 29.
Table 31. ADC0/ADC1 Control 0 Register (Register 0x001B)
Bits
Bit Name
Settings Description
5
ADC_0_1_SINC
This bit selects either a third-order or fourth-order sinc filter. This setting must not be changed
while the core is running. The CORE_RUN bit must be set to 0 for this setting to be updated.
0
1
Fourth-order sinc.
Third-order sinc.
[1:0]
ADC_0_1_FS
These bits set the ADC sample rate. The ADAU1777 supports the option of 768 kHz as well. Note
that the frequency selected must match the CORE_FS selected via Bits[2:1] of Register 0x0009.
00
01
10
11
96 kHz.
192 kHz.
768 kHz.
Reserved.
Rev. 0 | Page 46 of 108
Data Sheet
ADAU1777
Table 32. ADC2/ADC31 Control 0 Register (Register 0x001C)
Bits
Bit Name
Settings Description
5
ADC_2_3_SINC
This bit selects either a third-order or fourth-order sinc filter. This setting must not be changed
while the core is running. The CORE_RUN bit must be set to 0 for this setting to be updated.
0
1
Fourth-order sinc.
Third-order sinc.
[1:0]
ADC_2_3_FS
These bits set the ADC sample rate. The ADAU1777 supports the option of 768 kHz as well.
00
01
10
11
96 kHz.
192 kHz.
768 kHz.
Reserved.
Table 33. Fast Rate Control Register (Register 0x004E)
Bits
Bit Name
Settings Description
[2:0]
RATE_DIV
Bits[2:0] set the fast rate division factor. This factor is used to divide the internal master clock
(6.144 MHz) when CORE_FS = 11. This setting must not be changed while the core is running.
CORE_RUN must be set to 0 for this setting to be updated. The settings for RATE_DIV follow:
000
001
010
011
100
101
Divide by 8 (768 kHz).
Divide by 9 (683 kHz).
Divide by 10 (614 kHz).
Divide by 12 (512 kHz).
Divide by 14 (439 kHz).
Divide by 16 (384 kHz).
Table 34. DAC Interpolation Control Register (Register 0x004F)
Bits
Bit Name
Settings Description
These bits set the DAC_RATE value, which sets the sample rate for the DAC only.
Core fS.
[7:6]
DAC_RATE
00
01
10
11
Core fS/4.
Core fS/8.
Reserved.
[5:3]
DAC_INTP
These bits set the DAC_INTP value, which sets the interpolation mode for the DAC.
Both DAC0 and DAC1 set to compensated interpolation.
DAC0 set to zero-order hold (ZOH), DAC1 set to compensated interpolation.
DAC0 set to compensated interpolation, DAC1 set to ZOH.
Both DAC0 and DAC1 set to ZOH.
DAC0 set to linear interpolation, DAC1 set to compensated interpolation.
DAC0 set to compensated interpolation, DAC1 set to linear interpolation.
Both DAC0 and DAC1 set to linear interpolation.
000
001
010
011
100
101
110
Rev. 0 | Page 47 of 108
ADAU1777
Data Sheet
Table 35. Volume Control Bypass Register (Register 0x0054)
Bits
Bit Name
Settings Description
5
DAC1VOL_BY
DAC1 volume control bypass.
0
1
Volume control enabled.
Bypassed.
4
3
2
1
0
DAC0VOL_BY
ADC3VOL_BY
ADC2VOL_BY
ADC1VOL_BY
ADC0VOL_BY
DAC0 volume control bypass.
Volume control enabled.
Bypassed.
0
1
ADC3 volume control bypass.
Volume control enabled.
Bypassed.
0
1
ADC2 volume control bypass.
Volume control enabled.
Bypassed.
0
1
ADC1 volume control bypass.
Volume control enabled.
Bypassed.
0
1
ADC0 volume control bypass.
Volume control enabled.
Bypassed.
0
1
Rev. 0 | Page 48 of 108
Data Sheet
ADAU1777
REGISTER SUMMARY
Table 36. Register Summary
Reg.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
Name
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
RW
CLK_CONTROL
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL_CTRL3
PLL_CTRL4
PLL_CTRL5
CLKOUT_SEL
REGULATOR
PLL_EN
RESERVED
SPK_FLT_DIS
XTAL_DIS
CLKSRC
M_MSB
M_LSB
N_MSB
N_LSB
CC_CDIV
CC_MDIV
COREN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESERVED
R
X
PLL_TYPE
LOCK
RESERVED
RESERVED
RESERVED
CLKOUT_FREQ
REG_PD
REGV
CORE_CONTROL [7:0]
ZERO_
STATE
BANK_SL
FAST_SLOW_RATE
CORE_FS
CORE_RUN 0x04
0x0A
0x0B
SLEEP_INST
[7:0]
[7:0]
RESERVED
SLEEP
0x00
R/W
R/W
CORE_ENABLE
RESERVED
LIM_EN
DSP_CLK_
EN
0x03
0x0C
0x0D
0x0E
0x0F
DBREG0
DBREG1
DBREG2
[7:0]
[7:0]
[7:0]
DBVAL0
DBVAL1
DBVAL2
0x00
0x00
0x00
0x10
R
R
R
CORE_IN_MUX_ [7:0]
0_1
CORE_IN_MUX_SEL_1
CORE_IN_MUX_SEL_3
DAC_SOURCE1
CORE_IN_MUX_SEL_0
CORE_IN_MUX_SEL_2
DAC_SOURCE0
R/W
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
CORE_IN_MUX_ [7:0]
2_3
0x32
0x10
0x32
0x54
0x76
0x54
0x76
0x04
0x10
0x32
0x00
0x19
0x19
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DAC_SOURCE_
0_1
[7:0]
PDM_SOURCE_
0_1
[7:0]
PDM_SOURCE1
SOUT_SOURCE1
SOUT_SOURCE3
SOUT_SOURCE5
SOUT_SOURCE7
RESERVED
PDM_SOURCE0
SOUT_SOURCE_ [7:0]
0_1
SOUT_SOURCE0
SOUT_SOURCE2
SOUT_SOURCE4
SOUT_SOURCE6
SOUT_SOURCE_ [7:0]
2_3
SOUT_SOURCE_ [7:0]
4_5
SOUT_SOURCE_ [7:0]
6_7
ADC_SDATA_
CH
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
ADC_SDATA1_ST
ASRC_OUT_SOURCE0
ASRC_OUT_SOURCE2
ASRC_IN_CH ASRC_OUT_EN
RESERVED
ADC_SDATA0_ST
ASRCO_
SOURCE_0_1
ASRC_OUT_SOURCE1
ASRC_OUT_SOURCE3
RESERVED
ASRCO_
SOURCE_2_3
ASRC_MODE
ASRC_IN_
EN
ADC_
CONTROL0
RESERVED
RESERVED
RESERVED
RESERVED
ADC_0_1_
SINC
ADC1_MUTE ADC0_MUTE
ADC3_MUTE ADC2_MUTE
ADC_0_1_FS
ADC_2_3_FS
ADC_
CONTROL1
ADC_2_3_
SINC
RESERVED
DCM_0_1
DCM_2_3
ADC_
CONTROL2
HP_0_1_EN
DMIC_POL0
DMIC_POL1
DMIC_SW0
DMIC_SW1
ADC_1_EN
ADC_3_EN
ADC_0_EN 0x00
ADC_2_EN 0x00
ADC_
HP_2_3_EN
CONTROL3
0x1F
0x20
0x21
0x22
ADC0_VOLUME [7:0]
ADC1_VOLUME [7:0]
ADC2_VOLUME [7:0]
ADC3_VOLUME [7:0]
ADC_0_VOL
ADC_1_VOL
ADC_2_VOL
ADC_3_VOL
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
Rev. 0 | Page 49 of 108
ADAU1777
Data Sheet
Reg.
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x23
PGA_CONTROL_ [7:0]
0
PGA_EN0
PGA_
MUTE0
PGA_GAIN0
0x40
R/W
0x24
0x25
0x26
0x27
0x28
0x29
PGA_CONTROL_ [7:0]
1
PGA_EN1
PGA_EN2
PGA_EN3
PGA_
MUTE1
PGA_GAIN1
PGA_GAIN2
PGA_GAIN3
0x40
0x40
0x40
R/W
R/W
R/W
R/W
R/W
R/W
PGA_CONTROL_ [7:0]
2
PGA_
MUTE2
PGA_CONTROL_ [7:0]
3
PGA_
MUTE3
PGA_STEP_
CONTROL
[7:0]
[7:0]
[7:0]
RESERVED
SLEW_RATE
SLEW_PD3
SLEW_PD2
SLEW_PD1
SLEW_PD0 0x00
PGA_10DB_
BOOST
RESERVED
PGA_3_
BOOST
PGA_2_BOOST
PGA_POP_DIS2
PGA_1_BOOST
PGA_POP_DIS1
PGA_0_
BOOST
0x00
POP_SUPPRESS
RESERVED
HP_POP_
HP_POP_
PGA_POP_
DIS3
PGA_POP_ 0x3F
DIS0
DIS1
DIS0
0x2A
0x2B
TALKTHRU
[7:0]
[7:0]
RESERVED
TALKTHRU_PATH
0x00
0x00
R/W
R/W
TALKTHRU_
GAIN0
TALKTHRU_GAIN0_VAL
TALKTHRU_GAIN1_VAL
0x2C
0x2D
0x2E
TALKTHRU_
GAIN1
[7:0]
[7:0]
[7:0]
0x00
0x00
0x18
R/W
R/W
R/W
MIC_BIAS
RESERVED
RESERVED
MIC_EN1
DAC_POL
MIC_EN0
RESERVED
RESERVED
RESERVED
MIC_GAIN1
DAC1_EN
MIC_
GAIN0
DAC_
DAC1_MUTE DAC0_MUTE
DAC0_EN
CONTROL1
0x2F
0x30
0x31
DAC0_VOLUME [7:0]
DAC1_VOLUME [7:0]
DAC_0_VOL
DAC_1_VOL
0x00
0x00
0x0F
R/W
R/W
R/W
OP_STAGE_
MUTES
[7:0]
RESERVED
HP_MUTE_R
HP_MUTE_L
0x32
0x33
SAI_0
SAI_1
[7:0]
[7:0]
SDATA_FMT
SAI
SER_PORT_FS
0x00
0x00
R/W
R/W
TDM_TS
BCLK_
TDMC
LR_MODE
TDM5_DIS
LR_POL
SAI_MSB
BCLKRATE
BCLKEDGE
SAI_MS
0x34
SOUT_
CONTROL0
[7:0]
TDM7_DIS
TDM6_DIS
TDM4_DIS
PDM_CTRL
TDM3_DIS
TDM2_DIS
TDM1_DIS
TDM0_DIS 0x00
R/W
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
PDM_OUT
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
PDM_CH
PDM_EN
0x00
0x00
0x00
0x10
0x00
0x00
0x00
0x00
0x11
0x00
0x87
0x05
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDM_PATTERN
MODE_MP0
MODE_MP1
MODE_MP2
MODE_MP3
MODE_MP4
MODE_MP5
MODE_MP6
PB_VOL_SET
PB_VOL_CONV
PATTERN
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MODE_MP0_VAL
MODE_MP1_VAL
MODE_MP2_VAL
MODE_MP3_VAL
MODE_MP4_VAL
MODE_MP5_VAL
MODE_MP6_VAL
PB_VOL_INIT_VAL
RESERVED
HOLD
GAINSTEP
RAMPSPEED
PB_VOL_CONV_VAL
DEBOUNCE
DEBOUNCE_
MODE
0x43
0x44
0x45
0x46
0x47
0x48
0x49
OP_STAGE_
CTRL
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
DEC_3_EN DEC_2_EN
HP_EN_R
HP_EN_L
HP_PDN_R
SINC_2_EN
MOD_0_EN
ADC_IBIAS23
MIC_IBIAS
ADC_SDATA1_
HP_PDN_L
0x0F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DECIM_PWR_
MODES
DEC_1_EN
DEC_0_EN
SINC_3_EN
MOD_1_EN
SINC_1_EN
INT_1_EN
SINC_0_EN 0x00
INTERP_PWR_
MODES
RESERVED
INT_0_EN
ADC_IBIAS01
DAC_IBIAS
0x00
0x00
0x00
0x7F
BIAS_
CONTROL0
HP_IBIAS
AFE_IBIAS01
AFE_IBIAS23
BIAS_
CONTROL1
RESERVED
RESERVED
CBIAS_DIS
PAD_
CONTROL0
DMIC2_3_
PU
DMIC0_1_PU LRCLK_PU
BCLK_PU
SCL_PU
ADC_SDATA0_
DAC_
PU
PU
SDATA_PU
PAD_
CONTROL1
RESERVED
SELFBOOT_
PU
SDA_PU
ADDR1_PU
ADDR0_PU 0x1F
Rev. 0 | Page 50 of 108
Data Sheet
ADAU1777
Reg.
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x4A
PAD_
CONTROL2
[7:0]
RESERVED
DMIC2_3_
PD
DMIC0_1_PD LRCLK_PD
BCLK_PD
ADC_SDATA1_
PD
ADC_SDATA0_
PD
DAC_
SDATA_PD
0x00
R/W
0x4B
0x4C
0x4D
PAD_
CONTROL3
[7:0]
[7:0]
[7:0]
RESERVED
RESERVED
RESERVED
SELFBOOT_
PD
SCL_PD
SDA_PD
ADDR1_PD
ADDR0_
PD
0x00
0x00
0x00
R/W
R/W
R/W
PAD_
CONTROL4
RESERVED
RESERVED
LRCLK_DRV
BCLK_DRV
SCL_DRV
ADC_SDATA1_
DRV
ADC_SDATA0_
DRV
RESERVED
PAD_
RESERVED
SDA_DRV
RESERVED
RESERVED
CONTROL5
0x4E
0x4F
FAST_RATE
[7:0]
[7:0]
RESERVED
RATE_DIV
RESERVED
0x00
0x00
R/W
R/W
DAC_
CONTROL0
DAC_RATE
RESERVED
DAC_INTP
0x54
VOL_BYPASS
[7:0]
DAC1VOL_BY DAC0VOL_
BY
ADC3VOL_BY ADC2VOL_BY
ADC1VOL_BY
ADC0VOL_ 0x00
BY
R/W
Rev. 0 | Page 51 of 108
ADAU1777
Data Sheet
REGISTER DETAILS
CLOCK CONTROL REGISTER
Address: 0x00, Reset: 0x00, Name: CLK_CONTROL
This register enables the internal clocks.
Table 37. Bit Descriptions for CLK_CONTROL
Bits Bit Name
Settings Description
Reset Access
7
PLL_EN
Enable PLL. When this bit is set to 0, the PLL is powered down and the PLL output
0x0
R/W
clock is disabled. Do not enable the PLL until after all the PLL control settings
(Register PLL_CTRL0 to Register PLL_CTRL5) are set. The PLL clock output is active
when both PLL_EN = 1 and COREN = 1.
0
1
PLL disabled.
PLL enabled.
Reserved.
6
5
RESERVED
0x0
0x0
R/W
R/W
SPK_FLT_DIS
Disable I2C spike filter. By default, the SDA and SCL inputs have a 50 ns spike
suppression filter. When the control interface is in SPI mode, this filter is disabled
regardless of this setting.
0
1
I2C spike filter enabled.
I2C spike filter disabled.
Disable crystal oscillator.
Crystal oscillator enabled.
Crystal oscillator disabled.
Main clock source.
4
3
XTAL_DIS
CLKSRC
0x0
0x0
R/W
R/W
0
1
0
1
External pin drives main clock.
PLL drives main clock. This bit must only be set after LOCK in Register PLL_CTRL5 has
gone high.
2
CC_CDIV
SCLK divider control. The core clock (SCLK) is used only by the core. It must run at
12.288 MHz.
0x0
R/W
0
1
Div 2: divide PLL/external clock by 2.
Div 1: divide PLL/external clock by 1.
Rev. 0 | Page 52 of 108
Data Sheet
ADAU1777
Bits Bit Name
Settings Description
MCLK divider control. The internal master clock (MCLK) of the IC is used by all digital
Reset Access
1
CC_MDIV
0x0
R/W
logic except the core. It must run at 12.288 MHz.
0
1
Div 2: divide PLL/external clock by 2.
Div 1: divide PLL/external clock by 1.
0
COREN
Main clock enable. When COREN = 0, it is only possible to write to this register and the 0x0
PLL control registers (PLL_CTRL0 to PLL_CTRL5). This control also enables the PLL
clock. If using the PLL, do not set COREN = 1 until LOCK in Register PLL_CTRL5 is 1.
Note that, after COREN is enabled, writing to the parameters is disabled until setting
DSP_CLK_EN in the CORE_ENABLE register.
R/W
0
1
Main clock disabled.
Main clock enabled.
PLL DENOMINATOR MSB REGISTER
Address: 0x01, Reset: 0x00, Name: PLL_CTRL0
Only write to this register when PLL_EN = 0 in Register CLK_CONTROL.
Table 38. Bit Descriptions for PLL_CTRL0
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
M_MSB
PLL denominator MSB.
0x0
R/W
PLL DENOMINATOR LSB REGISTER
Address: 0x02, Reset: 0x00, Name: PLL_CTRL1
Only write to this register when PLL_EN = 0 in Register CLK_CONTROL.
Table 39. Bit Descriptions for PLL_CTRL1
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
M_LSB
PLL denominator LSB.
0x0
R/W
PLL NUMERATOR MSB REGISTER
Address: 0x03, Reset: 0x00, Name: PLL_CTRL2
Only write to this register when PLL_EN = 0 in Register CLK_CONTROL.
Table 40. Bit Descriptions for PLL_CTRL2
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
N_MSB
PLL numerator MSB.
0x0
R/W
Rev. 0 | Page 53 of 108
ADAU1777
Data Sheet
PLL NUMERATOR LSB REGISTER
Address: 0x04, Reset: 0x00, Name: PLL_CTRL3
Only write to this register when PLL_EN = 0 in Register CLK_CONTROL.
Table 41. Bit Descriptions for PLL_CTRL3
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
N_LSB
PLL numerator LSB.
0x0
R/W
PLL INTEGER SETTING REGISTER
Address: 0x05, Reset: 0x00, Name: PLL_CTRL4
Only write to this register when PLL_EN = 0 in Register CLK_CONTROL.
Table 42. Bit Descriptions for PLL_CTRL4
Bits
Bit Name
RESERVED
R
Settings
Description
Reset
0x0
Access
R/W
7
Reserved.
[6:3]
PLL integer setting.
0x0
R/W
0000 Reserved.
0001 Reserved.
0010 2.
0011 3.
0100 4.
0101 5.
0110 6.
0111 7.
1000 8.
[2:1]
X
PLL input clock divide ratio.
0x0
0x0
R/W
R/W
00 Pin clock input/1.
01 Pin clock input/2.
10 Pin clock input/3.
11 Pin clock input/4.
PLL type.
0
PLL_TYPE
0
1
Integer.
Fractional.
Rev. 0 | Page 54 of 108
Data Sheet
ADAU1777
PLL LOCK FLAG REGISTER
Address: 0x06, Reset: 0x00, Name: PLL_CTRL5
Table 43. Bit Descriptions for PLL_CTRL5
Bits
[7:1]
0
Bit Name
RESERVED
LOCK
Settings
Description
Reset
Access
R/W
R
Reserved.
0x0
0x0
Flag to indicate if the PLL is locked. This bit is read only.
0
1
PLL unlocked.
PLL locked.
CLKOUT SETTING SELECTION REGISTER
Address: 0x07, Reset: 0x00, Name: CLKOUT_SEL
When the ADC_SDATA1/CLKOUT/MP6 pin is set to clock output mode, the frequency of the output clock is set in this register.
CLKOUT can be used to provide a master clock to another IC, the clock for digital microphones, or as the clock for the PDM output stream.
The 12 MHz/24 MHz setting is used when clocking another IC, 3 MHz/6 MHz is used for PDMOUT, and 1.5 MHz/3 MHz is used when
clocking digital microphones. The CLKOUT frequency is derived from the master clock frequency, which is assumed to (and always must) be
12.288 MHz. The 12.288 MHz and 24.576 MHz output modes are not functional if PDM is enabled (Register PDM_OUT, Bits[1:0]).
Table 44. Bit Descriptions for CLKOUT_SEL
Bits
[7:3]
[2:0]
Bit Name
Settings
Description
Reset
0x0
Access
R/W
RESERVED
Reserved.
CLKOUT_FREQ
CLKOUT pin frequency.
0x0
R/W
000 Master clock × 2 (24.576 MHz).
001 Master clock (12.288 MHz).
010 Master clock/2 (6.144 MHz).
011 Master clock/4 (3.072 MHz).
100 Master clock/8 (1.536 MHz).
111 Clock output off = 0.
Rev. 0 | Page 55 of 108
ADAU1777
Data Sheet
REGULATOR CONTROL REGISTER
Address: 0x08, Reset: 0x00, Name: REGULATOR
Table 45. Bit Descriptions for REGULATOR
Bits
[7:3]
2
Bit Name
RESERVED
REG_PD
Settings
Description
Reset
Access
R/W
Reserved.
0x0
0x0
Powers down LDO regulator.
Regulator active.
R/W
0
1
Regulator powered down.
Set regulator output voltage.
[1:0]
REGV
0x0
R/W
00 1.2 V.
01 1.1 V.
10 Reserved.
11 Reserved.
CORE CONTROL REGISTER
Address: 0x09, Reset: 0x04, Name: CORE_CONTROL
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
[7] ZERO_STATE (R/W)
Zeroes the state of the data memory
during bank switching
[0] CORE_RUN (R/W)
Run bit for the core
0: Core off.
0: Do not zero state during bank switch.
1: Zero state during back switch.
1: Core on.
[2:1] CORE_FS (R/W)
This bit sets the core sample rate
00: Reserved.
01: 96 kHz.
10: 192 kHz.
[6:5] BANK_SL (R/W)
Selects active filter bank
00: Bank A active.
01: Bank B active.
10: Reserved.
11: 768 kHz.
11: Reserved.
[4:3] FAST_SLOW_RATE (R/W)
Selects the speed of the slow rate
relative to the fast rate
00: slow rate = fast rate.
01: slow rate = fast rate/4.
10: slow rate = fast rate/8.
Table 46. Bit Descriptions for CORE_CONTROL
Bits Bit Name Settings Description
ZERO_STATE
Reset Access
7
Zeroes the state of the data memory during bank switching. When switching
active parameter banks between two settings, zeroing the state of the bank
prevents the new filter settings from being active on old data that is recirculating in
the filters. Zeroing the state may prevent filter instability or unwanted noises
upon bank switching.
0x0
R/W
0
1
Do not zero state during bank switch.
Zero state during back switch.
Rev. 0 | Page 56 of 108
Data Sheet
ADAU1777
Bits Bit Name
Settings Description
Selects active filter bank.
Reset Access
[6:5] BANK_SL
0x0
R/W
00 Bank A active.
01 Bank B active.
10 Reserved.
11 Reserved.
[4:3] FAST_SLOW_RATE
Selects the speed of the slow rate relative to the fast rate. Do not change this
setting while the core is running. CORE_RUN must be set to 0 for this setting to
be updated.
0x0
R/W
00 Slow rate = fast rate.
01 Slow rate = fast rate/4.
10 Slow rate = fast rate/8.
[2:1] CORE_FS
This bit sets the core sample rate. Do not change this setting while the core is
running. CORE_RUN must be set to 0 for this setting to be updated.
0x2
R/W
00 Reserved.
01 96 kHz.
10 192 kHz.
11 768 kHz. When this mode is set, the fast rate of the core is set in Bits RATE_DIV in
the fast rate control register.
0
CORE_RUN
Run bit for the core. Enable this bit only when the program and parameters are
loaded and the sample rate settings are set. CORE_RUN starts and stops the
core at the beginning of the program.
0x0
R/W
0
1
Core off.
Core on.
SLEEP ON PROGRAM ADDRESS COUNT REGISTER
Address: 0x0A, Reset: 0x00, Name: SLEEP_INST
The SLEEP bits control which registers are sleeping. For example, if SLEEP = 7, only instructions at Address 0x00 to Address 0x05 are
executed. SLEEP = 0 disables sleeping.
Rev. 0 | Page 57 of 108
ADAU1777
Data Sheet
Table 47. Bit Descriptions for SLEEP_INST
Bits Bit Name
[7:5] RESERVED
[4:0] SLEEP
Settings Description
Reset Access
Reserved.
0x0
0x0
R/W
R/W
Sleep at Address SLEEP − 2. These bits control which registers are sleeping. Subtracting
2 from the SLEEP setting indicates the number of addresses that are affected. For
example, if SLEEP = 7, only instructions at Address 0x00 to Address 0x05 are executed.
Do not change this setting while the core is running. CORE_RUN must be set to 0 for
this setting to be updated.
00000 No sleep, all instructions are executed.
00001 Reserved.
00010 Sleep on 0 (0x00).
00011 Sleep on 1 (0x01).
00100 Sleep on 2 (0x02).
00101 Sleep on 3 (0x03).
00110 Sleep on 4 (0x04).
00111 Sleep on 5 (0x05).
01000 Sleep on 6 (0x06).
01001 Sleep on 7 (0x07).
01010 Sleep on 8 (0x08).
01011 Sleep on 9 (0x09).
01100 Sleep on 10 (0x0A).
01101 Sleep on 11 (0x0B).
01110 Sleep on 12 (0x0C).
01111 Sleep on 13 (0x0D).
10000 Sleep on 14 (0x0E).
10001 Sleep on 15 (0x0F).
10010 Sleep on 16 (0x10).
10011 Sleep on 17 (0x11).
10100 Sleep on 18 (0x12).
10101 Sleep on 19 (0x13).
10110 Sleep on 20 (0x14).
10111 Sleep on 21 (0x15).
11000 Sleep on 22 (0x16).
11001 Sleep on 23 (0x17).
11010 Sleep on 24 (0x18).
11011 Sleep on 25 (0x19).
11100 Sleep on 26 (0x1A).
11101 Sleep on 27 (0x1B).
11110 Sleep on 28 (0x1C).
11111 Sleep on 29 (0x1D).
Rev. 0 | Page 58 of 108
Data Sheet
ADAU1777
FILTER ENGINE AND LIMITER CONTROL REGISTER
Address: 0x0B, Reset: 0x03, Name: CORE_ENABLE
Disabling the limiter only disables the attack operation. The decay operation is always active; therefore, a limiter can be safely disabled
while the decay operation performs gain adjustments.
Table 48. Bit Descriptions for CORE_ENABLE
Bits Bit Name
Settings Description
Reset Access
[7:2] RESERVED
Reserved.
0x0
R/W
R/W
1
LIM_EN
Limiter enable. When the limiter function is disabled, a fixed maximum gain setting is 0x1
applied to instructions using the limiters.
0
1
Disabled.
Enabled.
0
DSP_CLK_EN
Enable the clock to the core. This bit directly controls the clock to the core. Set this bit 0x1
to 0 when the chip is used in a codec only configuration, in which the core is not
used. Writing to any of the biquad coefficient registers (Parameter Memory Address
0x0E0 to Parameter Memory Address 0x2BF) is blocked until this bit is 1. Do not use
this bit to start or stop the core while it is running, because it immediately starts or
stops the core clock and does not allow the program to finish. Instead, use
CORE_RUN in the CORE_CONTROL register to start or stop the core.
R/W
0
1
Core clock disabled.
Core clock enabled.
DB VALUE REGISTER 0 READ
Address: 0x0C, Reset: 0x00, Name: DBREG0
The core can write data to this register, and the data is automatically converted to a level in dB. The most common use for this register is to determine
the rms value of a signal by taking the absolute value, and then performing low-pass filtering and moving the result to the DBREG0 register.
Table 49. Bit Descriptions for DBREG0
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DBVAL0
DB Value Register 0 read.
0x0
R
00000000 −96 dB.
00010000 −90 dB.
00100000 −84 dB.
00110000 −78 dB.
11100000 −12 dB.
11110000 −6 dB.
11111111 −0.375 dB.
Rev. 0 | Page 59 of 108
ADAU1777
Data Sheet
DB VALUE REGISTER 1 READ
Address: 0x0D, Reset: 0x00, Name: DBREG1
The core can write data to this register, and the data is automatically converted to a level in dB. The most common use for this register is to deter-
mine the rms value of a signal by taking the absolute value, and then performing low-pass filtering and moving the result to the DBREG1 register.
Table 50. Bit Descriptions for DBREG1
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DBVAL1
DB Value Register 1 read.
0x0
R
00000000 −96 dB.
00010000 −90 dB.
00100000 −84 dB.
00110000 −78 dB.
11100000 −12 dB.
11110000 −6 dB.
11111111 −0.375 dB.
DB VALUE REGISTER 2 READ
Address: 0x0E, Reset: 0x00, Name: DBREG2
The core can write data to this register, and the data is automatically converted to a level in dB. The most common use for this register is to deter-
mine the rms value of a signal by taking the absolute value, and then performing low-pass filtering and moving the result to the DBREG2 register.
Table 51. Bit Descriptions for DBREG2
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DBVAL2
DB Value Register 2 read.
0x0
R
00000000 −96 dB.
00010000 −90 dB.
00100000 −84 dB.
00110000 −78 dB.
11100000 −12 dB.
11110000 −6 dB.
11111111 −0.375 dB.
Rev. 0 | Page 60 of 108
Data Sheet
ADAU1777
CORE CHANNEL 0/CORE CHANNEL 1 INPUT SELECT REGISTER
Address: 0x0F, Reset: 0x10, Name: CORE_IN_MUX_0_1
Table 52. Bit Descriptions for CORE_IN_MUX_0_1
Bits
Bit Name
Settings Description
Reset
0x1
Access
[7:4] CORE_IN_MUX_SEL_1
Core Input Channel 1 source.
R/W
0000 AIN0/DMIC0.
0001 AIN1/DMIC1.
0010 AIN2/DMIC2.
0011 AIN3/DMIC3.
0100 Reserved.
0101 Reserved.
0110 Reserved.
0111 Reserved.
1000 Reserved.
1001 Reserved.
1010 Reserved.
1011 Reserved.
1100 Input ASRC Channel 0.
1101 Input ASRC Channel 1.
Core Input Channel 0 source.
0000 AIN0/DMIC0.
0001 AIN1/DMIC1.
0010 AIN2/DMIC2.
0011 AIN3/DMIC3.
0100 Reserved.
[3:0] CORE_IN_MUX_SEL_0
0x0
R/W
0101 Reserved.
0110 Reserved.
0111 Reserved.
1000 Reserved.
1001 Reserved.
1010 Reserved.
1011 Reserved.
1100 Input ASRC Channel 0.
1101 Input ASRC Channel 1.
Rev. 0 | Page 61 of 108
ADAU1777
Data Sheet
CORE CHANNEL 2/CORE CHANNEL 3 INPUT SELECT REGISTER
Address: 0x10, Reset: 0x32, Name: CORE_IN_MUX_2_3
Table 53. Bit Descriptions for CORE_IN_MUX_2_3
Bits
Bit Name
Settings Description
Reset
Access
[7:4] CORE_IN_MUX_SEL_3
Core Input Channel 3 source.
0x3
R/W
0000 AIN0/DMIC0.
0001 AIN1/DMIC1.
0010 AIN2/DMIC2.
0011 AIN3/DMIC3.
0100 Reserved.
0101 Reserved.
0110 Reserved.
0111 Reserved.
1000 Reserved.
1001 Reserved.
1010 Reserved.
1011 Reserved.
1100 Input ASRC Channel 0.
1101 Input ASRC Channel 1.
Core Input Channel 2 source.
0000 AIN0/DMIC0.
0001 AIN1/DMIC1.
0010 AIN2/DMIC2.
0011 AIN3/DMIC3.
0100 Reserved.
[3:0] CORE_IN_MUX_SEL_2
0x2
R/W
0101 Reserved.
0110 Reserved.
0111 Reserved.
1000 Reserved.
1001 Reserved.
1010 Reserved.
1011 Reserved.
1100 Input ASRC Channel 0.
1101 Input ASRC Channel 1.
Rev. 0 | Page 62 of 108
Data Sheet
ADAU1777
DAC INPUT SELECT REGISTER
Address: 0x11, Reset: 0x10, Name: DAC_SOURCE_0_1
Table 54. Bit Descriptions for DAC_SOURCE_0_1
Bits Bit Name
Settings Description
Reset Access
[7:4] DAC_SOURCE1
DAC1 input source. Do not change this setting while the core is running.
0x1
R/W
CORE_RUN must be set to 0 for this setting to be updated.
0000 Core Output 0.
0001 Core Output 1.
0010 Core Output 2.
0011 Core Output 3.
0100 Reserved.
0101 Reserved.
0110 Reserved.
0111 Reserved.
1000 Reserved.
1001 Reserved.
1010 Reserved.
1011 Reserved.
1100 Input ASRC Channel 0.
1101 Input ASRC Channel 1.
[3:0] DAC_SOURCE0
DAC0 input source. Do not change this setting while the core is running.
CORE_RUN must be set to 0 for this setting to be updated.
0x0
R/W
0000 Core Output 0.
0001 Core Output 1.
0010 Core Output 2.
0011 Core Output 3.
0100 Reserved.
0101 Reserved.
0110 Reserved.
0111 Reserved.
1000 Reserved.
1001 Reserved.
1010 Reserved.
1011 Reserved.
1100 Input ASRC Channel 0.
1101 Input ASRC Channel 1.
Rev. 0 | Page 63 of 108
ADAU1777
Data Sheet
PDM MODULATOR INPUT SELECT REGISTER
Address: 0x12, Reset: 0x32, Name: PDM_SOURCE_0_1
Table 55. Bit Descriptions for PDM_SOURCE_0_1
Bits
Bit Name
Settings
Description
Reset
0x3
Access
[7:4]
PDM_SOURCE1
PDM Modulator Channel 1 input source.
R/W
0000 Core Output 0.
0001 Core Output 1.
0010 Core Output 2.
0011 Core Output 3.
0100 Reserved.
0101 Reserved.
0110 Reserved.
0111 Reserved.
1000 Reserved.
1001 Reserved.
1010 Reserved.
1011 Reserved.
1100 Input ASRC Channel 0.
1101 Input ASRC Channel 1.
[3:0]
PDM_SOURCE0
PDM Modulator Channel 0 input source.
0x2
R/W
0000 Core Output 0.
0001 Core Output 1.
0010 Core Output 2.
0011 Core Output 3.
0100 Reserved.
0101 Reserved.
0110 Reserved.
0111 Reserved.
1000 Reserved.
1001 Reserved.
1010 Reserved.
1011 Reserved.
1100 Input ASRC Channel 0.
1101 Input ASRC Channel 1.
Rev. 0 | Page 64 of 108
Data Sheet
ADAU1777
SERIAL DATA OUTPUT 0/SERIAL DATA OUTPUT 1 INPUT SELECT REGISTER
Address: 0x13, Reset: 0x54, Name: SOUT_SOURCE_0_1
Table 56. Bit Descriptions for SOUT_SOURCE_0_1
Bits
Bit Name
Settings
Description
Reset
0x5
Access
[7:4]
SOUT_SOURCE1
Serial Data Output Channel 1 source select.
R/W
0000 Reserved.
0001 Reserved.
0010 Reserved.
0011 Reserved.
0100 Output ASRC Channel 0.
0101 Output ASRC Channel 1.
0110 Output ASRC Channel 2.
0111 Output ASRC Channel 3.
1000 Serial Input 0.
1001 Serial Input 1.
1010 Serial Input 2.
1011 Serial Input 3.
1100 Serial Input 4.
1101 Serial Input 5.
1110 Serial Input 6.
1111 Serial Input 7.
[3:0]
SOUT_SOURCE0
Serial Data Output Channel 0 source select.
0x4
R/W
0000 Reserved.
0001 Reserved.
0010 Reserved.
0011 Reserved.
0100 Output ASRC Channel 0.
0101 Output ASRC Channel 1.
0110 Output ASRC Channel 2.
0111 Output ASRC Channel 3.
1000 Serial Input 0.
1001 Serial Input 1.
1010 Serial Input 2.
1011 Serial Input 3.
1100 Serial Input 4.
1101 Serial Input 5.
1110 Serial Input 6.
1111 Serial Input 7.
Rev. 0 | Page 65 of 108
ADAU1777
Data Sheet
SERIAL DATA OUTPUT 2/SERIAL DATA OUTPUT 3 INPUT SELECT REGISTER
Address: 0x14, Reset: 0x76, Name: SOUT_SOURCE_2_3
Table 57. Bit Descriptions for SOUT_SOURCE_2_3
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
SOUT_SOURCE3
Serial Data Output Channel 3 source select.
0x7
R/W
0000 Reserved.
0001 Reserved.
0010 Reserved.
0011 Reserved.
0100 Output ASRC Channel 0.
0101 Output ASRC Channel 1.
0110 Output ASRC Channel 2.
0111 Output ASRC Channel 3.
1000 Serial Input 0.
1001 Serial Input 1.
1010 Serial Input 2.
1011 Serial Input 3.
1100 Serial Input 4.
1101 Serial Input 5.
1110 Serial Input 6.
1111 Serial Input 7.
[3:0]
SOUT_SOURCE2
Serial Data Output Channel 2 source select.
0000 Reserved.
0x6
R/W
0001 Reserved.
0010 Reserved.
0011 Reserved.
0100 Output ASRC Channel 0.
0101 Output ASRC Channel 1.
0110 Output ASRC Channel 2.
0111 Output ASRC Channel 3.
1000 Serial Input 0.
1001 Serial Input 1.
1010 Serial Input 2.
1011 Serial Input 3.
1100 Serial Input 4.
1101 Serial Input 5.
1110 Serial Input 6.
1111 Serial Input 7.
Rev. 0 | Page 66 of 108
Data Sheet
ADAU1777
SERIAL DATA OUTPUT 4/SERIAL DATA OUTPUT 5 INPUT SELECT REGISTER
Address: 0x15, Reset: 0x54, Name: SOUT_SOURCE_4_5
Table 58. Bit Descriptions for SOUT_SOURCE_4_5
Bits
Bit Name
Settings
Description
Reset
0x5
Access
[7:4]
SOUT_SOURCE5
Serial Data Output Channel 5 source select.
R/W
0000 Reserved.
0001 Reserved.
0010 Reserved.
0011 Reserved.
0100 Output ASRC Channel 0.
0101 Output ASRC Channel 1.
0110 Output ASRC Channel 2.
0111 Output ASRC Channel 3.
1000 Serial Input 0.
1001 Serial Input 1.
1010 Serial Input 2.
1011 Serial Input 3.
1100 Serial Input 4.
1101 Serial Input 5.
1110 Serial Input 6.
1111 Serial Input 7.
[3:0]
SOUT_SOURCE4
Serial Data Output Channel 4 source select.
0000 Reserved.
0x4
R/W
0001 Reserved.
0010 Reserved.
0011 Reserved.
0100 Output ASRC Channel 0.
0101 Output ASRC Channel 1.
0110 Output ASRC Channel 2.
0111 Output ASRC Channel 3.
1000 Serial Input 0.
1001 Serial Input 1.
1010 Serial Input 2.
1011 Serial Input 3.
1100 Serial Input 4.
1101 Serial Input 5.
1110 Serial Input 6.
1111 Serial Input 7.
Rev. 0 | Page 67 of 108
ADAU1777
Data Sheet
SERIAL DATA OUTPUT 6/SERIAL DATA OUTPUT 7 INPUT SELECT REGISTER
Address: 0x16, Reset: 0x76, Name: SOUT_SOURCE_6_7
Table 59. Bit Descriptions for SOUT_SOURCE_6_7
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
SOUT_SOURCE7
Serial Data Output Channel 7 source select.
0x7
R/W
0000 Reserved.
0001 Reserved.
0010 Reserved.
0011 Reserved.
0100 Output ASRC Channel 0.
0101 Output ASRC Channel 1.
0110 Output ASRC Channel 2.
0111 Output ASRC Channel 3.
1000 Serial Input 0.
1001 Serial Input 1.
1010 Serial Input 2.
1011 Serial Input 3.
1100 Serial Input 4.
1101 Serial Input 5.
1110 Serial Input 6.
1111 Serial Input 7.
[3:0]
SOUT_SOURCE6
Serial Data Output Channel 6 source select.
0000 Reserved.
0x6
R/W
0001 Reserved.
0010 Reserved.
0011 Reserved.
0100 Output ASRC Channel 0.
0101 Output ASRC Channel 1.
0110 Output ASRC Channel 2.
0111 Output ASRC Channel 3.
1000 Serial Input 0.
1001 Serial Input 1.
1010 Serial Input 2.
1011 Serial Input 3.
1100 Serial Input 4.
1101 Serial Input 5.
1110 Serial Input 6.
1111 Serial Input 7.
Rev. 0 | Page 68 of 108
Data Sheet
ADAU1777
ADC_SDATA0/ADC_SDATA1 CHANNEL SELECT REGISTER
Address: 0x17, Reset: 0x04, Name: ADC_SDATA_CH
Table 60. Bit Descriptions for ADC_SDATA_CH
Bits Bit Name
Settings Description
Reset Access
[7:4] RESERVED
Reserved.
0x0
0x1
R/W
R/W
[3:2] ADC_SDATA1_ST
SDATA1 output channel output select. These bits select the output channel at
which ADC_SDATA1 starts to output data. The output port sequentially outputs
data following this start channel according to the setting of Bit SAI.
00 Channel 0.
01 Channel 2.
10 Channel 4.
11 Channel 6.
[1:0] ADC_SDATA0_ST
SDATA0 output channel output select. These bits select the output channel at
which ADC_SDATA0 starts to output data. The output port sequentially outputs
data following this start channel according to the setting of Bit SAI.
0x0
R/W
00 Channel 0.
01 Channel 2.
10 Channel 4.
11 Channel 6.
OUTPUT ASRC0/OUTPUT ASRC1 SOURCE REGISTER
Address: 0x18, Reset: 0x10, Name: ASRCO_SOURCE_0_1
Table 61. Bit Descriptions for ASRCO_SOURCE_0_1
Bits
Bit Name
Settings Description
Reset
Access
[7:4] ASRC_OUT_SOURCE1
Output ASRC Channel 1 source select.
0x1
R/W
0000 Core Output 0.
0001 Core Output 1.
0010 Core Output 2.
0011 Core Output 3.
0100 ADC0.
0101 ADC1.
0110 ADC2.
0111 ADC3.
Rev. 0 | Page 69 of 108
ADAU1777
Data Sheet
Bits
Bit Name
Settings Description
1000 Serial Input 0.
1001 Serial Input 1.
1010 Serial Input 2.
1011 Serial Input 3.
1100 Serial Input 4.
1101 Serial Input 5.
1110 Serial Input 6.
1111 Serial Input 7.
Reset
Access
[3:0] ASRC_OUT_SOURCE0
Output ASRC Channel 0 source select.
0x0
R/W
0000 Core Output 0.
0001 Core Output 1.
0010 Core Output 2.
0011 Core Output 3.
0100 ADC0.
0101 ADC1.
0110 ADC2.
0111 ADC3.
1000 Serial Input 0.
1001 Serial Input 1.
1010 Serial Input 2.
1011 Serial Input 3.
1100 Serial Input 4.
1101 Serial Input 5.
1110 Serial Input 6.
1111 Serial Input 7.
OUTPUT ASRC2/OUTPUT ASRC3 SOURCE REGISTER
Address: 0x19, Reset: 0x32, Name: ASRCO_SOURCE_2_3
Table 62. Bit Descriptions for ASRCO_SOURCE_2_3
Bits
Bit Name
Settings Description
Reset
Access
[7:4] ASRC_OUT_SOURCE3
Output ASRC Channel 3 source select.
0x3
R/W
0000 Core Output 0.
0001 Core Output 1.
0010 Core Output 2.
0011 Core Output 3.
0100 ADC0.
Rev. 0 | Page 70 of 108
Data Sheet
ADAU1777
Bits
Bit Name
Settings Description
0101 ADC1.
Reset
Access
0110 ADC2.
0111 ADC3.
1000 Serial Input 0.
1001 Serial Input 1.
1010 Serial Input 2.
1011 Serial Input 3.
1100 Serial Input 4.
1101 Serial Input 5.
1110 Serial Input 6.
1111 Serial Input 7.
[3:0] ASRC_OUT_SOURCE2
Output ASRC Channel 2 source select.
0x2
R/W
0000 Core Output 0.
0001 Core Output 1.
0010 Core Output 2.
0011 Core Output 3.
0100 ADC0.
0101 ADC1.
0110 ADC2.
0111 ADC3.
1000 Serial Input 0.
1001 Serial Input 1.
1010 Serial Input 2.
1011 Serial Input 3.
1100 Serial Input 4.
1101 Serial Input 5.
1110 Serial Input 6.
1111 Serial Input 7.
INPUT ASRC CHANNEL SELECT REGISTER
Address: 0x1A, Reset: 0x00, Name: ASRC_MODE
Rev. 0 | Page 71 of 108
ADAU1777
Data Sheet
Table 63. Bit Descriptions for ASRC_MODE
Bits
[7:4]
[3:2]
Bit Name
Settings
Description
Reset
Access
R/W
RESERVED
ASRC_IN_CH
Reserved.
0x0
0x0
Input ASRC channel select.
R/W
00 Serial Input Port Channel 0/Serial Input Port Channel 1.
01 Serial Input Port Channel 2/Serial Input Port Channel 3.
10 Serial Input Port Channel 4/Serial Input Port Channel 5.
11 Serial Input Port Channel 6/Serial Input Port Channel 7.
Output ASRC enable.
1
0
ASRC_OUT_EN
ASRC_IN_EN
0x0
0x0
R/W
R/W
0
1
Disabled.
Enabled.
Input ASRC enable.
Disabled.
0
1
Enabled.
ADC0/ADC1 CONTROL 0 REGISTER
Address: 0x1B, Reset: 0x19, Name: ADC_CONTROL0
Table 64. Bit Descriptions for ADC_CONTROL0
Bits Bit Name
Settings Description
Reset Access
[7:6] RESERVED
Reserved.
0x0
0x0
R/W
R/W
5
4
3
2
ADC_0_1_SINC
Selects third- or fourth-order sinc. Do not change this setting while the core is
running. CORE_RUN must be set to 0 for this setting to be updated.
0
1
Fourth-order sinc.
Third-order sinc.
ADC1_MUTE
ADC0_MUTE
RESERVED
Mute ADC1. Muting is accomplished by setting the volume control to maximum
attenuation. This bit has no effect if volume control is bypassed.
0x1
0x1
0x0
R/W
R/W
R/W
0
1
Unmuted.
Muted.
Mute ADC0. Muting is accomplished by setting the volume control to maximum
attenuation. This bit has no effect if volume control is bypassed.
0
1
Unmuted.
Muted.
Reserved.
Rev. 0 | Page 72 of 108
Data Sheet
ADAU1777
Bits Bit Name
Settings Description
Sets ADC sample rate. The settings of these bits must be consistent with the
Reset Access
[1:0] ADC_0_1_FS
0x1
R/W
settings of the FAST_ SLOW_RATE bits, and CORE_RUN must be set to 0 for this
setting to be updated.
00 96 kHz.
01 192 kHz.
10 768 kHz.
11 Reserved.
ADC2/ADC3 CONTROL 0 REGISTER
Address: 0x1C, Reset: 0x19, Name: ADC_CONTROL1
Table 65. Bit Descriptions for ADC_CONTROL1
Bits Bit Name
Settings Description
Reset Access
[7:6] RESERVED
Reserved.
0x0
0x0
R/W
R/W
5
ADC_2_3_SINC
Selects third- or fourth-order sinc. Do not change this setting while the core is
running. CORE_RUN must be set to 0 for this setting to be updated.
0
1
Fourth-order sinc.
Third-order sinc.
Mute ADC3.
Unmuted.
4
3
ADC3_MUTE
ADC2_MUTE
0x1
0x1
R/W
R/W
0
1
Muted.
Mute ADC2. Muting is accomplished by setting the volume control to maximum
attenuation. This bit has no effect if volume control is bypassed.
0
1
Unmuted.
Muted.
2
RESERVED
Reserved.
0x0
0x1
R/W
R/W
[1:0] ADC_2_3_FS
Sets ADC sample rate. The settings of these bits must be consistent with the
settings of the FAST_ SLOW_RATE bits, and CORE_RUN must be set to 0 for this
setting to be updated.
00 96 kHz.
01 192 kHz.
10 768 kHz.
11 Reserved.
Rev. 0 | Page 73 of 108
ADAU1777
Data Sheet
ADC0/ADC1 CONTROL 1 REGISTER
Address: 0x1D, Reset: 0x00, Name: ADC_CONTROL2
Table 66. Bit Descriptions for ADC_CONTROL2
Bits Bit Name
RESERVED
[6:5] HP_0_1_EN
Settings Description
Reset Access
7
Reserved.
0x0
0x0
R/W
R/W
High-pass filter settings.
00 Off.
01 1 Hz.
10 4 Hz.
11 8 Hz.
4
3
2
1
DMIC_POL0
DMIC_SW0
DCM_0_1
Selects microphone polarity.
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
0
1
0 positive, 1 negative.
1 positive, 0 negative.
Digital microphone swap.
0
1
Channel swap off (left channel on rising edge, right channel on falling edge).
Swap left and right.
Sets the input source to ADCs or digital microphones.
Decimator source set to ADC.
0
1
Decimator source set to digital microphones.
ADC_1_EN
Enable ADC1. This bit must be set in conjunction with the SINC_1_EN bit in the
DECIM_PWR_MODES register to fully enable or disable the ADC.
0
1
Disable.
Enable.
0
ADC_0_EN
Enable ADC0. This bit must be set in conjunction with the SINC_0_EN bit in the
DECIM_PWR_MODES register to fully enable or disable the ADC.
0x0
R/W
0
1
Disable.
Enable.
Rev. 0 | Page 74 of 108
Data Sheet
ADAU1777
ADC2/ADC3 CONTROL 1 REGISTER
Address: 0x1E, Reset: 0x00, Name: ADC_CONTROL3
Table 67. Bit Descriptions for ADC_CONTROL3
Bits Bit Name
RESERVED
[6:5] HP_2_3_EN
Settings Description
Reset Access
7
Reserved.
0x0
0x0
R/W
R/W
High-pass filter settings.
00 Off.
01 1 Hz.
10 4 Hz.
11 8 Hz.
4
3
2
1
DMIC_POL1
DMIC_SW1
DCM_2_3
Microphone polarity.
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
0
1
0 positive, 1 negative.
1 positive, 0 negative.
Digital microphone swap.
0
1
Channel swap off (left channel on rising edge, right channel on falling edge).
Swap left and right.
Sets the input source to ADCs or digital microphones.
Decimator source set to ADC.
0
1
Decimator source set to digital microphone.
ADC_3_EN
Enable ADC3. This bit must be set in conjunction with the SINC_3_EN bit in the
DECIM_PWR_MODES register to fully enable or disable the ADC.
0
1
Disable.
Enable.
0
ADC_2_EN
Enable ADC2. This bit must be set in conjunction with the SINC_2_EN bit in the
DECIM_PWR_MODES register to fully enable or disable the ADC.
0x0
R/W
0
1
Disable.
Enable.
ADC0 VOLUME CONTROL REGISTER
Address: 0x1F, Reset: 0x00, Name: ADC0_VOLUME
When SINC_0_EN is set, the volume starts to ramp from −95.625 dB to the value in this register. The volume ramp time is (number of
steps) × 16/fS, where there are 256 steps between 0 dB and −95.625 dB. For example, with fS = 192 kHz, the volume ramps from −95.625 dB to
0 dB in 21 ms.
Rev. 0 | Page 75 of 108
ADAU1777
Data Sheet
Table 68. Bit Descriptions for ADC0_VOLUME
Bits
Bit Name
Settings
Description
Reset
0x0
Access
[7:0]
ADC_0_VOL
ADC0 volume setting.
R/W
00000000 0 dB.
00000001 −0.375 dB.
11111111 −95.625 dB.
ADC1 VOLUME CONTROL REGISTER
Address: 0x20, Reset: 0x00, Name: ADC1_VOLUME
When SINC_1_EN is set, the volume starts to ramp from −95.625 dB to the value in this register. The volume ramp time is (number of
steps) × 16/fS, where there are 256 steps between 0 dB and −95.625 dB. For example, with fS = 192 kHz, the volume ramps from −95.625 dB to
0 dB in 21 ms.
Table 69. Bit Descriptions for ADC1_VOLUME
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
ADC_1_VOL
ADC1 volume setting.
0x0
R/W
00000000 0 dB.
00000001 −0.375 dB.
11111111 −95.625 dB.
ADC2 VOLUME CONTROL REGISTER
Address: 0x21, Reset: 0x00, Name: ADC2_VOLUME
When SINC_2_EN is set, the volume starts to ramp from −95.625 dB to the value in this register. The volume ramp time is (number of
steps) × 16/fS, where there are 256 steps between 0 dB and −95.625 dB. For example, with fS = 192 kHz, the volume ramps from
−95.625 dB to 0 dB in 21 ms.
Table 70. Bit Descriptions for ADC2_VOLUME
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
ADC_2_VOL
ADC2 volume setting.
0x0
R/W
00000000 0 dB.
00000001 −0.375 dB.
11111111 −95.625 dB.
Rev. 0 | Page 76 of 108
Data Sheet
ADAU1777
ADC3 VOLUME CONTROL REGISTER
Address: 0x22, Reset: 0x00, Name: ADC3_VOLUME
When SINC_3_EN is set, the volume starts to ramp from −95.625 dB to the value in this register. The volume ramp time is (number of
steps) × 16/fS, where there are 256 steps between 0 dB and −95.625 dB. For example, with fS = 192 kHz, the volume ramps from
−95.625 dB to 0 dB in 21 ms.
Table 71. Bit Descriptions for ADC3_VOLUME
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
ADC_3_VOL
ADC3 volume setting.
0x0
R/W
00000000 0 dB.
00000001 −0.375 dB.
11111111 −95.625 dB.
PGA CONTROL 0 REGISTER
Address: 0x23, Reset: 0x40, Name: PGA_CONTROL_0
This register controls the PGA connected to AIN0.
Table 72. Bit Descriptions for PGA_CONTROL_0
Bits Bit Name
Settings Description
Reset
Access
7
PGA_EN0
Select line or microphone input. Note that the PGA inverts the signal going
0x0
R/W
through it.
0
1
AIN0 used as a single-ended line input. PGA powered down.
AIN0 used as a single-ended microphone input. PGA powered up with slewing.
6
PGA_MUTE0
Enable PGA mute. When PGA is muted, PGA_GAIN0 is ignored.
0x1
0x0
R/W
R/W
0
1
Unmuted.
Muted.
[5:0] PGA_GAIN0
Set the gain of PGA0.
000000 −12 dB.
000001 −11.25 dB.
010000 0 dB.
111110 +34.5 dB.
111111 +35.25 dB.
Rev. 0 | Page 77 of 108
ADAU1777
Data Sheet
PGA CONTROL 1 REGISTER
Address: 0x24, Reset: 0x40, Name: PGA_CONTROL_1
This register controls the PGA connected to AIN1.
Table 73. Bit Descriptions for PGA_CONTROL_1
Bits Bit Name
Settings Description
Reset
Access
7
PGA_EN1
Select line or microphone input. Note that the PGA inverts the signal going
0x0
R/W
through it.
0
1
AIN1 used as a single-ended line input. PGA powered down.
AIN1 used as a single-ended microphone input. PGA powered up with slewing.
6
PGA_MUTE1
Enable PGA1 mute. When PGA is muted, PGA_GAIN1 is ignored.
0x1
0x0
R/W
R/W
0
1
Unmuted.
Muted.
[5:0] PGA_GAIN1
Set the gain of PGA1.
000000 −12 dB.
000001 −11.25 dB.
010000 0 dB.
111110 +34.5 dB.
111111 +35.25 dB.
PGA CONTROL 2 REGISTER
Address: 0x25, Reset: 0x40, Name: PGA_CONTROL_2
This register controls the PGA connected to AIN2.
Table 74. Bit Descriptions for PGA_CONTROL_2
Bits Bit Name
Settings Description
Reset
Access
7
PGA_EN2
Select line or microphone input. Note that the PGA inverts the signal going
0x0
R/W
through it.
0
1
AIN2 used as a single-ended line input. PGA powered down.
AIN2 used as a single-ended microphone input. PGA powered up with slewing.
Rev. 0 | Page 78 of 108
Data Sheet
ADAU1777
Bits Bit Name
Settings Description
Enable PGA2 mute. When PGA is muted, PGA_GAIN2 is ignored.
Unmuted.
Reset
Access
6
PGA_MUTE2
0x1
R/W
0
1
Muted.
[5:0] PGA_GAIN2
Set the gain of PGA2.
0x0
R/W
000000 −12 dB.
000001 −11.25 dB.
010000 0 dB.
111110 +34.5 dB.
111111 +35.25 dB.
PGA CONTROL 3 REGISTER
Address: 0x26, Reset: 0x40, Name: PGA_CONTROL_3
This register controls the PGA connected to AIN3.
Table 75. Bit Descriptions for PGA_CONTROL_3
Bits Bit Name
Settings Description
Reset
Access
7
PGA_EN3
Select line or microphone input. Note that the PGA inverts the signal going
0x0
R/W
through it.
0
1
AIN3 used as a single-ended line input. PGA powered down.
AIN3 used as a single-ended microphone input. PGA powered up with slewing.
6
PGA_MUTE3
Enable PGA3 mute. When PGA is muted, PGA_GAIN3 is ignored.
0x1
0x0
R/W
R/W
0
1
Unmuted.
Muted.
[5:0] PGA_GAIN3
Set the gain of PGA3.
000000 −12 dB.
000001 −11.25 dB.
010000 0 dB.
111110 +34.5 dB.
111111 +35.25 dB.
Rev. 0 | Page 79 of 108
ADAU1777
Data Sheet
PGA SLEW CONTROL REGISTER
Address: 0x27, Reset: 0x00, Name: PGA_STEP_CONTROL
If PGA slew is disabled with the SLEW_PDx controls, the SLEW_RATE parameter is ignored for that PGA block.
Table 76. Bit Descriptions for PGA_STEP_CONTROL
Bits
[7:6]
[5:4]
Bit Name
RESERVED
SLEW_RATE
Settings
Description
Reset
Access
R/W
Reserved.
0x0
0x0
Controls how fast the PGA is slewed when changing gain.
R/W
00 21.5 ms.
01 42.5 ms.
10 85 ms.
3
2
1
0
SLEW_PD3
SLEW_PD2
SLEW_PD1
SLEW_PD0
PGA3 slew disable.
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
0
1
PGA slew enabled.
PGA slew disabled.
PGA2 slew disable.
PGA slew enabled.
PGA slew disabled.
PGA1 slew disable.
PGA slew enabled.
PGA slew disabled.
PGA0 slew disable.
PGA slew enabled.
PGA slew disabled.
0
1
0
1
0
1
PGA 10 DB GAIN BOOST REGISTER
Address: 0x28, Reset: 0x00, Name: PGA_10DB_BOOST
Each PGA can have an additional +10 dB gain added, making the PGA gain range −2 dB to +46 dB.
Rev. 0 | Page 80 of 108
Data Sheet
ADAU1777
Table 77. Bit Descriptions for PGA_10DB_BOOST
Bits
[7:4]
3
Bit Name
Settings
Description
Reset
Access
R/W
RESERVED
Reserved.
0x0
0x0
PGA_3_BOOST
Boost control for PGA3.
R/W
0
1
Default PGA gain set in Register PGA_CONTROL_3.
Additional 10 dB gain above setting in Register PGA_CONTROL_3.
Boost control for PGA2.
2
1
0
PGA_2_BOOST
PGA_1_BOOST
PGA_0_BOOST
0x0
0x0
0x0
R/W
R/W
R/W
0
1
Default PGA gain set in Register PGA_CONTROL_2.
Additional 10 dB gain above setting in Register PGA_CONTROL_2.
Boost control for PGA1.
0
1
Default PGA gain set in Register PGA_CONTROL_1.
Additional 10 dB gain above setting in Register PGA_CONTROL_1.
Boost control for PGA0.
0
1
Default PGA gain set in Register PGA_CONTROL_0.
Additional 10 dB gain above setting in Register PGA_CONTROL_0.
INPUT AND OUTPUT CAPACITOR CHARGING REGISTER
Address: 0x29, Reset: 0x3F, Name: POP_SUPPRESS
Table 78. Bit Descriptions for POP_SUPPRESS
Bits
[7:6]
5
Bit Name
Settings
Description
Reset
0x0
Access
R/W
RESERVED
Reserved.
HP_POP_DIS1
Disable pop suppression on Headphone Output 1.
0x1
R/W
0
Enabled.
1
Disabled.
4
3
2
HP_POP_DIS0
PGA_POP_DIS3
PGA_POP_DIS2
Disable pop suppression on Headphone Output 0.
0x1
0x1
0x1
R/W
R/W
R/W
0
1
Enabled.
Disabled.
Disable pop suppression on PGA3 input.
0
1
Enabled.
Disabled.
Disable pop suppression on PGA2 input.
0
1
Enabled.
Disabled.
Rev. 0 | Page 81 of 108
ADAU1777
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
1
PGA_POP_DIS1
Disable pop suppression on PGA1 input.
0x1
R/W
0
Enabled.
1
Disabled.
0
PGA_POP_DIS0
Disable pop suppression on PGA0 input.
0x1
R/W
0
1
Enabled.
Disabled.
DSP BYPASS PATH REGISTER
Address: 0x2A, Reset: 0x00, Name: TALKTHRU
Table 79. Bit Descriptions for TALKTHRU
Bits
[7:2]
[1:0]
Bit Name
Settings
Description
Reset
0x0
Access
R/W
RESERVED
Reserved.
TALKTHRU_PATH
Signal path when DSP bypass is enabled.
0x0
R/W
00 No DSP bypass.
01 ADC0 to DAC0.
10 ADC1 to DAC1.
11 ADC0 and ADC1 to DAC0 and DAC1.
DSP BYPASS GAIN FOR PGA0 REGISTER
Address: 0x2B, Reset: 0x00, Name: TALKTHRU_GAIN0
Table 80. Bit Descriptions for TALKTHRU_GAIN0
Bits
Bit Name
Settings Description
Reset
Access
[7:0] TALKTHRU_GAIN0_VAL
Sets the DAC0 volume when DSP bypass mode is enabled.
0x0
R/W
DSP BYPASS GAIN FOR PGA1 REGISTER
Address: 0x2C, Reset: 0x00, Name: TALKTHRU_GAIN1
Table 81. Bit Descriptions for TALKTHRU_GAIN1
Bits
Bit Name
Settings Description
Reset
Access
[7:0] TALKTHRU_GAIN1_VAL
Sets the DAC1 volume when DSP bypass mode is enabled.
0x0
R/W
Rev. 0 | Page 82 of 108
Data Sheet
ADAU1777
MICBIAS0_1 CONTROL REGISTER
Address: 0x2D, Reset: 0x00, Name: MIC_BIAS
Table 82. Bit Descriptions for MIC_BIAS
Bits
[7:6]
5
Bit Name
RESERVED
MIC_EN1
Settings
Description
Reset
Access
R/W
Reserved.
0x0
0x0
MICBIAS1 output enable.
Disabled.
R/W
0
1
Enabled.
4
MIC_EN0
MICBIAS0 output enable.
Disabled.
0x0
R/W
0
1
Enabled.
3
2
1
RESERVED
RESERVED
MIC_GAIN1
Reserved.
0x0
0x0
0x0
R/W
R/W
R/W
Reserved.
Level of the MICBIAS1 output.
0.9 × AVDD.
0
1
0.65 × AVDD.
0
MIC_GAIN0
Level of the MICBIAS0 output.
0.9 × AVDD.
0x0
R/W
0
1
0.65 × AVDD.
DAC CONTROL REGISTER
Address: 0x2E, Reset: 0x18, Name: DAC_CONTROL1
Table 83. Bit Descriptions for DAC_CONTROL1
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
RESERVED
Reserved.
0x0
R/W
Rev. 0 | Page 83 of 108
ADAU1777
Data Sheet
Bits
Bit Name
Settings
Description
Invert input polarity.
Normal.
Reset
Access
5
DAC_POL
0x0
0x1
0x1
R/W
0
1
Inverted.
4
3
DAC1_MUTE
DAC0_MUTE
Mute DAC1.
Unmuted.
R/W
R/W
0
1
Muted.
Mute DAC0.
Unmuted.
0
1
Muted.
2
1
RESERVED
DAC1_EN
Reserved.
0x0
0x0
R/W
R/W
Enable DAC1.
Disable DAC1.
Enable DAC1.
Enable DAC0.
Disable DAC0.
Enable DAC0.
0
1
0
DAC0_EN
0x0
R/W
0
1
DAC0 VOLUME CONTROL REGISTER
Address: 0x2F, Reset: 0x00, Name: DAC0_VOLUME
Table 84. Bit Descriptions for DAC0_VOLUME
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC_0_VOL
DAC0 volume setting.
0x0
R/W
00000000 0 dB.
00000001 −0.375 dB.
11111111 −95.625 dB.
DAC1 VOLUME CONTROL REGISTER
Address: 0x30, Reset: 0x00, Name: DAC1_VOLUME
Rev. 0 | Page 84 of 108
Data Sheet
ADAU1777
Table 85. Bit Descriptions for DAC1_VOLUME
Bits
Bit Name
Settings
Description
Reset
0x0
Access
[7:0]
DAC_1_VOL
DAC1 volume setting.
R/W
00000000 0 dB.
00000001 −0.375 dB.
11111111 −95.625 dB.
HEADPHONE OUTPUT MUTES REGISTER
Address: 0x31, Reset: 0x0F, Name: OP_STAGE_MUTES
Table 86. Bit Descriptions for OP_STAGE_MUTES
Bits Bit Name
[7:4] RESERVED
[3:2] HP_MUTE_R
Settings Description
Reset
0x0
Access
R/W
Reserved.
Mute the right output pins. When a pin is muted, it can be used as a common-mode 0x3
output.
R/W
00 Outputs unmuted.
01 HPOUTRP/LOUTRP muted, HPOUTRN/LOUTRN unmuted.
10 HPOUTRP/LOUTRP unmuted, HPOUTRN/LOUTRN muted.
11 Both output pins muted.
[1:0] HP_MUTE_L
Mute the left output pins. When a pin is muted, it can be used as a common-mode
output.
0x3
R/W
00 Outputs unmuted.
01 HPOUTLP/LOUTLP muted, HPOUTLN/LOUTLN unmuted.
10 HPOUTLP/LOUTLP unmuted, HPOUTLN/LOUTLN muted.
11 Both output pins muted.
SERIAL PORT CONTROL 0 REGISTER
Address: 0x32, Reset: 0x00, Name: SAI_0
Using 16-bit serial input/output limits device performance.
Rev. 0 | Page 85 of 108
ADAU1777
Data Sheet
Table 87. Bit Descriptions for SAI_0
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
SDATA_FMT
Serial data format.
00 TDM, I2S—data delayed from edge of LRCLK by 1 BCLK cycle.
0x0
0x0
0x0
R/W
01 TDM, left justified—data synchronized to edge of LRCLK.
10 Right justified, 24-bit data.
11 Right justified, 16-bit data.
Serial port mode.
[5:4]
[3:0]
SAI
R/W
R/W
00 Stereo (I2S, left justified, right justified).
01 TDM2.
10 TDM4.
11 TDM8.
SER_PORT_FS
Sampling rate on the serial ports.
0000 48 kHz.
0001 8 kHz.
0010 12 kHz.
0011 16 kHz.
0100 24 kHz.
0101 32 kHz.
0110 96 kHz.
0111 192 kHz.
SERIAL PORT CONTROL 1 REGISTER
Address: 0x33, Reset: 0x00, Name: SAI_1
Using 16-bit serial input/output limits device performance.
Table 88. Bit Descriptions for SAI_1
Bits Bit Name
Settings Description
Reset
0x0
Access
7
TDM_TS
Select whether to tristate unused TDM channels or to actively drive these data slots.
R/W
0
1
Unused outputs driven.
Unused outputs tristated.
Rev. 0 | Page 86 of 108
Data Sheet
ADAU1777
Bits Bit Name
Settings Description
Bit width in TDM mode.
Reset
Access
6
5
4
3
2
1
0
BCLK_TDMC
LR_MODE
LR_POL
0x0
R/W
0
1
24-bit data in each TDM channel.
16-bit data in each TDM channel.
Sets LRCLK mode.
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
0
1
50% duty cycle clock.
Pulse—LRCLK is a single BCLK cycle wide pulse.
Sets LRCLK polarity.
0
1
50%: when LRCLK goes low and then high, pulse mode is short positive pulse.
50%: when LRCLK goes high and then low, pulse mode is short negative pulse.
Sets data to be input/output either MSB or LSB first.
MSB first data.
SAI_MSB
BCLKRATE
BCLKEDGE
SAI_MS
0
1
LSB first data.
Sets the number of bit clock cycles per data channel.
32 BCLK cycles/channel.
0
1
16 BCLK cycles/channel.
Sets the bit clock edge on which data changes.
Data changes on falling edge.
0
1
Data changes on rising edge.
Sets the serial port into master or slave mode.
LRCLK/BCLK slave.
0
1
LRCLK/BCLK master.
TDM OUTPUT CHANNEL DISABLE REGISTER
Address: 0x34, Reset: 0x00, Name: SOUT_CONTROL0
This register is for use only in TDM mode.
Table 89. Bit Descriptions for SOUT_CONTROL0
Bits
Bit Name
Settings
Description
Reset
0x0
Access
7
TDM7_DIS
Disable data in TDM Output Slot 7.
Output channel enabled.
Output channel disabled.
R/W
0
1
Rev. 0 | Page 87 of 108
ADAU1777
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
6
TDM6_DIS
Disable data in TDM Output Slot 6.
Output channel enabled.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
0
1
Output channel disabled.
Disable data in TDM Output Slot 5.
Output channel enabled.
5
4
3
2
1
0
TDM5_DIS
TDM4_DIS
TDM3_DIS
TDM2_DIS
TDM1_DIS
TDM0_DIS
R/W
R/W
R/W
R/W
R/W
R/W
0
1
Output channel disabled.
Disable data in TDM Output Slot 4.
Output channel enabled.
0
1
Output channel disabled.
Disable data in TDM Output Slot 3.
Output channel enabled.
0
1
Output channel disabled.
Disable data in TDM Output Slot 2.
Output channel enabled.
0
1
Output channel disabled.
Disable data in TDM Output Slot 1.
Output channel enabled.
0
1
Output channel disabled.
Disable data in TDM Output Slot 0.
Output channel enabled.
0
1
Output channel disabled.
PDM ENABLE REGISTER
Address: 0x36, Reset: 0x00, Name: PDM_OUT
Table 90. Bit Descriptions for PDM_OUT
Bits Bit Name
Settings Description
Reset Access
[7:5] RESERVED
Reserved.
0x0
0x0
R/W
R/W
4
PDM_CTRL
Enable the control pattern in the PDM data stream.
Disabled.
Enabled.
0
1
Rev. 0 | Page 88 of 108
Data Sheet
ADAU1777
Bits Bit Name
Settings Description
Selects the channel on which the control patterns are written. Do not change these
Reset Access
[3:2] PDM_CH
0x0
R/W
control bits while the PDM channel is operating and transmitting audio.
00 Both channels.
01 Left channel.
10 Right channel.
11 Reserved.
[1:0] PDM_EN
Enable PDM output on Pin PDMOUT.
0x0
R/W
00 PDM disabled.
01 PDM left signal in both PDM channels.
10 PDM right signal in both PDM channels.
11 PDM stereo.
PDM PATTERN SETTING REGISTER
Address: 0x37, Reset: 0x00, Name: PDM_PATTERN
Table 91. Bit Descriptions for PDM_PATTERN
Bits Bit Name Settings Description
Reset Access
[7:0] PATTERN
PDM pattern byte. The PDM pattern byte must not be changed while the PDM channel
is operating and transmitting the pattern.
0x0
R/W
MP0 FUNCTION SETTING REGISTER
Address: 0x38, Reset: 0x00, Name: MODE_MP0
Table 92. Bit Descriptions for MODE_MP0
Bits
[7:5]
[4:0]
Bit Name
Settings
Description
Reset
0x0
Access
R/W
RESERVED
Reserved.
MODE_MP0_VAL
Sets the function of Pin DAC_SDATA/MP0.
0x0
R/W
00000 Serial Input 0.
00001 Mute ADC0.
00010 Mute ADC1.
00011 Mute ADC2.
00100 Mute ADC3.
00101 Mute ADC0 and ADC1.
00110 Mute ADC2 and ADC3.
00111 Mute all ADCs.
Rev. 0 | Page 89 of 108
ADAU1777
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
01000 Mute DAC0.
01001 Mute DAC1.
01010 Mute both DACs.
01011 A/B bank switch.
01110 Enable compression.
01111 DSP bypass enable.
10000 Push-button volume up.
10001 Push-button volume down.
MP1 FUNCTION SETTING REGISTER
Address: 0x39, Reset: 0x10, Name: MODE_MP1
Table 93. Bit Descriptions for MODE_MP1
Bits
[7:5]
[4:0]
Bit Name
Settings
Description
Reset
0x0
Access
R/W
RESERVED
Reserved.
MODE_MP1_VAL
Sets the function of Pin ADC_SDATA0/PDMOUT/MP1.
0x10
R/W
00000 Serial Output 0.
00001 Mute ADC0.
00010 Mute ADC1.
00011 Mute ADC2.
00100 Mute ADC3.
00101 Mute ADC0 and ADC1.
00110 Mute ADC2 and ADC3.
00111 Mute all ADCs.
01000 Mute DAC0.
01001 Mute DAC1.
01010 Mute both DACs.
01011 A/B bank switch.
01110 Enable compression.
01111 DSP bypass enable.
10000 Push-button volume up.
10001 Push-button volume down.
10010 PDM modulator output.
Rev. 0 | Page 90 of 108
Data Sheet
ADAU1777
MP2 FUNCTION SETTING REGISTER
Address: 0x3A, Reset: 0x00, Name: MODE_MP2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] RESERVED
[4:0] MODE_MP2_VAL (R/W)
Sets the function of Pin BCLK/MP2
00000: Bit clock.
00001: Mute ADC0.
00010: Mute ADC1.
...
01111: DSP bypass enable.
10000: Push-button volume up.
10001: Push-button volume down.
Table 94. Bit Descriptions for MODE_MP2
Bits
[7:5]
[4:0]
Bit Name
Settings
Description
Reset
0x0
Access
R/W
RESERVED
Reserved.
MODE_MP2_VAL
Sets the function of Pin BCLK/MP2
Bit clock.
0x0
R/W
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
Mute ADC0.
Mute ADC1.
Mute ADC2.
Mute ADC3.
Mute ADC0 and ADC1.
Mute ADC2 and ADC3.
Mute all ADCs.
Mute DAC0.
Mute DAC1.
Mute both DACs.
A/B bank switch.
Reserved.
Reserved.
Enable compression.
DSP bypass enable.
Push-button volume up.
Push-button volume down.
MP3 FUNCTION SETTING REGISTER
Address: 0x3B, Reset: 0x00, Name: MODE_MP3
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] RESERVED
[4:0] MODE_MP3_VAL (R/W)
Sets the function of Pin LRCLK/MP3
00000: Left/right clock.
00001: Mute ADC0.
00010: Mute ADC1.
...
01111: DSP bypass enable.
10000: Push-button volume up.
10001: Push-button volume down.
Table 95. Bit Descriptions for MODE_MP3
Bits
Bit Name
Settings
Description
Reset
0x0
Access
[7:5]
RESERVED
Reserved.
R/W
Rev. 0 | Page 91 of 108
ADAU1777
Data Sheet
Bits
Bit Name
MODE_MP3_VAL
Settings
Description
Reset
0x0
Access
[4:0]
Sets the function of Pin LRCLK/MP3
Left/right clock.
Mute ADC0.
R/W
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
Mute ADC1.
Mute ADC2.
Mute ADC3.
Mute ADC0 and ADC1.
Mute ADC2 and ADC3.
Mute all ADCs.
Mute DAC0.
Mute DAC1.
Mute both DACs.
A/B bank switch.
Reserved.
Reserved.
Enable compression.
DSP bypass enable.
Push-button volume up.
Push-button volume down.
MP4 FUNCTION SETTING REGISTER
Address: 0x3C, Reset: 0x00, Name: MODE_MP4
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] RESERVED
[4:0] MODE_MP4_VAL (R/W)
Sets the function of Pin DMIC0_1/MP4
00000: Digital Microphone Input Channel
0/Digital Microphone Input Channel 1.
00001: Mute ADC0.
00010: Mute ADC1.
...
01111: DSP bypass enable.
10000: Push-button volume up.
10001: Push-button volume down.
Table 96. Bit Descriptions for MODE_MP4
Bits
Bit Name
Settings
Description
Reset
0x0
Access
[7:5] RESERVED
Reserved.
R/W
R/W
[4:0] MODE_MP4_VAL
Sets the function of Pin DMIC0_1/MP4
0x0
00000
00001
00010
00011
00100
00101
00110
00111
01000
Digital Microphone Input Channel 0/Digital Microphone Input Channel 1.
Mute ADC0.
Mute ADC1.
Mute ADC2.
Mute ADC3.
Mute ADC0 and ADC1.
Mute ADC2 and ADC3.
Mute all ADCs.
Mute DAC0.
Rev. 0 | Page 92 of 108
Data Sheet
ADAU1777
Bits
Bit Name
Settings
01001
01010
01011
01100
01101
01110
01111
10000
10001
Description
Reset
Access
Mute DAC1.
Mute both DACs.
A/B bank switch.
Reserved.
Reserved.
Enable compression.
DSP bypass enable.
Push-button volume up.
Push-button volume down.
MP5 FUNCTION SETTING REGISTER
Address: 0x3D, Reset: 0x00, Name: MODE_MP5
Table 97. Bit Descriptions for MODE_MP5
Bits
Bit Name
Settings
Description
Reset
0x0
Access
R/W
[7:5] RESERVED
Reserved.
[4:0] MODE_MP5_VAL
Sets the function of Pin DMIC2_3/MP5.
0x0
R/W
00000 Digital Microphone Input Channel 2/Digital Microphone Input Channel 3.
00001 Mute ADC0.
00010 Mute ADC1.
00011 Mute ADC2.
00100 Mute ADC3.
00101 Mute ADC0 and ADC1.
00110 Mute ADC2 and ADC3.
00111 Mute all ADCs.
01000 Mute DAC0.
01001 Mute DAC1.
01010 Mute both DACs.
01011 A/B bank switch.
01100 Reserved.
01101 Reserved.
01110 Enable compression.
01111 DSP bypass enable.
10000 Push-button volume up.
10001 Push-button volume down.
Rev. 0 | Page 93 of 108
ADAU1777
Data Sheet
MP6 FUNCTION SETTING REGISTER
Address: 0x3E, Reset: 0x11, Name: MODE_MP6
Table 98. Bit Descriptions for MODE_MP6
Bits
[7:5]
[4:0]
Bit Name
Settings
Description
Reset
0x0
Access
R/W
RESERVED
Reserved.
MODE_MP6_VAL
Sets the function of Pin ADC_SDATA1/CLKOUT/MP6.
0x11
R/W
00000 Serial Output 1.
00001 Mute ADC0.
00010 Mute ADC1.
00011 Mute ADC2.
00100 Mute ADC3.
00101 Mute ADC0 and ADC1.
00110 Mute ADC2 and ADC3.
00111 Mute all ADCs.
01000 Mute DAC0.
01001 Mute DAC1.
01010 Mute both DACs.
01011 A/B bank switch.
01100 Reserved.
01101 Reserved.
01110 Enable compression.
01111 DSP bypass enable.
10000 Push-button volume up.
10001 Push-button volume down.
10010 Clock output.
PUSH-BUTTON VOLUME SETTINGS REGISTER
Address: 0x3F, Reset: 0x00, Name: PB_VOL_SET
This register must be written before Bits PB_VOL_CONV_VAL are set to something other than the default value. Otherwise, the push-
button volume control is initialized to −96 dB.
Rev. 0 | Page 94 of 108
Data Sheet
ADAU1777
Table 99. Bit Descriptions for PB_VOL_SET
Bits Bit Name
Settings Description
Reset Access
[7:3] PB_VOL_INIT_VAL
Sets the initial volume of the push-button volume control. Each increment of
this register attenuates the level by 1.5 dB, from 0 dB to −46.5 dB.
0x0
R/W
00000 0.0 dB.
00001 −1.5 dB.
11111 −46.5 dB.
[2:0] HOLD
Sets the length of time that the button is held before the volume ramp begins.
0x0
R/W
000 150 ms.
001 300 ms.
010 450 ms.
011 600 ms.
100 900 ms.
101 1200 ms.
PUSH-BUTTON VOLUME CONTROL ASSIGNMENT REGISTER
Address: 0x40, Reset: 0x87, Name: PB_VOL_CONV
Table 100. Bit Descriptions for PB_VOL_CONV
Bits Bit Name
Settings Description
Reset Access
[7:6] GAINSTEP
Sets the gain step for each press of the volume control button.
0x2
R/W
00 0.375 dB/press.
01 1.5 dB/press.
10 3.0 dB/press.
11 4.5 dB/press.
[5:3] RAMPSPEED
Sets the speed in dB/sec at which the volume control ramps when a button is held.
0x0
R/W
000 60 dB/sec.
001 48 dB/sec.
010 36 dB/sec.
011 30 dB/sec.
100 24 dB/sec.
101 18 dB/sec.
110 12 dB/sec.
111 6 dB/sec.
Rev. 0 | Page 95 of 108
ADAU1777
Data Sheet
Bits Bit Name
Settings Description
Converters controlled by push-button volume. The push-button volume
Reset Access
[2:0] PB_VOL_CONV_VAL
0x7
R/W
control is enabled when these bits are set to something other than the default
setting (111). When set to 111, the push-button volume is disabled and the
converter volumes are set by the ADCx_VOLUME and DACx_VOLUME
registers.
000 ADC0 and ADC1.
001 ADC2 and ADC3.
010 All ADCs.
011 DAC0 and DAC1.
100 DAC0.
101 DAC1.
110 Reserved.
111 None (default).
DEBOUNCE MODES REGISTER
Address: 0x41, Reset: 0x05, Name: DEBOUNCE_MODE
Table 101. Bit Descriptions for DEBOUNCE_MODE
Bits
[7:3]
[2:0]
Bit Name
RESERVED
DEBOUNCE
Settings
Description
Reset
Access
R/W
Reserved.
0x0
0x5
The debounce time setting for the MPx inputs.
R/W
000 Debounce 300 µs.
001 Debounce 600 µs.
010 Debounce 900 µs.
011 Debounce 5 ms.
100 Debounce 10 ms.
101 Debounce 20 ms.
110 Debounce 40 ms.
111 No debounce.
Rev. 0 | Page 96 of 108
Data Sheet
ADAU1777
HEADPHONE LINE OUTPUT SELECT REGISTER
Address: 0x43, Reset: 0x0F, Name: OP_STAGE_CTRL
Table 102. Bit Descriptions for OP_STAGE_CTRL
Bits Bit Name
Settings Description
Reset Access
[7:6] RESERVED
Reserved.
0x0
0x0
R/W
R/W
5
4
HP_EN_R
HP_EN_L
Sets the right channel in line output or headphone mode.
0
1
Right output in line output mode.
Right output in headphone mode.
Sets the left channel in line output or headphone mode
Left output in line output mode.
0x0
0x3
R/W
R/W
0
1
Left output in headphone output mode.
[3:2] HP_PDN_R
Output stage power control. These bits power down the right output stage, regardless
of whether the device is in line output or headphone mode. After enabling the
headphone output, wait at least 6 ms before unmuting the headphone output by
setting HP_MUTE_R in the OP_STAGE_MUTES register to 00.
00 HPOUTRN/LOUTRN and HPOUTRP/LOUTRP outputs enabled.
01 HPOUTRN/LOUTRN enabled, HPOUTRP/LOUTRP disabled.
10 HPOUTRN/LOUTRN disabled, HPOUTRP/LOUTRP enabled.
11 Right output stages powered down.
[1:0] HP_PDN_L
Output stage power control. These bits power down the left output stage, regardless of 0x3
whether the device is in line output or headphone mode. After enabling the
headphone output, wait at least 6 ms before unmuting the headphone output by
setting HP_MUTE_L in the OP_STAGE_MUTES register to 00.
R/W
00 HPOUTLN/LOUTLN and HPOUTLP/LOUTLP outputs enabled.
01 HPOUTLN/LOUTLN enabled, HPOUTLP/LOUTLP disabled.
10 HPOUTLN/LOUTLN disabled, HPOUTLP/LOUTLP enabled.
11 Left output stages powered down.
DECIMATOR POWER CONTROL REGISTER
Address: 0x44, Reset: 0x00, Name: DECIM_PWR_MODES
The bits in this register enable clocks to the digital filters and the ASRC decimator filters of the ADCs. These bits must be enabled for all
channels used in the design. To use the ADCs, these SINC_x_EN bits must be enabled along with the appropriate ADC_x_EN bits in the
ADC_CONTROL2 and ADC_CONTROL3 registers. If the digital microphone inputs are used, the SINC_x_EN bits can be set without
setting ADC_x_EN.
Rev. 0 | Page 97 of 108
ADAU1777
Data Sheet
Table 103. Bit Descriptions for DECIM_PWR_MODES
Bits
Bit Name
Settings
Description
Reset
Access
7
DEC_3_EN
Control power to the ASRC3 decimator.
Powered down.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
0
1
Powered up.
6
5
4
3
2
1
0
DEC_2_EN
DEC_1_EN
DEC_0_EN
SINC_3_EN
SINC_2_EN
SINC_1_EN
SINC_0_EN
Control power to the ASRC2 decimator.
Powered down.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
Powered up.
Control power to the ASRC1 decimator.
Powered down.
0
1
Powered up.
Control power to the ASRC0 decimator.
Powered down.
0
1
Powered up.
ADC3 filter power control.
Powered down.
0
1
Powered up.
ADC2 filter power control.
Powered down.
0
1
Powered up.
ADC1 filter power control.
Powered down.
0
1
Powered up.
ADC0 filter power control.
Powered down.
0
1
Powered up.
Rev. 0 | Page 98 of 108
Data Sheet
ADAU1777
ASRC INTERPOLATOR AND DAC MODULATOR POWER CONTROL REGISTER
Address: 0x45, Reset: 0x00, Name: INTERP_PWR_MODES
Table 104. Bit Descriptions for INTERP_PWR_MODES
Bits
[7:4]
3
Bit Name
RESERVED
MOD_1_EN
Settings
Description
Reset
Access
R/W
Reserved.
0x0
0x0
DAC Modulator 1 enable.
Powered down.
Powered up.
R/W
0
1
2
1
0
MOD_0_EN
INT_1_EN
INT_0_EN
DAC Modulator 0 enable.
Powered down.
Powered up.
0x0
0x0
0x0
R/W
R/W
R/W
0
1
ASRC Interpolator 1 enable.
Powered down.
Powered up.
0
1
ASRC Interpolator 0 enable.
Powered down.
Powered up.
0
1
ANALOG BIAS CONTROL 0 REGISTER
Address: 0x46, Reset: 0x00, Name: BIAS_CONTROL0
Table 105. Bit Descriptions for BIAS_CONTROL0
Bits Bit Name
Settings Description
Reset Access
0x0 R/W
[7:6] HP_IBIAS
Headphone output bias current setting. Higher bias currents result in higher
performance.
00 Normal operation (default).
01 Extreme power saving.
10 Enhanced performance.
11 Power saving.
Rev. 0 | Page 99 of 108
ADAU1777
Data Sheet
Bits Bit Name
Settings Description
Analog Front-End 0 and Analog Front-End 1 bias current setting. Higher bias
Reset Access
[5:4] AFE_IBIAS01
0x0
0x0
0x0
R/W
R/W
R/W
currents result in higher performance.
00 Normal operation (default).
01 Extreme power saving.
10 Enhanced performance.
11 Power saving.
[3:2] ADC_IBIAS23
ADC2 and ADC3 bias current setting. Higher bias currents result in higher
performance.
00 Normal operation (default).
01 Reserved.
10 Enhanced performance.
11 Power saving.
[1:0] ADC_IBIAS01
ADC0 and ADC1 bias current setting. Higher bias currents result in higher
performance.
00 Normal operation (default).
01 Reserved.
10 Enhanced performance.
11 Power saving.
ANALOG BIAS CONTROL 1 REGISTER
Address: 0x47, Reset: 0x00, Name: BIAS_CONTROL1
Table 106. Bit Descriptions for BIAS_CONTROL1
Bits Bit Name
Settings Description
Reset Access
7
6
RESERVED
CBIAS_DIS
Reserved.
0x0
0x0
R/W
R/W
Central analog bias circuitry. Higher bias currents result in higher performance.
Powered up.
0
1
Powered down.
[5:4] AFE_IBIAS23
Analog Front-End 2 and Analog Front-End 3 bias current setting. Higher bias
currents result in higher performance.
0x0
R/W
00 Normal operation (default).
01 Extreme power saving.
10 Enhanced performance.
11 Power saving.
Rev. 0 | Page 100 of 108
Data Sheet
ADAU1777
Bits Bit Name
Settings Description
Microphone input bias current setting. Higher bias currents result in higher
Reset Access
[3:2] MIC_IBIAS
0x0
R/W
performance.
00 Normal operation (default).
01 Extreme power saving.
10 Enhanced performance.
11 Power saving.
[1:0] DAC_IBIAS
DAC bias current setting. Higher bias currents result in higher performance.
00 Normal operation (default).
01 Power saving.
0x0
R/W
10 Superior performance.
11 Enhanced performance.
DIGITAL PIN PULL-UP CONTROL 0 REGISTER
Address: 0x48, Reset: 0x7F, Name: PAD_CONTROL0
Enable pull-up resistors for each digital pin.
Table 107. Bit Descriptions for PAD_CONTROL0
Bits
Bit Name
Settings
Description
Reset
0x0
Access
R/W
7
RESERVED
DMIC2_3_PU
Reserved.
6
Pull-up disable.
Pull-up enabled.
Pull-up disabled.
Pull-up disable.
Pull-up enabled.
Pull-up disabled.
Pull-up disable.
Pull-up enabled.
Pull-up disabled.
Pull-up disable.
Pull-up enabled.
Pull-up disabled.
0x1
R/W
0
1
5
4
3
DMIC0_1_PU
LRCLK_PU
BCLK_PU
0x1
0x1
0x1
R/W
R/W
R/W
0
1
0
1
0
1
Rev. 0 | Page 101 of 108
ADAU1777
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
2
ADC_SDATA1_PU
Pull-up disable.
Pull-up enabled.
Pull-up disabled.
Pull-up disable.
Pull-up enabled.
Pull-up disabled.
Pull-up disable.
Pull-up enabled.
Pull-up disabled.
0x1
R/W
0
1
1
0
ADC_SDATA0_PU
DAC_SDATA_PU
0x1
0x1
R/W
R/W
0
1
0
1
DIGITAL PIN PULL-UP CONTROL 1 REGISTER
Address: 0x49, Reset: 0x1F, Name: PAD_CONTROL1
Enable pull-up resistors for each digital pin.
Table 108. Bit Descriptions for PAD_CONTROL1
Bits
[7:5]
4
Bit Name
Settings
Description
Reset
0x0
Access
R/W
RESERVED
Reserved.
SELFBOOT_PU
Pull-up disable.
Pull-up enabled.
Pull-up disabled.
Pull-up disable.
Pull-up enabled.
Pull-up disabled.
Pull-up disable.
Pull-up enabled.
Pull-up disabled.
Pull-up disable.
Pull-up enabled.
Pull-up disabled.
Pull-up disable.
Pull-up enabled.
Pull-up disabled.
0x1
R/W
0
1
3
2
1
0
SCL_PU
0x1
0x1
0x1
0x1
R/W
R/W
R/W
R/W
0
1
SDA_PU
0
1
ADDR1_PU
ADDR0_PU
0
1
0
1
Rev. 0 | Page 102 of 108
Data Sheet
ADAU1777
DIGITAL PIN PULL-DOWN CONTROL 0 REGISTER
Address: 0x4A, Reset: 0x00, Name: PAD_CONTROL2
Enable pull-down resistors for each digital pin.
Table 109. Bit Descriptions for PAD_CONTROL2
Bits
Bit Name
Settings
Description
Reset
Access
R/W
7
RESERVED
DMIC2_3_PD
Reserved.
0x0
0x0
6
Pull-down enable.
Pull-down disabled.
Pull-down enabled.
Pull-down enable.
Pull-down disabled.
Pull-down enabled.
Pull-down enable.
Pull-down disabled.
Pull-down enabled.
Pull-down enable.
Pull-down disabled.
Pull-down enabled.
Pull-down enable.
Pull-down disabled.
Pull-down enabled.
Pull-down enable.
Pull-down disabled.
Pull-down enabled.
Pull-down enable.
Pull-down disabled.
Pull-down enabled.
R/W
0
1
5
4
3
2
1
0
DMIC0_1_PD
LRCLK_PD
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
1
BCLK_PD
0
1
ADC_SDATA1_PD
ADC_SDATA0_PD
DAC_SDATA_PD
0
1
0
1
0
1
DIGITAL PIN PULL-DOWN CONTROL 1 REGISTER
Address: 0x4B, Reset: 0x00, Name: PAD_CONTROL3
Enable pull-down resistors for each digital pin.
Rev. 0 | Page 103 of 108
ADAU1777
Data Sheet
Table 110. Bit Descriptions for PAD_CONTROL3
Bits
[7:5]
4
Bit Name
Settings
Description
Reset
Access
R/W
RESERVED
Reserved.
0x0
0x0
SELFBOOT_PD
Pull-down enable.
Pull-down disabled.
Pull-down enabled.
Pull-down enable.
Pull-down disabled.
Pull-down enabled.
Pull-down enable.
Pull-down disabled.
Pull-down enabled.
Pull-down enable.
Pull-down disabled.
Pull-down enabled.
Pull-down enable.
Pull-down disabled.
Pull-down enabled.
R/W
0
1
3
2
1
0
SCL_PD
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
0
1
SDA_PD
0
1
ADDR1_PD
ADDR0_PD
0
1
0
1
DIGITAL PIN DRIVE STRENGTH CONTROL 0 REGISTER
Address: 0x4C, Reset: 0x00, Name: PAD_CONTROL4
Table 111. Bit Descriptions for PAD_CONTROL4
Bits
Bit Name
RESERVED
RESERVED
RESERVED
Settings
Description
Reserved.
Reserved.
Reserved.
Reset
0x0
Access
R/W
7
6
0x0
R/W
5
0x0
R/W
Rev. 0 | Page 104 of 108
Data Sheet
ADAU1777
Bits
Bit Name
Settings
Description
Reset
Access
4
LRCLK_DRV
Drive strength control.
Low drive strength.
High drive strength.
Drive strength control.
Low drive strength.
High drive strength.
Drive strength control.
Low drive strength.
High drive strength.
Drive strength control.
Low drive strength.
High drive strength.
Reserved.
0x0
0x0
0x0
0x0
0x0
R/W
0
1
3
2
1
0
BCLK_DRV
R/W
R/W
R/W
R/W
0
1
ADC_SDATA1_DRV
ADC_SDATA0_DRV
RESERVED
0
1
0
1
DIGITAL PIN DRIVE STRENGTH CONTROL 1 REGISTER
Address: 0x4D, Reset: 0x00, Name: PAD_CONTROL5
Table 112. Bit Descriptions for PAD_CONTROL5
Bits
[7:5]
4
Bit Name
RESERVED
RESERVED
SCL_DRV
Settings
Description
Reset
0x0
Access
R/W
Reserved.
Reserved.
0x0
R/W
3
Drive strength control.
Low drive strength.
High drive strength.
Drive strength control.
Low drive strength.
High drive strength.
Reserved.
0x0
R/W
0
1
2
SDA_DRV
0x0
R/W
0
1
1
0
RESERVED
RESERVED
0x0
0x0
R/W
R/W
Reserved.
FAST RATE CONTROL REGISTER
Address: 0x4E, Reset: 0x00, Name: FAST_RATE
Rev. 0 | Page 105 of 108
ADAU1777
Data Sheet
Table 113. Bit Descriptions for FAST_RATE
Bits Bit Name
[7:3] RESERVED
[2:0] RATE_DIV
Settings Description
Reset Access
Reserved.
0x0
0x0
R/W
R/W
Set fast rate division factor. This factor is used to divide the internal master clock
(6.144 MHz) when CORE_FS = 11. Do not change this setting while the core is running.
CORE_RUN must be set to 0 for this setting to be updated.
000 Divide by 8 (768 kHz).
001 Divide by 9 (683 kHz).
010 Divide by 10 (614 kHz).
011 Divide by 12 (512 kHz).
100 Divide by 14 (439 kHz).
101 Divide by 16 (384 kHz).
DAC INTERPOLATION CONTROL REGISTER
Address: 0x4F, Reset: 0x00, Name: DAC_CONTROL0
The lowest interpolator latency is achieved with a zero-order hold (ZOH) selection. ZOH can be used for both 768 kHz and 192 kHz data.
For 96 kHz data, use the linear interpolation to attain the lowest latency.
Table 114. Bit Descriptions for DAC_CONTROL0
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
DAC_RATE
Sample rate for DAC.
0x0
R/W
00 Core fS.
01 Core fS/4.
10 Core fS/8.
11 Reserved.
[5:3]
DAC_INTP
Interpolation mode for the DAC.
0x0
R/W
000 Both DAC0 and DAC1 set to compensated interpolation.
001 DAC0 set to ZOH, DAC1 set to compensated interpolation.
010 DAC0 set to compensated interpolation, DAC1 set to ZOH.
011 Both DAC0 and DAC1 set to ZOH.
100 DAC0 set to linear interpolation, DAC1 set to compensated interpolation.
101 DAC0 set to compensated interpolation, DAC1 set to linear interpolation.
110 Both DAC0 and DAC1 set to linear interpolation.
Rev. 0 | Page 106 of 108
Data Sheet
ADAU1777
Bits
Bit Name
Settings
Description
Reset
Access
[2:0]
RESERVED
Reserved.
0x0
R/W
VOLUME CONTROL BYPASS REGISTER
Address: 0x54, Reset: 0x00, Name: VOL_BYPASS
Table 115. Bit Descriptions for VOL_BYPASS
Bits
[7:6]
5
Bit Name
Settings
Description
Reset
0x0
Access
R/W
RESERVED
DAC1VOL_BY
Reserved.
DAC1 volume control bypass.
Volume control enabled.
Bypassed.
0x0
R/W
0
1
4
3
2
1
0
DAC0VOL_BY
ADC3VOL_BY
ADC2VOL_BY
ADC1VOL_BY
ADC0VOL_BY
DAC0 volume control bypass.
Volume control enabled.
Bypassed.
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
0
1
ADC3 volume control bypass.
Volume control enabled.
Bypassed.
0
1
ADC2 volume control bypass.
Volume control enabled.
Bypassed.
0
1
ADC1 volume control bypass.
Volume control enabled.
Bypassed.
0
1
ADC0 volume control bypass.
Volume control enabled.
Bypassed.
0
1
Rev. 0 | Page 107 of 108
ADAU1777
Data Sheet
OUTLINE DIMENSIONS
3.805
3.765
3.725
7
6
5
4
3
2
1
A
B
C
D
E
F
BALL A1
IDENTIFIER
3.235
3.195
3.155
2.50
REF
0.50
BSC
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
3.00 REF
0.390
0.360
0.330
0.660
0.600
0.540
SIDE VIEW
COPLANARITY
0.05
SEATING
PLANE
0.360
0.320
0.280
0.270
0.240
0.210
Figure 79. 36-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-36-4)
Dimension shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Package Description
Package Option
ADAU1777BCBZRL −40°C to +85°C
EVAL-ADAU1777Z
36-Ball Wafer Level Chip Scale Package [WLCSP], 13”Tape and Reel
Evaluation Board
CB-36-4
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14796-0-12/16(0)
Rev. 0 | Page 108 of 108
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