ADAU1977 [ADI]
Quad ADC with Diagnostics; 四ADC与诊断
| 型号： | ADAU1977 |
| 厂家： | 
ADI |
| 描述： | Quad ADC with Diagnostics |
| 文件： | 总64页 (文件大小：3415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad ADC with Diagnostics
Data Sheet
ADAU1977
FEATURES
GENERAL DESCRIPTION
Programmable microphone bias (5 V to 9 V) with diagnostics
Four 10 V rms capable direct-coupled differential inputs
On-chip PLL for master clock
Low EMI design
106 dB ADC dynamic range
The ADAU1977 incorporates four high performance analog-to-
digital converters (ADCs) with direct-coupled inputs capable of
10 V rms. The ADC uses multibit sigma-delta (Σ-Δ) architecture
with continuous time front end for low EMI. The ADCs can be
connected to the electret microphone (ECM) directly and pro-
vide the bias for powering the microphone. Built-in diagnostic
circuitry detects faults on input lines and includes comprehensive
diagnostics for faults on microphone inputs. The faults reported
are short to battery, short to microphone bias, short to ground,
short between positive and negative input pins, and open input
terminals. In addition, each diagnostic fault is available as an
IRQ flag for ease in system design. An I2C/SPI control port is
also included. The ADAU1977 uses only a single 3.3 V supply.
The part internally generates the microphone bias voltage. The
microphone bias is programmable in a few steps from 5 V to 9 V.
The low power architecture reduces the power consumption.
An on-chip PLL can derive the master clock from an external
clock input or frame clock (sample rate clock). When fed with
a frame clock, the PLL eliminates the need for a separate high
frequency master clock in the system. The ADAU1977 is
available in a 40-lead LFCSP package.
−95 dB THD + N
Selectable digital high-pass filter
24-bit ADC with 8 kHz to 192 kHz sample rates
Digital volume control with autoramp function
I2C/SPI control
Software-controllable clickless mute
Software power-down
Right justified, left justified, I2S justified, and TDM modes
Master and slave operation modes
40-lead LFCSP package
Qualified for automotive applications
APPLICATIONS
Automotive audio systems
Active noise cancellation system
FUNCTIONAL BLOCK DIAGRAM
ADAU1977
5V TO 9V
BOOST
3.3V TO 1.8V
REGULATOR
CONVERTER
MICBIAS
MB_GND
DVDD
I
50mA
OUT
PROG
BIAS
PGND
AIN1P
AIN1N
AIN2P
AIN2N
AIN3P
AIN3N
AIN4P
AIN4N
IOVDD
ADC
ADC
LRCLK
BCLK
ADC
ADC
SDATAOUT1
SDATAOUT2
AGND1
AVDD2
AGND3
PLL
VBAT
SCL/CCLK
SDA/COUT
ADDR1/CIN
ADDR0/CLATCH
FAULT
AVDDx
I2C/SPI
CONTROL
BG
REF
DIAGNOSTICS
PD/RST
AGND2
AGND2
AGNDx
Figure 1.
Rev. A
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Tel: 781.329.4700
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www.analog.com
ADAU1977
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register Details ............................................................................... 35
Master Power and Soft Reset Register..................................... 35
PLL Control Register ................................................................. 36
DC-to-DC Boost Converter Control Register ....................... 37
MICBIAS and Boost Control Register .................................... 38
Block Power Control and Serial Port Control Register......... 39
Serial Port Control Register1.................................................... 40
Serial Port Control Register2.................................................... 41
Channel Mapping for Output Serial Ports Register............... 42
Channel Mapping for Output Serial Ports Register............... 44
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Analog Performance Specifications ........................................... 3
Diagnostic and Fault Specifications........................................... 4
Digital Input/Output Specifications........................................... 5
Power Supply Specifications........................................................ 5
Digital Filters Specifications ....................................................... 6
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 14
Overview...................................................................................... 14
Power Supply and Voltage Reference....................................... 14
Power-On Reset Sequence ........................................................ 14
PLL and Clock............................................................................. 15
DC-to-DC Boost Converter...................................................... 16
Microphone Bias......................................................................... 17
Analog Inputs.............................................................................. 17
ADC ............................................................................................. 21
ADC Summing Modes .............................................................. 21
Diagnostics.................................................................................. 21
Serial Audio Data Output Ports—Data Format ..................... 23
Control Ports................................................................................... 28
I2C Mode...................................................................................... 29
SPI Mode ..................................................................................... 32
Register Summary .......................................................................... 34
Serial Output Drive and Overtemperature Protection
Control Register ......................................................................... 46
Post ADC Gain Channel 1 Control Register.......................... 47
Post ADC Gain Channel 2 Control Register.......................... 48
Post ADC Gain Channel 3 Control Register.......................... 49
Post ADC Gain Channel 4 Control Register.......................... 50
High-Pass Filter and DC Offset Control Register and
Master Mute................................................................................ 51
Diagnostics Control Register.................................................... 52
Diagnostics Report Register Channel 1 .................................. 53
Diagnostics Report Register Channel 2 .................................. 54
Diagnostics Report Register Channel 3 .................................. 55
Diagnostics Report Register Channel 4 .................................. 56
Diagnostics Interrupt Pin Control Register 1......................... 57
Diagnostics Interrupt Pin Control Register 2......................... 58
Diagnostics Adjustments Register 1 ........................................ 59
Diagnostics Adjustments Register 2 ........................................ 60
ADC Clipping Status Register .................................................. 61
Digital DC High-Pass Filter and Calibration Register.......... 62
Applications Circuit ....................................................................... 63
Outline Dimensions ....................................................................... 64
Ordering Guide .......................................................................... 64
Automotive Products................................................................. 64
REVISION HISTORY
3/13—Rev. 0 to Rev. A
Changes to Channel Mapping for Output Serial Ports Register
Section and Table 34 .......................................................................44
Changes to Figure 46.......................................................................63
Changes to Ordering Guide...........................................................64
Changed CP-40-9 to CP-40-14.........................................Universal
Changes to Hysteresis AINxP and AINxN Shorted Together
Parameter, Table 2..............................................................................4
Changes to Thermal Resistance Section and Table 8....................9
Changes to SPI Mode Section........................................................32
1/13—Revision 0: Initial Version
Rev. A | Page 2 of 64
SPECIFICATIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
AVDDx/IOVDD = 3.3 V; DVDD (internally generated) = 1.8 V; VBAT = 14.4 V; TA = −40°C to +105°C, unless otherwise noted; master
clock = 12.288 MHz (48 kHz fS, 256 × fS mode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz; word width =
24 bits; load capacitance (digital output) = 20 pF; load current (digital output) = 1 mA; digital input voltage high = 2.0 V; digital input
voltage low = 0.8 V.
ANALOG PERFORMANCE SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
LINE INPUT APPLICATION
Full-Scale Differential Input Voltage
Full-Scale Single-Ended Input Voltage
MICROPHONE INPUT APPLICATION
Differential Input Voltage
QUASI DC INPUT
Single-Ended Input Voltage
Input Common-Mode Voltage
Peak Input Voltage
See Figure 46
DC-coupled, VCM at AINxP/AINxN = 7 V
DC-coupled, VCM at AINxP/AINxN = 7 V
See Figure 46, MICBIAS = 8.5 V
DC-coupled, VCM at AINxP = 5.66 V, AINxN = 2.83 V
10
5
V rms
V rms
2
5
V rms
V peak
V dc
V
VCM at AINxP/AINxN pins
VCM + V ac peak at AINxP/AINxN pins
0
0
8
14
MICROPHONE BIAS
Output Voltage
Programmable from 5 V to 9 V in steps of 0.5 V; the
output voltage is within the specified load
regulation
5
9
V
Load Regulation
Output Current
Output Noise
From no load to maximum load of 25 mA at 5 V
From no load to maximum load of 45 mA at 9 V
At MICBIAS = 5 V
−1
−1
+0.2
+0.3
+1
+1
25
45
32
54
%
%
mA
mA
µV rms
µV rms
dB
At MICBIAS = 9 V
20 Hz to 20 kHz, MICBIAS = 5 V
20 Hz to 20 kHz, MICBIAS = 9 V
350 mV rms, 1 kHz ripple on VBOOST_IN at 10 V
Referred to full scale at 1 kHz
With CLOAD = 1 nF
22
35
60
60
40
Power Supply Rejection Ratio (PSRR)
Interchannel Isolation at MICBIAS Pin
Start-Up Time
dB
ms
BOOST CONVERTER
Input Voltage
Input Current
2.97
3.3
195
220
50
3.63
V
L = 4.7 µH, fSW = 1.536 MHz, MICBIAS = 9 V at 45 mA load
L = 2.2 µH, fSW = 3.072 MHz, MICBIAS = 9 V at 45 mA load
MICBIAS = 5 V
mA
mA
mA
mA
%
Output Current
Load Regulation
MICBIAS = 9 V
88
From no load to maximum load of 50 mA at MICBIAS −1
= 5 V
From no load to maximum load of 88 mA at MICBIAS −1
= 9 V
+1
+1
%
Input Overcurrent Threshold
Switching Frequency
900
mA peak
MHz
MHz
fS = 48 kHz L = 2.2 µH
fS = 48 kHz, L = 4.7 µH
4.7
3.072
1.536
10
External Load Capacitor at VBOOST_OUT Pin
ANALOG-TO-DIGITAL CONVERTERS
Input Resistance
22
µF
Differential
Between AINxP and AINxN
Between AINxP and AINxN
50
25
24
kΩ
kΩ
Bits
Single-Ended (Rin1977
ADC Resolution
Dynamic Range (A-Weighted)1
)
Input = 1 kHz, −60 dBFS
Line Input
Microphone Input
Total Harmonic Distortion Plus Noise
(THD + N)
Referred to full-scale differential input = 10 V rms
Referred to full-scale differential input = 2 V rms
Input = 1 kHz, −1 dBFS (0 dBFS = 10 V rms input)
103
106
92
−95
dB
dB
dB
−89
Digital Gain Post ADC
Gain Error
Gain step size = 0.375 dB
−35.625
−10
+60
+10
dB
%
Interchannel Gain Mismatch
−0.25
+0.25
dB
ADAU1977
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
0.6
60
Max
Unit
ppm/°C
dB
Gain Drift
Common-Mode Rejection Ratio (CMRR)
1 V rms, 1 kHz
1 V rms, 20 kHz
56
dB
Power Supply Rejection Ratio (PSRR)
Interchannel Isolation
Interchannel Phase Deviation
REFERENCE
100 mV rms, 1 kHz on AVDDx = 3.3 V
70
100
0
dB
dB
Degrees
Internal Reference Voltage
Output Impedance
VREF pin
1.47
8
1.50
20
1.54
192
V
kΩ
ADC SERIAL PORT
Output Sample Rate
kHz
1 For fS ranging from 44.1 kHz to 192 kHz.
DIAGNOSTIC AND FAULT SPECIFICATIONS
Applicable to differential microphone input using MICBIAS on AINxP and AINxN pins.
Table 2.
Test Conditions/
Comments
Parameter
Min
Typ
Max
Unit
INPUT VOLTAGE THRESHOLDS FOR FAULT DETECTION1
Hysteresis AINxP or AINxN Shorted to VBAT
SHT_B_TRIP = 10 0.79 × VBAT
SHT_B_TRIP = 01 0.84 × VBAT
SHT_B_TRIP = 00 0.89 × VBAT
SHT_B_TRIP = 11 0.93 × VBAT
SHT_T_TRIP = 00 MICBIAS(0.5 0.015) MICBIAS(0.5
0.035)
0.85 × VBAT
0.9 × VBAT
0.95 × VBAT
0.975 × VBAT
0.86 × VBAT
0.91 × VBAT
0.96 × VBAT
0.99 × VBAT
MICBIAS(0.5
0.047)
V
V
V
V
V
Hysteresis AINxP and AINxN Shorted Together
SHT_T_TRIP = 01 MICBIAS(0.5 0.001) MICBIAS(0.5
0.017)
MICBIAS(0.5
0.03)
MICBIAS(0.5
0.08)
V
V
SHT_T_TRIP = 10 MICBIAS(0.5 0.05)
MICBIAS(0.5
0.071)
Hysteresis AINxP or AINxN Shorted to Ground
Hysteresis AINxP Shorted to MICBIAS
SHT_G_TRIP = 10
SHT_G_TRIP = 01
SHT_G_TRIP = 00
SHT_G_TRIP = 11
SHT_M_TRIP = 10 0.82 × MICBIAS
SHT_M_TRIP = 01 0.87 × MICBIAS
SHT_M_TRIP = 00 0.92 × MICBIAS
SHT_M_TRIP = 11 0.95 × MICBIAS
0.04 × VREF
0.08 × VREF
0.12 × VREF
0.19 × VREF
0.1 × VREF
0.133 × VREF
0.2 × VREF
0.266 × VREF
0.85 × MICBIAS
0.9 × MICBIAS
0.95 × MICBIAS
0.975 × MICBIAS
0.13 × VREF
0.16 × VREF
0.22 × VREF
0.28 × VREF
0.89 × MICBIAS
0.94 × MICBIAS
1.0 × MICBIAS
1.0 × MICBIAS
V
V
V
V
V
V
V
V
Hysteresis AINxP or AINxN Open Circuit2
Refer to the
AINxP shorted to
MICBIAS and the
AINxN shorted
to ground
specifications for
upper and lower
thresholds.
FAULT DURATION
Programmable
10
100
150
ms
1 The threshold limits are tested with VREF = 1.5 V, MICBIAS = 5 V to 8.5 V, and VBAT = 11 V to 18 V set using an external source. When VBAT ≤ MICBIAS, a short to VBAT
cannot be distinguished from a short to MICBIAS, and reporting a short to VBAT fault takes precedence over a short to MICBIAS fault.
2 The AINxP open terminal fault cannot be distinguished from the AINxN open terminal fault because the voltage at the AINxP and AINxN pins remain at MICBIAS and
ground, respectively, when either of these two terminals becomes open circuit.
Rev. A | Page 4 of 64
Data Sheet
ADAU1977
DIGITAL INPUT/OUTPUT SPECIFICATIONS
Table 3.
Parameter
Test Conditions/Comments
Min
Max
Unit
INPUT
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Leakage Current
Input Capacitance
0.7 × IOVDD
V
V
µA
pF
0.3 × IOVDD
10
5
OUTPUT
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
IOH = 1 mA
IOL = 1 mA
IOVDD − 0.60
V
V
0.4
POWER SUPPLY SPECIFICATIONS
L = 4.7 µH, AVDDx = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V, fS = 48 kHz (master mode), unless otherwise noted.
Table 4.
Parameter
Test Conditions/Comments
Min
1.62
3.0
Typ
1.8
3.3
3.3
14.4
Max
1.98
3.6
3.6
18
Unit
DVDD
AVDDx
IOVDD
VBAT 1
On-chip LDO
V
V
V
V
1.62
IOVDD Current
Normal Operation
Master clock = 256 fS
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz to 192 kHz
450
880
1.75
20
µA
µA
mA
µA
Power-Down
AVDDx Current
Normal Operation
Boost off, 4-channel ADC, DVDD internal
Boost on, 4-channel ADC, DVDD internal
Boost off, 4-channel ADC, DVDD external
Boost on, 4-channel ADC, DVDD external
14
14.5
9.6
10.1
270
mA
mA
mA
mA
µA
Power-Down
Boost Converter Current
Normal Operation
Boost on, 4-channel ADC, MICBIAS = 8.5 V, no load
Boost on, 4-channel ADC, MICBIAS = 8.5 V, 42 mA
34
168
180
mA
mA
µA
Power-Down
DVDD Current
Normal Operation
Power-Down
VBAT Current
DVDD external = 1.8 V
VBAT = 14.4 V
4.5
65
mA
µA
Normal Operation
Power-Down
575
575
625
625
µA
µA
POWER DISSIPATION
Normal Operation
AVDDx
Master clock = 256 fS, 48 kHz
DVDD internal, MICBIAS = 8.5 V at 42 mA load
PD/RST pin held low
265
9
mW
mW
Power-Down, All Supplies
1 When VBAT ≤ MICBIAS, a short to VBAT cannot be distinguished from a short to MICBIAS, and reporting a short to VBAT fault takes precedence over a short to MICBIAS fault.
Rev. A | Page 5 of 64
ADAU1977
Data Sheet
DIGITAL FILTERS SPECIFICATIONS
Table 5.
Parameter
Mode
Factor
Min
Typ
Max
Unit
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
All modes, typical at fS = 48 kHz
0.4375 × fS
21
0.015
24
27
kHz
dB
kHz
kHz
dB
0.5 × fS
0.5625 × fS
Stop-Band Attenuation
Group Delay
79
fS = 8 kHz to 96 kHz
fS = 192 kHz
22.9844/fS
479
35
µs
µs
HIGH-PASS FILTER
Cutoff Frequency
Phase Deviation
Settling Time
All modes, typical at 48 kHz
At −3 dB point
At 20 Hz
0.9375
10
Hz
Degrees
ADC DIGITAL GAIN
Gain Step Size
All modes
0
60
dB
dB
0.375
Rev. A | Page 6 of 64
Data Sheet
ADAU1977
TIMING SPECIFICATIONS
Table 6.
Limit at
Min Max Unit Description
Parameter
INPUT MASTER CLOCK (MCLK)
Duty Cycle
40
60
%
MCLKIN duty cycle; MCLKIN at 256 × fS, 384 × fS, 512 × fS, and 768 × fS
fMCLK
See Table 10
MHz MCLKIN frequency, PLL in MCLK mode
RESET
Reset Pulse
15
ns
RST low
PLL
Lock Time
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
10
ms
400
0.6
kHz
µs
µs
SCL frequency
SCL high
SCL low
1.3
0.6
µs
Setup time; relevant for repeated start condition
tSCH
0.6
µs
Hold time; after this period of time, the first clock pulse is generated
tDS
tDH
100
0
ns
Data setup time
Data hold time
tSCR
tSCF
tSDR
tSDF
300
300
300
300
1.3
ns
ns
ns
ns
µs
µs
SCL rise time
SCL fall time
SDA rise time
SDA fall time
Bus-free time; time between stop and start
Setup time for stop condition
tBFT
tSUSTO
SPI PORT
tCCPH
tCCPL
fCCLK
tCDS
0.6
35
35
10
10
10
10
40
10
30
30
30
ns
ns
CCLK high
CCLK low
MHz CCLK frequency
ns
ns
ns
ns
ns
ns
ns
ns
CIN setup to CCLK rising
tCDH
tCLS
CIN hold from CCLK rising
CLATCH setup to CCLK rising
CLATCH hold from CCLK rising
CLATCH high
tCLH
tCLPH
tCOE
COUT enable from CLATCH falling
COUT delay from CCLK falling
COUT tristate from CLATCH rising
tCOD
tCOTS
ADC SERIAL PORT
tABH
tABL
tALS
tALH
tABDD
10
10
10
5
ns
ns
ns
ns
ns
BCLK high, slave mode
BCLK low, slave mode
LRCLK setup to BCLK rising, slave mode
LRCLK hold from BCLK rising, slave mode
SDATAOUTx delay from BCLK falling
18
Rev. A | Page 7 of 64
ADAU1977
Data Sheet
tALS
LRCLK
tALH
tABH
BCLK
tABL
tABDD
SDATAOUTx
LEFT JUSTIFIED
MODE
MSB
MSB – 1
tABDD
SDATAOUTx
I S MODE
MSB
2
tABDD
SDATAOUTx
RIGHT JUSTIFIED
MODE
MSB
LSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Output Port Timing
tCLH
tCLS
tCLPH
tCOE
tCCPL
tCCPH
CLATCH
CCLK
CIN
tCDH
tCDS
tCOTS
COUT
tCOD
Figure 3. SPI Port Timing
tSCH
STOP
START
tDS
tSCH
tSDR
SDA
tSDF
tSCLH
tBFT
tSCR
SCL
tSCS
tSUSTO
tSCLL
tSCF
tDH
Figure 4. I2C Port Timing
Rev. A | Page 8 of 64
Data Sheet
ADAU1977
ABSOLUTE MAXIMUM RATINGS
Table 7.
THERMAL RESISTANCE
θJA represents thermal resistance, junction-to-ambient, and θJC
represents the thermal resistance, junction-to-case. All
characteristics are for a standard JEDEC board per JESD51.
Parameter
Rating
Analog Supply (AVDDx)
Digital Supply
−0.3 V to +3.63 V
DVDD
IOVDD
−0.3 V to +1.98 V
−0.3 V to +3.63 V
20 mA
−0.3 V to +18 V
−0.3 V to +3.63 V
−40°C to +105°C
−40°C to +125°C
−65°C to +150°C
Table 8. Thermal Resistance
Package Type
40-Lead LFCSP
θJA
θJC
Unit
Input Current (Except Supply Pins)
Analog Input Voltage (AINx, VBAT Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Ambient)
Junction Temperature Range
Storage Temperature Range
32.8
1.93
°C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 9 of 64
ADAU1977
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
AGND1
VREF
1
2
3
4
5
6
7
8
9
30 VBAT
INDICATOR
29 AGND3
28 MB_GND
27 MICBIAS
26 VBOOST_IN
25 VBOOST_OUT
24 SW
PLL_FILT
AVDD2
ADAU1977
AGND2
TOP VIEW
(Not to Scale)
PD/RST
MCLKIN
FAULT
23 SW
SA_MODE
22 PGND
DVDD 10
21 PGND
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO THE GROUND PLANE ON THE PCB.
Figure 5. Pin Configuration, 40-Lead LFCSP
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
In/Out1
Description
1
2
3
4
AGND1
VREF
PLL_FILT
AVDD2
P
O
O
P
P
I
Analog Ground.
Voltage Reference. Decouple this pin to AGNDx with 10 µF||100 nF capacitors.
PLL Loop Filter. Return this pin to AVDDx using recommended loop filter components.
Analog Power Supply. Connect this pin to analog 3.3 V supply.
Analog Ground.
5
AGND2
6
PD/RST
Power-Down Reset (Active Low).
7
8
9
MCLKIN
FAULT
SA_MODE
DVDD
DGND
IOVDD
SDATAOUT1
SDATAOUT2
LRCLK
I
O
I
Master Clock Input.
Fault Output. Programmable logic output.
Standalone Mode. Connect this pin to IOVDD using a 10 kΩ pull-up resistor for standalone mode.
1.8 V Digital Power Supply Output. Decouple this pin to DGND with a 0.1 µF capacitor.
Digital Ground.
Digital Input and Output Power Supply. Connect this pin to a supply in the range of 1.8 V to 3.3 V.
ADC Serial Data Output Pair 1.
ADC Serial Data Output Pair 2.
Frame Clock for the ADC Serial Port.
Bit Clock for the ADC Serial Port.
Serial Data Output I2C/Control Data Output (SPI).
Serial Clock Input I2C/Control Clock Input (SPI).
Chip Address Bit 0 Setting I2C/Chip Select Input for Control Data (SPI).
Chip Address Bit 1 Setting I2C/Control Data Input (SPI).
Power Ground Boost Converter.
Power Ground Boost Converter.
Inductor Switching Terminal.
Inductor Switching Terminal.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
O
P
P
O
O
I/O
I/O
I/O
I
BCLK
SDA/COUT
SCL/CCLK
ADDR0/CLATCH
ADDR1/CIN
PGND
PGND
SW
SW
VBOOST_OUT
VBOOST_IN
MICBIAS
MB_GND
I
I
P
P
I
I
O
I
Boost Converter Output. Decouple this pin to PGND with a 10 µF capacitor.
MICBIAS Regulator Input. Connect this pin to VBOOST_OUT (Pin 25).
Microphone Bias Output. Decouple this pin to AGNDx using a 10 µF capacitor.
Analog Return Ground for the Microphone Bias Regulator. Connect this pin directly to AGNDx
for best noise performance.
O
P
29
30
AGND3
VBAT
P
I
Analog Ground.
Voltage Sense for Diagnostics. Connect this pin to a load dump suppressed battery voltage.
Decouple this to AGNDx using a 0.1 µF capacitor.
Rev. A | Page 10 of 64
Data Sheet
ADAU1977
Pin No.
31
32
33
34
35
36
37
38
Mnemonic
In/Out1
Description
AVDD3
AIN1N
AIN1P
AIN2N
AIN2P
AIN3N
AIN3P
AIN4N
AIN4P
AVDD1
EP
P
I
I
I
I
I
I
I
I
Analog Power Supply. Connect this pin to an analog 3.3 V supply.
Analog Input Channel 1 Inverting Input.
Analog Input Channel 1 Noninverting Input.
Analog Input Channel 2 Inverting Input.
Analog Input Channel 2 Noninverting Input.
Analog Input Channel 3 Inverting Input.
Analog Input Channel 3 Noninverting Input.
Analog Input Channel 4 Inverting Input.
Analog Input Channel 4 Noninverting Input.
Analog Power Supply. Connect this pin to an analog 3.3 V supply.
39
40
P
Exposed Pad. The exposed pad must be connected to the ground plane on the printed circuit
board (PCB).
1 I = input, O = output, I/O = input/output, and P= power.
Rev. A | Page 11 of 64
ADAU1977
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
–10
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
20k
100k
1M
10M 20M
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 6. Fast Fourier Transform, 2 mV Differential Input at fS = 48 kHz
Figure 9. CMRR Differential Input, Referenced to 1 V Differential Input
0
–10
0
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 7. Fast Fourier Transform, −1 dBFS Differential Input
Figure 10. Fast Fourier Transform, No Input
0
0.10
0.08
0.06
0.04
0.02
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–0.02
–0.04
–0.06
–0.08
–0.10
–100
–110
–120
–130
–140
–150
–160
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
FREQUENCY (Hz)
12
0
2
4
6
8
10
INPUT AMPLITUDE (V rms)
Figure 8. THD + N vs. Input Amplitude
Figure 11. ADC Pass-Band Ripple at fS = 48 kHz
Rev. A | Page 12 of 64
Data Sheet
ADAU1977
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5000 10000 15000 20000 25000 30000 35000 40000
FREQUENCY (Hz)
Figure 12. ADC Filter Stop-Band Response at fS = 48 kHz
Rev. A | Page 13 of 64
ADAU1977
Data Sheet
THEORY OF OPERATION
the part enables the DVDD regulator. However, the internal ADC
OVERVIEW
POR
and digital core reset is controlled by the internal
signal
The ADAU1977 incorporates four high performance ADCs
with an integrated boost converter for microphone bias, the
associated microphone diagnostics for fault detection, and a
phase-locked loop circuit for generating the necessary on-chip
clock signals.
(power-on reset) circuit, which monitors the DVDD level.
Therefore, the device does not come out of a reset until DVDD
POR
reaches 1.2 V and the
signal is released. The DVDD settling
time depends on the charge-up time for the external capacitors
and on the AVDDx ramp-up time.
POWER SUPPLY AND VOLTAGE REFERENCE
The internal POR circuit is provided with hysteresis to ensure
that a reset of the part is not initiated by an instantaneous glitch
The ADAU1977 requires a single 3.3 V power supply. Separate
power supply input pins are provided for the analog and boost
converter. These pins should be decoupled to AGND with 100 nF
ceramic chip capacitors placed as close as possible to the pins to
minimize noise pickup. A bulk aluminum electrolytic capacitor
of at least 10 μF must be provided on the same PCB as the ADC.
It is important that the analog supply be as clean as possible for
best performance.
RST
on DVDD. The typical trip points are 1.2 V with
high and
low. This ensures that the core is not
reset until the DVDD level falls below the 0.6 V trip point.
PD RST
pin is pulled high, the internal regulator
RST
0.6 V ( 20%) with
As soon as the
/
starts charging up the CEXT on the DVDD pin. The DVDD charge-
up time is based on the output resistance of the regulator and
the external decoupling capacitor. The time constant can be
calculated as
The supply voltage for the digital core (DVDD) is generated
using an internal low dropout regulator. The typical DVDD
output is 1.8 V and must be decoupled using a 100 nF ceramic
capacitor and a 10 µF capacitor. Place the 100 nF ceramic
capacitor as close as possible to the DVDD pin.
tC = ROUT × CEXT (ROUT = 20 Ω typical)
For example, if CEXT is 10 µF, then tC is 200 µs and is the time to
reach the DVDD voltage, within 63.6%.
The voltage reference for the analog blocks is generated
internally and output at the VREF pin (Pin 2). The typical
voltage at the pin is 1.5 V with an AVDDx of 3.3 V.
The POR circuit releases an internal reset of the core when DVDD
reaches 1.2 V (see Figure 13). Therefore, it is recommended to
wait for at least the tC period to elapse before sending I2C or SPI
control signals.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the IOVDD supply. The IOVDD
can be in the range of 1.8 V to 3.3 V. The IOVDD pin must
be decoupled with a 100 nF capacitor placed as close to the
IOVDD pin as possible. It is recommended to connect the
AGND, DGND, PGND, and exposed pad to a single GND
plane on the PCB for best performance.
AVDDx
PD/RST
1.2V
tRESET
The ADC internal voltage reference is output from the VREF pin
and should be decoupled using a 100 nF ceramic capacitor in
parallel with a 10 μF capacitor. The VREF pin has limited
current capability. The voltage reference is used as a reference to
the ADC; therefore, it is recommended not to draw current
from this pin for external circuits. When using this reference,
use a noninverting amplifier buffer to provide a reference to
other circuits in the application.
tC
DVDD (1.8V)
tD
0.48V
POR
Figure 13. Power-On Reset Timing
When applying a hardware reset to the part by pulling the
In reset mode, the VREF pin is disabled to save power and is
PD RST
/
pin (Pin 6) low and then high, there are certain time
RST
enabled only when the
pin is pulled high.
RST
restrictions. During the
low pulse period, the DVDD starts
POWER-ON RESET SEQUENCE
discharging. The discharge time constant is decided by the internal
resistance of the regulator and CEXT. The time required for DVDD
to fall from 1.8 V to 0.48 V (0.6 V − 20%) can be estimated using
the following equation:
The ADAU1977 requires that a single 3.3 V power supply be
provided externally at the AVDDx pin. The part internally generates
DVDD (1.8 V), which is used for the digital core of the ADC.
The DVDD supply output pin (Pin 10) is provided to connect
the decoupling capacitors to DGND. The typical recommended
values for the decoupling capacitors are 100 nF in parallel with
10 µF. During a reset, the DVDD regulator is disabled to reduce
tD = 1.32 × RINT × CEXT
where RINT = 64 kΩ typical. (RINT can vary due to process by 20%.)
For example, if CEXT is 10 µF, then tD is 0.845 sec.
PD RST
power consumption. After the
/
pin (Pin 6) is pulled high,
Rev. A | Page 14 of 64
Data Sheet
ADAU1977
Depending on CEXT, tD may vary and in turn decide the minimum
The PLL_LOCK bit (Bit 7) of Register 0x01 indicates the lock
status of the PLL. It is recommended that after initial power-up
the PLL lock status be read to ensure that the PLL outputs the
correct frequency before unmuting the audio outputs.
RST
RST
hold period for the
for the tD time period to initialize the core properly.
RST
pulse. The
pulse must be held low
The required
low pulse period can be reduced by adding a
resistor across CEXT. The new tD value can then be calculated as
Table 10. Required Input MCLK for Common Sample Rates
MCS
(Bits[2:0])
Frequency Multi- MCLKIN Frequency
tD = 1.32 × REQ × CEXT
fS (kHz) plication Ratio
(MHz)
where REQ = 64 kΩ || REXT
.
000
001
010
011
100
000
001
010
011
100
000
001
010
011
100
000
001
010
011
100
000
001
010
011
100
32
32
32
32
128 × fS
256 × fS
384 × fS
512 × fS
768 × fS
128 × fS
256 × fS
384 × fS
512 × fS
768 × fS
128 × fS
256 × fS
384 × fS
512 × fS
768 × fS
64 × fS
4.096
8.192
The resistor ensures that DVDD not only discharges quickly during
a reset or an AVDDx power loss but also resets the internal blocks
correctly. Note that some power loss in this resistor is to be
expected because the resistor constantly draws current from
DVDD. The typical value for CEXT is 10 µF and for REXT is 3 kΩ.
This results in a time constant of
12.288
16.384
24.576
5.6448
11.2896
16.9344
22.5792
33.8688
6.144
12.288
18.432
24.576
36.864
6.144
32
44.1
44.1
44.1
44.1
44.1
48
48
48
48
48
tD = 1.32 × REQ × CEXT = 37.8 ms
where REQ = 2.866 kΩ (64 kΩ || 3 kΩ).
Using this equation at a set CEXT value, the REXT can be
RST
calculated for a desired
pulse period.
There is also a software reset register (S_RST, Bit 7 of Register 0x00)
available that can be used to reset the part, but it must be noted
that during an AVDDx power loss, the software reset may not
ensure proper initialization because DVDD may not be stable.
+3.3V
96
96
96
96
128 × fS
192 × fS
256 × fS
384 × fS
32 × fS
12.288
18.432
24.576
36.864
6.144
AVDD1 AVDD3 AVDD2
96
192
192
192
192
192
DVDD
64 × fS
96 × fS
128 × fS
192 × fS
12.288
18.432
24.576
36.864
3.3V TO 1.8V
REGULATOR
C
0.1µF
C
10µF
MLCC X7R
R
EXT
3kΩ
EXT
TO INTERNAL
BLOCKS
+1.8V OR +3.3V
IOVDD
The PLL can accept the audio frame clock (sample rate clock) as
input, but the serial port must be configured as a slave and the
frame clock must be fed to the part from the master. It is strongly
recommended that the PLL be disabled, reprogrammed with the
new setting, and then reenabled. A lock bit is provided that can be
polled via the I2C to check whether the PLL has acquired lock.
ADAU1977
C
0.1µF
Figure 14. DVDD Regulator Output Connections
PLL AND CLOCK
The PLL requires an external filter, which is connected at the
PLL_FILT pin (Pin 3). The recommended PLL filter circuit for
MCLK or LRCLK mode is shown in Figure 15. Using NPO
capacitors is recommended for temperature stability. Place the
filter components close to the device for best performance.
The ADAU1977 has a built-in analog PLL to provide a jitter-
free master clock to the internal ADC. The PLL must be
programmed for the appropriate input clock frequency. The
PLL Control Register 0x01 is used for setting the PLL.
The CLK_S bit (Bit 4) of Register 0x01 is used for setting the
clock source for the PLL. The clock source can be either the
MCLKIN pin or the LRCLK pin (slave mode). In LRCLK mode,
the PLL can support sample rates between 32 kHz and 192 kHz.
AVDDx
AVDDx
39nF
5.6nF
2.2nF
390pF
4.87kΩ
1kΩ
PLL_LF
PLL_LF
In MCLK input mode, the MCS bits (Bits[2:0] of Register 0x01)
must be set to the desired input clock frequency for the MCLKIN
pin. Table 10 shows the input MCLK required for the most
common sample rates and the MCS bit settings.
LRCLK MODE
MCLK MODE
Figure 15. PLL Filter
Rev. A | Page 15 of 64
ADAU1977
Data Sheet
and if it exceeds the set current threshold for 1.2 ms, the boost
converter shuts down. The fault condition is recorded into
Register 0x02 and asserts the fault interrupt pin. This condi
tion is cleared after reading the BOOST_OV bit (Bit 2) or
the BOOST_OC bit (Bit 0) in Register 0x02. The overcurrent
protection bit, OC_EN (Bit 1), or the overvoltage protection bit,
OV_EN (Bit 3), is on by default, and it is recommended not to
disable the bit.
DC-TO-DC BOOST CONVERTER
The boost converter generates a supply voltage for the
microphone bias circuit from a fixed 3.3 V supply. The boost
converter output voltage is programmable using Register 0x03.
The boost converter output voltage is approximately 1 V above
the set microphone bias voltage. The boost converter uses the
clock from the PLL, and the switching frequency is dependent
on the sample rate of the ADC. The FS_RATE bits (Bits[6:5] of
Register 0x02) must be set to the desired sample rate. The boost
converter switching frequency can be selected to be 1.5 MHz or
3 MHz using Bit 4 of Register 0x02. For the 1.5 MHz switching
frequency, the recommended value for the inductor is 4.7 µH,
whereas for the 3 MHz switching frequency, the recommended
value for the inductor is 2.2 µH.
Each protection circuit has two modes for recovery after a fault
event: autorecovery and manual recovery. The recovery mode
can be selected using Bit 0 of Register 0x03. The autorecovery
mode attempts to enable the boost converter after a set recovery
time, typically 20 ms. The manual recovery mode enables the boost
converter only if the user writes 1 to the MRCV bit (Bit 1). If the
fault persists, the boost converter remains in shutdown mode
until the fault is cleared.
Table 12 lists the typical switching frequency based on the
sample rates.
The boost converter is capable of supplying the 42 mA of total
output current at the MICBIAS output. The boost converter has
overcurrent protection at the input; the threshold is around
900 mA peak. Ensure that the 3.3 V power supply feeding the
boost converter has built-in overcurrent protection because there is
no protection internal to ADAU1977 for a short circuit to any of
the ground pins (AGND/DGND/PGND) at the VBOOST_OUT
or VBOOST_IN pin.
Inductor Selection
For the boost converter to operate efficiently, the inductor selection
is critical. The two most important parameters for the inductor
are the saturation current rating and the dc resistance. The recom-
mended saturation rating for the inductor must be >1 A. The dc
resistance affects the efficiency of the boost converter. Assuming
that the board trace resistances are negligible for 80% efficiency,
the dc resistance of the inductor should be less than 50 mΩ.
By default, the boost converter is disabled on power-up to allow
the flexibility of connecting an external voltage source at the
VBOOST_IN pin to power the microphone bias circuit. The boost
converter can be enabled by using the BOOST_EN bit (Bit 2 of
Register 0x03).
Table 11 lists some of the recommended inductors for the
application.
Table 11. Recommended Inductors1
Value
2.2 µH
4.7 µH
Manufacturer
Würth Elektronik
Würth Elektronik
Manufacturer Part Number
Capacitor Selection
7440430022
7440530047
The boost converter output is available at the VBOOST_OUT pin
(Pin 25) and must be decoupled to PGND using a 10 µF ceramic
capacitor to remove the ripple at the switching frequency. The
capacitor must have low ESR and good temperature stability.
The MLCC X7R/NPO dielectric type with 25 V is recommended.
Care must be taken to place this capacitor as close as possible to
the VBOOST_OUT pin (Pin 25).
1 Check with the manufacturer for the appropriate temperature ratings for a
given application.
The boost converter has a soft start feature that prevents inrush
current from the input source.
The boost converter has built-in overcurrent and overtemperature
protection. The input current to the boost converter is monitored
Table 12. Typical Switching Frequency Based on the Sample Rates
Boost Converter Switching Frequency
Base Sample Rate (kHz) Sample Rates (kHz)
Inductor = 2.2 µH
(1024/12) × fS
(1024/16) × fS
(1024/16) × fS
Inductor = 4.7 µH
(1024/22) × fS
(1024/30) × fS
(1024/32) × fS
32
8/16/32/64
44.1
48
11.025/22.05/44.1/88.2/176.4
12/24/48/96/192
Rev. A | Page 16 of 64
Data Sheet
ADAU1977
The block diagram shown in Figure 16 represents the typical
input circuit.
MICROPHONE BIAS
The microphone bias is generated by the input voltage at the
VBOOST_IN pin (Pin 26) via a linear regulator to ensure low
noise performance and to reject the high frequency noise from
the boost converter. If the internal boost converter output is
used, the VBOOST_OUT pin (Pin 25) must be connected to
the VBOOST_IN pin (Pin 26). If an external supply is used for
the microphone bias, the supply can be fed at the VBOOST_IN
pin (Pin 26); in this case, leave the VBOOST_OUT pin (Pin 25)
open. The microphone bias voltage is programmable from 5 V
to 9 V by using the MB_VOLTS bits (Bits[7:4] of Register 0x03).
The microphone bias output voltage is available at the MICBIAS pin
(Pin 27). This pin can be decoupled to AGND using a maximum of
up to a 10 µF capacitor with an ESR of at least 1 Ω. For higher
value capacitors, especially those above 1 nF, the ESR of the capa-
citor should be ≥ 1 Ω to ensure the stability of the microphone
bias regulator. Register 0x03 can be used to enable the microphone
bias. Table 12 lists the switching frequency of the boost converter
based on the inductor value and common sample rates.
In most audio applications, the dc content of the signal is removed
by using a coupling capacitor. However, the ADAU1977 consists
of a unique input structure that allows direct coupling of the
input signal, eliminating the need for using a large coupling
capacitor at the input. Each input has a fixed 14 dB attenuator
connected to AGND for accommodating a 10 V rms differential
input. The typical input resistance is approximately 26 kΩ from
each input to AGND.
In dc-coupled applications, if the VCM at AINxP and AINxN is
the same, the dc content in the ADC output is close to 0. If the
input pins are presented with different common-mode dc levels,
the difference between the two levels appears at the ADC output
and can be removed by enabling the high-pass filter.
The high-pass filter has a 1.4 Hz, 6 dB per octave cutoff at a
48 kHz sample rate. The cutoff frequency scales directly with
the sample frequency. However, care is required in dc-coupled
applications to ensure that the common-mode dc voltage does
not exceed the specified limit. The common-mode loop can
accommodate a common-mode dc voltage from 0 V to 7 V. The
input required for the full-scale ADC output (0 dBFS) is typically
10 V rms differential.
ANALOG INPUTS
The ADAU1977 has four differential analog inputs. The ADCs
can accommodate both dc- and ac-coupled input signals.
R
V
2R
2R
R
R
X
AINxP
AINxN
R
V
REF
V
Y
R
R
V
V
V
= V INPUT DIFFERENTIAL
ID
= V
= V
AT AINx+
AT AINx–
ICM+
ICM–
CM
CM
Figure 16. Analog Input Block
Rev. A | Page 17 of 64
ADAU1977
Data Sheet
Line Inputs
Line Input Unbalanced or Single-Ended Pseudo Differential
AC-Coupled Case
This section describes some of the possible ways to connect the
ADAU1977 for line level inputs.
For a single-ended application, the signal swing is reduced by half
because only one input is used for the signal, and the other input is
connected to 0 V. As a result, the input signal capability is reduced
to 5 V rms in a single-ended application. With a common-mode dc
voltage of 7.2 V, the signal can swing between (7.2 V + 7.07 V)
= +14.27 V p-p and (7.2 V − 7 V) = 0.13 V. Therefore, this
results in approximately a 14.14 V p-p differential signal swing
and measures around −6.16 dBFS (ac only with dc high-pass
filter) at the ADC output. See Figure 19.
Line Input Balanced or Differential Input DC-Coupled Case
For example, in the case of a typical power amplifier for an auto-
mobile, the output can swing around 10 V rms differential with
approximately 7.2 V common-mode dc input voltage (assuming
a 14.4 V battery and bridge-tied load connection). The signal at
each input pin has a 5 V rms or 14.14 V p-p signal swing. With
a common-mode dc voltage of 7.2 V, the signal can swing between
(7.2 V + 7.07 V) = +14.27 V p-p and (7 V − 7.07 V) = 0.13 V at
each input. Therefore, this results in approximately a 28.54 V p-p
differential signal swing and measures around −0.16 dBFS (ac
only with dc high-pass filter) at the ADC output. See Figure 17.
The values of the resistors (R1/R2) and capacitors (C1/C2) are
similar to those for the balanced ac-coupled case described in
the Line Input Balanced or Differential Input AC-Coupled Case
section.
Line Input Balanced or Differential Input AC-Coupled Case
Line Input Unbalanced or Single-Ended AC-Coupled Case
For an amplifier output case with ac coupling, refer to Figure 18
for information about connecting the line level inputs to the
ADAU1977. In this case, the AINxP/AINxN pins must be
pulled up to the required common-mode level using the
resistors on MICBIAS. The VCM must be such that the input
never swings below a ground. In other words, if the input signal
is 14 V p-p, the VCM must be around 14 V/2 = 7 V to ensure that
the signal never swings below a ground. The microphone bias
can provide the required clean reference for generating the VCM
The R1 value can be calculated as follows:
R1 = Rin1977 (MB − VCM)/VCM
For a single-ended application, the signal swing is reduced by half
because only one input is used for the signal, and the other input is
connected to 0 V. As a result, the input signal capability is reduced
to 5 V rms in a single-ended application. With a common-mode dc
voltage of 7.2 V, the signal can swing between (7.2 V + 7.07 V) =
+14.27 V p-p and (7.2 V − 7 V) = 0.13 V. Therefore, this results
in approximately a 14.14 V p-p differential signal swing and
measures around −6.16 dBFS (ac only with dc high-pass filter)
at the ADC output. The difference in the common-mode dc
voltage between the positive and negative input (7.2 V) would
appear at the ADC output if the signal was not high-pass filtered.
See Figure 20.
.
where:
V
CM is the peak-to-peak input swing divided by 2.
The values of the resistor (R1) and capacitor (C1) are similar to
those for the balanced ac-coupled case described in the Line
Input Balanced or Differential Input AC-Coupled Case section.
MB = 8.5 V.
Rin1977 is the single-ended input resistance (see Table 1).
However, in this case the equivalent input resistance of AINxP/
AINxN is reduced and can be calculated as R1 || Rin1977
Input Resistance = R1 × Rin1977/(R1 + Rin1977
where Rin1977 is the single-ended value from Table 1.
.
)
The C1 and C2 values can be determined for the required low
frequency cutoff using the following equation:
C1 or C2 = 1/(2 × π × fC × Input Resistance)
Rev. A | Page 18 of 64
Data Sheet
ADAU1977
TYPICAL AUDIO POWER
AMPLIFIER OUTPUT
AINx+
AINx–
ATTENUATOR
14dB
ADAU1977
V
V
= 10V rms AC
= 7V DC
DIFF
CM
Figure 17. Connecting the Line Level Inputs—Differential DC-Coupled Case
C3
MICBIAS
TYPICAL AUDIO POWER
AMPLIFIER OUTPUT
R1
R2
C1
AINx+
AINx–
ATTENUATOR
14dB
C2
ADAU1977
V
f = 10V RMS AC
DIF
Figure 18. Connecting the Line Level Inputs—Differential AC-Coupled Case
C3
MICBIAS
TYPICAL AUDIO POWER
AMPLIFIER OUTPUT
R1
R2
C1
AINx+
AINx–
ATTENUATOR
14dB
C2
ADAU1977
V
= 5V rms AC
IN
Figure 19. Connecting the Line Level Inputs—Pseudo Differential AC-Coupled Case
C3
MICBIAS
TYPICAL AUDIO POWER
AMPLIFIER OUTPUT
R1
C1
AINx+
AINx–
ATTENUATOR
14dB
ADAU1977
V
= 5V rms AC
IN
Figure 20. Connecting the Line Level Inputs—Single-Ended AC-Coupled Case
Rev. A | Page 19 of 64
ADAU1977
Data Sheet
Microphone Inputs
level of 2/3 × MICBIAS on the AINxP and 1/3 × MICBIAS on
the AINxN pins, this results in around −14 dBFS (ac only with
dc high-pass filter) at the ADC output because the input is 14 dB
below the full-scale input of 10 V rms differential. See Figure 21.
This section describes some ways to connect the ADAU1977 for
microphone input applications. The MICBIAS voltage and the
bias resistor value depend on the ECM selected. The ADAU1977
can provide the MICBIAS from 5 V up to 9 V in 0.5 V steps. In
an application requiring multiple microphones, care must be
taken not to exceed the MICBIAS output current rating.
ECM Pseudo Differential Input AC-Coupled Case
For a typical MEMS ECM module, the output signal swing is
low. With a typical 3.3 V supply, the ECM module can output a
2 V rms differential signal. The signal at the input pin has a 1 V rms
or 2.8 V p-p signal swing. For this application, it is recommended
to bias the input pins using resistors to 7 V dc, similar to the
case described in the Line Input Unbalanced or Single-Ended
Pseudo Differential AC-Coupled Case section. See Figure 22.
ECM Balanced or Differential Input DC-Coupled Case
For example, in a typical ECM, the output signal swing depends
on the MICBIAS voltage. With a typical 8.5 V supply, the ECM can
output a 2 V rms differential signal. The signal at each input pin
has a 1 V rms or 2.8 V p-p signal swing. With a common-mode dc
MICBIAS
TYPICAL
R
ECM MODULE
MICROPHONE
AINx+
AINx–
ATTENUATOR
14dB
ADAU1977
R
V
V
V
= 2V rms AC DIFFERENTIAL
IN
≈ 2/3 × MICBIAS
≈ 1/3 × MICBIAS
CM+
CM–
R = TYPICAL 300Ω TO 500Ω
NOTES
1. THE DIAGNOSTICS FEATURE IS AVAILABLE.
Figure 21. Connecting the Microphone Inputs—Differential Input DC-Coupled Case
TYPICAL ECM
WITH PREAMP
MODULE
C3
MICBIAS
V
DD
R1
R2
AINx+
ATTENUATOR
14dB
AINx–
ADAU1977
V
= 5V rms AC
MAX
NOTES
1. THE DIAGNOSTICS FEATURE IS NOT AVAILABLE.
Figure 22. Connecting the Microphone Inputs—Pseudo Differential Input AC-Coupled Case
Rev. A | Page 20 of 64
Data Sheet
ADAU1977
is enabled and the microphone is connected as recommended
in the appropriate application circuit (see Figure 21).
ADC
The ADAU1977 contains four Δ-Σ ADC channels configured
as two stereo pairs with configurable differential/single-ended
inputs. The ADC can operate at a nominal sample rate of 32 kHz
up to 192 kHz. The ADCs include on-board digital antialiasing
filters with 79 dB stop-band attenuation and linear phase response.
Digital outputs are supplied through two serial data output pins
(one for each stereo pair) and a common frame clock (LRCLK)
and bit clock (BCLK). Alternatively, one of the TDM modes can
be used to support up to 16 channels on a single TDM data line.
Diagnostics Reporting
The diagnostics status is reported individually for each channel
in Register 0x11 through Register 0x14. The faults listed in
Table 13 are reported on each input pin.
Table 13. Faults Reported
Fault
AINxP AINxN
Short to Battery
Short to MICBIAS
Short to Ground
Short Between Positive and Negative Inputs
Open Input
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
With smaller amplitude input signals, a 10-bit programmable
digital gain compensation for an individual channel is provided
to scale up the output word to full scale. Care must be taken to
avoid overcompensation (large gain compensation), which leads
to clipping and THD degradation in the ADC.
Diagnostics Adjustments
The ADCs also have a dc-offset calibration algorithm to null
the systematic dc offset of the ADC. This feature is useful for dc
measurement applications.
Short Circuit to Battery Supply
When an input terminal is shorted to the battery, the voltage at
the terminal approaches the battery voltage. Any voltage higher
than the set threshold is reported as a fault. The threshold can
be set using the SHT_B_TRIP bits, Bits[1:0] of Register 0x17
(see Table 14).
ADC SUMMING MODES
The four ADCs can be grouped into either a single stereo ADC
or a single mono ADC to increase the signal-to-noise ratio (SNR)
for the application. Two options are available: one option for
summing two channels of the ADC and another option for
summing all four channels of the ADC. Summing is performed
in the digital block.
Table 14. Setting the Short to Battery Threshold
SHT_B_TRIP
(Register 0x17, Bits[1:0])
Short to Battery Threshold
0.95 × VBAT
0.9 × VBAT
0.85 × VBAT
0.975 × VBAT
00
01
10
11
2-Channel Summing Mode
When the SUM_MODE Bits (Bits[7:6] of Register 0x0E) are
set to 01, the Channel 1 and Channel 2 ADC data are combined
and output from the SDATAOUT1 pin. Similarly, the Channel 3
and Channel 4 ADC data are combined and output from the
SDATAOUT2 pin. As a result, the SNR improves by 3 dB. For
this mode, both Channel 1 and Channel 2 must be connected to
the same input signal source. Similarly, Channel 3 and Channel 4
must be connected to the same input signal source.
Short Circuit to MICBIAS
This feature is supported only on the AINxP terminal. When
an AINxP terminal is shorted to MICBIAS, the voltage at the
AINxP terminal approaches the MICBIAS voltage. Any voltage
higher than the set threshold is reported as a fault. The threshold
can be set using the SHT_M_TRIP bits, Bits[5:4] of Register 0x17
(see Table 15).
4-Channel Summing Mode
When the SUM_MODE Bits (Bits[7:6] of Register 0x0E) are set
to 10, the Channel 1 through Channel 4 ADC data are combined
and output from the SDATAOUT1 pin. As a result, the SNR
improves by 6 dB. For this mode, all four channels must be
connected to the same input signal source.
Table 15. Setting the Short to MICBIAS Threshold
SHT_M_TRIP
(Register 0x17, Bits[5:4])
Short to MICBIAS Threshold
0.95 × MICBIAS
0.9 × MICBIAS
0.85 × MICBIAS
0.975 × MICBIAS
00
01
10
11
DIAGNOSTICS
The diagnostics block monitors the input pins in real time and
reports a fault as an interrupt signal on the FAULT pin (Pin 8),
which triggers sending an interrupt request to an external
controller. The diagnostics status registers (Register 0x11 through
Register 0x14) for Channel 1 through Channel 4 are also updated.
Refer to the register map table (Table 25) and the register details
tables (Table 42, Table 43, Table 44, and Table 45) for more infor-
mation about the diagnostics register content. The diagnostics
can be enabled or disabled for each channel using Bits[3:0] of
Register 0x10. The diagnostics are provided only when MICBIAS
Short Circuit to Ground
When an input terminal is shorted to ground, the terminal
voltage reaches close to 0 V. Any voltage lower than the set
threshold is reported as a fault. The threshold is referenced to
VREF and, therefore, scales with the voltage at the VREF pin.
Rev. A | Page 21 of 64
ADAU1977
Data Sheet
The threshold can be set using the SHT_G_TRIP bits, Bits[3:2]
of Register 0x17 (see Table 16).
reported. The fault cannot indicate which terminal is open
circuited because any terminal that is open circuited pulls AINxP
to MICBIAS and AINxN to a common ground.
Table 16.
SHT_G_TRIP
FAULT Pin
The FAULT pin is an output pin that can be programmed to be
active high or active low logic using the IRQ_POL bit (Bit 4 of
Register 0x15). In addition, the FAULT pin can be set using the
IRQ_DRIVE bit (Bit 5 of Register 0x15) to drive always or to drive
only during a fault and is otherwise set to high-Z. The fault status
is registered in the IRQ_RESET bit (Bit 6 of Register 0x15). The
IRQ_RESET bit is a latched bit and is set in the event of a fault
and cleared only after the fault status bit is read.
(Register 0x17, Bits[3:2])
Short to Ground Threshold
0.2 × VREF
0.133 × VREF
0.1 × VREF
0.266 × VREF
00
01
10
11
Microphone Terminal Short Circuited
When both input terminals are shorted, both the AINxP and
AINxN input terminals are at the same voltage—around
MICBIAS/2. Any voltage between the set thresholds is reported
as a fault. The upper and lower threshold voltages can be set
using the SHT_T_TRIP bits, Bits[7:6] of Register 0x17 (see
Table 17).
Fault Timeout
To prevent the false triggering of a fault event, the fault timeout
adjust bits (Bits[5:4] of Register 0x18) are provided. These bits
can be used to set the time that the fault needs to persist before
being reported. The timeout can be set to 0 ms, 50 ms, 100 ms,
or 150 ms using the FAULT_TO bits (Bits[5:4] of Register 0x18).
The default value is 100 ms. A fault is recorded only if the
condition persists for more than a set minimum timeout.
The following equations can be used to calculate the upper and
lower thresholds:
Upper Threshold = MICBIAS(0.5 + x)
Lower Threshold = MICBIAS(0.5 − x)
Fault Masking
The faults can be masked to prevent triggering an interrupt
on the FAULT pin. Fault masking can be set using Bits[6:0] of
Register 0x16. The mask can be set for the faults listed in Table 18.
where x can be set using the SHT_T_TRIP bits, Bits[7:6] of
Register 0x17 (see Table 17).
Table 17.
SHT_T_TRIP
(Register 0x17, Bits [7:6])
Table 18. Fault Masking
Fault
Short to Battery
Short to MICBIAS
Short to Ground
Short Between Positive and Negative Inputs
Open Input
AINxP AINxN
x
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
00
01
10
11
0.035
0.017
0.071
Reserved
Microphone Terminals Open
When a fault mask bit is set, it is applied to all the channels.
There is no individual fault mask available per channel using this
bit. To mask individual channels, use the DIAG_MASK[4:1] bits
(Bits[3:0] of Register 0x15).
In the event that any of the input terminals becomes open
circuited, AINxP is pulled to MICBIAS and AINxN is pulled to
a common ground. When the AINxP terminal is at a voltage
that is higher than the short to the MICBIAS threshold (set
using Bits[5:4] of Register 0x17) and the AINxN terminal
voltage is at a voltage that is less than the short to the ground
threshold (set using Bits[3:2] of Register 0x17), a fault is
Diagnostics Sequence
The sequence shown in Figure 23 is recommended for reading
the faults reported by diagnostics.
NORMAL
NORMAL
AINx+/
AINx–
FAULT EVENT
FAULT
FAULT
FAULT
FAULT
FAULT
TIMEOUT
TIMEOUT
TIMEOUT
TIMEOUT
TIMEOUT
IRQ TO
SYSTEM MICRO
IRQ TO
SYSTEM MICRO
IRQ TO
SYSTEM MICRO
IRQ TO
SYSTEM MICRO
IRQ TO
SYSTEM MICRO
FAULT
PIN
2
2
2
2
2
2
I C SEQUENCE
I C SEQUENCE
I C SEQUENCE
I C SEQUENCE
I C SEQUENCE
I C
Figure 23. Diagnostics Sequence
Rev. A | Page 22 of 64
Data Sheet
ADAU1977
7. If after the fifth reading, the diagnostics still report the
In the event of a fault on an input pin, the FAULT pin goes low or
high depending on the setting of the IRQ_POL bit in Register 0x15
to send an interrupt request to the system microcontroller. The
system microcontroller responds to the interrupt request by
communicating with the ADAU1977 via the I2C.
presence of a fault, the fault exists on the respective input
and must be attended to.
SERIAL AUDIO DATA OUTPUT PORTS—DATA
FORMAT
The following is the typical interrupt service routine:
The serial audio port comprises four pins: BCLK, LRCLK,
SDATAOUT1, and SDATAOUT2. The ADAU1977 ADC outputs
are available on the SDATAOUT1 and SDATAOUT2 pins in
serial format. The BCLK and LRCLK pins serve as the bit clock
and frame clock, respectively. The port can be operated as master
or slave and can be set either in stereo mode (2-channel mode)
or in TDM multichannel mode. The supported popular audio
formats are I2S, left justified (LJ), right justified (RJ).
1. An interrupt request is generated from the ADAU1977 to
the system microcontroller.
2. Read Register 0x11 through Register 0x14. (It is recom-
mended to read all four diagnostics status registers—
Register 0x11 through Register 0x14—in one sequence.
Reading the registers as a single read may not report the
status accurately.)
3. Write Register 0x15, Bit 6 (the IRQ_RESET bit).
4. Wait for the fault timeout period to expire.
5. If the fault was temporary and did not persist, the interrupt
service ends and the intermittent fault is ignored. If the
fault persists, another interrupt request is generated from
the ADAU1977, and the user should continue on to Step 6.
6. Repeat Step 2 through Step 4 four times.
Stereo Mode
In 2-channel or stereo mode, the SDATAOUT1 outputs ADC
data for Channel 1 and Channel 2, and the SDATOUT2 outputs
ADC data for Channel 3 and Channel 4. Figure 24 through
Figure 28 show the supported audio formats.
BCLK
LRCLK
SDATAOUT1
CHANNEL 1
(I2S MODE)
CHANNEL 2
8 TO 32 BCLKs
8 TO 32 BCLKs
CHANNEL 4
SDATAOUT2
CHANNEL 3
(I2S MODE)
NOTES
1. SAI = 0.
2. SDATA_FMT = 0 (I2S).
Figure 24. I2S Audio Format
BCLK
LRCLK
SDATAOUT1
(LJ MODE)
CHANNEL 1
CHANNEL 3
CHANNEL 2
CHANNEL 4
SDATAOUT2
(LJ MODE)
NOTES
1. SDATA_FMT = 1 (LJ).
Figure 25. LJ Audio Format
BCLK
LRCLK
SDATAOUT1
(RJ MODE)
CHANNEL 1
CHANNEL 3
CHANNEL 2
CHANNEL 4
SDATAOUT2
(RJ MODE)
NOTES
1. SDATA_FMT = 2 (RJ, 24-BIT).
Figure 26. RJ Audio Format
Rev. A | Page 23 of 64
ADAU1977
Data Sheet
output pin goes high-Z so that the same data line can be shared
with other devices on the TDM bus.
TDM Mode
Register 0x05 through Register 0x08 provide programmability
for the TDM mode. The TDM slot width, data width, and
channel assignment, as well as the pin used to output the data,
are programmable.
The TDM port can be operated as either a master or a slave.
In master mode, the BCLK and LRCLK are output from the
ADAU1977, whereas in slave mode, the BCLK and LRCLK pins
are set to receive the clock from the master in the system.
By default, serial data is output on the SDATAOUT1 pin;
however, the SDATA_SEL bit (Bit 7 of Register 0x06) can be
used to change the setting so that serial data is output from the
SDATAOUT2 pin.
Both the nonpulse and pulse modes are supported. In nonpulse
mode, the LRCLK signal is typically 50% of the duty cycle, whereas
in pulse mode, the LRCLK signal must be at least one BCLK wide
(see Figure 27 and Figure 28).
The TDM mode supports 2, 4, 8, or 16 channels. The ADAU1977
outputs four channels of data in the assigned slots (Figure 29
shows the data slot assignments). During the unused slots, the
BCLK
32/24/16 BCLKs
32/24/16 BCLKs
32/24/16 BCLKs
LRCLK
2
CHANNEL 1
CHANNEL 2
8 TO 32 BCLKs
CHANNEL N
SDATA I
S
8 TO 32 BCLKs
8 TO 32 BCLKs
CHANNEL 2
CHANNEL 1
CHANNEL N
SDATA LJ
8 TO 32 BCLKs
8 TO 32 BCLKs
8 TO 32 BCLKs
2
CHANNEL 1
24 OR 16 BCLKs
CHANNEL 2
24 OR 16 BCLKs
CHANNEL N
SDATA I
S
24 OR 16 BCLKs
NOTES
1. SAI = 001 (2 CHANNELS), 010 (4 CHANNELS), 011 (8 CHANNELS), 100 (16 CHANNELS).
2
2. SDATA_FMT = 00 (I S), 01 (LJ), 10 (RJ, 24-BIT), 11 (RJ, 16-BIT).
3. BCLK_EDGE = 0.
4. LRCLK_MODE = 0.
5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 (16 BCLKs).
Figure 27. TDM Nonpulse Mode Audio Format
BCLK
LRCLK
2
32/24/16 BCLKs
32/24/16 BCLKs
32/24/16 BCLKs
CHANNEL 1
CHANNEL 2
8 TO 32 BCLKs
CHANNEL N
8 TO 32 BCLKs
SDATA I
S
8 TO 32 BCLKs
CHANNEL 2
CHANNEL 1
CHANNEL N
SDATA LJ
8 TO 32 BCLKs
8 TO 32 BCLKs
8 TO 32 BCLKs
2
CHANNEL 1
24 OR 16 BCLKs
CHANNEL 2
CHANNEL N
24 OR 16 BCLKs
SDATA I
S
24 OR 16 BCLKs
NOTES
1. SAI = 001 (2 CHANNELS), 010 (4 CHANNELS), 011 (8 CHANNELS), 100 (16 CHANNELS)
2
2. SDATA_FMT = 00 (I S), 01 (LJ), 10 (RJ, 24-BIT), 11 (RJ, 16-BIT)
3. BCLK_EDGE = 0
4. LRCLK_MODE = 1
5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 (16 BCLKs)
Figure 28. TDM Pulse Mode Audio Format
Rev. A | Page 24 of 64
Data Sheet
ADAU1977
LRCLK
NUMBER OF BCLK CYCLES = (NUMBER OF BCLKs/SLOT) × NUMBER OF SLOTS
BCLK
SLOT1
SLOT2
SDATAOUTx-TDM2
SDATAOUTx-TDM4
SDATAOUTx-TDM8
SDATAOUTx-TDM16
SLOT1
SLOT2
SLOT3
SLOT4
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT8
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT8
SLOT9
SLOT10
SLOT11
SLOT12
SLOT13
SLOT14
SLOT15
SLOT16
DATA WIDTH
16/24 BITS
HIGH-Z
HIGH-Z
SLOT WIDTH
16/24/32BITS
Figure 29. TDM Mode Slot Assignment
Rev. A | Page 25 of 64
ADAU1977
Data Sheet
The bit clock frequency depends on the sample rate, the slot
width, and the number of bit clocks per slot. Table 19 can be
used to calculate the BCLK frequency.
care must be taken to choose the combination that is most
suitable for the application.
Connection Options
The sample rate (fS) can range from 8 kHz up to 192 kHz.
Figure 30 through Figure 34 show the available options for
connecting the serial audio port in I2S or TDM mode. In TDM
mode, it is recommended to include the pull-down resistor on
the data signal to prevent the line from floating when the
SDATAOUTx pin of ADAU1977 goes high-Z during an inactive
period. The resistor value should be such that no more than
2 mA is drawn from the SDATAOUTx pin. Although the resistor
value is typically in the range of 10 kΩ to 47 kΩ, the appropriate
resistor value depends on the devices on the data bus.
However, in master mode, the maximum bit clock frequency
(BCLK) is 24.576 MHz. For example, for a sample rate of
192 kHz, 128 × fS is the maximum possible BCLK frequency.
Therefore, only 128 bit clock cycles are available per TDM
frame. There are two options in this case: either operate with a
32-bit data width in TDM4 or operate with a 16-bit data width
in TDM8. In slave mode, this limitation does not exist because
the bit clock and frame clock are fed to the ADAU1977. Various
combinations of BCLK frequency and mode are available, but
Table 19. Bit Clock Frequency TDM Mode
BCLK Frequency
Mode
TDM2
TDM4
TDM8
TDM16
16 Bit Clocks Per Slot
32 × fS
64 × fS
128 × fS
256 × fS
24 Bit Clocks Per Slot
48 × fS
96 × fS
192 × fS
384 × fS
32 Bit Clocks Per Slot
64 × fS
128 × fS
256 × fS
512 × fS
MASTER
SLAVE
DSP
ADAU1977
BCLK
LRCLK
SDATAOUT1
SDATAOUT2
Figure 30. Serial Port Connection Option 1—I2S/LJ/RJ Mode, ADAU1977 Master
SLAVE
MASTER
DSP
ADAU1977
BCLK
LRCLK
SDATAOUT1
SDATAOUT2
Figure 31. Serial Port Connection Option 2—I2S/LJ/RJ Mode, ADAU1977 Slave
Rev. A | Page 26 of 64
Data Sheet
ADAU1977
MASTER
SLAVE
DSP
ADAU1977
BCLK
LRCLK
SDATAOUTx
SLAVE
ADAU1977
OR
SIMILIAR ADC
BCLK
LRCLK
SDATAOUTx
Figure 32. Serial Port Connection Option 3—TDM Mode, ADAU1977 Master
SLAVE
SLAVE
DSP
ADAU1977
BCLK
LRCLK
SDATAOUTx
MASTER
ADAU1977
OR
SIMILIAR ADC
BCLK
LRCLK
SDATAOUTx
Figure 33. Serial Port Connection Option 4—TDM Mode, Second ADC Master
SLAVE
MASTER
DSP
ADAU1977
BCLK
LRCLK
SDATAOUTx
SLAVE
ADAU1977
OR
SIMILIAR ADC
BCLK
LRCLK
SDATAOUTx
Figure 34. Serial Port Connection Option 5—TDM Mode, DSP Master
Rev. A | Page 27 of 64
ADAU1977
Data Sheet
CONTROL PORTS
The ADAU1977 control port allows two modes of operation—
either 2-wire I2C mode or 4-wire SPI mode—that are used for
setting the internal registers of the part. Both the I2C and SPI
modes allow read and write capability of the registers. All the
registers are eight bits wide. The registers start at Address 0x00
and end at Address 0x1A.
However, to operate the PLL, serial audio ports, and boost
converter, the master clock is necessary.
By default, the ADAU1977 operates in I2C mode, but the part can
CLATCH
be put into SPI mode by pulling the
pin low three times.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 20 describes the
control port pin functions in both modes.
The control port in both I2C and SPI modes is slave only and,
therefore, requires the master in the system to operate. The registers
can be accessed with or without the master clock to the part.
Table 20. Control Port Pin Functions
I2C Mode
SPI Mode
Pin No.
17
18
Pin Name
Pin Functions
SDA: data
SCL: clock
I2C Device Address Bit 0
I2C Device Address Bit 1
Pin Type
Pin Functions
Pin Type
SDA/COUT
SCL/CCLK
ADDR0/CLATCH
ADDR1/CIN
I/O
COUT: output data
CCLK: input clock
CLATCH: input
O
I
I
I
I
I
19
20
CIN: input data
I
Rev. A | Page 28 of 64
Data Sheet
ADAU1977
I2C MODE
VIL is the maximum voltage at Logic Level 0 (that is, 0.4 V, as
per the I2C specifications).
The ADAU1977 supports a 2-wire serial (I2C-compatible) bus
protocol. Two pins—serial data (SDA) and serial clock (SCL)—
are used to communicate with the system I2C master controller.
In I2C mode, the ADAU1977 is always a slave on the bus, meaning
that it cannot initiate a data transfer. Each slave device on the
I2C bus is recognized by a unique device address. The device
ISINK is the current sink capability of the I/O pin.
The SDA pin can sink 2 mA current; therefore, the minimum
value of RPULL UP for an IOVDD of 3.3 V is 1.5 kΩ.
Depending on the capacitance of the board, the speed of the bus
can be restricted to meet the rise time and fall time specifications.
W
address and R/ byte for the ADAU1977 are shown in Table 21.
For fast mode with a bit rate time of around 1 Mbps, the rise
time must be less than 550 ns. Use the following equation to
determine whether the rise time specification can be met:
The address resides in the first seven bits of the I2C write. Bit 7
and Bit 6 of the I2C address for the ADAU1977 are set by the
levels on the ADDR1 and ADDR0 pins. The LSB of the first I2C
t = 0.8473 × RPULL UP × CBOARD
.
W
byte (the R/ bit) from the master identifies whether it is a read
To meet the 300 ns rise time requirement, the CBOARD must be
less than 236 pF.
or write operation. Logic Level 1 in LSB corresponds to a read
operation, and Logic Level 0 corresponds to a write operation.
For the SCL pin, the calculations depend on the current sink
capability of the I2C master used in the system.
Table 21. ADAU1977 I2C First Byte Format
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Addressing
ADDR1 ADDR0
1
0
0
0
1
R/W
Initially, each device on the I2C bus is in an idle state and monitors
the SDA and SCL lines for a start condition and the proper address.
The I2C master initiates a data transfer by establishing a start
condition, defined by a high-to-low transition on SDA while
SCL remains high. This indicates that an address/data stream
follows. All devices on the bus respond to the start condition
and acquire the next eight bits from the master (the 7-bit address
The first seven bits of the I2C chip address for the ADAU1977
are xx10001. Bit 0 and Bit 1 of the address byte can be set using
the ADDR1 and ADDR0 pins to set the chip address to the
desired value.
The 7-bit I2C device address can be set to one of four possible
options using the ADDR1 and ADDR0 pins:
W
plus the R/ bit) MSB first. The master sends the 7-bit device
•
•
•
•
I2C Device Address 0010001 (0x11)
I2C Device Address 0110001 (0x31)
I2C Device Address 1010001 (0x51)
I2C Device Address 1110001 (0x71)
address with the read/write bit to all the slaves on the bus. The
device with the matching address responds by pulling the data
line (SDA) low during the ninth clock pulse. This ninth bit is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and return to the idle condition.
In I2C mode, both the SDA and SCL pins require that an
appropriate pull-up resistor be connected to IOVDD. The
voltage on these signal lines should not exceed the voltage on
the IOVDD pin. Figure 46 shows a typical connection diagram
for the I2C mode.
W
The R/ bit determines the direction of the data. A Logic 0 on the
LSB of the first byte means that the master is to write information
to the slave, whereas a Logic 1 means that the master is to read
information from the slave after writing the address and repeating
the start address. A data transfer takes place until a master initiates
a stop condition. A stop condition occurs when SDA transitions
from low to high while SCL is held high.
The value of the pull-up resistor for the SDA or SCL pin can be
calculated as follows.
Minimum RPULL UP = (IOVDD – VIL)/ISINK
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
during normal read and write operations, the ADAU1977
immediately jumps to the idle condition.
where:
IOVDD is the I/O supply voltage, typically ranging from 1.8 V
up to 3.3 V.
Rev. A | Page 29 of 64
ADAU1977
Data Sheet
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
SCL
FIRST BYTE (DEVICE ADDRESS)
SECOND BYTE (REGISTER ADDRESS)
THIRD BYTE (DATA)
ADDR1 ADDR0
1
0
0
0
1
R/W
SDA
STOP
ACK
ADAU1977
ACK
ADAU1977
START
Figure 35. I2C Write to ADAU1977 Single Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SCL
FIRST BYTE (DEVICE ADDRESS)
SECOND BYTE (REGISTER ADDRESS)
ADDR1 ADDR0
1
0
0
0
1
R/W
SDA
ACK
ADAU1977
ACK
ADAU1977
START
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SCL
SDA
THIRD BYTE (DEVICE ADDRESS)
DATA BYTE FROM ADAU1977
ADDR1 ADDR0
1
0
0
0
1
R/W
NO ACK
ACK
ADAU1977
REPEAT START
STOP
Figure 36. I2C Read from ADAU1977 Single Byte
Rev. A | Page 30 of 64
Data Sheet
ADAU1977
I2C Read and Write Operations
W
followed by the chip address byte with the R/ bit set to 1
(read). This causes the ADAU1977 SDA to reverse and begin
driving data back to the master. The master then responds every
ninth pulse with an acknowledge pulse to the ADAU1977.
Figure 37 shows the format of a single-word write operation.
Every ninth clock pulse, the ADAU1977 issues an acknowledge
by pulling SDA low.
Figure 40 shows the format of a burst mode read sequence. This
figure shows an example of a read from sequential single-byte
registers. The ADAU1977 increments its address registers after
every byte because the ADAU1977 uses an 8-bit register address.
Figure 38 shows the format of a burst mode write sequence.
This figure shows an example of a write to sequential single-
byte registers. The ADAU1977 increments its address register
after every byte because the requested address corresponds to a
register or memory area with a 1-byte word length.
Figure 37 to Figure 40 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
Figure 39 shows the format of a single-word read operation.
W
Note that the first R/ bit is 0, indicating a write operation.
This is because the address still needs to be written to set up the
internal address. After the ADAU1977 acknowledges the receipt
of the address, the master must issue a repeated start command
S
CHIP ADDRESS,
R/W = 0
AS
REGISTER ADDRESS
8 BITS
AS
DATA BYTE
P
Figure 37. Single-Word I2C Write Format
S
CHIP
ADDRESS,
R/W = 0
AS REGISTER
CHIP
AS DATA AS DATA AS DATA AS DATA
BYTE 1 BYTE 2 BYTE 3 BYTE 4
AS ...
P
ADDRESS ADDRESS,
8 BITS R/W = 0
Figure 38. Burst Mode I2C Write Format
S
CHIP
ADDRESS,
R/W = 0
AS
REGISTER
ADDRESS
8 BITS
AS
S
CHIP
ADDRESS,
R/W = 1
AS
DATA
BYTE 1
P
Figure 39. Single-Word I2C Read Format
S
CHIP
ADDRESS,
R/W = 0
AS REGISTER AS
ADDRESS
S
CHIP
ADDRESS,
R/W = 1
AS DATA AM
BYTE 1
DATA AM ...
BYTE 2
P
8 BITS
Figure 40. Burst Mode I2C Read Format
Rev. A | Page 31 of 64
ADAU1977
Data Sheet
Data Bytes
SPI MODE
By default, the ADAU1977 is in I2C mode. To invoke SPI control
The number of data bytes varies according to the register being
accessed. During a burst mode write, an initial register address is
written followed by a continuous sequence of data for consecutive
register locations.
CLATCH
mode, pull
low three times. This can be done by per-
forming three dummy writes to the SPI port (the ADAU1977 does
not acknowledge these three writes; see Figure 41). Beginning
with the fourth SPI write, data can be written to or read from
the device. The ADAU1977 can be taken out of SPI mode only
by a full reset initiated by power cycling the device.
A sample timing diagram for a single-word SPI write operation to a
register is shown in Figure 42. A sample timing diagram of a single-
word SPI read operation is shown in Figure 43. The COUT pin
goes from being high-Z to being driven at the beginning of Byte 3.
In this example, Byte 0 to Byte 1 contain the device address, the
CLATCH
The SPI port uses a 4-wire interface, consisting of the
CCLK, CIN, and COUT signals, and it is always a slave port.
CLATCH
,
W
R/ bit, and the register address to be read. Subsequent bytes
The
signal should go low at the beginning of a trans-
carry the data from the device.
action and high at the end of a transaction. The CCLK signal
latches CIN on a low-to-high transition. COUT data is shifted out
of the ADAU1977 on the falling edge of CCLK and should be
clocked into a receiving device, such as a microcontroller, on
the CCLK rising edge. The CIN signal carries the serial input
data, and the COUT signal carries the serial output data. The
COUT signal remains tristated until a read operation is requested.
This allows direct connection to other SPI-compatible peripheral
COUT ports for sharing the same system controller port. All
SPI transactions have the same basic format shown in Table 24.
A timing diagram is shown in Figure 3. All data should be written
MSB first.
Standalone Mode
The ADAU1977 can also be operated in standalone mode.
However, in standalone mode, the boost converter, microphone
bias, and diagnostics blocks are powered down. To set the part
in standalone mode, pull the SA_MODE pin to IOVDD. In this
mode, some pins change functionality to provide more flexibility
(see Table 23 for more information).
Table 23. Pin Functionality in Standalone Mode
Pin Function
Setting
Description
ADDR0
0
1
I2S SAI format
TDM modes, determined by the
SDATAOUT2 pin
W
Chip Address R/
W
The LSB of the first byte of an SPI transaction is a R/ bit. This bit
determines whether the communication is a read (Logic Level 1)
or a write (Logic Level 0). This format is shown in Table 22.
ADDR1
SDA
0
1
0
1
0
1
0
1
0
1
Master mode SAI
Slave mode SAI
MCLK = 256 × fS, PLL on
MCLK = 384 × fS, PLL on
48 kHz sample rate
96 kHz sample rate
TDM4—LRCLK pulse
TDM8—LRCLK pulse
Slot 1 to Slot 4 in TDM8
Slot 5 to Slot 8 in TDM8
W
Table 22. ADAU1977 SPI Address and R/ Byte Format
SCL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
R/W
SDATAOUT2
FAULT
Register Address
The 8-bit address word is decoded to a location in one of the
registers. This address is the location of the appropriate register.
If set for TDM8 mode, the FAULT pin is used as an input for
assigning the ADC data slot to prevent collision with other data
on TDM bus.
Table 24. Generic Control Word Format
Byte 0
Byte 1
Byte 2
Byte 31
Device Address[6:0], R/W
Register Address[7:0]
Data[7:0]
Data[7:0]
1 Continues to end of data.
Rev. A | Page 32 of 64
Data Sheet
ADAU1977
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CLATCH
CCLK
CIN
Figure 41. SPI Mode Initial Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21 22
23
24
25
14
CLATCH
CCLK
DEVICE ADDRESS (7 BITS)
R/W
REGISTER ADDRESS BYTE
DATA BYTE
CIN
Figure 42. SPI Write to ADAU1977 Clocking (Single-Word Write Mode)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21 22
23
24
25
14
CCLK
CLATCH
DEVICE ADDRESS (7 BITS)
REGISTER ADDRESS BYTE
DATA BYTE
CIN
R/W
DATA BYTE FROM ADAU1977
COUT
Figure 43. SPI Read from ADAU1977 Clocking (Single-Word Read Mode)
CLATCH
CCLK
CIN
DATA BYTE1
DEVICE
ADDRESS
BYTE
REGISTER
ADDRESS
BYTE
DATA BYTE2
DATA BYTE n – 1
DATA BYTE n
Figure 44. SPI Write to ADAU1977 (Multiple Bytes)
CLATCH
CCLK
CIN
DEVICE
ADDRESS
BYTE
REGISTER
ADDRESS
BYTE
COUT
DATA BYTE1
DATA BYTE2
DATA BYTE3
DATA BYTE n – 1
DATA BYTE n
Figure 45. SPI Read from ADAU1977 (Multiple Bytes)
Rev. A | Page 33 of 64
ADAU1977
Data Sheet
REGISTER SUMMARY
Table 25 is the control register summary. The registers can be accessed using the I2C control port or the SPI control port.
Table 25. ADAU1977 Register Summary
Reg Name
Bits Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
0x00 M_POWER
0x01 PLL_CONTROL
0x02 BST_CONTROL
[7:0] S_RST
RESERVED
PWUP
0x00 RW
0x41 RW
0x4A RW
[7:0] PLL_LOCK
[7:0] BST_GOOD
PLL_MUTE
RESERVED
CLK_S
RESERVED
OV_EN
MCS
FS_RATE
BOOST_SW_
FREQ
BOOST_OV
OC_EN
BOOST_OC
0x03 MB_BST_CONTROL [7:0]
MB_VOLTS
LDO_EN
MB_EN
BOOST_EN
ADC_EN3
MRCV
BOOST_RCVR 0x7D RW
0x04 BLOCK_POWER_SAI [7:0] LR_POL
BCLKEDGE
VREF_EN
SAI
ADC_EN4
ADC_EN2
FS
ADC_EN1
0x3F RW
0x02 RW
0x00 RW
0x10 RW
0x32 RW
0xF0 RW
0xA0 RW
0xA0 RW
0xA0 RW
0xA0 RW
0x02 RW
0x0F RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x05 SAI_CTRL0
[7:0]
SDATA_FMT
0x06 SAI_CTRL1
[7:0] SDATA_SEL
SLOT_WIDTH
CMAP_C2
DATA_WIDTH LR_MODE
SAI_MSB
BCLKRATE
SAI_MS
0x07 SAI_CMAP12
0x08 SAI_CMAP34
0x09 SAI_OVERTEMP
0x0A POSTADC_GAIN1
0x0B POSTADC_GAIN2
0x0C POSTADC_GAIN3
0x0D POSTADC_GAIN4
0x0E MISC_CONTROL
0x10 DIAG_CONTROL
0x11 DIAG_STATUS1
0x12 DIAG_STATUS2
0x13 DIAG_STATUS3
0x14 DIAG_STATUS4
0x15 DIAG_IRQ1
[7:0]
CMAP_C1
CMAP_C3
[7:0]
CMAP_C4
[7:0] SAI_DRV_C4
SAI_DRV_C3
SAI_DRV_C2
SAI_DRV_C1
DRV_HIZ
OT_MCRV
OT_RCVR
OT
[7:0]
[7:0]
[7:0]
[7:0]
PADC_GAIN1
PADC_GAIN2
PADC_GAIN3
PADC_GAIN4
[7:0]
SUM_MODE
RESERVED
RESERVED
MIC_SHORT1 MICH_OPEN1 MICH_SB1
MMUTE
RESERVED
DIAG_EN3
DC_CAL
[7:0]
DIAG_EN4
MICH_SG1
MICH_SG2
MICH_SG3
MICH_SG4
DIAG_EN2
MICL_SB1
MICL_SB2
MICL_SB3
MICL_SB4
DIAG_EN1
MICL_SG1
MICL_SG2
MICL_SG3
MICL_SG4
[7:0] RESERVED
[7:0] RESERVED
[7:0] RESERVED
[7:0] RESERVED
[7:0] RESERVED
MICH_SMB1
MICH_SMB2
MICH_SMB3
MICH_SMB4
MIC_SHORT2 MIC_OPEN2
MIC_SHORT3 MIC_OPEN3
MIC_SHORT4 MIC_OPEN4
MICH_SB2
MICH_SB3
MICH_SB4
IRQ_POL
IRQ_RESET
IRQ_DRIVE
DIAG_MASK4 DIAG_MASK3 DIAG_MASK2 DIAG_MASK1 0x20 RW
0x16 DIAG_IRQ2
[7:0] BST_FAULT_
MASK
MIC_SHORT_ MIC_OPEN_
MICH_SB_
MASK
MICH_SG_
MASK
RESERVED
MICL_SB_
MASK
MICL_SG_
MASK
0x00 RW
MASK
MASK
0x17 DIAG_ADJUST1
0x18 DIAG_ADJUST2
0x19 ASDC_CLIP
[7:0]
[7:0]
[7:0]
SHT_T_TRIP
RESERVED
SHT_M_TRIP
FAULT_TO
SHT_G_TRIP
SHT_B_TRIP
HYST_SM_EN HYST_SG_EN HYST_SB_EN
0x00 RW
0x20 RW
0x00 RW
0x00 RW
RESERVED
ADC_CLIP4
DC_HPF_C4
RESERVED
ADC_CLIP3
DC_HPF_C3
ADC_CLIP2
DC_HPF_C2
ADC_CLIP1
DC_HPF_C1
0x1A DC_HPF_CAL
[7:0] DC_SUB_C4
DC_SUB_C3
DC_SUB_C2
DC_SUB_C1
Rev. A | Page 34 of 64
Data Sheet
ADAU1977
REGISTER DETAILS
MASTER POWER AND SOFT RESET REGISTER
Address: 0x00, Reset: 0x00, Name: M_POWER
The power management control register is used for enabling boost regulator, microphone bias, PLL, band gap reference, ADC, and LDO
regulator.
Table 26. Bit Descriptions for M_POWER
Bits
Bit Name
Settings
Description
Reset
Access
7
S_RST
Software Reset. The software reset resets all internal circuitry and places
all control registers to their default state. It is not necessary to reset the
ADAU1977 during a power-up or power-down cycle.
0x0
RW
0
1
Normal Operation
Software Reset
Reserved.
[6:1]
0
RESERVED
PWUP
0x00
RW
RW
Master Power-Up Control. The master power-up control fully powers up or 0x0
powers down the ADAU1977. This must be set to 1 to power up the
ADAU1977. Individual blocks can be powered down via their respective
power control registers.
0
1
Full Power-Down
Master Power-Up
Rev. A | Page 35 of 64
ADAU1977
Data Sheet
PLL CONTROL REGISTER
Address: 0x01, Reset: 0x41, Name: PLL_CONTROL
Table 27. Bit Descriptions for PLL_CONTROL
Bits
Bit Name
Settings
Description
Reset
Access
7
PLL_LOCK
PLL Lock Status. PLL lock status bit. When one PLL is locked.
0x0
R
0
1
PLL Not Locked
PLL Locked
6
PLL_MUTE
PLL Unlock Automute. When set to 1, mutes the ADC output if PLL
becomes unlocked.
0x1
RW
0
1
No Automatic Mute on PLL Unlock
Automatic Mute with PLL Unlock
5
4
RESERVED
CLK_S
Reserved.
0x0
0x0
RW
RW
PLL Clock Source Select. Selecting input clock source for PLL.
MCLK Used for PLL Input
LRCLK Used for PLL Input; Only Supported for Sample Rates > 32 kHz
0
1
[2:0]
MCS
Master Clock Select. MCS bits determine the frequency multiplication
ratio of the PLL. It must be set based on the input MCLK frequency and
sample rate.
0x1
RW
001 256 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other
sample rates)
010 384 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other
sample rates)
011 512 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other
sample rates)
100 768 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other
sample rates)
000 128 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other
sample rates)
Rev. A | Page 36 of 64
Data Sheet
ADAU1977
Bits
Bit Name
Settings
Description
Reset
Access
101 Reserved
110 Reserved
111 Reserved
DC-TO-DC BOOST CONVERTER CONTROL REGISTER
Address: 0x02, Reset: 0x4A, Name: BST_CONTROL
Table 28. Bit Descriptions for BST_CONTROL
Bits
Bit Name
Settings
Description
Reset
Access
7
BST_GOOD
Boost Converter Output Status.
Boost Converter Output Not Stabilized
Boost Converter Output Good
Sample Rate Control for Boost Switching Frequency.
0x0
R
0
1
[6:5]
FS_RATE
0x2
RW
00 8 kHz/16 kHz/32 kHz/64 kHz/128 kHz fS
01 11.025 kHz/22.05 kHz/44.1 kHz/88.2 kHz/176.4 kHz fS
10 12 kHz/24 kHz/48 kHz/96 kHz/192 kHz fS
11 Reserved
4
3
2
1
0
BOOST_SW_FREQ
OV_EN
Boost Regulator Switching Frequency.
0x0
0x1
0x0
0x1
0x0
RW
RW
R
0
1
1.5 MHz Switching Frequency
3 MHz Switching Frequency
Overvoltage Fault Protection Enable.
Disable
0
1
Enable
BOOST_OV
OC_EN
Boost Converter Overvoltage Fault Status.
Normal Operation
Overvoltage Fault
0
1
Overcurrent Fault Protection Enable.
Disable
Enable
RW
R
0
1
BOOST_OC
Boost Converter Overcurrent Fault Status.
Normal Operation
Boost Overcurrent Protection Active
0
1
Rev. A | Page 37 of 64
ADAU1977
Data Sheet
MICBIAS AND BOOST CONTROL REGISTER
Address: 0x03, Reset: 0x7D, Name: MB_BST_CONTROL
Table 29. Bit Descriptions for MB_BST_CONTROL
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
MB_VOLTS
MICBIAS Output Voltage.
0x7
RW
0000 5.0 V
0001 5.5 V
0010 6.0 V
0011 6.5 V
0100 7.0 V
0101 7.5 V
0110 8.0 V
0111 8.5 V
1000 9.0 V
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
3
2
1
MB_EN
MICBIAS Enable.
MICBIAS Powered Down
MICBIAS Enabled
0x1
0x1
0x0
RW
RW
W
0
1
BOOST_EN
MRCV
Boost Enable.
Boost Off
Boost On
0
1
Boost Fault Manual Recovery.
Normal Operation
Attempt Manual Boost Fault Recovery
0
1
Rev. A | Page 38 of 64
Data Sheet
ADAU1977
Bits
Bit Name
Settings
Description
Reset
Access
0
BOOST_RCVR
Boost Recovery Mode.
0x1
RW
0
1
Automatic Fault Recovery
Manual Fault Recovery; Use MRCV to Recover
BLOCK POWER CONTROL AND SERIAL PORT CONTROL REGISTER
Address: 0x04, Reset: 0x3F, Name: BLOCK_POWER_SAI
Table 30. Bit Descriptions for BLOCK_POWER_SAI
Bits
Bit Name
Settings
Description
Reset
Access
7
LR_POL
Sets LRCLK Polarity.
0x0
RW
0
1
LRCLK Low then High
LRCLK High then Low
6
5
4
3
2
1
0
BCLKEDGE
LDO_EN
Sets the Bit Clock Edge on Which Data Changes.
Data Changes on Falling Edge
Data Changes on Rising Edge
LDO Regulator Enable.
LDO Powered Down
LDO Enabled
0x0
0x1
0x1
0x1
0x1
0x1
0x1
RW
RW
RW
RW
RW
RW
RW
0
1
0
1
VREF_EN
ADC_EN4
ADC_EN3
ADC_EN2
ADC_EN1
Voltage Reference Enable.
Voltage Reference Powered Down
Voltage Reference Enabled
ADC Channel 3 Enable.
ADC Channel Powered Down
ADC Channel Enabled
0
1
0
1
ADC Channel 3 Enable.
ADC Channel Powered Down
ADC Channel Enabled
0
1
ADC Channel 2 Enable.
ADC Channel Powered Down
ADC Channel Enabled
0
1
ADC Channel 1 Enable.
ADC Channel Powered Down
ADC Channel Enabled
0
1
Rev. A | Page 39 of 64
ADAU1977
Data Sheet
SERIAL PORT CONTROL REGISTER1
Address: 0x05, Reset: 0x02, Name: SAI_CTRL0
Table 31. Bit Descriptions for SAI_CTRL0
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
SDATA_FMT
Serial Data Format.
00 I2S Data Delayed from Edge of LRCLK by 1 BCLK
01 Left Justified
0x0
RW
10 Right Justified, 24-Bit Data
11 Right Justified, 16-Bit Data
Serial Port Mode.
[5:3]
[2:0]
SAI
FS
0x0
0x2
RW
RW
000 Stereo (I2S, LJ, RJ)
001 TDM2
010 TDM4
011 TDM8
100 TDM16
Sampling Rate.
000 8 kHz to 12 kHz
001 16 kHz to 24 kHz
010 32 kHz to 48 kHz
011 64 kHz to 96 kHz
100 128 kHz to 192 kHz
Rev. A | Page 40 of 64
Data Sheet
ADAU1977
SERIAL PORT CONTROL REGISTER2
Address: 0x06, Reset: 0x00, Name: SAI_CTRL1
Table 32. Bit Descriptions for SAI_CTRL1
Bits
Bit Name
Settings
Description
Reset
Access
7
SDATA_SEL
SDATAOUTx Pin Selection in TDM4 or Greater Modes.
SDATAOUT1 used for output
SDATAOUT2 used for output
0x0
RW
0
1
[6:5]
SLOT_WIDTH
Number of BCLKs per Slot in TDM Mode.
0x0
RW
00 32 BCLKs per TDM slot
01 24 BCLKs per TDM slot
10 16 BCLKs per TDM slot
11 Reserved
4
3
2
1
DATA_WIDTH
LR_MODE
SAI_MSB
Output Data Bit Width.
24-bit data
16-bit data
0x0
0x0
0x0
0x0
RW
RW
RW
RW
0
1
Sets LRCLK Mode.
50% duty cycle clock
Pulse—LRCLK is a single BCLK cycle wide pulse
Sets Data to be Input/Output either MSB or LSB First.
MSB first data
0
1
0
1
LSB first data
BCLKRATE
Sets the Number of Bit Clock Cycles per Data Channel Generated When in
Master Mode.
0
1
32 BCLKs/channel
16 BCLKs/channel
0
SAI_MS
Sets the Serial Port into Master or Slave Mode.
LRCLK/BCLK Slave
LRCLK/BCLK Master
0x0
RW
0
1
Rev. A | Page 41 of 64
ADAU1977
Data Sheet
CHANNEL MAPPING FOR OUTPUT SERIAL PORTS REGISTER
Address: 0x07, Reset: 0x10, Name: SAI_CMAP12
Table 33. Bit Descriptions for SAI_CMAP12
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
CMAP_C2
ADC Channel 2 Output Mapping.
0x1
RW
0000 Slot 1 for Channel
0001 Slot 2 for Channel
0010 Slot 3 for Channel (on SDATAOUT2 in stereo modes)
0011 Slot 4 for Channel (on SDATAOUT2 in stereo modes)
0100 Slot 5 for Channel (TDM8+ only)
0101 Slot 6 for Channel (TDM8+ only)
0110 Slot 7 for Channel (TDM8+ only)
0111 Slot 8 for Channel (TDM8+ only)
1000 Slot 9 for Channel (TDM16 only)
1001 Slot 10 for Channel (TDM16 only)
1010 Slot 11 for Channel (TDM16 only)
1011 Slot 12 for Channel (TDM16 only)
1100 Slot 13 for Channel (TDM16 only)
1101 Slot 14 for Channel (TDM16 only)
1110 Slot 15 for Channel (TDM16 only)
1111 Slot 16 for Channel (TDM16 only)
Rev. A | Page 42 of 64
Data Sheet
ADAU1977
Bits
Bit Name
Settings
Description
Reset
Access
[3:0]
CMAP_C1
ADC Channel 1 Output Mapping. If CMAP is set to a slot that doesn’t exist
for a given serial mode, then that channel will not be driven. For example,
if CMAP is set to Slot 9 and the serial format is I2S, then that channel will
not be driven. If more than one channel is set to the same slot, only the
lowest channel number will be driven; other channels will not be driven.
0x0
RW
0000 Slot 1 for Channel
0001 Slot 2 for Channel
0010 Slot 3 for Channel (on SDATAOUT2 in stereo modes)
0011 Slot 4 for Channel (on SDATAOUT2 in stereo modes)
0100 Slot 5 for Channel (TDM8+ only)
0101 Slot 6 for Channel (TDM8+ only)
0110 Slot 7 for Channel (TDM8+ only)
0111 Slot 8 for Channel (TDM8+ only)
1000 Slot 9 for Channel (TDM16 only)
1001 Slot 10 for Channel (TDM16 only)
1010 Slot 11 for Channel (TDM16 only)
1011 Slot 12 for Channel (TDM16 only)
1100 Slot 13 for Channel (TDM16 only)
1101 Slot 14 for Channel (TDM16 only)
1110 Slot 15 for Channel (TDM16 only)
1111 Slot 16 for Channel (TDM16 only)
Rev. A | Page 43 of 64
ADAU1977
Data Sheet
CHANNEL MAPPING FOR OUTPUT SERIAL PORTS REGISTER
Address: 0x08, Reset: 0x32, Name: SAI_CMAP34
Table 34. Bit Descriptions for SAI_CMAP34
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
CMAP_C4
ADC Channel 4 Output Mapping.
0x3
RW
0000 Slot 1 for Channel
0001 Slot 2 for Channel
0010 Slot 3 for Channel (on SDATAOUT2 in stereo modes)
0011 Slot 4 for Channel (on SDATAOUT2 in stereo modes)
0100 Slot 5 for Channel (TDM8+ only)
0101 Slot 6 for Channel (TDM8+ only)
0110 Slot 7 for Channel (TDM8+ only)
0111 Slot 8 for Channel (TDM8+ only)
1000 Slot 9 for Channel (TDM16 only)
1001 Slot 10 for Channel (TDM16 only)
1010 Slot 11 for Channel (TDM16 only)
1011 Slot 12 for Channel (TDM16 only)
1100 Slot 13 for Channel (TDM16 only)
1101 Slot 14 for Channel (TDM16 only)
1110 Slot 15 for Channel (TDM16 only)
1111 Slot 16 for Channel (TDM16 only)
Rev. A | Page 44 of 64
Data Sheet
ADAU1977
Bits
Bit Name
Settings
Description
Reset
Access
[3:0]
CMAP_C3
ADC Channel 3 Output Mapping.
0x2
RW
0000 Slot 1 for Channel
0001 Slot 2 for Channel
0010 Slot 3 for Channel (on SDATAOUT2 in stereo modes)
0011 Slot 4 for Channel (on SDATAOUT2 in stereo modes)
0100 Slot 5 for Channel (TDM8+ only)
0101 Slot 6 for Channel (TDM8+ only)
0110 Slot 7 for Channel (TDM8+ only)
0111 Slot 8 for Channel (TDM8+ only)
1000 Slot 9 for Channel (TDM16 only)
1001 Slot 10 for Channel (TDM16 only)
1010 Slot 11 for Channel (TDM16 only)
1011 Slot 12 for Channel (TDM16 only)
1100 Slot 13 for Channel (TDM16 only)
1101 Slot 14 for Channel (TDM16 only)
1110 Slot 15 for Channel (TDM16 only)
1111 Slot 16 for Channel (TDM16 only)
Rev. A | Page 45 of 64
ADAU1977
Data Sheet
SERIAL OUTPUT DRIVE AND OVERTEMPERATURE PROTECTION CONTROL REGISTER
Address: 0x09, Reset: 0xF0, Name: SAI_OVERTEMP
Table 35. Bit Descriptions for SAI_OVERTEMP
Bits
Bit Name
Settings
Description
Reset
Access
7
SAI_DRV_C4
Channel 4 Serial Output Drive Enable.
0x1
RW
0
1
Channel Not Driven on Serial Output Port
Channel Driven on Serial Output Port; Slot Determined by CMAP
Channel 3 Serial Output Drive Enable.
6
5
4
3
SAI_DRV_C3
SAI_DRV_C2
SAI_DRV_C1
DRV_HIZ
0x1
0x1
0x1
0x0
RW
RW
RW
RW
0
1
Channel Not Driven on Serial Output Port
Channel Driven on Serial Output Port; Slot Determined by CMAP
Channel 2 Serial Output Drive Enable.
Channel Not Driven on Serial Output Port
Channel Driven on Serial Output Port; Slot Determined by CMAP
Channel 1 Serial Output Drive Enable.
0
1
0
1
Channel Not Driven on Serial Output Port
Channel Driven on Serial Output Port; Slot Determined by CMAP
Select Whether to Tristate Unused SAI Channels or to Actively Drive These
Data Slots.
0
1
Unused Outputs Driven Low
Unused Outputs High-Z
2
1
OT_MCRV
OT_RCVR
Overtemperature Manual Recovery Attempt.
Normal Operation
Attempt Manual Overtemperature Recovery
Overtemperature Manual Recovery.
Automatic Recovery from Overtemperature Fault
0x0
0x0
W
0
1
RW
0
1
Manual Recovery from Overtemperature Fault, Must Set OT_MCRV Register
Rev. A | Page 46 of 64
Data Sheet
ADAU1977
Bits
Bit Name
Settings
Description
Reset
Access
0
OT
Overtemperature Status.
Normal Operation
Overtemperature Fault
0x0
R
0
1
POST ADC GAIN CHANNEL 1 CONTROL REGISTER
Address: 0x0A, Reset: 0xA0, Name: POSTADC_GAIN1
Table 36. Bit Descriptions for POSTADC_GAIN1
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PADC_GAIN1
Channel 1 Post ADC Gain.
0xA0
RW
00000000 +60 dB Gain
00000001 +59.625 dB Gain
00000010 +59.25 dB Gain
... ...
10011111 +0.375 dB Gain
10100000 0 dB Gain
10100001 −0.375 dB Gain
... ...
11111110 −35.625 dB Gain
11111111 Mute
Rev. A | Page 47 of 64
ADAU1977
Data Sheet
POST ADC GAIN CHANNEL 2 CONTROL REGISTER
Address: 0x0B, Reset: 0xA0, Name: POSTADC_GAIN2
Table 37. Bit Descriptions for POSTADC_GAIN2
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PADC_GAIN2
Channel 2 Post ADC Gain.
0xA0
RW
00000000 +60 dB Gain
00000001 +59.625 dB Gain
00000010 +59.25 dB Gain
... ...
10011111 +0.375 dB Gain
10100000 0 dB Gain
10100001 −0.375 dB Gain
... ...
11111110 −35.625 dB Gain
11111111 Mute
Rev. A | Page 48 of 64
Data Sheet
ADAU1977
POST ADC GAIN CHANNEL 3 CONTROL REGISTER
Address: 0x0C, Reset: 0xA0, Name: POSTADC_GAIN3
Table 38. Bit Descriptions for POSTADC_GAIN3
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PADC_GAIN3
Channel 3 Post ADC Gain.
0xA0
RW
00000000 +60 dB Gain
00000001 +59.625 dB Gain
00000010 +59.25 dB Gain
... ...
10011111 +0.375 dB Gain
10100000 0 dB Gain
10100001 −0.375 dB Gain
... ...
11111110 −35.625 dB Gain
11111111 Mute
Rev. A | Page 49 of 64
ADAU1977
Data Sheet
POST ADC GAIN CHANNEL 4 CONTROL REGISTER
Address: 0x0D, Reset: 0xA0, Name: POSTADC_GAIN4
Table 39. Bit Descriptions for POSTADC_GAIN4
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PADC_GAIN4
Channel 4 Post ADC Gain.
0xA0
RW
00000000 +60 dB Gain
00000001 +59.625 dB Gain
00000010 +59.25 dB Gain
... ...
10011111 +0.375 dB Gain
10100000 0 dB Gain
10100001 −0.375 dB Gain
... ...
11111110 −35.625 dB Gain
11111111 Mute
Rev. A | Page 50 of 64
Data Sheet
ADAU1977
HIGH-PASS FILTER AND DC OFFSET CONTROL REGISTER AND MASTER MUTE
Address: 0x0E, Reset: 0x02, Name: MISC_CONTROL
Table 40. Bit Descriptions for MISC_CONTROL
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
SUM_MODE
Channel Summing Mode Control for Higher SNR.
0x0
RW
00 Normal 4-Channel Operation
01 2-Channel Summing Operation (See the ADC Summing Modes Section)
10 1-Channel Summing Operation (See the ADC Summing Modes Section)
11 Reserved
Reserved.
5
4
RESERVED
MMUTE
0x0
0x0
RW
RW
Master Mute.
0
1
Normal Operation
All Channels Muted
Reserved.
[3:1]
0
RESERVED
DC_CAL
0x1
0x0
RW
RW
DC Calibration Enable.
Normal Operation
Perform DC Calibration
0
1
Rev. A | Page 51 of 64
ADAU1977
Data Sheet
DIAGNOSTICS CONTROL REGISTER
Address: 0x10, Reset: 0x0F, Name: DIAG_CONTROL
Table 41. Bit Descriptions for DIAG_CONTROL
Bits
[7:4]
3
Bit Name
RESERVED
DIAG_EN4
Settings
Description
Reset
0x0
Access
RW
Reserved.
Diagnostics Enable Channel 4.
Diagnostics Disabled
Diagnostics Enabled
Diagnostics Enable Channel 3.
Diagnostics Disabled
Diagnostics Enabled
Diagnostics Enable Channel 2.
Diagnostics Disabled
Diagnostics Enabled
Diagnostics Enable Channel 1.
Diagnostics Disabled
Diagnostics Enabled
0x1
RW
0
1
2
1
0
DIAG_EN3
DIAG_EN2
DIAG_EN1
0x1
0x1
0x1
RW
RW
RW
0
1
0
1
0
1
Rev. A | Page 52 of 64
Data Sheet
ADAU1977
DIAGNOSTICS REPORT REGISTER CHANNEL 1
Address: 0x11, Reset: 0x00, Name: DIAG_STATUS1
Table 42. Bit Descriptions for DIAG_STATUS1
Bits
Bit Name
Settings
Description
Reset
0x0
Access
RW
7
RESERVED
MIC_SHORT1
Reserved.
6
Mic Terminals Shorted.
Normal Operation
Mic Terminals Shorted
Mic Open Connection.
Normal Operation
Mic Open Connection
Mic High Shorted to Supply.
Normal Operation
Mic High Shorted to Supply
Mic High Shorted to Ground.
Normal Operation
Mic High Shorted to Ground
Mic High Shorted to MICBIAS.
Normal Operation
Mic High Shorted to MICBIAS
Mic Low Shorted to Supply.
Normal Operation
Mic Low Shorted to Supply
Mic Low Shorted to Ground.
Normal Operation
0x0
R
0
1
5
4
3
2
1
0
MICH_OPEN1
MICH_SB1
MICH_SG1
MICH_SMB1
MICL_SB1
0x0
0x0
0x0
0x0
0x0
0x0
R
R
R
R
R
R
0
1
0
1
0
1
0
1
0
1
MICL_SG1
0
1
Mic Low Shorted to Ground
Rev. A | Page 53 of 64
ADAU1977
Data Sheet
DIAGNOSTICS REPORT REGISTER CHANNEL 2
Address: 0x12, Reset: 0x00, Name: DIAG_STATUS2
Table 43. Bit Descriptions for DIAG_STATUS2
Bits
Bit Name
Settings
Description
Reset
0x0
Access
RW
7
RESERVED
MIC_SHORT2
Reserved.
6
Mic Terminals Shorted.
Normal Operation
Mic Terminals Shorted
Mic Open Connection.
Normal Operation
Mic Open Connection
Mic High Shorted to Supply.
Normal Operation
Mic High Shorted to Supply
Mic High Shorted to Ground.
Normal Operation
Mic High Shorted to Ground
Mic High Shorted to MICBIAS.
Normal operation
Mic High Shorted to MICBIAS
Mic Low Shorted to Supply.
Normal Operation
Mic Low Shorted to Supply
Mic Low Shorted to Ground.
Normal Operation
0x0
R
0
1
5
4
3
2
1
0
MIC_OPEN2
MICH_SB2
MICH_SG2
MICH_SMB2
MICL_SB2
MICL_SG2
0x0
0x0
0x0
0x0
0x0
0x0
R
R
R
R
R
R
0
1
0
1
0
1
0
1
0
1
0
1
Mic Low Shorted to Ground
Rev. A | Page 54 of 64
Data Sheet
ADAU1977
DIAGNOSTICS REPORT REGISTER CHANNEL 3
Address: 0x13, Reset: 0x00, Name: DIAG_STATUS3
Table 44. Bit Descriptions for DIAG_STATUS3
Bits
Bit Name
Settings
Description
Reset
0x0
Access
RW
7
RESERVED
MIC_SHORT3
Reserved.
6
Mic Terminals Shorted.
Normal Operation
Mic Terminals Shorted
Mic Open Connection.
Normal Operation
Mic Open Connection
Mic High Shorted to Supply.
Normal Operation
Mic High Shorted to Supply
Mic High Shorted to Ground.
Normal Operation
Mic High Shorted to Ground
Mic High Shorted to MICBIAS.
Normal Operation
Mic High Shorted to MICBIAS
Mic Low Shorted to Supply.
Normal Operation
Mic Low Shorted to Supply
Mic Low Shorted to Ground.
Normal Operation
0x0
R
0
1
5
4
3
2
1
0
MIC_OPEN3
MICH_SB3
MICH_SG3
MICH_SMB3
MICL_SB3
MICL_SG3
0x0
0x0
0x0
0x0
0x0
0x0
R
R
R
R
R
R
0
1
0
1
0
1
0
1
0
1
0
1
Mic Low Shorted to Ground
Rev. A | Page 55 of 64
ADAU1977
Data Sheet
DIAGNOSTICS REPORT REGISTER CHANNEL 4
Address: 0x14, Reset: 0x00, Name: DIAG_STATUS4
Table 45. Bit Descriptions for DIAG_STATUS4
Bits
Bit Name
Settings
Description
Reset
0x0
Access
RW
7
RESERVED
MIC_SHORT4
Reserved.
6
Mic Terminals Shorted.
Normal Operation
Mic Terminals Shorted
Mic Open Connection.
Normal Operation
Mic Open Connection
Mic High Shorted to Supply.
Normal Operation
Mic High Shorted to Supply
Mic High Shorted to Ground.
Normal Operation
Mic High Shorted to Ground
Mic High Shorted to MICBIAS.
Normal Operation
Mic High Shorted to MICBIAS
Mic Low Shorted to Supply.
Normal Operation
Mic Low Shorted to Supply
Mic Low Shorted to Ground.
Normal Operation
0x0
R
0
1
5
4
3
2
1
0
MIC_OPEN4
MICH_SB4
MICH_SG4
MICH_SMB4
MICL_SB4
MICL_SG4
0x0
0x0
0x0
0x0
0x0
0x0
R
R
R
R
R
R
0
1
0
1
0
1
0
1
0
1
0
1
Mic Low Shorted to Ground
Rev. A | Page 56 of 64
Data Sheet
ADAU1977
DIAGNOSTICS INTERRUPT PIN CONTROL REGISTER 1
Address: 0x15, Reset: 0x20, Name: DIAG_IRQ1
Table 46. Bit Descriptions for DIAG_IRQ1
Bits
Bit Name
RESERVED
IRQ_RESET
Settings
Description
Reset
0x0
Access
RW
7
Reserved.
6
FAULT Pin Reset.
0x0
RW
0
1
Normal Operation
Reset FAULT Pin
5
4
3
2
1
0
IRQ_DRIVE
FAULT Pin Drive Options.
FAULT Pin Always Driven
FAULT Pin Only Driven During Fault, Otherwise High-Z
FAULT Pin Polarity.
Faults Set FAULT Pin Low
0x1
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
0
1
IRQ_POL
0
1
Faults Set FAULT Pin High
DIAG_MASK4
DIAG_MASK3
DIAG_MASK2
DIAG_MASK1
FAULT Pin Mask for All Channel 4 Faults.
Faults on Channel 4 Trigger FAULT Pin
Faults on Channel 4 Do Not Trigger FAULT Pin
FAULT Pin Mask for All Channel 3 Faults.
Faults on Channel 3 Trigger FAULT Pin
Faults on Channel 3 Do Not Trigger FAULT Pin
FAULT Pin Mask for All Channel 2 Faults.
Faults on Channel 2 Trigger FAULT Pin
Faults on Channel 2 Do Not Trigger FAULT Pin
FAULT Pin Mask for All Channel 1 Faults.
Faults on Channel 1 Trigger FAULT Pin
Faults on Channel 1 Do Not Trigger FAULT Pin
0
1
0
1
0
1
0
1
Rev. A | Page 57 of 64
ADAU1977
Data Sheet
DIAGNOSTICS INTERRUPT PIN CONTROL REGISTER 2
Address: 0x16, Reset: 0x00, Name: DIAG_IRQ2
Table 47. Bit Descriptions for DIAG_IRQ2
Bits
Bit Name
Settings
Description
Reset
Access
7
BST_FAULT_MASK
FAULT Pin Mask for Boost Faults.
Boost Faults Assert FAULT Pin
Boost Faults Do Not Assert FAULT Pin
FAULT Pin Mask for Mic Terminal Short Fault.
Faults Trigger FAULT Pin
Faults Do Not Trigger FAULT Pin
FAULT Pin Mask for Mic Open Connection Fault.
Faults Trigger FAULT Pin
Faults Do Not Trigger FAULT Pin
FAULT Pin Mask for Mic High Short to Supply Fault.
Faults Trigger FAULT Pin
Faults Do Not Trigger FAULT Pin
FAULT Pin Mask for Mic High Short to Ground Fault.
Faults Trigger FAULT Pin
Faults Do Not Trigger FAULT Pin
FAULT Pin Mask for Mic Low Short to Supply Fault.
Faults Trigger FAULT Pin
Faults Do Not Trigger FAULT Pin
FAULT Pin Mask for Mic Low Short to Ground Fault.
Faults Trigger FAULT Pin
0x0
RW
0
1
6
5
4
3
1
0
MIC_SHORT_MASK
MIC_OPEN_MASK
MICH_SB_MASK
MICH_SG_MASK
MICL_SB_MASK
MICL_SG_MASK
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
0
1
0
1
0
1
0
1
0
1
0
1
Faults Do Not Trigger FAULT Pin
Rev. A | Page 58 of 64
Data Sheet
ADAU1977
DIAGNOSTICS ADJUSTMENTS REGISTER 1
Address: 0x17, Reset: 0x00, Name: DIAG_ADJUST1
Table 48. Bit Descriptions for DIAG_ADJUST1
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
SHT_T_TRIP
Short Fault to Other Terminal Trip Point Adjust.
00 0.465 × MICBIAS to 0.535 × MICBIAS
01 0.483 × MICBIAS to 0.517 × MICBIAS
10 0.429 × MICBIAS to 0.571 × MICBIAS
11 Reserved
0x0
RW
[5:4]
[3:2]
[1:0]
SHT_M_TRIP
SHT_G_TRIP
SHT_B_TRIP
Short Fault to Mic Bias Trip Point Adjust.
00 0.95 × MICBIAS
01 0.9 × MICBIAS
10 0.85 × MICBIAS
11 0.975 × MICBIAS
0x0
0x0
0x0
RW
RW
RW
Short Fault to Ground Trip Point Adjust.
00 0.2 × VREF
01 0.133 × VREF
10 0.1 × VREF
11 0.266 × VREF
Short Fault to Supply/Battery Trip Point Adjust.
00 0.95 × VBAT
01 0.9 × VBAT
10 0.85 × VBAT
11 0.975 × VBAT
Rev. A | Page 59 of 64
ADAU1977
Data Sheet
DIAGNOSTICS ADJUSTMENTS REGISTER 2
Address: 0x18, Reset: 0x20, Name: DIAG_ADJUST2
Table 49. Bit Descriptions for DIAG_ADJUST2
Bits
[7:6]
[5:4]
Bit Name
RESERVED
FAULT_TO
Settings
Description
Reset
0x0
Access
RW
Reserved.
Fault Timeout Adjust.
0x2
RW
00 No Fault Timeout Period (That Is, the Time That the Fault Needs to Persist
Before Being Reported)
01 50 ms Fault Timeout Period
10 100 ms Fault Timeout Period (Default)
11 150 ms Fault Timeout Period
Reserved.
3
2
RESERVED
0x0
0x0
RW
RW
HYST_SM_EN
Hysteresis Short to MICBIAS Enable.
0
1
Disable
Enable
1
0
HYST_SG_EN
HYST_SB_EN
Hysteresis Short to Ground Enable.
Disable
Enable
0x0
0x0
RW
RW
0
1
Hysteresis Short to Battery Enable.
0
1
Disable
Enable
Rev. A | Page 60 of 64
Data Sheet
ADAU1977
ADC CLIPPING STATUS REGISTER
Address: 0x19, Reset: 0x00, Name: ASDC_CLIP
Table 50. Bit Descriptions for ASDC_CLIP
Bits
[7:4]
3
Bit Name
RESERVED
ADC_CLIP4
Settings
Description
Reset
0x0
Access
RW
Reserved.
ADC Channel 4 Clip Status.
Normal Operation
ADC Channel Clipping
ADC Channel 3 Clip Status.
Normal Operation
ADC Channel Clipping
ADC Channel 2 Clip Status.
Normal Operation
ADC Channel Clipping
ADC Channel 1 Clip Status.
Normal Operation
0x0
R
0
1
2
1
0
ADC_CLIP3
ADC_CLIP2
ADC_CLIP1
0x0
0x0
0x0
R
R
R
0
1
0
1
0
1
ADC Channel Clipping
Rev. A | Page 61 of 64
ADAU1977
Data Sheet
DIGITAL DC HIGH-PASS FILTER AND CALIBRATION REGISTER
Address: 0x1A, Reset: 0x00, Name: DC_HPF_CAL
Table 51. Bit Descriptions for DC_HPF_CAL
Bits
Bit Name
Settings
Description
Reset
Access
7
DC_SUB_C4
Channel 4 DC Subtraction from Calibration.
No DC Subtraction
DC Value from DC Calibration Is Subtracted
Channel 3 DC Subtraction from Calibration.
No DC Subtraction
DC Value from DC Calibration Is Subtracted
Channel 2 DC Subtraction from Calibration.
No DC Subtraction
DC Value from DC Calibration Is Subtracted
Channel 1 DC Subtraction from Calibration.
No DC Subtraction
0x0
RW
0
1
6
5
4
3
2
1
0
DC_SUB_C3
DC_SUB_C2
DC_SUB_C1
DC_HPF_C4
DC_HPF_C3
DC_HPF_C2
DC_HPF_C1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
RW
0
1
0
1
0
1
DC Value from DC Calibration Is Subtracted
Channel 4 DC High-Pass Filter Enable.
HPF Off
0
1
HPF On
Channel 3 DC High-Pass Filter Enable.
HPF Off
HPF On
0
1
Channel 2 DC High-Pass Filter Enable.
HPF Off
HPF On
0
1
Channel 1 DC High-Pass Filter Enable.
HPF Off
HPF On
0
1
Rev. A | Page 62 of 64
Data Sheet
ADAU1977
APPLICATIONS CIRCUIT
+3.3V
10µF
MLCC X7R
C12
0.1µF
C13
0.1µF
C11
0.1µF
C14
0.1µF
C10
10µF
MLCC X7R
DVDD
BOOST
CONVERTER
50mA
MICBIAS
5V TO 9V
3.3V TO 1.8V
REGULATOR
C9
C15
0.1µF
C16
I
OUT
R
10µF ELECTROLYTIC
1nF MAX MLCC
EXT
10µF
MLCC X7R
ADAU1977
PROG
BIAS
R1
R3
PGND
+1.8V OR +3.3V
IOVDD
C7
0.1µF
AIN1+
AIN1–
AIN2+
AIN2–
AIN3+
AIN3–
AIN4+
AIN4–
MIC1
ADC
ADC
ADC
ADC
V
V
= 2V DIFF
AC
LRCLK
BCLK
SDATAOUT1
SDATAOUT2
MIC2
= 2V DIFF
AC
TO DSP
LINE1
V
= 7V, V = 10V DIFF
CM
AC
LINE2
IOVDD
V
= 7V, V = 10V DIFF
CM
AC
VBAT
AGND1
AVDD2
AGND3
AVDDx
C1 C2 C3 C4 C5 C6 C7 C8 R2
R4
SCL/CCLK
SDA/COUT
ADDR1/CIN
ADDR0/CLATCH
FAULT
DIAGNOSTICS
C1 TO C8 = 1000pF
R1 TO R4 TYP = 500Ω ±0.1%
BG
REF
I2C/SPI
CONTROL
MICRO-
CONTROLLER
PLL
AGNDx
MB_GND
PD/RESET
AGND2
AGND2
R13
R14
C18
10µF
C19
0.1µF
C21
R17
C20
+3.3V (AVDD2)
NOTES
1. R9, R10, R15 = TYPICAL 2kΩ FOR IOVDD = 3.3V, 1kΩ FOR 1.8V.
2. R11 THROUGH R14 USED FOR SETTING THE DEVICE IN I C MODE.
3. R16 = TYPICAL 47kΩ FOR IOVDD = 3.3V, 22kΩ FOR 1.8V.
4. PLL LOOP FILTER:
2
PLL INPUT OPTION
LRCLK
MCLK
R17
C20
C21
4.87kΩ
2200pF
39nF
1kΩ
390pF
5600pF
5. FOR MORE INFORMATION ABOUT CALCULATING THE VALUE OF R
, SEE THE POWER-ON RESET SEQUENCE SECTION.
EXT
Figure 46. Typical Application Schematic—Two Microphones, Two Line Inputs, I2C and I2S Mode
Rev. A | Page 63 of 64
ADAU1977
Data Sheet
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
31
30
40
1
0.50
BSC
4.05
3.90 SQ
3.75
EXPOSED
PAD
21
20
10
11
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 47. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature Range
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Package Description
Package Option
ADAU1977WBCPZ
ADAU1977WBCPZ-R7
ADAU1977WBCPZ-RL
EVAL-ADAU1977Z
40-Lead LFCSP_WQ
CP-40-14
CP-40-14
CP-40-14
40-Lead LFCSP_WQ, 7” Tape and Reel
40-Lead LFCSP_WQ, 13”Tape and Reel
Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADAU1977W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain
the specific Automotive Reliability reports for these models.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
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D10296-0-3/13(A)
Rev. A | Page 64 of 64
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SI9130DB
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SI9136_11
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SI9130_11
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SI9137
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
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