ADBMS1818 [ADI]
18-Cell Battery Monitor with Daisy Chain Interface;
| 型号： | ADBMS1818 |
| 厂家： | 
ADI |
| 描述： | 18-Cell Battery Monitor with Daisy Chain Interface 电池 |
| 文件： | 总89页 (文件大小：5941K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
ADBMS1818
18-Cell Battery Monitor with Daisy Chain Interface
► 9 general-purpose digital I/O or analog inputs
► Temperature or other sensor inputs
► Configurable as an I2C or SPI master
► 6 µA sleep mode supply current
► 64-lead eLQFP package
FEATURES
► Measures up to 18 battery cells in series
► 3 mV maximum total measurement error
► Stackable architecture for high voltage systems
► Built-in isoSPI interface
► 1 Mb isolated serial communications
APPLICATIONS
► Uses a single twisted pair, up to 100 meters
► Low EMI susceptibility and emissions
► Bidirectional for broken wire protection
► 290 µs to measure all cells in a system
► Synchronized voltage and current measurement
► 16-bit Δ-Σ ADC with programmable third-order noise filter
► Backup battery systems
► Grid energy storage
► Residential energy storage
► UPS
► High power portable equipment
► Passive cell balancing up to 200 mA (maximum) with program-
mable pulse‑width modulation
GENERAL DESCRIPTION
The ADBMS1818 is a multicell battery stack monitor that measures
up to 18 series connected battery cells with a total measurement
error (TME) of less than 3.0 mV. The cell measurement range
of 0 V to 5 V makes the ADBMS1818 suitable for most battery
chemistries. All 18 cells can be measured in 290 µs, and lower data
acquisition rates can be selected for high noise reduction.
TYPICAL APPLICATION CIRCUIT
Multiple ADBMS1818 devices can be connected in series, permit-
ting simultaneous cell monitoring of long, high voltage battery
™
strings. Each ADBMS1818 has an isoSPI interface for high
Figure 1. Typical Application Circuit
speed, RF immune, long distance communications. Multiple devi-
ces are connected in a daisy chain with one host processor connec-
tion for all devices. This daisy chain can be operated bidirectionally,
ensuring communication integrity, even in the event of a fault along
the communication path.
The ADBMS1818 can be powered directly from the battery stack or
from an isolated supply. The ADBMS1818 includes passive balanc-
ing for each cell, with individual pulse-width modulation (PWM) duty
cycle control for each cell. Other features include an on-board 5 V
regulator, nine general-purpose I/O lines, and a sleep mode, where
current consumption is reduced to 6 µA.
Figure 2. Cell 18 Measurement Error vs. Temperature
All registered trademarks and trademarks are the property of their
respective owners. Protected by U.S. patents, including 8908779,
9182428, and 9270133.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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Data Sheet
ADBMS1818
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
General Description...............................................1
Typical Application Circuit......................................1
Specifications........................................................ 3
ADC DC Specifications...................................... 3
Voltage Reference Specifications.......................4
General DC Specifications................................. 5
ADC Timing Specifications.................................6
SPI DC Specifications........................................ 7
IsoSPI DC Specifications................................... 7
IsoSPI Idle/Wake-Up Specifications...................8
IsoSPI Pulse Timing Specifications....................8
SPI Timing Requirements.................................. 8
isoSPI Timing Specifications..............................9
Absolute Maximum Ratings.................................10
ESD Caution.....................................................10
Pin Configuration and Function Descriptions.......11
Typical Performance Characteristics...................13
Functional Block Diagram....................................19
Improvements from the LTC6811-1..................... 20
Theory of Operation.............................................21
State Diagram.................................................. 21
ADBMS1818 Core State Descriptions..............21
isoSPI State Descriptions.................................22
Power Consumption.........................................22
ADC Operation.................................................23
Data Acquisition System Diagnostics...............29
Watchdog and Discharge Timer.......................35
S Pin Pulse-Width Modulation for Cell
Balancing........................................................36
Discharge Timer Monitor..................................37
I2C/SPI Master on ADBMS1818 Using
GPIOs.............................................................37
S Pin Pulsing Using the S Pin Control
Settings.......................................................... 41
S Pin Muting.....................................................43
Serial Interface Overview................................. 43
4-Wire Serial Peripheral Interface (SPI)
Physical Layer................................................43
2-Wire Isolated Interface (isoSPI) Physical
Layer.............................................................. 43
Data Link Layer................................................ 53
Network Layer.................................................. 53
Memory Map........................................................61
Applications Information...................................... 68
Providing DC Power.........................................68
Internal Protection and Filtering....................... 68
Cell Balancing.................................................. 72
Discharge Control During Cell
Measurements................................................74
Digital Communications....................................75
Enhanced Applications.....................................83
Reading External Temperature Probes............ 85
Typical Application...............................................86
Related Devices.................................................. 87
Outline Dimensions............................................. 88
Ordering Guide.................................................89
analog.com
Rev. 0 | 2 of 89
Data Sheet
ADBMS1818
SPECIFICATIONS
Specifications are at TA = 25°C, unless otherwise noted. The test conditions are V+ = 59.4 V and VREG = 5.0 V, unless otherwise noted. The
ISOMD pin is tied to the V– pin, unless otherwise noted.
ADC DC SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Measurement Resolution
ADC Offset Voltage1
ADC Gain Error 1
0.1
mV/Bit
mV
%
0.1
0.01
±0.2
TME in Normal Mode
C(n) to C(n–1), GPIO(n) to V– = 0
C(n) to C(n–1) = 2.0
C(n) to C(n–1), GPIO(n) to V– = 2.0, apply over the full specified temperature
mV
mV
mV
±2.6
±2.8
range
C(n) to C(n–1) = 3.3
C(n) to C(n–1), GPIO(n) to V– = 3.3, apply over the full specified temperature
±3.0
±4.0
mV
mV
range
C(n) to C(n–1) = 4.2
C(n) to C(n–1), GPIO(n) to V– = 4.2, apply over the full specified temperature
±3.8
±4.8
mV
mV
range
C(n) to C(n–1), GPIO(n) to V– = 5.0
±1
mV
%
Sum of all cells, apply over the full specified temperature range
Internal temperature, T = maximum specified temperature
VREG pin, apply over the full specified temperature range
VREF2 pin, apply over the full specified temperature range
Digital supply voltage, VREGD, apply over the full specified temperature range
C(n) to C(n–1), GPIO(n) to V– = 0
±0.05
±5
±0.35
°C
%
–1
–0.15
0.05
0.5
0
–0.05
–0.5
0.20
1.5
%
%
TME in Filtered Mode
±0.1
mV
mV
mV
C(n) to C(n–1) = 2.0
C(n) to C(n–1), GPIO(n) to V– = 2.0, apply over the full specified temperature
±1.6
±1.8
range
C(n) to C(n–1) = 3.3
C(n) to C(n–1), GPIO(n) to V– = 3.3, apply over the full specified temperature
±2.2
±3.0
mV
mV
range
C(n) to C(n–1) = 4.2
C(n) to C(n–1), GPIO(n) to V– = 4.2, apply over the full specified temperature
±2.8
±3.8
mV
mV
range
C(n) to C(n–1), GPIO(n) to V– = 5.0
±1
mV
%
Sum of all cells, apply over the full specified temperature range
Internal temperature, T = maximum specified temperature
VREG pin, apply over the full specified temperature range
VREF2 pin, apply over the full specified temperature range
Digital supply voltage, VREGD, apply over the full specified temperature range
C(n) to C(n–1), GPIO(n) to V– = 0
C(n) to C(n–1), GPIO(n) to V– = 2.0, apply over the full specified temperature
range
C(n) to C(n–1), GPIO(n) to V– = 3.3, apply over the full specified temperature
range
C(n) to C(n–1), GPIO(n) to V– = 4.2, apply over the full specified temperature
±0.05
±5
±0.35
°C
%
–1
–0.15
0.05
0.8
0
–0.05
–0.5
0.20
1.5
%
%
TME in Fast Mode
±2
mV
mV
±6.5
±8.5
±12.5
mV
mV
range
C(n) to C(n–1), GPIO(n) to V– = 5.0
±10
mV
%
Sum of all cells, apply over the full specified temperature range
Internal temperature, T = maximum specified temperature
VREG pin, apply over the full specified temperature range
±0.15
±5
±0.5
1
°C
%
–1.5
–0.15
analog.com
Rev. 0 | 3 of 89
Data Sheet
ADBMS1818
SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VREF2 pin, apply over the full specified temperature range
–0.18
–2.5
0.05
–0.4
0.32
2
%
%
V
Digital supply voltage, VREGD, apply over the full specified temperature range
C(n), n = 1 to 18, apply over the full specified temperature range
Input Range
C(n–1)
C(n–1)
+ 5
C0, apply over the full specified temperature range
0
0
1
V
GPIO(n), n = 1 to 9, apply over the full specified temperature range
C(n), n = 0 to 18, apply over the full specified temperature range
5
V
Input Leakage Current (IL) When Inputs Are Not
Being Measured
10
±250
nA
GPIO(n), n = 1 to 9, apply over the full specified temperature range
C(n), n = 0 to 18
10
±1
±250
130
nA
μA
Input Current When Inputs Are Being Measured
(State: Core = Measure)
GPIO(n), n = 1 to 9
±1
μA
μA
Input Current During Open Wire Detection
Apply over the full specified temperature range
70
100
1
The ADC specifications are guaranteed by the TME specification.
VOLTAGE REFERENCE SPECIFICATIONS
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
1st Reference Voltage (VREF1
)
VREF1 pin, no load, apply over the full specified temperature
range
3.0
3.15
3.3
V
1st Reference Voltage Temperature Coefficient
(TC)
VREF1 pin, no load
3
ppm/°C
1st Reference Voltage Thermal Hysteresis
1st Reference Voltage Long Term Drift
VREF1 pin, no load
VREF1 pin, no load
20
20
3
ppm
ppm/√KHR
V
2nd Reference Voltage (VREF2
)
VREF2 pin, no load, apply over the full specified temperature
range
VREF2 pin, 5 kΩ load to V−, apply over the full specified
2.993
2.992
3.007
3.008
3
V
temperature range
2nd Reference Voltage TC
VREF2 pin, no load
VREF2 pin, no load
VREF2 pin, no load
10
ppm/°C
ppm
2nd Reference Voltage Thermal Hysteresis
2nd Reference Voltage Long Term Drift
100
60
ppm/√KHR
analog.com
Rev. 0 | 4 of 89
Data Sheet
ADBMS1818
SPECIFICATIONS
GENERAL DC SPECIFICATIONS
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
V+ Supply Current (IVP) (See Figure 53)
State: core = sleep, isoSPI = idle, VREGD = 0 V
6.1
6.1
11
18
µA
µA
State: core = sleep, isoSPI = idle, VREGD = 0 V , apply over
the full specified temperature range
State: core = sleep, isoSPI = idle, VREGD = 5 V
3
3
5
9
µA
µA
State: core = sleep, isoSPI = idle, VREGD = 5 V , apply over
the full specified temperature range
State: core = standby
9
6
14
14
22
28
µA
µA
State: core = standby, apply over the full specified
temperature range
State: core = REFUP
0.4
0.55
0.55
0.8
mA
mA
State: core = REFUP, apply over the full specified
temperature range
0.375
0.825
State: core = measure
0.65
0.6
0.95
0.95
1.35
1.4
mA
mA
State: core = measure, apply over the full specified
temperature range
VREG Supply Current (IREG(CORE)) (See Figure 53) State: core = sleep, isoSPI = idle, VREGD = 5 V
3.1
3.1
6
9
µA
µA
State: core = sleep, isoSPI = idle, VREGD = 5 V, apply over
the full specified temperature range
State: core = standby
10
6
35
35
60
65
µA
µA
State: core = standby, apply over the full specified
temperature range
State: core = REFUP
0.4
0.3
0.9
0.9
1.4
1.5
mA
mA
State: core = REFUP, apply over the full specified
temperature range
State: core = measure
14
15
15
16
mA
mA
State: core = measure, apply over the full specified
temperature range
13.5
16.5
Additional VREG Supply Current If isoSPI Is in
Ready/Active States (IREG(isoSPI)
Note: Active State Current Assumes tCLK = 1 µs 1
ISOMD = 0, RB1 + RB2 = 2 kΩ, ready, apply over the full
specified temperature range
3.6
5.6
4.0
7.0
1.0
1.3
1.6
1.8
16
4.5
6.8
5.2
8.5
1.8
2.3
2.5
3.1
60
5.2
8.1
6.5
10.5
2.4
3.3
3.5
4.8
90
mA
mA
mA
mA
mA
mA
mA
mA
V
)
ISOMD = 0, RB1 + RB2 = 2 kΩ, active, apply over the full
specified temperature range
ISOMD = 1, RB1 + RB2 = 2 kΩ, ready, apply over the full
specified temperature range
ISOMD = 1, RB1 + RB2 = 2 kΩ, active, apply over the full
specified temperature range
ISOMD = 0, RB1 + RB2 = 20 kΩ, ready, apply over the full
specified temperature range
ISOMD = 0, RB1 + RB2 = 20 kΩ, active, apply over the full
specified temperature range
ISOMD = 1, RB1 + RB2 = 20 kΩ, ready, apply over the full
specified temperature range
ISOMD = 1, RB1 + RB2 = 20 kΩ, active, apply over the full
specified temperature range
V+ Supply Voltage
V+ to C18 Voltage
V+ to C12 Voltage
TME specifications met, apply over the full specified
temperature range
TME specifications met, apply over the full specified
temperature range
–0.3
V
TME specifications met, apply over the full specified
temperature range
40
V
analog.com
Rev. 0 | 5 of 89
Data Sheet
ADBMS1818
SPECIFICATIONS
Table 3.
Parameter
C13 Voltage
Test Conditions/Comments
Min
Typ
Max
Unit
TME specifications met, apply over the full specified
temperature range
2.5
V
C7 Voltage
TME specifications met, apply over the full specified
temperature range
1
V
V
VREG Supply Voltage (VREG
DRIVE Output Voltage
)
TME supply rejection < 1 mV/V, apply over the full specified
temperature range
4.5
5
5.5
Sourcing 1 µA
5.4
5.2
5.7
5.7
5.9
6.1
V
V
Sourcing 1 µA, apply over the full specified temperature
range
Sourcing 500 µA, apply over the full specified temperature
range
5.1
2.7
5.7
6.1
V
Digital Supply Voltage (VREGD
)
Apply over the full specified temperature range
3
3.6
10
V
Discharge Switch On Resistance
Thermal Shutdown Temperature
Watchdog Timer Pin Low (VOL(WDT)
VCELL = 3.6 V, apply over the full specified temperature range
4
Ω
°C
V
150
)
WDT pin sinking 4 mA, apply over the full specified
temperature range
0.4
0.4
General-Purpose I/O Pin Low (VOL(GPIO)
)
GPIO pin sinking 4 mA (used as digital output), apply over
the full specified temperature range
V
1
The active state current is calculated from dc measurements. The active state current is the additional average supply current into VREG when there are continuous 1 MHz
communications on the isoSPI ports with 50% data 1s and 50% data 0s. Slower clock rates reduce the supply current.
ADC TIMING SPECIFICATIONS
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
(tCYCLE) (See Figure 55, Figure 56, and Figure 58)
Measurement and Calibration Cycle Time When
Starting from the REFUP State in Normal Mode
Measure 18 cells, apply over the full specified temperature
range
2027
2343
2488
µs
Measure 3 cells, apply over the full specified temperature range 352
407
432
µs
µs
Measure 18 cells and 2 GPIO inputs, apply over the full
specified temperature range
2717
3140
3335
Measurement and Calibration Cycle Time When
Starting from the REFUP State in Filtered Mode
Measure 18 cells, apply over the full specified temperature
range
174.2
201.3
213.8
ms
Measure 3 cells, apply over the full specified temperature range 29.1
33.6
35.7
ms
ms
Measure 18 cells and 2 GPIO inputs, apply over the full
specified temperature range
232.3
268.5
285.1
Measurement and Calibration Cycle Time When
Starting from the REFUP State in Fast Mode
Measure 18 cells, apply over the full specified temperature
range
970
1121
1191
µs
Measure 3 cells, apply over the full specified temperature range 176
203
215
µs
µs
Measure 18 cells and 2 GPIO inputs, apply over the full
specified temperature range
1307
1511
1605
Skew Time (tSKEW1). The Time Difference
Between Cell 18 and GPIO1 Measurements,
Command = ADCVAX (See Figure 58)
Fast mode, apply over the full specified temperature range
Normal mode, apply over the full specified temperature range
168
470
194
543
206
577
µs
µs
Skew Time(tSKEW2). The Time Difference Between Fast mode, apply over the full specified temperature range
202
580
233
670
248
711
µs
µs
Cell 18 and Cell 1 Measurements, Command =
ADCV (See Figure 55)
Normal mode, apply over the full specified temperature range
Regulator Start-Up Time (tWAKE
)
VREG generated from the DRIVE pin (see Figure 84), apply over
the full specified temperature range
200
400
µs
analog.com
Rev. 0 | 6 of 89
Data Sheet
ADBMS1818
SPECIFICATIONS
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Watchdog or Discharge Timer (tSLEEP) (See Figure DTEN pin = 0 or DCTO, Bits[3:0] = 0000, apply over the full
1.8
2
2.2
sec
87)
specified temperature range
DTEN pin = 1 and DCTO, Bits[3:0] ≠ 0000
0.5
120
4.4
min
ms
Reference Wake-Up Time (tREFUP (See Figure
55)). Added to tCYCLE Time When Starting from
the Standby State. tREFUP = 0 When Starting from
Other States
tREFUP is independent of the number of channels measured and 2.7
the ADC mode, apply over the full specified temperature range
3.5
3.3
ADC Clock Frequency (fS)
MHz
SPI DC SPECIFICATIONS
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SPI Pin Digital Input Voltage High (VIH(SPI))
CSB, SCK, and SDI pins, apply over the full specified
temperature range
2.3
V
SPI Pin Digital Input Voltage Low （VIL(SPI)
)
CSB, SCK, and SDI pins, apply over the full specified
temperature range
0.8
V
Configuration Pin Digital Input Voltage High
(VIH(CFG)
Configuration Pin Digital Input Voltage Low
(VIL(CFG)
Digital Input Current (ILEAK(DIG)
ISOMD, DTEN, and GPIO1 to GPIO9 pins, apply over the full
specified temperature range
2.7
V
)
ISOMD, DTEN, and GPIO1 to GPIO9 pins, apply over the full
specified temperature range
1.2
±1
V
)
)
CSB, SCK, SDI, ISOMD, and DTEN pins, apply over the full
specified temperature range
μA
V
Digital Output Low (VOL(SDO)
)
SDO pin sinking 1 mA, apply over the full specified temperature
range
0.3
ISOSPI DC SPECIFICATIONS
See Figure 78.
Table 6.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Voltage on IBIAS Pin (VBIAS
)
Ready/active state, apply over the full specified temperature
range
1.9
2.0
2.1
V
Idle state
0
V
Isolated Interface Bias Current (IB)
Isolated Interface Current Gain (AIB
RBIAS = 2 kΩ to 20 kΩ, apply over the full specified temperature 0.1
range
1.0
22
mA
)
Transmitter pulse amplitude (VA) = ≤ 1.6 V, IB = 1 mA, apply
over the full specified temperature range
18
20
20
mA/mA
IB = 0.1 mA, apply over the full specified temperature range
18
24.5
1.6
mA/mA
V
Transmitter Pulse Amplitude (VA)
VA = IPx voltage (VIPx) – IMx voltage (VIMx), apply over the full
specified temperature range
Threshold-Setting Voltage on ICMP Pin (VICMP
)
Receiver comparator threshold voltage (VTCMP) = receiver
comparator threshold voltage gain (ATCMP) × VICMP, apply over
the full specified temperature range
0.2
1.5
V
Input Leakage Current on ICMP Pin (ILEAK (ICMP)
)
VICMP = 0 V to VREG, apply over the full specified temperature
range
±1
±1
0.6
µA
µA
V/V
Leakage Current on IPx and IMx Pins (ILEAK (IPx/
Idle state, VIPx or VIMx, 0 V to VREG, apply over the full specified
temperature range
)
IMx)
Receiver Comparator Threshold Voltage Gain
Receiver common-mode bias (VCM) = VREG/2 to VREG – 0.2 V,
VICMP = 0.2 V to 1.5 V, apply over the full specified temperature
range
0.4
0.5
(ATCMP
)
Receiver Common-Mode Bias (VCM
)
IPx and IMx not driving
(VREG – VICMP/3 – 167 mV)
V
analog.com
Rev. 0 | 7 of 89
Data Sheet
ADBMS1818
SPECIFICATIONS
Table 6.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Receiver Input Resistance (RIN
)
Single-ended to the IPA, IMA, IPB, and IMB pins, apply over
the full specified temperature range
26
35
45
kΩ
ISOSPI IDLE/WAKE-UP SPECIFICATIONS
See Figure 87.
Table 7.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Differential Wake-Up Voltage (VWAKE
)
Dwell time at VWAKE before wake detection (tDWELL) = 240 ns,
apply over the full specified temperature range
200
mV
tDWELL
VWAKE = 200 mV, apply over the full specified temperature
range
240
4.3
ns
Start-Up Time After Wake Detection (tREADY
)
Apply over the full specified temperature range
Apply over the full specified temperature range
10
µs
Idle Timeout Duration (tIDLE
)
5.5
6.7
ms
ISOSPI PULSE TIMING SPECIFICATIONS
See Figure 83.
Table 8.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Chip Select Half Pulse Width (t1/2PW(CS)
)
Transmitter, apply over the full specified temperature range
Receiver, apply over the full specified temperature range
Transmitter, apply over the full specified temperature range
Receiver, apply over the full specified temperature range
Transmitter, apply over the full specified temperature range
Receiver, apply over the full specified temperature range
Transmitter, apply over the full specified temperature range
Receiver, apply over the full specified temperature range
120
70
150
90
180
110
190
330
60
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select Signal Filter (tFILT(CS)
Chip Select Pulse Inversion Delay (tINV(CS)
Chip Select Valid Pulse Window (tWNDW(CS)
Data Half Pulse Width (t1/2PW(D)
Data Signal Filter (tFILT(D)
Data Pulse Inversion Delay (tINV(D)
Data Valid Pulse Window (tWNDW(D)
)
)
120
220
40
155
270
50
)
)
)
10
25
35
)
40
55
65
)
70
90
110
SPI TIMING REQUIREMENTS
See Figure 77 and Figure 86.
Table 9.
Parameter
Test Conditions/Comments
Min
Typ
Max
Units
1
SCK Period (tCLK
)
Apply over the full specified temperature range
Apply over the full specified temperature range
Apply over the full specified temperature range
1
µs
ns
ns
ns
SDI Setup Time Before SCK Rising Edge (t1)
SDI Hold Time After SCK Rising Edge (t2) d
SCK Low (t3)
25
25
200
tCLK = t3 + t4 ≥ 1 µs, apply over the full specified temperature
range
SCK High (t4)
tCLK = t3 + t4 ≥ 1 µs, apply over the full specified temperature
range
200
ns
CSB Rising Edge to CSB Falling Edge (t5)
SCK Rising Edge to CSB Rising Edge (t6) 1
CSB Falling Edge to SCK Rising Edge (t7) 1
Apply over the full specified temperature range
Apply over the full specified temperature range
Apply over the full specified temperature range
0.65
0.8
1
µs
µs
µs
1
These timing specifications are dependent on the delay through the cable and include allowances for 50 ns of delay in each direction. 50 ns corresponds to 10 m of Category 5
(CAT-5) cable (which has a velocity of propagation of 66% the speed of light). Using longer cables requires derating these specs by the amount of additional delay.
analog.com
Rev. 0 | 8 of 89
Data Sheet
ADBMS1818
SPECIFICATIONS
ISOSPI TIMING SPECIFICATIONS
See Figure 86.
Table 10.
Parameter
Test Conditions/Comments
Min
Typ
Max
Units
SCK Falling Edge to SDO Valid (t8)1
Apply over the full specified temperature range
Apply over the full specified temperature range
Apply over the full specified temperature range
Apply over the full specified temperature range
Apply over the full specified temperature range
Apply over the full specified temperature range
Apply over the full specified temperature range
60
ns
ns
ns
ns
ns
ns
ns
ns
SCK Rising Edge to Short ±1 Transmit (t9)
50
CSB Transition to Long ±1 Transmit (t10
)
60
1
CSB Rising Edge to SDO Rising (t11
Data Return Delay (tRTN
Chip-Select Daisy-Chain Delay (tDSY(CS)
Data Daisy-Chain Delay (tDSY(D)
Data Daisy-Chain Lag (vs. Chip Select) (tLAG
)
200
425
180
300
70
)
325
375
120
250
35
)
)
200
0
)
= (tDSY(D) + t1/2PW(D)) – (tDSY(CS) + t1/2PW(CS)), apply over the full
specified temperature range
Chip Select High to Low Pulse Governor (t5(GOV)
)
Apply over the full specified temperature range
Apply over the full specified temperature range
Apply over the full specified temperature range
0.6
0.8
2
0.82
1.05
10
µs
µs
µs
Data to Chip-Select Pulse Governor (t6(GOV)
)
isoSPI Port Reversal Blocking tBLOCK Window
1
These specifications do not include rise or fall time of SDO. Although fall time (typically 5 ns due to the internal pull-down transistor) is not a concern, the rising edge transition
time (tRISE) is dependent on the pull-up resistance and load capacitance on the SDO pin. The time constant must be chosen such that SDO meets the setup time requirements
of the microcontroller unit (MCU).
analog.com
Rev. 0 | 9 of 89
Data Sheet
ADBMS1818
ABSOLUTE MAXIMUM RATINGS
Table 11.
Table 11.
Parameter
Value
Parameter
Value
Total Supply Voltage, V+ to V–
Supply Voltage (Relative to C12), V+ to C12 50 V
Input Voltage (Relative to V–)
112.5 V
Storage Temperature Range
Device HBM ESD Classification
Device CDM ESD Classification
–65°C to 150°C
Level 1C
Level C5
C0
–0.3 V to 6 V
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.
C18
–0.3 V to MIN ( V+ + 5.5 V, 112.5 V)
–0.3 V to MIN (8 × n, 112.5 V)
–0.3 V to VREG + 0.3 V, ≤ 6 V
–0.3 V to 7 V
C(n), S(n)
IPA, IMA, IPB, and IMB
DRIVE
All Other Pins
–0.3 V to 6 V
Voltage Between Inputs
C(n) to C(n–1) and S(n) to C(n–1)
ESD CAUTION
–0.3 V to 8 V
–0.3 V to 21 V
C18 to C15, C15 to C12, C12 to C9, C9 to
C6, C6 to C3, and C3 to C0
ESD (electrostatic discharge) sensitive device. Charged devi-
ces and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Current In and Out of Pins
All Pins Except VREG, IPA, IMA, IPB, IMB,
C(n), and S(n)
10 m
IPA, IMA, IPB, and IMB
30 mA
Specified Junction Temperature Range
Junction Temperature
–40°C to 85°C
150°C
analog.com
Rev. 0 | 10 of 89
Data Sheet
ADBMS1818
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
V+
Positive Supply Pin.
Cell Inputs.
2, 4, 6, 8, 10, 12,
14, 16, 18, 20, 22,
24, 26, 28, 30, 32,
34, 36, 38
C0 to C18
3, 5, 7, 9, 11, 13,
15, 17, 19, 21, 23,
25, 27, 29, 31, 33,
35, 37
S1 to S18
Balance Inputs/Outputs. 18 internal N-channel metal-oxide semiconductor field effect transistors (MOSFETs) are connected between
S(n) and C(n–1) for discharging cells.
39 to 47
GPIO1 to GPIO9
General Purpose I/O. GPIO1 to GPIO9 can be used as digital inputs or digital outputs or as analog inputs with a measurement range
from V– to 5 V. GPIO3, GPIO4, and GPIO5 can be used as I2C or SPI ports.
48
VREG
5 V Regulator Input. Bypass with an external 1 μF capacitor.
Connect the base of an NPN transistor to the DRIVE pin. Connect the collector to V+ and the emitter to VREG
.
49
DRIVE
VREF2
VREF1
DTEN
50
Buffered 2nd Reference Voltage for Driving Multiple 10 kΩ Thermistors. Bypass with an external 1 μF capacitor.
ADC Reference Voltage. Bypass with an external 1 μF capacitor. No dc loads allowed.
Discharge Timer Enable. Connect DTEN to VREG to enable the discharge timer.
51
52
53, 54, 61, 62
SDI, SDO, CSB,
SCK
4-Wire SPI. Active low chip select (CSB), serial clock (SCK), and serial data in (SDI) are digital inputs. Serial data out (SDO) is an
open drain NMOS output pin. SDO requires a 5 kΩ pull-up resistor.
55
56
ISOMD
Serial Interface Mode. Connecting ISOMD to VREG configures Pin 53, Pin 54, Pin 61, and Pin 62 of the ADBMS1818 for 2-wire isoSPI
mode. Connecting ISOMD to V– configures the ADBMS1818 for 4-wire SPI mode.
WDT
Watchdog Timer Output Pin. This is an open drain negative metal-oxide semiconductor (NMOS) digital output. WDT can be left
disconnected or connected with a 1 M resistor to VREG. If the ADBMS1818 does not receive a valid command within 2 seconds, the
watchdog timer circuit resets the ADBMS1818 and the WDT pin goes high impedance.
57
IBIAS
Isolated Interface Current Bias. Tie IBIAS to V– through a resistor divider to set the interface output current level. When the isoSPI
interface is enabled, the IBIAS pin voltage is 2 V. The IPA and IMA or IPB and IMB output current drive is set to 20 times the current,
IB, sourced from the IBIAS pin.
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Rev. 0 | 11 of 89
Data Sheet
ADBMS1818
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 12. Pin Function Descriptions
Pin No.
Mnemonic
Description
58
ICMP
Isolated Interface Comparator Voltage Threshold Set. Tie ICMP to the resistor divider between IBIAS and V– to set the voltage
threshold of the isoSPI receiver comparators. The comparator thresholds are set to half the voltage on the ICMP pin.
59, 60
61, 62
63, 64
V–
Negative Supply Pins. The V– pins must be shorted together, external to the IC.
Isolated 2-Wire Serial Interface Port A. IMA (negative) and IPA (positive) are a differential input/output pair.
Isolated 2-Wire Serial Interface Port B. IMB (negative) and IPB (positive) are a differential input/output pair.
V–. The exposed pad must be soldered to the PCB.
IMA, IPA
IMB, IPB
Exposed Pad
Table 13. Serial Port Pins
Port
ISOMD = VREG
ISOMD = V–
Port B
IPB
IPB
(Pin 57, Pin 58, Pin 63, and Pin 64)
IMB
ICMP
IBIAS
NC
IMB
ICMP
IBIAS
SDO
SDI
Port A
(Pin 53, Pin 54, Pin 61, and Pin 62)
NC
IPA
SCK
CSB
IMA
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Rev. 0 | 12 of 89
Data Sheet
ADBMS1818
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Figure 8. Noise Filter Response
Figure 4. Measurement Noise vs. Input, Normal Mode
Figure 5. Measurement Noise vs. Input, Filtered Mode
Figure 6. Measurement Noise vs. Input, Fast Mode
Figure 9. Measurement Error vs. VREG
Figure 10. Measurement Error vs. V+
Figure 7. Measurement Error Due to IR Reflow
Figure 11. Top Cell Measurement Error vs. V+
analog.com
Rev. 0 | 13 of 89
Data Sheet
ADBMS1818
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 16. VREF1 and VREF2 Power-Up
Figure 12. Measurement Error vs. Common-Mode Voltage
Figure 17. VREG and VDRIVE Power-Up
Figure 13. Measurement Error Due to a VREG AC Disturbance
Figure 18. Typical Wake-Up Pulse Amplitude, VWAKE vs. Wake-Up Dwell Time,
tDWELL
Figure 14. Measurement Error Due to a V+ AC Disturbance (PSRR is Power
Supply Rejection Ratio)
Figure 19. Measurement Error vs. Temperature
Figure 15. Measurement Error Common-Mode Rejection Ratio (CMRR) vs.
Frequency
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Rev. 0 | 14 of 89
Data Sheet
ADBMS1818
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 24. GPIO Measurement Error vs. Input RC Values
Figure 20. Measurement Error vs. Input, Normal Mode
Figure 21. Measurement Error vs. Input, Filtered Mode
Figure 22. Measurement Error vs. Input, Fast Mode
Figure 25. Measurement Time vs. Temperature
Figure 26. Sleep Supply Current vs. V+
Figure 27. Standby Supply Current vs. V+
Figure 23. Cell Measurement Error vs. Input RC Values
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Rev. 0 | 15 of 89
Data Sheet
ADBMS1818
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 28. REFUP Supply Current vs. V+
Figure 29. Measure Supply Current vs. V+
Figure 30. VREF1 vs. Temperature
Figure 32. VREF2 and VREG Line Regulation
Figure 33. VREF2 and V+ Line Regulation
Figure 34. VREF2 Load Regulation (IOUT is Output Current)
Figure 35. VREF2 Change Due to IR Reflow
Figure 31. VREF2 vs. Temperature
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Rev. 0 | 16 of 89
Data Sheet
ADBMS1818
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 36. VDRIVE vs. Temperature
Figure 37. VDRIVE and V+ Line Regulation
Figure 38. VDRIVE Load Regulation
Figure 40. Increase in Die Temperature vs. Internal Discharge Current
Figure 41. Internal Die Temperature Measurement Error vs. Temperature
Figure 42. isoSPI Current (Ready) vs. Temperature
Figure 43. isoSPI Current (Active) vs. isoSPI Clock Frequency
Figure 39. Discharge Switch On Resistance vs. Cell Voltage
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Rev. 0 | 17 of 89
Data Sheet
ADBMS1818
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 44. IBIAS Pin Voltage vs. Temperature
Figure 48. isoSPI Driver Common-Mode Voltage (Port A and Port B) vs. Pulse
Amplitude
Figure 45. IBIAS Pin Voltage Load Regulation
Figure 49. isoSPI Comparator Threshold Gain (Port A and Port B) vs.
Receiver Common Mode
Figure 46. isoSPI Driver Current Gain (Port A and Port B) vs. IBIAS Current
Figure 50. isoSPI Comparator Threshold Gain (Port A and Port B) vs. ICMP
Voltage
Figure 47. isoSPI Driver Current Gain (Port A and Port B) vs. Temperature
Figure 51. isoSPI Comparator Threshold Gain (Port A and Port B) vs.
Temperature
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Rev. 0 | 18 of 89
Data Sheet
ADBMS1818
FUNCTIONAL BLOCK DIAGRAM
Figure 52. Functional Block Diagram
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Rev. 0 | 19 of 89
Data Sheet
ADBMS1818
IMPROVEMENTS FROM THE LTC6811-1
The ADBMS1818 is an evolution of the LTC6811-1 design. Table 14
summarizes the feature changes and additions in the ADBMS1818.
Table 14.
Additional ADBMS1818 Features
Benefits
Relevant Data Sheet Section(s)
The ADBMS1818 has 3 ADCs operating simultaneously
vs. 2 ADCs on the LTC6811-1.
3 cells can be measured during each conversion cycle.
ADC Operation
In addition to the 3 ADC Digital filters, there is a 4th filter
that is used for redundancy.
Checks that all digital filters are free of faults.
ADC Conversion with Digital Redundancy for a
description and PS, Bits[1:0] in Table 25
Measure Cell 7 with ADC1 and ADC2 simultaneously
and then measure Cell 13 with ADC2 and ADC3
simultaneously using the ADOL command.
Checks that ADC2 is as accurate as ADC1 and also
checks that ADC3 is as accurate as ADC2.
Overlap Cell Measurement (ADOL Command)
A monitoring feature can be enabled during the discharge Improved cell balancing.
timer. Cell balancing can be automatically terminated
when cell voltages reach a programmable undervoltage
threshold.
Discharge Timer Monitor
The internal discharge MOSFETs can provide 200 mA
of balancing current (80 mA if the die temperature is
over 85°C). The balancing current is independent of cell
voltage.
Faster cell balancing, especially for low cell voltages.
Cell Balancing with Internal MOSFETs
ADC DC Specifications
The C0 pin voltage is allowed to range between 0 V and 1 C0 does not have to connect directly to V–.
V without affecting the TME.
The mute and unmute commands allow the host to turn off Greater control of timing between S pins. Turning off and S Pin Muting
and turn on the discharge pins (S pins) without overwriting cell measurements.
register values.
Auxiliary measurements have an open-wire diagnostic
feature
Improved fault detection.
Auxiliary Open Wire Check (AXOW Command)
Four additional GPIO pins have been added for a total of
nine.
Increased number of temperature or other sensors that
can be measured.
Auxiliary (GPIO) Measurements (ADAX Command) and
Auxiliary Open Wire Check (AXOW Command)
A daisy chain of ADBMS1818s can operate in both
directions (both ports can be a master or slave).
Redundant communication path.
Reversible isoSPI
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Rev. 0 | 20 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
ADBMS1818 returns to the sleep state. If the discharge timer is
disabled, only the watchdog timer is relevant.
STATE DIAGRAM
The operation of the ADBMS1818 is divided into two separate
sections: the core circuit and the isoSPI circuit. Both sections have
an independent set of operating states, as well as a shutdown
timeout.
REFUP State
To reach this state, the REFON bit in Configuration Register Group
A must be set to 1 (using the WRCFGA command, see Table
50). The ADCs are off. The reference is powered up so that the
ADBMS1818 can initiate ADC conversions more quickly than from
the standby state.
ADBMS1818 CORE STATE DESCRIPTIONS
Sleep State
The reference and ADCs are powered down. The watchdog timer
(see the Watchdog and Discharge Timer section) has timed out.
The discharge timer is either disabled or timed out. The supply
currents are reduced to minimum levels. The isoSPI ports are in the
idle state. The DRIVE pin is 0 V.
When a valid ADC command is received, the IC goes to the
measure state to begin the conversion. Otherwise, the ADBMS1818
returns to the standby state when the REFON bit is set to 0, either
manually (using WRCFGA command) or automatically when the
watchdog timer expires (the ADBMS1818 then moves straight into
the sleep state if both timers are expired).
If a wake-up signal is received (see the Waking Up the Serial
Interface section), the ADBMS1818 enters the standby state.
Measure State
Standby State
The ADBMS1818 performs ADC conversions in the measure state.
The reference and ADCs are powered up.
The reference and the ADCs are off. The watchdog timer and/or
the discharge timer is running. The DRIVE pin powers the VREG
pin to 5 V through an external transistor. Alternatively, VREG can be
powered by an external supply.
After ADC conversions complete, the ADBMS1818 transitions to
either the REFUP or standby state, depending on the REFON bit.
Additional ADC conversions can be initiated more quickly by setting
REFON = 1 to take advantage of the REFUP state.
When a valid ADC command is received or the REFON bit is set
to 1 in Configuration Register Group A, the IC pauses for tREFUP to
allow the reference to power up and then enters either the REFUP
or measure state. Otherwise, if no valid commands are received for
tSLEEP (when both the watchdog and discharge timer expire), the
Note that non ADC commands do not cause a core state transition.
Only an ADC conversion or diagnostic commands place the core in
the measure state.
Figure 53. ADBMS1818 Operation State Diagram
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Data Sheet
ADBMS1818
THEORY OF OPERATION
ISOSPI STATE DESCRIPTIONS
POWER CONSUMPTION
The ADBMS1818 has two isoSPI ports (Port A and Port B) for
daisy-chain communication.
The ADBMS1818 is powered via two pins: V+ and VREG. The V+
input requires voltage greater than or equal to the top cell voltage
minus 0.3 V and provides power to the high voltage elements of
the core circuits. The VREG input requires 5 V and provides power
to the remaining core circuits and the isoSPI circuitry. The VREG
input can be powered through an external transistor, driven by the
regulated DRIVE output pin. Alternatively, VREG can be powered by
an external supply.
Idle State
In the idle state, the isoSPI ports are powered down.
When isoSPI Port A or Port B receives a wake-up signal (see the
Waking Up the Serial Interface section), the isoSPI enters the ready
state. This transition happens quickly (within tREADY) if the core is in
the standby state. If the core is in the sleep state when the isoSPI
receives a wake-up signal, the core transitions to the ready state
The power consumption varies according to the operational states.
Table 15 and Table 16 provide equations to approximate the supply
pin currents in each state. The V+ pin current depends only on the
core state. However, the VREG pin current depends on both the
core state and isoSPI state, and can therefore be divided into two
components. The isoSPI interface draws current only from the VREG
pin.
within tWAKE
.
Ready State
In the ready state, the isoSPI port(s) are ready for communication.
The serial interface current in the ready state depends on the status
of the ISOMD pin and RBIAS = RB1 + RB2 (the external resistors tied
to the IBIAS pin). If there is no activity (that is, no wake-up signal)
on Port A or Port B for greater than tIDLE, the ADBMS1818 enters
the idle state. When the serial interface is transmitting or receiving
data, the ADBMS1818 enters the active state.
IREG = IREG(CORE) + IREG(isoSPI)
In the sleep state, the VREG pin draws approximately 3.1 μA if
powered by an external supply. Otherwise, the V+ pin supplies the
necessary current.
Table 15. Core Supply Current
State
IVP
IREG(CORE)
Active State
Sleep
In the active state, the ADBMS1818 is transmitting and receiving
data using one or both of the isoSPI ports. The serial interface
consumes maximum power in the active state. The supply current
increases with clock frequency as the density of isoSPI pulses
increases.
VREG = 0 V
VREG = 5 V
Standby
REFUP
6.1 µA
3 µA
0 µA
3.1 µA
35 µA
900 µA
15 mA
14 µA
550 µA
950 µA
Measure
Table 16. isoSPI Supply Current Equations
isoSPI State
ISOMD Connection
IREG(isoSPI)
Idle
Not applicable
0 mA
Ready
VREG
V−
2.2 mA + 3 × IB
1.5 mA + 3 × IB
100ns
Active
VREG
Write: 2 . 5mA
Read: 2 . 5mA
+
3
+
20
20
×
×
I
B
t
CLK
100ns × 1 . 5
+
3
+
×
× I
B
t
CLK
V−
100ns
1 . 8mA
+
3
+
20
×
× I
B
t
CLK
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Rev. 0 | 22 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
referred to as the fast mode. The increase in speed comes from a
reduction in the OSR. This increase results in an increase in noise
and average measurement error.
ADC OPERATION
There are three ADCs inside the ADBMS1818. The three ADCs
operate simultaneously when measuring 18 cells. Only one ADC is
used to measure the general-purpose inputs. This section uses the
term ADC to refer to one or all ADCs, depending on the operation
being performed. This section refers to ADC1, ADC2, and ADC3
when it is necessary to distinguish between the three circuits, such
as in the timing diagrams.
Mode 26 Hz (filtered): In this mode, the ADC digital filter –3 dB
frequency is lowered to 26 Hz by increasing the OSR. This mode is
also referred to as the filtered mode due to its low –3 dB frequency.
The accuracy is similar to the 7 kHz (normal) mode with lower
noise.
Modes 14 kHz, 3 kHz, 2 kHz, 1 kHz, and 422 Hz: Modes 14 kHz, 3
kHz, 2 kHz, 1 kHz, and 422 Hz provide additional options to set the
ADC digital filter –3 dB at 13.5 kHz, 3.4 kHz, 1.7 kHz, 845 Hz, and
422 Hz, respectively. The accuracy of the 14 kHz mode is similar to
the 27 kHz (fast) mode. The accuracy of the 3 kHz, 2 kHz, 1 kHz,
and 422 Hz modes is similar to the 7 kHz (normal) mode.
ADC Modes
The ADCOPT bit (CFGAR0, Bit 0) in Configuration Register Group
A and the mode selection bits, MD, Bits[1:0], in the conversion
command together provide eight modes of operation for the ADC
which correspond to different oversampling ratios (OSRs). The
accuracy and timing of these modes are summarized in Table 17. In
each mode, the ADC first measures the inputs and then performs a
calibration of each channel. The names of the modes are based on
the –3 dB bandwidth of the ADC measurement.
The filter bandwidths and the conversion times for these modes
are provided in Table 17. If the core is in the standby state,
an additional tREFUP time is required to power up the reference
before beginning the ADC conversions. The reference can remain
powered up between ADC conversions if the REFON bit in Configu-
ration Register Group A is set to 1 so that the core is in REFUP
state after delay tREFUP. The subsequent ADC commands do not
have the tREFUP delay before beginning ADC conversions.
Mode 7 kHz (normal): In this mode, the ADC has high resolution
and low TME. This mode is considered the normal operating mode
because of the optimum combination of speed and accuracy.
Mode 27 kHz (fast): In this mode, the ADC has maximum through-
put but has some increase in TME. Therefore, this mode is also
Table 17. ADC Filter Bandwidth and Accuracy
TME Specification at 3.3 V,
25°C
TME Specification at 3.3V, –
40°C, +85°C
Mode
–3 dB Filter BW
–40 dB Filter BW
27 kHz (Fast Mode)
14 kHz
27 kHz
13.5 kHz
6.8 kHz
3.4 kHz
1.7 kHz
845 Hz
422 Hz
26 Hz
84 kHz
42 kHz
21 kHz
10.5 kHz
5.3 kHz
2.6 kHz
1.3 kHz
82 Hz
±8.5 mV
±8.5 mV
±3 mV
±8.5 mV
±8.5 mV
±4 mV
7 kHz (Normal Mode)
3 kHz
±3 mV
±4 mV
2 kHz
±3 mV
±4 mV
1 kHz
±3 mV
±4 mV
422 Hz
±3 mV
±4 mV
26 Hz (Filtered Mode)
±2.2 mV
±3.0 mV
analog.com
Rev. 0 | 23 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
ADC Range and Resolution
ADC Range vs. Voltage Reference Value
The C inputs and GPIO inputs have the same range and resolution.
The ADC inside the ADBMS1818 has an approximate range from
–0.82 V to +5.73 V. Negative readings are rounded to 0 V. The
format of the data is a 16-bit unsigned integer where the LSB rep-
resents 100 μV. Therefore, a reading of 0x80E8 (33,000 decimal)
indicates a measurement of 3.3 V.
Typical ADCs have a range that is exactly twice the value of
the voltage reference, and the ADC measurement error is directly
proportional to the error in the voltage reference. The ADBMS1818
ADC is not typical.
The absolute value of VREF1 is trimmed up or down to compensate
for gain errors in the ADC. Therefore, the ADC TME specifications
are superior to the VREF1 specifications. For example, the 25°C
specification of the TME when measuring 3.300 V in 7 kHz (normal)
mode is ±3 mV, and the 25°C specification for VREF1 is 3.150 V ±
150 mV.
Δ-Σ ADCs have quantization noise which depends on the input
voltage, especially at low oversampling ratios, such as in fast mode.
In some of the ADC modes, the quantization noise increases as
the input voltage approaches the upper and lower limits of the ADC
range. For example, the total measurement noise vs. input voltage
in normal and filtered modes is shown in Figure 54.
Measuring Cell Voltages (ADCV Command)
The specified range of the ADC is 0 V to 5 V. In Table 18, the preci-
sion range of the ADC is arbitrarily defined as 0.5 V to 4.5 V. This
range is where the quantization noise is relatively constant even in
the lower OSR modes (see Figure 54). Table 18 summarizes the
total noise in this range for all eight ADC operating modes. Also
shown in Table 18 is the noise free resolution. For example, 14-bit
noise free resolution in normal mode implies that the top 14 bits are
noise free with a dc input, but that the 15th and 16th LSBs flicker.
The ADCV command initiates the measurement of the battery cell
inputs, Pin C0 through Pin C18. This command has options to
select the number of channels to measure and the ADC mode. See
the Commands section for the ADCV command format.
Figure 55 shows the timing of the ADCV command that measures
all 18 cells. After the receipt of the ADCV command to measure
all 18 cells, ADC1 sequentially measures the bottom 6 cells. ADC2
measures the middle 6 cells and ADC3 measures the top 6 cells.
After the cell measurements complete, each channel is calibrated to
remove any offset errors.
Table 19 shows the conversion times for the ADCV command
measuring all 18 cells. The total conversion time is given by t6C
which indicates the end of the calibration step.
Figure 56 shows the timing of the ADCV command that measures
only 3 cells.
Figure 54. Measurement Noise vs. Input Voltage
Table 18. ADC Range and Resolution
Noise Free
Mode
Full Range1
Specified Range
Precision Range2
LSB
Format
Maximum Noise
Resolution3
27 kHz (Fast)
–0.8192 V to
+5.7344 V
0 V to 5 V
0.5 V to 4.5 V
100 μV
Unsigned 16 bits
±4 mV p-p
10 bits
14 kHz
–0.8192 V to
+5.7344 V
0 V to 5 V
0 V to 5 V
0 V to 5 V
0 V to 5 V
0 V to 5 V
0 V to 5 V
0.5 V to 4.5 V
0.5 V to 4.5 V
0.5 V to 4.5 V
0.5 V to 4.5 V
0.5 V to 4.5 V
0.5 V to 4.5 V
100 μV
100 μV
100 μV
100 μV
100 μV
100 μV
Unsigned 16 bits
Unsigned 16 bits
Unsigned 16 bits
Unsigned 16 bits
Unsigned 16 bits
Unsigned 16 bits
±1 mV p-p
12 bits
14 bits
14 bits
15 bits
15 bits
15 bits
7 kHz (Normal)
3 kHz
–0.8192 V to
+5.7344 V
±250 μV p-p
±150 μV p-p
±100 μV p-p
±100 μV p-p
±100 μV p-p
–0.8192 V to
+5.7344 V
2 kHz
–0.8192 V to
+5.7344 V
1 kHz
–0.8192 V to
+5.7344 V
422 Hz
–0.8192 V to
+5.7344 V
analog.com
Rev. 0 | 24 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 18. ADC Range and Resolution
Noise Free
Mode
Full Range1
Specified Range
Precision Range2
LSB
Format
Maximum Noise
±50 μV p-p
Resolution3
26 Hz (Filtered)
–0.8192 V to
+5.7344 V
0 V to 5 V
0.5 V to 4.5 V
100 μV
Unsigned 16 bits
16 bits
1
Negative readings are rounded to 0 V.
2
3
Precision range is the range over which the noise is less than the maximum noise.
Noise free resolution is a measure of the noise level within the precision range.
Figure 55. Timing for ADCV Command Measuring all 18 Cells
Table 19. Conversion and Synchronization Times for ADCV Command Measuring All 18 Cells in Different Modes
Conversion Times (μs)
Synchronization Time (μs)
tSKEW2
Mode
t0
t1M
t2M
t5M
t6M
t6C
27 kHz
14 kHz
7 kHz
3 kHz
2 kHz
1 kHz
422 Hz
26 Hz
0
0
0
0
0
0
0
0
58
104
244
291
1,121
1,296
2343
233
87
163
390
466
379
145
261
494
960
1890
29,818
279
681
815
670
512
1263
2426
4753
9408
149,044
1513
2909
5702
11,287
178,851
3041
1252
2415
4742
9397
149,033
977
4437
1,908
3770
59,624
7230
12,816
201,325
Figure 56. Timing for ADCV Command Measuring 3 Cells
Table 20 shows the conversion time for the ADCV command measuring only 3 cells. t1C indicates the total conversion time for this command.
Table 20. Conversion Times for ADCV Command Measuring 3 Cells in Different Modes
Conversion Times (μs)
Mode
t0
t1M
t1C
27 kHz
14 kHz
7 kHz
0
0
0
58
203
232
407
87
145
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Rev. 0 | 25 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 20. Conversion Times for ADCV Command Measuring 3 Cells in Different Modes
Conversion Times (μs)
Mode
t0
t1M
t1C
3 kHz
2 kHz
1 kHz
422 Hz
26 Hz
0
0
0
0
0
261
523
494
756
960
1221
2152
33,570
1890
29,818
analog.com
Rev. 0 | 26 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
the ADAX command to measure subsets of the GPIOs and the
2nd reference separately or to measure all nine GPIOs and the
2nd reference in a single command. See the Commands section
for the ADAX command format. All auxiliary measurements are
relative to the V– pin voltage. This command can be used to read
external temperatures by connecting temperature sensors to the
GPIOs. These sensors can be powered from the 2nd reference,
which is also measured by the ADAX command, resulting in precise
ratiometric measurements.
Undervoltage and Overvoltage Monitoring
Whenever the C inputs are measured, the results are compared
to undervoltage and overvoltage thresholds stored in the memory.
If the reading of a cell is above the overvoltage limit, a bit in the
memory is set as a flag. Similarly, measurement results below the
undervoltage limit cause a flag to be set. The overvoltage and
undervoltage thresholds are stored in Configuration Register Group
A. The flags are stored in Status Register Group B and Auxiliary
Register Group D.
Figure 57 shows the timing of the ADAX command measuring
all nine GPIOs and the 2nd reference. All 10 measurements are
carried out on ADC1 alone. The 2nd reference is measured after
GPIO5 and before GPIO6.
Auxiliary (GPIO) Measurements (ADAX
Command)
The ADAX command initiates the measurement of the GPIO inputs.
This command has options to select which GPIO input to measure
(GPIO1 to GPIO9) and which ADC mode to use. The ADAX
command also measures the 2nd reference. There are options in
Table 21 shows the conversion time for the ADAX command meas-
uring all nine GPIOs and the 2nd reference. t10C indicates the total
conversion time.
Figure 57. Timing for ADAX Command Measuring All GPIOs and 2nd Reference
Table 21. Conversion and Synchronization Times for ADAX Command Measuring All GPIOs and 2nd Reference in Different Modes
Conversion Times (μs)
t9M
Synchronization Time (μs)
Mode
t0
t1M
t2M
t10M
t10C
tSKEW
27 kHz
14 kHz
7 kHz
3 kHz
2 kHz
1 kHz
422 Hz
26 Hz
0
0
0
0
0
0
0
0
58
104
163
279
512
977
1908
3770
431
478
1825
420
87
693
769
2116
682
145
261
494
960
1890
29,818
1217
2264
4358
8547
16,926
1350
2514
4841
9496
18,805
298,078
3862
1205
2253
4347
8536
16,915
268,260
5025
7353
12,007
21,316
335,498
59,624
268,271
analog.com
Rev. 0 | 27 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
fies the synchronization of battery cell voltage and current measure-
ments when current sensors are connected to the GPIO1 or GPIO2
inputs. Figure 58 shows the timing of the ADCVAX command. See
the Commands section for the ADCVAX command format. The
Auxiliary (GPIO) Measurements with Digital
Redundancy (ADAXD Command)
The ADAXD command operates similarly to the ADAX command
except that an additional diagnostic is performed using digital re-
dundancy. PS, Bits[1:0] in Configuration Register Group B must be
set to 0 or 1 during the ADAXD command to enable redundancy.
See the ADC Conversion with Digital Redundancy section.
synchronization of the current and voltage measurements, tSKEW1
,
in fast mode is within 194 μs.
Table 22 shows the conversion and synchronization time for the
ADCVAX command in different modes. The total conversion time
The execution time of the ADAX command and the ADAXD com-
mand is the same.
for the command is given by t8C
.
Measuring Cell Voltages and GPIOs (ADCVAX
Command)
The ADCVAX command combines 18 cell measurements with 2
GPIO measurements (GPIO1 and GPIO2). This command simpli-
Figure 58. Timing of ADCVAX Command
Table 22. Conversion and Synchronization Times for ADCVAX Command in Different Modes
Conversion Times (μs)
Synchronization Time (μs)
tSKEW1
Mode
t0
t1M
t2M
t3M
t4M
t5M
t6M
t7M
t8M
t8C
27 kHz
14 kHz
7 kHz
3 kHz
2 kHz
1 kHz
422 Hz
26 Hz
0
0
0
0
0
0
0
0
58
104
151
205
252
306
352
399
1511
194
87
163
238
321
397
480
556
632
1744
310
145
261
494
960
1890
29,818
279
413
554
688
829
963
1097
2028
3890
7613
15,061
238,479
3140
543
512
762
1020
1,950
3812
7536
119,245
1270
2433
4761
9415
149,052
1527
2924
5717
11,302
178,866
1778
3407
6665
13,181
208,672
4071
1008
1939
3801
7525
119,234
977
1460
2857
5649
89,431
5933
1908
3770
59,624
9657
17,104
268,450
analog.com
Rev. 0 | 28 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
internal die temperature (ITMP), analog power supply (VA), and
digital power supply (VD). These parameters are described in
Sum of All Cells Measurement section, Internal Die Temperature
Measurement section, and Power Supply Measurements section.
All 8 ADC modes described in the ADC Modes section are available
for these conversions. See the Commands section for the ADSTAT
command format. Figure 59 shows the timing of the ADSTAT
command measuring all 4 internal device parameters.
DATA ACQUISITION SYSTEM DIAGNOSTICS
The battery monitoring data acquisition system is comprised of the
multiplexers, ADCs, 1st reference, digital filters, and memory. To
ensure long term reliable performance, there are several diagnostic
commands that can be used to verify the proper operation of these
circuits.
Measuring Internal Device Parameters
(ADSTAT Command)
Table 23 shows the conversion time of the ADSTAT command
measuring all 4 internal parameters. t4C indicates the total conver-
sion time for the ADSTAT command.
The ADSTAT command is a diagnostic command that measures
the following internal device parameters: Sum of all cells (SC),
Figure 59. Timing for ADSTAT Command Measuring SC, ITMP, VA, and VD
Table 23. Conversion and Synchronization Times for ADSTAT Command Measuring SC, ITMP, VA, and VD in Different Modes
Conversion Times (μs)
Synchronization Time (μs)
tSKEW
Mode
t0
t1M
t2M
t3M
t4M
t4C
27 kHz
14 kHz
7 kHz
3 kHz
2 kHz
1 kHz
422 Hz
26 Hz
0
0
0
0
0
0
0
0
58
104
151
198
742
140
87
163
238
314
858
227
145
261
494
960
1890
29,818
279
413
547
1556
2022
2953
4814
8538
134,211
402
512
762
1012
1943
3805
7529
119,238
751
977
1460
2857
5649
89,431
1449
2845
5638
89,420
1908
3770
59,624
analog.com
Rev. 0 | 29 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
fourth digital integration and differentiation machine that is used for
redundancy and error checking.
Sum of All Cells Measurement
The sum of all cells (SC) measurement is the voltage between C18
and C0 with a 30:1 attenuation. The 16-bit ADC value of sum of
all cells measurement is stored in Status Register Group A. Any
potential difference between the C0 and V– pins results in an error
in the SC measurement equal to this difference. From the SC value,
the sum of all cell voltage measurements is given by:
All of the ADC and self test commands, except ADAX and ADSTAT,
can operate with digital redundancy. This includes ADCV, ADOW,
CVST, ADOL, ADAXD, AXOW, AXST, ADSTATD, STATST, ADC-
VAX, and ADCVSC. When performing an ADC conversion with
redundancy, the analog modulator sends its bit stream to both
the primary digital machine and the redundant digital machine. At
the end of the conversion, the results from the two machines are
compared. If any mismatch occurs, a value of 0xFF0X (≥6.528 V)
is written to the result register. This value is outside of the clamping
range of the ADC and the host identifies this as a fault indication.
The last four bits are used to indicate which nibble(s) of the result
values did not match.
Sum of all cells = SC × 30 × 100 µV
Internal Die Temperature Measurement
The ADSTAT command can measure the internal die temperature
(ITMP). The 16-bit ADC value of the ITMP is stored in Status Regis-
ter Group A. From ITMP, the actual die temperature is calculated
using the expression:
Table 24. Indication of Digital Redundancy Fault Bit Location
Result
Indication
Internal Die Temperature (°C) =
0b1111_1111_0000_0XXX
0b1111_1111_0000_1XXX
0b1111_1111_0000_X0XX
0b1111_1111_0000_X1XX
0b1111_1111_0000_XX0X
0b1111_1111_0000_XX1X
0b1111_1111_0000_XXX0
0b1111_1111_0000_XXX1
No fault detected in Bit 15 to Bit 12
Fault detected in Bit 15 to Bit 12
No fault detected in Bit 11 to Bit 8
Fault detected in Bit 11 to Bit 8
No fault detected in Bit 7 to Bit 4
Fault detected in Bit 7 to Bit 4
No fault detected in Bit 3 to Bit 0
Fault detected in Bit 3 to Bit 0
100μV
7 . 6mV
ITMP ×
°C - 276°C
Power Supply Measurements
The ADSTAT command is also used to measure the analog power
supply (VREG) and digital power supply (VREGD). The 16-bit ADC
value of the analog power supply measurement (VA) is stored in
Status Register Group A. The 16-bit ADC value of the digital power
supply measurement (VD) is stored in Status Register Group B.
From VA and VD, the power supply measurements are given by:
Because there is a single redundant digital machine, the machine
can apply redundancy to only one ADC at a time. By default,
the ADBMS1818 automatically selects the ADC path redundancy.
However, the user can choose an ADC redundancy path selection
by writing to the PS, Bits[1:0] in Configuration Register Group B.
Analog power supply measurement (VREG) = VA × 100 µV
Digital power supply measurement (VREGD) = VD × 100 µV
The value of VREG is determined by external components. VREG
must be between 4.5 V and 5.5 V to maintain accuracy. The value
of VREGD is determined by internal components. The normal range
of VREGD is 2.7 V to 3.6 V.
Table 25 shows all possible ADC path redundancy selections.
When the FDRF bit in Configuration Register Group B is written to
1, this bit forces the digital redundancy comparison to fail during
subsequent ADC conversions.
Measuring Internal Device Parameters with
Digital Redundancy (ADSTATD Command)
Measuring Cell Voltages and Sum of All Cells
(ADCVSC Command)
The ADSTATD command operates similarly to the ADSTAT com-
mand except that an additional diagnostic is performed using digital
redundancy. PS, Bits[1:0] in Configuration Register Group B must
be set to 0 or 1 during the ADSTATD command to enable redun-
dancy. See the ADC Conversion with Digital Redundancy section.
The ADCVSC command combines 18 cell measurements and
the sum of all cells measurement. This command simplifies the
synchronization of the individual battery cell voltage and the total
sum of all cells measurements. Figure 60 shows the timing of the
ADCVSC command. See the Commands section for the ADCVSC
command format. The synchronization of the cell voltage and sum
of all cells measurements, tSKEW, in fast mode is within 147 μs.
The execution time of the ADSTAT command and the ADSTATD
command is the same.
ADC Conversion with Digital Redundancy
Table 26 shows the conversion and synchronization time for the
ADCVSC command in different modes. The total conversion time
Each of the three internal ADCs contains its own digital integra-
tion and differentiation machine. The ADBMS1818 also contains a
for the command is given by t7C
.
analog.com
Rev. 0 | 30 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 25. ADC Path Redundancy Selection
PS, Bits[1:0] = 00
PS, Bits[1:0] = 01
Redundant
PS, Bits[1:0] = 10
Redundant
PS, Bits[1:0] = 11
Redundant
Redundant
Measure
Measure
Path Select
Path Select
Measure
Path Select
Measure
Path Select
Measure
Cells 1, 7, 13
Cells 2, 8, 14
Cells 3, 9, 15
Cells 4, 10, 16
Cells 5, 11, 17
Cells 6, 12, 18
Cell 7 (ADOL)
Cell 13 (ADOL)
GPIO[n]2
2nd Reference2
SC2
ITMP2
VA2
VD 2
ADC1
ADC2
ADC3
ADC1
ADC2
ADC3
ADC2
ADC2
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
Cell 1
Cell 8
Cell 15
Cell 4
Cell 11
Cell 18
Cell 7
Cell 13
GPIO[n]
2nd Reference
SC
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
Cell 1
Cell 2
Cell 3
Cell 4
Cell 5
Cell 6
Cell 7
N/A1
ADC2
ADC2
ADC2
ADC2
ADC2
ADC2
ADC2
ADC2
ADC2
ADC2
ADC2
ADC2
ADC2
ADC2
Cell 7
Cell 8
Cell 9
Cell 10
Cell 11
Cell 12
Cell 7
Cell 13
N/A1
N/A1
N/A1
N/A1
N/A1
ADC3
ADC3
ADC3
ADC3
ADC3
ADC3
ADC3
ADC3
ADC3
ADC3
ADC3
ADC3
ADC3
ADC3
Cell 13
Cell 14
Cell 15
Cell 16
Cell 17
Cell 18
N/A 1
Cell 13
N/A1
N/A1
N/A1
N/A1
N/A1
N/A1
GPIO[n]
2nd Reference
SC
ITMP
ITMP
VA
VA
VD
VD
N/A1
1
N/A means not applicable.
2
Note that the ADAX and ADSTAT commands are identical to the ADAXD and ADSTATD commands except that ADAX and ADSTAT do not apply any digital redundancy.
Figure 60. Timing of ADCVSC Command Measuring All 19 Cells, SC
Table 26. Conversion and Synchronization Times for ADCVSC Command in Different Modes
Synchronization
Time (μs)
Conversion Times (μs)
Mode t0
t1M
t2M
t3M
t4M
t5M
t6M
t7M
t7C
tSKEW
27
0
58
104
151
205
259
306
352
1331
147
kHz
14
0
87
163
238
321
404
480
556
1534
235
kHz
7 kHz
3 kHz
2 kHz
1 kHz
0
0
0
0
0
145
261
494
960
1890
279
413
554
695
829
963
2756
3571
5200
8458
14,974
409
512
762
1020
1950
3812
7536
1277
2441
4768
9423
1527
2924
5717
11,302
1778
3407
6665
13,181
758
977
1460
2857
5649
1456
2853
5645
1908
3770
422
Hz
26 Hz
0
29,818
59,624
89,431
119,245
149,059
178,866
208,672
234,902
89,427
analog.com
Rev. 0 | 31 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 27. Conversion Times for ADOL Command
Conversion Times (μs)
t2M
Overlap Cell Measurement (ADOL Command)
The ADOL command first simultaneously measures Cell 7 with
ADC1 and ADC2. Then, the ADOL command simultaneously meas-
ures Cell 13 with both ADC2 and ADC3. The host can compare
the results against each other to look for inconsistencies that may
indicate a fault. The result of the Cell 7 measurement from ADC2
is placed in Cell Voltage Register Group C where the Cell 7 result
normally resides. The result from ADC1 is placed in Cell Voltage
Register Group C where the Cell 8 result normally resides. The
result of the Cell 13 measurement from ADC3 is placed in Cell
Voltage Register Group E where the Cell 13 result normally resides.
The result from ADC2 is placed in Cell Voltage Register Group E
where the Cell 14 result normally resides. Figure 61 shows the
timing of the ADOL command. See the Commands section for the
ADOL command format.
Mode
t0
t1M
t2C
3 kHz
2 kHz
1 kHz
422 Hz
26 Hz
0
0
0
0
0
262
513
1024
1490
2420
4282
67,119
495
979
960
1910
3772
59,626
1891
29,818
Digital Filter Check
The Δ-Σ ADC is composed of a 1-bit pulse density modulator
followed by a digital filter. A pulse density modulated bit stream has
a higher percentage of 1s for higher analog input voltages. The
digital filter converts this high frequency 1-bit stream into a single
16-bit word.
This is why a Δ-Σ ADC is often referred to as an oversampling
converter.
The self test commands verify the operation of the digital filters
and memory. Figure 62 shows the operation of the ADC during self
test. The output of the 1-bit pulse density modulator is replaced by
a 1-bit test signal. The test signal passes through the digital filter
and is converted to a 16-bit value. The 1-bit test signal undergoes
the same digital conversion as the regular 1-bit signal from the
modulator, so the conversion time for any self test command is
exactly the same as the corresponding regular ADC conversion
command. The 16-bit ADC value is stored in the same register
groups as the corresponding regular ADC conversion command.
The test signals are designed to place alternating one-zero patterns
in the registers. Table 28 provides a list of the self test commands.
If the digital filters and memory are working properly, then the
registers contain the values shown in Table 28. For more details
see the Commands section.
Figure 61. Timing for ADOL Command
Table 27 shows the conversion time for the ADOL command. t2C
indicates the total conversion time for this command.
Table 27. Conversion Times for ADOL Command
Conversion Times (μs)
Mode
t0
t1M
t2M
t2C
27 kHz
14 kHz
7 kHz
0
0
0
58
106
164
281
384
442
791
87
146
Figure 62. Operation of ADBMS1818 ADC Self Test
Table 28. Self Test Command Summary
Output Pattern in Different ADC Modes
Command
Self Test Option
27 kHz
14 kHz
7 kHz, 3 kHz, 2 kHz, 1 kHz, 422 Hz, 26 Hz
Results Register Groups
CVST
ST, Bits[1:0] = 01
ST, Bits[1:0] = 10
ST, Bits[1:0] = 01
ST, Bits[1:0] = 10
0x9565
0x6A9A
0x9565
0x6A9A
0x9553
0x6AAC
0x9553
0x6AAC
0x9555
0x6AAA
0x9555
0x6AAA
C1V to C18V (CVA, CVB, CVC, CVD, CVE, CVF)
AXST
G1V to GV9, REF (AUXA, AUXB, AUXC, AUXD)
analog.com
Rev. 0 | 32 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 28. Self Test Command Summary
Output Pattern in Different ADC Modes
14 kHz 7 kHz, 3 kHz, 2 kHz, 1 kHz, 422 Hz, 26 Hz
Command
Self Test Option
27 kHz
Results Register Groups
SC, ITMP, VA, VD (STATA, STATB)
STATST
ST, Bits[1:0] = 01
ST, Bits[1:0] = 10
0x9565
0x6A9A
0x9553
0x9555
0x6AAC
0x6AAA
analog.com
Rev. 0 | 33 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
performs ADC conversions on the C pin inputs identically to the
ADCV command, except for two internal current sources sink or
source current into the two C pins while they are being measured.
The pull-up (PUP) bit of the ADOW command determines whether
the current sources are sinking or sourcing 100 μA.
Accuracy Check
Measuring an independent voltage reference is the optimal
means to verify the accuracy of a data acquisition system. The
ADBMS1818 contains a 2nd reference for this purpose. The ADAX
command initiates the measurement of the 2nd reference. The
results are placed in Auxiliary Register Group B. The range of
the result depends on the ADC1 measurement accuracy and the
accuracy of the 2nd reference, including thermal hysteresis and
long term drift. Readings outside the 2.992 V to 3.012 V range
indicate the system is out of its specified tolerance. ADC2 is verified
by comparing it to ADC1 using the ADOL command. ADC3 is
verified by comparing it to ADC2 using the ADOL command.
The following simple algorithm can be used to check for an open
wire on any of the 19 C pins:
1. Run the 18-cell command ADOW with PUP = 1 at least twice.
Read the cell voltages for cells 1 through 18 once at the end
and store them in array CELLPU(n).
2. Run the 18-cell command ADOW with PUP = 0 at least twice.
Read the cell voltages for cells 1 through 18 once at the end
and store them in array CELLPD(n).
3. Take the difference between the pull-up and pull-down meas-
urements made in Step 1 and Step 2 for cells 2 to 18: CELL∆(n)
= CELLPU(n) – CELLPD(n).
4. For all values of n from 1 to 17: If CELL∆(n+1) < –400 mV,
then C(n) is open. If CELLPU(1) = 0.0000, then C(0) is open. If
CELLPD(18) = 0.0000, then C(18) is open.
Mux Decoder Check
The diagnostic command DIAGN ensures the proper operation
of each multiplexer channel. The command cycles through all
channels and sets the MUXFAIL bit to 1 in Status Register Group
B if any channel decoder fails. The MUXFAIL bit is set to 0 if the
channel decoder passes the test. The MUXFAIL bit is also set to 1
on a power-on reset (POR) or after a CLRSTAT command.
The above algorithm detects open wires using normal mode con-
versions with as much as 10 nF of capacitance remaining on the
ADBMS1818 side of the open wire. However, if more external
capacitance is on the open C pin, then the length of time that
the open wire conversions run in Step 1 and Step 2 must be
increased to give the 100 μA current sources time to create a large
enough difference for the algorithm to detect an open connection.
This action can be accomplished by running more than two ADOW
commands in Step 1 and Step 2, or by using filtered mode conver-
sions instead of normal mode conversions. Refer to Table 29 to
determine how many conversions are necessary.
The DIAGN command takes approximately 400 μs to complete if
the core is in the REFUP state and about 4.5 ms to complete if the
core is in the standby state. The polling methods described in the
Polling Methods section can be used to determine the completion of
the DIAGN command.
ADC Clear Commands
ADBMS1818 has 3 clear ADC commands: CLRCELL, CLRAUX,
and CLRSTAT. These commands clear the registers that store all
ADC conversion results.
Table 29. Number of ADOW Commands Required
The CLRCELL command clears Cell Voltage Register Groups A, B,
C, D, E, and F. All bytes in these registers are set to 0xFF by the
CLRCELL command.
Number of ADOW Commands Required in Step 1
and Step 2
External C Pin
Capacitance
Normal Mode
Filtered Mode
The CLRAUX command clears Auxiliary Register Groups A, B, C,
and D. All bytes in these registers, except the last four registers of
Group D, are set to 0xFF by the CLRAUX command.
≤10 nF
100 nF
1 μF
2
2
2
2
2
10
100
The CLRSTAT command clears Status Register Groups A and
B, except for the REV and RSVD bits in Status Register Group
B. A read back of the REV bits returns the revision code of the
part. RSVD bits always read back 0s. All overvoltage (OV) and
undervoltage (UV) flags, MUXFAIL bit, and THSD bit in Status
Register Group B and Auxiliary Register Group D are set to 1
by the CLRSTAT command. The THSD bit is set to 0 after the
RDSTATB command. The registers storing SC, ITMP, VA, and VD
are all set to 0xFF by the CLRSTAT command.
C
1 + ROUNDUP (C/10 nF)
Auxiliary Open Wire Check (AXOW Command)
The AXOW command is used to check for any open wires between
the GPIO pins of the ADBMS1818 and the external circuit. This
command performs ADC conversions on the GPIO pin inputs identi-
cally to the ADAX command, except internal current sources sink or
source current into each GPIO pin while it is being measured. The
pull-up (PUP) bit of the AXOW command determines whether the
current sources are sinking or sourcing 100 μA.
Open Wire Check (ADOW Command)
The ADOW command is used to check for any open wires between
the ADCs of the ADBMS1818 and the external cells. This command
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Data Sheet
ADBMS1818
THEORY OF OPERATION
B) and the remainder of Configuration Register Group B are reset
by the watchdog timer when the discharge timer is disabled. The
WDT pin is pulled high by the external pull-up when the watchdog
time elapses. The watchdog timer is always enabled, and the timer
resets after every valid command with matching command PEC.
Thermal Shutdown
To protect the ADBMS1818 from overheating, there is a thermal
shutdown circuit included inside the IC. If the temperature detected
on the die rises above approximately 150°C, the thermal shutdown
circuit trips and resets the configuration register groups and S
Control Register Group (including S control bits in PWM/S Control
Register Group B) to their default states and turns off all discharge
switches. When a thermal shutdown event has occurred, the THSD
bit in Status Register Group B goes high. The CLRSTAT command
can also set the THSD bit high for diagnostic purposes. This bit
is cleared when a read operation is performed on Status Register
Group B (RDSTATB command). The CLRSTAT command sets the
THSD bit high for diagnostic purposes but does not reset the
configuration register groups.
The discharge timer is used to keep the discharge switches turned
on for programmable time duration. If the discharge timer is being
used, the discharge switches are not turned off when the watchdog
timer is activated.
To enable the discharge timer, connect the DTEN pin to VREG (see
Figure 63). In this configuration, the discharge switches remain on
for the programmed time duration that is determined by the DCTO
value written in Configuration Register Group A. Table 31 shows the
various time settings and the corresponding DCTO value.
Revision Code
The Status Register Group B contains a 4-bit revision code (REV).
If software detection of the device revision is necessary, contact
the factory for details. Otherwise, ignore the code. In all cases,
however, the values of all bits must be used when calculating the
packet error code (PEC) on data reads.
WATCHDOG AND DISCHARGE TIMER
When there is no valid command for more than 2 seconds, the
watchdog timer expires, which resets the configuration register
bytes CFGAR0-3 and the GPIO bits in Configuration Register
Group B in all cases. CFGAR4, CFGAR5, the S Control Register
Group (including S control bits in PWM/S Control Register Group
Figure 63. Watchdog and Discharge Timer
Table 30. DCTO Settings
DCTO
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Time
Disabled 0.5
1
2
3
4
5
10
15
20
30
40
60
75
90
120
(Minutes)
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Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 31. Discharge Timer Settings
and CFGAR5 and CFGBR0 and CFGBR1 may be corrupted. If the
discharge timer activates in the middle of a RDSCTRL or RDPSB
command, the S Control Register Group (including S control bits in
PWM/S Control Register Group B) resets, as per Table 31. As a
result, the read back data may be corrupted.
Watchdog Timer
Discharge Timer
DTEN = 0, DCTO = XXXX Resets CFGAR0-5,
CFGBR0-1 and SCTRL
Disabled
when it fires
DTEN = 1, DCTO = 0000
Resets CFGAR0-5,
CFGBR0-1 and SCTRL
when it fires
Disabled
S PIN PULSE-WIDTH MODULATION FOR CELL
BALANCING
DTEN = 1, DCTO != 0000 Resets CFGAR0-3 and
GPIO Bits in CFGBR0
Resets CFGAR4-5,
SCTRL, and remainder of
CFGBR0-1 when it fires
For additional control of cell discharging, the host may configure
the S pins to operate using PWM. While the watchdog timer is
not expired, the DCC bits in the configuration register groups
control the S pins directly. After the watchdog timer expires, PWM
operation begins and continues for the remainder of the selected
discharge time or until a wake-up event occurs (and the watchdog
timer is reset). During PWM operation, the DCC bits must be set to
1 for the PWM feature to operate.
when it fires
Table 31 summarizes the status of the configuration register groups
after a watchdog timer or discharge timer event. The status of
the discharge timer can be determined by reading Configuration
Register Group A using the RDCFGA command. The DCTO value
indicates the time left before the discharge timer expires, as shown
in Table 32.
Once PWM operation begins, the configurations in the PWM regis-
ter can cause some or all S pins to be periodically deasserted to
achieve the desired duty cycle as shown in Table 33. Each PWM
signal operates on a 30 second period. For each cycle, the duty
cycle can be programmed from 0% to 100% in increments of 1/15 =
6.67% (2 seconds).
Table 32. Status of the Discharge Timer
DCTO (Read Value)
Discharge Timer Left (Minutes)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Disabled (or) timer has timed out
0 < timer ≤ 0.5
0.5 < timer ≤ 1
1 < timer ≤ 2
Each S pin PWM signal is sequenced at different intervals to ensure
that no two pins switch on or off at the same time. The switching
interval between channels is 62.5 ms, and 1.125 sec is required for
all 18 pins to switch (18 × 62.5 ms).
2 < timer ≤ 3
3 < timer ≤ 4
4 < timer ≤ 5
5 < timer ≤ 10
Table 33. S Pin Pulse-Width Modulation Settings
10 < timer ≤ 15
15 < timer ≤ 20
20 < timer ≤ 30
30 < timer ≤ 40
40 < timer ≤ 60
60 < timer ≤ 75
75 < timer ≤ 90
90 < timer ≤ 120
DCC Bit
(Configuration
Register
Groups)
PWMC
Setting
On Time
(sec)
Off Time
(sec)
Duty Cycle
(%)
0
4’bXXXX
0
Continuously
Off
0
1
4’b1111
Continuously
On
0
100.0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4’b1110
4’b1101
4’b1100
4’b1011
4’b1010
4’b1001
4’b1000
4’b0111
4’b0110
4’b0101
4’b0100
4’b0011
4’b0010
4’b0001
4’b0000
28
26
24
22
20
18
16
14
12
10
8
2
93.3
86.7
80.0
73.3
66.7
60.0
53.3
46.7
40.0
33.3
26.7
20.0
13.3
6.7
4
Unlike the watchdog timer, the discharge timer does not reset
when there is a valid command. The discharge timer can only be
reset after a valid WRCFGA (Write Configuration Register Group A)
command. There is a possibility that the discharge timer expires in
the middle of some commands.
6
8
10
12
14
16
18
20
22
24
26
28
If the discharge timer activates in the middle of a WRCFGA com-
mand, the configuration register groups and S Control Register
Group (including S control bits in PWM/S Control Register Group B)
reset as per Table 31. However, at the end of the valid WRCFGA
command, the new data is copied to Configuration Register Group
A. The new configuration data is not lost when the discharge timer
is activated.
6
4
2
If the discharge timer activates in the middle of a RDCFGA or
RDCFGB command, the configuration register groups reset as per
Table 31. As a result, the read back data from bytes CFGAR4
0
Continuously
Off
0
analog.com
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Data Sheet
ADBMS1818
THEORY OF OPERATION
The default values of the PWM control settings (located in PWM
Register Group and PWM/S Control Register Group B) are all 1s.
Upon entering sleep mode, the PWM control settings are initialized
to their default values.
and SCKM ports of the SPI, respectively. The SPI master on the
ADBMS1818 supports SPI Mode 3 (CHPA = 1 and CPOL = 1).
The GPIOs are open-drain outputs, so an external pull-up is re-
quired on these ports to operate as an I2C or SPI master. It is also
important to write the GPIO bits to 1 in the configuration register
groups so these ports are not pulled low internally by the device.
DISCHARGE TIMER MONITOR
The ADBMS1818 has the ability to periodically monitor cell voltages
while the discharge timer is active. The host writes the DTMEN bit
in Configuration Register Group B to 1 to enable this feature.
COMM Register
ADBMS1818 has a 6-byte COMM register, as shown in Table 34.
This register stores all data and control bits required for I2C or
SPI communication to a slave. The COMM register contains three
bytes of data Dn, Bits[7:0] to be transmitted to or received from
the slave device. ICOMn, Bits[3:0] specify control actions before
transmitting/receiving each data byte. FCOMn, Bits[3:0] specify
control actions after transmitting/receiving each data byte.
When the discharge timer monitor is enabled and the watchdog
timer has expired, the ADBMS1818 performs a conversion of all cell
voltages in 7 kHz (normal) mode every 30 seconds. The overvolt-
age and undervoltage comparisons are performed and flags are set
if cells have crossed a threshold. For any undervoltage cells, the
discharge timer monitor automatically clears the associated DCC bit
in Configuration Register Group A or Configuration Register Group
B so that the cell is no longer discharged. Clearing the DCC bit also
disables PWM discharge. With this feature, the host can write the
undervoltage threshold to the desired discharge level and use the
discharge timer monitor to discharge all, or selected, cells (using
either constant discharge or PWM discharge) down to that level.
If ICOMn, Bit 3 in the COMM register is set to 1, the device
becomes an SPI master, and if the bit is set to 0, the device
becomes an I2C master.
Table 35 describes the valid write codes for ICOMn, Bits[3:0] and
FCOMn, Bits[3:0] and their behavior when using the device as an
I2C master.
During discharge timer monitoring, digital redundancy checking is
performed on the cell voltage measurements. If a digital redundan-
cy failure occurs, all DCC bits are cleared.
Table 36 describes the valid write codes for ICOMn, Bits[3:0] and
FCOMn, Bits[3:0] and their behavior when using the device as an
SPI master.
I2C/SPI MASTER ON ADBMS1818 USING
GPIOS
Note that only the codes listed in Table 35 and Table 36 are valid
for ICOMn, Bits[3:0] and FCOMn, Bits[3:0]. Writing any other code
that is not listed in Table 35 and Table 36 to ICOMn, Bits[3:0] and
FCOMn, Bits[3:0] may result in unexpected behavior on the I2C or
SPI port.
The I/O ports GPIO3, GPIO4, and GPIO5 on the ADBMS1818 can
be used as an I2C or SPI master port to communicate to an I 2C or
SPI slave. In the case of an I2C master, GPIO4 and GPIO5 form the
SDA and SCL ports of the I2C interface, respectively. In the case of
an SPI master, GPIO3, GPIO4, and GPIO5 are the CSBM, SDIOM,
Table 34. COMM Register Memory Map
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
COMM0
COMM1
COMM2
COMM3
COMM4
COMM5
R/W
R/W
R/W
R/W
R/W
R/W
ICOM0, Bit 3
D0, Bit 3
ICOM0, Bit 2
D0, Bit 2
ICOM0, Bit 1
D0, Bit 1
ICOM0, Bit 0
D0, Bit 0
D0, Bit 7
D0, Bit 6
D0, Bit 5
D0, Bit 4
FCOM0, Bit 3
D1, Bit 7
FCOM0, Bit 2
D1, Bit 6
FCOM0, Bit 1
D1, Bit 5
FCOM0, Bit 0
D1, Bit 4
ICOM1, Bit 3
D1, Bit 3
ICOM1, Bit 2
D1, Bit 2
ICOM1, Bit 1
D1, Bit 1
ICOM1, Bit 0
D1, Bit 0
FCOM1, Bit 3
D2, Bit 7
FCOM1, Bit 2
D2, Bit 6
FCOM1, Bit 1
D2, Bit 5
FCOM1, Bit 0
D2, Bit 4
ICOM2, Bit 3
D2, Bit 3
ICOM2, Bit 2
D2, Bit 2
ICOM2, Bit 1
D2, Bit 1
ICOM2, Bit 0
D2, Bit 0
FCOM2, Bit 3
FCOM2, Bit 2
FCOM2, Bit 1
FCOM2, Bit 0
Table 35. Write Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on I2C Master
Control Bits
Code
Action
Description
ICOMn, Bits[3:0]
0110
0001
0000
0111
0000
1000
1001
Start
Generate a start signal on I2C port followed by a data transmission
Generate a stop signal on I2C port
Proceed directly to data transmission on I2C port
Release SDA and SCL and ignore the rest of the data
Master generates an ACK Signal on ninth clock cycle
Master generates a NACK signal on ninth clock cycle
Master generates a NACK signal followed by a stop signal
Stop
Blank
No transmit
Master ACK
Master NACK
Master NACK + stop
FCOMn, Bits[3:0]
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Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 36. Write Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on SPI Master
Control Bits
Code
Action
Description
ICOMn, Bits[3:0]
1000
1010
1001
1111
CSBM low
Generates a CSBM low signal on SPI port (GPIO3)
Drives CSBM (GPIO3) high, then low
CSBM falling edge
CSBM high
No transmit
CSBM low
Generates a CSBM high signal on SPI port (GPIO3)
Releases the SPI port and ignores the rest of the data
Holds CSBM low at the end of byte transmission
Transitions CSBM high at the end of byte transmission
FCOMn, Bits[3:0]
X000
1001
CSBM high
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Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 37. Read Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on I2C
Master
COMM Commands
Three commands help accomplish I2C or SPI communication to the
slave device: WRCOMM, STCOMM, and RDCOMM.
Control
Bits
Code
Description
1001
Slave generated a NACK signal, master generated a
stop signal
WRCOMM Command: This command is used to write data to the
COMM register. This command writes 6 bytes of data to the COMM
register. The PEC needs to be written at the end of the data. If the
PEC does not match, all data in the COMM register is cleared to
1s when CSB goes high. See the Bus Protocols section for more
details on a write command format.
In case of the SPI master, the read back codes for ICOMn, Bits[3:0]
and FCOMn, Bits[3:0] are always 0111 and 1111, respectively. Dn,
Bits[7:0] contain the data byte transmitted by the SPI slave.
Figure 64 shows the operation of ADBMS1818 as an I2C or SPI
master using the GPIOs.
STCOMM Command: This command initiates I2C/SPI communica-
tion on the GPIO ports. The COMM register contains 3 bytes of
data to be transmitted to the slave. During this command, the data
bytes stored in the COMM register are transmitted to the slave I2C
or SPI device and the data received from the I2C or SPI device is
stored in the COMM register. This command uses GPIO4 (SDA),
and GPIO5 (SCL) for I2C communication or GPIO3 (CSBM), GPIO4
(SDIOM), and GPIO5 (SCKM) for SPI communication.
Figure 64. ADBMS1818 I2C or SPI Master Using GPIOs
The STCOMM command is followed by 24 clock cycles for each
byte of data transmitted to the slave device while holding CSB low.
For example, to transmit three bytes of data to the slave, send
the STCOMM command and its PEC followed by 72 clock cycles.
Pull CSB high at the end of the 72 clock cycles of the STCOMM
command.
Any number of bytes can be transmitted to the slave in groups
of 3 bytes using these commands. The GPIO ports do not reset
between different STCOMM commands. However, if the wait time
between the commands is greater than 2 sec, the watchdog times
out and resets the ports to their default values.
To transmit several bytes of data using an I2C master, a start
signal is only required at the beginning of the entire data stream.
A stop signal is only required at the end of the data stream. All
intermediate data groups can use a blank code before the data byte
and an ACK/NACK signal as appropriate after the data byte. SDA
and SCL do not reset between different STCOMM commands.
During I2C or SPI communication, the data received from the slave
device is updated in the COMM register.
RDCOMM Command: The data received from the slave device
can be read back from the COMM register using the RDCOMM
command. The command reads back six bytes of data followed by
the PEC. See the Bus Protocols section for more details on a read
command format.
To transmit several bytes of data using an SPI master, a CSBM
low signal is sent at the beginning of the 1st data byte. CSBM can
be held low or taken high for intermediate data groups using the
appropriate code on FCOMn, Bits[3:0]. A CSBM high signal is sent
at the end of the last byte of data. CSBM, SDIOM, and SCKM do
not reset between different STCOMM commands.
Table 37 describes the possible read back codes for ICOMn,
Bits[3:0] and FCOMn, Bits[3:0] when using the device as an I2C
master. Dn, Bits[7:0] contain the data byte transmitted by the I2C
slave.
Table 37. Read Codes for ICOMn, Bits[3:0] and FCOMn, Bits[3:0] on I2C
Master
Figure 65 shows the 24 clock cycles following the STCOMM com-
mand for an I2C master in different cases. Note that if ICOMn,
Bits[3:0] specified a stop condition, after the stop signal is sent, the
SDA and SCL lines are held high and all data in the rest of the word
is ignored. If ICOMn, Bits[3:0] are a no transmit, both SDA and SCL
lines are released, and the rest of the data in the word is ignored.
This is used when a particular device in the stack does not have to
communicate to a slave.
Control
Bits
Code
Description
ICOMn,
Bits[3:0]
0110
Master generated a start signal
0001
0000
0111
0000
Master generated a stop signal
Blank, SDA was held low between bytes
Blank, SDA was held high between bytes
Master generated an ACK signal
Figure 66 shows the 24 clock cycles following the STCOMM com-
mand for an SPI master. Similar to the I2C master, if ICOMn,
Bits[3:0] specified a CSBM HIGH or a no transmit condition, the
CSBM, SCKM, and SDIOM lines of the SPI master are released
and the rest of the data in the word is ignored.
FCOMn,
Bits[3:0]
0111
1111
0001
Slave generated an ACK signal
Slave generated a NACK signal
Slave generated an ACK signal, master generated a
stop signal
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Data Sheet
ADBMS1818
THEORY OF OPERATION
Figure 65. STCOMM Timing Diagram for an I2C Master
Figure 66. STCOMM Timing Diagram for an SPI Master
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Data Sheet
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THEORY OF OPERATION
Timing Specifications of I2C and SPI Master
Table 39. SPI Master Timing
Timing Relationship to Timing Specifications at
The timing of the ADBMS1818 I2C or SPI master is controlled
by the timing of the communication at the primary SPI of the
ADBMS1818. Table 38 shows the I2C master timing relationship
to the primary SPI clock. Table 39 shows the SPI master timing
specifications.
SPI Master Parameter
Primary SPI
tCLK = 1 μs
1
When using isoSPI, t4 is generated internally and is a minimum of 30 ns. Also,
t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high times of the SCK
input, each with a specified minimum of 200 ns.
Table 38. I2C Master Timing
S PIN PULSING USING THE S PIN CONTROL
SETTINGS
Timing Relationship to Timing Specifications at
I2C Master Parameter
Primary SPI
tCLK = 1 μs
The S pins of the ADBMS1818 can be used as a simple serial
interface, which is particularly useful for controlling the LT8584, a
monolithic flyback dc-to-dc converter, designed to actively balance
large battery stacks. The LT8584 has several operating modes
which are controlled through a serial interface. The ADBMS1818
can communicate to an LT8584 by sending a sequence of pulses
on each S pin to select a specific LT8584 mode. The S pin control
settings (located in S Control Register Group and PWM/S Control
Register Group B) are used to specify the behavior for each of
the 18 S pins, where each nibble specifies whether the S pin
drives high, drives low, or sends a pulse sequence between 1
and 7 pulses. The figures in this section show the possible S pin
behaviors that can be sent to the LT8584.
SCL Clock Frequency
tHD, STA
tLOW
1/(2 × tCLK
)
500 kHz maximum
200 ns minimum
1 μs minimum
t3
tCLK
tHIGH
tCLK
1 μs minimum
1
tSU, STA
tHD, DAT
tSU, DAT
tSU, STO
tBUF
tCLK + t4
1.03 μs minimum
30 ns minimum
200 ns minimum
1.03 μs minimum
3 μs minimum
t4
t3
1
tCLK + t4
3 × tCLK
1
When using isoSPI, t4 is generated internally and is a minimum of 30 ns. Also,
t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high times of the SCK
input, each with a specified minimum of 200 ns.
The S pin pulses occur at a pulse rate of 6.44 kHz (155 μs period).
The pulse width is 77.6 μs. The S pin pulsing begins when the
STSCTRL command is sent, after the last command PEC clock,
provided that the command PEC matches. The host can then
continue to clock SCK in order to poll the status of the pulsing.
This polling works similarly to the ADC polling feature. The data out
remains logic low until the S pin pulsing sequence completes.
Table 39. SPI Master Timing
Timing Relationship to Timing Specifications at
SPI Master Parameter
Primary SPI
tCLK = 1 μs
SDIOM Valid to SCKM
Rising Setup
t3
200 ns minimum
1
SDIO Valid from SCKM
Rising Hold
tCLK + t4
1.03 μs minimum
While the S pin pulsing is in progress, new STSCTRL, WRSCTRL,
or WRPSB commands are ignored. The PLADC command can be
used to determine when the S pin pulsing completes.
SCKM Low
SCKM High
tCLK
1 μs minimum
1 μs minimum
2 μs minimum
tCLK
SCKM Period
(SCKM_Low +
SCKM_High)
2 × tCLK
If the WRSCTRL (or WRPSB) command and command PEC are
received correctly but the data PEC does not match, the S pin
control settings are cleared.
CSBM Pulse Width
3 × tCLK
3 μs minimum
1
SCKM Rising to CSBM
Rising
5 × tCLK + t4
5.03 μs minimum
If a DCC bit in Configuration Register Group A or Configuration
Register Group B is asserted, the ADBMS1818 drives the selected
S pin low, regardless of the S pin control settings. The host must
leave the DCC bits set to 0 when using the S pin control settings.
CSBM Falling to SCKM
Falling
t3
200 ns minimum
1.2 μs minimum
CSBM Falling to SCKM
Rising
tCLK + t3
The CLRSCTRL command can be used to quickly reset the S pin
control settings to all 0s and force the pulsing machine to release
control of the S pins. This command can be helpful in reducing the
diagnostic control loop time in an high reliability application.
SCKM Falling to SDIOM
Valid
Master Requires < tCLK
The following figures show the S pin pulsing behavior.
Figure 67. S Pin Behavior when S Pin Control Bits = 0000
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Data Sheet
ADBMS1818
THEORY OF OPERATION
Figure 68. S Pin Behavior when S Pin Control Bits = 0001
Figure 69. S Pin Behavior when S Pin Control Bits = 0010
Figure 70. S Pin Behavior when S Pin Control Bits = 0011
Figure 71. S Pin Behavior when S Pin Control Bits = 0100
Figure 72. S Pin Behavior when S Pin Control Bits = 0101
Figure 73. S Pin Behavior when S Pin Control Bits = 0110
Figure 74. S Pin Behavior when S Pin Control Bits = 0111
Figure 75. S Pin Behavior when S Pin Control Bits = 1xxx
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Data Sheet
THEORY OF OPERATION
S PIN MUTING
ADBMS1818
2-WIRE ISOLATED INTERFACE (ISOSPI)
PHYSICAL LAYER
The S pins can be disabled by sending the mute command and
reenabled by sending the unmute command. The mute and un-
mute commands do not require any subsequent data and thus
the commands propagate quickly through a stack of ADBMS1818
devices. This action allows the host to quickly (<100 µs) disable
and reenable discharging without disturbing register contents. This
ability can be useful, for instance, to allow a specific settling time
before taking cell measurements. The mute status is reported in the
read-only MUTE bit in Configuration Register Group B.
The 2-wire interface provides a means to interconnect ADBMS1818
devices using simple twisted pair cabling. The interface is designed
for low packet error rates when the cabling is subjected to high RF
fields. Isolation is achieved through an external transformer.
Standard SPI signals are encoded into differential pulses. The
strength of the transmission pulse and the threshold level of the re-
ceiver are set by two external resistors. The values of the resistors
allow the user to trade-off power dissipation for noise immunity.
SERIAL INTERFACE OVERVIEW
Figure 78 shows how the isoSPI circuit operates. A 2 V reference
drives the IBIAS pin. External resistors RB1 and RB2 create the
reference current, IB. This current sets the drive strength of the
transmitter. RB1 and RB2 also form a voltage divider to supply a
fraction of the 2 V reference for the ICMP pin. The receiver circuit
threshold is half of the voltage at the ICMP pin.
There are two types of serial ports on the ADBMS1818: a standard
4-wire SPI and a 2-wire isoSPI. The state of the ISOMD pin
determines whether Pin 53, Pin 54, Pin 61, and Pin 62 are a 2-wire
or 4-wire serial port.
The ADBMS1818 is used in a daisy-chain configuration.
A second isoSPI uses Pin 57, Pin 58, Pin 63, and Pin 64.
External Connections
The ADBMS1818 has 2 serial ports, Port B and Port A. Port B is
always configured as a 2-wire interface. Port A is either a 2-wire or
4-wire interface, depending on the connection of the ISOMD pin.
4-WIRE SERIAL PERIPHERAL INTERFACE
(SPI) PHYSICAL LAYER
External Connections
When Port A is configured as a 4-wire interface, Port A is always
the slave port and Port B is the master port. Communication is
always initiated on Port A of the first device in the daisy-chain
configuration. The final device in the daisy chain does not use
Port B, and it must be terminated into RM. Figure 79 shows the
simplest port connections possible when the microprocessor and
the ADBMS1818s are located on the same PCB. In Figure 79,
capacitors are used to couple signals between the ADBMS1818s.
Connecting ISOMD to V– configures serial Port A for 4-wire SPI.
The SDO pin is an open drain output that requires a pull-up resistor
tied to the appropriate supply voltage (see Figure 76).
When Port A is configured as a 2-wire interface, communication
can be initiated on either Port A or Port B. If communication is
initiated on Port A, ADBMS1818 configures Port A as a slave and
Port B as a master. Likewise, if communication is initiated on Port
B, ADBMS1818 configures Port B as a slave and Port A as a
master. See the Reversible isoSPI section for a detailed description
of the reversible isoSPI.
Figure 76. 4-Wire SPI Configuration
Figure 80 is an example of a robust interconnection of multiple
identical PCBs, each containing one ADBMS1818 configured for
operation in a daisy chain. The microprocessor is located on a sep-
arate PCB. To achieve 2-wire isolation between the microprocessor
PCB and the 1st ADBMS1818 PCB, use the LTC6820 support IC.
The LTC6820 is functionally equivalent to the diagram in Figure 78.
In this example, communication is initiated on Port A. Therefore, the
ADBMS1818 configures Port A as a slave and Port B as a master.
Timing
The 4-wire serial port is configured to operate in an SPI system
using CPHA = 1 and CPOL = 1. Consequently, data on SDI must
be stable during the rising edge of SCK. The timing is depicted in
Figure 77. The maximum data rate is 1 Mbps. However, the device
is tested at a higher data rate in production to guarantee operation
at the maximum specified data rate.
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Rev. 0 | 43 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Figure 77. Timing Diagram of 4-Wire Serial Peripheral Interface
Figure 78. isoSPI Interface
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Data Sheet
ADBMS1818
THEORY OF OPERATION
Figure 79. Capacitive-Coupled Daisy-Chain Configuration
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Data Sheet
ADBMS1818
THEORY OF OPERATION
Figure 80. Transformer-Isolated Daisy-Chain Configuration
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Data Sheet
ADBMS1818
THEORY OF OPERATION
Figure 82. ICMP must not be tied to GND but can be tied directly to
IBIAS. A bias resistance (2 kΩ to 20 kΩ) is required for IBIAS. Do
not tie IBIAS directly to VREG or V–. Finally, IPB and IMB must be
terminated into a 100 Ω resistor (not tied to VREG or V–).
Using a Single ADBMS1818
When only one ADBMS1818 is needed, the device can be used as
a single (non daisy-chained) device if the second isoSPI port (Port
B) is properly biased and terminated, as shown in Figure 81 and
Figure 81. Single Device Using 2-Wire Port A
Figure 82. Single Device Using 4-Wire Port A
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Rev. 0 | 47 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 40. isoSPI Pulse Types
First Level
(t1/2PW
Selecting Bias Resistors
Second Level
(t1/2PW
The adjustable signal amplitude allows the system to trade power
consumption for communication robustness, and the adjustable
comparator threshold allows the system to account for signal loss-
es.
)
)
Pulse Type
Ending Level
Long +1
Long –1
Short +1
Short –1
+VA (150 ns)
–VA (150 ns)
+VA (50 ns)
–VA (50 ns)
–VA (150 ns)
+VA (150 ns)
–VA (50 ns)
+VA (50 ns)
0 V
0 V
0 V
0 V
The isoSPI transmitter drive current and comparator voltage thresh-
old are set by a resistor divider (RBIAS = RB1 + RB2) between IBIAS
and V–. The divided voltage is connected to the ICMP pin, which
sets the comparator threshold to half of this voltage (VICMP). When
either isoSPI is enabled (not idle), IBIAS is held at 2 V, causing IB to
flow out of the IBIAS pin. The IPx and IMx pin drive currents are 20
× IB.
The receiver is designed to detect each of these isoSPI pulse
types. For successful detection, the incoming isoSPI pulses (CSB
or data) must meet the following requirements:
► t1/2PW of incoming pulse > tFILT of the receiver and
► tINV of incoming pulse < tWNDW of the receiver
As an example, if the divider resistor, RB1, is 2.8 kΩ and resistor
RB2 is 1.21 kΩ (so that RBIAS = 4 kΩ), then
The worst-case margin (Margin 1) for the first condition is the
difference between the minimum t1/2PW of the incoming pulse and
the maximum tFILT of the receiver. Likewise, the worst-case margin
(Margin 2) for the second condition is the difference between
minimum tWNDW of the receiver and maximum tINV of the incoming
pulse. These timing relations are shown in Figure 83.
2
V
+ R
IB =
=
0 . 5 mA
R
B1
B2
IDRV = IIPx = IIMx = 20 × IB = 10 mA
R
B2
VICMP = 2 V ×
= IB × RB2 = 603 mV
R
+ R
B1
B2
A host microcontroller does not have to generate isoSPI pulses to
use this 2-wire interface. The first ADBMS1818 in the system can
communicate to the microcontroller using the 4-wire SPI on its Port
A, then daisy chain to other ADBMS1818s using the 2-wire isoSPI
on its Port B. Alternatively, the LTC6820 can be used to translate
the SPI signals into isoSPI pulses.
VTCMP = 0.5 × VICMP = 302 mV
In this example, the pulse drive current IDRV is 10 mA, and the
receiver comparators detect pulses with IPx to IMx amplitudes
greater than ±302 mV.
If the isolation barrier uses 1:1 transformers connected by a twisted
pair and terminated with 120 Ω resistors on each end, then the
transmitted differential signal amplitude (±) is the following:
R
M
VA = IDRV
×
= 0.6 V
2
This calculation result ignores transformer and cable losses, which
may reduce the amplitude.
isoSPI Pulse Detail
Two ADBMS1818 devices can communicate by transmitting and
receiving differential pulses back and forth through an isolation
barrier. The transmitter can output three voltage levels: +VA, 0 V,
and –VA. A positive output results from IPx sourcing current and
IMx sinking current across the load resistor, RM. A negative voltage
is developed by IPx sinking and IMx sourcing. When both outputs
are off, the load resistance forces the differential output to 0 V.
Figure 83. isoSPI Pulse Detail
Operation with Port A Configured for SPI
To eliminate the dc signal component and enhance reliability, the
isoSPI uses two different pulse lengths. This allows four types of
pulses to be transmitted, as shown in Table 40. A +1 pulse is
transmitted as a positive pulse followed by a negative pulse. A
–1 pulse is transmitted as a negative pulse followed by a positive
pulse. The duration of each pulse is defined as t1/2PW because each
pulse is half of the required symmetric pair. (The total isoSPI pulse
duration is 2 × t1/2PW).
When the ADBMS1818 is operating with Port A as a SPI (ISOMD
= V–), the SPI detects one of four communication events: CSB
falling, CSB rising, SCK rising with SDI = 0, and SCK rising with
SDI = 1. Each event is converted into one of the four pulse types
for transmission through the daisy chain. Long pulses are used to
transmit CSB changes and short pulses are used to transmit data,
as explained in Table 41.
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Rev. 0 | 48 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 41. Port B (Master) isoSPI Port Function
Table 42. Port A (Slave) isoSPI Port Function
Communication Event (Port A SPI)
Transmitted Pulse (Port B isoSPI)
Received Pulse (Port A
isoSPI)
Internal SPI Port Action Return Pulse
CSB Rising
Long +1
Long –1
Short +1
Short –1
2. Pulse SCK
1. Set SDI = 0
CSB Falling
Short –1
(No return pulse if not in
read mode or if reading a
1 bit)
SCK Rising Edge, SDI = 1
SCK Rising Edge, SDI = 0
2. Pulse SCK
Operation with Port A Configured for isoSPI
The slave isoSPI port never transmits long (CSB) pulses. Further-
more, a slave isoSPI port only transmits short –1 pulses, never a +1
pulse. The master port recognizes a null response as a Logic 1.
On the other side of the isolation barrier (that is, at the other end
of the cable), the 2nd ADBMS1818 has ISOMD = VREG so that its
Port A is configured for isoSPI. The slave isoSPI port (Port A or
Port B) receives each transmitted pulse and reconstructs the SPI
signals internally, as shown in Table 42. In addition, during a read
command this port can transmit return data pulses.
Reversible isoSPI
When the ADBMS1818 is operating with Port A configured for
isoSPI, communication can be initiated from either Port A or Port B.
In other words, ADBMS1818 can configure either Port A or Port B
as a slave or master, depending on the direction of communication.
The reversible isoSPI feature permits communication from both
directions in a stack of daisy-chained devices. See Figure 84 for an
example schematic. Figure 85 shows the operation of the reversible
isoSPI.
Table 42. Port A (Slave) isoSPI Port Function
Received Pulse (Port A
isoSPI)
Internal SPI Port Action Return Pulse
Long +1
Long –1
Short +1
Drive CSB high
Drive CSB low
1. Set SDI = 1
None
Short –1 pulse if reading a
0 bit
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Rev. 0 | 49 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Figure 84. Reversible isoSPI Daisy Chain
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Data Sheet
ADBMS1818
THEORY OF OPERATION
Figure 85. Reversible isoSPI State Diagram
When ADBMS1818 is in the sleep state, the device responds to
a valid wake-up signal on either Port A or Port B. This is true for
either configuration of the ISOMD pin.
that was transmitted by the device. Any long isoSPI pulse sent to
the master port inside tBLOCK is rejected by the device. This ensures
the ADBMS1818 cannot switch ports because of signal reflections
from poorly terminated cables (<100 m cable length).
If the wake-up signal is sent on Port A, ADBMS1818 transmits a
long +1 isoSPI pulse (CSB rising) on Port B after the isoSPI is
powered up. If the wake-up signal is sent on Port B, ADBMS1818
powers up the isoSPI but does not transmit a long +1 isoSPI pulse
on Port A.
Timing Diagrams
Figure 86 shows the isoSPI timing diagram for a read command to
daisy-chained ADBMS1818 devices. The ISOMD pin is tied to V–
on the bottom part so that its Port A is configured as an SPI port
(CSB, SCK, SDI, and SDO). The isoSPI signals of three stacked
devices are shown labeled with the port (Port A or Port B) and part
number. Note that ISO B1 and ISO A2 is actually the same signal,
but shown on each end of the transmission cable that connects Part
1 and Part 2. Likewise, ISO B2 and ISO A3 is the same signal, but
with the cable delay shown between Part 2 and Part 3.
When ADBMS1818 is in the ready state, communication can be
initiated by sending a long –1 isoSPI pulse (CSB falling) on either
Port A or Port B. The ADBMS1818 automatically configures the port
that receives the long –1 isoSPI pulse as the slave and the other
port is configured as the master. The isoSPI pulses are transmitted
through the master port to the rest of the devices in the daisy chain.
In the active state, the ADBMS1818 is in the middle of the com-
munication and CSB of the internal SPI port is low. At the end
of communication a long +1 pulse (CSB rising) on the slave port
returns the device to the ready state. Although it is not part of
a normal communication routine, the ADBMS1818 allows Port A
and Port B to be swapped inside the active state. This feature
is useful for the master controller to reclaim control of the slave
port of ADBMS1818, irrespective of the current state of the ports.
This action can be done by sending a long –1 isoSPI pulse on the
master port after a time delay of tBLOCK from the last isoSPI signal
Bit WN to Bit W0 refer to the 16-bit command code and the 16-bit
PEC of a read command. At the end of Bit W0, the three parts
decode the read command and begin shifting out data, which is
valid on the next rising edge of clock SCK. Bit XN to Bit X0 refer
to the data shifted out by Part 1. Bit YN to Bit Y0 refer to the data
shifted out by Part 2, and Bit ZN to Bit Z0 refer to the data shifted
out by Part 3. All this data is read back from the SDO port on Part 1
in a daisy-chained fashion.
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Rev. 0 | 51 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Figure 86. isoSPI Timing Diagram
up the next device in the stack which, in turn, wakes up the next
device. If there are N devices in the stack, all the devices are
powered up within the time
Waking Up the Serial Interface
The serial ports (SPI or isoSPI) enter the low power idle state
if there is no activity on Port A or Port B for a time of tIDLE
.
N × tWAKE or N × tREADY, depending on the core state. For large
stacks, the time N × tWAKE may be equal to or larger than tIDLE. In
this case, after waiting longer than the time of N × tWAKE, the host
can send another dummy byte and wait for the time N × tREADY to
ensure that all devices are in the ready state.
The wake-up circuit monitors activity on Pin 61 through Pin 64. If
ISOMD = V–, Port A is in SPI mode. Activity on the CSB pin or
SCK pin wakes up the SPI. If ISOMD = VREG, Port A is in isoSPI
mode. Differential activity on IPA to IMA (or IPB to IMB) wakes up
the isoSPI. The ADBMS1818 is ready to communicate when the
isoSPI state changes to ready within tWAKE or tREADY, depending on
the core state (see Figure 53 and the Sleep State, Standby State,
REFUP State, and Measure State sections for details).
Method 1 can be used when all devices on the daisy chain are
in the idle state, which guarantees that the devices propagate the
wake-up signal up the daisy chain. However, this method fails to
wake up all devices when a device in the middle of the chain is in
the ready state instead of the idle state. When this happens, the
device in the ready state does not propagate the wake-up pulse,
so the devices above it remain in the idle state. This situation can
occur when attempting to wake up the daisy chain after only tIDLE of
idle time (some devices may be idle, some may not).
Figure 87 shows the timing and the functionally equivalent circuit
(only Port A shown). Common-mode signals do not wake up the
serial interface. The interface is designed to wake up after receiving
a large signal single-ended pulse, or a low-amplitude symmetric
pulse. The differential signal (SCK(IPA) – CSB(IMA)), must be at
least VWAKE = 200 mV for a minimum duration of tDWELL = 240 ns to
qualify as a wake-up signal that powers up the serial interface.
Waking a Daisy Chain—Method 1
The ADBMS1818 sends a long +1 pulse on Port B after it is ready
to communicate. In a daisy-chained configuration, this pulse wakes
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Rev. 0 | 52 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Figure 87. Wake-Up Detection and Idle Timer
► IN7 = IN0 XOR PEC, Bit 6
Waking a Daisy Chain—Method 2
► IN8 = IN0 XOR PEC, Bit 7
► IN10 = IN0 XOR PEC, Bit 9
► IN14 = IN0 XOR PEC, Bit 13
3. Update the 15-bit PEC as follows:
A more robust wake-up method does not rely on the built-in wake-
up pulse, but manually sends isoSPI traffic for enough time to
wake the entire daisy chain. At a minimum, a pair of long isoSPI
pulses (–1 and +1) is needed for each device, separated by more
than tREADY or tWAKE (if the core state is standby mode or sleep
mode, respectively), but less than tIDLE. This allows each device to
wake up and propagate the next pulse to the following device. This
method works even if some devices in the chain are not in the idle
state. In practice, implementing Method 2 requires toggling the CSB
pin (of the LTC6820, or bottom ADBMS1818 with ISOMD = 0) to
generate the long isoSPI pulses. Alternatively, dummy commands
(such as RDCFGA) can be executed to generate the long isoSPI
pulses.
► PEC, Bit 14 = IN14
► PEC, Bit 13 = PEC, Bit 12
► PEC, Bit 12 = PEC, Bit 11
► PEC, Bit 11 = PEC, Bit 10
► PEC, Bit 10 = IN10
► PEC, Bit 9 = PEC, Bit 8
► PEC, Bit 8 = IN8
► PEC, Bit 7 = IN7
DATA LINK LAYER
► PEC, Bit 6 = PEC, Bit 5
► PEC, Bit 5 = PEC, Bit 4
► PEC, Bit 4 = IN4
All data transfers on ADBMS1818 occur in byte groups. Every byte
consists of 8 bits. Bytes are transferred with the MSB first. CSB
must remain low for the entire duration of a command sequence,
including between a command byte and subsequent data. On a
write command, data is latched in on the rising edge of CSB.
► PEC, Bit 3 = IN3
► PEC, Bit 2 = PEC, Bit 1
► PEC, Bit 1 = PEC, Bit 0
► PEC, Bit 0 = IN0
NETWORK LAYER
Packet Error Code
4. Go back to Step 2 until all the data is shifted. The final PEC
(16 bits) is the 15-bit value in the PEC register with a 0 bit
appended to its LSB.
The PEC is a 15-bit cyclic redundancy check (CRC) value calculat-
ed for all of the bits in a register group in the order they are passed,
using the initial PEC value of 000000000010000 and the following
characteristic polynomial: x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1.
Figure 88 shows the 15-bit PEC algorithm. An example to calculate
the PEC for a 16-bit word (0x0001) is listed in Table 43. The PEC
for 0x0001 is computed as 0x3D6E after stuffing a 0 bit at the LSB.
For longer data streams, the PEC is valid at the end of the last bit of
data sent to the PEC register.
To calculate the 15-bit PEC value, a simple procedure can be
established:
The ADBMS1818 calculates the PEC for any command or data
received and compares it with the PEC following the command or
data. The command or data is regarded as valid only if the PEC
matches. ADBMS1818 also attaches the calculated PEC at the end
of the data it shifts out. Table 44 shows the format of PEC while
writing to or reading from ADBMS1818.
1. Initialize the PEC to 000000000010000 (PEC is a 15‑bit register
group).
2. For each bit DIN coming into the PEC register group, set:
► IN0 = DIN XOR PEC, Bit 14
► IN3 = IN0 XOR PEC, Bit 2
► IN4 = IN0 XOR PEC, Bit 3
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Rev. 0 | 53 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Figure 88. 15-Bit PEC Computation Circuit
Table 43. PEC Calculation for 0x0001
PEC, Bit 13
PEC, Bit 13
PEC, Bit 12
PEC, Bit 11
PEC, Bit 10
PEC, Bit 9
PEC, Bit 8
PEC, Bit 7
PEC, Bit 6
PEC, Bit 5
PEC, Bit 4
PEC, Bit 3
PEC, Bit 2
PEC, Bit 1
PEC, Bit 0
IN14
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
2
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
3
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
5
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
9
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
10
1
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
11
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
1
0
0
1
0
1
1
0
12
1
0
1
1
0
0
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
1
0
13
1
1
1
0
1
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
1
0
14
0
1
0
1
1
0
1
1
0
0
1
0
1
1
1
0
1
0
1
1
0
1
1
15
0
0
1
1
1
1
0
1
0
1
1
0
1
1
1
0
0
1
1
1
1
0
1
0
1
1
0
1
1
1
0
IN10
PEC Word
IN8
IN7
IN4
IN3
IN0
DIN
Clock Cycle
16
Table 44. Write/Read PEC Format
Name
PEC0
PEC1
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
PEC, Bit 14
PEC, Bit 6
PEC, Bit 13
PEC, Bit 5
PEC, Bit 12
PEC, Bit 4
PEC, Bit 11
PEC, Bit 3
PEC, Bit 10
PEC, Bit 2
PEC, Bit 9
PEC, Bit 1
PEC, Bit 8
PEC, Bit 0
PEC, Bit 17
0
analog.com
Rev. 0 | 54 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
While writing any command to ADBMS1818, the command bytes
CMD0 and CMD1 (see Table 47 and Table 48) and the PEC bytes
PEC0 and PEC1 are sent on Port A in the following order:
The next method overcomes this limitation. The controller can send
an ADC start command, perform other tasks, and then send a poll
ADC converter status (PLADC) command to determine the status
of the ADC conversions (see Figure 90). After entering the PLADC
command, SDO goes low if the device is busy performing conver-
sions. SDO is pulled high at the end of conversions. However, SDO
also goes high when CSB goes high even if the device has not
completed the conversion.
CMD0, CMD1, PEC0, PEC1
After a write command to daisy-chained ADBMS1818 devices,
data is sent to each device followed by the PEC. For example,
when writing Configuration Register Group A to two daisy-chained
devices (primary device P, stacked device S), the data is sent to the
primary device on Port A in the following order:
If using a single ADBMS1818 that communicates in isoSPI mode,
the low-side port transmits a data pulse only in response to a
master isoSPI pulse received by it. Therefore, after entering the
command in either method of polling described previously, isoSPI
data pulses are sent to the part to update the conversion status.
These pulses can be sent using the LTC6820 by simply clocking its
SCK pin. In response to this pulse, the ADBMS1818 sends back a
low isoSPI pulse if it is still busy performing conversions or a high
data pulse if it has completed the conversions. If a CSB high isoSPI
pulse is sent to the device, the device exits the polling command.
CFGAR0(S), … , CFGAR5(S), PEC0(S), PEC1(S), CFGAR0(P),
… , CFGAR5(P), PEC0(P), PEC1(P)
After a read command for daisy-chained devices, each device shifts
out its data and the PEC that it computed for its data on Port
A followed by the data received on Port B. For example, when
reading Status Register Group B from two daisy -chained devices
(primary device P, stacked device S), the primary device sends out
data on Port A in the following order:
In a daisy-chained configuration of N stacked devices, the same
two polling methods can be used. If the bottom device communi-
cates in SPI mode, the SDO of the bottom device indicates the
conversion status of the entire stack. That is, SDO remains low until
all the devices in the stack have completed the conversions. In the
first method of polling, after an ADC conversion command is sent,
clock pulses are sent on SCK while keeping CSB low. The SDO
status becomes valid only at the end of N clock pulses on SCK.
During the first N clock pulses, the bottom ADBMS1818 in the daisy
chain outputs a 0 or a low data pulse. After N clock pulses, the
output data from the bottom ADBMS1818 gets updated for every
clock pulse that follows (see Figure 91). In the second method, the
PLADC command is sent followed by clock pulses on SCK while
keeping CSB low. Similar to the first method, the SDO status is
valid only after N clock cycles on SCK and gets updated after every
clock cycle that follows (see Figure 92).
STBR0(P), … , STBR5(P), PEC0(P), PEC1(P), STBR0(S), … ,
STBR5(S), PEC0(S), PEC1(S)
See the Bus Protocols section for the command format.
All devices in a daisy-chained configuration receive the command
bytes simultaneously. For example, to initiate ADC conversions in a
stack of devices, a single ADCV command is sent, and all devices
start conversions at the same time. For read and write commands,
a single command is sent, and the stacked devices effectively turn
into a cascaded shift register, in which data is shifted through each
device to the next higher (on a write) or the next lower (on a read)
device in the stack. See the Serial Interface Overview section.
Polling Methods
The simplest method to determine ADC completion is for the
controller to start an ADC conversion and wait for the specified
conversion time to pass before reading the results.
If the bottom device communicates in isoSPI mode, isoSPI data
pulses are sent to the device to update the conversion status.
Using the LTC6820, this action can be achieved by just clocking
the SCK pin. The conversion status is valid only after the bottom
ADBMS1818 device receives N isoSPI data pulses and the status
gets updated for every isoSPI data pulse that follows. The device
returns a low data pulse if any of the devices in the stack is busy
performing conversions and returns a high data pulse if all the
devices are free.
If using a single ADBMS1818 that communicates in SPI mode
(ISOMD pin tied low), there are two methods of polling. The first
method is to hold CSB low after an ADC conversion command
is sent. After entering a conversion command, the SDO line is
driven low when the device is busy performing conversions. SDO
is pulled high when the device completes conversions. However,
SDO also goes high when CSB goes high even if the device has
not completed the conversion (see Figure 89). A problem with this
method is that the controller is not free to perform other serial
communications while waiting for ADC conversions to complete.
analog.com
Rev. 0 | 55 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Figure 89. SDO Polling After an ADC Conversion Command (Single ADBMS1818)
Figure 90. SDO Polling Using PLADC Command (Single ADBMS1818)
Figure 91. SDO Polling After an ADC Conversion Command (Daisy-Chain Configuration)
Figure 92. SDO Polling Using PLADC Command (Daisy-Chain Configuration)
analog.com
Rev. 0 | 56 of 89
Data Sheet
THEORY OF OPERATION
Bus Protocols
ADBMS1818
Table 45. Protocol Key
PEC0
PEC1
n
PEC Byte 0 (see Table 44)
The protocol formats for commands are depicted in Table 46, Table
47, and Table 48. Table 45 is the key for reading the protocol
diagrams.
PEC Byte 1 (see Table 44)
Number of bytes
…
Continuation of protocol
Master to slave
Table 45. Protocol Key
CMD0
CMD1
Command Byte 0 (see Table 49)
Command Byte 1 (see Table 49)
Slave to master
Table 46. Poll Command
8
8
8
8
CMD0
CMD1
PEC0
PEC1
Poll Data
Table 47. Write Command
8
8
8
8
8
8
8
8
8
8
CMD0
CMD1
PEC0
PEC1
Data byte
low
…
Data byte
high
PEC0
PEC1
Shift Byte 1
…
Shift Byte n
Table 48. Read Command
8
8
8
8
8
8
8
8
8
8
CMD0
CMD1
PEC0
PEC1
Data byte
low
…
Data byte
high
PEC0
PEC1
Shift Byte 1
…
Shift Byte n
Command Format: The format for the commands is shown in Table 49. CC, Bits[10:0] is the 11-bit command code. A list of all the command
codes is shown in Table 50. All commands have a value 0 for CMD0, Bit 7 through CMD0, Bit 3. The PEC must be computed on the entire
16-bit command (CMD0 and CMD1).
Table 49. Command Format
Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMD0
CMD1
W
W
0
0
0
0
0
CC, Bit 10
CC, Bit 2
CC, Bit 9
CC, Bit 1
CC, Bit 8
CC, Bit 0
CC, Bit 7
CC, Bit 6
CC, Bit 5
CC, Bit 4
CC, Bit 3
Commands
Table 50 lists all the commands and their options.
Table 50. Command Codes
CC, Bits[10:0] – Command Code
Command Description
Name
10
9
8
7
6
5
4
3
2
1
0
Write Configuration Register Group A
Write Configuration Register Group B
Read Configuration Register Group A
Read Configuration Register Group B
Read Cell Voltage Register Group A
Read Cell Voltage Register Group B
Read Cell Voltage Register Group C
Read Cell Voltage Register Group D
Read Cell Voltage Register Group E
Read Cell Voltage Register Group F
Read Auxiliary Register Group A
Read Auxiliary Register Group B
Read Auxiliary Register Group C
Read Auxiliary Register Group D
WRCFGA
WRCFGB
RDCFGA
RDCFGB
RDCVA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
RDCVB
RDCVC
RDCVD
RDCVE
RDCVF
RDAUXA
RDAUXB
RDAUXC
RDAUXD
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Rev. 0 | 57 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 50. Command Codes
CC, Bits[10:0] – Command Code
Command Description
Name
10
9
8
7
6
5
4
3
2
1
0
Read Status Register Group A
Read Status Register Group B
Write S Control Register Group
Write PWM Register Group
RDSTATA
RDSTATB
WRSCTRL
WRPWM
WRPSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
0
1
0
0
1
1
1
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
Write PWM/S Control Register Group B
Read S Control Register Group
Read PWM Register Group
1
1
0
0
RDSCTRL
RDPWM
1
1
1
0
0
0
1
0
Read PWM/S Control Register Group B
Start S Control Pulsing and Poll Status
Clear S Control Register Group
RDPSB
1
1
1
0
STSCTRL
CLRSCTRL
1
0
0
1
1
0
0
0
Start Cell Voltage ADC Conversion and Poll Status ADCV
MD, Bit
1
MD, Bit
0
DCP
CH, Bit 2
CH, Bit 1
CH, Bit 0
Start Open Wire ADC Conversion and Poll Status
ADOW
CVST
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
MD, Bit
1
MD, Bit
0
PUP
1
DCP
1
0
0
0
0
0
0
1
1
1
1
0
CH, Bit 2
CH, Bit 1
CH, Bit 0
Start Self Test Cell Voltage Conversion and Poll
Status
MD, Bit
1
MD, Bit
0
ST, Bit ST, Bit
1
0
1
0
1
0
1
1
0
Start Overlap Measurements of Cell 7 and Cell 13
Voltages
ADOL
MD, Bit
1
MD, Bit
0
0
0
DCP
Start GPIOs ADC Conversion and Poll Status
ADAX
MD, Bit
1
MD, Bit
0
1
1
0
0
0
CHG, Bit 2 CHG, Bit 1 CHG, Bit 0
CHG, Bit 2 CHG, Bit 1 CHG, Bit 0
CHG, Bit 2 CHG, Bit 1 CHG, Bit 0
Start GPIOs ADC Conversion with Digital
Redundancy and Poll Status
ADAXD
AXOW
MD, Bit
1
MD, Bit
0
0
0
Start GPIOs Open Wire ADC Conversion and Poll
Status
MD, Bit
1
MD, Bit
0
PUP
1
Start Self Test GPIOs Conversion and Poll Status
AXST
MD, Bit
1
MD, Bit
0
ST, Bit ST, Bit
1
0
1
1
1
0
Start Status Group ADC Conversion and Poll
Status
ADSTAT
ADSTATD
STATST
ADCVAX
ADCVSC
MD, Bit
1
MD, Bit
0
1
1
0
CHST, Bit
2
CHST, Bit
1
CHST, Bit 0
Start Status Group ADC Conversion with Digital
Redundancy and Poll Status
MD, Bit
1
MD, Bit
0
0
0
0
CHST, Bit
2
CHST, Bit
1
CHST, Bit 0
Start Self Test Status Group Conversion and Poll
Status
MD, Bit
1
MD, Bit
0
ST, Bit ST, Bit
1
0
1
1
1
1
1
1
1
1
1
0
Start Combined Cell Voltage and GPIO1, GPIO2
Conversion and Poll Status
MD, Bit
1
MD, Bit
0
1
1
DCP
DCP
Start Combined Cell Voltage and SC Conversion
and Poll Status
MD, Bit
1
MD, Bit
0
1
1
Clear Cell Voltage Register Groups
Clear Auxiliary Register Groups
Clear Status Register Groups
Poll ADC Conversion Status
Diagnose MUX and Poll Status
Write COMM Register Group
Read COMM Register Group
Start I2C/SPI Communication
Mute Discharge
CLRCELL
CLRAUX
CLRSTAT
PLADC
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
1
DIAGN
WRCOMM
RDCOMM
STCOMM
Mute
Unmute Discharge
Unmute
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Rev. 0 | 58 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 51. Command Bit Descriptions
Name
Description
Values
MD, Bits[1:0]
ADC Mode
MD
00
01
10
11
ADCOPT(CFGAR0, Bit 0) = 0
422 Hz mode
ADCOPT(CFGAR0, Bit 0) = 1
1 kHz mode
14 kHz mode
3 kHz mode
2 kHz mode
27 kHz mode (fast)
7 kHz mode (normal)
26 Hz mode (filtered)
DCP
Discharge Permitted
DCP
0
Discharge Not Permitted
Discharge Permitted
1
CH, Bits[2:0]
Cell Selection for
ADC Conversion
Total Conversion Time in the 8 ADC Modes
CH
000
001
010
011
100
101
110
27 kHz
1.1 ms
203 μs
203 μs
203 μs
203 μs
203 μs
203 μs
14 kHz
7 kHz
2.3 ms
407 μs
407 μs
407 μs
407 μs
407 μs
407 μs
3 kHz
3.0 ms
523 μs
523 μs
523 μs
523 μs
523 μs
523 μs
2 kHz
4.4 ms
756 μs
756 μs
756 μs
756 μs
756 μs
756 μs
1 kHz
7.2 ms
1.2 ms
1.2 ms
1.2 ms
1.2 ms
1.2 ms
1.2 ms
422 Hz
12.8 ms
2.2 ms
2.2 ms
2.2 ms
2.2 ms
2.2 ms
2.2 ms
26 Hz
201 ms
34 ms
34 ms
34 ms
34 ms
34 ms
34 ms
All cells
1.3 ms
232 μs
232 μs
232 μs
232 μs
232 μs
232 μs
Cells 1, 7, 13
Cells 2, 8, 14
Cells 3, 9, 15
Cells 4, 10, 16
Cells 5, 11, 17
Cells 6, 12, 18
PUP
Pull-Up/Pull- Down
Current for Open
Wire Conversions
PUP
0
1
Pull-down current
Pull-up current
ST, Bits[1:0]
Self Test Mode
Selection
Self Test Conversion Result
ST
01
10
27 kHz
0x9565
0x6A9A
14 kHz
0x9553
0x6AAC
7 kHz
0x9555
0x6AAA
3 kHz
0x9555
0x6AAA
2 kHz
0x9555
0x6AAA
1 kHz
0x9555
0x6AAA
422 Hz
0x9555
0x6AAA
26 Hz
0x9555
0x6AAA
Self Test 1
Self test 2
CHG, Bits[2:0]
GPIO Selection for
ADC Conversion
Total Conversion Time in the 8 ADC Modes
CHG
000
27 kHz
1.8 ms
14 kHz
2.1 ms
7 kHz
3 kHz
5.0ms
2 kHz
1 kHz
422 Hz
26 Hz
GPIO1 to
GPIO5, 2nd
Reference,
GPIO6 to
GPIO9
3.9 ms
7.4 ms
12.0 ms
21.3 ms
335 ms
001
010
011
100
GPIO1 and
GPIO6
380 μs
380 μs
380 μs
380 μs
439 μs
439 μs
439 μs
439 μs
788 μs
788 μs
788 μs
788 μs
1.0 ms
1.0 ms
1.0 ms
1.0 ms
1.5 ms
1.5 ms
1.5 ms
1.5 ms
2.4 ms
2.4 ms
2.4 ms
2.4 ms
4.3 ms
4.3 ms
4.3 ms
4.3 ms
67.1 ms
67.1 ms
67.1 ms
67.1 ms
GPIO2 and
GPIO7
GPIO3 and
GPIO8
GPIO4 and
GPIO9
101
110
GPIO5
200 μs
200 μs
229 μs
229 μs
403 μs
403 μs
520 μs
520 μs
753 μs
753 μs
1.2 ms
1.2 ms
2.1 ms
2.1 ms
34 ms
34 ms
2nd Reference
CHST,
Status Group
Selection
Total Conversion Time in the 8 ADC Modes
Bits[2:0]1
CHST
000
27 kHz
742 μs
14 kHz
858 μs
7 kHz
3 kHz
2 kHz
1 kHz
422 Hz
8.5 ms
26 Hz
SC, ITMP, VA,
VD
1.6 ms
2.0 ms
3.0 ms
4.8 ms
134 ms
analog.com
Rev. 0 | 59 of 89
Data Sheet
ADBMS1818
THEORY OF OPERATION
Table 51. Command Bit Descriptions
Name
Description
Values
520 μs
001
010
011
100
SC
ITMP
VA
200 μs
200 μs
200 μs
200 μs
229 μs
229 μs
229 μs
229 μs
403 μs
403 μs
403 μs
403 μs
753 μs
753 μs
753 μs
753 μs
1.2 ms
1.2 ms
1.2 ms
1.2 ms
2.1 ms
2.1 ms
2.1 ms
2.1 ms
34 ms
34 ms
34 ms
34 ms
520 μs
520 μs
520 μs
VD
1
Note: Valid options for CHST in ADSTAT command are 0 to 4. If CHST is set to 5/6 in ADSTAT command, the ADBMS1818 ignores the command.
analog.com
Rev. 0 | 60 of 89
Data Sheet
ADBMS1818
MEMORY MAP
Table 52. Configuration Register Group A
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CFGAR0
CFGAR1
CFGAR2
CFGAR3
CFGAR4
CFGAR5
R/W
R/W
R/W
R/W
R/W
R/W
GPIO5
VUV[7]
VOV[3]
VOV[11]
DCC8
GPIO4
VUV[6]
VOV[2]
VOV[10]
DCC7
GPIO3
VUV[5]
VOV[1]
VOV[9]
DCC6
GPIO2
VUV[4]
VOV[0]
VOV[8]
DCC5
GPIO1
VUV[3]
VUV[11]
VOV[7]
DCC4
REFON
VUV[2]
VUV[10]
VOV[6]
DCC3
DTEN
ADCOPT
VUV[0]
VUV[8]
VOV[4]
DCC1
VUV[1]
VUV[9]
VOV[5]
DCC2
DCTO[3]
DCTO[2]
DCTO[1]
DCTO[0]
DCC12
DCC11
DCC10
DCC9
Table 53. Configuration Register Group B
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CFGBR0
CFGBR1
CFGBR2
CFGBR3
CFGBR4
CFGBR5
R/W
R/W
R/W
R/W
R/W
R/W
DCC16
MUTE
DCC15
FDRF
DCC14
PS[1]
DCC13
PS[0]
GPIO9
DTMEN
RSVD0
RSVD0
RSVD0
RSVD0
GPIO8
DCC0
GPIO7
DCC18
RSVD0
RSVD0
RSVD0
RSVD0
GPIO6
DCC17
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
RSVD0
Table 54. Cell Voltage Register Group A
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVAR0
CVAR1
CVAR2
CVAR3
CVAR4
CVAR5
R
R
R
R
R
R
C1V[7]
C1V[15]
C2V[7]
C2V[15]
C3V[7]
C3V[15]
C1V[6]
C1V[14]
C2V[6]
C2V[14]
C3V[6]
C3V[14]
C1V[5]
C1V[13]
C2V[5]
C2V[13]
C3V[5]
C3V[13]
C1V[4]
C1V[12]
C2V[4]
C2V[12]
C3V[4]
C3V[12]
C1V[3]
C1V[11]
C2V[3]
C2V[11]
C3V[3]
C3V[11]
C1V[2]
C1V[10]
C2V[2]
C2V[10]
C3V[2]
C3V[10]
C1V[1]
C1V[9]
C2V[1]
C2V[9]
C3V[1]
C3V[9]
C1V[0]
C1V[8]
C2V[0]
C2V[8]
C3V[0]
C3V[8]
Table 55. Cell Voltage Register Group B
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVBR0
CVBR1
CVBR2
CVBR3
CVBR4
CVBR5
R
R
R
R
R
R
C4V[7]
C4V[15]
C5V[7]
C5V[15]
C6V[7]
C6V[15]
C4V[6]
C4V[14]
C5V[6]
C5V[14]
C6V[6]
C6V[14]
C4V[5]
C4V[13]
C5V[5]
C5V[13]
C6V[5]
C6V[13]
C4V[4]
C4V[12]
C5V[4]
C5V[12]
C6V[4]
C6V[12]
C4V[3]
C4V[11]
C5V[3]
C5V[11]
C6V[3]
C6V[11]
C4V[2]
C4V[10]
C5V[2]
C5V[10]
C6V[2]
C6V[10]
C4V[1]
C4V[9]
C5V[1]
C5V[9]
C6V[1]
C6V[9]
C4V[0]
C4V[8]
C5V[0]
C5V[8]
C6V[0]
C6V[8]
Table 56. Cell Voltage Register Group C
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVCR0
CVCR1
CVCR21
CVCR3 1
CVCR4
CVCR5
R
R
R
R
R
R
C7V[7]
C7V[6]
C7V[5]
C7V[4]
C7V[3]
C7V[2]
C7V[1]
C7V[9]
C8V[1] 1
C8V[9] 1
C9V[1]
C9V[9]
C7V[0]
C7V[8]
C8V[0] 1
C8V[8] 1
C9V[0]
C9V[8]
C7V[15]
C8V[7] 1
C8V[15] 1
C9V[7]
C7V[14]
C8V[6] 1
C8V[14] 1
C9V[6]
C7V[13]
C8V[5] 1
C8V[13] 1
C9V[5]
C7V[12]
C8V[4] 1
C8V[12] 1
C9V[4]
C7V[11]
C8V[3] 1
C8V[11] 1
C9V[3]
C7V[10]
C8V[2] 1
C8V[10] 1
C9V[2]
C9V[15]
C9V[14]
C9V[13]
C9V[12]
C9V[11]
C9V[10]
1
After performing the ADOL command, CVCR2 and CVCR3 of Cell Voltage Register Group C contain the result of measuring Cell 7 from ADC1.
Table 57. Cell Voltage Register Group D
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVDR0
CVDR1
R
R
C10V[7]
C10V[6]
C10V[5]
C10V[4]
C10V[3]
C10V[2]
C10V[1]
C10V[9]
C10V[0]
C10V[8]
C10V[15]
C10V[14]
C10V[13]
C10V[12]
C10V[11]
C10V[10]
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Rev. 0 | 61 of 89
Data Sheet
ADBMS1818
MEMORY MAP
Table 57. Cell Voltage Register Group D
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVDR2
CVDR3
CVDR4
CVDR5
R
R
R
R
C11V[7]
C11V[15]
C12V[7]
C12V[15]
C11V[6]
C11V[14]
C12V[6]
C12V[14]
C11V[5]
C11V[13]
C12V[5]
C12V[13]
C11V[4]
C11V[12]
C12V[4]
C12V[12]
C11V[3]
C11V[11]
C12V[3]
C12V[11]
C11V[2]
C11V[10]
C12V[2]
C12V[10]
C11V[1]
C11V[9]
C12V[1]
C12V[9]
C11V[0]
C11V[8]
C12V[0]
C12V[8]
Table 58. Cell Voltage Register Group E
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVER0
CVER1
CVER21
CVER3 1
CVER4
CVER5
R
R
R
R
R
R
C13V[7]
C13V[6]
C13V[5]
C13V[4]
C13V[3]
C13V[2]
C13V[1]
C13V[9]
C14V[1] 1
C14V[9] 1
C15V[1]
C15V[9]
C13V[0]
C13V[8]
C14V[0] 1
C14V[8] 1
C15V[0]
C15V[8]
C13V[15]
C14V[7] 1
C14V[15] 1
C15V[7]
C13V[14]
C14V[6] 1
C14V[14] 1
C15V[6]
C13V[13]
C14V[5] 1
C14V[13] 1
C15V[5]
C13V[12]
C14V[4] 1
C14V[12] 1
C15V[4]
C13V[11]
C14V[3] 1
C14V[11] 1
C15V[3]
C13V[10]
C14V[2] 1
C14V[10] 1
C15V[2]
C15V[15]
C15V[14]
C15V[13]
C15V[12]
C15V[11]
C15V[10]
1
After performing the ADOL command, CVER2 and CVER3 of Cell Voltage Register Group E contain the result of measuring Cell 13 from ADC2.
Table 59. Cell Voltage Register Group F
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CVFR0
CVFR1
CVFR2
CVFR3
CVFR4
CVFR5
R
R
R
R
R
R
C16V[7]
C16V[15]
C17V[7]
C17V[15]
C18V[7]
C18V[15]
C16V[6]
C16V[14]
C17V[6]
C17V[14]
C18V[6]
C18V[14]
C16V[5]
C16V[13]
C17V[5]
C17V[13]
C18V[5]
C18V[13]
C16V[4]
C16V[12]
C17V[4]
C17V[12]
C18V[4]
C18V[12]
C16V[3]
C16V[11]
C17V[3]
C17V[11]
C18V[3]
C18V[11]
C16V[2]
C16V[10]
C17V[2]
C17V[10]
C18V[2]
C18V[10]
C16V[1]
C16V[9]
C17V[1]
C17V[9]
C18V[1]
C18V[9]
C16V[0]
C16V[8]
C17V[0]
C17V[8]
C18V[0]
C18V[8]
Table 60. Auxiliary Register Group A
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AVAR0
AVAR1
AVAR2
AVAR3
AVAR4
AVAR5
R
R
R
R
R
R
G1V[7]
G1V[15]
G2V[7]
G2V[15]
G3V[7]
G3V[15]
G1V[6]
G1V[14]
G2V[6]
G2V[14]
G3V[6]
G3V[14]
G1V[5]
G1V[13]
G2V[5]
G2V[13]
G3V[5]
G3V[13]
G1V[4]
G1V[12]
G2V[4]
G2V[12]
G3V[4]
G3V[12]
G1V[3]
G1V[11]
G2V[3]
G2V[11]
G3V[3]
G3V[11]
G1V[2]
G1V[10]
G2V[2]
G2V[10]
G3V[2]
G3V[10]
G1V[1]
G1V[9]
G2V[1]
G2V[9]
G3V[1]
G3V[9]
G1V[0]
G1V[8]
G2V[0]
G2V[8]
G3V[0]
G3V[8]
Table 61. Auxiliary Register Group B
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AVBR0
AVBR1
AVBR2
AVBR3
AVBR4
AVBR5
R
R
R
R
R
R
G4V[7]
G4V[15]
G5V[7]
G5V[15]
REF[7]
REF[15]
G4V[6]
G4V[14]
G5V[6]
G5V[14]
REF[6]
REF[14]
G4V[5]
G4V[13]
G5V[5]
G5V[13]
REF[5]
REF[13]
G4V[4]
G4V[12]
G5V[4]
G5V[12]
REF[4]
REF[12]
G4V[3]
G4V[11]
G5V[3]
G5V[11]
REF[3]
REF[11]
G4V[2]
G4V[10]
G5V[2]
G5V[10]
REF[2]
REF[10]
G4V[1]
G4V[9]
G5V[1]
G5V[9]
REF[1]
REF[9]
G4V[0]
G4V[8]
G5V[0]
G5V[8]
REF[0]
REF[8]
Table 62. Auxiliary Register Group C
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AVCR0
AVCR1
AVCR2
AVCR3
R
R
R
R
G6V[7]
G6V[15]
G7V[7]
G7V[15]
G6V[6]
G6V[14]
G7V[6]
G7V[14]
G6V[5]
G6V[13]
G7V[5]
G7V[13]
G6V[4]
G6V[12]
G7V[4]
G7V[12]
G6V[3]
G6V[11]
G7V[3]
G7V[11]
G6V[2]
G6V[10]
G7V[2]
G7V[10]
G6V[1]
G6V[9]
G7V[1]
G7V[9]
G6V[0]
G6V[8]
G7V[0]
G7V[8]
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Rev. 0 | 62 of 89
Data Sheet
ADBMS1818
MEMORY MAP
Table 62. Auxiliary Register Group C
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AVCR4
AVCR5
R
R
G8V[7]
G8V[6]
G8V[5]
G8V[4]
G8V[3]
G8V[2]
G8V[1]
G8V[9]
G8V[0]
G8V[8]
G8V[15]
G8V[14]
G8V[13]
G8V[12]
G8V[11]
G8V[10]
Table 63. Auxiliary Register Group D
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AVDR0
AVDR1
AVDR2
AVDR3
AVDR4
AVDR5
R
R
R
R
R
R
G9V[7]
G9V[15]
RSVD1
RSVD1
C16OV
RSVD1
G9V[6]
G9V[14]
RSVD1
RSVD1
C16UV
RSVD1
G9V[5]
G9V[13]
RSVD1
RSVD1
C15OV
RSVD1
G9V[4]
G9V[12]
RSVD1
RSVD1
C15UV
RSVD1
G9V[3]
G9V[11]
RSVD1
RSVD1
C14OV
C18OV
G9V[2]
G9V[10]
RSVD1
RSVD1
C14UV
C18UV
G9V[1]
G9V[9]
RSVD1
RSVD1
C13OV
C17OV
G9V[0]
G9V[8]
RSVD1
RSVD1
C13UV
C17UV
Table 64. Status Register Group A
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STAR0
STAR1
STAR2
STAR3
STAR4
STAR5
R
R
R
R
R
R
SC[7]
SC[6]
SC[5]
SC[4]
SC[3]
SC[2]
SC[1]
SC[0]
SC[15]
ITMP[7]
ITMP[15]
VA[7]
SC[14]
ITMP[6]
ITMP[14]
VA[6]
SC[13]
ITMP[5]
ITMP[13]
VA[5]
SC[12]
ITMP[4]
ITMP[12]
VA[4]
SC[11]
ITMP[3]
ITMP[11]
VA[3]
SC[10]
ITMP[2]
ITMP[10]
VA[2]
SC[9]
SC[8]
ITMP[1]
ITMP[9]
VA[1]
ITMP[0]
ITMP[8]
VA[0]
VA[15]
VA[14]
VA[13]
VA[12]
VA[11]
VA[10]
VA[9]
VA[8]
Table 65. Status Register Group B
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STBR0
STBR1
STBR2
STBR3
STBR4
STBR5
R
R
R
R
R
R
VD[7]
VD[6]
VD[5]
VD[4]
VD[3]
VD[2]
VD[1]
VD[0]
VD[8]
C1UV
C5UV
C9UV
THSD
VD[15]
C4OV
C8OV
C12OV
REV[3]
VD[14]
C4UV
C8UV
C12UV
REV[2]
VD[13]
C3OV
C7OV
C11OV
REV[1]
VD[12]
C3UV
C7UV
C11UV
REV[0]
VD[11]
C2OV
C6OV
C10OV
RSVD
VD[10]
C2UV
C6UV
C10UV
RSVD
VD[9]
C1OV
C5OV
C9OV
MUXFAIL
Table 66. COMM Register Group
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
COMM0
COMM1
COMM2
COMM3
COMM4
COMM5
R/W
R/W
R/W
R/W
R/W
R/W
ICOM0[3]
D0[3]
ICOM0[2]
D0[2]
ICOM0[1]
D0[1]
ICOM0[0]
D0[0]
D0[7]
D0[6]
D0[5]
D0[4]
FCOM0[3]
D1[7]
FCOM0[2]
D1[6]
FCOM0[1]
D1[5]
FCOM0[0]
D1[4]
ICOM1[3]
D1[3]
ICOM1[2]
D1[2]
ICOM1[1]
D1[1]
ICOM1[0]
D1[0]
FCOM1[3]
D2[7]
FCOM1[2]
D2[6]
FCOM1[1]
D2[5]
FCOM1[0]
D2[4]
ICOM2[3]
D2[3]
ICOM2[2]
D2[2]
ICOM2[1]
D2[1]
ICOM2[0]
D2[0]
FCOM2[3]
FCOM2[2]
FCOM2[1]
FCOM2[0]
Table 67. S Control Register Group
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCTRL0
SCTRL1
SCTRL2
SCTRL3
SCTRL4
SCTRL5
R/W
R/W
R/W
R/W
R/W
R/W
SCTL2[3]
SCTL4[3]
SCTL6[3]
SCTL8[3]
SCTL10[3]
SCTL12[3]
SCTL2[2]
SCTL4[2]
SCTL6[2]
SCTL8[2]
SCTL10[2]
SCTL12[2]
SCTL2[1]
SCTL4[1]
SCTL6[1]
SCTL8[1]
SCTL10[1]
SCTL12[1]
SCTL2[0]
SCTL4[0]
SCTL6[0]
SCTL8[0]
SCTL10[0]
SCTL12[0]
SCTL1[3]
SCTL3[3]
SCTL5[3]
SCTL7[3]
SCTL9[3]
SCTL11[3]
SCTL1[2]
SCTL3[2]
SCTL5[2]
SCTL7[2]
SCTL9[2]
SCTL11[2]
SCTL1[1]
SCTL3[1]
SCTL5[1]
SCTL7[1]
SCTL9[1]
SCTL11[1]
SCTL1[0]
SCTL3[0]
SCTL5[0]
SCTL7[0]
SCTL9[0]
SCTL11[0]
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Data Sheet
ADBMS1818
MEMORY MAP
Table 68. PWM Register Group
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWMR0
PWMR1
PWMR2
PWMR3
PWMR4
PWMR5
R/W
R/W
R/W
R/W
R/W
R/W
PWM2[3]
PWM4[3]
PWM6[3]
PWM8[3]
PWM10[3]
PWM12[3]
PWM2[2]
PWM4[2]
PWM6[2]
PWM8[2]
PWM10[2]
PWM12[2]
PWM2[1]
PWM4[1]
PWM6[1]
PWM8[1]
PWM10[1]
PWM12[1]
PWM2[0]
PWM4[0]
PWM6[0]
PWM8[0]
PWM10[0]
PWM12[0]
PWM1[3]
PWM3[3]
PWM5[3]
PWM7[3]
PWM9[3]
PWM11[3]
PWM1[2]
PWM3[2]
PWM5[2]
PWM7[2]
PWM9[2]
PWM11[2]
PWM1[1]
PWM3[1]
PWM5[1]
PWM7[1]
PWM9[1]
PWM11[1]
PWM1[0]
PWM3[0]
PWM5[0]
PWM7[0]
PWM9[0]
PWM11[0]
Table 69. PWM/S Control Register Group B
Register
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PSR0
PSR1
PSR2
PSR3
PSR4
PSR5
R/W
R/W
R/W
R/W
R/W
R/W
PWM14[3]
PWM16[3]
PWM18[3]
SCTL14[3]
SCTL16[3]
SCTL18[3]
PWM14[2]
PWM16[2]
PWM18[2]
SCTL14[2]
SCTL16[2]
SCTL18[2]
PWM14[1]
PWM16[1]
PWM18[1]
SCTL14[1]
SCTL16[1]
SCTL18[1]
PWM14[0]
PWM16[0]
PWM18[0]
SCTL14[0]
SCTL16[0]
SCTL18[0]
PWM13[3]
PWM15[3]
PWM17[3]
SCTL13[3]
SCTL15[3]
SCTL17[3]
PWM13[2]
PWM15[2]
PWM17[2]
SCTL13[2]
SCTL15[2]
SCTL17[2]
PWM13[1]
PWM15[1]
PWM7[1]
PWM13[0]
PWM15[0]
PWM17[0]
SCTL13[0]
SCTL15[0]
SCTL17[0]
SCTL13[1]
SCTL15[1]
SCTL17[1]
Table 70. Memory Map Bit Descriptions
GPIOx
GPIOx pin control
Write: 0 → GPIOx pin pull-down on, 1 → GPIOx pin pull-down off (default)
Read: 0 → GPIOx pin at Logic 0, 1 → GPIOx pin at Logic 1
1: reference remains powered up until watchdog timeout
REFON
DTEN
Reference powered
up
Discharge timer ena-
ble (read only)
0: reference shuts down after conversions (default)
1: enables the discharge timer for discharge switches
ADCOPT
ADC mode option bit
0 → selects modes 27 kHz, 7 kHz, 422 Hz or 26 Hz with MD, Bits[1:0] in ADC conversion commands (default)
1 → selects modes 14 kHz, 3 kHz, 1 kHz, or 2 kHz with MD, Bits[1:0] in ADC conversion commands
Comparison voltage = (VUV + 1) × 16 × 100 μV, default: VUV = 0x000
VUV
Undervoltage com-
parison voltage1
VOV
Overvoltage compari- Comparison voltage = VOV × 16 × 100 μV, default: VOV = 0x000
son voltage1
DCC[x]
Discharge Cell x
x = 1 to 18:
1: turn on shorting switch for Cell x
0: turn off shorting switch for Cell x (default)
x = 0:
1: turn on GPIO9 pull-down
0: turn off GPIO9 pull-down (default)
DCTO
Discharge time out
value
DCT
O
0
1
2
1
2
3
2
3
4
3
4
5
4
5
6
5
6
7
8
9
A
B
C
D
E
F
(write
)
Time Disa- 0.5
10
7
15
8
20
9
30
A
40
B
60
C
75
D
90
E
120
F
(mi-
nutes
)
bled
DCT
O
0
1
(read)
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Rev. 0 | 64 of 89
Data Sheet
ADBMS1818
MEMORY MAP
Table 70. Memory Map Bit Descriptions
Time Disa- 0 to
0.5 to 1 to 2 2 to 3 3 to 4 4 to 5 5 to
10
10 to 15 to 20 to 30 to 40 to 60 to 75 to 90 to
left
bled
or
0.5
1
15
20
30
40
60
75
90
120
(mi-
nutes time-
out
)
MUTE
FDRF
Mute status (read on- 1: mute is activated and discharging is disabled
ly)
0: mute is deactivated
Force digital redun-
dancy failure
1: forces the digital redundancy comparison for ADC conversions to fail
0: enables the normal redundancy comparison
PS,
Digital redundancy
path selection
11: redundancy is applied only to the ADC3 digital path
Bits[1:0]
10: redundancy is applied only to the ADC2 digital path
01: redundancy is applied only to the ADC1 digital path
00: redundancy is applied sequentially to the ADC1, ADC2, and ADC3 digital paths during cell conversions and applied to ADC1 during
AUX and STATUS conversions
DTMEN
CxV
Enable discharge tim- 1: enables the discharge timer monitor function if the DTEN pin is asserted
er monitor
0: disables the discharge timer monitor function. The normal discharge timer function is enabled if the DTEN pin is asserted
Cell x voltage1
x = 1 to 18
16-bit ADC measurement value for Cell x
Cell voltage for Cell x = CxV × 100 μV
CxV is rest to 0xFFFF on power-up and after clear command
x = 1 to 9
GxV
GPIO x voltage1
16-bit ADC measurement value for GPIOx
Voltage for GPIOx = GxV × 100 μV
GxV is reset to 0xFFFF on power-up and after clear command
16-bit ADC measurement value for 2nd reference
REF
SC
2nd reference volt-
age1
Sum of all cells meas- 16-bit ADC measurement value of the sum of all cell voltages, sum of all cells voltage = SC × 100 μV × 30
urement1
ITMP
VA
Internal die tempera-
ture1
16-bit ADC measurement value of the internal die temperature, temperature measurement voltage = ITMP × 100 μV/7.6mV/°C − 276°C
Analog power supply
voltage1
16-bit ADC measurement value of the analog power supply voltage, analog power supply voltage = VA × 100 μV, the value of VA is set by
external components that must be in the range of 4.5 V to 5.5 V for normal operation
VD
Digital power supply
voltage1
16-bit ADC measurement value of the digital power supply voltage, digital power supply voltage = VD × μV, normal range is within 2.7 V
to 3.6 V
CxOV
Cell x overvoltage flag x = 1 to 18
Cell voltage compared to VOV comparison voltage
0: Cell x not flagged for overvoltage condition
1: Cell x flagged
CxUV
Cell x undervoltage
flag
x = 1 to 18
Cell voltage compared to VUV comparison voltage
0: Cell x not flagged for overvoltage condition
1: Cell x flagged
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Rev. 0 | 65 of 89
Data Sheet
ADBMS1818
MEMORY MAP
Table 70. Memory Map Bit Descriptions
REV
Revision code
Reserved bits
Reserved bits
Reserved bits
Device revision code
RSVD
Read: read back value can be 1 or 0
Read: read back value is always 0
RSVD0
RSVD1
MUXFAIL
Read: read back value is always 1
Multiplexer self test
result
Read: 0 → multiplexer passed self test, 1 → multiplexer failed self test
THSD
Thermal shutdown
status
Read: 0 → thermal shutdown has not occurred, 1 → thermal shutdown has occurred, THSD Bit cleared to 0 on read of Status Register
Group B
SCTx[x]
S pin control bits
0000: drive S pin high (deasserted)
0001: send 1 high pulse on S pin
0010: send 2 high pulses on S pin
0011: send 3 high pulses on S pin
0100: send 4 high pulses on S pin
0101: send 5 high pulses on S pin
0110: send 6 high pulses on S pin
0111: send 7 high pulses on S pin
1xxx: drive S pin low (asserted)
PWMx[x]
PWM discharge con-
trol
0000: selects 0% discharge duty cycle if DCCx = 1 and watchdog timer has expired
0001: selects 6.7% discharge duty cycle if DCCx = 1 and watchdog timer has expired
0010: selects 13.3% discharge duty cycle if DCCx = 1 and watchdog timer has expired
...
1110: selects 93.3% discharge duty cycle if DCCx = 1 and watchdog timer has expired
1111: selects 100% discharge duty cycle if DCCx = 1 and watchdog timer has expired
ICOMn
Initial communication Write
bits
I2C
0110
0001
0000
0111
Start
Stop
Blank
No transmit
1111
SPI
I2C
1000
1010
1001
CSB low
0110
CSB falling edge
0001
CSB high
0000
No transmit
0111
Read
Start from master
stop from master
SDA low between
bytes
SDA high be-
tween bytes
SPI
0111
0001
1000
0000
0111
Dn
I2C/SPI communica-
tion data byte
Data transmitted (received) to (from) I2C/SPI slave device
FCOMn
Final communication
control bits
Write
I2C
0000
1001
Master ACK
X000
Master NACK
1001
Master NACK + stop
SPI
I2C
CSB high
1111
Read
0000
0111
0001
1001
ACK from
master
ACK from
slave
NACK from
slave
ACK from
NACK from slave +
stop from master
slave + stop
from master
SPI
1111
1
Voltage equations use the decimal value of registers, 0 to 4095 for 12 bits and 0 to 65535 for 16 bits.
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Data Sheet
ADBMS1818
MEMORY MAP
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Rev. 0 | 67 of 89
Data Sheet
ADBMS1818
APPLICATIONS INFORMATION
PROVIDING DC POWER
Simple Linear Regulator
The primary supply pin for the ADBMS1818 is the 5 V (±0.5 V)
VREG input pin. To generate the required 5 V supply for VREG
,
the DRIVE pin can be used to form a discrete regulator with the
addition of a few external components, as shown in Figure 93. The
DRIVE pin provides a 5.7 V output, capable of sourcing 1 mA.
When buffered with an NPN transistor, the DRIVE pin provides a
stable 5 V over temperature. The NPN transistor must be chosen
to have a sufficient Beta over temperature (> 40) to supply the
necessary supply current. The peak VREG current requirement of
the ADBMS1818 approaches 35 mA when simultaneously commu-
nicating over isoSPI and making ADC conversions. If the VREG pin
is required to support any additional load, a transistor with an even
higher Beta may be required.
Figure 94. VREG Powered From Cell Stack with High Efficiency Regulator
INTERNAL PROTECTION AND FILTERING
Internal Protection Features
The ADBMS1818 incorporates various ESD safeguards to ensure
robust performance. An equivalent circuit showing the specific
protection structures is shown in Figure 95. Zener- like suppressors
are shown with their nominal clamp voltage, and the unmarked
diodes exhibit standard PN junction behavior.
Filtering of Cell and GPIO Inputs
The ADBMS1818 uses a Δ-Σ ADC, which includes a Δ-Σ modulator
followed by a sinc3 finite impulse response (FIR) digital filter,
which greatly relaxes input filtering requirements. Furthermore, the
programmable oversampling ratio allows the user to determine
the best trade-off between measurement speed and filter cutoff fre-
quency. Even with this high order low-pass filter, fast transient noise
can still induce some residual noise in measurements, especially
in the faster conversion modes. This noise can be minimized by
adding an RC, low-pass decoupling to each ADC input, which also
helps reject potentially damaging high energy transients. Adding
more than about 100 Ω to the ADC inputs begins to introduce a
systematic error in the measurement, which can be improved by
raising the filter capacitance or mathematically compensating in
software with a calibration procedure. For situations that demand
the highest level of battery voltage ripple rejection, grounded ca-
pacitor filtering is recommended. This configuration has a series
resistance and capacitors that decouple high frequency noise to
V–. In systems where noise is less periodic or higher oversampling
rates are in use, a differential capacitor filter structure is adequate.
In this configuration there are series resistors to each input, but
the capacitors connect between the adjacent C pins. However,
the differential capacitor sections interact. As a result, the filter
response is less consistent and results in less attenuation than
predicted by the RC, by approximately a decade. Note that the
capacitors only see one cell of applied voltage (thus smaller and
lower cost) and tend to distribute transient energy uniformly across
the IC (reducing stress events on the internal protection structure).
Figure 96 shows the two methods schematically. ADC accuracy
varies with R and C as shown in the typical performance curves,
but the error is minimized if R = 100 Ω and C = 10 nF. The GPIO
pins always use a grounded capacitor configuration because the
measurements are all with respect to V–.
Figure 93. Simple VREG Power Source Using NPN Pass Transistor
The NPN collector can be powered from any voltage source that
is a minimum 6 V above V–. This includes the cells that are being
monitored, or an unregulated power supply. A 100 Ω, 100 nF
RC decoupling network is recommended for the collector power
connection to protect the NPN from transients. The emitter of the
NPN must be bypassed with a 1 µF capacitor. Larger capacitance
must be avoided because this increases the wake-up time of the
ADBMS1818. Some attention must be given to the thermal charac-
teristic of the NPN, as there can be significant heating with a high
collector voltage.
Improved Regulator Power Efficiency
For improved efficiency when powering the ADBMS1818 from the
cell stack, VREG can be powered from a dc-to-dc converter, rather
than the NPN pass transistor. An ideal circuit is based on the
LT8631 step-down regulator, as shown in Figure 94. A 100 Ω
resistor is recommended between the battery stack and the LT8631
input, which prevents in-rush current when connecting to the stack
and reduces conducted electromagnetic interference (EMI). The
EN/UV pin must be connected to the DRIVE pin, which puts the
LT8631 into a low power state when the ADBMS1818 is in the sleep
state.
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Figure 95. Internal ESD Protection Structures of the ADBMS1818
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Figure 96. Input Filter Structure Configurations
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ADCV command. Figure 98 shows the standard ADCV command
sequence. Figure 98 shows the recommended command sequence
and timing that allow the mux to settle. The purpose of the modified
procedure is to allow the mux to settle at C1/C7/C13 before the
start of the measurement cycle. The delay between the C1/C7/C13
ADCV command and the all channel ADCV command is dependent
on the time constant of the RC being used. The general guidance
is to wait 6τ between the C1/C7/C13 ADCV command and the
all channel ADCV command. Figure 97 shows the expected TME
when using the recommended command sequence.
Using Nonstandard Cell Input Filters
A cell pin filter of 100 Ω and 10 nF is recommended for all applica-
tions. This filter provides the best combination of noise rejection
and TME performance. In applications that use C pin RC filters
larger than 100 Ω and 10 nF, there may be additional measurement
error. Figure 97 shows how both total TME and TME variation
increase as the RC time constant increases. The increased error
is related to the mux settling. It is possible to reduce TME lev-
els to near data sheet specifications by implementing an extra
single channel conversion before issuing a standard all channel
Figure 97. Cell Measurement TME
Figure 98. ADC Command Order
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Data Sheet
ADBMS1818
APPLICATIONS INFORMATION
transistors. The ADBMS1818 includes an internal pull-up PMOS
transistor with a 1 kΩ series resistor. The S pins can act as digital
outputs suitable for driving the gate of an external MOSFET, as
shown in Figure 99. Figure 96 shows external MOSFET circuits that
include RC filtering. For applications with very low cell voltages, the
PMOS in Figure 99 can be replaced with a PNP. When a PNP is
used, the resistor in series with the base must be reduced.
CELL BALANCING
Cell Balancing with Internal MOSFETs
With passive balancing, if one cell in a series stack becomes over-
charged, an S output can slowly discharge this cell by connecting it
to a resistor. Each S output is connected to an internal N-channel
MOSFET with a maximum on resistance of 10 Ω. An external
resistor must be connected in series with these MOSFETs to allow
most of the heat to be dissipated outside of the ADBMS1818
package, as shown in Figure 99.
Choosing a Discharge Resistor
When sizing the balancing resistor, it is important to know the
typical battery imbalance and the allowable time for cell balancing.
In most small battery applications, it is reasonable for the balancing
circuitry to be able to correct for a 5% state of charge (SOC) error
with 5 hours of balancing. For example, a 5 AHr battery with a 5%
SOC imbalance has approximately 250 mA Hrs of imbalance. Using
a 50 mA balancing current, the error can be corrected in 5 hours.
With a 100 mA balancing current, the error can be corrected in 2.5
hours. In systems with very large batteries, it is difficult to use pas-
sive balancing to correct large SOC imbalances in short periods of
time. The excessive heat created during balancing generally limits
the balancing current. In large capacity battery applications, if short
balancing times are required, an active balancing solution must
be considered. When choosing a balance resistor, the following
equations can be used to help determine a resistor value:
The internal discharge switches (MOSFETs) S1 through S18 can
be used to passively balance cells as shown in Figure 99 with
balancing current of 200 mA or less (80 mA or less if the die
temperature is over 85°C). Balancing current larger than 200 mA
is not recommended for the internal switches due to excessive
die heating. When discharging cells with the internal discharge
switches, the die temperature must be monitored. See the Thermal
Shutdown section.
Note that the antialiasing filter resistor is part of the discharge path
and must be removed or reduced. Use of an RC for added cell
voltage measurement filtering is permitted, but the filter resistor
must remain small, typically around 10 Ω to reduce the effect on the
balance current.
Balance Current =
%
of SOC Imbalance × Battery Capacity
Number of Hours to Balance
Balance Resistor =
Nominal Cell Voltage
Balance Current
Active Cell Balancing
Applications that require 1 A or greater of cell balancing current
must consider implementing an active balancing system. Active
balancing allows for much higher balancing currents without the
generation of excessive heat. Active balancing also allows for ener-
gy recovery since most of the balance current is redistributed back
to the battery pack. Figure 100 shows a simple active balancing
implementation using the LT8584. The LT8584 also has advanced
features that can be controlled via the ADBMS1818. See the S Pin
Pulsing Using the S Pin Control Settings section and the LT8584
data sheet for more details.
Figure 99. Internal/External Discharge Circuits
Cell Balancing with External Transistors
For applications that require balancing currents above 200 mA or
large cell filters, the S outputs can be used to control external
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Data Sheet
ADBMS1818
APPLICATIONS INFORMATION
Figure 100. 18-Cell Battery Stack Module with Active Balancing
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Data Sheet
ADBMS1818
APPLICATIONS INFORMATION
fast enough for the cell voltage to completely settle before the
measurement starts. For the best measurement accuracy when
running discharge, the mute and unmute commands must be
used. The mute command can be issued to temporarily disable
all discharge transistors before the ADCV command is issued. After
the cell conversion completes, an unmute command can be sent
to reenable all discharge transistors that were previously on. Using
this method maximizes the measurement accuracy with a very
small time penalty.
DISCHARGE CONTROL DURING CELL
MEASUREMENTS
If the discharge permitted (DCP) bit is high at the time of a cell
measurement command, the S pin discharge states do not change
during cell measurements. If the DCP bit is low, S pin discharge
states are disabled while the corresponding cell or adjacent cells
are being measured. If using an external discharge transistor, the
relatively low 1 kΩ impedance of the internal ADBMS1818 PMOS
transistors allow the discharge currents to fully turn off before the
cell measurement. Table 71 shows the ADCV command with DCP
= 0. In this table, off indicates that the S pin discharge is forced off
irrespective of the state of the corresponding DCC bit. On indicates
that the S pin discharge remains on during the measurement period
if it was on prior to the measurement command.
Method to Verify Discharge Circuits
When using the internal discharge feature, the ability to verify
discharge functionality can be implemented in the software. In
applications using an external discharge MOSFET, an additional
resistor can be added between the battery cell and the source of
the discharge MOSFET, which allows the system to test discharge
functionality.
In some cases, it is not possible for the automatic discharge
control to eliminate all measurement error caused by running the
discharges. This is due to the discharge transistor not turning off
Table 71. Discharge Control During an ADCV Command with DCP = 0
Cell Measurement Periods
Cell Calibration Periods
Cell 1,
Cell 7,
Cell 13
Cell 2,
Cell 8,
Cell 14
Cell 3,
Cell 9,
Cell 15
Cell 1,
Cell 4, Cell Cell 5, Cell Cell 6, Cell Cell 7,
10, Cell 16 11, Cell 17 12, Cell 18 Cell 13
Cell 2,
Cell 8,
Cell 14
Cell 3,
Cell 9,
Cell 15
Cell 4, Cell Cell 5, Cell Cell 6, Cell
10, Cell 16 11, Cell 17 12, Cell 18
Discharge Pin
t0 to t1M
t1M to t2M t2M to t3M t3M to t4M
t4M to t5M
t5M to t6M
t6M to t1C t1C to t2C t2C to t3C t3C to t4C
t4C to t5C
t5C to t6C
S1
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
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Data Sheet
ADBMS1818
APPLICATIONS INFORMATION
Both circuits are shown in Figure 101. The functionality of the
discharge circuits can be verified by conducting cell measurements
and comparing measurements when the discharge is off to meas-
urements when the discharge is on. The measurement taken when
the discharge is on requires that the discharge permit (DCP) bit
be set. The change in the measurement when the discharge is
turned on is calculable based on the resistor values. The following
algorithm can be used in conjunction with Figure 101 to verify each
discharge circuit:
DIGITAL COMMUNICATIONS
PEC Calculation
The PEC can be used to ensure that the serial data read from the
ADBMS1818 is valid and has not been corrupted. This feature is
critical for reliable communication, particularly in environments of
high noise. The ADBMS1818 requires that a PEC be calculated for
all data being read from and written to the ADBMS1818. For this
reason, it is important to have an efficient method for calculating the
PEC.
► Step 1: Measure all cells with no discharging (all S outputs off)
and read and store the results.
The C code provides a simple implementation of a lookup table
derived PEC calculation method. There are two functions. The first
function init_PEC15_Table() must only be called once when the
microcontroller starts and initializes a PEC15 table array called
pec15Table[]. This table is used in all future PEC calculations.
The PEC15 table can also be hard coded into the microcontroller
rather than running the init_PEC15_Table() function at startup. The
pec15() function calculates the PEC and returns the correct 15-bit
PEC for byte arrays of any given length.
► Step 2: Turn on S1, S7, and S13.
► Step 3: Measure C1 to C0, C7 to C6, and C13 to C12.
► Step 4: Turn off S1, S7, and S13.
► Step 5: Turn on S2, S8, and S14.
► Step 6: Measure C2 to C1, C8 to C7, and C14 to C13.
► Step 7: Turn off S2, S8, and S14.
► ...
► Step 17: Turn on S6, S12, and S18.
► Step 18: Measure C6 to C5, C12 to C11, and C18 to C17.
► Step 19: Turn off S6, S12, and S18.
/************************************
Copyright 2012 Analog Devices, Inc. (ADI)
► Step 20: Read the Cell Voltage Register Groups to get the
results of Step 2 through Step 19.
Permission to freely use, copy, modify, and distribute this software
for any purpose with or without fee is hereby granted, provided
that the above copyright notice and this permission notice appear
in all copies: THIS SOFTWARE IS PROVIDED “AS IS” AND ADI
DISCLAIMS ALL WARRANTIES
► Step 21: Compare new readings with old readings. Each cell
voltage reading must have decreased by a fixed percentage set
by RDISCHARGE and RFILTER for internal designs and RDISCHARGE1
and RDISCHARGE2 for external MOSFET designs. The exact
amount of the decrease depends on the resistor values and
MOSFET characteristics.
INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS. IN NO EVENT SHALL ADI BE LIABLE FOR ANY
SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES
OR ANY DAMAGES WHATSOEVER RESULTING FROM ANY
USE OF SAME, INCLUDING ANY LOSS OF USE OR DATA
OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLI-
GENCE OR OTHER TORTUOUS ACTION, ARISING OUT OF OR
IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
SOFTWARE.
***************************************/
int16 pec15Table[256];
int16 CRC15_POLY = 0x4599;
void init_PEC15_Table()
{
for (int i = 0; i < 256; i++)
Figure 101. Balancing Self Test Circuit
{
remainder = i << 7;
for (int bit = 8; bit > 0; --bit)
{
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Data Sheet
ADBMS1818
APPLICATIONS INFORMATION
if (remainder & 0x4000)
by the RB1 and RB2 resistors. The receiver threshold is half of the
voltage present on the ICMP pin.
{
The following guidelines must be followed when setting IB (100 μA
to 1 mA) and the receiver comparator threshold voltage VICMP/2:
remainder = ((remainder << 1));
remainder = (remainder ^ CRC15_POLY)
RM = Transmission Line Cℎaracteristic
}
Impedance Z0
else
Signal Amplitude = VA
=
20
×
IB
×
RM/2
{
Receiver Comparator Threshold (VTCMP) = K × VA
Voltage on ICMP Pin (VCIMP) = 2 × VTCMP
RB2 = VICMP/IB
remainder = ((remainder << 1));
}
}
RB1 = (2/IB) - (RB2
)
pec15Table[i] = remainder&0xFFFF;
Select IB and K (signal amplitude VA to receiver comparator thresh-
old ratio) according to the application:
}
► For lower power links: IB = 0.5 mA and K = 0.5.
► For full power links: IB = 1 mA and K = 0.5.
► For long links (>50m): IB = 1 mA and K = 0.25.
}
unsigned int16 pec15 (char *data , int len)
{
For applications with little system noise, setting IB to 0.5 mA is a
good compromise between power consumption and noise immuni-
ty. Using this IB setting with a 1:1 transformer and RM = 100 Ω,
RB1 must be set to 3.01 k, and RB2 set to 1 kΩ. With a typical
CAT5 twisted pair, these settings allow communication up to 50 m.
For applications in very noisy environments or that require cables
longer than 50 m, it is recommended to increase IB to 1 mA. Higher
drive current compensates for the increased insertion loss in the
cable and provides high noise immunity. When using cables over
50 m and a transformer with a 1:1 turns ratio and RM = 100 Ω, RB1
is 1.5 k, and RB2 is 499 Ω.
int16 remainder,address;
remainder = 16;//PEC seed
for (int i = 0; i < len; i++)
{
address = ((remainder >> 7) ^ data[i]) & 0xff;//calculate PEC table
address remainder = (remainder << 8 ) ^ pec15Table[address];
}
return (remainder*2);//The CRC15 has a 0 in the LSB so the final
value must be multiplied by 2
The maximum clock rate of an isoSPI link is determined by the
length of the isoSPI cable. For cables 10 m or less, the maximum
1 MHz SPI clock frequency is possible. As the length of the cable
increases, the maximum possible SPI clock rate decreases. This
dependence is a result of the increased propagation delays that
can create possible timing violations. Figure 102 shows how the
maximum data rate reduces as the cable length increases when
using a CAT5 twisted pair.
}
isoSPI IBIAS and ICMP Setup
The ADBMS1818 allows the isoSPI links of each application to
be optimized for power consumption or for noise immunity. The
power and noise immunity of an isoSPI system is determined by
the programmed IB current, which controls the isoSPI signaling
currents. IB can range from 100 μA to 1 mA. Internal circuitry scales
up this bias current to create the isoSPI signal currents equal to
be 20 × IB. A low IB reduces the isoSPI power consumption in the
ready and active states, whereas a high IB increases the amplitude
of the differential signal voltage VA across the matching termination
resistor, RM. The IB current is programmed by the sum of the RB1
and RB2 resistors connected between the 2 V IBIAS pin and GND,
as shown in Figure 103. The receiver input threshold is set by the
ICMP voltage that is programmed with the resistor divider created
Cable delay affects three timing specifications: tCLK, t6, and t7. In
the electrical characteristics table, each of these specifications is
derated by 100 ns to allow for 50 ns of cable delay. For longer
cables, the minimum timing parameters may be calculated as
shown below:
tCLK, t6, and t7 > 0.9 μs + 2 × tCABLE (0.2 m per ns)
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Data Sheet
ADBMS1818
APPLICATIONS INFORMATION
Figure 102. Data Rate vs. Cable Length
Figure 103. isoSPI Circuit
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Data Sheet
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the serial timing and affects data latency and throughput. The
maximum number of devices in an isoSPI daisy chain is strictly
dictated by the serial timing requirements. However, it is important
to note that the serial read back time, and the increased current
consumption, might dictate a practical limitation.
Implementing a Modular isoSPI Daisy Chain
The hardware design of a daisy-chain isoSPI bus is identical for
each device in the network due to the daisy-chain point to point
architecture. The simple design as shown in Figure 103 is function-
al, but inadequate for most designs. The termination resistor, RM,
must be split and bypassed with a capacitor, as shown in Figure
104. This change provides both a differential and a common mode
termination, and as such, increases the system noise immunity.
For a daisy chain, the following two timing considerations for proper
operation dominate (see Figure 86):
1. t6, the time between the last clock and the rising chip select,
must be long enough.
2. t5, the time from a rising chip select to the next falling chip
select (between commands), must be long enough.
Both t5 and t6 must be lengthened as the number of
ADBMS1818 devices in the daisy chain increases. The equa-
tions for these times are below:
t5 > (Number of Devices × 70 ns) + 900 ns, t6 > (Number of
Devices × 70 ns) + 950 ns
Connecting Multiple ADBMS1818s on the Same
PCB
Figure 104. Daisy Chain Interface Components
When connecting multiple ADBMS1818 devices on the same PCB,
only a single transformer is required between the ADBMS1818
isoSPI ports. The absence of the cable also reduces the noise
levels on the communication lines and often only a split termination
is required. Figure 105 shows an example application that has
multiple ADBMS1818 devices on the same PCB, communicating to
the bottom MCU through an LTC6820 isoSPI driver. If a transformer
with a center tap is used, a capacitor can be added for improved
noise rejection. Additional noise filtering can be provided with dis-
crete common-mode chokes (not shown) placed on both sides of
the single transformer.
The use of cables between battery modules, particularly in hazard
applications, can lead to increased noise susceptibility in the com-
munication lines. For high levels of electromagnetic interference
(EMC), additional filtering is recommended. The circuit example in
Figure 104 shows the use of common-mode chokes (CMC) to add
common-mode noise rejection from transients on the battery lines.
The use of a center tapped transformer also provides additional
noise performance. A bypass capacitor connected to the center tap
creates a low impedance for common-mode noise (see Figure 104).
Since transformers without a center tap can be less expensive, they
may be preferred. In this case, the addition of a split termination
resistor and a bypass capacitor (see Figure 104) can enhance the
isoSPI performance. Large center tap capacitors greater than 10 nF
must be avoided as they may prevent the isoSPI common-mode
voltage from settling. Common-mode chokes similar to those used
in Ethernet or CANbus applications are recommended. Specific
examples are provided in Table 73.
On single board designs with low noise requirements, it is possible
for a simplified capacitor isolated coupling as shown in Figure 106
to replace the transformer.
In this circuit, the transformer is directly replaced by two 10 nF
capacitors. An optional CMC provides noise rejection similar to
application circuits using transformers. The circuit is designed to
use IBIAS and ICMP settings identical to the transformer circuit.
An important daisy chain design consideration is the number of
devices in the isoSPI network. The length of the chain determines
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Data Sheet
ADBMS1818
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Figure 105. Daisy Chain Interface Components on Single Board
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Data Sheet
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Figure 106. Capacitive Isolation Coupling for ADBMS1818s on the Same PCB
the receiver as the time the signal is above the threshold set at
the ICMP pin. Slow rise and fall times cut into the timing margins.
Generally, it is best to keep pulse edges as fast as possible. When
evaluating transformers, it is also worth noting the parallel winding
capacitance. While transformers have very good CMRR at a low
frequency, this rejection degrades at higher frequencies, largely due
to the winding to winding capacitance. When choosing a transform-
er, it is best to pick one with less parallel winding capacitance when
possible.
Connecting an MCU to an ADBMS1818 with an
isoSPI Data Link
The LTC6820 converts a standard 4-wire SPI into a 2-wire iso-
SPI link that can communicate directly with the ADBMS1818. An
example is shown in Figure 107. The LTC6820 can be used in
applications to provide isolation between the microcontroller and
the stack of ADBMS1818 devices. The LTC6820 also enables
system configurations that have the battery management system
(BMS) controller at a remote location relative to the ADBMS1818
devices and the battery pack.
When choosing a transformer, it is equally important to pick a
device that has an adequate isolation rating for the application.
The working voltage rating of a transformer is a key specification
when selecting a device for an application. Interconnecting daisy-
chain links between ADBMS1818 devices see <60 V stress in
typical applications. Ordinary pulse and local area network (LAN)
type transformers suffice. Connections to the LTC6820, in general,
may need much higher working voltage ratings for good long-term
reliability. Usually, matching the working voltage to the voltage of
the entire battery stack is conservative. Unfortunately, transformer
vendors often only specify one-second high voltage testing, and
this is not equal to the long-term (permanent) rating of the device.
For example, according to most safety standards, a 1.5 kV rated
transformer is expected to handle 230 V continuously, and a 3
kV device is capable of 1100 V long-term, though manufacturers
may not always certify to those levels (refer to actual vendor data
for specifics). Usually, the higher voltage transformers are called
high-isolation or reinforced insulation types by the suppliers. Table
72 shows a list of transformers that have been evaluated in isoSPI
links.
Transformer Selection Guide
As shown in Figure 103, a transformer or pair of transformers
isolates the isoSPI signals between two isoSPI ports. The isoSPI
signals have programmable pulse amplitudes up to 1.6 V p-p and
pulse widths of 50 ns and 150 ns. To be able to transmit these
pulses with the necessary fidelity, the system requires that the
transformers have primary inductances above 60 μH and a 1:1
turns ratio. It is also necessary to use a transformer with less
than 2.5 μH of leakage inductance. In terms of pulse shape, the
primary inductance mostly affects the pulse droop of the 50 ns
and 150 ns pulses. If the primary inductance is too low, the pulse
amplitude begins to droop and decay over the pulse period. When
the pulse droop is severe enough, the effective pulse width seen
by the receiver drops substantially, reducing noise margin. Some
droop is acceptable as long as it is a relatively small percentage of
the total pulse amplitude. The leakage inductance primarily affects
the rise and fall times of the pulses. Slower rise and fall times
effectively reduce the pulse width. Pulse width is determined by
analog.com
Rev. 0 | 80 of 89
Data Sheet
ADBMS1818
APPLICATIONS INFORMATION
In most applications, a CMC is also necessary for noise rejection.
Table 73 includes a list of suitable CMCs if the CMC is not already
integrated into the transformer being used.
Figure 107. Interfacing an ADBMS1818 with a μC Using an LTC6820 for Isolated SPI Control
Table 72. Recommended Transformers
Working
Voltage
Cent
er
Width (with
Supplier
Part Number
Temperature Range
(VWORKING
)
VHIPOT/60 sec
Tap
CMC
Height
Length
Leads)
Pins
AEC-Q200
Recommended Dual Transformers
Pulse
Pulse
Pulse
Pulse
Sumida
Sumida
Wurth
Wurth
Wurth
Halo
HX1188FNL
HX0068ANL
–40°C to 85°C
–40°C to 85°C
–40°C to 105°C
–40°C to 125°C
–40°C to 125°C
60 V
(estimate)
1.5 kV rms
1.5 kV rms
4.3 kV dc
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
No
6.0 mm
2.1 mm
3.4 mm
4.9 mm
9 mm
12.7
mm
9.7 mm
9.7 mm
16SMT
16SMT
10SMT
12SMT
12SMT
16SMT
16SMT
12SMT
12SMT
16SMT
No
No
Yes
Yes
No
No
No
No
No
Yes
60 V
(estimate)
12.7
mm
HM2100NL
1000 V
14.7
mm
14.9 mm
14.7 mm
15.1 mm
9.4 mm
HM2112ZNL
1000 V
4.3 kV dc
Yes
Yes
Yes
Yes
Yes
Yes
Yes
14.8
mm
CLP178-C20114
CLP0612-C20115
7490140110
1000 V
(estimate)
3.75 kV rms
3.75 kV rms
4 kV rms
17.5
mm
600 V rms
5.7 mm
12.7
mm
–40°C to 85°C
0°C to 70°C
250 V rms
Yes
No
10.9
mm
24.6
mm
17.0 mm
15.2 mm
15.2 mm
9.5 mm
7490140111
1000 V
(estimate)
4.5 kV rms
4 kV rms
8.4 mm
8.4 mm
6.4 mm
17.1
mm
749014018
0°C to 70°C
250 V rms
Yes
Yes
17.1
mm
TG110-AE050N5LF
–40°C to 85/125°C
60 V
(estimate)
1.5 kV rms
12.7
mm
Recommended Single Transformers
Pulse
PE-68386NL
–40°C to 130°C
60 V
(estimate)
1.5 kV dc
No
No
2.5 mm 6.7 mm
5.7 mm 7.6 mm
8.6 mm
6SMT
No
Pulse
Pulse
Wurth
Halo
HM2101NL
HM2113ZNL
–40°C to 105°C
–40°C to 125°C
–40°C to 105°C
–40°C to 125°C
–40°C to 125°C
–40°C to 105°C
1000 V
1600 V
250 V
4.3 kV dc
4.3 kV dc
3 kV rms
3 kV rms
3 kV rms
5 kV rms
No
Yes
No
Yes
Yes
No
No
No
No
9.3 mm
15.5 mm
9.1 mm
6SMT
6SMT
4SMT
6SMT
6SMT
6TH
Yes
Yes
No
3.5 mm
2.2 mm 4.4 mm
10 mm 9.5 mm
9 mm
750340848
TGR04-6506V6LF
TGR04-A6506NA6NL
TDR04-A550ALLF
300 V
Yes
Yes
Yes
12.1 mm
12.1 mm
16.6 mm
No
Halo
300 V
9.4 mm 8.9 mm
6.4 mm 8.9 mm
Yes
Yes
Halo
1000 V
analog.com
Rev. 0 | 81 of 89
Data Sheet
ADBMS1818
APPLICATIONS INFORMATION
Table 72. Recommended Transformers
Working
Voltage
Cent
er
Width (with
Supplier
Part Number
Temperature Range
(VWORKING
)
VHIPOT/60 sec
Tap
CMC
Height
Length
Leads)
Pins
AEC-Q200
TDK
ALT4532V-201-T001
–40°C to 105°C
60 V
~1 kV
Yes
No
2.9 mm 3.2 mm
4.5 mm
6SMT
Yes
(estimate)
Sumida
CEEH96BNP-
LTC6804/11
–40°C to 125°C
600 V
2.5 kV rms
No
No
7 mm
9.2 mm
9.2 mm
12.0 mm
4SMT
No
Sumida
Sumida
TDK
CEP99NP-LTC6804
ESMIT-4180/A
–40°C to 125°C
–40°C to 105°C
–40°C to 125°C
600 V
2.5 kV rms
3 kV rms
Yes
No
No
No
No
10 mm
12.0 mm
9.1 mm
8SMT
4SMT
8SMT
No
Yes
No
250 V rms
3.5 mm 5.2 mm
VGT10/9EE-204S2P4
250 V
(estimate)
2.8 kV rms
Yes
10.6
mm
10.4
mm
12.7 mm
Table 73. Recommended Common-Mode Chokes
Manufacturer
Part Number
TDK
ACT45B-101-2P
Murata
DLW43SH101XK2
analog.com
Rev. 0 | 82 of 89
Data Sheet
ADBMS1818
APPLICATIONS INFORMATION
connected cell or left open. The unused S pins can simply be left
disconnected.
isoSPI Layout Guidelines
The layout of the isoSPI signal lines also plays a significant role in
maximizing the noise immunity of a data link. The following layout
guidelines are recommended:
Alternatively, to optimize measurement synchronization in applica-
tions with fewer than 18 cells, the unused C pins can be equally
distributed between the top of the third mux (C18), the top of the
second mux (C12) and the top of the first mux (C6) (see Figure
108). If the number of cells being measured is not a multiple
of three, the top mux(es) must have fewer cells connected. The
unused cell inputs must be tied to the other unused inputs on the
same mux and connected to the battery stack through a 100 Ω
resistor. The unused inputs result in a reading of 0.0 V for those
cells.
1. The transformer must be placed as close to the isoSPI cable
connector as possible. The distance must be kept less than 2
cm. The ADBMS1818 must be placed close to but at least 1 cm
to 2 cm away from the transformer to help isolate the IC from
magnetic field coupling.
2. A V– ground plane must not extend under the transformer,
the isoSPI connector, or in between the transformer and the
connector.
3. The isoSPI signal traces must be as direct as possible while
isolated from adjacent circuitry by ground metal or space. No
traces must cross the isoSPI signal lines, unless separated by a
ground plane on an inner layer.
Current Measurement with a Hall-Effect Sensor
The ADBMS1818 auxiliary ADC inputs (GPIO pins) may be used
for any analog signal, including active sensors with 0 V to 5
V analog outputs. For battery current measurements, Hall-effect
sensors provide an isolated, low power solution. Figure 109 shows
schematically a typical Hall-effect sensor that produces two outputs
that proportion to the VCC provided. The sensor in Figure 109 has
two bidirectional outputs centered at half of VCC. CH1 is a 0 A to 50
A low range and CH2 is a 0 A to 200 A high range. The sensor is
powered from a 5 V source and produces analog outputs that are
connected to the GPIO pins or inputs of the mux application shown
in Figure 111. The use of GPIO1 and GPIO2 as the ADC inputs
has the possibility of being digitized within the same conversion
sequence as the cell inputs (using the ADCVAX command), thus
synchronizing cell voltage and cell current measurements.
System Supply Current
The ADBMS1818 has various supply current specifications for the
different states of operation. The average supply current depends
on the control loop in the system. It is necessary to know which
commands are being executed each control loop cycle, and the
duration of the control loop cycle. With this information, it is possible
to determine the percentage of time the ADBMS1818 is in the
measure state versus the low power sleep state. The amount
of isoSPI or SPI communication also affects the average supply
current.
Table 74. Daisy Chain Serial Time Equations
Calculating Serial Throughput
Data Bytes
Command CMD Bytes + Data PEC
Communication
Time
For any given ADBMS1818, the calculation to determine communi-
cation time is simple: it is the number of bits in the transmission
multiplied by the SPI clock period being used. The control protocol
of the ADBMS1818 is uniform. Therefore, almost all commands can
be categorized as a write or read operation. Table 74 can be used
to determine the number of bits in a given ADBMS1818 command.
Type
+ CMD PEC per IC
Total Bits
Read
4
4
4
8
8
0
(4 + (8 × #ICs)) × 8 Total bits × clock
period
Write
(4 + (8 × #ICs)) × 8 Total bits × clock
period
Operation
4 × 8 = 32
32 × clock period
ENHANCED APPLICATIONS
Using the ADBMS1818 with Fewer than 18
Cells
Cells can be connected in a conventional bottom (C1) to top (C18)
sequence with all unused C inputs either shorted to the highest
analog.com
Rev. 0 | 83 of 89
Data Sheet
ADBMS1818
APPLICATIONS INFORMATION
Figure 108. Cell Connection Schemes for 16 Cells and 14 Cells
Figure 109. Interfacing a Typical Hall-Effect Battery Current Sensor to Auxiliary ADC Inputs
analog.com
Rev. 0 | 84 of 89
Data Sheet
ADBMS1818
APPLICATIONS INFORMATION
ments to 16 different signals (Figure 111). The GPIO1 ADC input
is used for measurement and mux control is provided by the I2C
port on GPIO4 and GPIO5. The buffer amplifier is selected for fast
settling and increases the usable throughput rate.
READING EXTERNAL TEMPERATURE
PROBES
Figure 110 shows the typical biasing circuit for a negative tempera-
ture coefficient (NTC) thermistor. The 10 kΩ at 25°C is the most
popular sensor value and the VREF2 output stage is designed to
provide the current required to bias several of these probes. The
biasing resistor is selected to correspond to the NTC value so the
circuit provides 1.5 V at 25°C (VREF2 is 3 V nominal). The overall
circuit response is approximately –1%/°C in the range of typical cell
temperatures, as shown in the chart of Figure 110.
Expanding the Number of Auxiliary
Measurements
The ADBMS1818 has nine GPIO pins that can be used as ADC
inputs. In applications that need to measure more than nine signals,
a mux circuit can be implemented to expand the analog measure-
Figure 110. Typical Temperature Probe Circuit and Relative Output
Figure 111. Mux Circuit Supports 16 Additional Analog Measurements
analog.com
Rev. 0 | 85 of 89
Data Sheet
ADBMS1818
TYPICAL APPLICATION
Figure 112. Typical Application Circuit
analog.com
Rev. 0 | 86 of 89
Data Sheet
ADBMS1818
RELATED DEVICES
Table 75. Related Devices
Model
Description
Comments
LTC6811-1/LTC6811-2
4th generation 12-cell battery stack Measures cell voltages for up to 12 series battery cells. Daisy-chain capability allows multiple devices to be
monitor and balancing IC.
connected to measure many battery cells simultaneously via the built-in 1 MHz, 2-wire isoSPI. Includes capability
for passive cell balancing.
LTC6820
isoSPI isolated communications
interface.
Provides an isolated interface for SPI communication up to 100 meters, using a twisted pair. Companion to the
LTC6804, LTC6806, LTC6811, LTC6812, LTC6813, and ADBMS1818.
LTC6812-1
4th generation 15-cell battery stack Measures cell voltages for up to 15 series battery cells. The isoSPI daisy-chain capability allows multiple devices
monitor and balancing IC.
to be interconnected to measure many battery cells simultaneously. The isoSPI bus can operate up to 1 MHz and
can be operated bidirectionally for fault conditions, such as a broken wire or connector. Includes internal passive
cell balancing capability of up to 200 mA.
LTC6813-1
4th generation 18-cell battery stack Automotive/industry application, measures cell voltages for up to 18 series battery cells. The isoSPI daisy-chain
monitor and balancing IC.
capability allows multiple devices to be interconnected to measure many battery cells simultaneously. The isoSPI
bus can operate up to 1 MHz and can be operated bidirectionally for fault conditions, such as a broken wire or
connector. Includes internal passive cell balancing capability of up to 200 mA with a wider temperature range
compared to the ADBMS1818.
analog.com
Rev. 0 | 87 of 89
Data Sheet
ADBMS1818
OUTLINE DIMENSIONS
Figure 113. Package Dimensions
analog.com
Rev. 0 | 88 of 89
Data Sheet
ADBMS1818
OUTLINE DIMENSIONS
Updated: January 15, 2021
ORDERING GUIDE
Package
Option
Model1
Temperature Range
Package Description
Packing Quantity
ADBMS1818ASWZ
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
64-Lead LQFP (10 mm × 10 mm w/ EP)
64-Lead LQFP (10 mm × 10 mm w/ EP)
64-Lead LQFP (10 mm × 10 mm w/ EP)
Tray, 160
Reel, 300
Reel, 1500
05-08-1982
05-08-1982
05-08-1982
ADBMS1818ASWZ-R7
ADBMS1818ASWZ-RL
1
Z = RoHS Compliant Part
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with the #TRMPBF suffix.
analog.com
Rev. 0 | 89 of 89
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