ADBT1002BSWZ [ADI]
4-Channel AFE, Digital Controller, and PWM for Battery Formation and Testing;
| 型号： | ADBT1002BSWZ |
| 厂家： | 
ADI |
| 描述： | 4-Channel AFE, Digital Controller, and PWM for Battery Formation and Testing 电池 |
| 文件： | 总44页 (文件大小：1420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
ADBT1002
4-Channel AFE, Digital Controller, and PWM for Battery Formation and Testing
FEATURES
APPLICATIONS
► Precise measurement of the voltage and current
► 4 PWM control channels up to 14 bits (effective) resolution
► Selectable synchronous and asynchronous rectifier operation
► Programmable dead time compensation
► Programmable switching frequency from 62.5 kHz to 500 kHz
in powers of 2 steps
► Multiphase operation
► Interchip digital current sharing
► Interchip frequency synchronization
► Digital control loop
► Programmable PID loop filters
► Fast dc bus voltage feedforward
► Integrated spectrum analysis per channel
► SPI port control and status interface
► Host interrupt on programmable status changes
► Constant current and constant voltage operating modes
► 15-bit setpoint resolution
► Input and output inrush current protection
► External NTC thermistor temperature sensing
► Internal die temperature measurement
► User calibration of input voltages and currents
► 0°C to 85°C operation
► Battery formation and testing
► High efficiency battery test systems with recycle capability
► Battery conditioning (charging and discharging) systems
GENERAL DESCRIPTION
The ADBT1002 is a flexible, feature rich digital controller that tar-
gets high volume battery testing and formation manufacturing and
precision battery test instrumentation applications. The ADBT1002
is optimized for minimal component count, maximum flexibility, and
minimum design time. Features include differential remote voltage
sense, current sense, pulse-width modulation (PWM) generation,
frequency synchronization, overvoltage protection (OVP), and cur-
rent sharing. Programmable protection features include overcurrent
protection (OCP), OVP limiting, and external overtemperature pro-
tection (OTP).
Parameters can be programmed over the serial peripheral interface
(SPI), providing extensive programming of the integrated loop filter,
PWM signal timing, and soft start timing. The SPI provides access
to the many monitoring and system test functions. Reliability is
improved through a built-in checksum and programmable protection
circuits.
A comprehensive graphical user interface (GUI) is provided for
simple system and channel configuration and programming of
the safety features. The ADBT1002 is available in a 100-lead
LQFP_EP.
TYPICAL APPLICATION DIAGRAM
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Data Sheet
ADBT1002
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
General Description...............................................1
Typical Application Diagram.................................. 1
Specifications........................................................ 3
Analog Front End and Controller
Supports Precharge Operation.........................15
Sequencer........................................................... 16
Instruction Definition.........................................16
Sequencing Modes...........................................16
Charge and Discharge Instruction Modes........18
Charge and Discharge Instruction Limits......... 18
Slew Rate.........................................................19
Parallel Operation.............................................19
Flags.................................................................19
Global Register Settings...................................20
Channel Static Settings....................................20
Instruction Set Architecture.............................. 20
Sequencer Operation Example........................ 24
Memory Mapped Registers................................. 25
Host SPI Interface Details................................... 37
SPI Overview....................................................37
Communications Protocols...............................37
Applications Information...................................... 39
Calibration........................................................ 39
Diagnostics.......................................................39
Operating Use Cases.......................................39
Outline Dimensions............................................. 44
Ordering Guide.................................................44
Specifications................................................... 3
Absolute Maximum Ratings...................................8
Thermal Resistance........................................... 8
Soldering............................................................ 8
Electrostatic Discharge (ESD) Ratings...............8
ESD Caution.......................................................8
Pin Configuration and Function Descriptions........ 9
Theory of Operation.............................................13
Overview.......................................................... 13
Analog Front End............................................. 14
Digital Controller...............................................14
Host SPI........................................................... 14
Host Interrupt Request..................................... 14
Clocking............................................................14
GPIOx Pins.......................................................14
Auxiliary ADC................................................... 14
Supports Coulombic Efficiency Measurement..14
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Data Sheet
ADBT1002
SPECIFICATIONS
AHVDD = 15 V, AHVSS = −15 V, VDDIO = AVDD = DVDD = 3.3 V, and TA = 0°C to 85°C, unless otherwise noted.
ANALOG FRONT END AND CONTROLLER SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CURRENT SENSE CHANNEL
Gain
40
V/V
Gain Error
VOUT =±2 V
0.2
%
Gain Drift
10
ppm/°C
LSB
LSB/°C
nA
System Input Offset Voltage
System Input Offset Voltage Drift
Input Bias Current
−10
+10
0.235
500
+62.5
RTI
VICM = VREF/2
30
Input Differential Voltage Range
Input Common-Mode Voltage Range
Differential Input Impedance
Common-Mode Input Impedance
Input Resistance
−62.5
mV
AHVSS + 5
AHVDD − 5
V
By design
24
kΩ
By design
246
492
110
kΩ
Both input pins
kΩ
Common-Mode Rejection Ratio (CMRR)
100
120
dB
CMRR Drift
0.05
ppm/°C
kHz
dB
Small Signal −3 dB Bandwidth (Gain = 40)1
Power Supply Rejection Ratio (PSRR)
Slew Rate
TA = 25°C, VOUT = 100 mV p-p
Supply voltage (Vs) = ±5 V to ±18 V
VOUT = ±2 V
600
0.6
V/μs
Readout Data Signal-to-Noise Ratio (SNR)
Update Rate4
MAF2 = 16, FIR3 on
31.25 kHz (OSR = 32)
66
69
72
75
dB
dB
dB
dB
mV
15.625 kHz (OSR = 64)
7.8125 kHz (OSR = 128)
3.90625 kHz (OSR = 256)
Full-Scale Input Range
−60
−10
+60
VOLTAGE SENSE AND CAPACITOR VOLTAGE
SENSE CHANNEL
Gain
0.5
V/V
%
Gain Error
VOUT = ±2 V
0.2
Gain Drift
10
ppm/°C
LSB
LSB/°C
V
Input Offset Voltage
Offset Voltage Drift
Input Common-Mode Voltage Range
Differential Input Impedance
Common-Mode Input Impedance
Input Resistance
+10
0.235
AHVDD − 5
AHVSS + 5
0.85
By design
1
MΩ
kΩ
By design
375
750
375
200
Noninverting pin
Inverting pin
kΩ
kΩ
Small Signal −3 dB Bandwidth (G = 0.5)5
TA = 25°C, VOUT = 100 mV p-p
kHz
CMRR
BVx_x
CVS_x
80
78
90
90
dB
dB
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Data Sheet
ADBT1002
SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CMRR Drift
BVx_x
0.235
3
ppm/°C
ppm/°C
dB
CVS_x
PSRR
100
120
0.15
30
Slew Rate
V/μs
Power Dissipation
mW
Readout Data SNR
Update Rate
MAF = 16, FIR on
31.25 kHz (OSR = 32)
15.625 kHz (OSR = 64)
7.8125 kHz (OSR = 128)
3.90625 kHz (OSR = 256)
Full-Scale Input Range
BATTERY CURRENT AND VOLTAGE ADCS
SNR
79
80
81
81
dB
dB
dB
dB
V
−4.8
+4.8
VREF = 2.5 V
1 kHz sine wave at 80% full scale
70
70
12
dB
Signal-to-Noise-and-Distortion (SINAD) Ratio
Resolution
dB
Bits
Differential Nonlinearity (DNL)6
Integral Nonlinearity (INL)
Sampling Rate
−1
−3
+1
+3
LSB
Internal voltage reference
LSB
1
MHz/Channel
VOLTAGE REFERENCE (INTERNAL)
Voltage Range
2.495
62.5
2.500
2.505
11
V
Temperature Coefficient
RMS Noise
7
7
ppm/°C
μV rms
REFCAP = 1 μF
PULSE-WIDTH MODULATION (PWM)
Resolution
External CLK = 16 MHz
14
Bits
kHz
ns
Switching Frequency
Programmable Dead Time
fSW
500
Minimum
Maximum
0
992.2
7.8125
0
ns
Dead Time Resolution7
ns
Delay from External SYNC (Programmable)
Minimum8
µs
Maximum at fSW
62.5 kHz9
=
16
µs
Delay Resolution
7.8125
ns
Effective Phase Shift Resolution
fSW = 62.5 kHz
0.176
0.352
0.703
1.406
Degrees
Degrees
Degrees
Degrees
fSW = 125 kHz
fSW = 250 kHz
fSW = 500 kHz
CHANNEL AC PERFORMANCE
Loop Bandwidth (Cross over Frequency)
10
2
50
kHz
μs
Constant Current to Constant Voltage Transition
Time
fSW = 500 kHz
fSW = 62.5 kHz
16
μs
Channel to Channel Isolation
Current and Voltage Readout Rate10
100
dB
Minimum OSR11
Maximum OSR
31,250
15.26
16
Samples/sec
Samples/sec
Bits
Output Data Resolution
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Data Sheet
ADBT1002
SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
AUXILIARY ADC
Resolution (Effective)
Sampling Rate
12
Bits
DC bus monitor disabled
DC bus monitor enabled
100,000
50,000
Samples/sec
Samples/sec
Input Voltage Range
Reference Voltage
0.1
−1
2.4
+1
V
Unity-Gain Offset
LSB
LSB/°C
μA
Unity-Gain Offset Drift
Current Excitation (4-Bit Programmable)
0.02
Minimum
Maximum
0
750
50
μA
Resolution
μA
LOGIC INPUTS (SPI_CS, SPI_SCK, SPI_SDIO,
SPI_SDO, FAULT_x, GPIOx, AND HW_IRQ)
Hysteresis = 600 mV
Input Voltage High (VIH
)
VDDIO × 0.8
−1
V
Input Voltage Low (VIL)
VDDIO × 0.2
V
Input Current High (IIH
)
VIN = VDDIO
VIN = DVSS
μA
μA
μA
pF
Input Current Low (IIL)
1
Input Pull-Down Current (HW_IRQ Only)
Input Capacitance
15
4
115
LOGIC OPEN-DRAIN OUTPUTS (SPI_SDIO,
SPI_SDO, AND HW_IRQ)
1 mA load
1 mA load
Output Low Voltage (VOL
)
0.4
V
Output High Leakage Current (IOH
LOGIC OUTPUTS (GPIO)
)
±0.1
±1.0
μA
Output Low Voltage (VOL
)
0.4
V
Output High Leakage Current (IOH
)
±0.1
3
±1.0
μA
V
Output High Voltage (VOH
)
VDDIO = 3.0 V
VDDIO = 3.3 V
VDDIO = 3.6 V
Default settings
3.3
3.6
V
V
Slew Rate12
Falling Edge
Rising Edge
5.2
4
ns
ns
Internal Oscillator Frequency
External Oscillator Frequency
Power Supplies
16
16
MHz
MHz
AHVDD
5.3
30.7
4.2
−5.3
6
V
Quiescent Current
AHVSS
Active and standby
Active and standby
3
4
mA
V
−26
mA
V
High Voltage Supply Range (AHVDD to AHVSS)
AVDD
10.6
3
36
3.3
40
3.6
0
3.6
47
V
Active
mA
mA
V
Standby
4.5
AVSS
VDDIO
3.3
2
V
Active and standby
6
μA
V
VDDDRV
3.3
4.6
26
Active
4.8
30
mA
μA
Standby
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Data Sheet
ADBT1002
SPECIFICATIONS
Table 1.
Parameter
DVDD
Test Conditions/Comments
Min
Typ
Max
Unit
3.3
21
V
Active
22
mA
mA
Standby
4.8
5.2
Power Dissipation
AHVDD
AHVDD = 12 V,
active and standby
50.4
63.6
mW
mW
AHVSS
AHVSS = −12 V,
active and standby
VDDIO
AVDD
Active and standby
Active
19.8
155
14.9
72.6
17.2
15.8
99
μW
mW
mW
mW
mW
mW
μW
Standby
Active
DVDD
Standby
Active
VDDDRV
Standby
PWM DRIVE LOGIC
DLx and DHx Drive Voltage13
VOH
PWM_DRV = 0
0 mA load
3
3.29
2.8
17
3.3
2.9
25
1
V
15 mA load
2.6
V
VOL
0 mA load
mV
V
15 mA load
0.6
10
0.8
23
DLx and DHx Sink Resistance
DLx and DHx Source Resistance
PWM_DRV = 0
PWM_DRV = 15
PWM_DRV = 0
PWM_DRV = 15
40
5
Ω
1.8
30
2.6
41
Ω
55
5.1
Ω
2.2
3.2
1
Ω
Internal Pull-Down Resistance
Drive Capacitive Load
MΩ
pF
10
100
1
Bandwidth is analog only. The readout data bandwidth is limited by the selected over sampling rate (OSR).
The moving average filter (MAF) is a 3-bit field in the MAF_CFG register (one per channel). The default value is 8.
The finite impulse response (FIR) filter in the readout filter is not bypassed (default).
The readout filter update rate is selected in a 5-bit field in the DSP_READOUT_FILT_CFG register.
The bandwidth is analog only. The readout data bandwidth is limited by the selected OSR.
Guaranteed by design.
2
3
4
5
6
7
8
9
For sync mode only.
CHANNEL_A_PHASE = 0x000 in the PMU_CHANNEL CFG1 register.
The 11-bit CHANNEL_A_PHASE in the PMU_CHANNEL_CFG1 register = 0x07FF and is the same for other channels.
10The readout update rate is set in a 5-bit field in the DSP_READOUT_FILT_CFG register. There is one per channel.
11Minimum OSR is based on the maximum readout rate of the current and voltage data for all four channels.
12The output pins (SPI_SDIO, SPI_SDO, GPIOx, EXTCLKIO, and HW_IRQ) have xxx_PAD_CFG registers with a 3-bit xxx_SLEW bitfield. The default is 0x7, which is the
fastest slew rate.
13PWM_DRV is a 4-bit field in the PWM_CFG1 channel register.
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Data Sheet
ADBT1002
SPECIFICATIONS
Table 2. SPI Bus Timing
Parameter
Symbol
Min
Typ
Max
Unit
TIMING REQUIREMENTS
Set-Up SPI_CS to SPI_CLK Edge
Minimum SPI_CLK Low Pulse Width
Minimum SPI_CLK High Pulse Width
Minimum SPI_CLK Period
tS
4
ns
ns
ns
ns
ns
ns
ns
tLO
tHI
31.25
31.25
62.5
4
tCLK
tDS
tDH
tH
Data Input Setup Time Before SPI_CLK Edge
Data Input Hold Time After SPI_CLK Edge
Hold SCLK to SPI_CS Deactivate
SWITCHING CHARACTERISTICS
Data Output Valid After SPI_CLK Edge
SPI_CS to SPI_SDIO/SPI_SDO High-Z
4
4
tACCESS
tZ
4
4
ns
ns
Figure 2. 3-Wire SPI Bus Timing Diagram
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Data Sheet
ADBT1002
ABSOLUTE MAXIMUM RATINGS
Table 3.
Table 4. Thermal Resistance
Package Type
Parameter
Rating
θJA
θJC
Unit
°C/W
Analog High Voltage Supply (Continuous),
AHVDD − AHVSS
50 V
SW-100-2
27.8
3.9
SOLDERING
AHVDD − AVSS
AVSS − AHVSS
50 V
30 V
It is important to follow the correct guidelines when laying out the
PCB footprint for the ADBT1002 and when soldering the device
onto the PCB. For detailed information about these guidelines, see
the EE-352 Engineer-to-Engineer Note.
Input Pin Voltages
(ISP_x, ISN_x, BVP_x, BVN_x, and CVS_x)
−0.3 V + AHVSS to AHVDD +
0.3 V
Digital Pins (Relative to DVSS)
DVSS and AVSS
−0.3 V to DVDD + 0.3 V
−0.3 V to +0.3 V
ELECTROSTATIC DISCHARGE (ESD) RATINGS
DVDD, AVDD, and VDDDRV
−0.3 V to DVDD + 0.3 V
SPI_SCK, SPI_CS, SPI_SDIO, and SPI_SDO −0.3 V to DVDD + 0.3 V
The following ESD information is provided for handling of ESD-sen-
sitive devices in an ESD protected area only.
REFIO
−0.3 V to DVDD + 0.3 V
Temperature
Operating Range
Storage Range
Junction
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.
0°C to +85°C
−65°C to +150°C
125°C
ESD Ratings for ADBT1002
Peak Solder Reflow
RoHS-Compliant Assemblies
(20 sec to 40 sec)
260°C
Table 5. ADBT1002, 100-Lead LQFP_EP
ESD Model
Withstand Threshold
Class
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.
HBM
CDM
1.5 kV
750 V
1C
1B
ESD CAUTION
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to PCB
thermal design is required.
θJA is the natural convection junction-to-ambient thermal resistance
measured in a one cubic foot sealed enclosure. θJC is the junction-
to-case thermal resistance.
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Data Sheet
ADBT1002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
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Rev. 0 | 9 of 44
Data Sheet
ADBT1002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
NC
No Connect.
2
NC
No Connect.
3
CVS_A
BVN_A
BVP_A
ISN_A
ISP_A
ISP_B
ISN_B
BVP_B
BVN_B
CVS_B
AHVDD
AHVSS
CVS_C
BVN_C
BVP_C
ISN_C
ISP_C
ISP_D
ISN_D
BVP_D
BVN_D
CVS_D
NC
Channel A Capacitor Voltage Sense Input.
Channel A Voltage Sense Negative Input.
Channel A Voltage Sense Positive Input.
Channel A Current Sense Negative Input.
Channel A Current Sense Positive Input.
Channel B Current Sense Positive Input.
Channel B Current Sense Negative Input.
Channel B Voltage Sense Positive Input.
Channel B Voltage Sense Negative Input.
Channel B Capacitor Voltage Sense Input.
AFE Positive Supply.
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
AFE Negative Supply. Ensure AVDD is applied before applying AHVSS.
Channel C Capacitor Voltage Sense Input.
Channel C Voltage Sense Negative Input.
Channel C Voltage Sense Positive Input.
Channel C Current Sense Negative Input.
Channel C Current Sense Positive Input.
Channel D Current Sense Positive Input.
Channel D Current Sense Negative Input.
Channel D Voltage Sense Positive Input.
Channel D Voltage Sense Negative Input.
Channel D Capacitor Voltage Sense Input.
No Connect.
NC
No Connect.
NC
No Connect.
NC
No Connect.
DH_D
DL_D
PWM Drive High, Channel D.
PWM Drive Low, Channel D.
VDDDRV
DH_C
DL_C
PWM Driver Supply.
PWM Drive High, Channel C
PWM Drive Low, Channel C.
DH_B
DL_B
PWM Drive High, Channel B.
PWM Drive Low, Channel B.
VDDDRV
DH_A
DL_A
PWM Driver Supply.
PWM Drive High, Channel A.
PWM Drive Low, Channel A.
DVDD_CAP
DVDD
NC
Digital Supply Source Capacitor. Connect a 10 μF decoupling capacitor from DVDD_CAP to DVSS.
Digital Supply Source, 3.3 V Typical.
No Connect.
AVDD
AVSS
Analog Supply Source, 3.3 V Typical. Ensure AVDD is applied before applying AHVSS.
Analog Supply Return.
EXTCLKIO
DVDD_CAP
DVSS
NC
External Oscillator Input and Clock Output.
Digital Supply Source Capacitor. Connect a 10 μF decoupling capacitor from DVDD_CAP to DVSS.
Digital Supply Return.
No Connect.
XTALP
XTALN
External Crystal High-Side Excitation Pin.
External Crystal Low-Side Excitation Pin.
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Data Sheet
ADBT1002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
AVSS
Analog Supply Return.
NC
No Connect.
AIN_COM
AIN0
Analog Input, ADC Common.
Analog Input, ADC Channel 0.
AIN1
Analog Input, ADC Channel 1.
AIN2
Analog Input, ADC Channel 2.
AIN3
Analog Input, ADC Channel 3.
AIN4
Analog Input, ADC Channel 4.
AIN5
Analog Input, ADC Channel 5.
AIN6
Analog Input, ADC Channel 6.
AIN7
Analog Input, ADC Channel 7.
AVSS
Analog Power Return.
REFCAP
REFGND
REFIOGND
REFIO
AVDD
Internal Reference Capacitor.
Internal Reference Ground.
Ground for Reference Input and Output.
Reference Input and Output. Connect a 10 μF from REFIO to AVSS.
Analog Power Supply. Ensure AVDD is applied before applying AHVSS.
Analog Power Return.
AVSS
FAULT_D
FAULT_C
FAULT_B
FAULT_A
RESET
GPIO0
GPIO1
VDDIO
VDDIO
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
AVDD_CAP
AVSS
Fault Detect Input, PWM Channel D Shutdown. Active low.
Fault Detect Input, PWM Channel C Shutdown. Active low.
Fault Detect Input, PWM Channel B Shutdown. Active low.
Fault Detect Input, PWM Channel A Shutdown. Active low.
Chip Reset. Active low.
General-Purpose Digital Input and Output 0.
General-Purpose Digital Input and Output 1.
Input and Output Supply.
Input and Output Supply.
General-Purpose Digital Input and Output 2.
General-Purpose Digital Input and Output 3.
General-Purpose Digital Input and Output 4.
General-Purpose Digital Input and Output 5.
General-Purpose Digital Input and Output 6.
General-Purpose Digital Input and Output 7.
General-Purpose Digital Input and Output 8.
General-Purpose Digital Input and Output 9.
General-Purpose Digital Input and Output 10.
Analog Power Return Capacitor. Connect a 10 μF decoupling capacitor from AVDD_CAP to AVSS.
Analog Power Return.
AVDD
Analog Power Supply. Ensure AVDD is applied before applying AHVSS.
Digital Input and Output Supply.
VDDIO
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
HW_IRQ
SPI_SDO
SPI_SDIO
SPI_SCK
General-Purpose Digital Input and Output 11.
General-Purpose Digital Input and Output 12.
General-Purpose Digital Input and Output 13.
General-Purpose Digital Input and Output 14.
General-Purpose Digital Input and Output 15.
Host Interrupt Request. Active low.
Host SPI Master Input, Slave Output (MISO).
Host SPI Master Output, Slave Input (MOSI) or Bidirectional.
Host SPI Clock.
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Data Sheet
ADBT1002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
99
SPI_CS
VDDIO
DVSS
Host SPI Select. Active low.
100
EPAD
Input and Output Supply.
Exposed Pad. DVSS for DVDD, VDDIO, and VDDDRV.
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Data Sheet
THEORY OF OPERATION
OVERVIEW
ADBT1002
a precision analog front end (AFE), measuring both battery current
and voltage using a high accuracy ADC, a user programmable
digital compensator, and a precision PWM. Additionally, there are
8 auxiliary ADC channels and 16 GPIOx pins.
The ADBT1002 is a highly integrated digital controller that provides
four channels of charge and discharge control with a focus on bat-
tery formation and test applications. Each channel is composed of
Figure 4. Functional Block Diagram
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Data Sheet
ADBT1002
THEORY OF OPERATION
Additionally, the GPIOx pins can be configured to provide interde-
vice digital current sharing communications when using multiple
ADBT1002 devices in parallel.
ANALOG FRONT END
Each channel has a precision current sense differential amplifier
with a fixed gain of 40 and a precision voltage sense differential
amplifier with a fixed gain of 0.5. A pair of simultaneous sampling
ADCs converts the conditioned current and voltage signals to 12-bit
digital representations before transferring the signals to the digital
controller.
The GPIO_PAD_CFG register is used to configure the GPIOx pin
parameters including slew rate, hysteresis, and drive strength. The
default bitfields, GPIO_SLEW, GPIO_HYST, and GPIO_DRV, have
default settings of 5 ns, 600 mV, and 10 Ω, respectively. These
default values are typically acceptable for most applications.
DIGITAL CONTROLLER
The GPIOx pins can be individually configured as inputs or outputs
by using the 16-bit GPIO_IEN_CFG and GPIO_OEN_CFG regis-
ters, respectively. Bits[15:0] in each register corresponds to GPIO0
through GPIO15.
A finite state machine (FSM)-based proportional integral derivative
(PID) controller provides digital loop control. The controller has
user-programmable filter coefficients for control loop compensation.
Current and voltage setpoints are register based and are configured
by the user over a host SPI. Separate current and voltage control
loops support constant current and constant voltage operation
modes. The controller output is used to command the duty cycle of
an 14-bit digital PWM. Operation of the controller is discussed in
the Sequencer Operation Example section.
When configured as standard GPIOx pins, there are five 16-bit
registers that can interact with these pins. In each case, Bit 0
corresponds to GPIO0, and Bit 15 corresponds to GPIO15. The
GPIO_READ register can be read to see the state of each GPIOx
pin, and the GPIO_WRITE register can be written to set the output
pins as 1 or 0. The GPIO_SET, GPIO_CLEAR, and GPIO_TOG-
GLE registers set, clear, or toggle, respectively, the GPIOx pins that
are set as standard GPIOx pin outputs.
HOST SPI
Control is provided by an external host through a 3-wire or a 4-wire
SPI. Use the SPI_CS, SPI_SCK, and SPI_SDIO pins for the 3-wire
SPI and use the SPI_CS, SPI_SCK, SPI_SDIO, and SPI_SDO
pins for the 4-wire SPI. This interface is used to configure the
controller through the memory mapped registers. These registers
are introduced in Table 11.
In addition to basic user-controlled GPIO operations, the GPIOx
pins can be configured for specific operation modes. This configura-
tion is done through the GPIO_MODE_CFG0 (for GPIO0 through
GPIO7 pins) and the GPIO_MODE_CFG1 (for GPIO8 through
GPIO15 pins) registers. All GPIOx pins can be configured as either
standard GPIO input and output functions or can be controlled
by the sequencer. The latter is used to control a battery isolation
switch that is used as part of the precharge operation. Additional
options for GPIO0 through GPIO7 are unique functions used for
interdevice communications when multiple devices are used in
parallel.
HOST INTERRUPT REQUEST
Use the HW_IRQ signal, HW_IRQ, to provide interrupt requests
to the host. Use the SPI port accessible set of registers to select
which internal events generate host interrupt requests. Event op-
tions include system errors, channel data ready, channel voltage
and current over limit detection, channel operation complete, and
auxiliary ADC high and low threshold detection.
When a GPIOx pin is controlled by the sequencer in a particular
channel, there is also a channel GPIO_CFG register where the
4 LSBs are used to select which GPIOx pin is controlled by the
sequencer of the channel.
CLOCKING
The ADBT1002 derives all internal clocking from either an internal
oscillator, an external 16 MHz crystal, or an external 16 MHz
oscillator. Phase interleaving can be configured to help minimize
input ripples as well as output ripples when channels are paralleled
for greater current capacity. The ADBT1002 also has a feature that
allows multiple ADBT1002 devices to be synchronized together,
which enables parallel channel operation in multiples of four.
AUXILIARY ADC
An 8-channel, 12-bit ADC is available for dedicated (for example,
internal temperature) or general-purpose external measurements.
Note that four of the channels have optional current sources for use
with the external thermistors for temperature measurement. The dc
bus voltage can also be sensed on an ADC channel and used in
a feedforward control mechanism to reduce the effect of dc bus
transients. All auxiliary ADC operations are user configurable.
GPIOX PINS
There are 16 GPIOx pins on the ADBT1002. Typical GPIOx pin
usage includes controlling the dc bus and battery isolation switches
or getting the digital inputs from the digital sources. The GPIOx
pins are user-programmable through the following set of memory
mapped registers. The GPIOx pins used for the battery isolation
switches can be assigned in the global registers for sequencer
control. This assigning facilitates the precharge operation at start-
up that prevents reverse current when connecting to the battery.
SUPPORTS COULOMBIC EFFICIENCY
MEASUREMENT
Coulombic efficiency is a ratio of the capacity during discharge to
the capacity during charge. The ADBT1002 supports this efficiency
through the integration of current over time. The integration results
are accessible through a set of registers.
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Data Sheet
ADBT1002
THEORY OF OPERATION
user to precharge the output stage before connecting to the cell,
which is described in additional detail in the Precharge Operation
section.
SUPPORTS PRECHARGE OPERATION
When connecting to a cell before a new formation or test cycle,
there is a possibility of having a large inrush current from the
battery to the discharged output stage. The ADBT1002 allows a
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Data Sheet
ADBT1002
SEQUENCER
limit or a timeout that the ADBT1002 uses to generate a flag that
goes into the ADBT1002 interrupt controller. The user must service
the interrupt, write the next instruction, and set the start bit. The
ADBT1002 continues to execute the last instruction until the host
CPU services the interrupt.
INSTRUCTION DEFINITION
The ADBT1002 works by executing instructions on each of the
four channels. Each instruction manages the control loop. The
ADBT1002 can operate with both constant current and constant
voltage.
The register map inside the channel provides a fixed layout for
the instruction. The repercussion of this layout is that all possible
fields are available independently, whether the instruction uses that
information or not. The host CPU is responsible for writing to all the
required fields for the instruction to execute as expected.
SEQUENCING MODES
Three possible sequencing modes exist to execute instructions
from a user point of view: manual, semiautomatic, and automatic.
Manual Mode
A double buffer mechanism exists to write the instruction. Only
when the start bit is written to the channel is a copy of the instruc-
tion forwarded to the state machine and executed. This technique
allows the next instruction to be written in advance. Access to the
registers regarding the instruction executing is available as a debug
feature.
In manual sequencing mode, the host central processing unit (CPU)
is responsible for feeding instructions to the ADBT1002. The user
writes the full instruction into the next instruction area (that is, the
registers prefixed with SEQ_NEXT_xxx) of the channel register
map. The user writes to the self clearing start bit after, which
initiates the execution of this instruction. The instruction provides a
Figure 5. Manual Sequencing Mode
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Data Sheet
SEQUENCER
ADBT1002
The start bit copies the instruction regardless of what the status
of the previous instruction is. Such an operation clears the internal
register. A readback for the internal flag is then provided through
the register map for debug purposes.
Semiautomatic Mode
In semiautomatic mode, the copy of the next instruction executes
when the following conditions are met:
► The current instruction hits the limits (voltage, current, or time),
which are the same reasons why an interrupt can be raised in
manual mode.
► A new instruction has been completely written in the register
map.
Automatic Mode
In automatic sequencing mode, all instructions must be program-
med into the instruction memory before setting the start bit. The
start bit resets the instruction pointer to the start of the channel
memory. Each instruction provides a limit or a timeout that termi-
nates the current instruction and advances the instruction pointer
to the next instruction. The channel issues a flag to the interrupt
controller when all instructions complete execution. The ADBT1002
inhibits any activity on the DH and DL signals once the instruction
sequence terminates.
To avoid executing the same instruction sequentially, there is a
bitfield that indicates when the next instruction is fully programmed
as follows:
► A flag is set by the user through the self clearing
NEXT_INSTR_READY bit in the register map.
► A flag is cleared whenever the instruction is copied from the
register map.
The instructions stored in the channel memory have variable length
payloads using 16-bit words. A fixed header is a one word length.
The payload depends on the instruction declared in the header. The
instruction pointer advances according to the expected payload. A
GUI is available to help users code instruction memory.
Figure 6. Automatic Sequencing Mode
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Data Sheet
ADBT1002
SEQUENCER
► If the VLIMIT_DELTA (MSB) bit is cleared, the VLIMIT bits,
Bits[14:0], represent an absolute positive voltage.
CHARGE AND DISCHARGE INSTRUCTION
MODES
► If the VLIMIT_DELTA bit is set, the limit is understood as an
increment (charge) or a decrement (discharge) from the first
VMEAS value read during the execution of an instruction.
The main purpose of this bit is to set this limit dynamically
without having to read the ADC value before programming this
instruction. This bit is related to the VSET_DELTA bit
(Register SEQ_VSET).
The ADBT1002 provides two PID control loops per channel, the
current loop and the voltage loop. Only one PID control loop is in
control at any given time. The PID control loop in control is the one
with the smallest error between the filtered ADC sample and the
target setpoint. Note that, VMEAS is the measurement on the
V channel.
► The VLIMIT is reached when the measured voltage is higher or
equal to the VLIMIT threshold with a charge instruction.
There are two independent bits to configure how the control loop
behaves:
► The VLIMIT is reached when the measured voltage is lower or
equal to the VLIMIT threshold with a discharge instruction.
► Constant current, where the I channel is in control, and the loop
target is set to the current setpoint (ISET).
► Constant voltage, where the V channel is in control, and the loop
target is set to the voltage setpoint (VSET).
ILIMIT
The following details the operation of the ILIMIT bits
(Register SEQ_ILIMIT):
There are four possible mode combinations or eight including
whether the loop is charging or discharging the battery.
► The ILIMIT threshold flags the instruction end on a charge or
discharge instruction with the constant voltage mode active.
► The ILIMIT bits, Bits[14:0], always represent the absolute current
magnitude.
► The ILIMIT is reached when the measured current is lower or
equal to the ILIMIT threshold with a charge instruction. A reverse
current while charging triggers the limit.
► The ILIMIT is reached when the measured current is higher
or equal to the negative value of the ILIMIT threshold with a
battery discharge instruction. A reverse current while discharging
triggers the limit.
The VSET bits (15 LSBs in Register SEQ_NEXT_VSET) can refer
to either the absolute value or a delta value based on VMEAS, as
determined by the VSET_DELTA bit (MSB in
Register SEQ_NEXT_VSET). The main purpose of the delta is
to allow the programming of a VSET value at some offset from
the last VMEAS value. The start-up (that is, precharge) procedure
uses the VSET_DELTA bit with zero offset to get to the current
battery voltage value. The precharge operation is discussed in the
Precharge Operation section.
CHARGE AND DISCHARGE INSTRUCTION
LIMITS
TLIMIT
There are three 16-bit programmable fields that represent instruc-
tion limits. VLIMIT is associated with the constant current mode of
operation and can be used to signal the end point of a constant
current charge or discharge. ILIMIT is associated with the constant
voltage mode of operation and is typically used to signal the end
point for a constant voltage charge or discharge operation. TLIMIT
can be used to either set the duration of an instruction or to set an
error overlimit when an instruction should have completed earlier.
The following details the usage of the NEXT_TLIMIT_SCALE and
NEXT_TLIMIT_VAL bitfields (Register SEQ_NEXT_TLIMIT):
► TLIMIT is the target for a timeout trigger event. The trigger is
asserted when the elapsed time is equal or greater than TLIMIT.
► A timeout trigger event can be used for either an error, if an
instruction must terminate through another limit, or for a timed
execution of an instruction (no error).
► The SEQ_NEXT_TLIMIT, Bits[15:0], are encoded as the
following:
► NEXT_TLIMIT_SCALE, Bits[15:14] are the time units, 3 =
minutes, 2 = minutes, 1 = milliseconds, and 0 = microseconds.
VLIMIT
The following details the operation of the VLIMIT bits
(Register SEQ_VLIMIT):
► The VLIMIT threshold flags the instruction end on a charge or
discharge instruction with constant current mode.
► In an instruction with both the constant voltage and constant
current modes, VLIMIT avoids early instruction termination by not
letting any crossing through ILIMIT (Bits[14:0],
Register SEQ_ILIMIT) to end the instruction before VLIMIT is
crossed. In addition, the V channel PID is not allowed to take
control until this threshold is reached.
► NEXT_TLIMIT_VAL, Bits[13:0] are the integer value.
► The time units set the resolution and the maximum time value.
On a scale of minutes, the resolution is minutes, and the
maximum time is 11.3 days. On a scale of microseconds,
the resolution is microseconds, and the maximum time is approx-
imately 16.5 ms.
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Data Sheet
ADBT1002
SEQUENCER
dependent on the interchip SPI communications rate of 8 MHz.
Communications between the master and slave devices take 2 μs
per 16-bit IMEAS transfer.
Zero Value Limit Implications
The following limit values have special meaning:
► TLIMIT_VAL = 0 means that the timeout is disabled, and no flag
is generated.
► ILIMIT = 0, or any low value, means that a constant voltage
operation can take a long time to complete.
► VLIMIT = 0 causes a constant current operation to terminate
immediately.
FLAGS
The flag block generates flags that end up in the interrupt controller
block of the ADBT1002. The user then unmasks individual flags (in
the INT_EN_CH_x registers), as required, to generate interrupts.
Flags are cleared when the channel interrupt status register con-
taining the flag is read.
SLEW RATE
The INSTR_DONE flag is set when an instruction hits the last limit,
or if it was the REST instruction when the timeout is reached. Keep
this flag separate from the SEQ_DONE flag for debug purposes.
When a new instruction loads, the INSTR_DONE flag resets in
automatic mode. The start bit can only reset the INSTR_DONE flag
in manual mode.
The ADBT1002 provides a slew rate function of the programmed
targets that smooths out the transition between instructions. With
this function disabled, a step waveform is seen at the error signal
of the control loop. With this function enabled, the step waveform is
transformed into a ramp waveform.
If the target value slewing function is enabled, the ADBT1002
ramps the target value from its measured value into the program-
med target value as part of the instruction. The register map
provides the slew rate for the ISET and VSET bits. The rate is
described within two fields: code and time. The code units are in
ADC codes, and the time is within the PID and PWM update rate.
If in automatic mode, the SEQ_DONE flag is set when the last
instruction finishes. When in manual mode, this flag is never set,
and the start bit resets the SEQ_DONE flag.
The INSTR_TIMEOUT flag results when the timeout is reached if
the flag was not another limit termination or the HALT instruction.
The VMEAS_OVER_LMT and IMEAS_OVER_LMT flags result
when the input data (ADC raw data for better latency) reaches
user specified VMEAS and IMEAS low and high levels,
specifically VMEAS_OVER_LIMITS_LOW_THLD and VMEAS_
OVER_LIMITS_HIGH_THLD, as well as IMEAS_OVER_LIM-
ITS_LOW_THLD and IMEAS_OVER_LIMITS_HIGH_THLD,
respectively. User can also specify the number of consecutive
overlimit samples for detection.
The starting point for the ramp is the first value measured with the
following limitations:
► In a charge instruction, ISET cannot be a negative value. If there
is a back current, ISET starts from 0, ramping up to the setpoint
target.
► In a discharge instruction, ISET cannot be a positive value. If
there is a positive current, ISET starts from 0, ramping down to
the setpoint target.
The INSTR_USER_IRQ flag is set when the sequencer reads the
next instruction with the NEXT_USER_IRQ bit set in the
channel SEQ_NEXT_INST register and finishes the execution of
that instruction.
► VSET is always positive.
A charge and discharge instruction that uses constant current
ramps ISET. A charge and discharge instruction for constant volt-
age ramps VSET.
The INSTR_ERR flag is set during various events that are not part
of the instruction. An instruction error writes a debug error code in
the channel register map so that it can be read by the host. Codes
include malformed instruction and division by zero.
PARALLEL OPERATION
Multiple channels can work in parallel to increase the working
current. When multiple channels work in parallel, a channel is
declared as the master and transmits the measurement for the
I channel (IMEAS) to the other channels. The master channel works
as described in the Two Parallel—Two Independent Channels Use
Case section and the Four Channels in Parallel Use Case section.
The other channels operate in constant current mode and target the
raw IMEAS from the master channel. Note that the IMEAS value
compensates for gain and offset.
The INSTR_MODE_TRANS flag is set upon detection of a mode
transition, such as a constant current to constant voltage transition.
Table 7. Sequencer Flags
Flag
Description
Instruction Finished, INSTR_DONE
Instruction has ended. If in manual
sequencing mode, the ADBT1002
expects a new instruction.
Sequence Finished, SEQ_DONE
Timeout, INSTR_TIMEOUT
Instruction halt was run or instruction
pointer points outside of the instruction
memory.
Groups of channels working in parallel can span multiple
ADBT1002 chips.
Transmitting of the IMEAS between channels on a single
ADBT1002 chip happens inside a PID cycle. Transmitting of the
IMEAS between channels of different ADBT1002 chips is
If instruction is set to flag timeouts,
TLIMIT was met.
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Data Sheet
ADBT1002
SEQUENCER
Table 7. Sequencer Flags
Manual sequencing mode provides a limited set of instructions.
Flag
Description
Bits marked with the X mean that the contents of those bits are do
not care. It is recommended to write 0s in these bits.
Measurement Current (IMEASUREMENT
Overlimit, IMEAS_OVER_LMT
)
IMEAS is outside of the globally
programmed thresholds.
Bits[1:0] of the header define the instruction, INST_TYPE.
Instructions include rest, stop, charge, or discharge.
Measurement Voltage
(VMEASUREMENTS) Overlimit,
VMEAS_OVER_LMT
VMEAS is outside of the globally
programmed thresholds.
CC and CV are bits in the header that represent a mode of
operation for the charge or the discharge of the battery.
User Interrupt, INSTR_USER_IRQ
The instruction with the
NEXT_USER_IRQ bit was executed.
Instruction Error, INSTR_ERR
Various motives. This flag is a read
instruction error code.
DISABLE_VI_LIMITS disables the use of VLIMIT or ILIMIT for
determining instruction end conditions. This bit also disables flag-
ging any voltage or current measurement overlimits.
Instruction Mode Transition,
INSTR_MODE_TRANS
The instruction transitioned from one
mode to another, such as from constant
current to constant voltage mode in
a constant current to constant voltage
operation.
PWM_AUTO_ASYNC_ENABLE enables or disables the automatic
PWM asynchronous mode transition based on current measure-
ments.
GLOBAL REGISTER SETTINGS
TLIMIT_MODE indicates whether the time limit is a normal end
condition, or if this bit is a timeout error that, if reached, raises a
flag.
The following global register settings list sits outside of the channel
register map, and these settings affect all four channels:
SLEW_EN enables a procedure in the charge or the discharge
where either ISET or VSET targets are ramped.
► PWM and loop update rate, which is common for all changes,
and the rates can be configured for 500 kHz, 250 kHz, 125 kHz,
and 62.5 kHz.
► Configuration of channels for parallel operation.
► Interrupt controller settings.
GPIO_VAL sets the value of the channel associated GPIOx. In a
standard application, this associated GPIOx controls a switch that
connects or disconnects the battery from the voltage regulator. A
static register inside the channel register map determines which
GPIOx that this GPIO_VAL bit controls.
► Auxiliary ADC configuration and readout.
CHANNEL STATIC SETTINGS
LOOP_START, when set, represents the first instruction that is part
of a loop. The hardware stores the address pointer. When set, the
first word in the payload must be the number of iterations of the
loop. The instruction sets the loop counter with this value if the
internal loop counter is 0.
The channel static settings that follow are registers that reside
in each of the channel register maps, but these settings are not
controllable per instruction.
► Slew rate settings (the enable bit is in the instruction)
► Measurement overlimit thresholds (hard limits that automatically
turn-off the channel)
► PWM automatic asynchronous mode transition thresholds
► Digital signal processor (DSP) datapath settings follow:
► Readout filter decimation rate
LOOP_END, when set, represents the last instruction that is part
of the loop. The loop counter decrements. If the new loop counter
value is not 0, the program jumps to the first instruction of the loop.
The V_SEL bit represents the two following options for feeding data
into the V channel:
► Numerically controlled oscillator (NCO)
► Frequency response analysis (FRA) demodulator
► Battery voltage measurement = 1’b0 means that the measure-
ment is taken across the BVP_x and BVN_x pins.
► Capacitor voltage measurement = 1’b1 means that the measure-
ment is taken across the CVS_x and BVN_x pins.
INSTRUCTION SET ARCHITECTURE
The instructions that can be programmed into the channel
sequencer follow. The word size in memory is 16 bits wide. Each
instruction has one word as the header and zero or more words as
the payloads.
PID_COEF_SET represents the different options for the PID
coefficients. It is desirable to reserve one set for the start-up
procedure when the battery is not connected, and another set for
the charge or discharge instructions.
To simplify register diagrams, 16-bit words are drawn into two rows
describing the lower 8 bits first and the higher 8 bits second.
USER_IRQ makes the instruction raise a user-defined interrupt at
instruction completion.
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Data Sheet
ADBT1002
SEQUENCER
Table 8. Instruction Header
Header
7
6
5
4
3
2
1
0
Header LSB Bits
PWM_AUTO_
ASYNC_
DISABLE_VI_
LIMITS
RESERVED
RESERVED
CC
CV
INST_TYPE[1:0]
ENABLE
Header MSB Bits TLIMIT_MODE
USER_IRQ
PID_COEF_SET V_SEL
LOOP_END
LOOP_START
GPIO_VAL
SLEW_EN
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Data Sheet
ADBT1002
SEQUENCER
During a rest instruction, the PID output is held for the duration of
TLIMIT to have it ready for the following instruction. The PWM out-
puts are overridden with a logic low level. GPIO_VAL can be used
to disconnect the battery. The channels can also be used as a data
acquisition system for taking voltage and current measurements
during this instruction.
Halt
Halt is coded with INST_TYPE = 2’b00.
This instruction halts the program thus raising the channel
SEQ_DONE flag in automatic mode. The program pointer is not
advanced. The PWM (DHx/DLx) outputs are overridden with a logic
low level.
The rest instruction payload is shown in Table 9. Note that TLIMIT
is a required parameter. A LOOP_CNT value is needed if
LOOP_START is set. In automatic mode only, LOOP_CNT (8-bit
count) must be included if the LOOP_START bit is set in the in-
struction. A later instruction with the LOOP_END bit set determines
the end of the list of instructions that get repeated in the loop.
There is no payload associated with the halt instruction.
Rest
Rest is coded with INST_TYPE = 2’b01.
Table 9. Rest Instruction Payload
Payload
7
6
5
4
3
2
1
0
Payload 0 LSB Bits
Payload 0 MSB Bits
Payload 1 LSB Bits
Payload 1 MSB Bits
TLIMIT, Bits[7:0]
TLIMIT, Bits[15:8]
LOOP_CNT, Bits[7:0] (Only if LOOP_START is set)
X (Don't Care)
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Data Sheet
ADBT1002
SEQUENCER
The DHx and DLx outputs are active and based on the control loop.
Charge and Discharge Operation
The VLIMIT_DELTA and VSET_DELTA bits tell whether VLIMIT or
VSET are based on the last V channel measurement.
This instruction is the main purpose of the ADBT1002 and controls
the charge or discharge of the battery.
The payload depends on which bitfields are enabled in the header.
Table 10. Charge and Discharge Instruction Payload
Header or Payload
7
6
5
4
3
2
1
0
Header LSBs1
Header MSBs1
Payload 0 LSB Bits
ISET, Bits[7:0] (Only if CC is set)
ISET, Bits[14:8] (Only if CC is set)
VSET, Bits[7:0] (Only if CV is set)
Payload 0 MSB Bits X (Don't Care)
Payload 1 LSB Bits
VSET_
Payload 1 MSB Bits
DELTA
VSET[14:8] (Only if CV is set)
Payload 2 LSB Bits
Reserved
Reserved
Payload 2 MSB Bits
Payload 3 LSB Bits
Reserved
Payload 3 MSB Bits
Reserved
Payload 4 LSB Bits
ILIMIT, Bits[7:0] (Only if CV is set)
ILIMIT, Bits[14:8] (Only if CV is set)
VLIMIT, Bits[7:0] (Only if CC is set)
Payload 4 MSB Bits X (Don't Care)
Payload 5 LSB Bits
VLIMIT_
Payload 5 MSB Bits
DELTA
VLIMIT, Bits[14:8] (Only if CC is set)
Payload 6 LSB Bits
Payload 6 MSB Bits
Payload 7 LSB Bits
Payload 7 MSB Bits
TLIMIT, Bits[7:0]
TLIMIT, Bits[15:8]
LOOP_CNT2, Bits[7:0] (Only if LOOP_START is set)
X (Don't Care)
1
See the Instruction Set Architecture section and Table 8 for additional information on this row.
2
In automatic mode only, LOOP_CNT (8-bit count) must be included if the LOOP_START bit is set in the instruction. A later instruction with the LOOP_END bit set determines
the end of the list of instructions that get repeated in the loop.
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Data Sheet
ADBT1002
SEQUENCER
The charge operation starts at t0. The charge current is 0, and the
battery voltage is an open-circuit voltage at the start. From t0 to t1,
only the constant current loop is in control. t1 is where the battery
voltage exceeds VLIMIT. Without VLIMIT, the charge can stop
prematurely because the initial battery current at start is 0, which
is less than ILIMIT. From t1 to t2, both the constant current and
the constant voltage loops are competing for control. The loop with
the lowest error is in control. At t2, control transitions from constant
current to constant voltage loop. Note that the error between the
battery voltage and VSET is 0. From t2 to t3, the constant voltage
loop is in control, and the charge current decreases. At t3, the
charge current reaches ILIMIT. In manual sequencer mode, an
INSTR_DONE flag generates that can in turn generate an interrupt
request. The host must service the interrupt request and either stop
the instruction or start a new one. Otherwise, in manual mode,
the current instruction keeps executing. In semiautomatic mode,
if another instruction is preloaded, it starts executing when the
current instruction limit is reached. Otherwise, with no preloaded
next instruction, the same operation continues execution as manual
mode. In either case, an INSTR_DONE flag is set that can be used
to generate a host interrupt. In automatic mode, the next instruction
in the sequence executes.
SEQUENCER OPERATION EXAMPLE
To highlight how limits and setpoints interact, a constant current to
constant voltage charge example description follows.
Constant Current to Constant Voltage Charge
Operation
Figure 7 demonstrates the ISET, VSET, ILIMIT, and VLIMIT usage
in a constant current to constant voltage charge operation. ISET
and VSET are the target constant current and constant voltage
values, respectively. ILIMIT is the battery current level that signifies
the end of the constant voltage portion of the charge cycle. VLIMIT
is the minimum battery voltage level before the constant voltage
loop can compete for control with the constant current loop.
Figure 7. Constant Current to Constant Voltage Operation
analog.com
Rev. 0 | 24 of 44
Data Sheet
ADBT1002
MEMORY MAPPED REGISTERS
Table 11. Register Block Summary
The SYSTEM_CTRL block contains a set of global registers. These
include system configuration, auxiliary ADC configuration, auxiliary
ADC data readback, multichannel configuration, and interrupt
management.
Name
Block
Address
SPI_SLV_CTRL
SPI_SLV_CTRL
0x0000
0x1000
0x2800
0x3000
0x3200
0x3400
0x3600
0x3800
0x3A00
0x3C00
0x3E00
SYSTEM_CTRL
ADC_CTRL
MISC_CTRL_DIG
ADC_COMMON_SETTINGS
CHANNEL_REGMAP
CHANNEL_REGMAP
CHANNEL_REGMAP
CHANNEL_REGMAP
SEQ_MEMORY
The ADC_CTRL block contains a few registers used to enable the
auxiliary ADC channels and to enable the current excitation for the
external temperature measurement.
CHANNEL_CTRLA
CHANNEL_CTRLB
CHANNEL_CTRLC
CHANNEL_CTRLD
CHANNEL_MEM0
CHANNEL_MEM1
CHANNEL_MEM2
CHANNEL_MEM3
Each of the four CHANNEL_CTRLx blocks contain the same set of
registers, whose addresses are offset by 0x0200 from channel to
channel. These individual channel blocks configure channel
sequencer operations, diagnostics configuration, and data
readback.
SEQ_MEMORY
SEQ_MEMORY
SEQ_MEMORY
The CHANNEL_MEMx blocks do not contain any registers. Instead,
these blocks each include 128 16-bit locations to store sequencer
configuration parameters when automatic mode operation is
selected.
Table 11 shows the various ADBT1002 register blocks and their
starting address. The SPI_SLV_CTRL block contains a set of regis-
ters used to configure the SPI port and communications protocol.
Table 12. SPI_SLV_CTRL (SPI_SLV_CTRL) Register Summary
Address
Name
Description
Reset
Access
0x0
0x1
0x2
INTERFACE_CONFIG
STREAM_MODE
Interface Configuration
Configure Loop Count
Interface Status
0x06
0x00
0x00
R/W
R/W
R/W
INTERFACE_STATUS
Table 13. SYSTEM_CTRL (MISC_CTRL_DIG) Register Summary
Address
Name
Description
Reset
Access
0x1000
0x1001
RST_CTRL
Software Reset Control Register 0x0000
R/W
R/W
PMU_CLOCK_SEL
Power Management Unit (PMU) 0x0001
Clock Selection Register
0x1002
0x1003
0x1004
0x1005
0x1006
PMU_CHANNEL_CFG0
PMU_CHANNEL_CFG1
PMU_CHANNEL_CFG2
PMU_CHANNEL_CFG3
PMU_CHANNEL_CFG4
Channel Enable Selection
Register
0x0010
R/W
R/W
R/W
R/W
R/W
Phase Adjustment for Channel A 0x0000
PWM Signal Register
Phase Adjustment for Channel B 0x0200
PWM Signal Register
Phase Adjustment for Channel C 0x0400
PWM Signal Register
Phase Adjustment for Channel D 0x0600
PWM Signal Register
0x1010
0x1012
0x1013
0x1014
0x101F
0x1020
RST_STA
Reset Status Register
0x0000
0x0000
0x0000
0x0000
0x00B2
0x0E2A
R/W
R
PMU_CLOCK_STATUS
PMU_OTP_STATUS
PMU_CHANNEL_STATUS
REV_ID_INFO
PMU Clock Status Register
PMU OTP Status Register
PWM Locking Status Register
Revision ID Register
R
R
R
SPI_SLV_PAD_CFG
SPI Slave Pad Configuration
Register
R/W
0x1021
0x1022
FAULT_PAD_CFG
GPIO_PAD_CFG
Fault Pad Configuration Register 0x0002
R/W
R/W
GPIO0 to GPOI1 Pad
Configuration Register
0x0035
0x1023
0x1024
EXTCLKIO_PAD_CFG
HW_IRQ_PAD_CFG
External Input and Output Clock 0x0035
Pad Configuration Register
R/W
R/W
Hardware Interrupt Pad
Configuration Register
0x003D
analog.com
Rev. 0 | 25 of 44
Data Sheet
ADBT1002
MEMORY MAPPED REGISTERS
Table 13. SYSTEM_CTRL (MISC_CTRL_DIG) Register Summary
Address
Name
Description
Reset
Access
0x1025
GPIO_IEN_CFG
GPIO Input Enable
Configuration Register
0x0000
R/W
R/W
R/W
R/W
0x1026
0x1027
0x1028
GPIO_OEN_CFG
GPIO Output Enable
Configuration Register
0x0000
0x0000
0x0000
GPIO_MODE_CFG0
GPIO_MODE_CFG1
GPIO0 to GPIO7 Mode
Configuration Register
GPIO8 to GPIO15 Mode
Configuration Register
0x1029
0x102A
0x102B
0x102C
0x102D
0x1040
GPIO_READ
GPIO Data Read Register
GPIO Data Write Register
GPIO Data Set Register
GPIO Data Clear Register
GPIO Data Toggle Register
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
R
GPIO_WRITE
GPIO_SET
R/W
W
GPIO_CLEAR
GPIO_TOGGLE
AIN0_FILT_CFG0
W
W
Configuration Register for
Filtering Applied to AIN0
R/W
0x1041
0x1042
0x1043
0x1044
0x1045
0x1046
0x1047
0x1048
0x1049
0x104A
0x104B
0x104C
0x104D
0x104E
0x104F
0x1050
0x1051
0x1052
AIN0_FILT_CFG1
AIN0_FILT_CFG2
AIN1_FILT_CFG0
AIN1_FILT_CFG1
AIN1_FILT_CFG2
AIN2_FILT_CFG0
AIN2_FILT_CFG1
AIN2_FILT_CFG2
AIN3_FILT_CFG0
AIN3_FILT_CFG1
AIN3_FILT_CFG2
AIN4_FILT_CFG0
AIN4_FILT_CFG1
AIN4_FILT_CFG2
AIN5_FILT_CFG0
AIN5_FILT_CFG1
AIN5_FILT_CFG2
AIN6_FILT_CFG0
Configuration Register for
Filtering Applied to AIN0
0x0000
0x0010
0x0000
0x0000
0x0010
0x0000
0x0000
0x0010
0x0000
0x0000
0x0010
0x0000
0x0000
0x0010
0x0000
0x0000
0x0010
0x0000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Configuration Register for
Filtering Applied to AIN0
Configuration Register for
Filtering Applied to AIN1
Configuration Register for
Filtering Applied to AIN1
Configuration Register for
Filtering Applied to AIN1
Configuration Register for
Filtering Applied to AIN2
Configuration Register for
Filtering Applied to AIN2
Configuration Register for
Filtering Applied to AIN2
Configuration Register for
Filtering Applied to AIN3.
Configuration Register for
Filtering Applied to AIN3
Configuration Register for
Filtering Applied to AIN3
Configuration Register for
Filtering Applied to AIN4
Configuration Register for
Filtering Applied to AIN4
Configuration Register for
Filtering Applied to AIN4
Configuration Register for
Filtering Applied to AIN5
Configuration Register for
Filtering Applied to AIN5
Configuration Register for
Filtering Applied to AIN5
Configuration Register for
Filtering Applied to AIN6
analog.com
Rev. 0 | 26 of 44
Data Sheet
ADBT1002
MEMORY MAPPED REGISTERS
Table 13. SYSTEM_CTRL (MISC_CTRL_DIG) Register Summary
Address
Name
Description
Reset
Access
0x1053
AIN6_FILT_CFG1
Configuration Register for
Filtering Applied to AIN6
0x0000
R/W
R/W
R/W
R/W
R/W
R/W
0x1054
0x1055
0x1056
0x1057
0x1058
AIN6_FILT_CFG2
AIN7_FILT_CFG0
AIN7_FILT_CFG1
AIN7_FILT_CFG2
TEMP_AFE_FILT_CFG0
Configuration Register for
Filtering Applied to AIN6
0x0010
0x0000
0x0000
0x0010
0x0000
Configuration Register for
Filtering Applied to AIN7
Configuration Register for
Filtering Applied to AIN7
Configuration Register for
Filtering Applied to AIN7
Configuration Register for
Filtering Applied to Temperature
AFE
0x1059
0x105A
0x105B
0x105C
0x105D
TEMP_AFE_FILT_CFG1
TEMP_AFE_FILT_CFG2
TEMP_DSP_FILT_CFG0
TEMP_DSP_FILT_CFG1
TEMP_DSP_FILT_CFG2
Configuration Register for
Filtering Applied to Temperature
AFE
0x0000
0x0010
0x0000
0x0000
0x0010
R/W
R/W
R/W
R/W
R/W
Configuration Register for
Filtering Applied to Temperature
AFE
Configuration Register for
Filtering Applied to Temperature
DSP
Configuration Register for
Filtering Applied to Temperature
DSP
Configuration Register for
Filtering Applied to Temperature
DSP
0x105E
0x105F
0x1060
0x1061
0x1062
DC_BUS_FILT_CFG0
DC_BUS_FILT_CFG1
DC_BUS_FILT_CFG2
DC_BUS_FILT_CFG3
TEMP_INT_CAL_CFG
Configuration Register for
Filtering Applied to DC Bus
0x0000
0x0000
0x0001
0x0000
0x0000
R/W
R/W
R/W
R/W
R/W
Configuration Register for
Filtering Applied to DC Bus
Configuration Register for
Filtering Applied to DC Bus
DC Bus Filter Initial Delay in
Multiples of 32 μs Register
Configuration for Temperature
Gain and Offset Internal
Calibration Register
0x1063
0x1064
0x1065
0x1066
0x106B
TEMP_CAL_0
Temperature Value for
Calibration Point 0 Register
0x0000
0x0000
0x0000
0x0000
0x0000
R/W
R/W
R/W
R/W
R/W
TEMP_CAL_1
Temperature Value for
Calibration Point 1 Register
TEMP_CAL_2
Temperature Value for
Calibration Point 2 Register
TEMP_CAL_3
Temperature Value for
Calibration Point 3 Register
TEMP_CAL_INV_MSB_0
Slope Between Temperature
0 and Temperature 1 MSBs
Register
0x106C
TEMP_CAL_INV_LSB_0
Slope Between Temperature
0 and Temperature 1 LSBs
Register
0x0000
R/W
analog.com
Rev. 0 | 27 of 44
Data Sheet
ADBT1002
MEMORY MAPPED REGISTERS
Table 13. SYSTEM_CTRL (MISC_CTRL_DIG) Register Summary
Address
Name
Description
Reset
Access
0x106D
TEMP_CAL_INV_MSB_1
Slope Between Temperature
1 and Temperature 2 MSBs
Register
0x0000
R/W
R/W
R/W
R/W
R/W
R/W
0x106E
0x106F
0x1070
0x1071
0x1072
TEMP_CAL_INV_LSB_1
TEMP_CAL_INV_MSB_2
TEMP_CAL_INV_LSB_2
TEMP_EXT_CAL_CFG0
TEMP_EXT_CAL_CFG1
Slope Between Temperature
1 and Temperature 2 LSBs
Register
0x0000
0x0000
0x0000
0x0000
0x0000
Slope Between Temperature
2 and Temperature 3 MSBs
Register
Slope Between Temperature
2 and Temperature 3 LSBs
Register
Configuration for Temperature
I Gain External Calibration
Register
Configuration for Temperature
I Gain External Calibration
Register
0x1080
0x1081
0x1082
0x1083
0x1084
0x1085
0x1086
0x1087
0x1088
AIN0_READOUT
AIN1_READOUT
AIN2_READOUT
AIN3_READOUT
AIN4_READOUT
AIN5_READOUT
AIN6_READOUT
AIN7_READOUT
TEMP_AFE_READOUT
Result of the Measure on the
External Pin AIN0 Register
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
R
R
R
R
R
R
R
R
R
Result of the Measure on the
External Pin AIN1 Register
Result of the Measure on the
External Pin AIN2 Register
Result of the Measure on
External Pin AIN3
Result of the Measure on the
External Pin AIN4 Register
Result of the Measure on the
External Pin AIN5 Register
Result of the Measure on the
External Pin AIN6 Register
Result of the Measure on the
External Pin AIN7 Register
Result of the Temperature
Measure of the AFE Domain
Register
0x1089
0x1090
TEMP_DSP_READOUT
DC_BUS_READOUT
Result of the Temperature
Measure of the DSP Domain
Register
0x0000
0x0000
R
R
Result of the DC Bus Filter
Used for Correction in All PIDs
Register
0x1091
0x10A0
0x10A1
0x10A2
DC_BUS_CORR_FACTOR_
READOUT
DC Bus Correction Factor for All 0x8000
Channels Register
R
MC_CTRL
MC_CFG0
MC_CFG1
Multichannel Global Control
Register
0x0000
0x0000
0x0020
R/W
R/W
R/W
Multichannel Mode, Slave
Channels Configuration Register
Multichannel Mode, External
Communications Configuration
Register
analog.com
Rev. 0 | 28 of 44
Data Sheet
ADBT1002
MEMORY MAPPED REGISTERS
Table 13. SYSTEM_CTRL (MISC_CTRL_DIG) Register Summary
Address
Name
Description
Reset
Access
0x10A3
MC_PAD_CFG0
Multichannel Mode, Pad
Configuration Register for Slave
SPI
0x002A
R/W
0x10A4
MC_PAD_CFG1
Multichannel Mode, Pad
Configuration Register for
Master SPI
0x0DDD
R/W
0x10C0
0x10C1
0x10C2
0x10C3
0x10C4
0x10C5
0x10C6
SYSTEM_INT_EN
INT_EN_CH_A
System Interrupt Enable
Register
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel A Interrupt Enable
Register
INT_EN_CH_B
Channel B Interrupt Enable
Register
INT_EN_CH_C
Channel C Interrupt Enable
Register
INT_EN_CH_D
Channel D Interrupt Enable
Register
INT_EN_AUX_ADC0
INT_EN_AUX_ADC1
Auxiliary Measurements
Interrupt Enable Register
Auxiliary Measurements
Interrupt Enable Register
0x10D0
0x10D1
SYSTEM_INT_ST
INT_ST_CH_A
System Interrupt Status Register 0x0000
R/W
R/W
Channel A Interrupt Status
Register
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x10D2
0x10D3
0x10D4
0x10D5
0x10D6
INT_ST_CH_B
Channel B Interrupt Status
Register
R/W
R/W
R/W
R/W
R/W
INT_ST_CH_C
Channel C Interrupt Status
Register
INT_ST_CH_D
Channel D Interrupt Status
Register
INT_ST_AUX_ADC0
INT_ST_AUX_ADC1
Auxiliary Measurements
Interrupt Status Register
Auxiliary Measurements
Interrupt Status Register
Table 14. ADC_CTRL (ADC_COMMON_SETTINGS) Register Summary
Address
Name
Description
Reset
Access
0x2800
AUX_ADC_CFG0
Current Values for External
Thermistor Applied in AIN0 to
AIN3 Pins Register
0x0000
R/W
0x2801
0x2803
AUX_ADC_CFG1
Control for Auxiliary Inputs
and Temperature Sensor Being
Measured Register
0x4000
0x00DA
R/W
R/W
ADC_COMMON_REG
AFE Chopping and Internal
Reference Amplifier Settings
Register
analog.com
Rev. 0 | 29 of 44
Data Sheet
ADBT1002
MEMORY MAPPED REGISTERS
Table 15. CHANNEL_CTRLA (CHANNEL_REGMAP) Register Summary
Address
Name
Description
Reset
Access
0x3000
SEQ_CTRL
Channel Sequencer Control
Register
0x0000
R/W
0x3001
0x3002
0x3003
0x3004
0x3005
SEQ_STATUS
SEQ_MEM_PTR
SEQ_INST
Channel Sequencer Status
Register
0x0000
0x0000
0x0000
0x0000
0x0000
R
Channel Sequencer Memory
Address Pointer Register
R
Channel Sequencer Instruction
Register
R/W
R/W
R/W
SEQ_ISET
Channel Sequencer Current
Setpoint Register
SEQ_VSET
Channel Sequencer Voltage
Setpoint Register
0x3006
0x3007
0x3008
Reserved
Reserved
SEQ_ILIMIT
Reserved
Reserved
0x0000
0x0000
0x0000
R/W
R/W
R/W
Channel Sequencer Current
Limit Register
0x3009
0x300A
0x300B
0x300C
0x300D
SEQ_VLIMIT
Channel Sequencer Voltage
Limit Register
0x0000
0x0000
0x0000
0x0000
0x0000
R/W
R/W
R/W
R/W
R/W
SEQ_TLIMIT
Channel Sequencer Time Limit
Register
SEQ_NEXT_INST
SEQ_NEXT_ISET
SEQ_NEXT_VSET
Channel Sequencer Next
Instruction Register
Channel Sequencer Next
Current Set Point Register
Channel Sequencer Next
Voltage Set Point Register
0x300E
0x300F
0x3010
Reserved
Reserved
Reserved
0x0000
0x0000
0x0000
R/W
R/W
R/W
Reserved
SEQ_NEXT_ILIMIT
Channel Sequencer Current-
Limit Register
0x3011
0x3012
0x3013
0x3014
0x3015
0x3016
0x3017
SEQ_NEXT_VLIMIT
SEQ_NEXT_TLIMIT
SLEW_RATE_CFG
Channel Sequencer Voltage
Limit Register
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel Sequencer Next Time
Limit Register
Slew Rate Configuration for the
Setpoints Register
GPIO_CFG
GPIO Configuration Associated
to the Channel Register
OPEN_LOOP_CFG
OPEN_LOOP_DC_VAL_MSB
OPEN_LOOP_DC_VAL_LSB
Open-Loop Configuration
Register
Open-Loop DC Value (MSB)
Register
Open-Loop DC Value (LSB)
Register
0x3018
0x3040
SLAVE_CFG
Slave Configuration Register
0x0008
0x0000
R/W
R/W
I_PID_KP_SET1_LSB
Current PID Proportional
Coefficient (LSB) Register, Set
to 1
0x3041
I_PID_KP_SET1_MSB
Current PID Proportional
Coefficient (MSB) Register, Set
to 1
0x0010
R/W
analog.com
Rev. 0 | 30 of 44
Data Sheet
ADBT1002
MEMORY MAPPED REGISTERS
Table 15. CHANNEL_CTRLA (CHANNEL_REGMAP) Register Summary
Address
Name
Description
Reset
Access
0x3042
I_PID_KI_SET1_LSB
Current PID Integral Coefficient
(LSB) Register, Set to 1
0x0000
R/W
R/W
R/W
0x3043
0x3044
I_PID_KI_SET1_MSB
I_PID_KD_SET1_LSB
Current PID Integral Coefficient
(MSB) Register, Set to 1
0x0000
0x0000
Current PID Derivative
Coefficient (LSB) Register, Set
to 1
0x3045
0x3046
0x3047
I_PID_KD_SET1_MSB
V_PID_KP_SET1_LSB
V_PID_KP_SET1_MSB
Current PID Derivative
Coefficient (MSB) Register, Set
to 1
0x0000
0x0000
0x0010
R/W
R/W
R/W
Voltage PID Proportional
Coefficient (LSB) Register, Set
to 1
Voltage PID Proportional
Coefficient (MSB) Register, Set
to 1
0x3048
0x3049
0x304A
V_PID_KI_SET1_LSB
V_PID_KI_SET1_MSB
V_PID_KD_SET1_LSB
Voltage PID Integral Coefficient
(LSB) Register, Set to 1
0x0000
0x0000
0x0000
R/W
R/W
R/W
Voltage PID Integral Coefficient
(MSB) Register, Set to 1
Voltage PID Derivative
Coefficient (LSB) Register, Set
to 1
0x304B
0x304C
0x304D
V_PID_KD_SET1_MSB
I_PID_KP_SET2_LSB
I_PID_KP_SET2_MSB
Voltage PID Derivative
Coefficient (MSB) Register, Set
to 1
0x0000
0x0000
0x0010
R/W
R/W
R/W
Current PID Proportional
Coefficient (LSB) Register, Set
to 2
Current PID Proportional
Coefficient (MSB) Register, Set
to 2
0x304E
0x304F
0x3050
I_PID_KI_SET2_LSB
I_PID_KI_SET2_MSB
I_PID_KD_SET2_LSB
Current PID Integral Coefficient
(LSB) Register, Set to 2
0x0000
0x0000
0x0000
R/W
R/W
R/W
Current PID Integral Coefficient
(MSB) Register, Set to 2
Current PID Derivative
Coefficient (LSB) Register, Set
to 2
0x3051
0x3052
0x3053
I_PID_KD_SET2_MSB
V_PID_KP_SET2_LSB
V_PID_KP_SET2_MSB
Current PID Derivative
Coefficient (MSB) Register, Set
to 2
0x0000
0x0000
0x0010
R/W
R/W
R/W
Voltage PID Proportional
Coefficient (LSB) Register, Set
to 2
Voltage PID Proportional
Coefficient (MSB) Register, Set
to 2
0x3054
0x3055
V_PID_KI_SET2_LSB
V_PID_KI_SET2_MSB
Voltage PID Integral Coefficient
(LSB) Register, Set to 2
0x0000
0x0000
R/W
R/W
Voltage PID Integral Coefficient
(MSB) Register, Set to 2
analog.com
Rev. 0 | 31 of 44
Data Sheet
ADBT1002
MEMORY MAPPED REGISTERS
Table 15. CHANNEL_CTRLA (CHANNEL_REGMAP) Register Summary
Address
Name
Description
Reset
Access
0x3056
V_PID_KD_SET2_LSB
Voltage PID Derivative
Coefficient (LSB) Register, Set
to 2
0x0000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x3057
0x3058
0x3059
0x305A
0x305B
0x305C
0x305D
0x305E
0x305F
0x3060
0x3061
0x3062
0x3063
0x3064
0x3065
0x3066
0x3067
V_PID_KD_SET2_MSB
Voltage PID Derivative
Coefficient (MSB) Register, Set
to 2
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
PID_CCCV_KTRANS_SET1
PID_CCCV_KTRANS_SET2
TEMP_EXT_CAL_0
PID Constant Current to
Constant Voltage Transition
Coefficient, Set to 1
PID Constant Current to
Constant Voltage Transition
Coefficient, Set to 2
Temperature Value for the
External Calibration Point 0
Register
TEMP_EXT_CAL_1
Temperature Value for the
External Calibration Point 1
Register
TEMP_EXT_CAL_2
Temperature Value for the
External Calibration Point 2
Register
TEMP_EXT_CAL_3
Temperature Value for the
External Calibration Point 3
Register
TEMP_EXT_CAL_4
Temperature Value for the
External Calibration Point 4
Register
TEMP_EXT_CAL_5
Temperature Value for the
External Calibration Point 5
Register
TEMP_EXT_CAL_INV_MSB_0
TEMP_EXT_CAL_INV_LSB_0
TEMP_EXT_CAL_INV_MSB_1
TEMP_EXT_CAL_INV_LSB_1
TEMP_EXT_CAL_INV_MSB_2
TEMP_EXT_CAL_INV_LSB_2
TEMP_EXT_CAL_INV_MSB_3
TEMP_EXT_CAL_INV_LSB_3
Slope Between the External
Temperature 0 and Temperature
1 MSBs Register
Slope Between the External
Temperature 0 and Temperature
1 LSBs Register
Slope Between the External
Temperature 1 and Temperature
2 MSBs Register
Slope Between the External
Temperature 1 and Temperature
2 LSBs Register
Slope Between the External
Temperature 2 and Temperature
3 MSBs Register
Slope Between the External
Temperature 2 and Temperature
3 LSBs Register
Slope Between the External
Temperature 3 and Temperature
4 MSBs Register
Slope Between the External
Temperature 3 and Temperature
4 LSBs Register
analog.com
Rev. 0 | 32 of 44
Data Sheet
ADBT1002
MEMORY MAPPED REGISTERS
Table 15. CHANNEL_CTRLA (CHANNEL_REGMAP) Register Summary
Address
Name
Description
Reset
Access
0x3068
TEMP_EXT_CAL_INV_MSB_4
Slope Between the External
Temperature 4 and Temperature
5 MSBs Register
0x0000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x3069
0x306A
0x306B
0x306C
0x306D
0x306E
0x306F
0x3070
0x3071
0x3072
0x3073
0x3074
0x3075
0x3076
0x3077
0x3078
0x3079
TEMP_EXT_CAL_INV_LSB_4
I_GAIN_EXT_CAL_T0
I_GAIN_EXT_CAL_T1
I_GAIN_EXT_CAL_T2
I_GAIN_EXT_CAL_T3
I_GAIN_EXT_CAL_T4
I_GAIN_EXT_CAL_T5
V_GAIN_INT_CAL_T0
V_GAIN_INT_CAL_T1
V_GAIN_INT_CAL_T2
V_GAIN_INT_CAL_T3
I_GAIN_INT_CAL_T0
I_GAIN_INT_CAL_T1
I_GAIN_INT_CAL_T2
I_GAIN_INT_CAL_T3
V_OFFSET_INT_CAL_T0
V_OFFSET_INT_CAL_T1
Slope Between the External
Temperature 4 and Temperature
5 LSBs Register
0x0000
0x4000
0x4000
0x4000
0x4000
0x4000
0x4000
Current Gain External
Calibration for Temperature 0,
Signed 2.14 Register
Current Gain External
Calibration for Temperature 1,
Signed 2.14 Register
Current Gain External
Calibration for Temperature 2,
Signed 2.14 Register
Current Gain External
Calibration for Temperature 3,
Signed 2.14 Register
Current Gain External
Calibration for Temperature 4,
Signed 2.14 Register
Current Gain External
Calibration for Temperature 5,
Signed 2.14 Register
Voltage Gain Internal Calibration 0x4000
for Temperature 0, Signed 2.14
Register
Voltage Gain Internal Calibration 0x4000
for Temperature 1, Signed 2.14
Register
Voltage Gain Internal Calibration 0x4000
for Temperature 2, Signed 2.14
Register
Voltage Gain Internal Calibration 0x4000
for Temperature 3, Signed 2.14
Register
Current Gain Internal Calibration 0x4000
for Temperature 0, Signed 2.14
Register
Current Gain Internal Calibration 0x4000
for Temperature 1, Signed 2.14
Register
Current Gain Internal Calibration 0x4000
for Temperature 2, Signed 2.14
Register
Current Gain Internal Calibration 0x4000
for Temperature 3, Signed 2.14
Register
Voltage Offset Internal
Calibration for Temperature 0,
Signed 1.15 Register
0x0000
Voltage Offset Internal
Calibration for Temperature 1,
Signed 1.15 Register
0x0000
analog.com
Rev. 0 | 33 of 44
Data Sheet
ADBT1002
MEMORY MAPPED REGISTERS
Table 15. CHANNEL_CTRLA (CHANNEL_REGMAP) Register Summary
Address
Name
Description
Reset
Access
0x307A
V_OFFSET_INT_CAL_T2
Voltage Offset Internal
Calibration for Temperature 2,
Signed 1.15 Register
0x0000
R/W
R/W
R/W
R/W
R/W
R/W
0x307B
0x307C
0x307D
0x307E
0x307F
V_OFFSET_INT_CAL_T3
I_OFFSET_INT_CAL_T0
I_OFFSET_INT_CAL_T1
I_OFFSET_INT_CAL_T2
I_OFFSET_INT_CAL_T3
Voltage Offset Internal
Calibration for Temperature 3,
Signed 1.15 Register
0x0000
0x0000
0x0000
0x0000
0x0000
Current Offset Internal
Calibration for Temperature 0,
Signed 1.15 Register
Current Offset Internal
Calibration for Temperature 1,
Signed 1.15 Register
Current Offset Internal
Calibration for Temperature 2,
Signed 1.15 Register
Current Offset Internal
Calibration for Temperature 3,
Signed 1.15 Register
0x3080
0x3081
0x3082
0x3083
0x3084
0x3085
0x3086
0x3087
0x3088
0x3089
0x308A
0x308B
0x308C
0x308D
0x308E
0x308F
0x3090
0x3091
DSP_READOUT_FILT_CFG
MAF_CFG
Configuration for the Readout
Filters Register
0x0003
0x0003
0x0002
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Configuration for the Moving
Average Filter Register
SDM_CFG
Configuration for the SDM
Register
DC_BUS_CORRECTION_CFG
PWM_CFG0
DC Bus Correction Configuration 0x0000
Register
Configuration for the PWM 0
Register
0x050A
0x0000
0x0000
0x0000
0x0002
0x8000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0001
PWM_CFG1
Configuration for the PWM 1
Register
PWM_CFG2
Configuration for the PWM 2
Register
PWM_CFG3
Configuration for the PWM 3
Register
NCO_CFG0
Configuration for the NCO 0
Register
NCO_CFG1
Configuration for the NCO 1
Register
NCO_PHASE_INCR_LSB
NCO_PHASE_INCR_MSB
NCO_PHASE_INIT_LSB
NCO_PHASE_INIT_MSB
DEMOD_CFG
NCO Phase Increment LSBs
Register
NCO Phase Increment MSBs
Register
NCO Initial Phase LSBs
Register
NCO Initial Phase MSBs
Register
Configuration for the FRA
Demodulator Register
DEMOD_ACCUM_COUNT_LSB Demodulator Integration Count
LSBs Register
DEMOD_ACCUM_COUNT_
MSB
Demodulator Integration Count
MSBs Register
FAULT_CFG
Fault Configuration Register
analog.com
Rev. 0 | 34 of 44
Data Sheet
ADBT1002
MEMORY MAPPED REGISTERS
Table 15. CHANNEL_CTRLA (CHANNEL_REGMAP) Register Summary
Address
Name
Description
Reset
Access
0x3092
MEAS_OVER_LIMITS_CFG
Overlimits Detection for
the Voltage and Current
Measurement ADC Raw Data
Configuration Register
0x0000
R/W
0x3093
0x3094
0x3095
0x3096
0x3100
VMEAS_OVER_LIMITS_
HIGH_THLD
High Overlimit Threshold for the 0x0000
Voltage Measurement ADC Raw
Data Register
R/W
R/W
R/W
R/W
R
VMEAS_OVER_LIMITS_
LOW_THLD
Low Overlimit Threshold for the
Voltage Measurement ADC Raw
Data Register
0x0000
IMEAS_OVER_LIMITS_
HIGH_THLD
High Overlimit Threshold for the 0x0000
Current Measurement ADC Raw
Data Register
IMEAS_OVER_LIMITS_
LOW_THLD
Low Overlimit Threshold for the
Current Measurement ADC Raw
Data Register
0x0000
DSP_READOUT_DATA_0
Readout Data, MSBs of Voltage 0x0000
Data Register (Whenever there
is a read on this register, the rest
of the readout data registers are
sampled.)
0x3101
0x3102
DSP_READOUT_DATA_1
DSP_READOUT_DATA_2
Readout Data, MSBs of Current 0x0000
Data Register
R
R
Readout Data, LSBs of the
Voltage and Current Data and
Tag Number Register
0x0000
0x3104
COULOMB_COUNT_0
Coulomb Integration Result
for the Ongoing Instruction 0
Register (Whenever there is a
read on this register, the rest
of the COULOMB_COUNT_1 to
COULOMB_COUNT_3 registers
are sampled.)
0x0000
R
0x3105
0x3106
0x3107
0x3108
0x3109
COULOMB_COUNT_1
Coulomb Integration Result
for the Ongoing Instruction 1
Register
0x0000
0x0000
0x0000
0x0000
0x0000
R
R
R
R
R
COULOMB_COUNT_2
Coulomb Integration Result
for the Ongoing Instruction 2
Register
COULOMB_COUNT_3
Coulomb Integration Result
for the Ongoing Instruction 3
Register
COULOMB_COUNT_PREV_0
COULOMB_COUNT_PREV_1
Coulomb Integration Result
for the Previous Instruction 0
Register
Coulomb Integration Result
for the Previous Instruction 1
Register
0x310A
0x310B
COULOMB_COUNT_PREV_2
COULOMB_COUNT_PREV_3
Coulomb Integration Result for
the Previous Instruction.
0x0000
0x0000
R
R
Coulomb Integration Result
for the previous Instruction 3
Register
analog.com
Rev. 0 | 35 of 44
Data Sheet
ADBT1002
MEMORY MAPPED REGISTERS
Table 15. CHANNEL_CTRLA (CHANNEL_REGMAP) Register Summary
Address
Name
Description
Reset
Access
0x310C
DEMOD_XV_I_RESULT_0
FRA PID Output + NCO
Demodulator Current Result 0
Register
0x0000
R
R
R
R
R
R
R
R
0x310D
0x310E
0x310F
0x3110
0x3111
0x3112
0x3113
DEMOD_XV_I_RESULT_1
DEMOD_XV_I_RESULT_2
DEMOD_XV_I_RESULT_3
DEMOD_XV_Q_RESULT_0
DEMOD_XV_Q_RESULT_1
DEMOD_XV_Q_RESULT_2
DEMOD_XV_Q_RESULT_3
FRA PID Output + NCO
Demodulator Current Result 1
Register
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
FRA PID Output + NCO
Demodulator Current Result 2
Register
FRA PID Output + NCO
Demodulator Current Result 3
Register
FRA PID Output + NCO
Demodulator Quadrature Result
0 Register
FRA PID Output + NCO
Demodulator Quadrature Result
1 Register
FRA PID Output + NCO
Demodulator Quadrature Result
2 Register
FRA PID Output + NCO
Demodulator Quadrature Result
3 Register
0x3114
0x3115
0x3116
0x3117
0x3118
0x3119
0x311A
0x311B
DEMOD_YI_I_RESULT_0
DEMOD_YI_I_RESULT_1
DEMOD_YI_I_RESULT_2
DEMOD_YI_I_RESULT_3
DEMOD_YI_Q_RESULT_0
DEMOD_YI_Q_RESULT_1
DEMOD_YI_Q_RESULT_2
DEMOD_YI_Q_RESULT_3
FRA PID Output Demodulator
Current Result 0 Register
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
R
R
R
R
R
R
R
R
FRA PID Output Demodulator
Current Result 1 Register
FRA PID Output Demodulator
Current Result 2 Register
FRA PID Output Demodulator
Current Result 3 Register
FRA PID Output Demodulator
Quadrature Result 0 Register
FRA PID Output Demodulator
Quadrature Result 1 Register
FRA PID Output Demodulator
Quadrature Result 2 Register
FRA PID Output Demodulator
Quadrature Result 3 Register
analog.com
Rev. 0 | 36 of 44
Data Sheet
ADBT1002
HOST SPI INTERFACE DETAILS
Additional SPI port features include cyclic redundancy check (CRC)
and address looping. The latter allows streaming over a limited
range of consecutive register addresses.
SPI OVERVIEW
The host communicates with the ADBT1002 through a SPI port.
The SPI port supports both 3-wire (with a single bidirectional data
signal) and traditional 4-wire interfaces (default). These interfaces
are selectable through configuration of the INTERFACE_CONFIG
register.
COMMUNICATIONS PROTOCOLS
All transfers are done with 16-bit words. The first 16-bit word of
each transaction (instruction phase) consists of a 15-bit register
address and a R/W bit. The MSB R/W bit is 0 for a write and a 1 for
a read.
SPI_SCK functions as a serial shift clock and is generated by the
host. The default clock polarity (CPOL) and clock phase (CPHA)
are both 0. The rising edge of SPI_SCK is used to latch data
from the host while the falling edge latches data to the host. The
maximum clock rate is 16 MHz.
Basic Read Operation
The instruction phase is performed in the first 16-bit word transfer.
The R/W bit, which is the MSB during the instruction phase shown
in Figure 8, is set to 1 for a read operation. The other 15 bits specify
the register address. The next 16-bit transfer from the host specifies
the number of consecutive 16-bit reads to perform. For a single
16-bit register read, this field is set to 0 or 1. Starting on the 33rd
SPI_SCLK, data is read out. If the number of reads is 2 or more,
SPI_CS must be asserted beyond the three basic single word 16-bit
transfers through the total number requested.
SPI_SDIO is a data input pin in 4-wire mode and a bidirectional
data pin in 3-wire mode.
SPI_SDO is the data output only pin used in 4-wire-mode. Note that
MSB first is the default mode, but LSB first can also be configured.
SPI_CS is an active low SPI chip select signal. A low going asser-
tion starts a read or write operation. Data streaming can also be
accommodated with automatic register address increment (default)
or decrement.
Figure 8. Basic 4-Wire Read Operation
analog.com
Rev. 0 | 37 of 44
Data Sheet
ADBT1002
HOST SPI INTERFACE DETAILS
phase. Additional data can be written by keeping SPI_CS asserted
while clocking in additional 16-bit words. The data is transferred to
sequential register addresses.
Basic Write Operation
Timing for basic write operation is shown in Figure 9. The R/W
bit in the instruction phase is 0 for a write operation. The 16-bit
data to be written to immediately follows the 16-bit instruction
Figure 9. Basic 4-Wire Write Operation
analog.com
Rev. 0 | 38 of 44
Data Sheet
ADBT1002
APPLICATIONS INFORMATION
samples, monitor current step changes, determine when the RC
time constant is complete, and estimate the voltage difference.
CALIBRATION
Facilitate System Calibration
DCIR = ΔV/ΔI
The ADBT1002 supports a means to facilitate a system calibration,
which includes registers for each ADC channel to include offset
and gain scaling calibration data. The user can provide external
stimulus, measure the results, and calculate the requisite offset and
gain scaling values over several temperature points. These values
can then be user programmed into the ADC calibration registers.
These values can then be used to compensate for system errors
over a specific temperature range.
During this measurement, the output data rate can be increased to
capture the transient response.
OPERATING USE CASES
4-Channel Independent Use Case
For the 4-channel independent use case, each channel conducts
a separate and independent measurement of the battery voltage
and current, and has independent control of the same. In addition,
each channel has independently programmable voltage and current
setpoints.
DIAGNOSTICS
Support DC Internal Resistance (DCIR)
Measurement
DCIR measurement is supported indirectly via accurate measure-
ment of the battery voltage. The external controller must store data
analog.com
Rev. 0 | 39 of 44
Data Sheet
ADBT1002
APPLICATIONS INFORMATION
Figure 10. 4-Channel Independent Use Case
analog.com
Rev. 0 | 40 of 44
Data Sheet
ADBT1002
APPLICATIONS INFORMATION
and current setpoints. However, with the two parallel channels, the
master channel (Channel A) uses both the voltage and current
setpoints, while the slave parallel channel uses only the current
setpoint. The current setpoint is provided automatically from the
master channel current measurement so that it tracks properly. The
host must program the master channel current setpoint with half of
the total desired current.
Two Parallel—Two Independent Channels Use
Case
This use case has two of the four channels operating in parallel
for increased current capacity, and the other two channels are
configured as independent channels. Each channel conducts sep-
arate and independent measurement of the battery voltage and
current, and has independent control of the same. Each of the two
independent channels have independently programmable voltage
Figure 11. Two Parallel—Two Independent Channels Use Case
analog.com
Rev. 0 | 41 of 44
Data Sheet
ADBT1002
APPLICATIONS INFORMATION
(Channel A) uses both the voltage and current setpoints, while the
slave parallel channels use only the current setpoint. The current
setpoint is provided automatically from the master channel current
measurement so that it tracks properly. The host must program the
master channel current setpoint with ¼ of the total desired current.
Four Channels in Parallel Use Case
This use case has all four channels operating in parallel for
increased current capacity. Each channel conducts separate and
independent measurement of the battery voltage and current, and
has independent control of the same. The master channel
Figure 12. Four Channels in Parallel Use Case
analog.com
Rev. 0 | 42 of 44
Data Sheet
ADBT1002
APPLICATIONS INFORMATION
This results in little to no current flowing upon connection of the
battery to the power stage.
Precharge Operation
When connecting a cell to the power stage, there is a chance
of a large current surge as a charge flows from the cell to the
uncharged output capacitor (C1 in Figure 13). The ADBT1002
supports measurement of both the battery voltage (BVN_x and
BVP_x) and the power stage output capacitor voltage (CVS_x).
These measurements allow users to precharge C1 to the potential
of the battery before closing the isolation switches (Q3 and Q4).
A GPIOx pin can be configured to provide control of the isolation
switches.
Measurement of both the cell and output capacitor voltages is
available via the SPI port and a set of memory mapped registers.
Use the VSET bit to control of the output capacitor voltage.
Figure 13. Precharge Function Diagram
analog.com
Rev. 0 | 43 of 44
Data Sheet
ADBT1002
OUTLINE DIMENSIONS
Figure 14. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP]
14 mm × 14 mm Body
(SW-100-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADBT1002BSWZ
0°C to 85°C
0°C to 85°C
100-Lead Low Profile Quad Flat Package [LQFP]
100-Lead Low Profile Quad Flat Package [LQFP]
SW-100-2
SW-100-2
ADBT1002BSWZ-RL
1
Z = RoHS Compliant Part.
©2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Rev. 0 | 44 of 44
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