ADC912AFP [ADI]
CMOS Microprocessor-Compatible 12-Bit A/D Converter; CMOS微处理器兼容的12位A / D转换器
| 型号： | ADC912AFP |
| 厂家： | 
ADI |
| 描述： | CMOS Microprocessor-Compatible 12-Bit A/D Converter |
| 文件： | 总16页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Microprocessor-Compatible
12-Bit A/D Converter
a
ADC912A
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low Cost
V
A
IN
AGND
REFIN
Low Transition Noise between Code
12-Bit Accurate
؎1/2 LSB Nonlinearity Error over Temperature
No Missing Codes at All Temperatures
10 s Conversion Time
5k⍀
V
DD
12-BIT DAC
V
SS
ADC912A
SUCCESSIVE
APPROXIMATION
REGISTER
Internal or External Clock
8- or 16-Bit Data Bus Compatible
Improved ESD Resistant Design
Latchup Resistant Epi-CMOS Processing
Low 95 mW Power Consumption
Space-Saving 24-Lead 0.3" DIP, or 24-Lead SOIC
12-BIT LATCH
BUSY
CS
4
8
CONTROL
LOGIC
RD
MULTIPLEXER
8
HBEN
APPLICATIONS
CLK OUT
CLK IN
THREE-STATE
OUTPUT
DRIVERS
THREE-STATE
OUTPUT
Data Acquisition Systems
DSP System Front End
Process Control Systems
Portable Instrumentation
CLOCK
OSCILLATOR
DRIVERS
D
D
D
D
DGND D D
3/11 0/8
11
8
7
4
GENERAL DESCRIPTION
not located at a transition voltage, see Figures 1 and 2. NPN
digital output transistors provide excellent bus interface timing,
125 ns access and bus disconnect time which results in faster
data transfer without the need for wait states. An external
1.25 MHz clock provides a 10 µs conversion time.
The ADC912A is a monolithic 12-bit accurate CMOS A/D
converter. It contains a complete successive-approximation A/D
converter built with a high-accuracy D/A converter, a precision
bipolar transistor high-speed comparator, and successive-
approximation logic including three-state bus interface for logic
compatibility. The accuracy of the ADC912A results from the
addition of precision bipolar transistors to Analog Devices’
advanced-oxide isolated silicon-gate CMOS process. Particular
attention was paid to the reduction of transition noise between
adjacent codes achieving a 1/6 LSB uncertainty. The low noise
design produces the same digital output for dc analog inputs
In stand-alone applications an internal clock can be used with
external crystal.
An external negative five-volt reference sets the 0 V to 10 V
input range. Plus 5 V and minus 12 V power supplies result in
95 mW of total power consumption.
256
256 SUCCESSIVE
CONVERSIONS
100
90
WITH
192
128
64
A
= 4.99756V
IN
10
0%
TRANSITION NOISE
0
2045 2046 2047 2048 2049
OUTPUT CODE – Decimal
ANALOG INPUT
Figure 2. Transition Noise Cross Plot
Figure 1. Code Repetition
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
(VDD = +5 V ؎ 5%, VSS = –11.4 V to –15.75 V, VREFIN = –5 V, Analog Input O V to
10 V; External fCLK = 1.25 MHz; –40؇C to +85؇C applies to ADC912A/F unless otherwise noted.)
ADC912A–SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
STATIC ACCURACY
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
VZSE
GFSE
TCGFS
–1
–1
–5
–6
+1
+1
+5
+6
15
LSB
LSB
LSB
LSB
VDD = +5 V, VSS = –12 V
VDD = +5 V, VSS = –12 V
Gain Error
Full-Scale Tempco1
5
ppm/°C
ANALOG INPUT
Input Voltage Range
Input Current Range
VIN
IIN
0
0
10
3
V
mA
POWER SUPPLIES
Positive Supply Current
Negative Supply Current
Power Consumption
IDD
ISS
PDISS
VDD = +5 V2
5
3
70
1/2
1/2
7
5
95
4
4
mA
mA
mW
LSB
LSB
VSS = –12 V2
VDD = +5 V2, VSS = –12 V2
Power Supply Rejection Ratio PSRR+
∆VDD
=
=
5%, AIN = 10 V
5%, AIN = 10 V
PSRR–
∆VSS
DIGITAL INPUTS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
VINH
VINL
IIN
CS, RD, HBEN
CS, RD, HBEN
CS, RD, HBEN
Digital Inputs, CS, RD, HBEN, CLKIN
2.4
4
V
V
µA
pF
0.8
1
10
Digital Input Capacitance
CIN
7
8
DIGITAL OUTPUTS
Logic Input High Voltage
Logic Input Low Voltage
Three-State Output Leakage
Digital Input Capacitance
VOH
VOL
IOZ
ISOURCE = 0.2 mA
ISINK = 1.6 mA
D11–D0/8
V
V
µA
pF
0.4
10
15
1
COUT
D11–D0/8
DYNAMIC PERFORMANCE
Conversion Time
TC
fCLK = 1.25 MHz3
Synchronous Clock
Asynchronous Clock
10.4
11.2
µs
µs
10.4
NOTES
1Guaranteed by design.
2Converter inactive; CS, RD = High, AIN = 10 V.
3See Synchronizing Start Conversion information in Converter Operation Details. Typicals (typ) are median values measured at 25 °C. See Typical Performance
Characteristics for additional information.
Specifications subject to change without notice.
5V
3k⍀
5V
DBN
DBN
C
C
3k⍀
L
L
3k⍀
DBN
DBN
DGND
DGND
10pF
10pF
3k⍀
B. HIGH-Z TOV (t3)
A. HIGH-Z TOV (t3)
OH
OL
DGND
DGND
ANDV
TO V (t6)
OL
ANDV TO V (t6)
OH
OL
OH
A.V TO HIGH-Z
OH
B.V TO HIGH-Z
OL
Figure 3. Load Circuits for Access Time
Figure 4. Load Circuits for Output Float Delay
–2–
REV. B
ADC912A
TIMING CHARACTERISTICS1, 2
(VDD = +5 V ؎ 5%, VSS = –11.4 V to –15.75 V, VREFIN = –5 V, Analog Input 0 V to 10 V;
External fCLK = 1.25 MHz; –40؇C to +85؇C applies to ADC912A/F unless otherwise noted. See Figures 5 to 8.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CS to RD Setup Time
t1
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD to BUSY Propagation Delay
Data Access Time after READ
Read Pulsewidth
CS to RD Hold Time
New Data Valid after BUSY
t23
t33
t4
150
125
CL = 100 pF
CL = 100 pF
65
90
0
t53
t6
–30
60
0
90
Bus Disconnect Time
t7
t8
t9
t10
20
20
20
350
HBEN to RD Setup Time
HBEN to RD Hold Time
Delay between Successive Read Operations
250
NOTES
1Guaranteed by design.
2All input control signals are specified with tR = tF = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3t3, t4, and t6 are measured with the load circuits of Figure 3 and timed for and output to cross 0.8 V or 2.4 V.
4t7 is the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 4.
Specifications subject to change without notice.
CS
TIMING DIAGRAMS
t5
t5
t1
t1
t4
CS
t4
RD
t1
t1
t5
tCONV
t2
t2
t3
tCONV
t7
RD
BUSY
t10
t2
t3
t7
tCONV
BUSY
DATA
NEW DATA
OLD DATA
DATA
DB – DB
DB – DB
11
0
t6
11
0
t3
t7
OLD DATA
NEW DATA
DB – DB
DATA
D
D
D
D
D
D
6
D
D
D
D
D
D
DB – DB
11
10
9
8
7
5
4
3/11 2/10
1/9
0/8
11
0
11
0
OUTPUTS
FIRST READ
(OLD DATA)
DB DB DB DB DB DB DB DB DB DB DB DB
DATA
11
10
9
8
7
6
5
4
3
2
1
0
D
D
D
D
D
D
D
D
D
D
D
D
11
10
9
8
7
6
5
4
3/11 2/10
1/9 0/8
OUTPUTS
SECOND
READ
DB DB DB DB DB DB DB DB DB DB DB DB
DB DB DB DB DB DB DB DB DB DB DB DB
0
11
10
9
8
7
6
5
4
3
2
1
0
READ
11
10
9
8
7
6
5
4
3
2
1
Figure 5. Parallel Read Timing Diagram, Slow-Memory
Mode (HBEN = LOW)
Figure 7. Parallel Read Timing Diagram, ROM Mode
(HBEN = LOW)
HBEN
t8
t8
t8
t9
t9
t9
CS
HBEN
t1
t1
t1
t8
t5
t5
t5
t8
t9
t9
t5
t4
t4
t4
CS
RD
RD
t1
t10
t1
t5
t2
t2
t3
t4
tCONV
t7
BUSY
t10
t2
t3
t7
t7
tCONV
t3
t3
BUSY
t7
OLD DATA
DB – DB
NEW DATA
DB – DB
t3
NEW DATA
DB – DB
t6
DATA
t7
7
0
7
0
11
8
OLD DATA
DATA
DB – DB
7
0
NEW DATA
NEW DATA
DATA
OUTPUTS
D
D
D
D
D
D
D
D
0/8
DB – DB
DB – DB
7
6
5
4
3/11
2/10
1/9
11
8
7
0
DATA
FIRST READ
(OLD DATA)
D
D
D
D
D
D
D
D
0/8
DB
DB
DB
DB
DB
DB
DB
DB
DB
7
6
5
4
3/11
2/10
1/9
7
6
5
4
3
2
1
0
OUTPUTS
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
FIRST READ
LOW
SECOND READ LOW LOW LOW
DB DB DB
7
6
5
4
3
2
1
0
10
9
8
11
DB
LOW
SECOND READ LOW LOW LOW
DB
4
DB
DB
DB
0
10
9
8
THIRD READ
11
7
6
5
3
2
1
Figure 6. Two-Byte Read Timing Diagram, Slow-Memory
Mode
Figure 8. Two-Byte Read Timing Diagram, ROM Mode
REV. B
–3–
ADC912A
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C, unless otherwise noted)
Operating Temperature Range
Extended Industrial: ADC912A/F . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C
Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA
Thermal Resistance θJA
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
V
REFIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
Digital Input Voltage to DGND,
Pins 17, 19–21 . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND,
Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
SOIC-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C
Pins 4–11, 13–16, 18, 22 . . . . . . . . . –0.3 V to VDD + 0.3 V
ORDERING GUIDE
Temperature
Range
INL
(LSB)
Package
Option
Model
Package Description
ADC912AFP
ADC912AFS
–40°C to +85°C
–40°C to +85°C
1
1
24-Lead Narrow-Body Plastic
24-Lead Wide-Body SOIC
N-24
R-24
Table I. Analog Input to Digital Output Code Conversion
Analog Input Voltage Output Code*
0 V to 10 V
–10 V to +10 V
DB11 (MSB) DB0 (LSB)
+FS – 1 LSB
+FS – 1 1/2 LSB
9.9976
9.9964
9.99951
9.9927
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1111φ
Midscale + 1/2 LSB 5.0012
0.0024
0.0000
1 0 0 0 0 0 0 0 0 0 0 φ
1 0 0 0 0 0 0 0 0 0 0 0
Midscale
5.0000
–FS + 1/2 LSB
–FS
0.0012
0.0000
–9.9976
–10.000
0 0 0 0 0 0 0 0 0 0 0 φ
0 0 0 0 0 0 0 0 0 0 0 0
*The symbol”φ” indicates a 0 or 1 with equal probability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADC912A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
ADC912A
(@ V = +5 V, V = –12 V or –15 V, VREF = –5 V, AIN = 0 V to 10 V, and TA = 25؇C, unless otherwise noted.)
WAFER TEST LIMITS
DD
SS
ADC912AG
Limit
Parameter
Symbol
Conditions
Unit
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
VZSE
GFSE
RAIN
VINH
VINL
IIN
1
1
8
LSB max
LSB max
LSB max
LSB max
kΩ min/max
V min
V max
µA max
V min
Guaranteed by Design
Gain Error
8
Analog Input Resistance
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Logic Output High Voltage
Logic Output Low Voltage
Positive Supply Current
Negative Supply Current
4/6
2.4
0.8
1
CS, RD, HBEN
CS, RD, HBEN
CS, RD, HBEN
ISOURCE = 0.2 mA
ISINK = 1.6 mA
VDD = +5 V, CS = RD = VDD, AIN = +10 V
VSS = –12 V, CS = RD = VDD, AIN = +10 V
VOH
VOL
IDD
4
0.4
7
V max
mA max
mA max
ISS
5
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
R
R
10V
+5V
+
+
+
+
C1
C1
C2
R
C1
R
C2
C2
1
2
24
23
22
21
20
19
18
17
16
15
14
13
–5V
–15V
C2
C1
3
NC
4
R
R
5
ADC912A
TOP VIEW
(Not to Scale)
6
7
NC
NC
R
8
9
NC
NC
NC
NC
10
11
12
R = 10⍀
C1 = 0.01F
C2 = 4.7F
NC = NO CONNECT
POWER SUPPLY SEQUENCE:
+5V, –15V, –5V, +10V
Figure 9. Burn-In Circuit
REV. B
–5–
ADC912A
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Description
l
AIN
Analog Input. 0 V to 10 V.
2
VREFIN
AGND
D11 . . . D4
Voltage Reference Input. Requires external –5 V reference.
Analog Ground.
Three-state data outputs become active when CS and RD are brought low.
3
4 . . . 11
13 . . . 16 D3/11 . . . D0/8 Individual pin function is dependent upon High Byte Enable (HBEN) input.
DATA BUS OUTPUT, CS and RD = LOW
Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Mnemonic*
HBEN = LOW
HBEN = HIGH DB11 DB10 DB9 DB8 Low Low Low Low DB11 DB10 DB9 DB8
*D11 . . . D0/8 are the ADC data output pins.
DB11 . . . DB0 are the 12-bit conversion results. DB11 is the MSB.
1
2
DGND
Digital Ground.
17
18
19
CLK IN
Clock Input Pin. An external TTL-compatible clock may be applied to this pin. Alternatively a crystal or
ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT (Pin 18).
Clock Output Pin. An inverted CLK IN signal appears at CLK OUT when an external clock is used. See
CLK IN (Pin 17) description for crystal (resonator).
High Byte Enable Input. Its primary function is to multiplex the 12 bits of conversion data onto the lower
D7 . . . D0/8 outputs (4 MSBs or 8 LSBs). See pin description 4 . . . 11 and 13 . . . 16. Also disables
conversion start when HBEN is high.
CLK OUT
HBEN
20
21
RD
CS
READ Input. This active LOW signal, in conjunction with CS, is used to enable the output data three
state drivers and initiates a conversion if CS and HBEN are low.
Chip Select Input. This active LOW signal, in conjunction with RD, is used to enable the output data
three-state drivers and initiates a conversion if RD and HBEN are low.
22
23
24
BUSY
VSS
VDD
BUSY output indicates converter status. BUSY is LOW during conversion.
Negative Supply, –12 V or –15 V.
Positive Supply, +5 V.
0V TO 10V
ANALOG INPUT
–5V
PIN CONFIGURATION
V
A
24
23
+5V
1
2
DD
IN
V
V
REFERENCE
–12V TO –15V
REFIN
SS
C2
C1
SOURCE
+
STATUS
OUTPUT
BUSY 22
3
AGND
A
IN
V
DD
1
2
24
23
22
21
20
19
18
17
16
15
14
13
D
21
4
CS
11
V
REFIN
V
P
CONTROL
INPUTS
SS
ADC912A
20
D
5
RD
10
AGND
3
BUSY
D
9
HBEN 19
6
D
11
4
CS
C3
D
8
18
17
16
15
14
13
7
CLK OUT
CLK IN
D
5
10
RD
ADC912A
TOP VIEW
(Not to Scale)
XTAL
D
7
8
D
9
6
HBEN
D
9
D
6
0/8
C4
D
D
8
7
CLK OUT
CLK IN
D
5
10
11
12
D
1/9
7
8
D
D
4
2/10
D
D
D
9
6
0/8
D
DGND
3/11
5
10
11
12
D
D
1/9
D
4
2/10
8-BIT OR 16-BIT P DATA BUS
DGND
D
3/11
XTAL = 1MHz, C1 = 0.1 F, C3 = 10 F
C3, C4 = 30pF TO 100pF DEPENDING ON XTAL CHOSEN
Figure 10. Basic Connection Diagram
–6–
REV. B
Typical Performance Characteristics–ADC912A
5
4
6
0.4
0.2
5
3
4
2
3
1
2
0
0
1
–1
–2
–3
–4
–5
0
–0.2
–0.4
–1
–2
–3
–4
0
1024
2048
3072
4096
–75 –50 –25
0
25
50
75 100 125
–75 –50 –25
0
25
50
75 100 125
TEMPERATURE –
C
TEMPERATURE –
C
DIGITAL OUTPUT CODE
TPC 3. Gain Error vs. Temperature
TPC 1. Nonlinearity Error vs. Digital
Output Code
TPC 2. Offset Error vs. Temperature
50
40
30
80
6
V
@ 5.25V
P
= IDD
؋
5 + ISS ؋
12 = 20pF
5
4
DD
DISS
C
OUT
f
= 1/13 f
CONV
CLK IN
I
SINK
T
= 25 C
A
20
10
3
60
40
0
EXT CLK IN
CS, RD = LOGIC HIGH
= 10V
2
A
IN
0
1
CLK = 1MHz XTAL
–10
0
–20
–1
–2
–3
–4
I
SOURCE
–30
–40
–50
I
@V
= –15.75V
SS
SS
0
100k
10k
CLK IN FREQUENCY – Hz
1
2
3
4
5
0
25
50
75 100 125
C
1k
1M
–75 –50 –25
TEMPERATURE –
V
OUTPUTVOLTAGE –Volts
O
TPC 5. Power Dissipation vs. CLK IN
Frequency
TPC 4. Supply Current vs.
Temperature
TPC 6. Digital Output Current vs.
Output Voltage
256
V
= +5V
= –12V
= 25؇C
4
2
DD
256 SUCCESSIVE
CONVERSIONS
WITH
V
T
SS
100
90
A
192
A
= 4.99756V
IN
128
64
0
0
–2
–4
10
0%
TRANSITION NOISE
ANALOG INPUT
2045 2046 2047 2048 2049
20
15
CONVERSIONTIME – s
10
5
0
OUTPUT CODE – Decimal
TPC 8. Transition Noise Cross Plot
TPC 7. Code Repetition
TPC 9. Linearity Error vs. Conversion
Time
–7–
REV. B
ADC912A
SYNCHRONIZING START CONVERSION
CIRCUIT CHARACTERISTICS
Aligning the negative edge of RD with the rising edge of CLK
IN provides synchronization of the internal start conversion
signal to other system devices for sampling applications.
The characteristic curves provide more complete static and
dynamic accuracy information necessary for repetitive sampling
applications often used in DSP processing. One of the impor-
tant characteristic curves provided displays integral nonlinearity
error (INL) versus output code with a typical value of 1/4 LSB.
Another very important characteristic associated with INL is the
transition noise shown in the transition noise cross plot. The
ADC912A offers extremely small, 1/6 LSB, transition noise
which maintains the system signal-to-noise ratio in DSP processing
applications. Code repetition plots show the precision internal
comparator of the ADC912A making the same decision every
time for dc input voltages. Code repetition along with no miss-
ing codes assures proper performance when the ADC912A is
used in servo-control systems.
When the negative edge of RD is aligned with the positive edge
of CLK IN, the conversion will take 10.4 microseconds. The
minimum setup time between the negative edge of CLK IN and
the negative edge of RD is 180 ns. Without synchronization the
conversion time will vary from 12.5 to 13.5 clock cycles. See
Figure 12.
CS, RD
BUSY
180ns MIN
CONVERTER OPERATION DETAILS
CLK IN
The CS, RD, and HBEN digital inputs control the start of
conversion. A high-to-low on both CS and RD initiate a conver-
sion sequence. The HBEN high-byte-enable input must be low
or coincident with the read RD input edge. The start of conver-
sion resets the internal successive approximation register (SAR)
and enables the three-state outputs. See Figure 11. The busy
line is active low during the conversion process.
DB
11
DB
10
DB
DB
0
9
(MSB)
BIT DECISION
MADE
Figure 12. External Clock Input Synchronization
POWER ON INITIALIZATION
0V TO 10V
During system power-up the ADC912A comes up in a random
state. Once the clock is operating or an external clock is applied,
the first valid conversion begins with the application of a high-
to-low transition on both CS and RD. The next 13 negative
clock edges complete the first conversion, producing valid data
at the digital outputs. This is important in battery-operated
systems where power supplies are shut down between measure-
ment times.
5k⍀
A
IN
2.5k⍀
–
+
0 TO
V
REFIN
COMPARATOR
–V
REF
AGND
12
DRIVING THE ANALOG INPUT
SAR
During conversion, the internal DAC output current modulates
the analog input current at the CLK IN frequency of 1.25 MHz.
The analog input to the ADC912A must not change during the
conversion process. This requires an external buffer with low
output impedance at 1.25 MHz. Suitable devices meeting this
requirement include the OP27, OP42, and the SMP-11.
12-BIT LATCH
Figure 11. Simplified Analog Input Circuitry of ADC912A
During conversion, the SAR sequences the internal voltage
output DAC from the most significant bit (MSB) to the least
significant bit (LSB). The analog input connects to the
comparator via a 5 kΩ resistor. The DAC, which has a 2.5 kΩ
output resistance, connects to the same comparator input.
The comparator, performing a zero crossing detection, tests the
addition of successively weighted bits from the DAC output
versus the analog input signal. The MSB decision occurs 200 ns
after the second positive edge of the CLK IN following conver-
sion initiation. The remaining 11-bit trials occur after the next
11 positive CLK IN edges. Once a conversion cycle is started it
cannot be stopped or restarted, without upsetting the remaining
bit decisions. Every conversion cycle must have 13 negative and
positive CLK IN edges. At the end of conversion the compara-
tor input voltage is zero. The SAR contains the 12-bit data
word representing the analog input voltage. The BUSY line
returns to logic high, signaling end of conversion. The SAR
transfers the new data to the 12-bit latch.
CLK
OUT
ADC912A
C1
*
INTERNAL
CLOCK
C2
CLK
IN
1M⍀
*CRYSTAL OR CERAMIC RESONATOR
Figure 13. ADC912A Simplified Internal Clock Circuit
–8–
REV. B
ADC912A
INTERNAL CLOCK OSCILLATOR
4095
4094
Figure 13 shows the ADC912A internal clock circuit. The clock
oscillates at the external crystal or ceramic resonator frequency.
The 1.25 MHz crystal or ceramic resonator connects between
the CLK IN (Pin 17) and the CLK OUT (Pin 18). Capacitance
values (C1, C2) depend on the crystal or ceramic resonator
manufacturer. The crystal vendors should be qualified due to
variations in C1 and C2 values required from vendor to vendor.
Typical values range from 30 pF to 100 pF.
FULL-SCALE
TRANSITION
AT FS – 1.5 LSB
2
1
EXTERNAL CLOCK INPUT
FS-2 FS-1 FS
– ANALOG INPUT IN LSB
2
0 0.5 1
A
A TTL compatible signal connected to CLK IN provides proper
converter clock operation. No connection is necessary to the
CLK OUT pin. The duty cycle of the external clock input can
vary from 45% to 55%. Figure 12 shows the important waveforms.
IN
Figure 15. Ideal ADC912A Input/Output Transfer
Characteristic
OFFSET AND FULL-SCALE ERROR ADJUSTMENT,
UNIPOLAR OPERATION
EXTERNAL REFERENCE
A low output resistance, negative five volt reference is necessary.
The external reference should be able to supply 3 mA of refer-
ence current. A bypass capacitor is necessary on the reference
input lead to minimize system noise as the internal DAC switches.
The reference input to the internal DAC is code dependent requir-
ing anywhere from zero to 3 mA. The reference voltage tolerance
has a direct influence on A/D converter full-scale voltage, and
the maximum input full-scale voltage equals 2 × –VREF. The
ADC912A is designed for ratiometric operation, but operation
using reference voltages between –5.00 V and 0 V will result in
degraded linearity performance. Integral linearity is fully tested and
guaranteed for references of –5 V. Figure 14 provides a good
–5 V reference that does not require precision resistors.
For applications where absolute accuracy is important, offset
and full-scale errors can be adjusted to zero. Figure 16 shows
the extra components required for full-scale error adjustment.
Zero offset is achieved by adjusting the null offset of the op amp
driving AIN.
+12V
3
2
7
V
IN
0V TO 10V
10⍀
6
1
A1
10k⍀
A
IN
5
4
1
ADC912A*
FULL
ZERO
ADJUST
SCALE
ADJUST
–12V
200⍀
+5V TO +15V
3
AGND
20k⍀
0.01F
+
2
INPUT
V
A1: OP27 – LOWEST NOISE (TRIMMER CONNECTS
BETWEEN PINS 1 & 8, WIPER TO 12V)
OP42 – BEST BANDWIDTH
10F//0.01F
100⍀
10k⍀
2
3
6
5
V+
OUT
100⍀
*EXTRA PINS OMITTED FOR CLARITY
–5V
OUTPUT
OP77
REF02
TRIM
GND
V–
Figure 16. Unipolar 0 V to 10 V Operation
Adjust the zero scale first by applying 1.22 mV (equivalent to
0.5 LSB input) to VIN. Adjust the op amp offset control until
the digital output toggles between 0000 0000 0000 and 0000
0000 0001. The next step is adjustment of full scale. Apply
9.9963 V (equivalent to FS – 1.5 LSB) to VIN and adjust R1
until the digital output toggles between 1111 1111 1110 and
1111 1111 1111.
4
–12V TO –15V
TRIM IS OPTIONAL, ONLY NECESSARY
FOR ABSOLUTE ACCURACY CIRCUITS
Figure 14. –5 V Reference
UNIPOLAR ANALOG INPUT OPERATION
Figure 15 shows the ideal input/output characteristic for the 0 V
to 10 V input range of the ADC912A. The designed output
code transitions occur midway between successive integer LSB
values (i.e., 0.5 LSB, 1.5 LSBs, 2.5 LSBs . . . FS – 1.5 LSBs).
The output code is natural binary with 1 LSB = FS/4096 =
(10/4096) V = 2.44 mV. The maximum full-scale input voltage
is (10 × 4095/4096) V = 9.9976 V.
REV. B
–9–
ADC912A
BIPOLAR ANALOG INPUT OPERATION
Calibration of the bipolar analog input circuits (Figures 17 and
18) should begin with zero adjustment first. Apply a +1/2 LSB
analog input to AIN, (see Tables II and III) and adjust RZ until the
successive digital output codes flicker between the following codes:
Bipolar analog input operation is achieved with an external
amplifier providing an analog offset. Figures 17 and 18 show
two circuit topologies that result in different digital-output cod-
ing. In Figure 17, offset binary coding is produced when the
external amplifier is connected in the inverting mode. Figure 19
shows the ideal transfer characteristics for both the inverting
and noninverting configurations given in Figures 17 and 18.
For noninverting, Figure 17
1000 0000 0000
1000 0000 0001
0111 1111 1111
0111 1111 1110
For inverting, Figure 18
R3
؎V
IN
Next, adjust full scale by applying a FS–3/2 LSB analog input to
AIN, (see Tables II and III) and adjust RFS until the successive
digital output codes flicker between the following codes:
R
FS
1
A
A1
IN
R4
R2
For Noninverting, Figure 17
1111 1111 1110
1111 1111 1111
0000 0000 0001
0000 0000 0000
R
Z
ADC912A*
R1
For Inverting, Figure 18
2
3
–5V
V
REFIN
10F
0.1F
AGND
Table II. Resistor and Potentiometer Values Required for
Figure 17
R1 = R2 = 20k⍀
SEE TABLE II FOR VALUES OF R3, R4, R , AND R
Z
FS
A1: OP27 LOWEST NOISE, OP42 BEST BANDWIDTH
V
V
IN Range R3
R4
k⍀
RZ
k⍀ k⍀
RFS
1/2 LSB FS/2–3/2 LSB
*EXTRA PINS OMITTED FOR CLARITY
k⍀
mV
V
Figure 17. Noninverting Bipolar Analog Input Operation
2.5
5.0
10.0
0
40.2 0.5 0.5
0.61
1.22
2.44
2.49817
4.99634
9.99268
The scaling resistors chosen in bipolar input applications should
be from the same manufacturer to obtain good resistor tracking
performance over temperature. When potentiometers are used
for absolute adjustment, 0.1% tolerance resistors should still be
used as shown in Figures 17 and 18 to minimize temperature
coefficient errors.
20.0 19.8 0.5 1.0
29.8 10.0 0.5 0.5
Table III. Resistor and Potentiometer Values Required for
Figure 18
VIN Range R1
R2
R3
RZ
RFS 1/2 LSB FS/2–3/2 LSB
R2
V
k⍀ k⍀ k⍀ k⍀ k⍀ mV
V
R
FS
R1
2.5
5.0
10.0
20.0 41.2 40.2
20.0 20.5 20.0
20.0 10.5 10.2 0.5
2
1
1
1
1
0.61
1.22
2.44
2.49817
4.99634
9.99268
؎V
IN
1
A
A1
IN
R
Z
ADC912A*
R3
DIGITAL OUTPUT
2
3
V
–5V
REFIN
111...111
INVERTING
FIGURE 18
10F
+
0.1F
111...110
AGND
NON-
INVERTING
FIGURE 17
100...001
SEE TABLE III FOR VALUES OF R1, R2, R3, R4, R , AND R
Z
A1: OP27 LOWEST NOISE, OP42 BEST BANDWIDTH
*EXTRA PINS OMITTED FOR CLARITY
FS
100...000
011...111
011...110
FS
+
– 1LSB
2
Figure 18. Inverting Bipolar Analog Input
000...001
000...000
FS
2
0V
– InputVoltage
FS
–
+
2
V
IN
Figure 19. Ideal Input/Output Transfer Characteristics for
Bipolar Input Circuits
–10–
REV. B
ADC912A
MICROPROCESSOR INTERFACING
is correct, then the Slow-Memory mode is virtually immune to
subsequent software modifications. Placing the microprocessor
in the WAIT state has an additional advantage of quieting the
digital system to reduce noise pickup in the analog conversion
circuitry. The 12-bit parallel Slow-Memory mode provides the
fastest analog sampling rate combined with digital data transfer
rate for sampled-data systems.
The ADC912A has self-contained logic for both 8-bit and 16-bit
data bus interfacing. The output data can be formatted into
either a 12-bit parallel word for a 16-bit data bus or an 8-bit
data word pair for an 8-bit data bus. Data is always right justi-
fied, i.e., LSB is the most right-hand bit in a 16-bit word. For a
two-byte read, only data outputs D7 . . . D0/8 are used. Byte
selection is governed by the HBEN input which controls an
internal digital multiplexer. This multiplexes the 12 bits of
conversion data onto the lower D7 . . . D0/8 outputs (4 MSBs or
8 LSBs) where it can be read in two read cycles. The 4 MSBs
always appear on D11 . . . D8 whenever the three-state output
drivers are turned on. See Figure 20.
PARALLEL READ, SLOW-MEMORY MODE
(HBEN = LOW)
Figure 5 shows the timing diagram and data bus status for Par-
allel Read, Slow-Memory Mode. CS and RD going low triggers
a conversion and the ADC912A acknowledges by taking BUSY
low. Data from the previous conversion appears on the three-
state data outputs. BUSY returns high at the end of conversion,
when the output latches have been updated, and the conversion
Two A/D conversion modes of operation are available for both
data bus sizes: the ROM mode and the Slow-Memory mode.
result is placed on data outputs D11 . . . D0/8
.
"1"
ADC912A
CONVERSION START
(POSITIVE EDGE
TRIGGER)
TWO-BYTE READ, SLOW-MEMORY MODE
D
Q
For a two-byte read only the eight data outputs D7 . . . D0/8
are used. Conversion start procedure and data output status for
the first read operation is identical to Parallel Read, Slow-Memory
Mode. See Figure 6, Timing Diagram and Data Bus Status. At
the end of conversion, the low data byte (DB7 . . . DB0) is read
from the A/D converter. A second READ operation with HBEN
high places the high byte on data outputs D3/11 . . . D0/8 and
disables conversion start. Note the 4 MSBs also appear on data
outputs D11 . . . D8 during these two READ operations.
HBEN
CS
RD
CLR
BUSY
ENABLETHREE-STATE
OUTPUTS
ACTIVE HIGH
(HBEN = "0")
PINS: D ... D
11
0/8
DATA BITS: DB ... DB
11
0
ENABLETHREE-STATE
OUTPUTS
ACTIVE HIGH
(HBEN = "1")
PINS: D ... D
8
11
PARALLEL READ, ROM MODE (HBEN = LOW)
A conversion is started with a READ operation. The 12 bits of
data from the previous conversion are available on data outputs
D11 . . . D0/8 (see Figure 7). This data may be disregarded if
not required. A second READ operation reads the new data
(DB11 . . . DB0) and starts another conversion. A delay at least
as long as the ADC912A conversion time must be allowed be-
tween READ operations. If a READ takes place prior to the end
of 13 CLKS of the ADC conversion, the remaining bits not yet
tested will be invalid.
DATA BITS: DB ... DB
11
8
PINS: D ... D
7
4
DATA BITS: LOGIC LOW
PINS: D ... D
3/11
0/8
DATA BITS: DB ... DB
11
8
Figure 20. Internal Logic for Control Inputs CS, RD, and
HBEN
In the ROM mode each READ instruction obtains new, valid
data, assuming the minimum timing requirements are satisfied.
However, since the data output from a current READ instruc-
tion was generated from a conversion initiated by a previous
READ operation, the current data may be out-of-date. To be
sure of obtaining up-to-date data, READ instructions may be
coded in pairs (with some NOPs between them); use only the
data from the second READ in each pair. The first READ starts
the conversion, the second READ gets the results.
TWO-BYTE READ, ROM MODE
For a two-byte read only the data outputs D7 . . . D0/8 are used.
Conversion is started in the same way with a READ operation
and the data output status is the same as the Parallel Read,
ROM Mode. See Figure 8, Two-Byte Read Timing Diagram,
ROM Mode. Two more READ operations are required to obtain
the new conversion result. A delay equal to the ADC912A con-
version time must be allowed between conversion start and
places the high byte (4 MSBs) on data outputs D3/11 . . . D0/8. A
third READ operation accesses the low data byte (DB7 . . . DB0)
and starts another conversion. The 4 MSBs also appear on data
outputs D11 . . . D8 during all three read operations above.
The Slow-Memory mode is the simplest. It is the method of
choice where compact coding is essential, or where software
bugs are a hazard. In this mode, a single READ instruction will
initiate a data conversion, interrupt the microprocessor until
completion (WAIT states are introduced), then read the results.
If the system throughput tolerates WAIT states, and the hardware
REV. B
–11–
ADC912A
CIRCUIT LAYOUT GUIDELINES
INTERFACING TO THE TMS32010 DSP PROCESSOR
Figure 22 shows an ADC912A to TMS32010 interface. The
ADC912A is operating in the ROM mode. The interface
is designed for the maximum TMS32010 clock frequency
of 20 MHz.
As with any high-speed A/D converters, good circuit layout
practice is essential. Wire-wrap boards are not recommended
due to stray pickup of the high-frequency digital noise. A PC
board offers the best results. Digital and analog grounds
should be separated even if they are ground planes instead of
ground traces. Do not lay digital traces adjacent to high-
impedance analog traces. Avoid digital layouts that radiate
high-frequency clock signals; i.e., do not lay out digital signal
lines and ground returns in the shape of a loop antenna. Shield
the analog input if it comes from a different PC board source.
Set up a single point ground at AGND (Pin 3) of the ADC912A;
tie all other analog grounds to this point. Also tie the logic
power supply ground, but no other digital grounds, to this point
(see Figure 21). Low impedance analog and digital power sup-
ply common returns are essential to low noise operation of the
ADC. Their trace widths should be as wide as possible. Good
power supply bypass capacitors located near the ADC package
ensure quiet operation. Place a 10 µF capacitor in parallel with a
0.01 µF ceramic capacitor across VDD to ground and VSS to
ground (near Pin 3).
ADDRESS BUS
PA PA
0
2
ADDRESS
DECODE
CS
RD
EN
DEN
TMS32010*
ADC912A*
D
11
D
15
DATA BUS
D
0/8
D
0
HBEN
*ESSENTIAL INTERFACE CIRCUITRY SHOWN FOR CLARITY
Figure 22. ADC912A to TMS32010 DSP Processor Interface
The ADC912A is mapped at a user-selected port address (PA).
The following I/O instruction starts a conversion and reads the
previous conversion into the data memory:
ANALOG
SUPPLY
DIGITAL
SUPPLY
+15V
GND
–15V
+5V
RETURN
IN DATA, PA
PA = Port Address
DATA = Data Memory Location
COMMON
GROUND
When conversion is complete, a second I/O instruction reads the
new data into the data memory and starts another conversion.
Sufficient A/D conversion time must be allowed between I/O
instructions. The very first data read after system power-up
should be discarded.
AGND
V
DGND
V
DD
SS
DIGITAL
CIRCUITS
ANALOG
CIRCUITS
ADC912A
USING WAIT STATES
The TMS32020 DSP processor has the added capability of
WAIT states. This feature simplifies the hardware required for
slow memory devices by extending the microprocessor bus
access time. Figure 23 shows an ADC912A to TMS32020
interface using one WAIT state to guarantee data interface at
the full 20 MHz clock frequency. This WAIT state extends the
bus access time by 200 ns. In this circuit the ADC912A operated
in the ROM mode where each input instruction (IN DATA, PA)
takes the previous conversion result and stores it in memory. The
next input instruction must be delayed for the length of the A/D
conversion time so that a new conversion result can be read.
Figure 21. Power Supply Grounding
In applications where the ADC912A data outputs and control
signals are connected to a continuously active microprocessor
bus, it is possible to get LSB level errors in conversion results.
These errors are due to a feedthrough from the microprocessor
to the internal comparator. The problem can be minimized by
forcing the microprocessor into a WAIT state during conversion
(see Slow-Memory microprocessor interfacing). An alternate
method is isolation of the data bus with three-state buffers, such
as the 74HC541.
–12–
REV. B
ADC912A
SLOW-MEMORY MODE OPERATION USING WAIT
STATES
ADDRESS BUS
A
A
15
0
The WAIT state feature of the TMS32020 can also be used to
operate the ADC912A in the Slow-Memory mode. This is
accomplished by driving the clock input of the 7474 flip-flop in
Figure 23, from the BUSY output of the ADC912A, instead of
the CLK OUT 1 of the TMS32020. Once a conversion has
started the READY input of the TMS32020 is not released until
the ADC912A completes its 12-bit A/D conversion. This stops
the TMS32020 during the conversion process reducing micro-
processor system noise generation. Another advantage for the
system software is the single instruction IN MEM, PA used to
start, process, and read the results of the A/D conversion. This
makes the software code more transportable between systems
operating at different clock speeds. The disadvantage is some
loss in instruction processing time.
ADDRESS
DECODE
EN
IS
R/W
READY
TMS32020
؋
2/CLK IN RD
CS
"1"
D
Q
7474
20MHz
CLR CK
ADC912A*
CLK OUT
BUSY
1
ROM MODE
SLOW-MEMORY
MODE
(ONE WAIT STATE)
D
11
D
15
DATA BUS
D
0/8
D
0
HBEN
*ESSENTIAL INTERFACE CIRCUITRY SHOWN FOR CLARITY
Figure 23. ADC912A to TMS32020 Interface Using Wait
States
REV. B
–13–
ADC912A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Narrow Body Plastic DIP Package
(N-24)
1.275 (32.30)
1.125 (28.60)
24
13
12
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77) SEATING
PLANE
0.045 (1.15)
24-Lead Wide Body SOIC Package
(R-24)
0.6141 (15.60)
0.5985 (15.20)
24
13
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
1
12
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
؋
45؇ 8؇
0؇
SEATING
PLANE
0.0500 0.0192 (0.49)
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
(1.27)
0.0138 (0.35)
BSC
–14–
REV. B
Revision History–ADC912A
Location
Page
Data Sheet changed from REV. A to REV. B.
Changes to General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to Static Accuracy section of Specification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
REV. B
–15–
–16–
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