ADCLK905_17 [ADI]
Ultrafast SiGe ECL Clock/Data Buffers;
| 型号： | ADCLK905_17 |
| 厂家： | 
ADI |
| 描述： | Ultrafast SiGe ECL Clock/Data Buffers |
| 文件： | 总16页 (文件大小：867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultrafast SiGe
ECL Clock/Data Buffers
Data Sheet
ADCLK905/ADCLK907/ADCLK925
FEATURES
TYPICAL APPLICATION CIRCUITS
V
V
REF
CC
95 ps propagation delay
V
T
7.5 GHz toggle rate
60 ps typical output rise/fall
D
D
Q
Q
60 fs random jitter (RJ)
On-chip terminations at both input pins
Extended industrial temperature range: −40°C to +125°C
2.5 V to 3.3 V power supply (VCC − VEE
)
V
EE
APPLICATIONS
Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer
Clock and data signal restoration and level shifting
Automated test equipment (ATE)
High speed instrumentation
High speed line receivers
V
1
REF
V 1
T
V
CC
Threshold detection
D1
D1
Q1
Q1
Converter clocking
V
V
EE
GENERAL DESCRIPTION
The ADCLK905 (one input, one output), ADCLK907 (dual one
input, one output), and ADCLK925 (one input, two outputs) are
ultrafast clock/data buffers fabricated on the Analog Devices, Inc.,
proprietary XFCB3 silicon germanium (SiGe) bipolar process.
EE
D2
D2
Q2
Q2
V
CC
V 2
T
The ADCLK905/ADCLK907/ADCLK925 feature full-swing
emitter coupled logic (ECL) output drivers. For PECL (positive
ECL) operation, bias VCC to the positive supply and VEE to ground.
For NECL (negative ECL) operation, bias VCC to ground and
V
2
REF
Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer
V
EE to the negative supply.
V
REF
V
CC
V
T
Q1
Q1
The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate,
10 Gbps data rate, and 60 fs random jitter (RJ).
D
D
The inputs have center tapped, 100 Ω, on-chip termination
resistors. A VREF pin is available for biasing ac-coupled inputs.
Q2
Q2
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to VCC − 2 V for a total
differential output swing of 1.6 V.
V
EE
Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer
The ADCLK905/ADCLK907/ADCLK925 are available in
16-lead LFCSP packages.
Rev. B
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Tel: 781.329.4700 ©2007–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADCLK905/ADCLK907/ADCLK925
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................9
Applications Information .............................................................. 12
Power/Ground Layout and Bypassing..................................... 12
Output Stages ............................................................................... 12
Optimizing High Speed Performance ..................................... 12
Buffer Random Jitter.................................................................. 12
Typical Application Circuits ......................................................... 13
Evaluation Board Schematic ......................................................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuits............................................................ 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
2/2017—Rev. A to Rev. B
Changes to Figure 4 and Table 4..................................................... 6
Changes to Figure 5 and Table 5..................................................... 7
Changes to Figure 6 and Table 6..................................................... 8
8/2016—Rev. 0 to Rev. A
Changed CP-16-3 to CP-16-27 .................................... Throughout
Changes to Figure 4 and Table 4..................................................... 6
Changes to Figure 5 and Table 5..................................................... 7
Changes to Figure 6 and Table 6 ..................................................... 8
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide .......................................................... 15
8/2007—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet
ADCLK905/ADCLK907/ADCLK925
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (Min) and maximum (Max) values are
given over the full VCC − VEE = 3.3 V 10% and TA = −40°C to +125°C variation, unless otherwise noted.
Table 1.
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input Voltage High Level
Input Voltage Low Level
Input Differential Range
VIH
VIL
VID
VEE + 1.6
VCC
V
VEE
0.2
VCC − 0.7
3.4
V
V p-p
−40°C to +85°C
( 1.7 V between input pins)
85°C to 125°C
( 1.4 V between input pins)
VID
CIN
0.2
2.8
V p-p
Input Capacitance
0.4
pF
Input Resistance, Single-Ended Mode
Input Resistance, Differential Mode
Input Resistance, Common Mode
Input Bias Current
50
Ω
100
50
Ω
kΩ
µA
Open VT
20
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
Output Voltage Low Level
Output Voltage Differential
Reference Voltage
VOH
VOL
VOD
VREF
VCC − 1.26
VCC − 1.99
610
VCC − 0.76
VCC − 1.54
1040
V
50 Ω to (VCC − 2.0 V)
50 Ω to (VCC − 2.0 V)
50 Ω to (VCC − 2.0 V)
V
mV
Output Voltage
(VCC + 1)/2
250
V
−500 µA to +500 µA
Output Resistance
Ω
AC PERFORMANCE
Propagation Delay
tPD
70
70
95
95
50
125
125
ps
ps
VCC = 3.3 V 10%,
VICM = VREF, VID = 0.5 V p-p
VCC = 2.5 V 5%,
VICM = VREF, VID = 0.5 V p-p
Propagation Delay Temperature Coefficient
fs/°C
ps
Propagation Delay Skew (Output to Output)
ADCLK907
15
10
35
VID = 0.5 V
VID = 0.5 V
Propagation Delay Skew (Output to Output)
ADCLK925
ps
Propagation Delay Skew (Device to Device)
Toggle Rate
ps
VID = 0.5 V
6
7.5
6.5
60
GHz
>0.8 V differential output swing,
VCC = 3.3 V 10%
GHz
>0.8 V differential output swing,
VCC = 2.5 V 5%
Random Jitter
Rise/Fall Time
Additive Phase Noise
622.08 MHz
RJ
fs rms
ps
VID = 1600 mV, 8 V/ns, VICM = 1.85 V
20%/80%
tR/tF
30
85
−138
−144
−152
−159
−161
−161
−135
−145
−153
−160
−161
−161
dBc/Hz @10 Hz offset
dBc/Hz @100 Hz offset
dBc/Hz @1 kHz offset
dBc/Hz @10 kHz offset
dBc/Hz @100 kHz offset
dBc/Hz >1 MHz offset
dBc/Hz @10 Hz offset
dBc/Hz @100 Hz offset
dBc/Hz @1 kHz offset
dBc/Hz @10 kHz offset
dBc/Hz @100 kHz offset
dBc/Hz >1 MHz offset
122.88 MHz
Rev. B | Page 3 of 16
ADCLK905/ADCLK907/ADCLK925
Data Sheet
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Supply Voltage Requirement
Power Supply Current
ADCLK905
VCC − VEE 2.375
3.63
V
2.5 V − 5% to 3.3 V + 10%
Static
Negative Supply Current
IVEE
IVCC
24
25
47
48
mA
mA
mA
mA
VCC − VEE = 2.5 V
40
63
V
CC − VEE = 3.3 V 10%
VCC − VEE = 2.5 V
CC − VEE = 3.3 V 10%
Positive Supply Current
V
ADCLK907
Negative Supply Current
IVEE
IVCC
48
50
94
96
mA
mA
mA
mA
VCC − VEE = 2.5 V
CC − VEE = 3.3 V 10%
VCC − VEE = 2.5 V
CC − VEE = 3.3 V 10%
80
V
Positive Supply Current
126
V
ADCLK925
Negative Supply Current
IVEE
IVCC
29
31
76
77
3
mA
mA
mA
mA
ps/V
dB
VCC − VEE = 2.5 V
CC − VEE = 3.3 V 10%
VCC − VEE = 2.5 V
CC − VEE = 3.3 V 10%
51
97
V
Positive Supply Current
V
Power Supply Rejection1
Output Swing Supply Rejection2
PSRVCC
PSRVCC
VCC − VEE = 3.0 V 20%
VCC − VEE = 3.0 V 20%
26
1 Change in TPD per change in VCC.
2 Change in output swing per change in VCC.
Rev. B | Page 4 of 16
Data Sheet
ADCLK905/ADCLK907/ADCLK925
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
Supply Voltage
VCC − VEE
6.0 V
Table 3. Thermal Resistance
Input Voltage
D (D1, D2), D (D1, D2)
Package Type
θJA
Unit
VEE − 0.5 V to
CC + 0.5 V
16-Lead LFCSP
70
°C/W
V
D1, D2, D1, D2 to VT Pin
(CML or PECL Termination)
D (D1, D2) to D (D1, D2)
40 mA
ESD CAUTION
1.8 V
Maximum Voltage on Output Pins
Maximum Output Current
VCC + 0.5 V
35 mA
2 V
Input Termination, VT to D (D1, D2), D (D1, D2)
Voltage Reference, VREF
VCC − VEE
Temperature
Operating Temperature Range, Ambient
Operating Temperature, Junction
Storage Temperature Range
−40°C to +125°C
150°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 5 of 16
ADCLK905/ADCLK907/ADCLK925
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D
1
2
3
4
12
11
10
9
Q
D
NC
NC
Q
ADCLK905
TOP VIEW
NC
NC
(Not to Scale)
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. EXPOSED PAD. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CIRCUIT.
IT CAN BE LEFT FLOATING FOR OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE
AND THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE APPLICATION BOARD IF IMPROVED
THERMAL AND/OR MECHANICAL STABILITY IS DESIRED. EXPOSED METAL AT THE CORNERS OF THE PACKAGE
IS CONNECTED TO THIS EXPOSED PAD. ALLOW SUFFICIENT CLEARANCE TO VIAS AND OTHER COMPONENTS.
Figure 4. ADCLK905 Pin Configuration
Table 4. Pin Function Descriptions for 1:1 ADCLK905 Buffer
Pin No.
Mnemonic
Description
1
2
D
Noninverting Input.
D
Inverting Input.
3, 4, 5, 6,
9, 10
NC
No Connect. No physical connection to the die.
7, 14
8, 13
11
VEE
VCC
Q
Negative Supply Voltage.
Positive Supply Voltage.
Inverting Output.
12
Q
Noninverting Output.
15
VREF
VT
Reference Voltage. Reference voltage for biasing ac-coupled inputs.
Center Tap. Center tap of 100 Ω input resistor.
16
EPAD
Exposed Pad. The exposed pad is not electrically connected to any part of the circuit. It can be left floating for
optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to
the application board if improved thermal and/or mechanical stability is desired. Exposed metal at the corners
of the package is connected to this exposed pad. Allow sufficient clearance to vias and other components.
Rev. B | Page 6 of 16
Data Sheet
ADCLK905/ADCLK907/ADCLK925
D1
1
2
3
4
12
11
10
9
Q1
Q1
Q2
Q2
D1
D2
D2
ADCLK907
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CIRCUIT.
IT CAN BE LEFT FLOATING FOR OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE
AND THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE APPLICATION BOARD IF IMPROVED
THERMAL AND/OR MECHANICAL STABILITY IS DESIRED. EXPOSED METAL AT THE CORNERS OF THE PACKAGE
IS CONNECTED TO THIS EXPOSED PAD. ALLOW SUFFICIENT CLEARANCE TO VIAS AND OTHER COMPONENTS.
Figure 5. ADCLK907 Pin Configuration
Table 5. Pin Function Descriptions for Dual 1:1 ADCLK907 Buffer
Pin No.
Mnemonic
Description
1
D1
D1
D2
D2
VT2
Noninverting Input 1.
2
Inverting Input 1.
3
Noninverting Input 2.
4
Inverting Input 2.
5
Center Tap 2. Center tap of 100 Ω input resistor, Channel 2.
Reference Voltage 2. Reference voltage for biasing ac-coupled inputs, Channel 2.
Negative Supply Voltage.
6
VREF
VEE
2
7, 14
8, 13
9
VCC
Q2
Q2
Q1
Q1
VREF
VT1
Positive Supply Voltage. Pin 8 and Pin 13 are not strapped internally.
Inverting Output 2.
10
11
12
15
16
Noninverting Output 2.
Inverting Output 1.
Noninverting Output 1.
1
Reference Voltage 1. Reference voltage for biasing ac-coupled inputs, Channel 1.
Center Tap 1. Center tap of 100 Ω input resistor, Channel 1.
EPAD
Exposed Pad. The exposed pad is not electrically connected to any part of the circuit. It can be left floating for
optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to
the application board if improved thermal and/or mechanical stability is desired. Exposed metal at the corners
of the package is connected to this exposed pad. Allow sufficient clearance to vias and other components.
Rev. B | Page 7 of 16
ADCLK905/ADCLK907/ADCLK925
Data Sheet
D
D
1
2
3
4
12
11
Q1
Q1
ADCLK925
TOP VIEW
10 Q2
Q2
NC
NC
(Not to Scale)
9
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. EXPOSED PAD. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CIRCUIT.
IT CAN BE LEFT FLOATING FOR OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE
AND THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE APPLICATION BOARD IF IMPROVED
THERMAL AND/OR MECHANICAL STABILITY IS DESIRED. EXPOSED METAL AT THE CORNERS OF THE PACKAGE
IS CONNECTED TO THIS EXPOSED PAD. ALLOW SUFFICIENT CLEARANCE TO VIAS AND OTHER COMPONENTS.
Figure 6. ADCLK925 Pin Configuration
Table 6. Pin Function Descriptions for 1:2 ADCLK925 Buffer
Pin No.
Mnemonic
Description
1
D
Noninverting Input.
2
D
Inverting Input.
3, 4, 5, 6
7, 14
8, 13
9
NC
VEE
VCC
Q2
Q2
Q1
Q1
VREF
VT
No Connect. No physical connection to the die.
Negative Supply Voltage.
Positive Supply Voltage.
Inverting Output 2.
10
Noninverting Output 2.
11
Inverting Output 1.
12
Noninverting Output 1.
15
Reference Voltage. Reference voltage for biasing ac-coupled inputs.
Center Tap. Center tap of 100 Ω input resistor.
16
EPAD
Exposed Pad. The exposed pad is not electrically connected to any part of the circuit. It can be left floating for
optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to
the application board if improved thermal and/or mechanical stability is desired. Exposed metal at the corners
of the package is connected to this exposed pad. Allow sufficient clearance to vias and other components.
Rev. B | Page 8 of 16
Data Sheet
ADCLK905/ADCLK907/ADCLK925
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0.0 V, TA = 25°C, outputs terminated 50 Ω to VCC − 2 V, unless otherwise noted.
2.37V
2.37V
Q
Q
Q
Q
1.37V
1.37V
200ps/DIV
100ps/DIV
Figure 7. Output Waveform, VCC = 3.3 V
Figure 10. Output Waveform, VCC = 3.3 V
–90
–100
–110
–120
–130
–140
–150
–160
–170
–90
–100
–110
–120
–130
–140
–150
–160
–170
AGILENT E5500
AGILENT E5500
CARRIER: 122.88MHz
NO SPURS
CARRIER: 622.08MHz
NO SPURS
10
100
1k
10k
100k
f (Hz)
1M
10M
100M
10
100
1k
10k
100k
f (Hz)
1M
10M
100M
Figure 11. Phase Noise at 622.08 MHz
Figure 8. Phase Noise at 122.88 MHz
300
250
200
150
100
50
–90
–100
–110
–120
–130
–140
–150
–160
–170
AGILENT E5500
CARRIER: 245.76MHz
NO SPURS
0
0
1
2
3
4
5
6
7
8
10
100
1k
10k
100k
f (Hz)
1M
10M
100M
INPUT SLEW RATE (V/ns)
Figure 12. RMS Jitter vs. Input Slew Rate
Figure 9. Phase Noise at 245.76 MHz
Rev. B | Page 9 of 16
ADCLK905/ADCLK907/ADCLK925
Data Sheet
1.1
1.0
0.9
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
+125°C
+25°C
–55°C
+125°C
0.8
0.7
+25°C
0.6
+125°C
–55°C
0.5
+25°C
–55°C
0.4
0
1
2
3
4
1
2
3
4
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 13. VOD vs. Power Supply Voltage
Figure 16. Power Supply Current vs. Supply Voltage, ADCLK925
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
100
99
98
97
96
95
94
+125°C
+25°C
–55°C
+125°C
+25°C
–55°C
0.4
0.6
0.8
1.0
1.2
(V)
1.4
1.6
1.8
2.5
3.0
3.5
4.0
V
POWER SUPPLY VOLTAGE (V)
ID
Figure 14. Power Supply Current vs. Power Supply Voltage, ADCLK905
Figure 17. Propagation Delay vs. VID
110
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
105
+125°C
100
+25°C
95
–55°C
90
1.6
2.1
2.6
3.1
3.6
INPUT COMMON MODE (V)
FREQUENCY (GHz)
Figure 15. Propagation Delay vs. VICM; Input Swing = 200 mV
Figure 18. Toggle Rate, Differential Output Swing vs. Frequency
Rev. B | Page 10 of 16
Data Sheet
ADCLK905/ADCLK907/ADCLK925
1
1
C4
C4
2
2
17ps/DIV
58ps/DIV
3
3
Figure 19. 2.488 Gbps PRBS 223 − 1 with OC-48/STM-16 Mask,
Measured p-p Jitter 8.1 ps, Source p-p Jitter 3.5 ps
Figure 22. 8.50 Gbps PRBS 223 − 1 with FC8500E ABS Beta Rx Mask,
Measured p-p Jitter 10.9 ps, Source p-p Jitter 4.4 ps
1
1
C4
C4
2
2
58ps/DIV
15ps/DIV
3
3
Figure 20. 9.95 Gbps PRBS 223 − 1 with OC-193/STM-64 Mask,
Measured p-p Jitter 10.5 ps, Source p-p Jitter 6.0 ps
Figure 23. 2.5 Gbps PRBS 223 − 1 with PCI Express 2.5 Rx Mask,
Measured p-p Jitter 8.1 ps, Source p-p Jitter 3.5 ps
1
1
C4
C4
2
2
29ps/DIV
34ps/DIV
3
3
Figure 21. 4.25 Gbps PRBS 223 − 1 with FC4250 (Optical) Mask,
Measured p-p Jitter 8.2 ps, Source p-p Jitter 3.4 ps
Figure 24. 5.0 Gbps PRBS 223 − 1 with PCI Express 5.0 Rx Mask,
Measured p-p Jitter 8.7 ps, Source p-p Jitter 3.5 ps
Rev. B | Page 11 of 16
ADCLK905/ADCLK907/ADCLK925
Data Sheet
APPLICATIONS INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
OPTIMIZING HIGH SPEED PERFORMANCE
The ADCLK905/ADCLK907/ADCLK925 buffers are designed
for very high speed applications. Consequently, high speed design
techniques must be used to achieve the specified performance.
It is critically important to use low impedance supply planes for
both the negative supply (VEE) and the positive supply (VCC) planes
as part of a multilayer board. Providing the lowest inductance
return path for switching currents ensures the best possible
performance in the target application.
As with any high speed circuit, proper design and layout
techniques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and cause oscillation. Discontinuities along input and output
transmission lines can also severely limit the specified jitter
performance by reducing the effective input slew rate.
In a 50 Ω environment, input and output matching have a
It is also important to adequately bypass the input and output
supplies. A 1 µF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.001 µF bypass capacitors
should be placed as close as possible to each of the VEE and VCC
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should be strictly avoided to maximize the
effectiveness of the bypass at high frequencies.
significant impact on performance. The buffer provides internal
D
50 Ω termination resistors for both D and inputs. The return
side should normally be connected to the reference pin provided.
The termination potential should be carefully bypassed, using
ceramic capacitors to prevent undesired aberrations on the
input signal due to parasitic inductance in the termination
return path. If the inputs are directly coupled to a source, care
must be taken to ensure the pins are within the rated input
differential and common-mode ranges.
If the return is floated, the device exhibits 100 Ω cross termination,
but the source must then control the common-mode voltage
and supply the input bias currents.
OUTPUT STAGES
The specified performance can be achieved only by using proper
transmission line terminations. The outputs of the ADCLK905/
ADCLK907/ADCLK925 buffers are designed to directly drive
800 mV into 50 Ω cable or microstrip/stripline transmission
lines terminated with 50 Ω referenced to VCC − 2 V. The PECL
output stage is shown in Figure 25. The outputs are designed for
best transmission line matching. If high speed signals must be
routed more than a centimeter, either the microstrip or the
stripline technique is required to ensure proper transition times
and to prevent excessive output ringing and pulse width-
dependent propagation delay dispersion.
There are ESD/clamp diodes between the input pins to prevent
the application of excessive offsets to the input transistors. ESD
diodes are not optimized for best ac performance. When a
clamp is desired, it is recommended that appropriate external
diodes be used.
BUFFER RANDOM JITTER
The ADCLK905/ADCLK907/ADCLK925 are specifically
designed to minimize added random jitter over a wide input
slew rate range. Provided sufficient voltage swing is present,
random jitter is affected most by the slew rate of the input signal.
Whenever possible, excessively large input signals should be
clamped with fast Schottky diodes because attenuators reduce the
slew rate. Input signal runs of more than a few centimeters
should be over low loss dielectrics or cables with good high
frequency characteristics.
V
CC
Q
Q
V
EE
Figure 25. Simplified Schematic Diagram of
the ADCLK905/ADCLK907/ADCLK925 PECL Output Stage
Rev. B | Page 12 of 16
Data Sheet
ADCLK905/ADCLK907/ADCLK925
TYPICAL APPLICATION CIRCUITS
V
CC
V
V
REF
REF
V
V
T
T
D
D
D
D
CONNECT V TO V
.
CONNECT V TO V
.
REF
T
CC
T
NOTES
1. PLACING A BYPASS CAPACITOR
FROM V TO GROUND CAN IMPROVE
T
THE NOISE PERFORMANCE.
Figure 26. Interfacing to CML Inputs
Figure 28. AC Coupling Differential Signals
V
V
REF
REF
V
T
V
T
V
– 2V
CC
D
D
D
D
CONNECT V TO V − 2V.
CC
CONNECT V , V
, AND D. PLACE A BYPASS
CAPACITOR FROM V TO GROUND.
T
T
REF
T
ALTERNATIVELY, V , V
, AND D CAN BE
T
REF
CONNECTED, GIVING A CLEANER LAYOUT AND
A 180º PHASE SHIFT.
Figure 27. Interfacing to PECL
Figure 29. Interfacing to AC-Coupled Single-Ended Inputs
Rev. B | Page 13 of 16
TP5
RED
V
1
V
REF
REF1
matched length ×2
J11
J12
CAL_1
0Ω resistors are NOT to be installed.
TP8
RED
C44
VREF
2
VREF2
.01UF
Solder bridges will be completed
by end user if desired.
A1
J8
J5
Q1
D1
1
Q1 12
Q1 11
D1
J6
J2
Q1_B
D1_B
2
D1
ADCLK9XX
matched lengths
Q2
J1
J3
D2
D2_B
3
4
D2
D2
Q2 10
LFCSP16-3X3
J7
J4
Q2_B
Q2
9
TP6
RED
VT1
VT1
PAD
PAD
VEE
C16
.1UF
VAL
C45
.01UF
0Ω resistors are NOT to be installed.
Solder bridges will be completed
by end user if desired.
TP7
RED
V
2
T
VT2
J10
J9
CAL_2
matched length ×2
TP2
RED
TP1
TP4
TP3
RED
VCC
VEE
BLK
BLK
VCC
VEE
JP1
V
T2
VREF
2
JP8
JP7
1
1
VT1
VREF1
2
2
1
1
2
2
0
0
0
0
Jumpers are NOT to be installed.
JP2
Solder bridges will be completed
by end user if desired.
JP3
JP4
JP6
JP5
1
1
2
2
1
1
2
2
0
0
0
0
Data Sheet
ADCLK905/ADCLK907/ADCLK925
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
12
EXPOSED
PAD
1.65
1.50 SQ
1.45
9
4
8
5
0.50
0.40
0.30
0.20 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 31. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-27)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
CP-16-27
CP-16-27
CP-16-27
CP-16-27
CP-16-27
CP-16-27
CP-16-27
CP-16-27
CP-16-27
Branding
Y03
ADCLK905BCPZ-WP
ADCLK905BCPZ-R7
ADCLK905BCPZ-R2
ADCLK907BCPZ-WP
ADCLK907BCPZ-R7
ADCLK907BCPZ-R2
ADCLK925BCPZ-WP
ADCLK925BCPZ-R7
ADCLK925BCPZ-R2
ADCLK905/PCBZ
ADCLK907/PCBZ
ADCLK925/PCBZ
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Y03
Y03
Y06
Y06
Y06
Y08
Y08
Y08
Evaluation Board
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. B | Page 15 of 16
ADCLK905/ADCLK907/ADCLK925
NOTES
Data Sheet
©2007–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06318-0-2/17(B)
Rev. B | Page 16 of 16
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