ADCLK914BCPZ-WP [ADI]
Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer; 超快，锗，开集HVDS时钟/数据缓冲器
| 型号： | ADCLK914BCPZ-WP |
| 厂家： | 
ADI |
| 描述： | Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer |
| 文件： | 总12页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultrafast, SiGe, Open-Collector
HVDS Clock/Data Buffer
ADCLK914
FUNCTIONAL BLOCK DIAGRAM
FEATURES
7.5 GHz operating frequency
160 ps propagation delay
V
V
CC
REF
100 ps output rise/fall
110 fs random jitter
On-chip input terminations
Extended industrial temperature range: −40°C to +125°C
3.3 V power supply (VCC − VEE
ADCLK914
V
T
50Ω
50Ω
50Ω 50Ω
Q
Q
D
D
)
APPLICATIONS
Clock and data signal restoration
High speed converter clocking
Broadband communications
Cellular infrastructure
V
EE
Figure 1.
High speed line receivers
ATE and high performance instrumentation
Level shifting
Threshold detection
GENERAL DESCRIPTION
The input has a center tapped, 100 Ω, on-chip termination
resistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS
(ac-coupled only). A VREF pin is available for biasing ac-coupled
inputs.
The ADCLK914 is an ultrafast clock/data buffer fabricated on
the Analog Devices, Inc., proprietary, complementary bipolar
(XFCB-3) silicon-germanium (SiGe) process. The ADCLK914
features high voltage differential signaling (HVDS) outputs
suitable for driving the latest Analog Devices high speed digital-
to-analog converters (DACs). The ADCLK914 has a single,
differential open-collector output.
The HVDS output stage is designed to directly drive 1.9 V each
side into 50 Ω terminated to VCC for a total differential output
swing of 3.8 V.
The ADCLK914 buffer operates up to 7.5 GHz with a 160 ps
propagation delay and adds only 110 fs random jitter (RJ).
The ADCLK914 is available in a 16-lead LFCSP. It is specified
for operation over the extended industrial temperature range of
−40°C to +125°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADCLK914
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications Information.................................................................9
Power/Ground Layout and Bypassing........................................9
HVDS Output Stage......................................................................9
Interfacing to High Speed DACs.................................................9
Optimizing High Speed Performance ........................................9
Random Jitter.................................................................................9
Typical Application Circuits ..................................................... 10
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
REVISION HISTORY
10/08—Rev. 0 to Rev. A
Changes to Input Low Voltage Parameter, Table 1....................... 3
Changes to Output High Voltage Parameter, Table 1 ................ 3
Changes to Output Low Voltage Parameter, Table 1.................. 3
Output Differential Range Parameter, Table 1 ............................ 3
Changes to Absolute Maximum Ratings Section ........................ 5
7/08—Revision 0: Initial Version
Rev. A | Page 2 of 12
ADCLK914
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 3.3 V, VEE = 0 V, TA = −40°C to +125°C. All outputs terminated through 50 Ω to VCC, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
VIH
VIL
VID
VEE + 1.65
VEE
0.2
VCC
VCC − 0.2
3.4
V
V
V p-p
Input Differential Range
TA = −40°C to +85°C
( 1.ꢀ V between input pins)
0.2
2.8
V p-p
TA = 85°C to 125°C
( 1.4 V between input pins)
Input Capacitance
Input Resistance
CIN
0.4
50
pF
Ω
Differential Mode
Common Mode
Input Bias Current
100
50
20
Ω
kΩ
μA
Open termination
DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
Output Differential Range
Reference Voltage
Output Voltage
Output Resistance
AC PERFORMANCE
Operating Frequency
VOH
VOL
VOD
VREF
VCC − 0.55
VCC − 2.ꢀ5
1.54
VCC − 0.40
VCC − 2.35
1.95
VCC − 0.25
VCC − 1.9
2.22
V
V
V
(VCC + 1)/2
250
V
Ω
−500 ꢁA to +500 ꢁA
ꢀ.5
GHz
ps
>1.1 V differential output swing,
VCC = 3.3 V 10%
VCC = 3.3 V 10%,VICM = VREF
VID = 1.6 V p-p
Propagation Delay
tPD
12ꢀ
158
140
202
65
,
Propagation Delay Temperature
Coefficient
Propagation Delay Skew (Device
to Device)
fs/°C
ps
VID = 1.6 V p-p
Output Rise Time
Output Fall Time
tR
tF
100
80
125
95
ps
ps
20%/80%
80%/20%
Wideband Random Jitter1
Additive Phase Noise
622.08 MHz
RJ
110
fs rms
VID = 1.6 V p-p, 6 V/ns, VICM = 1.85 V
−132
−143
−151
−156
−15ꢀ
−156
−133
−143
−153
−158
−159
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10 Hz offset
@100 Hz offset
@1 kHz offset
@10 kHz offset
@100 kHz offset
>1 MHz offset
@10 Hz offset
@100 Hz offset
@1 kHz offset
@10 kHz offset
@100 kHz offset
>1 MHz offset
245.ꢀ6 MHz
Rev. A | Page 3 of 12
ADCLK914
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
@10 Hz offset
@100 Hz offset
@1 kHz offset
@10 kHz offset
122.88 MHz
−150
−156
−160
−161
−161
−160
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@100 kHz offset
>1 MHz offset
POWER SUPPLY
Supply Voltage Requirement
Power Supply Current
VCC
2.9ꢀ
3.63
V
Negative Supply Current
Positive Supply Current
Power Supply Rejection2
Output Swing Supply Rejection3
IVEE
IVCC
PSRVCC
66
34
111
55
13
150
ꢀ3
mA
mA
ps/V
dB
Includes output current
VCC = 3.3 V 10%
VCC = 3.3 V 10%
−15
1 Calculated from SNR of ADC method. See Figure 8 for rms jitter vs. input slew rate.
2 Change in tPD per change in VCC
3 Change in output swing per change in VCC.
.
Rev. A | Page 4 of 12
ADCLK914
ABSOLUTE MAXIMUM RATINGS
Table 2.
Values of θJA are provided for package comparison and PCB
Parameter
Rating
design considerations. θJA can be used for a first-order
Supply Voltage (VCC to GND)
Input Voltage
Maximum Output Voltage
Minimum Output Voltage
Input Termination
6.0 V
approximation of TJ by the equation
−0.5 V to VCC + 0.5 V
VCC + 0.5 V
VEE − 0.5 V
2 V
VCC − VEE
−40°C to +125°C
150°C
TJ = TA + (θJA × PD)
where TA is the ambient temperature (°C).
Values of θJB are provided for package comparison and PCB
design considerations.
Voltage Reference
Operating Temperature Range, Ambient
Operating Temperature, Junction
Storage Temperature Range
Table 3. Thermal Parameters for ADCLK914 16-Lead LFCSP
Symbol Description1
Value Units
−65°C to +150°C
Junction-to-ambient thermal
resistance, 0.0 meters per sec air
flow per JEDEC JESD51-2 (still air)
ꢀ8.4
68.5
61.4
48.8
1.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Junction-to-ambient thermal
resistance, 1.0 meter per sec air flow
per JEDEC JESD51-6 (moving air)
θJMA
θJMA
θJB
Junction-to-ambient thermal
resistance, 2.5 m/s air flow per
JEDEC JESD51-6 (moving air)
Junction-to-board thermal
resistance, 1.0 meter per sec air flow
per JEDEC JESD51-8 (moving air)
THERMAL PERFORMANCE
The ADCLK914 is specified for a case temperature (TCASE). To
ensure that TCASE is not exceeded, use an airflow source.
Junction-to-case thermal resistance
(die-to-heatsink) per MIL-Std 883,
Method 1012.1
θJC
To determine the junction temperature on the application PCB
Junction-to-top-of-package
characterization parameter, 0
meters per sec air flow per JEDEC
JESD51-2 (still air)
2.0
ΨJT
TJ = TCASE + (ΨJT × PD)
where:
TJ is the junction temperature (°C).
1 Descriptions based on using a 2s2p test board.
TCASE is the case temperature (°C) measured by the customer at
top center of package.
ESD CAUTION
ΨJT is determined by the values listed in Table 3.
PD is the power dissipation.
Rev. A | Page 5 of 12
ADCLK914
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
12 Q
11 Q
10 NC
D
D
1
2
3
4
ADCLK914
NC
NC
TOP VIEW
(Not to Scale)
9
NC
NC = NO CONNECT
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
D
D
Noninverting Input.
Inverting Input.
3, 4, 5, 6, 9, 10 NC
No Connect. No physical connection to the die.
Negative Supply Voltage.
Positive Supply Voltage.
ꢀ, 14
8, 13
11
VEE
VCC
Q
Inverting Output.
12
Q
Noninverting Output.
15
16
VREF
VT
Reference Voltage. Reference voltage for biasing ac-coupled inputs.
Center Tap. Center tap of 100 Ω input resistor.
Heat Sink/
Exposed Pad
NC
No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit.
It can be left floating for optimal electrical isolation between the package handle and the substrate of the
die. It can also be soldered to ground on the application board if improved thermal and/or mechanical
stability is needed. Exposed metal at the corners of the package is connected to this back surface. Allow
sufficient clearance for vias and other components.
Rev. A | Page 6 of 12
ADCLK914
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0 V, TA = 25°C. All outputs terminated through 50 ꢀ to VCC, unless otherwise noted.
Q
Q
Q
Q
62.5ps/DIV
100ps/DIV
Figure 3. Output Waveform at 1 GHz, VCC = 3.3 V
Figure 6. Output Waveform at 1 GHz, VCC = 3.3 V
–120
–120
–130
–140
–150
–160
–130
–140
–150
–160
–170
–170
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 4. Phase Noise at 122.88 MHz
Figure 7. Phase Noise at 622.08 MHz
–120
350
T
= 25°C
A
300
250
–130
–140
–150
–160
200
150
100
50
–170
0
10
100
1k
10k
100k
1M
10M
100M
0
1
2
3
4
5
6
7
8
FREQUENCY (Hz)
INPUT SLEW RATE (V/ns)
Figure 5. Phase Noise at 245.76 MHz
Figure 8. RMS Jitter vs. Input Slew Rate
Rev. A | Page ꢀ of 12
ADCLK914
3.80
3.75
3.70
3.65
3.60
3.55
162
160
158
156
154
152
150
148
146
3.50
2.97
3.13
3.30
3.46
3.63
0.4
0.8
1.2
1.6
2.0
POWER SUPPLY VOLTAGE (V)
INPUT DIFFERENTIAL (V p-p)
Figure 9. Differential Output Swing vs. Power Supply Voltage
Figure 12. Propagation Delay vs. VID; VICM = 2.15 V
115
4.0
114
113
112
111
110
109
108
107
106
105
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5
2.97
3.13
3.30
3.46
3.63
FREQUENCY (GHz)
POWER SUPPLY VOLTAGE (V)
Figure 10. Power Supply Current vs. Power Supply Voltage
Figure 13. Toggle Rate, Differential Output Swing vs. Frequency
200
180
160
140
120
100
80
60
40
20
0
0.5
1.0
1.5
2.0
2.5
INPUT COMMON MODE (V)
Figure 11. Propagation Delay vs. VICM; VID = 1.6 V p-p
Rev. A | Page 8 of 12
ADCLK914
APPLICATIONS INFORMATION
losses. The ADCLK914, in turn, may be driven directly by
POWER/GROUND LAYOUT AND BYPASSING
standard or low swing PECL, CML, CMOS, or LVTTL sources,
or by LVDS with simple ac coupling, as illustrated in Figure 15
through Figure 19.
The ADCLK914 buffer is designed for very high speed applica-
tions. Consequently, high speed design techniques must be used
to achieve the specified performance. It is critically important to
use low impedance supply planes for both the negative supply
(VEE) and the positive supply (VCC) planes as part of a multilayer
board. Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed circuit, proper design and layout tech-
niques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power, and ground
impedances, as well as other layout issues, can severely limit
performance and can cause oscillation. Discontinuities along
input and output transmission lines can also severely limit the
specified jitter performance by reducing the effective input
slew rate.
It is also important to adequately bypass the input and output
supplies. Place a 1 μF electrolytic bypass capacitor within several
inches of each power supply pin to ground. In addition, place
multiple high quality 0.001 μF bypass capacitors as close as
possible to each VEE and VCC supply pin and connect these cap-
acitors to the GND plane with redundant vias. Carefully select
high frequency bypass capacitors for minimum inductance and
ESR. To maximize the effectiveness of the bypass capacitors at
high frequencies, strictly avoid parasitic layout inductance.
Input and output matching have a significant impact on
performance. The ADCLK914 buffer provides internal 50 Ω
D
termination resistors for both D and inputs. The return side
can be connected to the reference pin provided or to a current
sink at VCC − 2 V for use with differential PECL, or to VCC for
direct coupled CML. The VREF pin should be left floating any
time that it is not used to minimize power consumption.
Slew currents may also appear at the VDD and VSS pins of the
device being driven by the ADCLK914.
HVDS OUTPUT STAGE
Note that the ADCLK914 VREF source is current-limited to resist
damage from momentary shorts to VEE or VCC and from capacitor
charging currents; for this reason, the VREF source cannot be
used as a PECL termination supply.
The ADCLK914 has been developed to provide a bipolar interface
to any CMOS device that requires extremely low jitter, high
amplitude clocks. It is intended to be placed as close as possible
to the receiving device and allows the rest of the clock distribu-
tion to run at standard CML or PECL levels.
Carefully bypass the termination potential using ceramic capa-
citors to prevent undesired aberrations on the input signal due
to parasitic inductance in the termination return path. If the
inputs are directly coupled to a source, care must be taken to
ensure that the pins remain within the rated input differential
and common-mode ranges.
Interconnects must be short and very carefully designed
because the single terminated design provides much less
margin for error than lower voltage, double terminated
transmission techniques.
Q
If the return is floated, the device exhibits 100 Ω cross-term-
ination, but the source must then control the common-mode
voltage and supply the input bias currents.
Q
ESD/clamp diodes between the input pins prevent the appli-
cation of excessive offsets to the input transistors. ESD diodes
are not optimized for best ac performance. If a clamp is needed,
it is recommended that appropriate external diodes be used.
40mA
7mA
7mA
V
V
V
EE
EE
EE
RANDOM JITTER
Figure 14. Simplified Schematic Diagram
of the ADCLK914 HVDS Output Stage
The ADCLK914 buffer has been specifically designed to
minimize random jitter over a wide input range. Provided
that sufficient voltage swing is present, random jitter is affected
most by the slew rate of the input signal. Whenever possible,
clamp excessively large input signals with fast Schottky diodes
because attenuators reduce the slew rate. Input signal runs of
more than a few centimeters should be over low loss dielectrics
or cables with good high frequency characteristics.
INTERFACING TO HIGH SPEED DACs
The ADCLK914 is designed to drive high amplitude, low jitter
clock signals into high speed, multi-GSPS DACs. The ADCLK914
should be placed as close as possible to the clock input of the
DAC so that the high slew rate and high amplitude clock signal
that these devices require do not cause routing difficulties,
generate EMI, or become degraded by dielectric and other
Rev. A | Page 9 of 12
ADCLK914
TYPICAL APPLICATION CIRCUITS
V
CC
V
V
REF
REF
V
V
T
T
V
– 2V
CC
D
D
D
D
CONNECT V TO V
CC
.
CONNECT V TO V – 2V.
CC
T
T
Figure 15. Interfacing to CML Inputs
Figure 18. Interfacing to ECL Inputs
V
V
REF
REF
V
V
T
T
D
D
D
D
CONNECT V TO V
REF
.
CONNECT V , V
T
, AND D. PLACE A BYPASS
T
REF
CAPACITOR FROM V TO GROUND.
NOTES
T
1. PLACING A BYPASS CAPACITOR
ALTERNATIVELY, V , V
, AND D CAN BE
T
REF
FROM V TO GROUND CAN IMPROVE
CONNECTED, GIVING A CLEANER LAYOUT AND
T
THE NOISE PERFORMANCE.
A 180º PHASE SHIFT.
Figure 19. Interfacing to AC-Coupled, Single-Ended Inputs
Figure 16. AC Coupling Differential Signals
V
CC
Q
Q
40mA
7mA
7mA
V
V
V
EE
EE
EE
Figure 17. Interfacing to High Speed DAC
Rev. A | Page 10 of 12
ADCLK914
OUTLINE DIMENSIONS
0.50
0.40
0.30
0.60 MAX
3.00
BSC SQ
PIN 1
INDICATOR
BOTTOM VIEW
*
1.65
1.50 SQ
1.35
13
12
16
1
0.45
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
4
9
8
0.50
BSC
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.90
0.85
0.80
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 20. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADCLK914BCPZ-WP1
ADCLK914BCPZ-Rꢀ1
ADCLK914BCPZ-R21
ADCLK914/PCBZ1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
CP-16-3
CP-16-3
CP-16-3
1 Z = RoHS Compliant Part.
Rev. A | Page 11 of 12
ADCLK914
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06561-0-10/08(A)
Rev. A | Page 12 of 12
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