ADCLK944 [ADI]
2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer; 2.5 V / 3.3 V ，四LVPECL输出的SiGe时钟扇出缓冲器
| 型号： | ADCLK944 |
| 厂家： | 
ADI |
| 描述： | 2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer |
| 文件： | 总12页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V/3.3 V, Four LVPECL Outputs,
SiGe Clock Fanout Buffer
ADCLK944
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Operating frequency: 7.0 GHz
Broadband random jitter: 50 fs rms
On-chip input terminations
LVPECL
ADCLK944
Q0
Q0
Power supply (VCC − VEE): 2.5 V to 3.3 V
V
REF
REFERENCE
Q1
Q1
Q2
Q2
Q3
Q3
APPLICATIONS
V
T
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
CLK
CLK
Medical and industrial imaging
ATE and high performance instrumentation
Figure 1.
The ADCLK944 features four full-swing emitter-coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
GENERAL DESCRIPTION
The ADCLK944 is an ultrafast clock fanout buffer fabricated on
the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to VCC − 2 V for a total differen-
tial output swing of 1.6 V.
The device has a differential input equipped with center-tapped,
differential, 100 Ω on-chip termination resistors. The input can
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF
pin is available for biasing ac-coupled inputs.
The ADCLK944 is available in a 16-lead LFCSP and is specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADCLK944
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Thermal Performance...................................................................5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
Theory of Operation .........................................................................9
Clock Inputs...................................................................................9
Clock Outputs................................................................................9
PCB Layout Considerations...................................................... 10
Input Termination Options....................................................... 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Clock Inputs and Outputs ........................................................... 3
Timing Characteristics ................................................................ 3
Power.............................................................................................. 4
Absolute Maximum Ratings............................................................ 5
Determining Junction Temperature .......................................... 5
REVISION HISTORY
3/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADCLK944
SPECIFICATIONS
Typical values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum and maximum values are given for the
full VCC − VEE = 3.3 V + 10% to 2.5 V − 5% and TA = −40°C to +85°C variation, unless otherwise noted.
CLOCK INPUTS AND OUTPUTS
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input Common-Mode Voltage VICM
VEE + 1.35
0.4
VCC − 0.1
3.4
V
V p-p
pF
Input Differential Voltage
Input Capacitance
VID
CIN
RIN
1.ꢀ V between input pins
0.4
Input Resistance
Single-Ended Mode
Differential Mode
Common Mode
50
100
50
Ω
Ω
kΩ
μA
VT open
Input Bias Current
20
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
Output Voltage Low Level
VOH
VOL
VCC − 1.26
VCC − 1.99
600
VCC − 0.ꢀ6
VCC − 1.54
960
V
V
mV
Load = 50 Ω to (VCC − 2.0 V)
Load = 50 Ω to (VCC − 2.0 V)
VOH − VOL, output static
Output Voltage, Single-Ended VO
Voltage Reference
Output Voltage
Output Resistance
VREF
(VCC + 1)/2
250
V
Ω
−500 μA to +500 μA
TIMING CHARACTERISTICS
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
AC PERFORMANCE
Maximum Output Frequency
6.2
ꢀ.0
GHz
Differential output voltage swing > 0.8 V
(see Figure 4)
Output Rise/Fall Time
Propagation Delay
Temperature Coefficient
Output-to-Output Skew1
Part-to-Part Skew
tR
tPD
35
ꢀ0
50
100
ꢀ5
ꢀ5
130
ps
ps
fs/°C
ps
ps
20% to 80%, measured differentially
VID = 1.6 V p-p
15
35
VID = 1.6 V p-p
Additive Time Jitter
Integrated Random Jitter
Broadband Random Jitter2
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise
fIN = 1 GHz
26
50
fs rms
fs rms
BW = 12 kHz to 20 MHz, CLK = 1 GHz
VID = 1.6 V p-p, 8 V/ns, VICM = 2 V
Input slew rate > 1 V/ns (see Figure 11)
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
−118
−135
−144
−150
−150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
>1 MHz offset
1 The output-to-output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
2 Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
Rev. 0 | Page 3 of 12
ADCLK944
POWER
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Supply Voltage Requirement
Power Supply Current
Negative Supply Current
VCC − VEE
2.3ꢀ5
3.63
V
3.3 V + 10% to 2.5 V − 5%
Static
VCC − VEE = 2.5 V 5%
VCC − VEE = 3.3 V 10%
VCC − VEE = 2.5 V 5%
VCC − VEE = 3.3 V 10%
IVEE
IVEE
IVCC
IVCC
PSRVCC
PSRVCC
35
3ꢀ
139
138
−3
28
mA
mA
mA
mA
ps/V
dB
49
Positive Supply Current
165
Power Supply Rejection1
Output Swing Supply Rejection2
1 Change in tPD per change in VCC
2 Change in output swing per change in VCC.
.
Rev. 0 | Page 4 of 12
ADCLK944
ABSOLUTE MAXIMUM RATINGS
DETERMINING JUNCTION TEMPERATURE
Table 4.
To determine the junction temperature on the application
printed circuit board (PCB), use the following equation:
Parameter
Rating
Supply Voltage
VCC − VEE
Input Voltage
CLK, CLK
6.0 V
TJ = TCASE + (ΨJT × PD)
where:
VEE − 0.5 V to VCC + 0.5 V
TJ is the junction temperature (°C).
CLK to CLK
1.8 V
2 V
T
CASE is the case temperature (°C) measured by the customer at
the top center of the package.
JT is as indicated in Table 5.
Input Termination, VT to CLK, CLK
Input Current, CLK, CLK to VT Pin
(CML, LVPECL Termination)
Maximum Voltage on Output Pins
Maximum Output Current
Voltage Reference (VREF
Operating Temperature
Ambient Range
40 mA
Ψ
PD is the power dissipation.
VCC + 0.5 V
35 mA
VCC to VEE
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order approx-
imation of TJ using the following equation:
)
−40°C to +85°C
150°C
−65°C to +150°C
TJ = TA + (θJA × PD)
Junction
Storage Temperature Range
where TA is the ambient temperature (°C).
Values of θJB are provided in Table 5 for package comparison
and PCB design considerations.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
THERMAL PERFORMANCE
Table 5.
Parameter
Symbol
Description
Value1
Unit
Junction-to-Ambient Thermal Resistance
Still Air
0.0 m/sec Airflow
Moving Air
θJA
Per JEDEC JESD51-2
Per JEDEC JESD51-6
ꢀ8
°C/W
θJMA
1.0 m/sec Airflow
2.5 m/sec Airflow
68
61
°C/W
°C/W
Junction-to-Board Thermal Resistance
Moving Air
θJB
θJC
ΨJT
Per JEDEC JESD51-8
1.0 m/sec Airflow
49
°C/W
°C/W
°C/W
Junction-to-Case Thermal Resistance (Die-to-Heat Sink)
Still Air
Per MIL-STD-883, Method 1012.1
0.0 m/sec Airflow
1.5
Junction-to-Top-of-Package Characterization Parameter
Still Air
Per JEDEC JESD51-2
0.0 m/sec Airflow
2.0
1 Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the
application to determine whether they are similar to those assumed in these calculations.
Rev. 0 | Page 5 of 12
ADCLK944
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK 1
12 Q1
11 Q1
10 Q2
V
2
3
T
ADCLK944
TOP VIEW
(Not to Scale)
V
REF
CLK 4
9
Q2
NOTES
1. EXPOSED PAD MUST BE CONNECTED
TO V
.
EE
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLK
Differential Input (Positive).
2
VT
Center Tap. This pin provides the center tap of a 100 Ω input resistor for the CLK and CLK inputs.
3
VREF
Reference Voltage. This pin provides the reference voltage for biasing ac-coupled CLK and CLK inputs.
4
CLK
Differential Input (Negative).
Negative Supply Pin.
Differential LVPECL Outputs.
Positive Supply Pin.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
The exposed pad must be connected to VEE.
5, 16
6, ꢀ
8, 13
9, 10
11, 12
14, 15
VEE
Q3, Q3
VCC
Q2, Q2
Q1, Q1
Q0, Q0
EPAD
Rev. 0 | Page 6 of 12
ADCLK944
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0.0 V, VICM = VREF, TA = 25°C, clock outputs terminated at 50 Ω to VCC − 2 V, unless otherwise noted.
1
1
CH1 300mV
M 1.25ns 20.0GS/s IT 25.0ps/pt
A CH1 36.0mV
CH1 300mV
M 250ps 20.0GS/s
A CH1 36.0mV
IT 5.0ps/pt
Figure 3. LVPECL Differential Output Waveform at 200 MHz
Figure 6. LVPECL Differential Output Waveform at 1000 MHz
1.55
1.50
1.45
1.40
1.6
1.4
1.2
+25°C
+85°C
–40°C
3.3V
2.5V
1.0
0.8
0.6
0.4
0.2
0
1.35
1.30
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
0
1000
2000 3000
4000 5000
6000
7000 8000
POWER SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
Figure 4. Differential Output Voltage Swing vs. Frequency
Figure 7. Differential Output Voltage Swing vs. Power Supply Voltage
and Temperature, VID = 1.6 V p-p
80
140
130
120
85
90
95
DELAY 3.3V
110
2.5V
100
105
110
100
3.3V
DELAY 2.5V
90
115
0.1
80
1.0
0.3
0.5
0.7
0.9
1.1
1.5
2.0
2.5
3.0
– V
3.5
DIFFERENTIAL INPUT VOLTAGE SWING (V)
DC COMMON-MODE VOLTAGE (V
)
ICM
EE
Figure 5. Propagation Delay vs. Differential Input Voltage Swing
Figure 8. Propagation Delay vs. DC Common-Mode Voltage
Rev. 0 | Page ꢀ of 12
ADCLK944
160
140
120
100
80
300
250
200
150
100
50
I
VCC
–40°C
+25°C
+85°C
60
40
I
VEE
20
0
0
2.375
2.500
2.625
2.970
3.300
3.630
0
5
10
15
20
POWER SUPPLY VOLTAGE (V)
INPUT SLEW RATE (V/ns)
Figure 9. Power Supply Current vs. Power Supply Voltage and Temperature,
All Outputs Loaded (50 Ω to VCC − 2 V)
Figure 11. Random Jitter vs. Input Slew Rate, VID Method
–90
–100
–110
–120
–130
–140
ADCLK944
–150
–160
CLOCK SOURCE
–170
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
Figure 10. Absolute Phase Noise Measured at 1 GHz with Agilent E5052B
Rev. 0 | Page 8 of 12
ADCLK944
THEORY OF OPERATION
Figure 13 through Figure 16 depict various LVPECL output
termination schemes. When dc-coupled, VCC of the receiving
buffer should match VS_DRV.
CLOCK INPUTS
The ADCLK944 accepts a differential clock input and distrib-
utes it to all four LVPECL outputs. The maximum specified
frequency is the point at which the output voltage swing is 50%
of the standard LVPECL swing (see Figure 4).
VS_DRV
V
= VS_DRV
LVPECL
ADCLK944
CC
Z
= 50Ω
0
50Ω
50Ω
V
– 2V
CC
The device has a differential input equipped with center-tapped,
differential, 100 Ω on-chip termination resistors. The input can
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended,
3.3 V operation only), and ac-coupled 1.8 V CMOS, LVDS, and
LVPECL inputs. A VREF pin is available for biasing ac-coupled
inputs (see Figure 20 and Figure 21).
Z
= 50Ω
0
Figure 13. DC-Coupled, 3.3 V LVPECL
Thevenin-equivalent termination uses a resistor network to provide
50 Ω termination to a dc voltage that is below VOL of the LVPECL
driver. In this case, VS_DRV on the ADCLK944 should equal
Maintain the differential input voltage swing from approxi-
mately 400 mV p-p to no more than 3.4 V p-p. See Figure 18
through Figure 21 for various clock input termination schemes.
VCC of the receiving buffer. Although the resistor combination
shown in Figure 14 results in a dc bias point of VS_DRV − 2 V,
the actual common-mode voltage is VS_DRV − 1.3 V because
there is additional current flowing from the ADCLK944 LVPECL
driver through the pull-down resistor.
Output jitter performance is significantly degraded by an input
slew rate below 1 V/ns, as shown in Figure 11. The ADCLK944
is specifically designed to minimize added random jitter over a
wide input slew rate range. Whenever possible, clamp excessively
large input signals with fast Schottky diodes because attenuators
reduce the slew rate. Input signal runs of more than a few centi-
meters should be over low loss dielectrics or cables with good
high frequency characteristics.
VS_DRV
ADCLK944
VS_DRV
V
CC
127Ω
127Ω
50Ω
SINGLE-ENDED
(NOT COUPLED)
LVPECL
50Ω
CLOCK OUTPUTS
83Ω
83Ω
The specified performance necessitates using proper transmis-
sion line terminations. The LVPECL outputs of the ADCLK944
are designed to directly drive 800 mV into a 50 Ω cable or into
microstrip/stripline transmission lines terminated with 50 Ω
referenced to VCC − 2 V, as shown in Figure 13. The LVPECL
output stage is shown in Figure 12. The outputs are designed
for best transmission line matching. If high speed signals must
be routed more than a centimeter, either the microstrip or the
stripline technique is required to ensure proper transition times
and to prevent excessive output ringing and pulse-width-dependent
propagation delay dispersion.
Figure 14. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination
LVPECL Y-termination (see Figure 15) is an elegant termination
scheme that uses the fewest components and offers both odd-
and even-mode impedance matching. Even-mode impedance
matching is an important consideration for closely coupled trans-
mission lines at high frequencies. Its main drawback is that it offers
limited flexibility for varying the drive strength of the emitter-
follower LVPECL driver. This can be an important consideration
when driving long trace lengths but is usually not an issue.
VS_DRV
V
= VS_DRV
ADCLK944
CC
V
CC
Z
= 50Ω
= 50Ω
0
50Ω
50Ω
50Ω
LVPECL
Z
0
Figure 15. DC-Coupled, 3.3 V LVPECL Y-Termination
Q
Q
VS_DRV
V
ADCLK944
CC
0.1nF
100Ω DIFFERENTIAL
(COUPLED)
100Ω
LVPECL
0.1nF
TRANSMISSION LINE
200Ω
200Ω
V
EE
Figure 12. Simplified Schematic Diagram
of the LVPECL Output Stage
Figure 16. AC-Coupled LVPECL with Parallel Transmission Line
Rev. 0 | Page 9 of 12
ADCLK944
If the return is floated, the device exhibits a 100 ꢁ cross-termi-
nation, but the source must then control the common-mode
voltage and supply the input bias currents.
PCB LAYOUT CONSIDERATIONS
The ADCLK944 buffer is designed for very high speed applica-
tions. Consequently, high speed design techniques must be used
to achieve the specified performance. It is critically important to
use low impedance supply planes for both the negative supply
(VEE) and the positive supply (VCC) planes as part of a multilayer
board. Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.
ESD/clamp diodes between the input pins prevent the application
from developing excessive offsets to the input transistors. ESD
diodes are not optimized for best ac performance. When a clamp
is required, it is recommended that appropriate external diodes
be used.
Exposed Metal Paddle
The following references to the ground plane assume that the VEE
power plane is grounded for LVPECL operation. Note that, for
ECL operation, the VCC power plane becomes the ground plane.
The exposed metal paddle on the ADCLK944 package is both an
electrical connection and a thermal enhancement. For the device
to function properly, the paddle must be properly attached to
the VEE pins.
It is also important to adequately bypass the input and output
supplies. Place a 1 μF electrolytic bypass capacitor within several
inches of each VCC power supply pin to the ground plane. In
addition, place multiple high quality 0.001 ꢀF bypass capacitors
as close as possible to each VCC supply pin, and connect the
capacitors to the ground plane with redundant vias. Select high
frequency bypass capacitors for minimum inductance and ESR.
To improve the effectiveness of the bypass at high frequencies,
minimize parasitic layout inductance. Also, avoid discontinuities
along input and output transmission lines; such discontinuities
can affect jitter performance.
When properly mounted, the ADCLK944 also dissipates heat
through its exposed paddle. The PCB acts as a heat sink for the
ADCLK944. The PCB attachment must provide a good thermal
path to a larger heat dissipation area. This requires a grid of vias
from the top layer of the PCB down to the VEE power plane (see
Figure 17). The ADCLK944 evaluation board (ADCLK944/PCBZ)
provides an example of how to attach the part to the PCB.
In a 50 Ω environment, input and output matching have a signif-
icant impact on performance. The buffer provides internal 50 Ω
VIAS TO V POWER
EE
CLK
termination resistors for both the CLK and
inputs. Normally,
PLANE
the return side is connected to the reference pin that is provided.
Bypass the termination potential using ceramic capacitors to
prevent undesired aberrations on the input signal due to parasitic
inductance in the termination return path. If the inputs are dc-
coupled to a source, take care to ensure that the pins are within
the rated input differential and common-mode voltage ranges.
Figure 17. PCB Land for Attaching Exposed Paddle
Rev. 0 | Page 10 of 12
ADCLK944
INPUT TERMINATION OPTIONS
V
CC
V
V
REF
REF
V
V
T
T
50Ω
50Ω
50Ω
50Ω
CLK
CLK
CLK
CLK
CONNECT V TO V
.
CONNECT V TO V
.
REF
T
CC
T
Figure 18. Interfacing to CML Inputs
Figure 20. AC Coupling Differential Signal Inputs, Such as LVDS
V
REF
V
T
V
REF
50Ω
50Ω
V
T
CLK
50Ω
50Ω
V
– 2V
CC
CLK
CLK
CLK
CONNECT V , V
REF
, AND CLK TOGETHER.
T
PLACE A BYPASS CAPACITOR FROM V TO
T
GROUND.
CONNECT V TO V − 2V.
CC
T
ALTERNATIVELY, V , V
, AND CLK CAN BE
T
REF
CONNECTED TOGETHER, GIVING A CLEANER
LAYOUT AND A 180° PHASE SHIFT.
Figure 21. Interfacing to AC-Coupled, Single-Ended Inputs
Figure 19. Interfacing to PECL Inputs
Rev. 0 | Page 11 of 12
ADCLK944
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.60
1.50 SQ
1.40
9
8
5
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 22. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-18)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADCLK944BCPZ-R2
ADCLK944BCPZ-Rꢀ
ADCLK944BCPZ-WP
ADCLK944/PCBZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
Evaluation Board
Package Option
CP-16-18
CP-16-18
Branding Code
Y2K
Y2K
Y2K
CP-16-18
1 Z = RoHS Compliant Part.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08770-0-3/10(0)
Rev. 0 | Page 12 of 12
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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