ADCLK946BCPZ [ADI]
Six LVPECL Outputs, SiGe Clock Fanout Buffer; 六LVPECL输出的SiGe时钟扇出缓冲器
| 型号： | ADCLK946BCPZ |
| 厂家： | 
ADI |
| 描述： | Six LVPECL Outputs, SiGe Clock Fanout Buffer |
| 文件： | 总12页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Six LVPECL Outputs,
SiGe Clock Fanout Buffer
ADCLK946
FUNCTIONAL BLOCK DIAGRAM
FEATURES
4.8 GHz operating frequency
75 fs rms broadband random jitter
On-chip input terminations
3.3 V power supply
LVPECL
ADCLK946
Q0
Q0
V
REFERENCE
REF
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
V
T
APPLICATIONS
CLK
CLK
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
Figure 1.
The ADCLK946 is an ultrafast clock fanout buffer fabricated on
the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The device has a differential input equipped with center-tapped,
differential, 100 Ω on-chip termination resistors. The input accepts
dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and
ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin
is available for biasing ac-coupled inputs.
The ADCLK946 features six full-swing emitter-coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to VCC − 2 V for a total differen-
tial output swing of 1.6 V.
The ADCLK946 is available in a 24-lead LFCSP and is specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
ADCLK946
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Performance...................................................................5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
Functional Description.....................................................................9
Clock Inputs...................................................................................9
Clock Outputs................................................................................9
PCB Layout Considerations...................................................... 10
Input Termination Options....................................................... 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 5
Determining Junction Temperature .......................................... 5
ESD Caution.................................................................................. 5
REVISION HISTORY
4/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADCLK946
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (typ) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values
are given over the full VCC − VEE = 3.3 V 10ꢀ and TA = −40°C to +85°C variation, unless otherwise noted.
Table 1. Clock Inputs and Outputs
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input Voltage High Level
Input Voltage Low Level
Input Differential Range
Input Capacitance
VIH
VIL
VID
CIN
VEE + 1.6
VEE
0.4
VCC
VCC − 0.2
3.4
V
V
V p-p
pF
1.ꢀ V between input pins
0.4
Input Resistance
Single-Ended Mode
Differential Mode
Common Mode
Input Bias Current
Hysteresis
50
100
50
20
10
Ω
Ω
kΩ
μA
mV
Open VT
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
Output Voltage Low Level
Output Voltage Differential
Reference Voltage
VOH
VOL
VOD
VREF
VCC − 1.26
VCC − 1.99
610
VCC − 0.ꢀ6
VCC − 1.54
960
V
V
mV
50 Ω to (VCC − 2.0 V)
50 Ω to (VCC − 2.0 V)
50 Ω to (VCC − 2.0 V)
Output Voltage
Output Resistance
(VCC + 1)/2
235
V
Ω
−500 μA to +500 μA
Table 2. Timing Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
AC PERFORMANCE
Maximum Output Frequency
4.5
4.8
GHz
See Figure 4 for differential output voltage vs.
frequency, >0.8 V differential output swing
Output Rise/Fall Time
Propagation Delay
Temperature Coefficient
Output-to-Output Skew
Part-to-Part Skew1
tR, tF
tPD
40
150
ꢀ5
185
50
9
90
220
ps
ps
fs/°C
ps
ps
20% to 80% measured differentially
VICM = 2 V, VID = 1.6 V p-p
28
45
VID = 1.6 V p-p
Additive Time Jitter
Integrated Random Jitter
Broadband Random Jitter2
Crosstalk-Induced Jitter3
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise
fIN = 1 GHz
28
ꢀ5
90
fs rms
fs rms
fs rms
BW = 12 kHz − 20 MHz, CLK = 1 GHz
VID = 1.6 V p-p, 8 V/ns, VICM = 2 V
Input slew rate > 1 V/ns (see Figure 11 for more details)
−119
−134
−145
−150
−150
dBc/Hz @ 100 Hz offset
dBc/Hz @ 1 kHz offset
dBc/Hz @ 10 kHz offset
dBc/Hz @ 100 kHz offset
dBc/Hz >1 MHz offset
1 The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
2 Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
3 The amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.
Rev. 0 | Page 3 of 12
ADCLK946
Table 3. Power
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Supply Voltage Requirement
Power Supply Current
Negative Supply Current
Positive Supply Current
Power Supply Rejection1
Output Swing Supply Rejection2
VCC − VEE 2.9ꢀ
3.63
V
3.3 V + 10%
Static
VCC − VEE = 3.3 V 10%
VCC − VEE = 3.3 V 10%
VCC − VEE = 3.3 V 10%
VCC − VEE = 3.3 V 10%
IVEE
IVCC
PSRVCC
PSRVCC
90
115
2ꢀ5
mA
mA
ps/V
dB
245
<3
28
1 Change in tPD per change in VCC
2 Change in output swing per change in VCC
.
.
Rev. 0 | Page 4 of 12
ADCLK946
ABSOLUTE MAXIMUM RATINGS
DETERMINING JUNCTION TEMPERATURE
Table 4.
To determine the junction temperature on the application
printed circuit board (PCB), use the following equation:
Parameter
Supply Voltage
VCC − VEE
Input Voltage
CLK, CLK
Rating
6.0 V
TJ = TCASE + (ΨJT × PD)
where:
VEE − 0.5 V to
VCC + 0.5 V
TJ is the junction temperature (°C).
T
CASE is the case temperature (°C) measured by the customer at
CLK, CLK to VT Pin (CML, LVPECL
Termination)
CLK to CLK
±±0 mꢀ
the top center of the package.
ΨJT is as indicated in Table 5.
PD is the power dissipation.
±1.ꢁ V
Input Termination, VT to CLK, CLK
Maximum Voltage on Output Pins
Maximum Output Current
±2 V
VCC + 0.5 V
35 mꢀ
VCC to VEE
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order approx-
imation of TJ by the equation
Voltage Reference (VREF
)
Operating Temperature Range
ꢀmbient
Junction
TJ = TA + (θJA × PD)
−±0°C to +ꢁ5°C
150°C
where TA is the ambient temperature (°C).
Storage Temperature Range
−65°C to +150°C
Values of θJB are provided in Table 5 for package comparison
and PCB design considerations.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
THERMAL PERFORMANCE
Table 5.
Parameter
Symbol
Description
Value1
Unit
Junction-to-ꢀmbient Thermal Resistance
Still ꢀir
0.0 m/sec ꢀirflow
Per JEDEC JESD51-2
5±.3
°C/W
θJꢀ
Moving ꢀir
1.0 m/sec ꢀirflow
Per JEDEC JESD51-6
Per JEDEC JESD51-6
±7.5
±2.6
°C/W
°C/W
θJMꢀ
θJMꢀ
2.5 m/sec ꢀirflow
Junction-to-Board Thermal Resistance
Moving ꢀir
1.0 m/sec ꢀirflow
Per JEDEC JESD51-ꢁ (moving air)
Per MIL-Std. ꢁꢁ3, Method 1012.1
33.0
2.0
°C/W
°C/W
θJB
θJC
Junction-to-Case Thermal Resistance (Die-to-Heat Sink)
Moving ꢀir
Junction-to-Top-of-Package Characterization Parameter
Still ꢀir
0 m/sec ꢀirflow
Per JEDEC JESD51-2
0.9
°C/W
ΨJT
1Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the
application to determine if they are similar to those assumed in these calculations.
Rev. 0 | Page 5 of 12
ADCLK946
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
V
CLK
CLK
1
2
3
4
5
6
18 V
EE
CC
17 Q2
16 Q2
15 Q3
14 Q3
ADCLK946
V
TOP VIEW
REF
V
V
(Not to Scale)
T
13 V
EE
CC
NOTES:
1. EXPOSED PADDLE MUST BE CONNECTED TO V
.
EE
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1, 6, ꢀ, 12, 19
2
Mnemonic
Description
VEE
CLK
CLK
Negative Supply Pin.
Differential Input (Positive).
Differential Input (Negative).
3
4
VREF
Reference Voltage. This pin provides the reference voltage for biasing ac-coupled CLK and CLK inputs.
5
VT
Center Tap. This pin provides the center tap of a 100 Ω input resistor for CLK and CLK inputs.
Differential LVPECL Outputs.
8, 9
Q5, Q5
Q4, Q4
VCC
Q3, Q3
Q2, Q2
Q1, Q1
Q0, Q0
EPAD
10, 11
13, 18, 24
14, 15
16, 1ꢀ
20, 21
22, 23
Differential LVPECL Outputs.
Positive Supply Pin.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
EPAD must be soldered to VEE.
Rev. 0 | Page 6 of 12
ADCLK946
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0.0 V, VICM = VREF, TA = 25°C, clock outputs terminated at 50 Ω to VCC − 2 V, unless otherwise noted.
C4
C3
C4
C3
C4
C3
100mV/DIV
500ps/DIV
100mV/DIV
100ps/DIV
Figure 3. LVPECL Output Waveform @ 200 MHz
Figure 6. LVPECL Output Waveform @ 1000 MHz
1.8
189
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
188
187
186
185
184
183
182
0
1000
2000
3000
4000
5000
–40
–20
0
20
40
60
80
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 4. Differential Output Swing vs. Frequency
Figure 7. Propagation Delay vs. Temperature
205
200
195
190
185
180
175
170
165
160
205
195
185
175
165
+85°C
+25°C
–40°C
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1
DIFFERENTIAL INPUT VOLTAGE SWING (V)
DC COMMON-MODE VOLTAGE (V)
Figure 5. Propagation Delay vs. Differential Input Voltage
Figure 8. Propagation Delay vs. Common-Mode Voltage vs. Temperature,
Input Slew Rate > 25 V/ns
Rev. 0 | Page ꢀ of 12
ADCLK946
1.56
1.54
1.52
1.50
1.48
1.46
1.44
1.42
–90
–100
–110
–120
–130
–140
–150
–160
–170
–40°C
+25°C
+85°C
ADCLK946
CLOCK SOURCE
2.75 2.85 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 3.75
10
100
1k
10k
100k
1M
10M
100M
POWER SUPPLY (V)
FREQUENCY OFFSET (Hz)
Figure 9. Differential Output Swing vs. Power Supply Voltage vs. Temperature,
VID = 1.6 V p-p
Figure 11. Absolute Phase Noise Measured @1 GHz with Agilent E5052
300
250
200
150
100
50
300
I
VCC
250
200
150
100
50
+85°C
+25°C
–40°C
I
VEE
0
0
0
5
10
15
20
25
2.97
3.30
POWER SUPPLY (V)
3.63
INPUT SLEW RATE (V/ns)
Figure 12. RMS Jitter vs. Input Slew Rate, VID Method
Figure 10. Power Supply Current vs. Power Supply Voltage vs. Temperature,
All Outputs Loaded (50 Ω to VCC − 2 V)
Rev. 0 | Page 8 of 12
ADCLK946
FUNCTIONAL DESCRIPTION
Thevenin-equivalent termination uses a resistor network to
CLOCK INPUTS
provide 50 Ω termination to a dc voltage that is below VOL of
the LVPECL driver. In this case, VS_DRV on the ADCLK946
should equal VCC of the receiving buffer. Although the resistor
combination shown in Figure 15 results in a dc bias point of
VS_DRV − 2 V, the actual common-mode voltage is VS_DRV −
1.3 V because there is additional current flowing from the
ADCLK946 LVPECL driver through the pull-down resistor.
The ADCLK946 accepts a differential clock input and distributes it
to all six LVPECL outputs. The maximum specified frequency is
the point at which the output voltage swing is 50ꢀ of the standard
LVPECL swing (see Figure 4).
The device has a differential input equipped with center-tapped,
differential, 100 Ω on-chip termination resistors. The input accepts
dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and
ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin
is available for biasing ac-coupled inputs (see Figure 1).
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue.
Maintain the differential input voltage swing from approximately
400 mV p-p to no more than 3.4 V p-p. See Figure 14 through
Figure 17 for various clock input termination schemes.
Output jitter performance is degraded by an input slew rate
below 1 V/ns, as shown in Figure 12. The ADCLK946 is
specifically designed to minimize added random jitter over a
wide input slew rate range. Whenever possible, clamp excessively
large input signals with fast Schottky diodes because attenuators
reduce the slew rate. Input signal runs of more than a few
centimeters should be over low loss dielectrics or cables with
good high frequency characteristics.
VS_DRV
V
= VS_DRV
ADCLK946
S
Z
= 50Ω
= 50Ω
0
50Ω
50Ω
V
– 2V
LVPECL
CC
Z
0
Figure 14. DC-Coupled, 3.3 V LVPECL
CLOCK OUTPUTS
VS_DRV
The specified performance necessitates using proper trans-
mission line terminations. The LVPECL outputs of the
ADCLK946 are designed to directly drive 800 mV into a 50 Ω
cable or into microstrip/stripline transmission lines terminated
with 50 Ω referenced to VCC − 2 V, as shown in Figure 14. The
LVPECL output stage is shown in Figure 13. The outputs are
designed for best transmission line matching. If high speed
signals must be routed more than a centimeter, either the
microstrip or the stripline technique is required to ensure
proper transition times and to prevent excessive output ringing
and pulse-width-dependent, propagation delay dispersion.
ADCLK946
VS_DRV
V
CC
127Ω
127Ω
50Ω
SINGLE-ENDED
(NOT COUPLED)
LVPECL
50Ω
83Ω
83Ω
Figure 15. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination
VS_DRV
V
= VS_DRV
ADCLK946
S
Z
= 50Ω
0
V
CC
50Ω
50Ω
50Ω
LVPECL
Z
= 50Ω
0
Figure 16. DC-Coupled, 3.3 V LVPECL Y-Termination
Q
Q
VS_DRV
V
ADCLK946
CC
0.1nF
100Ω DIFFERENTIAL
(COUPLED)
100Ω
LVPECL
0.1nF
TRANSMISSION LINE
200Ω
200Ω
V
EE
Figure 13. Simplified Schematic Diagram of
the LVPECL Output Stage
Figure 17. AC-Coupled, LVPECL with Parallel Transmission Line
Figure 14 through Figure 17 depict various LVPECL output
termination schemes. When dc-coupled, VCC of the receiving
buffer should match the VS_DRV.
Rev. 0 | Page 9 of 12
ADCLK946
ensure that the pins are within the rated input differential and
common-mode ranges.
PCB LAYOUT CONSIDERATIONS
The ADCLK946 buffer is designed for very high speed
applications. Consequently, high speed design techniques must
be used to achieve the specified performance. It is critically
important to use low impedance supply planes for both the
negative supply (VEE) and the positive supply (VCC) planes as
part of a multilayer board. Providing the lowest inductance
return path for switching currents ensures the best possible
performance in the target application.
If the return is floated, the device exhibits a 100 ꢁ cross-
termination, but the source must then control the common-
mode voltage and supply the input bias currents.
There are ESD/clamp diodes between the input pins to prevent
the application from developing excessive offsets to the input
transistors. ESD diodes are not optimized for best ac perfor-
mance. When a clamp is required, it is recommended that
appropriate external diodes be used.
The following references to the ground plane assume that
the VEE power plane is grounded for LVPECL operation.
Note that, for ECL operation, the VCC power plane becomes
the ground plane.
Exposed Metal Paddle
The exposed metal paddle on the ADCLK946 package is both
an electrical connection and a thermal enhancement. For the
device to function properly, the paddle must be properly
attached to the VEE pin.
It is also important to adequately bypass the input and output
supplies. Place a 1 μF electrolytic bypass capacitor within several
inches of each VCC power supply pin to the ground plane. In
addition, place multiple high quality 0.001 μF bypass capacitors
as close as possible to each of the VCC supply pins, and connect
the capacitors to the ground plane with redundant vias.
Carefully select high frequency bypass capacitors for minimum
inductance and ESR. To improve the effectiveness of the bypass
at high frequencies, minimize parasitic layout inductance. Also,
avoid discontinuities along input and output transmission lines
that can affect jitter performance.
When properly mounted, the ADCLK946 also dissipates heat
through its exposed paddle. The PCB acts as a heat sink for the
ADCLK946. The PCB attachment must provide a good thermal
path to a larger heat dissipation area. This requires a grid of vias
from the top layer down to the VEE power plane (see Figure 18).
The ADCLK946 evaluation board (ADCLK946/PCBZ)
provides an example of how to attach the part to the PCB.
In a 50 Ω environment, input and output matching have a
significant impact on performance. The buffer provides internal
CLK
50 Ω termination resistors for both CLK and
inputs.
VIAS TO V POWER
EE
Normally, the return side is connected to the reference pin that is
provided. Carefully bypass the termination potential using
ceramic capacitors to prevent undesired aberrations on the
input signal due to parasitic inductance in the termination
return path. If the inputs are dc-coupled to a source, take care to
PLANE
Figure 18. PCB Land for Attaching Exposed Paddle
Rev. 0 | Page 10 of 12
ADCLK946
INPUT TERMINATION OPTIONS
V
CC
V
V
REF
REF
V
V
T
T
50Ω
50Ω
50Ω
50Ω
CLK
CLK
CLK
CLK
CONNECT V TO V
CC
.
CONNECT V TO V
.
REF
T
T
Figure 19. Interfacing to CML Inputs
Figure 21. AC-Coupling Differential Signals Inputs, Such as LVDS
V
REF
V
T
50Ω
50Ω
V
REF
CLK
V
T
CLK
50Ω
50Ω
V
– 2V
CC
CLK
CLK
CONNECT V , V
, AND CLK. PLACE A BYPASS
CAPACITOR FROM V TO GROUND.
T
REF
T
ALTERNATIVELY, V , V
, AND CLK CAN BE
T
REF
CONNECTED, GIVING A CLEANER LAYOUT AND
A 180° PHASE SHIFT.
CONNECT V TO V − 2V.
CC
T
Figure 20. Interfacing to PECL Inputs
Figure 22. Interfacing to AC-Coupled Single-Ended Inputs
Rev. 0 | Page 11 of 12
ADCLK946
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
0.50
BSC
PIN 1
INDICATOR
*
2.45
2.30 SQ
2.15
TOP
VIEW
3.75
BSC SQ
EXPOSED
PA D
(BOTTOMVIEW)
0.50
0.40
0.30
6
13
12
7
0.23 MIN
0.80 MAX
0.65 TYP
1.00
0.85
0.80
2.50 REF
12° MAX
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
SECTION OF THIS DATA SHEET.
*
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 23. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
CP-24-2
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADCLK946BCPZ1
ADCLK946BCPZ-REELꢀ1
ADCLK946/PCBZ1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Evaluation Board
Package Option
CP-24-2
CP-24-2
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08053-0-4/09(0)
Rev. 0 | Page 12 of 12
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