ADCLK948BCPZ-REEL7 [ADI]

Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer; 两个可选的输入，8个LVPECL输出的SiGe时钟扇出缓冲器


型号：	ADCLK948BCPZ-REEL7
厂家：	ADI
描述：	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer 两个可选的输入，8个LVPECL输出的SiGe时钟扇出缓冲器时钟驱动器逻辑集成电路 PC
文件：	总12页 (文件大小：366K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Two Selectable Inputs, 8 LVPECL Outputs,

SiGe Clock Fanout Buffer

ADCLK948

FEATURES

FUNCTIONAL BLOCK DIAGRAM

LVPECL

2 selectable differential inputs

4.8 GHz operating frequency

75 fs rms broadband random jitter

On-chip input terminations

3.3 V power supply

ADCLK948

APPLICATIONS

Low jitter clock distribution

Clock and data signal restoration

Level translation

REFERENCE

Wireless communications

REF

Wired communications

Medical and industrial imaging

ATE and high performance instrumentation

V 0

CLK0

GENERAL DESCRIPTION

The ADCLK948 is an ultrafast clock fanout buffer fabricated

on the Analog Devices, Inc., proprietary XFCB3 silicon german-

ium (SiGe) bipolar process. This device is designed for high

speed applications requiring low jitter.

V 1

CLK1

The device has two selectable differential inputs via the IN_SEL

control pin. Both inputs are equipped with center tapped,

differential, 100 Ω on-chip termination resistors. The inputs

accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),

and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A

IN_SEL

REFERENCE

REF

_REFx pin is available for biasing ac-coupled inputs.

Figure 1.

The ADCLK948 features eight full-swing emitter coupled logic

(ECL) output drivers. For LVPECL (positive ECL) operation,

bias V_CCto the positive supply and V_EEto ground. For ECL

operation, bias V_CCto ground and V_EEto the negative supply.

The output stages are designed to directly drive 800 mV each

side into 50 Ω terminated to V_CC− 2 V for a total differential

output swing of 1.6 V.

The ADCLK948 is available in a 32-lead LFCSP and specified

for operation over the standard industrial temperature range of

−40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADCLK948

TABLE OF CONTENTS

Features .............................................................................................. 1

Pin Configuration and Function Descriptions..............................6

Typical Performance Characteristics ..............................................7

Functional Description.....................................................................9

Clock Inputs...................................................................................9

Clock Outputs................................................................................9

Clock Input Select (IN_SEL) Settings...................................... 10

PCB Layout Considerations...................................................... 10

Input Termination Options....................................................... 11

Outline Dimensions....................................................................... 12

Ordering Guide .......................................................................... 12

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Absolute Maximum Ratings............................................................ 5

Determining Junction Temperature .......................................... 5

ESD Caution.................................................................................. 5

Thermal Performance.................................................................. 5

REVISION HISTORY

7/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 12

ADCLK948

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Typical (Typ column) values are given for V_CC− V_EE= 3.3 V and T_A= 25°C, unless otherwise noted. Minimum (Min column) and maximum

(Max column) values are given over the full V_CC− V_EE= 3.3 V 10ꢀ and T_A= −40°C to +85°C variation, unless otherwise noted.

Table 1. Clock Inputs and Outputs

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

DC INPUT CHARACTERISTICS

Input Common Mode Voltage V_ICM

V_EE+ 1.5

0.4

V_CC− 0.1

3.4

V p-p

Input Differential Range

Input Capacitance

V_ID

C_IN

1.ꢀ V between input pins

0.4

Input Resistance

Single-Ended Mode

Differential Mode

Common Mode

Input Bias Current

Hysteresis

100

kΩ

μA

Open V_Tx

DC OUTPUT CHARACTERISTICS

Output Voltage High Level

Output Voltage Low Level

Output Voltage Differential

Reference Voltage

V_OH

V_OL

V_OD

V_REF

V_CC− 1.26

V_CC− 1.99

610

V_CC− 0.ꢀ6

V_CC− 1.54

960

50 Ω to (V_CC− 2.0 V)

Output Voltage

Output Resistance

(V_CC+ 1)/2

235

−500 μA to +500 μA

Table 2. Timing Characteristics

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

AC PERFORMANCE

Maximum Output Frequency

4.5

4.8

GHz

See Figure 4 for differential output voltage

vs. frequency, >0.8 V differential output

swing

Output Rise Time

Output Fall Time

Propagation Delay

Temperature Coefficient

Output-to-Output Skew¹

Part-to-Part Skew

t_R

t_F

t_PD

1ꢀ5

ꢀ5

210

245

fs/°C

20% to 80% measured differentially

V_ICM= 2 V, V_ID= 1.6 V p-p

V_ID= 1.6 V p-p

Additive Time Jitter

Integrated Random Jitter

Broadband Random Jitter²

Crosstalk-Induced Jitter³

CLOCK OUTPUT PHASE NOISE

Absolute Phase Noise

ꢀ5

fs rms

BW = 12 kHz − 20 MHz, CLK = 1 GHz

V_ID= 1.6 V p-p, 8 V/ns, V_ICM= 2 V

Input slew rate > 1 V/ns (see Figure 11, the

phase noise plot, for more details)

f_IN= 1 GHz

−119

−134

−145

−150

dBc/Hz @100 Hz offset

dBc/Hz @1 kHz offset

dBc/Hz @10 kHz offset

dBc/Hz @100 kHz offset

dBc/Hz >1 MHz offset

¹The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.

²Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.

³This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.

Rev. 0 | Page 3 of 12

ADCLK948

Table 3. Input Select Control Pin

Parameter

Symbol

Min

Typ

Max

V_CC

100

0.6

Unit

ꢁA

Logic 1 Voltage

Logic 0 Voltage

Logic 1 Current

Logic 0 Current

V_IH

V_IL

I_IH

V_CC− 0.4

V_EE

I_IL

Capacitance

Table 4. Power

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

POWER SUPPLY

Supply Voltage Requirement

Power Supply Current

Negative Supply Current

Positive Supply Current

Power Supply Rejection¹

Output Swing Supply Rejection²

V_CC− V_EE2.9ꢀ

3.63

3.3 V + 10%

Static

V_CC− V_EE= 3.3 V 10%

I_VEE

I_VCC

PSR_VCC

120

330

ps/V

288

¹Change in t_PDper change in V_CC

²Change in output swing per change in V_CC.

Rev. 0 | Page 4 of 12

ADCLK948

ABSOLUTE MAXIMUM RATINGS

DETERMINING JUNCTION TEMPERATURE

Table 5.

To determine the junction temperature on the application

printed circuit board (PCB), use the following equation:

Parameter

Rating

Supply Voltage

V_CC− V_EE

Input Voltage

CLK0, CLK1, CLK0, CLK1, IN_SEL

6 V

T_J= T_CASE+ (Ψ_JT× P_D)

where:

V_EE− 0.5 V to

V_CC+ 0.5 V

T_Jis the junction temperature (°C).

_CASEis the case temperature (°C) measured by the customer at

CLK0, CLK1, CLK0, CLK1 to V_Tx Pin (CML,

LVPECL Termination)

40 mA

the top center of the package.

Ψ_JTis from Table 6.

P_Dis the power dissipation.

CLK0, CLK1 to CLK0, CLK1

1.8 V

2 V

Input Termination, V_Tx to CLK0, CLK1, CLK0,

and CLK1

Values of θ_JAare provided for package comparison and PCB

design considerations. θ_JAcan be used for a first-order approxi-

mation of T_Jby the equation

Maximum Voltage on Output Pins

Maximum Output Current

Voltage Reference (V_REFx)

Operating Temperature Range

Ambient

V_CC+ 0.5 V

35 mA

V_CCto V_EE

T_J= T_A+ (θ_JA× P_D)

−40°C to +85°C

150°C

−65°C to +150°C

where T_Ais the ambient temperature (°C).

Junction

Storage Temperature Range

Values of θ_JBare provided in Table 6 for package comparison

and PCB design considerations.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

THERMAL PERFORMANCE

Table 6.

Parameter

Symbol

Description

Value¹

Unit

Junction-to-Ambient Thermal Resistance

θ_JA

Still Air

0 m/sec Air Flow

Moving Air

Per JEDEC JESD51-2

Per JEDEC JESD51-6

49.8

°C/W

θ_JMA

1 m/sec Air Flow

2.5 m/sec Air Flow

43.5

39.0

°C/W

Junction-to-Board Thermal Resistance

Moving Air

θ_JB

Per JEDEC JESD51-8

1 m/sec Air Flow

Junction-to-Case Thermal Resistance

Moving Air

Die-to-Heatsink

Junction-to-Top-of-Package Characterization Parameter

Still Air

30.ꢀ

8.8

°C/W

θ_JC

Per MIL-STD 883, Method 1012.1

Per JEDEC JESD51-2

Ψ_JT

0 m/sec Air Flow

0.ꢀ

¹Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the

application to determine if they are similar to those assumed in these calculations.

Rev. 0 | Page 5 of 12

ADCLK948

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK0

24 Q2

23 Q2

22 Q3

21 Q3

20 Q4

19 Q4

18 Q5

17 Q5

PIN 1

INDICATOR

REF

V 0

ADCLK948

CLK1

TOP VIEW

(Not to Scale)

V 1

REF

NOTES

1. NC = NO CONNECT.

2. EPAD MUST BE SOLDERED TO V POWER PLANE.

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

CLK0

Differential Input (Positive) 0.

CLK0

Differential Input (Negative) 0.

V_REF

V_T0

Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0 inputs.

Center Tap. Center tap of a 100 Ω input resistor for CLK0 and CLK0 inputs.

Differential Input (Positive) 1.

CLK1

V_T1

Differential Input (Negative) 1.

ꢀ

Center Tap. Center tap of a 100 Ω input resistor for CLK1 and CLK1 inputs.

Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1 inputs.

No Connection.

Positive Supply Pin.

Differential LVPECL Outputs.

V_REF

V_CC

10, 15, 16, 25, 26, 31

11, 12

Qꢀ, Qꢀ

Q6, Q6

Q5, Q5

Q4, Q4

Q3, Q3

Q2, Q2

Q1, Q1

Q0, Q0

IN_SEL

EPAD

13, 14

Differential LVPECL Outputs.

1ꢀ, 18

Differential LVPECL Outputs.

19, 20

Differential LVPECL Outputs.

21, 22

Differential LVPECL Outputs.

23, 24

Differential LVPECL Outputs.

2ꢀ, 28

Differential LVPECL Outputs.

29, 30

Differential LVPECL Outputs.

Input Select. Logic 0 selects CLK0 and CLK0 inputs. Logic 1 selects CLK1 and CLK1 inputs.

EPAD must be connected to V_EE.

(33)

Rev. 0 | Page 6 of 12

ADCLK948

TYPICAL PERFORMANCE CHARACTERISTICS

V_CC= 3.3 V, V_EE= 0 V, V_ICM= V_REFx, T_A= 25°C, clock outputs terminated at 50 Ω to V_CC− 2 V, unless otherwise noted.

100mV/DIV

500ps/DIV

100mV/DIV

100ps/DIV

Figure 3. LVPECL Output Waveform @ 200 MHz

Figure 6. LVPECL Output Waveform @ 1000 MHz

1.8

214

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

213

212

211

210

209

208

207

1000

2000

3000

4000

5000

–40

–20

FREQUENCY (MHz)

TEMPERATURE (°C)

Figure 4. Differential Output Voltage vs. Frequency, V_ID> 1.1 V p-p

Figure 7. Propagation Delay vs. Temperature, V_ID= 1.6 V p-p

225

220

215

210

205

200

195

190

185

180

230

220

210

200

190

+85°C

+25°C

–40°C

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1

DIFFERENTIAL INPUT VOLTAGE SWING (V)

DC COMMON-MODE VOLTAGE (V)

Figure 5. Propagation Delay vs. Differential Input Voltage

Figure 8. Propagation Delay vs. DC Common-Mode Voltage vs. Temperature,

Input Slew Rate > 25 V/ns

Rev. 0 | Page ꢀ of 12

ADCLK948

1.56

1.54

1.52

1.50

1.48

1.46

1.44

1.42

–90

–100

–110

–120

–130

–140

–150

–160

–170

ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT

E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A

WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672),

WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A

WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D).

–40°C

+25°C

+85°C

ADCLK948

CLOCK SOURCE

2.75 2.85 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 3.75

100

10k

100k

10M

100M

POWER SUPPLY (V)

FREQUENCY OFFSET (Hz)

Figure 9. Differential Output Voltage Swing vs. Power Supply Voltage vs.

Temperature, V_ID= 1.6 V p-p

Figure 11. Absolute Phase Noise Measured @1 GHz

300

250

200

150

100

350

ICC

300

250

200

+85°C

+25°C

–40°C

150

100

IEE

2.75

3.00

3.25

3.50

3.75

INPUT SLEW RATE (V/ns)

SUPPLY VOLTAGE (V)

Figure 12. RMS Random Jitter vs. Input Slew Rate, V_IDMethod

Figure 10. Power Supply Current vs. Power Supply Voltage vs. Temperature,

All Outputs Loaded (50 Ω to V_CC− 2 V).

Rev. 0 | Page 8 of 12

ADCLK948

FUNCTIONAL DESCRIPTION

Thevenin-equivalent termination uses a resistor network to

CLOCK INPUTS

provide 50 Ω termination to a dc voltage that is below V_OLof

the LVPECL driver. In this case, VS_DRV on the ADCLK948

should equal V_Sof the receiving buffer. Although the resistor

combination shown (in Figure 15) results in a dc bias point of

VS_DRV − 2 V, the actual common-mode voltage is VS_DRV −

1.3 V because there is additional current flowing from the

ADCLK948 LVPECL driver through the pull-down resistor.

The ADCLK948 accepts a differential clock input from one of

two inputs and distributes the selected clock to all eight LVPECL

outputs. The maximum specified frequency is the point at which

the output voltage swing is 50ꢀ of the standard LVPECL swing

(see Figure 4). See the functional block diagram (Figure 1) and

the General Description section for more clock input details.

See Figure 19 through Figure 23 for various clock input

termination schemes.

LVPECL Y-termination is an elegant termination scheme that

uses the fewest components and offers both odd- and even-mode

impedance matching. Even-mode impedance matching is an

important consideration for closely coupled transmission lines

at high frequencies. Its main drawback is that it offers limited

flexibility for varying the drive strength of the emitter follower

LVPECL driver. This can be an important consideration when

driving long trace lengths but is usually not an issue.

Output jitter performance is degraded by an input slew rate

below 4 V/ns, as shown in Figure 12. The ADCLK948 is

specifically designed to minimize added random jitter over a

wide input slew rate range. Whenever possible, clamp excessively

large input signals with fast Schottky diodes because attenuators

reduce the slew rate. Input signal runs of more than a few

centimeters should be over low loss dielectrics or cables with

good high frequency characteristics.

VS_DRV

= VS_DRV

ADCLK948

= 50Ω

CLOCK OUTPUTS

50Ω

– 2V

LVPECL

The specified performance necessitates using proper transmission

line terminations. The LVPECL outputs of the ADCLK948 are

designed to directly drive 800 mV into a 50 Ω cable or into

microstrip/stripline transmission lines terminated with 50 ꢁ

referenced to V_CC− 2 V, as shown in Figure 14. The LVPECL

output stage is shown in Figure 13. The outputs are designed for

best transmission line matching. If high speed signals must be

routed more than a centimeter, either the microstrip or the

stripline technique is required to ensure proper transition times

and to prevent excessive output ringing and pulse width depen-

dent propagation delay dispersion.

Figure 14. DC-Coupled, 3.3 V LVPECL

VS_DRV

ADCLK948

VS_DRV

127Ω

50Ω

SINGLE-ENDED

(NOT COUPLED)

LVPECL

50Ω

83Ω

Figure 15. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination

VS_DRV

= VS_DRV

ADCLK948

= 50Ω

50Ω

LVPECL

= 50Ω

Figure 16. DC-Coupled, 3.3 V LVPECL Y-Termination

VS_DRV

ADCLK948

0.1nF

Figure 13. Simplified Schematic Diagram of the LVPECL Output Stage

100Ω DIFFERENTIAL

(COUPLED)

100Ω

LVPECL

Figure 14 through Figure 17 depict various LVPECL output

termination schemes. When dc-coupled, V_Sof the receiving buffer

should match VS_DRV.

0.1nF

TRANSMISSION LINE

200Ω

Figure 17. AC-Coupled, LVPECL with Parallel Transmission Line

Rev. 0 | Page 9 of 12

ADCLK948

return path. If the inputs are dc-coupled to a source, take care to

ensure that the pins are within the rated input differential and

common-mode ranges.

CLOCK INPUT SELECT (IN_SEL) SETTINGS

A Logic 0 on the IN_SEL pin selects the Input CLK0 and

Input

. A Logic 1 on the IN_SEL pin selects Input CLK1

CLK0

If the return is floated, the device exhibits a 100 ꢁ cross termi-

nation, but the source must then control the common-mode

voltage and supply the input bias currents.

and Input

CLK1

PCB LAYOUT CONSIDERATIONS

The ADCLK948 buffer is designed for very high speed applica-

tions. Consequently, high speed design techniques must be used

to achieve the specified performance. It is critically important

to use low impedance supply planes for both the negative supply

(V_EE) and the positive supply (V_CC) planes as part of a multilayer

board. Providing the lowest inductance return path for switching

currents ensures the best possible performance in the target

application.

There are ESD/clamp diodes between the input pins to prevent

the application from developing excessive offsets to the input

transistors. ESD diodes are not optimized for best ac perfor-

mance. When a clamp is required, it is recommended that

appropriate external diodes be used.

Exposed Metal Paddle

The exposed metal paddle on the ADCLK948 package is both

an electrical connection and a thermal enhancement. For the

device to function properly, the paddle must be properly

attached to the V_EEpower plane.

The following references to the GND plane assume that the V_EE

power plane is grounded for LVPECL operation. Note that, for

ECL operation, the V_CCpower plane becomes the ground plane.

When properly mounted, the ADCLK948 also dissipates heat

through its exposed paddle. The PCB acts as a heat sink for the

ADCLK948. The PCB attachment must provide a good thermal

path to a larger heat dissipation area. This requires a grid of vias

from the top layer down to the V_EEpower plane (see Figure 18).

The ADCLK948 evaluation board (ADCLK948/PCBZ) pro-

vides an example of how to attach the part to the PCB.

It is also important to adequately bypass the input and output

supplies. Place a 1 μF electrolytic bypass capacitor within several

inches of each V_CCpower supply pin to the GND plane. In

addition, place multiple high quality 0.001 μF bypass capacitors

as close as possible to each of the V_CCsupply pins, and connect

the capacitors to the GND plane with redundant vias. Carefully

select high frequency bypass capacitors for minimum induc-

tance and ESR. To improve the effectiveness of the bypass at

high frequencies, minimize parasitic layout inductance. Also,

avoid discontinuities along input and output transmission lines

that can affect jitter performance.

VIAS TO V POWER

In a 50 ꢁ environment, input and output matching have a

significant impact on performance. The buffer provides internal

PLANE

CLKx

50 Ω termination resistors for both CLKx and

inputs.

Normally, the return side is connected to the reference pin that is

provided. Carefully bypass the termination potential using

ceramic capacitors to prevent undesired aberrations on the

input signal due to parasitic inductance in the termination

Figure 18. PCB Land for Attaching Exposed Paddle

Rev. 0 | Page 10 of 12

ADCLK948

INPUT TERMINATION OPTIONS

REF

V x

50Ω

CLKx

ADCLK948

CONNECT V x TO V

REF

Figure 19. DC-Coupled CML Input Termination

Figure 21. AC-Coupled Input Termination, Such as LVDS and LEVPECL

REF

V x

50Ω

CLKx

REF

0.01µF

(OPTIONAL)

V x

CLKx

50Ω

ADCLK948

CLKx

CONNECT V x, V

x, AND CLKx. PLACE A

CLKx

REF

BYPASS CAPACITOR FROM V x TO GROUND.

ALTERNATIVELY, V x, V

x, AND CLKx CAN BE

REF

CONNECTED, GIVING A CLEANER LAYOUT AND

A 180º PHASE SHIFT.

ADCLK948

Figure 20. DC-Coupled LVPECL Input Termination

Figure 22. AC-Coupled Single-Ended Input Termination

REF

V x

50Ω

CLKx

ADCLK948

Figure 23. DC-Coupled 3.3 V CMOS Input Termination

Rev. 0 | Page 11 of 12

ADCLK948

OUTLINE DIMENSIONS

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

0.50

BSC

PIN 1

INDICATOR

TOP

VIEW

2.85

2.70 SQ

2.55

EXPOSED

PAD

(BOTTOM VIEW)

4.75

BSC SQ

0.50

0.40

0.30

0.20 MIN

3.50 REF

0.80 MAX

1.00

0.85

0.80

12° MAX

0.65 TYP

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

0.30

0.25

0.18

SEATING

PLANE

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 24. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADCLK948BCPZ¹

ADCLK948BCPZ-REELꢀ¹

ADCLK948/PCBZ¹

Temperature Range

−40°C to +85°C

Package Description

32-Lead LFCSP_VQ

Evaluation Board

Package Option

CP-32-8

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D08280-0-7/09(0)

Rev. 0 | Page 12 of 12

ADCLK948BCPZ-REEL7 [ADI]

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