ADCMP393ARZ-RL7 [ADI]
Comparators;
ADI 
Single/Dual/Quad Comparators
With Known Power-Up State
Data Sheet
ADCMP391/ADCMP392/ADCMP393
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
VCC
Single-supply voltage operation: 2.3 V to 5.5 V
Rail-to-rail common-mode input voltage range
Low input offset voltage across VCMR: 1 mV typical
Guarantees comparator output logic low from VCC = 0.9 V to
undervoltage lockout (UVLO)
ADCMP391
IN+
OUT
IN–
GND
Operating temperature range: −40°C to +125°C
Package types:
8-lead, narrow body SOIC (ADCMP391/ADCMP392)
14-lead, narrow body SOIC (ADCMP393)
14-lead TSSOP (ADCMP393)
Figure 1.
VCC
ADCMP392
INA+
OUTA
INA–
APPLICATIONS
INB+
OUTB
INB–
Battery management/monitoring
Power supply detection
GND
Window comparators
Figure 2.
Threshold detectors/discriminators
Microprocessor systems
VCC
GENERAL DESCRIPTION
ADCMP393
INA+
OUTA
INA–
The ADCMP391/ADCMP392/ADCMP393 are
single/dual/quad rail-to-rail input, low power comparators ideal
for use in general-purpose applications. These comparators
operate from a single supply voltage of 2.3 V to 5.5 V and draw
a minimal amount of current. The single ADCMP391
consumes only 18.6 µA of supply current. The dual ADCMP392
and the quad ADCMP393 consumes 22.1 µA and 26.8 µA of
supply current, respectively. The low voltage and low current
operation of these devices makes it ideal for battery-powered
systems.
INB+
OUTB
INB–
INC+
OUTC
INC–
IND+
OUTD
IND–
GND
Figure 3.
The comparators features a common-mode input voltage range
of 200 mV beyond rails, an offset voltage of 1 mV typical across
the full common-mode range, and a UVLO monitor. In addition,
the design of the comparators allows a defined output state
upon power-up, a logic low output while the supply voltage is
less than the UVLO threshold.
The ADCMP391 and ADCMP392 are available in 8-lead,
narrow body SOIC package while the ADCMP393 is available
in a 14-lead, narrow body SOIC package and a 14-lead TSSOP
package. The comparators are specified to operate over the
−40°C to +125°C extended temperature range.
Rev. D
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ADCMP391/ADCMP392/ADCMP393
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Open-Drain Output................................................................... 10
Power-Up Behavior.................................................................... 10
Crossover Bias Point .................................................................. 10
Comparator Hysteresis .............................................................. 10
Typical Applications....................................................................... 11
Adding Hysteresis....................................................................... 11
Window Comparator for Positive Voltage Monitoring......... 11
Window Comparator for Negative Voltage Monitoring .......... 12
Programmable Sequencing Control Circuit............................... 12
Mirrored Voltage Sequencer Example..................................... 14
Threshold and Timeout Programmable Voltage Supervisor .... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Basic Comparator....................................................................... 10
Rail-to-Rail Input (RRI) ............................................................ 10
REVISION HISTORY
4/16—Rev. C to Rev. D
Changes to Adding Hysteresis Section ........................................ 11
Changes to Figure 34...................................................................... 13
Changes to Programming Sequencing Control Circuit Section;
Added Figure 25; Changes to Figure 26........................................ 11
Changes to Figure 27 and Figure 28 ............................................ 12
Changes to Figure 29...................................................................... 13
Changes to Mirrored Voltage Sequencer Example Section ...... 13
Changes to Figure 30, and Figure 31 ........................................... 14
Added Figure 32, Outline Dimensions........................................ 15
Changes to Ordering Guide.......................................................... 15
3/15—Rev. B to Rev. C
Added ADCMP391/ADCMP392 (Throughout) ......................... 1
Changes to Equation 4..............................................................................12
Changes to Equation 13 and 15..............................................................13
Changes to Ordering Guide .......................................................... 18
6/14—Rev. 0 to Rev. A
10/14—Rev. A to Rev. B
Changes to Product Title..................................................................1
Changes to Mirrored Voltage Sequencer Example Section ...... 14
Changes to Threshold and Timeout Programmable Voltage
Supervisor Section.......................................................................... 14
Added TSSOP Package (Throughout)........................................... 1
Changes to Data Sheet Title ...................................................................... 1
Added Figure 3; Renumbered Sequentially .................................. 5
Changes to Open-Drain Output Section ......................................... 9
5/14—Revision 0: Initial Version
Rev. D | Page 2 of 17
Data Sheet
ADCMP391/ADCMP392/ADCMP393
SPECIFICATIONS
VCC = 2.3 V to 5.5 V, TA = −40°C to +125°C, VCMR = −200 mV to VCC + 200 mV, unless otherwise noted. Typical values are at TA = 25°C.
Table 1.
Parameter
Symbol
VCC
Min
Typ
Max
Unit
Test Conditions/Comments1
POWER SUPPLY
Supply Voltage
2.3
0.9
5.5
UVLORISE
V
V
Guarantees comparator output low
VCC Quiescent Current
ADCMP391
ICC
18.6
18.5
22.1
20.7
26.8
26.6
24.7
23.8
29.3
26.5
36.8
34.3
µA
µA
µA
µA
µA
µA
All outputs in high-Z state, VOD = 0.1 V
All outputs low, VOD = 0.1 V
All outputs in high-Z state, VOD = 0.1 V
All outputs low, VOD = 0.1 V
All outputs in high-Z state, VOD = 0.1 V
All outputs low, VOD = 0.1 V
ADCMP392
ADCMP393
UNDERVOLTAGE LOCKOUT
VCC Rising
UVLORISE
UVLOHYS
2.062
5
2.162
25
2.262
50
V
Hysteresis
mV
COMPARATOR INPUT
Common-Mode Input Range
Input Offset Voltage
VCMR
VOS
−200
VCC + 200
mV
mV
mV
mV
mV
nA
nA
nA
nA
mV
mV
0.5
0.5
1
2.5
2.5
5
INx+ = INx− = 1 V
INx+ = INx− = 1 V, TA = −40°C to +85°C
1
5
TA = −40°C to +85°C
VCMR = −50 mV to VCC + 50 mV
INx+ = INx− = 1 V
VCMR = −50 mV to VCC + 50 mV
VCMR = −50 mV to VCC + 50 mV, TA = −40°C to +85°C
VCM = 1 V
Input Offset Current
Input Bias Current
IOS
IBIAS
10
30
80
10
4
Input Hysteresis
VHYS
3
6
8
COMPARATOR OUTPUT
Output Low Voltage
VOL
0.1
0.01
0.3
0.15
150
V
V
nA
VCC = 2.3 V, ISINK = 2.5 mA
VCC = 0.9 V, ISINK = 100 µA
VOUT = 0 V to 5.5 V
Output Leakage Current
COMPARATOR CHARACTERISTICS
Power Supply Rejection Ratio
Common-Mode Rejection Ratio
Voltage Gain
Rise Time2
Fall Time2
ILEAK
PSRR
CMRR
AV
60
50
80
74
132
1.1
0.15
dB
dB
dB
µs
tR
VOUT = 10% to 90% of VCC
VOUT = 90% to 10% of VCC
tF
µs
Propagation Delay
Input Rising2
tPROP_R
4.7
4.9
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
VCM = 1 V, VCC = 2.3 V, VOD = 10 mV
VCM = 1 V, VCC = 5 V, VOD = 10 mV
VCM = 1 V, VCC = 2.3 V, VOD = 100 mV
VCM = 1 V, VCC = 5 V, VOD = 100 mV
VCM = 1 V, VCC = 2.3 V, VOD = 10 mV
VCM = 1 V, VCC = 5 V, VOD= 10 mV
VCM = 1 V, VCC = 2.3 V, VOD = 10 mV
VCM = 1 V, VCC = 5 V, VOD = 10 mV
VCM = 1 V, VCC = 2.3 V, VOD = 100 mV
VCM = 1 V, VCC = 5 V, VOD = 100 mV
VCM = 1 V, VCC = 2.3 V, VOD = 10 mV
VCM = 1 V, VCC = 5 V, VOD = 10 mV
2.8
3.2
ADCMP392 Channel B
Input Falling2
4.9
9.7
4.5
9.5
tPROP_F
2
4.2
ADCMP392 Channel B
4.7
5
1 VOD = overdrive voltage.
2 RPULLUP = 10 kΩ, and CL = 50 pF.
Rev. D | Page 3 of 17
ADCMP391/ADCMP392/ADCMP393
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Rating
Table 3. Thermal Resistance
Package Type
VCC Pin
All INx+ and INx− Pins
All OUTx Pins
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
10 mA
−65°C to +150°C
−40°C to +125°C
300°C
θJA
Unit
°C/W
°C/W
°C/W
8-Lead Narrow-Body SOIC
14-Lead Narrow-Body SOIC
14-Lead TSSOP
121
80
125
OUTx Pins Sink Current (ISINK
)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (10 sec)
Junction Temperature
ESD CAUTION
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. D | Page 4 of 17
Data Sheet
ADCMP391/ADCMP392/ADCMP393
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NIC
IN–
1
2
3
4
8
7
6
5
NIC
ADCMP391
TOP VIEW
(Not to Scale)
VCC
OUT
NIC
IN+
GND
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
Figure 4. ADCMP391 Pin Configuration
Table 4. ADCMP391 Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 5, 8
NIC
IN−
IN+
GND
OUT
Not Internally Connected
Comparator Inverting Input
Comparator Noninverting Input
Device Ground
Comparator Output, Open-Drain
Device Supply Input
2
3
4
6
7
VCC
OUTA
INA–
INA+
GND
1
2
3
4
8
7
6
5
VCC
ADCMP392
TOP VIEW
(Not to Scale)
OUTB
INB–
INB+
Figure 5. ADCMP392 Pin Configuration
Table 5. ADCMP392 Pin Function Descriptions
Pin No.
Mnemonic
OUTA
INA−
INA+
GND
INB+
INB−
OUTB
VCC
Description
1
2
3
4
5
6
7
8
Comparator A Output, Open-Drain
Comparator A Inverting Input
Comparator A Noninverting Input
Device Ground
Comparator B Noninverting Input
Comparator B Inverting Input
Comparator B Output, Open-Drain
Device Supply Input
Rev. D | Page 5 of 17
ADCMP391/ADCMP392/ADCMP393
Data Sheet
OUTB
OUTA
VCC
1
2
3
4
5
6
7
14 OUTC
13 OUTD
12 GND
11 IND+
10 IND–
1
2
3
4
5
6
7
14 OUTC
OUTB
OUTA
VCC
13 OUTD
12 GND
11 IND+
10 IND–
ADCMP393
TOP VIEW
(Not to Scale)
ADCMP393
TOP VIEW
(Not to Scale)
INA–
INA+
INB–
INB+
INA–
INA+
INB–
INB+
9
8
INC+
INC–
9
8
INC+
INC–
Figure 6. ADCMP393 SOIC Pin Configuration
Figure 7. ADCMP393 TSSOP Pin Configuration
Table 6. ADCMP393 Pin Function Descriptions
Pin No.
Mnemonic
OUTB
OUTA
VCC
Description
1
2
3
Comparator B Output, Open Drain
Comparator A Output, Open Drain
Device Supply Input
4
5
6
7
8
9
10
11
12
13
14
INA−
INA+
INB−
INB+
INC−
INC+
IND−
IND+
GND
OUTD
OUTC
Comparator A Inverting Input
Comparator A Noninverting Input
Comparator B Inverting Input
Comparator B Noninverting Input
Comparator C Inverting Input
Comparator C Noninverting Input
Comparator D Inverting Input
Comparator D Noninverting Input
Device Ground
Comparator D Output, Open Drain
Comparator C Output, Open Drain
Rev. D | Page 6 of 17
Data Sheet
ADCMP391/ADCMP392/ADCMP393
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
2.5
2.0
T
T
T
T
= +25°C
= +85°C
= +125°C
= –40°C
SAMPLE 1
A
A
A
A
SAMPLE 2
SAMPLE 3
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–0.5
–1.0
–1.5
–2.0
–2.5
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
COMMON-MODE VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 8. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
CC = 3.3 V
Figure 11. Input Offset Voltage (VOS) vs. Supply Voltage (VCC), VCM = 1 V
for Various Temperatures
V
2.5
2.0
2.4
V
V
V
= 2.3V
= 3.3V
= 5.5V
CC
CC
CC
IN+ = IN– + 10mV
2.2
V
= IN– = 1V
CM
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–40 –25 –10
5
20
35
50
65
80
95 110 125
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 9. Input Offset Voltage (VOS) vs. Temperature for
Various Supply Voltages (VCC), VCM = 1 V
Figure 12. Output Voltage (VOUT) vs. Supply Voltage (VCC), RPULLUP = 10 kΩ
55
55
50
45
40
35
30
25
20
15
10
ADCMP391
ADCMP392
ADCMP391
ADCMP392
ADCMP393
50
ADCMP393
45
40
35
30
25
20
15
10
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 10. Supply Current vs. Supply Voltage (VCC) at Output Low Voltage
for Various Temperatures
Figure 13. Supply Current vs. Supply Voltage (VCC) at Output High Voltage
for Various Temperatures
Rev. D | Page 7 of 17
ADCMP391/ADCMP392/ADCMP393
Data Sheet
50
50
45
40
35
30
25
20
15
10
5
ADCMP391
ADCMP392
ADCMP393
ADCMP391
ADCMP392
ADCMP393
45
40
35
30
25
20
15
10
5
–50
0
50
100
–50
0
50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. Supply Current vs. Temperature at Output High Voltage
Figure 17. Supply Current vs. Temperature at Output Low Voltage
for Various Supply Voltages (VCC
)
for Various Supply Voltages (VCC
)
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
V
V
V
= 2.3V
= 3.3V
= 5.5V
CC
CC
CC
T
T
T
T
= +25°C
A
A
A
A
= +85°C
= +125°C
= –40°C
–50
–25
0
25
50
75
100
125
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 15. Input Hysteresis vs. Temperature for
Various Supply Voltages (VCC), VCM = 1 V
Figure 18. Input Hysteresis vs. Supply Voltage (VCC) for
Various Temperatures, VCM = 1 V
8
7
6
5
4
3
2
14
12
10
8
V
V
V
= 2.3V
= 3.3V
= 5.5V
R
V
C
= 10kΩ
PULLUP
V
V
V
= 2.3V
= 3.3V
= 5.5V
R
= 10kΩ
PULLUP
= 10mV
= 50pF
= 1V
CC
CC
CC
CC
CC
CC
= 10mV
V
OD
OD
= 50pF
C
L
L
V
= 1V
V
CM
CM
6
4
2
0
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Propagation Delay vs. Temperature, Low to High, VOD = 10 mV
Figure 19. Propagation Delay vs. Temperature, High to Low, VOD = 10 mV
Rev. D | Page 8 of 17
Data Sheet
ADCMP391/ADCMP392/ADCMP393
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
10
9
8
7
6
5
4
3
2
1
V
V
V
= 2.3V
= 3.3V
= 5.5V
R
C
V
= 10kΩ
= 50pF
V
V
V
= 2.3V
= 3.3V
= 5.5V
R
C
V
= 10kΩ
= 50pF
= 1V
CC
CC
CC
PULLUP
CC
CC
CC
PULLUP
L
L
= 1V
CM
CM
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
INPUT OVERDRIVE VOLTAGE (mV)
INPUT OVERDRIVE VOLTAGE (mV)
Figure 20. Propagation Delay vs. Input Overdrive Voltage, Low to High
Figure 23. Propagation Delay vs. Input Overdrive Voltage, High to Low
12
5.0
R
C
V
= 10kΩ
= 50pF
V
V
V
= 2.3V
= 3.3V
= 5.5V
R
C
V
= 10kΩ
= 50pF
V
V
V
= 2.3V
= 3.3V
= 5.5V
PULLUP
CC
CC
CC
PULLUP
CC
CC
CC
L
L
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
= 1V
= 1V
CM
CM
10
8
6
4
2
0
10
30
50
70
90
10
30
50
70
90
INPUT OVERDRIVE VOLTAGE (mV)
INPUT OVERDRIVE VOLTAGE (mV)
Figure 21. Propagation Delay vs. Input Overdrive Voltage, Low to High,
ADCMP392 Channel B
Figure 24. Propagation Delay vs. Input Overdrive Voltage, High to Low,
ADCMP392 Channel B
200
18
V
C
= 3.3V
= 50pF
V
C
= 3.3V
= 50pF
CC
CC
L
L
190
180
170
160
150
140
130
120
110
100
16
14
12
10
8
6
4
2
0
1
10
100
1
10
100
PULL-UP RESISTANCE (kΩ)
PULL-UP RESISTANCE (kΩ)
Figure 22. Output Voltage Rise Time (tR) vs. Pull-Up Resistance (RPULLUP
)
Figure 25. Output Voltage Fall Time (tF) vs. Pull-Up Resistance (RPULLUP)
Rev. D | Page 9 of 17
ADCMP391/ADCMP392/ADCMP393
Data Sheet
THEORY OF OPERATION
BASIC COMPARATOR
POWER-UP BEHAVIOR
In its most basic configuration, a comparator can be used to
convert an analog input signal to a digital output signal (see
Figure 26). The analog signal on INx+ is compared to the
voltage on INx−, and the voltage at OUTx is either high or low,
depending on whether INx+ is at a higher or lower potential
than INx−, respectively.
On power-up, when VCC reaches 0.9 V, the ADCMP391/
ADCMP392/ADCMP393 is guaranteed to assert an output low
logic. When the voltage on the VCC pin exceeds UVLO, the
comparator inputs take control.
CROSSOVER BIAS POINT
Rail-to-rail inputs of this type of architecture, in both op amps
and comparators, have a dual front-end design. PMOS devices
are inactive near the VCC rail, and NMOS devices are inactive near
GND. At some predetermined point in the common-mode range, a
crossover occurs. At this point, normally 0.8 V and VCC − 0.8 V, the
measured offset voltages change.
V
CC
V+
INx+
INx–
V
IN
OUTx
V
REF
COMPARATOR HYSTERESIS
In noisy environments, or when the differential input amplitudes
are relatively small or slow moving, adding hysteresis (VHYS) to
the comparator is often desirable. The transfer function for a
comparator with hysteresis is shown in Figure 27. As the input
voltage approaches the threshold (0 V in Figure 27) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +VHYS/2. The
new switch threshold becomes −VHYS/2. The comparator remains
in the high state until the −VHYS/2 threshold is crossed from
below the threshold region in a negative direction. In this
manner, noise or feedback output signals centered on the 0 V
input cannot cause the comparator to switch states unless it
V
OUT
V+
V
REF
0V
t
V
IN
Figure 26. Basic Comparator and Input and Output Signals
RAIL-TO-RAIL INPUT (RRI)
Using a CMOS nonRRI stage (that is, a single differential pair)
limits the input voltage to approximately one gate-to-source
voltage (VGS) away from one of the supply lines. Because VGS for
normal operation is commonly more than 1 V, a single differential
pair input stage comparator greatly restricts the allowable input
voltage. This restriction can be quite limiting with low voltage
supplies. To resolve this issue, RRI stages allow the input signal
range to extend up to the supply voltage range. In the case of the
ADCMP391/ADCMP392/ADCMP393, the inputs continue to
operate 200 mV beyond the supply rails.
exceeds the region bounded by
VHYS/2.
OUTPUT
V
OH
OPEN-DRAIN OUTPUT
V
OL
The ADCMP391/ADCMP392/ADCMP393 have an open-drain
output stage that requires an external resistor to pull up to the
logic high voltage level when the output transistor is switched
off. The pull-up resistor must be large enough to avoid excessive
power dissipation, but small enough to switch logic levels
reasonably quickly when the comparator output is connected to
other digital circuitry. The rise time of the open-drain output
depends on the pull-up resistor (RPULLUP) and load capacitor (CL)
used.
INPUT
0V
–V
+V
HYST
2
HYST
2
Figure 27. Comparator Hysteresis Transfer Function
The rise time can be calculated by
tR = 2.2 RPULLUP CL
(1)
Rev. D | Page 10 of 17
Data Sheet
ADCMP391/ADCMP392/ADCMP393
TYPICAL APPLICATIONS
ADDING HYSTERESIS
WINDOW COMPARATOR FOR POSITIVE VOLTAGE
MONITORING
To add hysteresis, see Figure 28; two resistors are used to create
different switching thresholds, depending on whether the input
signal is increasing or decreasing in magnitude. When the input
voltage increases, the threshold is above VREF, and when the
When monitoring a positive supply, the desired nominal
operating voltage for monitoring is denoted by VM, IM is the
nominal current through the resistor divider, VOV is the
overvoltage trip point, and VUV is the undervoltage trip point.
input voltage decreases, the threshold is below VREF
.
V
= 5V
V
M
CC
R
X
R
PULL-UP
INA+
INA–
V
PH
OUTx
INx–
INx+
OUTA
OUTB
V
= 2.5V
IN
REF
V
R
LOAD
R
V
Y
REF
R1
INB+
INB–
R2
V
PL
R
Z
V
OUT
Figure 29. Positive Undervoltage/Overvoltage Monitoring Configuration
Figure 29 illustrates the positive voltage monitoring input
connection. Three external resistors, RX, RY, and RZ, divide the
positive voltage for monitoring, VM, into the high-side voltage,
V
IN
V
PH, and the low-side voltage, VPL. The high-side voltage is
V
V
IN_HIGH
IN_LOW
connected to the INA+ pin and the low-side voltage is
connected to the INB− pin.
Figure 28. Noninverting Comparator Configuration with Hysteresis
The upper input threshold level is given by
To trigger an overvoltage condition, the low-side voltage (in this
case, VPL) must exceed the VREF threshold on the INB+ pin.
Calculate the low-side voltage, VPL, by the following:
V
REF (R1+ R2)
VIN_HI
=
(2)
R2
Assuming RLOAD >> R2, RPULLUP
The lower input threshold level is given by
VREF R1+ R2 + RPULLUP −VCCR1
R2 + RPULLUP
.
RZ
(5)
VPL =VREF =VOV
RX + RY + RZ
(
)
In addition,
RX + RY + RZ = VM/IM
VIN _ LO
=
(3)
(4)
(6)
The hysteresis is the difference between these voltages levels.
Therefore, RZ, which sets the desired trip point for the
overvoltage monitor, is calculated as
VREF R1RPULL UP +VCCR1R2
−
VHYS
=
R2(R2 + RPULL
)
UP
(
VREF
)
(
VM
)
)
−
(7)
(8)
RZ =
(
VOV
)
(IM
To trigger the undervoltage condition, the high-side voltage,
PH, must be less than the VREF threshold on the INA− pin. The
high-side voltage, VPH, is calculated by
V
RY + RZ
VPH =VREF =VUV
RX + RY + RZ
Because RZ is already known, RY can be expressed as
VREF VM
(
)
(
)
− RZ
(9)
RY =
(
VUV
)
(IM
)
When RY and RZ are known, RX can be calculated by
RX = (VM/IM) – RY − RZ
(10)
If VM, IM, VOV, or VUV changes, each step must be recalculated.
Rev. D | Page 11 of 17
ADCMP391/ADCMP392/ADCMP393
Data Sheet
Because RZ is already known, RY can be expressed as follows:
WINDOW COMPARATOR FOR NEGATIVE VOLTAGE
MONITORING
VREF
(
VM −VREF
)
− RZ
RY =
(15)
(16)
Figure 30 shows the circuit configuration for negative supply
voltage monitoring. To monitor a negative voltage, a reference
voltage is required to connect to the end node of the voltage
IM
When RY and RZ are known, RX is then calculated by
VM −VREF
(
VREF −VUV
)
(
)
− RY − RZ
divider circuit, in this case, VREF
.
RX =
IM
V
REF
PROGRAMMABLE SEQUENCING CONTROL CIRCUIT
R
Z
INA+
INA–
V
NH
The circuit shown in Figure 31 is used to control the power
supply sequencing. The delay is set by the combination of the
pull-up resistor (RPULLUP), the load capacitor (CL), and the
resistor divider network.
OUTA
OUTB
R
V
Y
REF
INB+
INB–
V
NL
V
/V
REF CC
R
X
R
V
PULLUP
M
R5
R4
R3
R2
R1
U1
INA+
INA–
SEQ
Figure 30. Negative Undervoltage/Overvoltage Monitoring Configuration
OUTA
OUTB
OUTC
OUTD
C
L
V4
V3
V2
V1
Equation 7, Equation 9, and Equation 10 need some minor
modifications for use with negative voltage monitoring. The
reference voltage, VREF, is added to the overall voltage drop;
therefore, it must be subtracted from VM, VUV, and VOV before
using each of them in Equation 7, Equation 9, and Equation 10.
INB+
INB–
INC+
INC–
To monitor a negative voltage level, the resistor divider circuit
divides the voltage differential level between VREF and the
negative supply voltage into the high-side voltage, VNH, and the
low-side voltage, VNL. The high-side voltage, VNH, is connected
to INC+, and the low-side voltage, VNL, is connected to IND−.
IND+
IND–
Figure 31. Programmable Sequencing Control Circuit
To trigger an overvoltage condition, the monitored voltage must
exceed the nominal voltage in terms of magnitude, and the
high-side voltage (in this case, VNH) on the INC+ pin must be
more negative than ground. Calculate the high-side voltage,
Figure 32 shows a simplified block diagram for the
programmable sequencing control circuit. The application
delays the enable signal, EN, of the external regulators (LDO x)
in a linear order when the open-drain signal (SEQ) changes
from low to high impedance.
V
NH, by the following:
RX + RY
RX + RY + RZ
(11)
(12)
The ADCMP391/ADCMP392/ADCMP393 have a defined
output state during startup, which prevents any regulator from
turning on if VCC is still below the UVLO threshold.
VNH = GND =
(
V
−VOV
)
+V
OV
REF
In addition,
RX + RY + RZ =
3.3V
IN
OUT
LDO 1
3.0V
1.8V
2.5V
1.2V
(
VM −VREF
)
EN
IM
GND
Therefore, RZ, which sets the desired trip point for the
overvoltage monitor, is calculated by
IN
OUT
LDO 2
V
/V
REF CC
EN
GND
VREF
(
VM −VREF
VREF −VOV
To trigger an undervoltage condition, the monitored voltage
)
t1
(13)
RZ =
t2
t3
t4
IM
(
)
SEQ
IN
OUT
LDO 3
GND
EN
must be less than the nominal voltage in terms of magnitude,
and the low-side voltage (in this case, VNL) on the IND− pin
must be more positive than ground. Calculate the low-side
voltage, VNL, by the following:
GND
IN
OUT
LDO 4
EN
GND
RX
(14)
VNL = GND =
(
V
−VUV
)
+V
UV
REF
Figure 32. Simplified Block Diagram of a Programmable
Sequencing Control Circuit
RX + RY + RZ
Rev. D | Page 12 of 17
Data Sheet
ADCMP391/ADCMP392/ADCMP393
First, determine the allowable current, IDIV, flowing through the
resistor divider. After the value for IDIV is determined, calculate
R1, R2, R3, R4, and R5 using the following formulas:
SEQ
V4
V3
V2
V1
V
C
L
t4
t3
OUTA
OUTB
OUTC
VREF
(22)
(23)
(24)
(25)
RDIV
R1 =
R2 =
R3 =
R4 =
=
= R1+ R2 + R3 + R4 + R5
IDIV
t2
V1RDIV
VREF
t1
OUTD
Figure 33. Programmable Sequencing Control Circuit Timing Diagram
V2RDIV
VREF
− R1
When the SEQ signal changes from low to high impedance, the
load capacitor, CL, starts to charge. The time it takes to charge the
load capacitor to the pull-up voltage (in this case, VREF or VCC) is the
maximum delay programmable in the circuit. It is recommended
to have the threshold within 10% to 90% of the pull-up voltage.
Calculate the maximum allowable delay by
V3RDIV
VREF
− R1− R2
− R1− R2 − R3
V4RDIV
VREF
(26)
(27)
tMAX = tR = 2.2 RPULLUP CL
(17)
R5 = RDIV − R1 − R2 − R3 − R4
The delay of each output is changed by changing the threshold
voltage, V1 to V4, when the comparator changes its output state.
To create a mirrored voltage sequence, add a resistor, RMIRROR
between the pull-up resistor (RPULLUP) and the load capacitor
(CL) as shown in Figure 34.
,
To calculate the voltage thresholds for the comparator, use the
following formulas:
V
/V
REF CC
−t
1
R
R
R
R
R
C
PULLUP
PULLUP
L
V1=V
V2 =V
V3 =V
V4 =V
1−e
1−e
1−e
1−e
(18)
(19)
(20)
(21)
REF
R5
R4
R3
R2
R1
R
U1
MIRROR
INA+
INA–
SEQ
OUTD
OUTC
OUTB
OUTA
C
L
V4
V3
V2
V1
−t
2
C
C
C
PULLUP
L
L
L
INB+
INB–
REF
−t
3
INC+
INC–
PULLUP
REF
IND+
IND–
−t
4
PULLUP
REF
The threshold voltages can come from a voltage reference or a
voltage divider circuit, as shown in Figure 31.
Figure 34. Circuit Configuration for a Mirrored Voltage Sequencer
Figure 34 shows the circuit configuration for a mirrored voltage
sequencer. When SEQ changes from low to high impedance, the
response is similar to Figure 33. When SEQ changes from high
impedance to low, the load capacitor (CL) starts to discharge at a
rate set by RMIRROR. The delay of each comparator is dependent
on the threshold voltage previously set for t1 to t4. The result is a
mirrored power-down sequence.
Rev. D | Page 13 of 17
ADCMP391/ADCMP392/ADCMP393
Data Sheet
SEQ
V4
V3
V2
V1
V1
V
V4
t5
C
V3
L
V2
t4
t3
OUTA
OUTB
t6
t2
t7
OUTC
OUTD
t1
t8
Figure 35. Mirrored Voltage Sequencer Timing Diagram
The timing diagram for the mirrored voltage sequencer is
shown in Figure 35.
MIRRORED VOLTAGE SEQUENCER EXAMPLE
To illustrate how the mirrored voltage sequencer works, see
Figure 32 and then consider a system that uses a VREF of 1 V and
requires a delay of 50 ms when SEQ changes from low to high
impedance, and between each regulator when turning on. These
considerations require a rise time of at least 200 ms for the pull-up
resistor (RPULLUP) and the load capacitor (CL). The sum of the
resistance of RMIRROR and RPULLUP must be large enough to charge the
capacitor longer than the minimum required delay. For a
symmetrical mirrored power-down sequence, the value of RMIRROR
must be much larger than RPULLUP. A 10 kΩ RPULLUP value limits the
pull-down current to 100 µA while giving a reasonable value for
Equation 18 through Equation 21 must account for the
additional resistance, RMIRROR, in the calculations of the voltage
thresholds. To calculate these new thresholds, see Equation 28
through Equation 31.
−t
1
V1 =VREF 1− e(
(28)
(29)
(30)
(31)
R
+ R
)
C
PULLUP
MIRROR
L
−t
2
V2 =VREF 1− e(
R
+ R
)
C
PULLUP
MIRROR
L
RMIRROR. A typical 1 µF capacitor together with a 150 kΩ RMIRROR
value gives a value of
−t
3
t
MAX = 2.2((160 × 103) × (1 × 10−6)) = 351 ms
(36)
V3 =VREF 1− e(
R
+ R
)
C
PULLUP
PULLUP
MIRROR
L
L
The threshold voltage required by each comparator is set by
Equation 28 to Equation 31. For example,
−t
4
−3
V4 =VREF 1− e(
R
+ R
)
C
MIRROR
−50×10
V1 =VREF 1−e 160 × 10
3
−6
× 1 × 10
RMIRROR provides the mirrored delay by prolonging the discharge
time of the capacitor. The mirrored voltage sequencer uses the
same threshold in Equation 28 to Equation 31 in a decreasing
order. To calculate the exact value of the mirrored delay time,
see Equation 32 through Equation 35.
where V1 = 268.38 mV.
Therefore, V2 = 464.74 mV, V3 = 608.39 mV, and V4 =
713.5 mV.
Next, consider 10 µA as the maximum current (IDIV) flowing
through the resistor divider network. This current gives the total
resistance of the divider network (RDIV) and the individual
resistor values using Equation 22 to Equation 27, resulting in
the following:
V 4
t5 = −RMIRRORCLln
t6 = −RMIRRORCLln
t7 = −RMIRRORCLln
(32)
(33)
(34)
(35)
VREF
V3
•
•
•
•
•
•
RDIV = 100 kΩ
VREF
R1 = 26.84 kΩ ≈ 26.7 kΩ
R2 = 19.64 kΩ ≈ 19.6 kΩ
R3 = 14.37 kΩ ≈ 14.3 kΩ
R4 = 10.51 kΩ ≈ 10.5 kΩ
R5 = 28.65 kΩ ≈ 28.7 kΩ
V2
VREF
V1
t8 = −RMIRRORCLln
VREF
Rev. D | Page 14 of 17
Data Sheet
ADCMP391/ADCMP392/ADCMP393
Resistor values from the calculation are nonindustry standard,
using industry standard resistor values resulted in a new RDIV
value of 99.8 kΩ. Due to the discrepancy of the calculated resistor
value to the industry standard value, the threshold of each
comparator also changed. Calculate the new threshold values
by using a simple voltage divider formula:
THRESHOLD AND TIMEOUT PROGRAMMABLE
VOLTAGE SUPERVISOR
Figure 36 shows a circuit configuration for a programmable
threshold and timeout circuit. The timeout, tRESET, defines the
duration that the input voltage (VIN) must be kept above the
RESET
threshold voltage to toggle the
device from operating when VIN is not stable. If VIN falls below
RESET
signal, preventing the
V1 = VREFR1/RDIV
(37)
the threshold voltage, the
signal toggles quickly.
1 V
99.8 kꢀ
26.7 kꢀ
where V1 =
= 267.54 mV.
V
V
CC
IN
R1
R
Therefore, V2 = 463.93 mV, V3 = 607.21 mV, and V4 = 712.42 mV.
PULLUP
OUTA
U1
Because the threshold of each comparator has changed, the time
when each comparator changes its output has also changed.
Calculate the new delay values for each comparator by using the
following equation:
R2
OUTB
U2
C
RESET
T
V
REF
Figure 36. Programmable Threshold and Timeout Circuit
V1
t1 CL
R
PULLUP RMIRROR
ln 1
(38)
V
TH
VREF
V
IN
267.54 mV
1
tRESET
tRESET
1
where t = −1 μF(10 kΩ + 150 kΩ)ln
= 49.81 ms.
1
RESET
Therefore, t2 = 99.78 ms, t3 = 149.52 ms, and t4 = 199.4 ms.
To calculate t5 through t8, use Equation 32 to Equation 35:
Figure 37. Threshold and Timeout Programmable Voltage Supervisor
Timing Diagram
During startup, the ADCMP391/ADCMP392/ADCMP393
guarantee a low output state when VCC is still below the UVLO
threshold, preventing the voltage supervisor from toggling.
V4
VREF
t5 RMIRROR CLln
When VIN reaches the threshold set by the resistor divider (R1
and R2) and VREF, OUT1 changes from low to high and starts to
charge the timeout capacitor (CT). If VIN is kept above the threshold
voltage and the voltage in CT reaches VREF, OUT2 toggles. If VIN
falls below the threshold voltage while CT is charging, the timeout
capacitor quickly discharges, preventing OUT2 from toggling
while VIN is not stable.
712.42 mV
1
where t5 = −150 kΩ × 1 μF × ln
= 50.86 ms.
Therefore, t6 = 74.83 ms, t7 = 115.2 ms, and t8 = 197.78 ms.
In the condition that VIN is tied to VCC, the circuit operates
when VCC is more than the minimum operating voltage.
The threshold voltage (VTH) is configured by changing the
resistor divider or VREF. Calculate the threshold voltage by
R1
R2
REF
(39)
VTH V
1
Timeout is adjusted by changing the values of the pull-up
resistor or the timeout capacitor. To set the timeout value,
determine the allowable current flowing through RPULLUP, IPULLUP
.
When IPULLUP is known, calculate RPULLUP and CT by the following
formulas:
R
PULLUP = VCC/IPULLUP
(40)
(41)
tRESET
CT
VREF
PULLUP ln 1
R
VCC
Rev. D | Page 15 of 17
ADCMP391/ADCMP392/ADCMP393
OUTLINE DIMENSIONS
Data Sheet
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 38. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 39. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
Rev. D | Page 16 of 17
Data Sheet
ADCMP391/ADCMP392/ADCMP393
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 40. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADCMP391ARZ
ADCMP391ARZ-RL7
ADCMP392ARZ
ADCMP392ARZ-RL7
ADCMP393ARZ
ADCMP393ARZ-RL7
ADCMP393ARUZ
ADCMP393ARUZ-RL7
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
R-8
R-8
R-8
R-8
R-14
R-14
RU-14
RU-14
1 Z = RoHS Compliant Part.
©2014–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12206-0-4/16(D)
Rev. D | Page 17 of 17
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