ADCMXL-BRKOUT_技术文档

Wide Bandwidth, Low Noise,

Vibration Sensor

Data Sheet

ADcmXL1021-1

FEATURES

FUNCTIONAL BLOCK DIAGRAM

VDD

GND

Single axis, digital output MEMS vibration sensing module

±±0 g measurement range

OUT_VDDM

POWER MANAGEMENT

Ultralow output noise density, 26 μg/√Hz (MTC mode)

Wide bandwidth: dc to 10 kHz within 3 dB flatness (RTS mode)

Embedded fast data conversion rate: 220 kSPS

6 digital FIR filters, 32 taps (coefficients), default options

High-pass filter cutoff frequencies: 1 kHz, ± kHz, 10 kHz

Low-pass filter cutoff frequencies: 1 kHz, ± kHz, 10 kHz

User configurable digital filter option (32 coefficients)

Spectral analysis through internal FFT

RST

CS

SCLK

DIN

MEMS

ACCELEROMETER

ADC

DOUT

SYNC/RTS

BUSY

ALM1

ALM2

Extended record length: 2048 bins with user configurable

bin sizes from 0.42 Hz to ±3.7 Hz

ADcmXL1021-1

Manual or timer-based (automatic) triggering

Windowing options: rectangular, Hanning, flat top

FFT record averaging, configurable up to 2±± records

Spectral defined alarm monitoring, 6 alarms

Time domain capture with statistical metrics

Extended record length: 4096 samples

Mean, standard deviation, peak, crest factor, skewness,

and Kurtosis

Configurable alarm monitoring

Figure 1.

GENERAL DESCRIPTION

The ADcmXL1021-1 is a complete vibration sensing system that

combines high performance vibration sensing (using a micro-

electromechanical systems (MEMS) accelerometer) with a variety

of signal processing functions to simplify the development of

smart sensor nodes in condition-based monitoring (CBM)

systems. The typical ultralow noise density (26 μg/√Hz) in the

MEMS accelerometers supports excellent resolution. The wide

bandwidth (dc to 10 kHz within 3 dB flatness) enables tracking

of key vibration signatures on many machine platforms.

Real-time data streaming at 220 kSPS

Burst mode communication with CRC-16 error checking

Storage: 10 data records

On demand self test with status flags

The signal processing includes high speed data sampling

(220 kSPS), 4096 time sample record lengths, filtering,

windowing, fast Fourier transform (FFT), user configurable

spectral or time statistic alarms, and error flags. The serial

peripheral interface (SPI) provides access to a register structure

that contains the vibration data and a wide range of user

configurable functions.

Sleep mode with external and timer driven wakeup

Digital temperature and power supply measurements

SPI-compatible serial interface

Identification registers: factory preprogrammed serial

number, device ID, user programmable ID

Single-supply operation: 3.0 V to 3.6 V

Operating temperature range: −40°C to +10±°C

Automatic shutdown at 12±°C (junction temperature)

23.7 mm × 27.0 mm × 12.4 mm aluminum package

36 mm flexible, 14-lead module with integrated flexible

connector

The ADcmXL1021-1 is available in a 23.7 mm × 27.0 mm ×

12.4 mm aluminum package with four mounting flanges to

support installation with standard machine screws. This light

weight package (13 g) provides consistent mechanical coupling

to the core sensors over a broad frequency range. The electrical

interface is through a 14-lead connector on a 36 mm flexible

cable, which enables a wide range of location and orientation

options for system mating connectors.

Mass: 13 g

APPLICATIONS

Vibration analysis

Condition-based monitoring (CbM) systems

Machine health

The ADcmXL1021-1 requires only a single, 3.3 V power supply

and supports an operating temperature range of −40°C to +105°C.

Instrumentation and diagnostics

Safety shutoff sensing

Multifunction pin names may be referenced by their relevant

function only.

Rev. 0

Document Feedback

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADcmXL1021-1

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

REC_CTRL, Recording Control .............................................. 31

REC_PRD, Record Period......................................................... 32

ALM_F_LOW, Alarm Frequency Band .................................. 33

ALM_F_HIGH, Alarm Frequency Band ................................ 33

ALM_MAG1, Alarm Level 1 .................................................... 33

ALM_MAG2, Alarm Level 2 .................................................... 33

ALM_PNTR, Alarm Pointer..................................................... 34

ALM_S_MAG Alarm Level...................................................... 34

ALM_CTRL, Alarm Conrol ..................................................... 34

FILT_CTRL, Filter Control....................................................... 34

AVG_CNT, Decimation Control.............................................. 35

DIAG_STAT, Status, and Error Flags....................................... 35

GLOB_CMD, Global Commands............................................ 36

ALM_STAT, Alarm Status......................................................... 36

ALM_PEAK, Alarm Peak Level............................................... 36

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 11

Core Sensors................................................................................ 11

Signal Processsing....................................................................... 11

Modes of Operation ................................................................... 12

Data Recording Options............................................................ 13

User Interface.............................................................................. 16

Basic Operation............................................................................... 19

Device Configuration ................................................................ 19

Dual Memory Structure ............................................................ 19

Power-Up Sequence ................................................................... 19

Trigger .......................................................................................... 19

Sample Rate ................................................................................. 20

Datapath Processing................................................................... 20

Spectral Alarms........................................................................... 22

Mechanical Mounting Recommendations.............................. 22

User Register Memory Map .......................................................... 23

User Register Details ...................................................................... 28

PAGE_ID, Page Number ........................................................... 28

TEMP_OUT, Internal Temperature......................................... 28

SUPPLY_OUT, Power Supply Voltage..................................... 28

FFT_AVG1, Spectral Averaging ............................................... 28

FFT_AVG2, Spectral Averaging ............................................... 29

BUF_PNTR, Buffer Pointer ...................................................... 29

REC_PNTR, Record Pointer..................................................... 30

OUT_BUF, Buffer Access Register........................................... 30

ANULL, Bias Calibration Register........................................... 31

TIME_STAMP_L and TIME_STAMP_H, Data Record

Timestamp................................................................................... 36

DAY_REV, Day and Revision ................................................... 37

YEAR_MON, Year and Month................................................. 37

PROD_ID, Product Identification ........................................... 37

SERIAL_NUM, Serial Number ................................................ 37

USER_SCRATCH ...................................................................... 37

REC_FLASH_CNT, Record Flash Endurance ....................... 37

MISC_CTRL, Miscellaneous Control ..................................... 37

REC_INFO1, Record Information........................................... 38

REC_INFO2, Record Information,.......................................... 38

REC_CNTR, Record Counter .................................................. 38

ALM_FREQ, Severe Alarm Frequency ................................... 38

STAT_PNTR, Statistic Result Pointer...................................... 38

STATISTIC, Statistic Result ...................................................... 39

FUND_FREQ, Fundamental Frequency................................. 39

FLASH_CNT_L, Flash Memory Endurance ......................... 39

FLASH_CNT_U, Flash Memory Endurance ......................... 39

FIR Filter Registers..................................................................... 40

Applications Information .............................................................. 41

Mechanical Interface.................................................................. 41

Outline Dimensions....................................................................... 42

Ordering Guide .......................................................................... 42

REVISION HISTORY

11/2019—Revision 0: Initial Version

Rev. 0 | Page 2 of 42

Data Sheet

ADcmXL1021-1

SPECIFICATIONS

T_A= 25°C and VDD = 3.3 V, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ACCELEROMETERS

Measurement Range¹

Sensitivity

50

g

FFT

Time Domain

Error over Temperature

Nonlinearity

Cross Axis Sensitivity

Alignment Error

Offset Error Over Temperature

Offset Temperature Coefficient

Output Noise

0.9535

1.907

5

0.2

2

5

34

mg/LSB

%

Best fit, straight line, full scale (FS) = 50 g

1.25

With respect to package

T_A= −40°C to +105°C

Real-time streaming (RTS) mode

100 Hz to 10 kHz, AVG_CNT = 0, MTC mode

1 Hz to 10 kHz, no filtering, RTS mode

Degrees

g

mg/°C

mg rms

µg/√Hz

Hz

3.2

26

32

Output Noise Density

3 dB Bandwidth

10,000

Sensor Resonant Frequency

CONVERSION RATE

Clock Accuracy

21

3

kHz

220

kSPS

%

FUNCTIONAL TIMING

Factory Reset Time Recovery

Start-Up Time

126

205

ms

Time from supply voltage reaching 3.0 V from

power-down until ready for command

Self Test Time

LOGIC INPUTS

92

ms

Input High Voltage, V_IH

Input Low Voltage, V_IL

Logic 1 Input Current, I_IH

Logic 0 Input Current, I_IL

All Except RST

2.5

V

µA

0.45

0.2

V_IH= 3.3 V

V_IL= 0 V

0.01

100

µA

mA

pF

1

RST

Input Capacitance, C_IN

DIGITAL OUTPUTS

Output Voltage

High, V_OH

10

I_OH= −1 mA

I_OL= 1 mA

1.4

V

Low, V_OL

0.4

Output Current

High, I_OH

Low, I_OL

I_OH= −1 mA

I_OL= 1 mA

2

mA

FLASH MEMORY

Endurance²

Data Retention³

THERMAL SHUTDOWN

Threshold

10,000

Cycles

Years

T_J= 85°C, see Figure 44

10

T_Jrising

125

15

°C

Hysteresis

OUT_VDDM MONITOR OUTPUT

Output Resistance

Logic output, logic high indicates good condition

Logic low when internal temperature exceeds

allowed range

90

100

110

kΩ

Rev. 0 | Page 3 of 42

ADcmXL1021-1

Data Sheet

Parameter

Test Conditions/Comments

Operating voltage range, VDD

Operating mode, VDD = 3.0 V

Operating mode, VDD = 3.3 V

Operating mode, VDD = 3.6 V

Sleep mode, VDD = 3.0 V

Min

Typ

3.3

22.9

23.2

23.9

0.1

Max

Unit

V

POWER SUPPLY VOLTAGE

Power Supply Current

3.0

3.6

mA

Sleep mode, VDD = 3.3 V

Sleep mode, VDD = 3.6 V

0.6

1.5

¹The maximum range depends on the frequency of the vibration.

²Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.

³Retention lifetime equivalent at junction temperature (T_J) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime depends on T_J.

TIMING SPECIFICATIONS

T_C= 25°C and VDD = 3.3 V, unless otherwise noted.

Table 2.

Normal Mode

Typ

RTS Mode

Typ

Parameter

f_SCLK

t_STALL

t_CLS

t_CHS

t_CS

Description

Min¹

0.01

16

35.7

Max¹Min

Max¹Unit

SCLK frequency

Stall period between data bytes

SCLK low period

14

8

14

MHz

µs

N/A²

35.7

ns

SCLK high period

CS

to SCLK edge

t_DAV

t_DSU

t_DHD

t_DSOE

t_HD

DOUT valid after SCLK edge

DIN setup time before SCLK rising edge

DIN hold time after SCLK rising edge

20

ns

6

8

6

8

0

assertion to DOUT active

20

CS

SCLK edge to DOUT invalid

t_SFS

Last SCLK edge to deassertion

35.7

12

CS

t_{RTS_BUSY}

RTS mode only, data out valid burst

readout period ends before BUSY rising

edge for next burst

N/A²

µs

¹Guaranteed by design and characterization, but not tested in production.

²N/A means not applicable. When using real-time streaming (RTS), the stall period is not applicable.

Timing Diagrams

CS

t_CHS

t_CLS

t_CS

t_SFS

1

2

3

4

5

6

15

16

SCLK

DOUT

t_DSOE

t_DAV

t_HD

MSB

DB14

t_DSU

DB13

DB12

DB11

DB10

DB2

DB1

LSB

t_DHD

DIN

R/W

A6

A5

A4

A3

A2

D2

D1

Figure 2. SPI Timing and Sequence

Rev. 0 | Page 4 of 42

Data Sheet

ADcmXL1021-1

t_STALL

CS

SCLK

Figure 3. Stall Time (Does Not Apply to RTS Mode)

12ms

DELAY

TRIGGER CAPTURE START

BY WRITING 0x0800 TO GLOB_CMD

REAL-TIME STREAMING FRAME (16 x 44 BITS)

HEADER 8 0x0000 WORDS, XL1:XL32, TEMP, STATUS, CRC

CS

SCLK

DIN

DON’T CARE

8 0x0000 WORDS

DON’T CARE

0x00, 0xAD

XL1[LSB, MSB]

DOUT

BUSY

NOTES

1. XLx IS ACCELEROMETER DATA; TEMP IS TEMPERATURE DATA.

Figure 4. RTS Mode Timing Diagram, Assumes REC_CTRL, Bits[1:0] = 0b11 (See Table 17)

NOT SHOWN ARE

31 16-BIT WORDS:

XL3 TO XL32

TEMPERATURE

CS

SCLK

DOUT

BUSY

t_{RTS_BUSY}

NOTES

1. XLx IS ACCELEROMETER DATA.

Figure 5. RTS Read Function Sequence Diagram, First Five Segments (See Table 17)

Rev. 0 | Page 5 of 42

ADcmXL1021-1

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 3.

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Pay careful attention

to PCB thermal design.

Parameter

Rating

Acceleration

Unpowered

2000 g

Powered

VDD to GND

2000 g

θ

_JAis the natural convection, junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure.

_JCis the junction to case thermal resistance.

−0.3 V to +3.6 V

Digital Input Voltage to GND

Digital Output Voltage to GND

Temperature Range

Operating Temperature

Storage Temperature

θ

The ADcmXL1021-1 is a multichip module that includes many

active components. The values in Table 4 identify the thermal

response of the hottest component inside of the ADcmXL1021-1

with respect to the overall power dissipation of the module.

This approach enables a simple method for predicting the

temperature of the hottest junction based on either ambient or case

temperature.

−40°C to +105°C

−65°C to +150°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond the

maximum operating conditions for extended periods may affect

product reliability.

For example, when T_A= 70°C, under normal operation mode

with a typical 23.2 mA current and 3.3 V supply voltage, the

hottest junction temperature in the ADcmXL1021-1 is 75.0°C.

T_J= θ_JA× VDD × I_DD+ 70°C

T_J= 65.1°C/W × 3.3 V × 0.0232 A + 70°C

T_J≈ 75.0°C

where I_DDis the current consumption of the device.

Table 4. Thermal Resistance

Package Type

ML-14-7¹

θ_JA

θ_JC

65.1°C/W

33.2°C/W

¹Thermal impedance simulated values come from a case with four machine

screws at a size of M2.5 × 0.4 mm (torque = 25 inch pounds). Secure the

ADcmXL1021-1 to the PCB.

ESD CAUTION

Rev. 0 | Page 6 of 42

Data Sheet

ADcmXL1021-1

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

13

14

Z

X

Y

PIN 1

PIN 14

PIN 13

Figure 6. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Type Description

Supply Ground.

1

2

GND

ALM1

Output Digital Output Only, Alarm 1 Output. This pin is configured by the ALM_CTRL register and is not used in

RTS mode.

3

SYNC/RTS

Input

Sync Function (SYNC)/RTS Burst Start/Stop (RTS). This pin is a digital input only and is edge (not level)

sensitive. This pin must be enabled in the MISC_CTRL register (Bit 12) before being used as an external

trigger. The SYNC pulse width must be at least 50 ns.

In MTC and MFFT modes, the SYNC pin acts as a manual trigger, this pin initiates a record capture event

when a low to high transition is detected, equivalent to SPI Command 0x0800 to the GLOB_CMD

register. In RTS and AFFT mode, when the logic level on this pin is high, conversion is active. When the

logic level on this pin is low, conversion is stopped after the current data record is completed.

4

5

ALM2

BUSY

Output Digital Output Only, Alarm 2 Output. This pin is configured by the ALM_CTRL register and is not used in

RTS mode.

Output Busy or Data Ready Indicator, Digital Output Only. In RTS mode, this pin is a logical output to indicate that

data is ready and available for download. The logical state resets to logic low when data is loading to the

output buffers. The pin is set high when data is ready for download. In other capture modes, the busy

indicator identifies the state of the module processor and if it is available for external commands. When

a command is executing, SPI access is not allowed, and the device is in a busy state. After this process

completes, whether a command or a record, the SPI is released, and the BUSY pin is set to logic high state.

Note that there is one exception to SPI port access while in the busy state, a capture can be terminated

by writing the unique 16-bit escape code, 0x00E8, to the GLOB_CMD register.

6

7

OUT_VDDM Output Power Supply Monitor (Digital Output). This pin is logic low when temperature exceeds threshold and

automatic shutdown occurs.

Input

Hardware Reset, Digital Input Only, Active Low. This pin enters the device in a known state by resetting

the microcontroller. This pin also loads the user configurable parameters from flash memory.

RST

8

9

10

11

12

VDD

GND

DIN

Supply Power Supply.

Supply Ground.

Input

SPI, Data Input Line.

DOUT

Output SPI, Data Output. DOUT is an output when CS is low. When CS is high, DOUT is in a three-state, high

impedance mode.

13

14

SCLK

CS

Input

SPI, Serial Clock.

SPI, Chip Select.

Rev. 0 | Page 7 of 42

ADcmXL1021-1

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

1000

100

10

1000

100

10

1

100

1k

10k

100k

1M

1

10

100

FREQUENCY (Hz)

Figure 7. Noise Density, Wideband, MTC, AVG_CNT = 0

Figure 10. Noise Density, Low Frequency, RTS Mode

25

20

15

10

5

3

2

1

0

–1

–2

–3

0

–5

–10

100

1k

10k

FREQUENCY (Hz)

AMBIENT TEMPERATURE (°C)

Figure 11. Sensitivity Error vs. Ambient Temperature, Normalized at 25°C

Figure 8. Relative Response, RTS Mode at 25°C

1000

100

10

14

12

10

8

6

4

2

0

–2

–4

–6

–8

–10

–12

–14

1

100

1k

10k

100k

1M

FREQUENCY (Hz)

AMBIENT TEMPERATURE (°C)

Figure 9. Noise Density, Wideband, RTS Mode

Figure 12. Normalized Offset vs. Ambient Temperature, Normalized at 25°C

Rev. 0 | Page 8 of 42

Data Sheet

ADcmXL1021-1

35

30

25

20

15

10

5

35

30

25

20

15

10

5

0

CURRENT (mA)

Figure 13. Operating Mode Current Distribution at 3.0 V Supply

Figure 16. Sleep Mode Current Distribution at 3.0 V Supply

60

50

40

30

20

10

0

25

20

15

10

5

0

CURRENT (mA)

Figure 14. Operating Mode Current Distribution at 3.3 V Supply

Figure 17. Sleep Mode Current Distribution at 3.3 V Supply

30

25

20

15

10

5

35

30

25

20

15

10

5

0

CURRENT (mA)

Figure 15. Operating Mode Current Distribution at 3.6 V Supply

Figure 18. Sleep Mode Current Distribution at 3.6 V Supply

Rev. 0 | Page 9 of 42

ADcmXL1021-1

Data Sheet

0

–10

–20

–30

–40

–50

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

10

20

30

40

50

60

70

80

90 100 110

0

10

20

30

40

50

60

70

80

90 100 110

FREQUENCY (kHz)

Figure 19. Digital Filter Frequency Response of the 1 kHz Low-Pass Filter

Figure 22. Digital Filter Frequency Response of the 1 kHz High-Pass Filter

0

–10

–20

–30

–40

–50

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

10

20

30

40

50

60

70

80

90 100 110

0

10

20

30

40

50

60

70

80

90 100 110

FREQUENCY (kHz)

Figure 20. Digital Filter Frequency Response of the 5 kHz Low-Pass Filter

Figure 23. Digital Filter Frequency Response of the 5 kHz High-Pass Filter

0

–10

–20

–30

–40

–50

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

10

20

30

40

50

60

70

80

90 100 110

0

10

20

30

40

50

60

70

80

90 100 110

FREQUENCY (kHz)

Figure 21. Digital Filter Frequency Response of the 10 kHz Low-Pass Filter

Figure 24. Digital Filter Frequency Response of the 10 kHz High-Pass Filter

Rev. 0 | Page 10 of 42

Data Sheet

ADcmXL1021-1

THEORY OF OPERATION

The ADcmXL1021-1 is a single axis, vibration monitoring

subsystem that includes a wide bandwidth, low noise MEMS

accelerometer, an analog-to-digital converter (ADC), high

performance signal processing, data buffers, record storage,

and a user interface that easily interfaces with most embedded

processors. See Figure 25 for a basic signal chain. The subsystem is

housed in an aluminum module that is mounted using four screws

(accepts screw size M2.5) and is designed to be mechanically stable

beyond 40 kHz. The combination of this mechanical mounting

and oversampling ensures that aliasing artifacts are minimized.

The moving component of the sensor is a polysilicon surface-

micromachined structure built on top of a silicon wafer. Poly-

silicon springs suspend the structure over the surface of the

wafer and provide a resistance against acceleration forces.

Deflection of the structure is measured using differential

capacitors that consist of independent fixed plates and plates

attached to the moving mass. Acceleration deflects the structure

and unbalances the differential capacitor, resulting in a sensor

output with an amplitude proportional to acceleration. Phase

sensitive demodulation determines the magnitude and polarity

of the acceleration.

MEMS

SIGNAL

USER

INTERFACE

ADC

SENSOR

PROCESSING

ANCHOR

MOVABLE

FRAME

PLATE

CAPACITORS

BUFFER/RECORDS

Figure 25. Basic Signal Chain

FIXED

PLATES

The ADcmXL1021-1 has a high operating input range of 50 g

and is suitable for vibration measurements in high bandwidth

applications, such as vibration analysis systems that monitor

and diagnose machine or system health. User configurable internal

processing supports both time domain and frequency domain

calculations.

UNIT SENSING

CELL

UNIT

FORCING

CELL

MOVING

PLATE

The low noise and high frequency bandwidth enable the

measurement of both repetitive vibration patterns and single

shock events caused by small moving parts, such as internal

bearings. The high g range provides the dynamic range used in

high vibration environments, such as heating, ventilation, and air

conditioning systems (HVAC), and heavy machine equipment. To

achieve best performance, be aware of system noise, mounting, and

signal conditioning for the particular application.

ANCHOR

Figure 26. MEMS Sensor Diagram

SIGNAL PROCESSSING

The signal chain of the ADcmXL1021-1 includes a wideband

accelerometer, a low-pass analog filter with a 13.5 kHz cutoff

frequency, an oversampling ADC (sampling at 220 kSPS), a

microcontroller, and discrete components to provide a flexible

vibration monitor subsystem that supports multiple processed

output modes. There are four modes of operation. One mode

of operation is the full rate RTS output. The three other modes

include system level signal processing: manual FFT mode (MFFT),

automatic FFT mode (AFFT), and manual time capture (MTC)

mode

Proper mounting is required to ensure full mechanical transfer

of vibration to accurately measure the desired vibration. A

common technique for high frequency mechanical coupling is

to use a combination of a threaded screw mount system and

adhesive where possible. For lower frequencies (below the full

capable bandwidth of the sensor), it is possible to use magnetic or

adhesive mounting. Proper mounting techniques ensure accurate

and repeatable results that are not influenced by measurement

system mechanical resonances and/or damping at the desired

frequencies and represents an efficient and proper mechanical

transfer to the system being monitored.

MTC mode supports 4096 consecutive time domain samples to

which averaging, finite impulse response (FIR), and windowing

signal processing can be enabled, along with the calculation of

statistics, alarm configuring, and monitoring. In MTC mode, the

raw time domain data is made available in register buffers for the

user to access and externally process.

CORE SENSORS

The ADcmXL1021-1 uses one ADXL1002 MEMS accelerometer,

with the sensing axis aligned with the axis of interest. Figure 26

is a simple mechanical diagram that shows how MEMS

accelerometers translate linear acceleration to representative

output signals.

In both FFT modes, MFFT and AFFT modes support the process

of calculating an FFT of the current time domain record.

A continuous RTS mode bypasses all device digital

computations and alarm monitoring, outputting real-time data

over the SPI in burst data output format (see Figure 5).

Rev. 0 | Page 11 of 42

ADcmXL1021-1

Data Sheet

digital processing is complete, the 4096 time domain sample

data record of vibration data is stored into the user data buffers,

using the signal flow diagram shown in Figure 28.

MODES OF OPERATION

The ADcmXL1021-1 supports four different modes of

operation: RTS, MTC, MFFT, and AFFT. Users can select the

mode of operation by writing the corresponding code to the

REC_CTRL register, Bits[1:0] (see Table 47).

Capturing is triggered by either a SPI write to the GLOB_CMD

register or by an external trigger. The ADcmXL1021-1 toggles

the output

when the data record is stored and the alarms

BUSY

are checked.

In three of these modes (MFFT, AFFT, and MTC), the

ADcmXL1021-1 captures, analyzes, and stores vibration data

in discrete events, known as capture events, and generates a record.

Each capture event concludes with storing the data as configured

in REC_CTRL register in the user data buffers, which are

accessible through the BUF_PNTR register (see Table 35).

The decimation filter reduces the effective rate of stored data

capture in the time record by averaging the sequential samples

together and filtering out of band signal and noise. This filter

has eight decimation rate settings (1, 2, 4, 8, 16, 32, 64, and 128)

and can support up to four different settings. These time data

records are time continuous captures with the decimation filter

acting on real-time data from the ADC to produce 4096 samples

(producing the 4096 time domain samples requires 2^Nsamples to

be processed internally, where N is the average count value, AVG_

CNT). When more than one user configured sample record setting

is in use, the ADcmXL1021-1 applies a single filter for each data

record and cycles through all desired options, one for each data

capture. Time statistic alarms can be configured for three levels

of reporting: normal, critical, and warning. A record mode option

allows all enabled time domain statistics to be stored, depending

on user preference, and is configured by setting the record

mode in Register REC_CTRL, Bits[3:2] (Register 0x1A and

Register 0x1B) = 0b10.

The two different FFT modes that produce vibration data in

spectral terms are MFFT and AFFT. The difference between

these two modes is the manner in which data capture and analysis

starts. In MFFT mode, users trigger a capture event by an external

digital signal or through a software command using the GLOB_

CMD register, Bit 11 (see Table 73). In AFFT mode, an internal

timer automatically triggers additional spectral record captures

without the need for an external trigger. Up to four different

sample rate profiles can be selected for the modes to cycle

through. The REC_PRD register (see Table 49) contains the

user configuration settings for the time that elapses between

each capture event when operating in the AFFT mode.

MTC Mode

When operating in MTC mode, the ADcmXL1021-1 captures

4096 consecutive time domain samples. An offset null signal

can be calculated and applied to the data using the command

register option. Signal processing functions such as low-pass

and high-pass FIR filtering and averaging can be applied. After

TIME

RECORD

N = 4096

CALCULATE STATUS/

CHECK ALARMS

DECIMATION

FILTER

DATA

BUFFER

Figure 27. Signal Processing Diagram for Manual Time Capture (MTC) Mode

USER

DECIMATION

FILTER

FIR

FILTER

32 TAPS

MEMS

SENSOR

DATA

STAT

HEADER

STATISTICAL ANALYSIS/

STATS ALARM CHECK

ADC

BUFFER

N = 4096

f_S÷ D

REGISTERS:

FILT_CTRL

FIR_COEFF_xxx

f_S= 220kSPS

REGISTER:

AVG_CNT

REGISTERS:

OUT_BUF

REGISTERS:

STAT

STAT_PNTR

NULL

REGISTERS:

ANULL

GLOB_CMD

Figure 28. MTC Signal Flow Diagram

Rev. 0 | Page 12 of 42

Data Sheet

ADcmXL1021-1

MFFT Mode

RTS Mode

MFFT mode can manually trigger a capture to create a single FFT

record with 2048 bins and allows various configuration options.

The ADcmXL1021-1 has configurable high-pass and low-pass

filters, decimation filtering, FFT averaging, and spectral alarms.

The ADcmXL1021-1 also has options to calculate velocity, apply

windowing, and apply offset compensation. MFFT mode is

configured by setting the record mode in Register REC_CTRL,

Bits[1:0] (Register 0x1A and Register 0x1B) = 0b00.

RTS mode is configured by setting the record mode in

Register REC_CTRL, Bits[1:0] (Register 0x1A and Register 0x1B) =

0b11.

When operating in RTS mode, the ADcmXL1021-1 samples the

accelerometer at a rate of 220 kSPS and makes this data

available through a burst pattern via the SPI.

DATA RECORDING OPTIONS

The ADcmXL1021-1 creates data records in FFT and MTC

modes and supports three methods of data storage for each data

record: immediate only, alarm triggered, and all mode. In MTC

mode, the time domain statistics are stored and are not the time

records.

Processing steps collect 4096 consecutive time domain samples and

filters the data similar to the MTC case. Additional windowing and

FFT averaging can be enabled and configured using the

4096 sample burst captures. The ADcmXL1021-1 provides

three different mathematical filtering options to processes the

time record data, prior to performing an FFT, the filter options

are rectangular, Hanning, or flat top. See the REC_CTRL

register in Table 47 for more information on selecting the window

option.

When immediate only mode is selected, only the most recent

capture data record is retained and accessible.

In alarm triggered mode, only data that triggered an alarm is

stored. When an alarm event is triggered, the ADcmXL1021-1

stores the header registers and the FFT data to flash memory.

Alarm triggered mode is helpful for continuous operation while

minimally impacting the limited endurance of the flash memory.

When a capture event is triggered by the user, the event follows

the process flow diagram shown in Figure 29. The FIR filter has

32 coefficients and processes at the full internal ADC sample

rate of 220 kSPS. Users can select from one of six FIR filter bank

options. Three of these filter banks have preset coefficients that

provide low-pass responses to support half power bandwidths of

1 kHz, 5 kHz, and 10 kHz, respectively. The other three filter

banks have preset coefficients that provide high-pass responses to

support half power bandwidths of 1 kHz, 5 kHz, and 10 kHz filter.

All six filter banks can be overwritten through user programming

and stored to flash memory.

In all mode, each data record is stored. The data stored includes

FFT header information and FFT data. Up to 10 FFT records

can be stored and retrieved.

The ADcmXL1021-1 samples, processes, and stores vibration

data to the FFT or the MTC data. In MTC mode, the record

contains 4096 samples. In MFFT mode and AFFT mode, each

record contains the 2048 bin FFT results. Table 6 describes the

registers that provide access to processed sensor data.

After the FIR filter is applied to the time domain data, if enabled,

the data is decimated according to the AVG_CNT setting until a

full 4096 time sample capture fills the data buffer. This decimation

produces a time record that is converted to a spectral record and

averaged, depending on the FFT_AVG1 or the FFT_AVG2 setting,

as appropriate (see Figure 41 for the FFT capture datapath and

appropriate registers).

Table 6. Output Data Registers

Register

Address

Description

TEMP_OUT

SUPPLY_OUT

BUF_PNTR

REC_PNTR

OUT_BUF

0x02

0x04

0x0A

0x0C

0x12

Internal temperature measurement

Internal power supply measurement

Data buffer index pointer

FFT record index pointer

Accelerometer data buffer

TIME

RECORD

N = 4096

DECIMATION

FILTER

FFT AND

AVERAGING

DATA

BUFFER

FIR

GLOB_CMD

TIME_STAMP_L 0x4C

TIME_STAMP_H 0x4E

0x3E

Global command register

Timestamp, lower word

Timestamp, upper word

Figure 29. Signal Processing Diagram for FFT Modes

AFFT Mode

REC_INFO1

REC_INFO2

0x66

0x68

FFT record header information

AFFT mode is configured by setting the record mode in Register

REC_CTRL, Bits[1:0] (Register 0x1A and Register 0x1B) = 0b01.

AFFT mode supports the same functionality as MFFT mode,

except AFFT mode automatically advances and independently

controls new capture events. New capture events are triggered

periodically and are configured in the register map using

REC_PRD.

To save power for long off time durations, the device can be

configured to sleep between auto captures using Bit 7 in the

REC_CTRL register.

Rev. 0 | Page 13 of 42

ADcmXL1021-1

Data Sheet

Reading Data from the Data Buffer

Accessing FFT Record Data

After completing a spectral record and updating each data buffer,

the ADcmXL1021-1 loads the first data sample from each data

buffer to the OUT_BUF registers (see Table 11) and sets the buffer

index pointer in the BUF_PNTR register to 0x0000 (see Table 7).

The index pointer determines which data samples load to the

OUT_BUF registers. For example, writing 0x009F to the

BUF_PNTR register (DIN = 0x8A9F, DIN = 0x8B00) causes the

160th sample in each data buffer location to load to the OUT_BUF

registers. The index pointer automatically increments with each

OUT_BUF read command, which causes the next set of capture

data to load to each capture buffer register. This automatic

increment enables an efficient method for reading all 4096 time

samples or 2048 FFT points in a record, using sequential read

commands, without needing to manipulate the BUF_PNTR

register.

Up to 10 FFT records can be stored in flash memory. The REC_

PNTR register (see Table 8) and GLOB_CMD bit (Bit 13, see

Figure 31) provide access to the FFT records.

The process when FFT averaging is enabled is as follows:

1. A capture is initiated.

2. Time domain samples are captured and filtered according

to AVG_CNT setting until 4096 time samples fill the

buffer.

3. The FFT is calculated from the time samples in the buffer

and the record is stored.

4. After the number of FFT averages is reached, all FFT

records in memory are averaged and stored.

5. Alarms are checked, flags are set, and the data record is

stored as per configuration

6. In either manual or automatic mode, the next sample rate

option is set.

DATA IN BUFFERS LOAD INTO

USER OUTPUT REGISTERS

7. The

signal is set.

BUSY

OUT_BUF

An FFT record is an FFT stored in flash, and an FFT capture is

an FFT stored in RAM.

0

BUF_PNTR

ACCELEROMETER

Table 8. REC_PNTR (Base Address = 0x0C), Read/Write

TIME/FFT

BUFFER

Bits

Description (Default = 0x0000)

Time statistic record pointer address

FFT record number pointer address

4096/2048

[12:8]

[3:0]

TIME/FFT ANALYSIS

FFT

RECORD

0

FFT

RECORD

1

FFT

RECORD

m

FFT

RECORD

9

SUPPLY_OUT

TEMP_OUT

m = REC_PNTR

GLOB_CMD, BIT 13 = 1

INTERNAL SAMPLING SYSTEM SAMPLES, PROCESSES, AND

STORES DATA IN FFT BUFFERS

Figure 30. Data Buffer Structure and Operation

SPI

REGISTERS

Table 7. BUF_PNTR (Base Address = 0x0A), Read/Write

FFT

BUFFER

Bits

Description (Default = 0x0000)

[15:12]

[11:0]

Not used

Figure 31. FFT Record Access

Data bits; range = 0 to 2047 (FFT), 0 to 4095 (time)

MTC Data Format

In MTC mode, the OUT_BUF register contains a single time

domain sample. When reading OUT_BUF, BUF_PNTR

automatically advances from 0 to 4095. The time domain data is

16-bit, twos complement acceleration data by default with a

resolution of 1 LSB = 1.907 mg. If velocity data is selected by

setting REC_CTRL, Bit 5 = 1, velocity data is stored in the

buffer registers instead. Velocity data has a resolution of 1 LSB =

18.62 mm/sec and is calculated by integrating the acceleration data.

Rev. 0 | Page 14 of 42

Data Sheet

ADcmXL1021-1

Table 11 lists the bit assignments for the OUT_BUF register. The

acceleration data format depends on the record type setting in the

REC_CTRL register. Table 41 and Table 42 shows data formatting

examples for the 16-bit, twos complement format used in manual

time mode.

The magnitude (out) can be calculated from the value read by

using the following equation:

OUT _ BUF

2048















2^^

Out =

× 0.9535 mg

Number of FFT Averages









In MTC mode, time domain statistic can be calculated by enabling

Bit 6 in the REC_CTRL register. The statistics value scales are

calculated based on setting of accelerometer or velocity. The time

domain statistics available are mean, standard deviation, peak,

peak-to-peak, crest factor, Kurtosis, and skewness. The scale of

all statistics are consistent with the data format selected (1 LSB

= 1.907 mg or 18.62 mm/sec for acceleration or velocity,

respectively), except crest factor, Kurtosis, and skew, which

require fractional numbers.

Table 12 and Table 43 show the data formatting examples for FFT

mode conversions from the OUT_BUF value to acceleration.

When reading the OUT_BUF register, BUF_PNTR automatically

advances from 0 to 2047. The FFT data is unsigned 16-bit data.

Table 12. FFT Magnitude Conversion from Register Value,

Data Format Examples

FFT

FFT Buffer Read Value (Bits)

0x0001

0x0002

0x00FF

0x7D00

0x0001

0x0002

0x00FF

0x0005

0x05FF

0x7530

0x00FF

0x7D00

Averages

Magnitude

0.953823 mg

0.954146 mg

1.039447 mg

48.18528 g

0.476911 mg

0.477073 mg

0.519724 mg

0.238779 mg

0.400762 mg

6.121809 g

Table 9. MTC Mode, 50 g Range, Data Format Examples

Acceleration (mg)

1

2

4

8

(1.907 mg/LSB)

+62486.7

+12498.5

+3.9

LSB

Hex.

Binary

+32,767 0x7FFF

+6554

+2

0111 1111 1111 1111

0001 1001 10011010

0000 0000 0000 0010

0000 0000 0000 0001

0000 0000 0000 0000

1111 1111 1111 1111

1111 1111 1111 1110

1110 0110 0110 0110

1000 0000 0000 0000

0x199A

0x0002

0x0001

0x0000

0xFFFF

0xFFFE

0xE666

+1.9

+1

0

−1.9

−1

−3.8

−2

−12498.5

−62488.6

−6554

−32,768 0x8000

0.129931 mg

6.02316 g

Table 10. MTC Mode, 50 g Range, Data Format Examples,

Configured for Optional Velocity Output Mode

Velocity (mm/sec),

0x7D00

0xAFCE

16

128

3.01158 g

30.65768 g

LSB = 18.62 mm/sec

+610,121.5

+122,035.5

+37.24

+18.62

0

−18.62

−37.24

−122,035.5

−610,121.5

LSB

Hex.

Binary

RTS Data Format

+32,767 0x7FFF

+6554

+2

+1

0

0111 1111 1111 1111

In RTS mode, continuous data is burst out of the SPI. Each data

frame consists of 16 samples of accelerometer data plus eight

words of zeros and a frame header, temperature reading, status

bits, and a 16-bit cyclical redundancy check (CRC) code. Each

data sample is 16-bit, twos complement acceleration data by

default with a resolution of 1 LSB = 1.907 mg. It is important that

the external host device is able to retrieve the burst data in a

sufficient time allotment, which is approximately 135 µs per data

frame. No internal corrections are applied to this data. Therefore,

the data may deviate from the results of other capture modes. Data

is unsigned and must be offset (subtract) by 0x8000 to obtain g

(signed data).

0x199A 0001 1001 10011010

0x0002

0x0001

0x0000

0xFFFF

0xFFFE

0xE666

0000 0000 0000 0010

0000 0000 0000 0001

0000 0000 0000 0000

1111 1111 1111 1111

1111 1111 1111 1110

1110 0110 0110 0110

1000 0000 0000 0000

−1

−2

−6554

−32,768 0x8000

Table 11. OUT_BUF (Base Address = 0x12), Read Only

Bits

Description (Default = 0x8000)

[15:0]

Output acceleration data buffer register. Format = twos

complement (time), unsigned integer (FFT).

When first entering RTS mode capture, the first eight samples are

all 0s and the CRC for the first frame is invalid. It is recommended

that the first data frame be ignored, and data for the second frame

and all subsequent frames be used.

FFT Data Format for AFFT and MFFT Modes

In both AFFT and MFFT modes, the OUT_BUF contains a

calculated FFT bin magnitude. The values contained in buffer

locations from 0 to 2047 represent the magnitude of frequency

bins of size, depending on the AVG_CNT value as shown in

Table 18.

Rev. 0 | Page 15 of 42

ADcmXL1021-1

Data Sheet

I/O LINES ARE COMPATIBLE WITH

3.3V LOGIC LEVEL

Table 13 shows several examples of how to translate RTS data

values, assuming nominal sensitivity and zero bias error.

VDD

3.3V

8

Table 13. RTS Mode Data Format Examples

SYSTEM

PROCESSOR

SPI MASTER

ADcmXL1021-1

Acceleration (g)

+62.532

+50

LSB

Hex.

Binary

14

13

11

12

2

SS

SCLK

MOSI

MISO

IRQ2

IRQ1

CS

65,535

58,967

32,770

32,769

32,768

32,767

32,766

6567

0xFFFF

1111 1111 1111 1111

SCLK

DIN

0xE657 1110 0110 0101 0111

0x8002 1000 0000 0000 0010

0x8001 1000 0000 0000 0001

0x8000 1000 0000 0000 0000

0x7FFF 0111 1111 1111 1111

0x7FFE 0111 1111 1111 1110

0x19A7 0001 1001 1010 0111

0x0000 0000 0000 0000 0000

+0.003816

+0.001908

0

DOUT

ALM1

ALM2

SYNC/RTS

BUSY

RST

4

−0.001908

−0.003816

−50

3

5

7

−62.534

0

GND GND GND

1

9

10

USER INTERFACE

Figure 32. Electrical Hookup Diagram

The user interface includes several important functions: a data

communications port, a trigger input, a busy indicator, and two

alarm indicator signals.

The register structure uses a paged addressing scheme that

contains seven pages, with each page containing 64 register

locations. Each register is 16 bits wide, with each 2-byte word

having its own unique address within the memory map of that

page. The SPI port has access to one page at a time. Select the

page to activate for SPI access by writing the corresponding

code to the PAGE_ID register. Read the PAGE_ID register to

determine which page is currently active. Table 14 displays the

PAGE_ID contents for each page and the basic functions. The

PAGE_ID register is located at Address 0x00 on each page.

Data communication between an embedded processor (master)

and the ADcmXL1021-1 takes place through the SPI, which

includes the , SCLK, DIN, and DOUT pins (see Table 5).

CS

The SYNC/RTS (see Table 5) pin provides user triggering options

in manual triggering modes. The alarm pins, ALM1 and ALM2,

are configurable to alert the user of an event that exceeds a user

defined threshold of a parameter.

The SYNC/RTS pin is used in RTS mode to support start and

Table 14. User Register Page Assignments

stop control over data capture and analysis operations. The

BUSY

Page No.

PAGE_ID

Function

pin (see Table 5) provides an indication of internal operation when

the ADcmXL1021-1 is executing a command. This signal helps

the master processor avoid SPI communication when the

ADcmXL1021-1 cannot support a response and can trigger an

external data acquisition after data capture and analysis events

are complete.

0

1

2

3

4

5

6

0x00

0x01

0x02

0x03

0x04

0X05

0x06

Configuration, data acquisition

FIR Filter Bank A

FIR Filter Bank B

FIR Filter Bank C

FIR Filter Bank D

FIR Filter Bank E

FIR Filter Bank F

The ADcmXL1021-1 uses an SPI for communication, which

enables simple connection with most embedded processor

platforms, as shown in Figure 32.

The factory default configuration for the

pin provides a busy

BUSY

indicator signal that transitions high when an event completes and

data is available for user access and remains low during processing.

Table 15. Generic Master Processor Pin Mnemonics and

Functions

Pin Mnemonic

Function

Slave select

SS

SCLK

Serial clock

MOSI

MISO

IRQ1, IRQ2

Master output, slave input

Master input, slave output

Interrupt request inputs (optional)

The ADcmXL1021-1 SPI supports full duplex serial communication

(simultaneous transmit and receive) and uses the bit sequence

shown in Figure 36. Table 16 shows a list of the most common

settings that control the operation of SPI-compatible ports in most

embedded processor platforms.

Rev. 0 | Page 16 of 42

Data Sheet

ADcmXL1021-1

Embedded processors typically use control registers to configure

serial ports for communicating with SPI slave devices, such as

the ADcmXL1021-1. Table 16 lists settings that describe the SPI

protocol of the ADcmXL1021-1. The initialization routine of the

master processor typically establishes these settings using firmware

commands to write them into the serial control registers.

SPI Write Commands

User control registers govern many internal operations. The

DIN bit sequence in Figure 36 provides a description to write to

these registers. Each configuration register contains 16 bits (two

bytes). Bits[7:0] contain the low byte, and Bits[15:8] contain the

high byte of each register. Each byte has a unique address in the

user register map (see Table 19). Updating the contents of a

register requires writing both bytes in the following sequence:

low byte first, high byte second. There are three parts to coding

a SPI command (see Figure 36) that write a new byte of data to

Table 16. Generic Master Processor SPI Settings

Processor Setting

Description

Master

SCLK Rate ≤ 14 MHz

SPI Mode 3

ADcmXL1021-1 operates as slave

Bit rate setting

Clock polarity/phase (CPOL = 1, CPHA = 1)

Bit sequence

R

a register: the write bit ( /W = 1), the address of the byte [A6:A0],

followed by the new data for that register address [DC7:DC0].

MSB First

Figure 34 provides a coding example for writing 0x2345 to

the FFT_AVG1 register, the 0x8623 command writes 0x23 to

Address 0x06 (lower byte) and the 0x8745 command writes

0x45 to Address 0x07 (upper byte).

16-Bit Mode

Readout Formatting

Shift register/data length

Little Endian

Table 19 lists user registers with lower byte addresses. Each

register consists of two bytes. Each byte has a unique 7-bit

address. Figure 33 relates the bits of each register to the upper

and lower addresses.

CS

SCLK

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

DIN

0x8623

0x8745

UPPER BYTE

LOWER BYTE

Figure 34. Single SPI Write Command

Figure 33. Generic Register Bit Definitions

SPI Read Commands

Register Structure

A single register read requires two 16-bit SPI cycles that use the

bit assignments shown in Figure 36. The beginning sequence

All communication with the ADcmXL1021-1 involves accessing

the user registers. The register structure contains both output data

and control registers. The output data registers include the latest

sensor data, alarm information, error flags, and identification data.

The control register contained in Page 0 includes configurable

options, such as time domain averaging, FFT averaging,

filtering, alarm parameters, diagnostics, and data collection

mode settings. Each user accessible register has two bytes

(upper and lower), and each byte has a unique address. See

Table 19 for a detailed list of all user registers, along with the

corresponding addresses.

R

sets /W = 0 and communicates the target address (Bits[A6:A0]).

Bits[DC7:DC0] are don’t care bits for a read DIN sequence.

DOUT clocks out the requested register contents during the

second sequence. The second sequence can also use DIN to set

up the next read.

Figure 35 provides an example that includes two register reads in

succession. This example starts with DIN = 0x0C00 to request the

contents of the REC_PNTR register, and follows with 0x0E00, to

request the contents of the OUT_BUF register. The sequence in

Figure 35 also shows the full duplex mode of operation, which

means that the ADcmXL1021-1 can receive requests on DIN

while also transmitting data out on DOUT within the same

16-bit SPI cycle.

All communication between the ADcmXL1021-1 and an

external processor involves either reading or writing these

16-bit user registers.

DIN

0x0C00

0x0E00

DOUT

REC_PNTR

OUT_BUF

Figure 35. SPI Mulitbyte Read Command Example

CS

SCLK

DIN

R/W A6

A5

R/W A6

A5

A4

A3

A2

A1

D9

A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

DOUT

D15 D14 D13 D12 D11 D10

D8

D7

D6

D5

D4

D3

D2

D1

D0

D15 D14 D13

NOTES

1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.

2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE

FOR OTHER DEVICES.

Figure 36. SPI Communication, Multibyte Sequence

Rev. 0 | Page 17 of 42

ADcmXL1021-1

Data Sheet

Busy Signal

The RTS burst contains 44 16-bit words (8 zero words, a header,

including an incrementing counter, 32 accelerometer data

words, temperature, status, and CRC). The external SCLK rate

must be between 8 MHz to 14 MHz to ensure that the complete

burst is read out before current data in the register buffer is

overwritten. The maximum SCLK for RTS burst outputs is

14 MHz 1%. The minimum SCLK required to support the

transfer is 8 MHz. The RTS burst response uses the sequencing

diagrams shown in Figure 4 and Figure 5 and the data format

shown in Table 17.

The factory default configuration provides the user with a busy

signal (

) that pulses low when the output data registers are

BUSY

updating (see signal orientation of busy signal in Figure 37). In

this configuration, connect to an interrupt service pin on

BUSY

the embedded processor, which triggers data collection, when

this signal pulses high.

SPI

COMMAND

BUSY

When first entering RTS mode capture, the first eight samples are

all 0s, and the CRC for the first frame is invalid. It is recommended

that the first frame be ignored, and that the data for the second

frame and all subsequent frames be used.

AVAILABLE

NOT AVAILABLE

BUSY

Figure 37. Busy Signal (

) Orientation After SPI Command

During the start-up and reset recovery processes, the

BUSY

signal can exhibit some transient behavior before data production

begins. Figure 37 provides an example of the behavior

Table 17. RTS Data Format

Byte Location in

BUSY

during command processing. A low signal indicates SPI access

is not available with the exception of the escape code that can

terminate a capture. Figure 38 shows the

Output Dataset

2-Byte Value Represents

0

0x0000

…

0x0000

signal during

BUSY

…

14

16

start up.

Fixed header: 0xccAD; where cc is an

incrementing counter value from 0x00 to

0xFF, which returns to 0x00 after 0xFF

TIME THAT VDD > 3V

VDD

MICROCONTROLLER IS BUSY

WHEN BUSY IS LOW

18

20

22

…

80

82

84

86

XL1 (oldest data from accelerometer)

XL2

XL3

…

BUSY

XL32

START-UP TIME

~200ms

Temperature

Status

CRC-16

BUSY

Figure 38.

Response During Start Up

RTS

The RTS function provides a method for reading data (time

domain acceleration data, temperature, status, and CRC code) that

does not require a stall time between each 16-bit segment and

only requires one command on the DIN line to initiate. System

processors can execute this mode by reading each segment of data

in the response, while holding the

line in a low state until

CS

after reading the last 16-bit segment of data. If the

line goes high

CS

before the completion of all data acquisition, the data from that

read request is lost.

Rev. 0 | Page 18 of 42

Data Sheet

ADcmXL1021-1

BASIC OPERATION

DEVICE CONFIGURATION

TRIGGER

Each register contains 16 bits (two bytes). Bits[7:0] contain the

low byte, and Bits[15:8] contain the high byte. Each byte has a

unique address in the user register map (see Table 19). Updating

the contents of a register requires writing to the low byte first

and the high byte second. There are three parts to coding a SPI

command, which writes a new byte of data to a register: the

All modes, including RTS mode, require a trigger to start. AFFT

mode and RTS mode also require a trigger to stop recording.

Start triggers arise either from using the SYNC/RTS digital input

pin or by setting Bit 11 in the GLOB_CMD register (see Table 73).

If using the SYNC/RTS pin as a trigger, the user must set Bit 12

in the MISC_CTRL register = 1 to enable this feature. While in

RTS mode, during a valid capture period, normal SPI access is

disabled until a valid stop is received.

R

write bit ( /W = 1), the 7-bit address code for the byte that this

command is updating, and the 16 bits of new data for that

location.

The user can stop a capture in RTS mode in two ways: via a

hardware pin or using software. The hardware pin method

uses the RTS pin, which is enabled in Bit 12 of the MISC_CTRL

register. The software method requires the user to set Bit 15 in

the REC_CTRL register to 1, which enables timeout mode which

must be configured prior to initiating a capture. In this case,

RTS mode stops after 30 ms with no user supplied external

DUAL MEMORY STRUCTURE

The ADcmXL1021-1 uses a dual memory structure (see Figure 39)

with static random access memory (SRAM), supporting real-time

operation and flash memory storing operational code and user

configurable register settings. The manual flash update command

(Bit 6 in the GLOB_CMD register) provides a single command

method for storing user configuration settings to flash memory for

automatic recall during the next power-on or reset recovery

process. During power-on or reset recovery, the ADcmXL1021-1

performs a CRC on the SRAM and compares this result to a CRC

computation from the same memory locations in flash memory.

If this memory test fails, the ADcmXL1021-1 resets and boots up

from the other flash memory location. The ADcmXL1021-1

provides an error flag for detecting when the backup flash

memory supported the last power-on or reset recovery. Table 19

shows a memory map for the user registers in the ADcmXL1021-

1, which includes flash backup support (indicated by yes or no

in the flash column).

readback clocks with

low. To restart RTS mode, use the

CS

normal start trigger options described in this section.

To stop a capture in AFFT mode, the user must issue a stop

command during a period when

is high (

is low

BUSY

when the device is configured for power saving mode and

sleeps between captures) or by write an escape code to the

device at any time. All other SPI writes are ignored. When

the ADcmXL1021-1 is in between active collecting periods (as

configured in the REC_PRD register), setting Bit 11 in the

GLOB_CMD register (see Table 73) to 1 (DIN = 0xBF08)

interrupts the operation and the ADcmXL1021-1 returns to

operating in the idle state. The REC_PRD counter starts at the

beginning of the capture and must be set to a period greater

than the longest capture time if multiple rate options (Sample

Rate 0 to Sample Rate 3) are enabled.

MANUAL

FLASH

BACKUP

NONVOLATILE

FLASH MEMORY

VOLATILE

SRAM

When operating in MFFT or MTC mode, the ADcmXL1021-1

operates in an idle state until it receives a command to start

collecting data. When the ADcmXL1021-1 is in this idle state,

setting Bit 11 in the GLOB_CMD register (see Table 73) to 1 starts

a data collection and processing event. An interruption of data

collection and processing causes a loss of all data from the

interrupted process. A positive pulse on the SYNC/RTS pin

provides the same start function as raising Bit 11 in the

GLOB_CMD register when operating in MFFT mode.

SPI ACCESS

(NO SPI ACCESS)

START-UP

RESET

Figure 39. SRAM and Flash Memory Diagram

POWER-UP SEQUENCE

The ADcmXL1021-1 requires only a single 3.3 V supply voltage

and supports communication with most 3 V compliant embedded

processor platforms using an SPI protocol. Avoid applying

voltage to the SYNC/RTS, , SCLK, and DIN input pins until

the proper supply voltage is applied to the module.

In cases with many averages, a capture event can last an extended

period with access to the SPI port (for example, when a device

stays in a busy state). In this case, an escape code is used to

terminate the active capture. The escape code is 0x00E8 and

is written to the GLOB_CMD register, using the two 16-bit

CS

The power ramp from 0 V to 3.0 V must be monotonic. The

module performs internal initialization, tests flash memory, and

performs a sensor self test after powering on. No SPI access is

allowed during this time. The module signals a completed

sequence 0xBEE8, followed by 0xBF00 and repeat until

BUSY

returns to a high logic state. A valid escape is also indicated in

Bit 4 of the DIAG_STAT register. After an escape is issued, any

data collected during the last capture is no longer valid. To

continue capturing data, refer to the normal start trigger options.

initialization by setting the

pin logic high.

BUSY

Rev. 0 | Page 19 of 42

ADcmXL1021-1

Data Sheet

data is stored in user accessible buffer, in place of the time

domain values, and spectral alarms are checked.

SAMPLE RATE

RTS mode has a fixed sample rate of 220 kSPS. The output is

streamed out in a burst data packet over the SPI communications

port. After the device is configured for RTS mode, conversion

starts and stops are controlled by the SYNC/RTS pin or by

stopping SPI activity for a period of time (see Bit 15 of the

REC_CTRL register). RTS mode is unique in that, when

configured, no additional processing is preformed and samples

are output directly from the ADC without null, filter, or digital

signal processing and alarms are not checked. A low-pass analog

filter with a 13.5 kHz cutoff frequency is always in the datapath

and, along with the high ADC sample rate, prevents aliasing.

An important note is that the execution of the retrieve record with

many FFT averages and a low sample rate may take minutes to

hours to complete. Because the device turns off SPI interrupts

during a recording, the user cannot send a stop command. Instead,

the device monitors the SPI receive buffer for the escape code, a SPI

write of 0x00E8 to the GLOB_CMD register, during the data

capture portion of the recording. Therefore, the user can escape

from a recording by writing 0x00E8 to the GLOB_CMD register.

It is recommended to write only 0x00E8 to the device, provide a

small delay, and then monitor the busy indicator or poll the status

register. Repeatedly send the 0x00E8 code and check the status

register until the status register shows the escape flag and busy

indicator/data ready flag.

For MTC mode, the sampling rate is always 220 kSPS and

captures 4096 samples. The module can be configured to perform

internal digital averaging.

DATAPATH PROCESSING

For the null function (see Figure 28), the user can write offset

correction values into the ANULL register (see Table 45). The

user can also initiate the autonull command via Bit 0 in the

GLOB_CMD register (see Table 73), which automatically

estimates the offset error and writes correction values to the

ANULL register. The autonull feature uses settings of SR3 to

capture and calculate a correction value and requires time to

complete.

For RTS mode, there is no digital processing of data internal to

the ADcmXL1021-1. Data is buffered internally to 32 sample

packets that are burst output over the SPI interface.

For MTC mode, AFFT mode, and MFFT mode, the initial

capture and processing procedure is the same and is as follows:

1. Capture 4096 consecutive time domain samples at 220 kSPS.

2. If AVG_CNT is enabled, apply the appropriate decimation

filter. Continue to collect data until 4096 time sample

buffer is filled.

3. Null data, if enabled.

4. Apply the FIR filter, if enabled.

The AVG_CNT register allows the selection of the number

of averages used in each capture for up to four sample rate

options. The REC_CTRL register selects which sample rate

options are enabled. The number of averages determines the

sample rate for each sample rate option by the following

equation:

If MTC mode is enabled, the remaining steps are required:

Sample Rate = 220 kHz/2^AVG_CNT[3:0]

5. Calculate the statistic values enabled.

6. Check the statistics against alarm settings.

7. Write the statistic values to the data buffer.

8. Calculate time domain statistics.

9. Check time domain alarms and set the alarm bit if

appropriate.

Table 18. FFT Bin Sizes, Frequency Limits (Hz)

Effective

AVG_CNT

Setting

(Averages)

Effective

Sample Rate, Bin Size,

Effective FFT

Maximum FFT

Frequency,

f_{_MAX}(Hz)

f_S(SPS)

220000

110000

55000

27500

13750

6875

f_{_MIN}(Hz)

53.71094

26.85547

13.42773

6.713867

3.356934

1.678467

0.839233

0.419617

10. Record statistic data according to the storage option

selected.

0 (1)

1 (2)

2 (4)

3 (8)

110000

55000

27500

13750

6875

3437.5

1718.75

859.375

11. Perform signal completion by setting the

pin.

BUSY

If AFFT or MFFT mode is enabled, the remaining steps occur

after the initial capture and processing:

4 (16)

5 (32)

6 (64)

7 (128)

5. Calculate the FFT based on the AVG_CNT setting.

6. Record data according to the storage option selected.

7. Check frequency domain alarms, set the alarm bit if

appropriate.

3437.5

1718.75

In MFFT mode and AFFT mode, each FFT data record starts

with a capture of 4096 time domain samples (after decimation,

if enabled), as with MTC mode. The data is processed with the

null function and FIR filter after the decimation filter, as with

MTC mode. An FFT calculation is performed on the data. This

8. Signal completion by setting the

pin.

BUSY

Rev. 0 | Page 20 of 42

Data Sheet

ADcmXL1021-1

USER

DATA

DECIMATION

FILTER

FIR

FILTER

32 TAPS

STATISTICAL

ANALYSIS/

ALARM CHECK

MEMS

SENSOR

STAT

HEADER

ADC

1

BUFFER

f_S÷ D

N = 4096

REGISTERS:

FILT_CTRL

FIR_COEFF_xxx

f_S= 220kSPS

REGISTER:

AVG_CNT

REGISTERS:

OUT_BUF

REGISTERS:

STAT

STAT_PNTR

NULL

REGISTERS:

ANNUL

GLOB_CMD

1

OPTIONAL VELOCITY CALCULATIONS APPLIED PRIOR TO USER BUFFER.

Figure 40. MTC Mode Datapath Processing

TIME

FAST

DECIMATION

FILTER

FIR

USER

DATA

BUFFERS

MEMS

SENSOR

WINDOW

FUNCTION

SPECTRAL

ALARMS

RECORD

CAPTURE

N = 4096

FOURIER

ADC

FILTER

TRANSFORM

32 TAPS

f_S÷ D

REGISTERS:

FILT_CTRL

FIR_COEFF_xxx

REGISTER:

REC_CTRL

f_S= 220kSPS

REGISTERS:

AVG_CNT

REGISTERS:

FFT_AVG1

FFT_AVG2

REC_INFO1

REC_INFO2

REGISTERS: REGISTERS:

OUT_BUF

ALM_CTRL

ALM_PNTR

FUND_FREQ

ALM_STAT

NULL

ALM_F_LOW ALM_PEAK

ALM_F_HIGH ALM_FREQ

ALM_MAG1

ALM_MAG2

ALM_S_MAG

REGISTERS:

ANNUL

GLOB_CMD

Figure 41. AFFT Mode and MFFT Mode Datapath Processing

After null corrections are applied, the data of the inertial sensor

passes through an FIR filter (using the FILT_CTRL register),

decimation filter (using the AVG_CNT register), and

windowing filter (using the REC_CTRL register), all of which

have user configurable attributes.

Decimation

Averaging options are available within the ADcmXL1021-1 and

reduce the amount of data required to be transferred for a given

bandwidth while also reducing random noise impact on the

signal to noise ratio. Decimation is set using the AVG_CNT

register and enabled in REC_CTRL register. The decimation

filter can be used when the module is configured for MTC,

MFFT, or AFFT operation but is not available in RTS mode.

Table 69 shows selectable sample rates and resulting FFT bin

width options.

The FIR filter includes six banks of coefficients with 32 taps

each. The FILT_CTRL register (see Table 65) provides the

configuration options for the use of the FIR filters of each

inertial sensor. Each FIR filter bank includes a preconfigured

filter, but the user can design filters and write over these values

using the register of each coefficient. Default filter configuration

options are either low-pass or high-pass filters with cutoff

frequencies of either 1 kHz, 5 kHz, or 10 kHz. Page 1 through

Page 6 define the six sets of FIR filter coefficients. Each page is

dedicated to a single filter. For example, Page 1 in the register

map provides the details for the 1 kHz low-pass FIR filter. These

filters represent typical cutoff frequencies for machine vibration

monitoring applications.

MTC mode, AFFT mode, and MFFT mode can be configured to

cycle automatically through up to four different AVG_CNT settings

(enabled in the REC_CTRL register): SR0, SR1, SR2, and SR3.

When more than one sample rate option is enabled (REC_

CTRL register, Bit 8 through Bit 11, see Table 47), the device

cycles through each one.

Windowing

There are three windowing options that can be applied to the

time domain recording before the FFT is computed. The typical

window for vibration monitoring is the Hanning window. This

window is provided as a default. A Hanning window is optimal

because it offers good amplitude resolution of the peaks between

frequency bins and minimal broadening of the peak. The

rectangular and flat top windows are also available because they

are common windowing options for vibration monitoring. The

rectangular window is a window of magnitude 1 providing a

flat time domain response. The flat top window is advantageous

because it can provide very accurate amplitudes with the

disadvantage of significant broadening of the peaks. This window is

useful when the magnitude accuracy of the peak is important.

FIR Filter

Six FIR filters are preprogrammed by default in memory and

available for use. The coefficients for these filters are stored in

Page 1 to Page 6 and provide selectable filter options for the

1 kHz, 5 kHz, or 10 kHz low-pass filter, and the 1 kHz, 5 kHz,

or 10 kHz high-pass filter. Users can write and store custom

filter setting by overwriting existing filter coefficients and

saving these values to flash memory.

Rev. 0 | Page 21 of 42

ADcmXL1021-1

Data Sheet

ALM_F_HIGH

ALM_MAG1

SPECTRAL ALARMS

ALM_F_LOW

When using MFFT mode or AFFT mode, six flexible alarms

can be configured with settings. There are 48 possible alarm

configurations considering there are six alarm bands (×4

sample rate options × 2 magnitude alarm levels).

ALM_MAG2

The ALM_PNTR register cycles through up to six alarm band

configurations per capture. A lower frequency register (ALM_

F_LOW) and an upper frequency register (ALM_F_HIGH) are

set to define a bandwidth of interest. ALM_MAG1 and

ALM_MAG2 define two levels of magnitude within the band

set on which to base two triggers. These levels allow two warning

levels for a trigger. Setting ALM_CTRL allows the setting of

enabling and disabling individual axes, two warning levels, the

number of events required to trigger an alarm, and the clearing

options for the trigger alerts.

1

2

3

4

5

6

FREQUENCY

Figure 42. Spectral Alarm Band Registers

MECHANICAL MOUNTING RECOMMENDATIONS

The alarm status is reported in the ALM_STAT register. These

registers show which alarm caused the last alarm event. If the

alarm is serviced immediately, REC_INFO1 and REC_INFO2

contain the last capture settings for additional information

about the event. Based on the record mode (REC_CTRL,

Bits[3:2]) setting, up to 10 FFT capture records can be stored in

memory.

Mechanical mounting is critical to ensure the best transfer of

vibration and avoiding resonances that may affect performance.

The ADcmXL1021-1 module has four mounting holes

integrated in the aluminum housing.

The mounting holes accept M2.5 screws to hold the module in

place. Stainless steel screws torqued to about 25 inch-pounds

are used for many of the characterization curves shown in the

Typical Performance Characteristics section.

When an alarm is triggered, the values in the ALM_PEAK register

represent the peak value. Only the values that triggered the alarm

are stored when the measured value for the given conditions

exceed the ALM_MAG1 and ALM_MAG2 threshold settings.

The magnitude is in the resolution as configured by the

FFT_AVG1 or FFT_AVG2 setting for the specific capture.

In some cases, when permanent mounting is an option,

industrial epoxies or adhesives, such as cyanoacrylate adhesive,

in addition to the mounting screws can enhance mechanical

coupling.

The alarm frequency bin of the peak deviation point is reported

in ALM_FREQ. The result is in units of resolution (Hz),

configured through the AVG_CNT setting for the specific

capture.

Rev. 0 | Page 22 of 42

Data Sheet

ADcmXL1021-1

USER REGISTER MEMORY MAP

Table 19. User Register Memory Map¹

Register Name

PAGE_ID²

R/W Flash Backup PAGE_ID

Address

Default Register Description

R/W No

0x00

0x00, 0x01

0x02, 0x03

0x04, 0x05

0x06, 0x07

0x08, 0x09

0x0A, 0x0B

0x0C, 0x0D

0x12, 0x13

0x18, 0x19

0x1A, 0x1B

0x1C, 0x1D

0x1E, 0x1F

0x20, 0x21

0x22, 0x23

0x28, 0x29

0x2E, 0x2F

0x30, 0x31

0x32, 0x33

0x34, 0x35

0x36, 0x37

0x38, 0x39

0x3A, 0x3B

0x3C, 0x3D

0x3E, 0x3F

0x44, 0x45

0x4A, 0x4B

0x4C, 0x4D

0x4E, 0x4F

0x50, 0x51

0x52, 0x53

0x54, 0x55

0x56, 0x57

0x0000

Page identifier

TEMP_OUT

SUPPLY_OUT

FFT_AVG1

FFT_AVG2

BUF_PNTR

REC_PNTR

OUT_BUF

ANULL

REC_CTRL

Reserved

R

No

0x8000³Internal temperature

0x8000³Power supply voltage (VDD)

R/W Yes

R/W No

0x0108

0x0101

0x0000

0x8000

0x0000

0x1102

0x00FF

0x0000

0x0080

0x0000

N/A

FFT average settings (SR0 and SR1)

FFT average settings (SR2 and SR3)

Buffer address pointer

Data record pointer

Output buffer data

Bias correction value (from auto null)

Record control register (mode of operation)

Reserved

R

No

R/W Yes

N/A N/A

R/W Yes

R/W Yes⁴

R/W No

R/W Yes

N/A N/A

R/W Yes

REC_PRD

Record period setting

ALM_F_LOW

ALM_F_HIGH

ALM_MAG1

ALM_MAG2

ALM_PNTR

ALM_S_MAG

ALM_CTRL

Reserved

Spectral alarm band, low frequency setting

Spectral alarm band, high frequency setting

Spectral alarm band, Alarm Magnitude 1

Spectral alarm band, Alarm Magnitude 2

Spectral alarm pointer

System alarm threshold setting

Alarm control settings

Reserved

FILT_CTRL

AVG_CNT

Filter control settings

Sample rate settings (SR0, SR1, SR2, and SR3)

Diagnostic and status flags

Global command triggers

Alarm status

Alarm peak value

Time stamp, lower word

DIAG_STAT

GLOB_CMD

ALM_STAT

ALM_PEAK

TIME_STAMP_L

TIME_STAMP_H

Reserved

DAY_REV

YEAR_MON

PROD_ID

R

W

R

No

Yes⁵

Time stamp, upper word

Reserved

N/A N/A

R

N/A

Firmware revision and firmware day code

Firmware date (month, year)

0x03FD Product identification for ADcmXL1021-1 models, equals

decimal 1021

SERIAL_NUM

USER_SCRATCH

REC_FLASH_CNT

Reserved

MISC_CTRL

REC_INFO1

REC_INFO2

REC_CNTR

ALM_FREQ

STAT_PNTR

Statistic

FUND_FREQ

FLASH_CNT_L

FLASH_CNT_U

PAGE_ID

FIR_COEF_A00

FIR_COEF_A01

R

N/A

0x00

0x01

0x58, 0x59

0x5A, 0x5B

0x5C, 0x5D

0x5E to 0x63

0x64, 0x65

0x66, 0x67

0x68, 0x69

0x6A, 0x6B

0x70, 0x71

0x72, 0x73

0x78, 0x79

0x7A, 0x7B

0x7C, 0x7D

0x7E, 0X7F

0x00, 0x01

0x02, 0x03

0x04, 0x05

N/A

Serial number, lot-specific , unique per device

Scratch register for user ID option

Write counter for data record portion of flash memory

Reserved

Miscellaneous control

Record Information 1

R/W Yes

N/A

R

N/A N/A

R/W No

R

R/W No

R

R/W Yes

R

N/A

Yes⁵

N/A

Yes⁵

0x0000

N/A

0x0000

0x0001

0x0006

0x0015

Record Information 2

Record counter

Frequency bin of most severe alarm

Pointer for time domain statistics

Selected statistical value

Fundamental frequency setting

Flash access counter, lower 16 bits

Flash access counter, upper 16 bits

Page identifier

Yes⁵

N/A

R/W No

R/W Yes

FIR Filter Bank A, Coefficient 0

FIR Filter Bank A, Coefficient 1

Rev. 0 | Page 23 of 42

ADcmXL1021-1

Data Sheet

Register Name

FIR_COEF_A02

FIR_COEF_A03

FIR_COEF_A04

FIR_COEF_A05

FIR_COEF_A06

FIR_COEF_A07

FIR_COEF_A08

FIR_COEF_A09

FIR_COEF_A10

FIR_COEF_A11

FIR_COEF_A12

FIR_COEF_A13

FIR_COEF_A14

FIR_COEF_A15

FIR_COEF_A16

FIR_COEF_A17

FIR_COEF_A18

FIR_COEF_A19

FIR_COEF_A20

FIR_COEF_A21

FIR_COEF_A22

FIR_COEF_A23

FIR_COEF_A24

FIR_COEF_A25

FIR_COEF_A26

FIR_COEF_A27

FIR_COEF_A28

FIR_COEF_A29

FIR_COEF_A30

FIR_COEF_A31

Reserved

R/W Flash Backup PAGE_ID

Address

Default Register Description

R/W Yes

N/A N/A

R/W No

R/W Yes

0x01

0x02

0x06, 0x07

0x08, 0x09

0x0A, 0x0B

0x0C, 0x0D

0x0E, 0x0F

0x10, 0x11

0x12, 0x13

0x14, 0x15

0x16, 0x17

0x18, 0x19

0x1A, 0x1B

0x1C, 0x1D

0x1E, 0x1F

0x20, 0x21

0x22, 0x23

0x24, 0x25

0x26, 0x27

0x28, 0x29

0x2A, 0x2B

0x2C, 0x2D

0x2E, 0x2F

0x30, 0x31

0x32, 0x33

0x34, 0x35

0x36, 0x37

0x38, 0x39

0x3A, 0x3B

0x3C, 0x3D

0x3E, 0x3F

0x40, 0x41

0x42 to 0x7F

0x00, 0x01

0x02, 0x03

0x04, 0x05

0x06, 0x07

0x08, 0x09

0x0A, 0x0B

0x0C, 0x0D

0x0E, 0x0F

0x10, 0x11

0x12, 0x13

0x14, 0x15

0x16, 0x17

0x18, 0x19

0x1A, 0x1B

0x1C, 0x1D

0x1E, 0x1F

0x20, 0x21

0x22, 0x23

0x24, 0x25

0x26, 0x27

0x28, 0x29

0x2A, 0x2B

0x0035

0x006B

FIR Filter Bank A, Coefficient 2

FIR Filter Bank A, Coefficient 3

0x00C1 FIR Filter Bank A, Coefficient 4

0x013C FIR Filter Bank A, Coefficient 5

0x01E0

FIR Filter Bank A, Coefficient 6

0x02AE FIR Filter Bank A, Coefficient 7

0x03A2 FIR Filter Bank A, Coefficient 8

0x04B3

FIR Filter Bank A, Coefficient 9

0x05D2 FIR Filter Bank A, Coefficient 10

0x06EE

0x07F2

FIR Filter Bank A, Coefficient 11

FIR Filter Bank A, Coefficient 12

0x08CB FIR Filter Bank A, Coefficient 13

0x0967

0x09B9

0x0967

FIR Filter Bank A, Coefficient 14

FIR Filter Bank A, Coefficient 15

FIR Filter Bank A, Coefficient 16

FIR Filter Bank A, Coefficient 17

0x08CB FIR Filter Bank A, Coefficient 18

0x07F2

0x06EE

FIR Filter Bank A, Coefficient 19

FIR Filter Bank A, Coefficient 20

0x05D2 FIR Filter Bank A, Coefficient 21

0x04B3 FIR Filter Bank A, Coefficient 22

0x03A2 FIR Filter Bank A, Coefficient 23

0x02AE FIR Filter Bank A, Coefficient 24

0x01E0

FIR Filter Bank A, Coefficient 25

0x013C FIR Filter Bank A, Coefficient 26

0x00C1 FIR Filter Bank A, Coefficient 27

0x006B

0x0035

0x0015

0x0006

N/A

FIR Filter Bank A, Coefficient 28

FIR Filter Bank A, Coefficient 29

FIR Filter Bank A, Coefficient 30

FIR Filter Bank A, Coefficient 31

Reserved

PAGE_ID

0x0002

0x0004

0x0001

0xFFEC

0xFFB9

0xFF62

0xFEF1

0xFE8C

0xFE76

0xFEFE

0x006B

0x02E1

0x0645

Page identifier

FIR_COEF_B00

FIR_COEF_B01

FIR_COEF_B02

FIR_COEF_B03

FIR_COEF_B04

FIR_COEF_B05

FIR_COEF_B06

FIR_COEF_B07

FIR_COEF_B08

FIR_COEF_B09

FIR_COEF_B10

FIR_COEF_B11

FIR_COEF_B12

FIR_COEF_B13

FIR_COEF_B14

FIR_COEF_B15

FIR_COEF_B16

FIR_COEF_B17

FIR_COEF_B18

FIR_COEF_B19

FIR_COEF_B20

FIR Filter Bank B, Coefficient 0

FIR Filter Bank B, Coefficient 1

FIR Filter Bank B, Coefficient 2

FIR Filter Bank B, Coefficient 3

FIR Filter Bank B, Coefficient 4

FIR Filter Bank B, Coefficient 5

FIR Filter Bank B, Coefficient 6

FIR Filter Bank B, Coefficient 7

FIR Filter Bank B, Coefficient 8

FIR Filter Bank B, Coefficient 9

FIR Filter Bank B, Coefficient 10

FIR Filter Bank B, Coefficient 11

0x0A34 FIR Filter Bank B, Coefficient 12

0x0E13

0x1130

0x12EC

0x1130

0x0E13

FIR Filter Bank B, Coefficient 13

FIR Filter Bank B, Coefficient 14

FIR Filter Bank B, Coefficient 15

FIR Filter Bank B, Coefficient 16

FIR Filter Bank B, Coefficient 17

FIR Filter Bank B, Coefficient 18

0x0A34 FIR Filter Bank B, Coefficient 19

0x0645 FIR Filter Bank B, Coefficient 20

Rev. 0 | Page 24 of 42

Data Sheet

ADcmXL1021-1

Register Name

FIR_COEF_B21

FIR_COEF_B22

FIR_COEF_B23

FIR_COEF_B24

FIR_COEF_B25

FIR_COEF_B26

FIR_COEF_B27

FIR_COEF_B28

FIR_COEF_B29

FIR_COEF_B30

FIR_COEF_B31

Reserved

R/W Flash Backup PAGE_ID

Address

Default Register Description

R/W Yes

N/A N/A

R/W No

R/W Yes

N/A N/A

R/W No

R/W Yes

0x02

0x03

0x04

0x2C, 0x2D

0x2E, 0x2F

0x30, 0x31

0x32, 0x33

0x34, 0x35

0x36, 0x37

0x38, 0x39

0x3A, 0x3B

0x3C, 0x3D

0x3E, 0x3F

0x40, 0x41

0x42 to 0x7F

0x00, 0x01

0x02, 0x03

0x04, 0x05

0x06, 0x07

0x08, 0x09

0x0A, 0x0B

0x0C, 0x0D

0x0E, 0x0F

0x10, 0x11

0x12, 0x13

0x14, 0x15

0x16, 0x17

0x18, 0x19

0x1A, 0x1B

0x1C, 0x1D

0x1E, 0x1F

0x20, 0x21

0x22, 0x23

0x24, 0x25

0x26, 0x27

0x28, 0x29

0x2A, 0x2B

0x2C, 0x2D

0x2E, 0x2F

0x30, 0x31

0x32, 0x33

0x34, 0x35

0x36, 0x37

0x38, 0x39

0x3A, 0x3B

0x3C, 0x3D

0x3E, 0x3F

0x40, 0x41

0x42 to 0x7F

0x00, 0x01

0x02, 0x03

0x04, 0x05

0x06, 0x07

0x08, 0x09

0x0A, 0x0B

0x0C, 0x0D

0x02E1

0x006B

0XFEFE

0xFE76

FIR Filter Bank B, Coefficient 21

FIR Filter Bank B, Coefficient 22

FIR Filter Bank B, Coefficient 23

FIR Filter Bank B, Coefficient 24

0XFE8C FIR Filter Bank B, Coefficient 25

0xFEF1

0xFF62

0xFFB9

0xFFEC

0x0001

0x0004

N/A

FIR Filter Bank B, Coefficient 26

FIR Filter Bank B, Coefficient 27

FIR Filter Bank B, Coefficient 28

FIR Filter Bank B, Coefficient 29

FIR Filter Bank B, Coefficient 30

FIR Filter Bank B, Coefficient 31

Reserved

PAGE_ID

0x0003

0x0025

Page identifier

FIR Filter Bank C, Coefficient 0

FIR_COEF_C00

FIR_COEF_C01

FIR_COEF_C02

FIR_COEF_C03

FIR_COEF_C04

FIR_COEF_C05

FIR_COEF_C06

FIR_COEF_C07

FIR_COEF_C08

FIR_COEF_C09

FIR_COEF_C10

FIR_COEF_C11

FIR_COEF_C12

FIR_COEF_C13

FIR_COEF_C14

FIR_COEF_C15

FIR_COEF_C16

FIR_COEF_C17

FIR_COEF_C18

FIR_COEF_C19

FIR_COEF_C20

FIR_COEF_C21

FIR_COEF_C22

FIR_COEF_C23

FIR_COEF_C24

FIR_COEF_C25

FIR_COEF_C26

FIR_COEF_C27

FIR_COEF_C28

FIR_COEF_C29

FIR_COEF_C30

FIR_COEF_C31

Reserved

0x005A FIR Filter Bank C, Coefficient 1

0x008F FIR Filter Bank C, Coefficient 2

0x009A FIR Filter Bank C, Coefficient 3

0x004D FIR Filter Bank C, Coefficient 4

0xFF8D FIR Filter Bank C, Coefficient 5

0xFE74

FIR Filter Bank C, Coefficient 6

0xFD5D FIR Filter Bank C, Coefficient 7

0xFCDD FIR Filter Bank C, Coefficient 8

0xFD97 FIR Filter Bank C, Coefficient 9

0x0003

0x0430

FIR Filter Bank C, Coefficient 10

FIR Filter Bank C, Coefficient 11

0x09A2 FIR Filter Bank C, Coefficient 12

0x0F5F FIR Filter Bank C, Coefficient 13

0x142C FIR Filter Bank C, Coefficient 14

0x16E8

FIR Filter Bank C, Coefficient 15

FIR Filter Bank C, Coefficient 16

0x142C FIR Filter Bank C, Coefficient 17

0x0F5F FIR Filter Bank C, Coefficient 18

0x09A2 FIR Filter Bank C, Coefficient 19

0x0430

0x0003

FIR Filter Bank C, Coefficient 20

FIR Filter Bank C, Coefficient 21

0xFD97 FIR Filter Bank C, Coefficient 22

0xFCDD FIR Filter Bank C, Coefficient 23

0xFD5D FIR Filter Bank C, Coefficient 24

0xFE74

FIR Filter Bank C, Coefficient 25

0xFF8D FIR Filter Bank C, Coefficient 26

0x004D FIR Filter Bank C, Coefficient 27

0x009A FIR Filter Bank C, Coefficient 28

0x008F

FIR Filter Bank C, Coefficient 29

0x005A FIR Filter Bank C, Coefficient 30

0x0025

N/A

FIR Filter Bank C, Coefficient 31

Reserved

PAGE_ID

0x0004

Page identifier

FIR_COEF_D00

FIR_COEF_D01

FIR_COEF_D02

FIR_COEF_D03

FIR_COEF_D04

FIR_COEF_D05

0xFD94 FIR Filter Bank D, Coefficient 0

0xFD62 FIR Filter Bank D, Coefficient 1

0xFD2A FIR Filter Bank D, Coefficient 2

0xFCE8

0xFC9C FIR Filter Bank D, Coefficient 4

0xFC43 FIR Filter Bank D, Coefficient 5

FIR Filter Bank D, Coefficient 3

Rev. 0 | Page 25 of 42

ADcmXL1021-1

Data Sheet

Register Name

FIR_COEF_D06

FIR_COEF_D07

FIR_COEF_D08

FIR_COEF_D09

FIR_COEF_D10

FIR_COEF_D11

FIR_COEF_D12

FIR_COEF_D13

FIR_COEF_D14

FIR_COEF_D15

FIR_COEF_D16

FIR_COEF_D17

FIR_COEF_D18

FIR_COEF_D19

FIR_COEF_D20

FIR_COEF_D21

FIR_COEF_D22

FIR_COEF_D23

FIR_COEF_D24

FIR_COEF_D25

FIR_COEF_D26

FIR_COEF_D27

FIR_COEF_D28

FIR_COEF_D29

FIR_COEF_D30

FIR_COEF_D31

Reserved

R/W Flash Backup PAGE_ID

Address

Default Register Description

R/W Yes

N/A N/A

R/W No

R/W Yes

0x04

0x05

0x0E, 0x0F

0x10, 0x11

0x12, 0x13

0x14, 0x15

0x16, 0x17

0x18, 0x19

0x1A, 0x1B

0x1C, 0x1D

0x1E, 0x1F

0x20, 0x21

0x22, 0x23

0x24, 0x25

0x26, 0x27

0x28, 0x29

0x2A, 0x2B

0x2C, 0x2D

0x2E, 0x2F

0x30, 0x31

0x32, 0x33

0x34, 0x35

0x36, 0x37

0x38, 0x39

0x3A, 0x3B

0x3C, 0x3D

0x3E, 0x3F

0x40, 0x41

0x42 to 0x7F

0x00, 0x01

0x02, 0x03

0x04, 0x05

0x06, 0x07

0x08, 0x09

0x0A, 0x0B

0x0C, 0x0D

0x0E, 0x0F

0x10, 0x11

0x12, 0x13

0x14, 0x15

0x16, 0x17

0x18, 0x19

0x1A, 0x1B

0x1C, 0x1D

0x1E, 0x1F

0x20, 0x21

0x22, 0x23

0x24, 0x25

0x26, 0x27

0x28, 0x29

0x2A, 0x2B

0x2C, 0x2D

0x2E, 0x2F

0x30, 0x31

0x32, 0x33

0xFBD7 FIR Filter Bank D, Coefficient 6

0xFB52

FIR Filter Bank D, Coefficient 7

0xFAAB FIR Filter Bank D, Coefficient 8

0xF9D2 FIR Filter Bank D, Coefficient 9

0xF8AB FIR Filter Bank D, Coefficient 10

0xF702

0xF468

FIR Filter Bank D, Coefficient 11

FIR Filter Bank D, Coefficient 12

0xEFBC FIR Filter Bank D, Coefficient 13

0xE4DC FIR Filter Bank D, Coefficient 14

0xAE85 FIR Filter Bank D, Coefficient 15

0x517B

0x1B24

0x1044

0x0B98

0x08FE

0x0755

0x062E

0x0555

FIR Filter Bank D, Coefficient 16

FIR Filter Bank D, Coefficient 17

FIR Filter Bank D, Coefficient 18

FIR Filter Bank D, Coefficient 19

FIR Filter Bank D, Coefficient 20

FIR Filter Bank D, Coefficient 21

FIR Filter Bank D, Coefficient 22

FIR Filter Bank D, Coefficient 23

0x04AE FIR Filter Bank D, Coefficient 24

0x0429 FIR Filter Bank D, Coefficient 25

0x03BD FIR Filter Bank D, Coefficient 26

0x0364

0x0318

FIR Filter Bank D, Coefficient 27

FIR Filter Bank D, Coefficient 28

0x02D6 FIR Filter Bank D, Coefficient 29

0x029E FIR Filter Bank D, Coefficient 30

0x026C FIR Filter Bank D, Coefficient 31

N/A

Reserved

PAGE_ID

0x0005

0xFF2B

0xFEF0

Page identifier

FIR Filter Bank E, Coefficient 0

FIR Filter Bank E, Coefficient 1

FIR_COEF_E00

FIR_COEF_E01

FIR_COEF_E02

FIR_COEF_E03

FIR_COEF_E04

FIR_COEF_E05

FIR_COEF_E06

FIR_COEF_E07

FIR_COEF_E08

FIR_COEF_E09

FIR_COEF_E10

FIR_COEF_E11

FIR_COEF_E12

FIR_COEF_E13

FIR_COEF_E14

FIR_COEF_E15

FIR_COEF_E16

FIR_COEF_E17

FIR_COEF_E18

FIR_COEF_E19

FIR_COEF_E20

FIR_COEF_E21

FIR_COEF_E22

FIR_COEF_E23

FIR_COEF_E24

0xFEAA FIR Filter Bank E, Coefficient 2

0xFE59 FIR Filter Bank E, Coefficient 3

0xFDFB FIR Filter Bank E, Coefficient 4

0xFD8C FIR Filter Bank E, Coefficient 5

0xFD09 FIR Filter Bank E, Coefficient 6

0xFC6B FIR Filter Bank E, Coefficient 7

0xFBA8 FIR Filter Bank E, Coefficient 8

0xFAB1

0xF96B

FIR Filter Bank E, Coefficient 9

FIR Filter Bank E, Coefficient 10

0xF7A1 FIR Filter Bank E, Coefficient 11

0xF4E5

0xF017

0xE512

FIR Filter Bank E, Coefficient 12

FIR Filter Bank E, Coefficient 13

FIR Filter Bank E, Coefficient 14

0xAE97 FIR Filter Bank E, Coefficient 15

0x5169 FIR Filter Bank E, Coefficient 16

0x1AEE FIR Filter Bank E, Coefficient 17

0x0FE9 FIR Filter Bank E, Coefficient 18

0x0B1B FIR Filter Bank E, Coefficient 19

0x085F

0x0695

0x054F

0x0458

0x0395

FIR Filter Bank E, Coefficient 20

FIR Filter Bank E, Coefficient 21

FIR Filter Bank E, Coefficient 22

FIR Filter Bank E, Coefficient 23

FIR Filter Bank E, Coefficient 24

Rev. 0 | Page 26 of 42

Data Sheet

ADcmXL1021-1

Register Name

FIR_COEF_E25

FIR_COEF_E26

FIR_COEF_E27

FIR_COEF_E28

FIR_COEF_E29

FIR_COEF_E30

FIR_COEF_E31

Reserved

R/W Flash Backup PAGE_ID

Address

Default Register Description

R/W Yes

N/A N/A

R/W No

R/W Yes

N/A N/A

0x05

0x06

0x34, 0x35

0x36, 0x37

0x38, 0x39

0x3A, 0x3B

0x3C, 0x3D

0x3E, 0x3F

0x40, 0x41

0x42 to 0x7F

0x00, 0x01

0x02, 0x03

0x04, 0x05

0x06, 0x07

0x08, 0x09

0x0A, 0x0B

0x0C, 0x0D

0x0E, 0x0F

0x10, 0x11

0x12, 0x13

0x14, 0x15

0x16, 0x17

0x18, 0x19

0x1A, 0x1B

0x1C, 0x1D

0x1E, 0x1F

0x20, 0x21

0x22, 0x23

0x24, 0x25

0x26, 0x27

0x28, 0x29

0x2A, 0x2B

0x2C, 0x2D

0x2E, 0x2F

0x30, 0x31

0x32, 0x33

0x34, 0x35

0x36, 0x37

0x38, 0x39

0x3A, 0x3B

0x3C, 0x3D

0x3E, 0x3F

0x40, 0x41

0x42 to 0x7F

0x02F7

0x0274

0x0205

FIR Filter Bank E, Coefficient 25

FIR Filter Bank E, Coefficient 26

FIR Filter Bank E, Coefficient 27

0x01A7 FIR Filter Bank E, Coefficient 28

0x0156

0x0110

FIR Filter Bank E, Coefficient 29

FIR Filter Bank E, Coefficient 30

0x00D5 FIR Filter Bank E, Coefficient 31

N/A

Reserved

PAGE_ID

0x0006

Page identifier

FIR_COEF_F00

FIR_COEF_F01

FIR_COEF_F02

FIR_COEF_F03

FIR_COEF_F04

FIR_COEF_F05

FIR_COEF_F06

FIR_COEF_F07

FIR_COEF_F08

FIR_COEF_F09

FIR_COEF_F10

FIR_COEF_F11

FIR_COEF_F12

FIR_COEF_F13

FIR_COEF_F14

FIR_COEF_F15

FIR_COEF_F16

FIR_COEF_F17

FIR_COEF_F18

FIR_COEF_F19

FIR_COEF_F20

FIR_COEF_F21

FIR_COEF_F22

FIR_COEF_F23

FIR_COEF_F24

FIR_COEF_F25

FIR_COEF_F26

FIR_COEF_F27

FIR_COEF_F28

FIR_COEF_F29

FIR_COEF_F30

FIR_COEF_F31

Reserved

0xFFD9 FIR Filter Bank F, Coefficient 0

0xFFB9

0xFF8C

0xFF50

0xFF02

0xFE9E

0xFE1F

FIR Filter Bank F, Coefficient 1

FIR Filter Bank F, Coefficient 2

FIR Filter Bank F, Coefficient 3

FIR Filter Bank F, Coefficient 4

FIR Filter Bank F, Coefficient 5

FIR Filter Bank F, Coefficient 6

0xFD7D FIR Filter Bank F, Coefficient 7

0xFCB0 FIR Filter Bank F, Coefficient 8

0xFBA8 FIR Filter Bank F, Coefficient 9

0xFA49

0xF861

0xF581

0xF089

0xE558

FIR Filter Bank F, Coefficient 10

FIR Filter Bank F, Coefficient 11

FIR Filter Bank F, Coefficient 12

FIR Filter Bank F, Coefficient 13

FIR Filter Bank F, Coefficient 14

0xAEAF FIR Filter Bank F, Coefficient 15

0x5151 FIR Filter Bank F, Coefficient 16

0x1AA8 FIR Filter Bank F, Coefficient 17

0x0F77 FIR Filter Bank F, Coefficient 18

0x0A7F FIR Filter Bank F, Coefficient 19

0x079F

0x05B7

0x0458

0x0350

0x0283

0x01E1

0x0162

0x00FE

0x00B0

0x0074

0x0047

0x0027

N/A

FIR Filter Bank F, Coefficient 20

FIR Filter Bank F, Coefficient 21

FIR Filter Bank F, Coefficient 22

FIR Filter Bank F, Coefficient 23

FIR Filter Bank F, Coefficient 24

FIR Filter Bank F, Coefficient 25

FIR Filter Bank F, Coefficient 26

FIR Filter Bank F, Coefficient 27

FIR Filter Bank F, Coefficient 28

FIR Filter Bank F, Coefficient 29

FIR Filter Bank F, Coefficient 30

FIR Filter Bank F, Coefficient 31

Reserved

¹N/A means not applicable.

²The PAGE_ID register can be written to change the target register location but does not change values on the defined page in the PAGE_ID register.

³The default value is valid until the first capture event, when the measurement data replaces the default value.

⁴For these registers, values can be stored in flash but are not available for readback until ALM_PNTR is set.

⁵Register values can be retrieved from records stored in flash using record retrieve commands.

Rev. 0 | Page 27 of 42

ADcmXL1021-1

Data Sheet

USER REGISTER DETAILS

PAGE_ID, PAGE NUMBER

SUPPLY_OUT, POWER SUPPLY VOLTAGE

The contents in the PAGE_ID register (see Table 20 and Table 21)

contain the current page setting. The ADcmXL1021-1 has

output and control registers split over seven pages, numbered

from zero to six. Page 1 to Page 6 are the configurable filter

coefficients. Page 0 contains user registers for various

configuration options and outputs.

The SUPPLY_OUT register (see Table 25 and Table 26) provides a

measurement (uncalibrated) of the voltage between the VDD

and GND pins at the start of a data capture event, when the

ADcmXL1021-1 is operating in the MFFT, AFFT, or MTC mode

of operation (see Table 47). Table 27 shows several examples of the

data format for the SUPPLY_OUT register.

As an example, write 0x8002 to select Page 2 for SPI-based user

access. After the register map is pointed to Page 2, any register

writes are used to configure the Filter Bank B coefficients. The

ADcmXL1021-1 user register map (see Table 19) provides a

functional summary of each page and the page assignments

associated with each user accessible register.

Table 25. SUPPLY_OUT Register Definition

Page Addresses Default

0x00 0x04, 0x05 0x8000¹

Access Flash Backup

R

No

¹Default value is valid until the first capture event, when the measurement

data replaces the default value

Table 26. SUPPLY_OUT Bit Descriptions

Table 20. PAGE_ID Register Definition

Bits

Description

Page¹

Addresses Default Access Flash Backup

[15:12]

[11:0]

Do not use

0x0000 0x00, 0x01 0x0000 R/W No

Voltage between VDD and GND pins. 0x0000 = 0 V,

1 LSB = 3.22 mV.

¹This register is located at Address 0x00 and Address 0x01 of each page.

Table 21. PAGE_ID Bit Descriptions

Table 27. Power Supply Data Format Examples

Bits

Description

Supply Level (V)

LSB

Hexadecimal

Binary

[15:0]

Page number, binary numerical format

3.6

1117 0x45D

1025 0x401

1024 0x400

1023 0x3FF

0100 0101 1101

0100 0000 0001

0100 0000 0000

0011 1111 1111

0011 1010 0010

3.3 + 0.003226

3.3

3.3 − 0.003226

3.0

TEMP_OUT, INTERNAL TEMPERATURE

The TEMP_OUT register (see Table 22 and Table 23) provides a

measurement (uncalibrated) of the temperature inside of the unit

at the conclusion of a data capture or analysis event, when the

ADcmXL1021-1 is operating in the MFFT, AFFT, or MTC mode of

operation (see Table 47). Table 24 shows several examples of the

data format for the TEMP_OUT register. The TEMP_OUT value is

related to the sensed temperature by the following relationship:

930

0x3A2

FFT_AVG1, SPECTRAL AVERAGING

The FFT_AVG1 register (see Table 28 and Table 29) contains

the user-configurable, spectral averaging settings for the SR0

and SR1 sample rate settings (see the AVG_CNT register in

Table 68). These settings determine the number of FFT records

that the ADcmXL1021-1 averages when generating the final

FFT result. When using the factory default value for the

FFT_AVG1 register, the FFT result for the sample rate, SR0,

contains an average of eight separate FFT records. The FFT result

for the SR1 sample rate contains a single FFT record (no spectral

averaging).

TEMP_OUT = (Temperature − 460°C)/(−0.46°C/LSB)

Table 22. TEMP_OUT Register Definition

Page Addresses Default

0x00 0x02, 0x03 0x8000¹

Access Flash Backup

R No

¹The default value is valid until the first capture event, when the

measurement data replaces the default value.

Increasing the number of FFT averages increases the overall

time for a record to be generated. The FFT averaging sequence

is as follows: 4096 samples are measured, FFT on 4096 samples,

accumulate FFT result, repeat until the number of FFTs specified in

FFT_AVG1 or FFT_AVG2 is reached. Then, compute the

average FFT, average power supply, and average temperature.

The power supply and temperature are measured after the

4096 samples are captured each time and accumulated.

Table 23. TEMP_OUT Bit Definitions

Bits

Description

[15:0]

Internal temperature data. Offset binary format is twos

complement, 1 LSB = −0.46°C, and there is an offset of

+460°C, except in RTC mode.

Table 24. TEMP_OUT Data Format Examples

Temperature

+105°C

+60°C

Decimal

Hexadecimal

Binary

772

870

0x0303

0x0365

0000 0011 0000 0011

0000 0011 0110 0101

0000 0011 1011 1100

0000 0011 1110 1000

0000 0100 0011 1111

Table 28. FFT_AVG1 Register Definition

+20°C

957

0x03BC

Addresses

Default

Access

Flash Backup

+0°C

−40°C

1000

1087

0x03E8

0x043F

0x06, 0x07

0x0108

R/W

Yes

Rev. 0 | Page 28 of 42

Data Sheet

ADcmXL1021-1

Table 29. FFT_AVG1 Bit Descriptions

BUF_PNTR, BUFFER POINTER

Bits

Description

The BUF_PNTR (see Table 34 and Table 35) controls the data

sample that loads to the OUT_BUF register (see Table 39) from the

user data buffers. The BUF_PNTR register contains 0x0000 at the

conclusion of each capture event and increments with each read of

the OUT_BUF register. When BUF_PNTR contains the maximum

value (2047 or 4095, see Table 35), the next increment (caused by a

read request OUT_BUF) causes the value in the BUF_PNTR

register to wrap around to 0x0000. The depth of the user data

buffer and, therefore, the range of numbers that BUF_PNTR

supports, depends on the mode of operation, according to the

setting in the REC_CTRL register, Bit 0 and Bit 1 (see Table 47).

[15:8] Number of records, SR1, 8 bit unsigned format, range: 1

to 255

[7:0]

Number of records, SR0, 8 bit unsigned format, range: 1

to 255

To eliminate averaging on both SR0 and SR1 settings, set

FFT_AVG1 = 0x0101 by using the following codes (in order) for

the DIN serial string: 0x8601 and 0x8701. Table 30 shows three

more examples of FFT_AVG1 settings, the number of records that

each setting corresponds to that produces each FFT_AVG1

value.

Table 30. FFT_AVG1 Formatting Examples

Table 34. BUF_PNTR Register Definition

Number of FFT Records

Addresses

Default

Access

Flash Backup

FFT_AVG1 Value

0x040C

0x0E1A

SR0

12

26

SR1

4

14

0x0A, 0x0B

0x0000

R/W

No

Table 35. BUF_PNTR Bit Descriptions

Bits Description

[15:12] Set these bits to 0, when writing to this register.

0xFF42

66

255

[11:0]

Buffer pointer value. Range = 0 to 2047 (in MFFT mode or

AFFT mode). Range = 0 to 4095 (in MTC mode).

FFT_AVG2, SPECTRAL AVERAGING

The FFT_AVG2 register (see Table 31 and Table 32) contains

the user-configurable, spectral averaging settings for the SR2

and SR3 sample rate settings (see the AVG_CNT register in

Table 68). These settings determine the number of FFT records

that the ADcmXL1021-1 averages when generating the final

FFT result. When using the factory default value for the

FFT_AVG2 register, the FFT result for the SR2 and SR3 sample

rates contains a single FFT record (no spectral averaging).

Writing a number to the BUF_PNTR register causes that sample

number for user data buffer to load to the OUT_BUF register. For

example, using the following code sequence on DIN writes 0x031C

to the BUF_PNTR register: 0x8A1C and 0x8B03. This write causes

the sample pointer to output (796) from the user data buffer to load

to OUT_BUF (see Figure 43).

XL DATA

0

Table 31. FFT_AVG2 Register Definition

Addresses

Default

Access

Flash Backup

0x08, 0x09

0x0101

R/W

Yes

796

OUT_BUF

Table 32. FFT_AVG2 Bit Descriptions

Bits Description

[15:8] Number of records, SR3, 8 bit unsigned format, range: 1

to 255

2047

[7:0]

Number of records, SR2, 8 bit unsigned format, range: 1

to 255

To configure the ADcmXL1021-1 to average two FFT records

for both SR2 and SR3 settings, set FFT_AVG2 = 0x0202 by using

the following codes (in order) for the DIN serial string: 0x8802 and

0x8702. Table 33 shows three more examples of FFT_AVG2

settings, the number of records that each setting corresponds to,

and the DIN code sequence that produces each FFT_AVG2 value.

USER DATA BUFFERS

Figure 43. Register Activity, BUF_PNTR = 0x031C (MFFT Mode or AFFT Mode)

Table 33. FFT_AVG2 Formatting Examples

Number of FFT Records

FFT_AVG2 Value

0x0407

SR2

7

SR3

4

0x0D50

0x2FFA

80

250

13

47

Rev. 0 | Page 29 of 42

ADcmXL1021-1

Data Sheet

REC_PNTR, RECORD POINTER

OUT_BUF, BUFFER ACCESS REGISTER

The REC_PNTR register (see Table 36 and Table 37) provides

access to the statistical metrics from MTC capture events and

spectral records from MFFT or AFFT capture events in the data

storage bank. Each spectral analysis record in the data storage

bank has a number from 0 to 9 that identifies the number to

write to the REC_PNTR register, Bits[3:0]. This write loads that

spectral record to the user data buffers. After the data from the

spectral record is in the user data buffers, the BUF_PNTR register

(see Table 35) and OUT_BUF register (see Table 39) provide

access to the data in the specified data record through the SPI. For

example, using the following DIN codes to set REC_PNTR =

0x0007 causes Spectral Record 7 to load to the user data buffers.

See Table 38 for additional examples.

The OUT_BUF register (see Table 39 and Table 40) provides

access to vibration data. When operating in MTC, MFFT, or

AFFT mode, OUT_BUF contains the accelerometer data sample

from the user data buffer, which the BUF_PNTR register (see

Table 35) commands. In RTS mode, data is streamed out from the

SPI interface, and data buffers of the registers are not used.

In modes other than RTS when data is stored, after a read of the

upper byte and lower byte, the buffer automatically updates

with the next data sample in the internal buffer, the BUF_

PNTR is auto-incremented. For MTC mode, the buffer can

support 4096 time domain samples, and BUF_PNTR can advance

from 0 to 4095. For AFFT and MFFT mode, the buffer supports

2048 FFT bin values, and BUF_PNTR can advance from 0 to 2047.

Each statistical record in the data storage bank has a number

from 0 through 31 that identifies the number to write to the

REC_PNTR register, Bits[12:8]. This write loads that statistical

record to the user statistical buffers. After the data from a

statistical record is in the user statistical buffers, the STAT_PNTR

register (see Table 105), statistic register (see Table 107) provide

access to this data through the SPI. For example, using the

following DIN codes to set REC_PNTR = 0x0B00 causes

Statistical Record 11 to load to the user statistical buffers:

0x8C00 and 0x8D0B. See Table 38 for additional examples.

Table 39. OUT_BUF Register Definition

Addresses

Default¹

Access

Flash Backup

0x12, 0x13

0x8000

R/W

No

¹The default value changes to 0x8000 when entering the first capture event

and is only valid until completion of the first capture event or

commencement of RTS mode.

Table 40. OUT_BUF Bit Descriptions

Bits

Description

[15:0]

Output data

Table 36. REC_PNTR Register Definition

The numerical format of the data in OUT_BUF depends on the

mode of operation (see the REC_CTRL register, Bits[1:0] in

Table 47). When operating in MTC mode (REC_CTRL, Bits[1:0]

= 10), the data in the OUT_BUF register uses a 16-bit, offset

binary format, where 1 LSB represents ~0.001907 g. This format

provides enough numerical range to support the measurement

range ( 50 g) and the maximum bias/offset from the core

sensor. Table 41 shows several examples of how to translate

these codes to the acceleration magnitude that the examples

represent for MTC mode, assuming nominal sensitivity and zero

bias error.

Addresses

Default

Access

Flash Backup

0x0C, 0x0D

0x0000

R/W

No

Table 37. REC_PNTR Bit Descriptions

Bits Description

[15:12] Set these bits to 0 when writing to this register

[12:8]

Record number, statistics (from MTC mode only), range =

0 to 31

[7:4]

[3:0]

Set these bits to 0 when writing to this register

Record number, spectral records, range = 0 to 9

(from MFFT mode and AFFT mode only)

MTC mode data in the OUT_BUF register uses a 16-bit,

twos complement format, where 1 LSB represents ~0.001907 g.

This format provides enough numerical range to support the

measurement range ( 50 g) and the maximum bias and offset

from the core sensor. Table 41 shows several examples of how to

translate these codes into the acceleration magnitude that the

codes represent, assuming nominal sensitivity and zero bias error.

Table 38. REC_PNTR Example Use Cases

REC_PNTR

DIN Codes

Value

Description

0x8C05

0x0005

Spectral Record 5 loads to

the user data buffer.

0x8D0C

0x0C00

0x1503

Statistical Record 12 loads to

the user statistics buffer.

Spectral Record 3 loads to

the user data buffer and

Statistical Record 21 loads to

the user statistics buffer.

If velocity calculations are enabled using Bit 5 in the REC_CTRL

register, calculated velocity data is stored in place of default

acceleration value. Data format examples are shown in Table 42.

0x8C03, 0x8D15

Rev. 0 | Page 30 of 42

Data Sheet

ADcmXL1021-1

Table 41. MTC Mode Data Format Examples

ANULL, BIAS CALIBRATION REGISTER

Acceleration (g)

+62.4867

+50

LSB

Hexadecimal

Binary

The ANULL register (see Table 44 and Table 45) contains the

bias correction value for the accelerometer, which the auto-null

command (see the GLOB_CMD register, Bit 0, in Table 73)

generates. The ANULL register also supports write access, which

enables users to write their own correction factors to the output

signal chain. The numerical format examples from Table 41 also

apply to the ANULL register. For example, writing the following

codes to DIN sets ANULL = 0xFDDE, which adjusts the offset

of the output signal chain by −546 LSB (~1.042 g = 1 g ÷ 524 LSBs

× 546 LSBs): 0x98DE and 0x99FD.

+32,767 0x7FFF

+26,219 0x666B

0111 1111 1111 1111

0110 0110 0110 1011

0000 0000 0000 0010

0000 0000 0000 0001

0000 0000 0000 0000

1111 1111 1111 1111

1111 1111 1111 1110

1001 1001 1001 0101

1000 0000 0000 0000

+0.003814

+0.001907

0

−0.001907

−0.003814

−50

+2

+1

0

−1

−2

0x0002

0x0001

0x0000

0xFFFF

0xFFFE

−26,220 0x9995

−32,768 0x8000

−62.4886

Table 42. MTC Mode Data Format Examples, Velocity

Calculations Enabled

Velocity

Table 44. ANULL Register Definition

Addresses

Default

Access

Flash Backup

0x18, 0x19

0x0000

R/W

Yes

(mm/sec)

+610,121.5

+487,844

+37.24

+18.62

0

−18.62

−37.24

−487,844

−610,121.5

LSB

Hexadecimal Binary

+32,767 0x7FFF

+26,200 0x6658

+2

+1

0

0111 1111 1111 1111

0110 0110 0101 1000

0000 0000 0000 0010

0000 0000 0000 0001

0000 0000 0000 0000

1111 1111 1111 1111

1111 1111 1111 1110

1001 1001 1010 0111

1000 0000 0000 0000

Table 45. ANULL Bit Descriptions

Bits

Description

0x0002

0x0001

0x0000

0xFFFF

0xFFFE

[15:0]

Bias correction factor. Twos complement,

1 LSB = 0.001907 g.

−1

−2

REC_CTRL, RECORDING CONTROL

The REC_CTRL register (see Table 46 and Table 47) contains

the configuration bits for a number of operational settings in

the ADcmXL1021-1: mode of operation, record storage, power

management, sample rates, and windowing.

−26,200 0x99A8

−32,768 0x8000

When operating in the FFT modes, either MFFT mode (REC_

CTRL1, Bits[1:0] = 00) or AFFT mode (REC_CTRL, Bits[1:0] =

01), the OUT_BUF register uses a 16-bit, unsigned binary format.

Due to the increased resolution capability of FFT values because of

averaging, converting the OUT_BUF value to acceleration is

accomplished by using the following equation:

Table 46. REC_CTRL Register Definitions

Addresses

Default

Access

Flash Backup

0x1A, 0x1B

0x1102

R/W

Yes

Table 47. REC_CTRL Bit Descriptions

OUT _ BUF

2048















2^^

Bits

Description

Output (mg) =

× 0.9535 mg

15

Real-time streaming timeout enable.

Not used.

Number of FFT Averages









14

[13:12] Window setting (MFFT mode and AFFT modes only).

00 = rectangular.

Table 43 shows the conversion from OUT_BUF value to

acceleration.

01 = Hanning (default).

10 = flat top.

11 = not applicable.

Table 43. Spectral Analysis Data Format Examples

Number of FFT

11

10

9

SR3, Sample Rate Option 3, enable = 1, disable = 0.

Sample rate = 220 kSPS ÷ 2^{AVG_CNT[15:12]}(see Table 68).

Acceleration (mg)

62467.43

6766.87

1.02

OUT_BUF Value

Averages

32767

26200

200

1

8

2

1

SR2, Sample Rate Option 2, enable = 1, disable = 0.

Sample rate = 220 kSPS ÷ 2^{AVG_CNT[11:8]}(see Table 68).

SR1, Sample Rate Option 1, enable = 1, disable = 0.

Sample rate = 220 kSPS ÷ 2^AVG_CNT[7:4](see Table 68).

0.95

1

64377.71

3060.90

0.12

0.95

1.91

39000

30000

8

2048

8

SR0, Sample Rate Option 0, enable = 1, disable = 0.

Sample rate = 220 kSPS ÷ 2^AVG_CNT[3:0](see Table 68).

7

Automatic power-down between recordings (MFFT,

AFFT, and MTC mode only). Requires a CS toggle to

wake up.

0 = no power-down.

1 = power-down after data collection/processing.

Rev. 0 | Page 31 of 42

ADcmXL1021-1

Data Sheet

Automatic Power-Down

Bits

6

Description

Enable compute statistics in MTC mode.

Enable velocity calculations.

0 = acceleration.

1 = calculated velocity.

Reserved.

Bit 7 in the REC_CTRL register (see Table 47) contains the

setting for the automated power-down function when the

ADcmXL1021-1 is operating in MFFT, AFFT, or MTC mode.

When this bit is set to 1, the ADcmXL1021-1 automatically

powers down after completing data collection and processing.

When this bit is set to 0, the ADcmXL1021-1 does not power

down after completing data collection and processing functions.

5

4

[3:2]

Flash memory record storage method (MFFT, AFFT,

and MTC modes only).

00 = none. No record storage to flash memory, current

data is available in SRAM until the next recording

event is stored.

01 = alarm triggered. Record storage occurs when the

vibration exceeds one of the configurable alarm

settings.

10 = all. Record storage happens at the conclusion of

each data collection and processing event.

After the device is in sleep mode, a

toggle is required to

CS

wake up before the next measurement can be used. If the device

is powered down between records in AFFT mode, wake up

occurs automatically before the next capture.

Calculate MTC Statistics

Bit 6 in the REC_CTRL register (see Table 47) contains the

setting to enable statistic calculation on MTC records

11 = reserved.

Calculate Velocity

[1:0]

Recording mode.

00 = MFFT mode.

01 = AFFT mode.

10 = MTC mode.

11 = RTS mode.

Bit 5 in the REC_CTRL register (see Table 47) contains the

setting to convert accelerometer data values to velocity values.

When this bit is set to 0, the user data buffers contain linear

acceleration data. When this bit is set to 1, the user data buffers

contain linear velocity data, which comes from integrating the

acceleration data with respect to time.

Real-Time Burst Mode Timeout Enabled

Bit 15 in the REC_CTRL register (see Table 47) contains the

settings that independently disable RTS mode if the available data

is not read. By default, RTS mode is enabled and disabled via

the digital pin, RTS. If this bit is enabled, RTS mode is halted

after failure to receive SCLK on five consecutive data ready

active periods.

Record Storage

Bits[3:2] in the REC_CTRL register (see Table 47) contain the

settings that determine when the ADcmXL1021-1 stores the

result of an FFT capture event to a record location. The MISC_

CTRL register is used for storing time domain statistics.

Recording Mode

Windowing

Bits[1:0] in the REC_CTRL register (see Table 47) establish

the mode of operation. When operating in MTC mode, the

ADcmXL1021-1 uses the signal processing diagram and user-

accessible registers shown in Figure 27. When operating in

AFFT and MFFT mode, the ADcmXL1021-1 uses the signal

processing diagram and user-accessible registers shown in

Figure 29.

Bits[13:12] in the REC_CTRL register (see Table 47) contain the

settings for the window function that the ADcmXL1021-1 uses

on the time domain data, prior to performing the FFT. The

factory default setting for these bits (01) selects the Hanning

window function. The other window options available are

rectangular (setting 0b00), or flat top (setting 0b10).

Spectral Record Selection

REC_PRD, RECORD PERIOD

Bits[11:8] in the REC_CTRL register (see Table 47) contain on

and off settings for the four different sample rate options that

are set using the AVG_CNT register.

The REC_PRD register (see Table 48 and Table 49) contains the

settings for the timer function that the ADcmXL1021-1 uses

when operating in AFFT mode.

The sample rate selector bits (SR0, SR1, SR2, and SR3) are used

when operating in MFFT, AFFT, or MTC mode. When only one

of these bits is set to 1, every data capture event uses that sample

rate setting. When two of the bits are set to 1, the

Table 48. REC_PRD Register Definition

Addresses

Default

Access

Flash Backup

0x1E, 0x1F

0x0000

R/W

Yes

ADcmXL1021-1 uses one of the sample rates for one data

capture event, and then switches to the other for the next

capture event. When all four bits are set to 1, the ADcmXL1021-1

uses the sample rates in the following order when switching to a

new sample rate for each new capture events: SR0, SR1, SR2, SR3,

SR0, SR1, and so on.

Table 49. REC_PRD Bit Descriptions

Bits Description

[15:10] Don’t care

[9:8]

Scale for data bits:

00 = 1 second/LSB, 01 = 1 minute/LSB, 10 = 1 hour/LSB

Data bits, binary format; range = 0 to 255

[7:0]

Rev. 0 | Page 32 of 42

Data Sheet

ADcmXL1021-1

Setting REC_PRD to 0x0005 establishes a 5 sec setting for the time

that elapses between the completion of one capture event and the

beginning of the next capture event. Table 50 shows several more

examples of configuration codes for the REC_PRD register.

The value of ALM_F_LOW applies to the FFT spectral record. The

exact frequency depends on the AVG_CNT register because this

setting reduces the full FFT bandwidth.

For example, when setting ALM_F_LOW = 0x0064, the lower

frequency of the alarm band starts at Bin 200. For example, if

AVG_CNT = 8, the lower frequency is set to 1200 Hz (1200 Hz =

(200 LSB × 220 kHz/8)/4096).

Table 50. REC_PRD Example Use Cases

REC_PRD Value

Timer Value

0x0022

34 sec

If AVG_CNT = 2, the lower frequency is 4800 Hz if ALM_F_LOW

= 0x0064.

0x010F

0x0218

15 minutes

24 hours

ALM_MAG1, ALARM LEVEL 1

ALM_F_LOW, ALARM FREQUENCY BAND

The ALM_MAG1 register sets a magnitude limit for the

output in which to trigger an alarm warning. A second, higher

trigger magnitude can be set in the ALM_MAG2 register and

can distinguish between a warning condition vs. a more critical

condition. When the ADcmXL1021-1 is operating in MFFT or

AFFT mode, the ALM_MAG1 register (see Table 55 and

Table 56) contains the magnitude of the vibration, which triggers

Alarm 1 for the spectral alarm setting contained in the ALM_

PNTR register (see Table 60). In this mode, the FFT band that is

compared to the trigger magnitude limit is between ALM_L_

LOW and ALM_F_HIGH.

Up to six individual spectral alarm bands can be specified with

two magnitude alarm levels. The ALM_PNTR register setting

identifies which alarm is currently addressed and being configured.

Spectral alarms apply when the ADcmXL1021-1 is operating in

MFFT or AFFT mode and when the ALM_F_LOW register (see

Table 51 and Table 52) contains the number of the lowest FFT

bin, which is included in the spectral alarm setting that the ALM_

PNTR register (see Table 60) contains.

The value of ALM_F_LOW applies to the FFT spectral record.

The exact frequency depends on AVG_CNT register because

this register setting reduces the full FFT bandwidth.

When in MTC mode, this limit applies to the statistics of the

time domain capture.

Table 51. ALM_F_LOW Register Definition

ALM_MAG1 can be used as a warning indicator and ALM_

MAG2 as a critical alarm indicator. Set ALM_MAG2 to a greater

or equal value as ALM_MAG1.

Addresses

Default

Access

Flash Backup

0x20, 0x21

0x0000

R/W

Yes

Table 52. ALM_F_LOW Bit Descriptions

Bits Description

[15:12] Don’t care

[11:0] Lower frequency, bin number; range = 0 to 2047

Table 55. ALM_MAG1 Register Definition

Addresses

Default

Access

Flash Backup

0x28, 0x29

0x0000

R/W

Yes

For example, when setting ALR_F_LOW = 0x0064, the lower

frequency of the alarm band starts at Bin 100. For example, if

AVG_CNT = 8, the lower frequency is set to 600 Hz (600 Hz =

(100 LSB × 220 kHz/8)/4096).

Table 56. ALM_MAG1 Bit Descriptions

Bits

Description

[15:0]

Alarm Trigger Level 1

The data format in the ALM_MAG1 register is the same as the

data format in the OUT_BUF register. See Table 43 for several

examples of this data format.

If AVG_CNT = 2, the lower frequency is 2400 Hz if ALM_F_LOW

= 0x0064.

ALM_F_HIGH, ALARM FREQUENCY BAND

ALM_MAG2, ALARM LEVEL 2

When the ADcmXL1021-1 is operating in MFFT or AFFT mode,

the ALM_F_HIGH register (see Table 53 and Table 54) contains

the number of the highest FFT bin included in the spectral alarm

setting. The ALM_PNTR register (see Table 60) contains the

information regarding which of the six alarms is being set.

When the ADcmXL1021-1 is operating in MFFT or AFFT

mode, the ALM_MAG2 register (see Table 57 and Table 58)

contains the magnitude of the vibration, which triggers Alarm 2

for the spectral alarm setting that the ALM_PNTR register (see

Table 60) contains. When in MTC mode, this limit applies to

the statistics of the time domain capture.

Table 53. ALM_F_HIGH Register Definition

Addresses

Default

Access

Flash Backup

Table 57. ALM_MAG2 Register Definition

0x22, 0x23

0x0000

R/W

Yes

Addresses

Default

Access

Flash Backup

0x2E, 0x2F

0x0000

R/W

Yes

Table 54. ALM_F_HIGH Bit Descriptions

Bits Description

[15:12] Don’t care

[11:0] Upper frequency, bin number; range = 0 to 2047

Table 58. ALM_MAG2 Bit Descriptions

Bits

Description

[15:0]

Alarm Trigger Level 2

Rev. 0 | Page 33 of 42

ADcmXL1021-1

Data Sheet

The data format in the ALM_MAG2 register is the same as the

data format in the OUT_BUF register. See Table 43 for several

examples of this data format.

When Bit 4 in the ALM_CTRL register is equal to 0, the ALM_

S_MAG register uses the same data format as the SUPPLY_

OUT register (see Table 26 and Table 27). When Bit 4 in the

ALM_CTRL register is equal to 1, the ALM_S_MAG register

uses the same data format as the TEMP_OUT register (see

Table 23 and Table 24).

The Alarm 2 magnitudes must be greater than or equal to Alarm 1.

ALM_PNTR, ALARM POINTER

When the ADcmXL1021-1 is operating in MFFT or AFFT mode,

the ALM_PNTR register (see Table 59 and Table 60) contains an

alarm pointer that identifies a specific spectral alarm by sample rate

(Bits[9:8]) and spectral band number (Bits[2:0]). Up to six alarms

can be configured per sample rate setting.

ALM_CTRL, ALARM CONROL

The ALM_CTRL register (see Table 63 and Table 64) contains a

number of configuration settings for the alarm function.

Table 63. ALM_CTRL Register Definition

Addresses

Default

Access

Flash Backup

Table 59. ALM_PNTR Register Definition

0x34, 0x35

0x0080

R/W

Yes

Addresses

Default

Access

Flash Backup

0x30, 0x31

0x0000

R/W

No

Table 64. ALM_CTRL Bit Descriptions

Bits Description

[15:13] Don’t care.

Table 60. ALM_PNTR Bit Descriptions

Bits Description

[15:10] Don’t care

[12]

Disables automatic clearing of spectral alarm status

bits upon a read of the status register.

[9:8]

Indicates the sample rate setting for which Alarm x is

defined

[11:8]

Response delay, range = 0 to 15.

Represents the number of spectral records for each

spectral alarm before a spectral alarm flag is set high.

00 = SR0

01 = SR1

02 = SR2

03 = SR3

7

Latch DIAG_STAT error flags. Requires a clear status

command (GLOB_CMD, Bit 4) to reset the flags to 0.

1 = enabled,

0 = disabled.

[7:3]

[2:0]

Don’t care

Spectral band number (1, 2, 3, 4, 5, or 6)

6

5

Enable Alarm 1 and Alarm 2 on ALM1 and ALM2,

respectively.

Setting ALM_PNTR = 0x0203 provides access to the settings for

the spectral alarm, which is associated with Sample Rate SR2

and Spectral Band 3. The current attributes from this spectral

alarm load to the ALM_F_LOW, ALM_F_HIGH, ALM_MAG1

and ALM_MAG2 registers. Writing to these registers changes

each setting for the spectral alarm, which is associated with

Sample Rate SR2 and Spectral Band 3 as well.

System alarm polarity.

1 = trigger when less than ALM_S_MAG.

0 = trigger when greater than ALM_S_MAG.

4

System alarm selection. 1 = temperature, 0 = power

supply.

3

2

1

0

System alarm: 1 = enabled, 0 = disabled.

Output alarm: 1 = enabled, 0 = disabled.

Reserved.

ALM_S_MAG ALARM LEVEL

The ALM_S_MAG register (see Table 61 and Table 62) contains

the magnitude of the system alarm, which can monitor the

temperature or power supply level according to Bits[5:4] in the

ALM_CTRL register (see Table 64).

Reserved.

FILT_CTRL, FILTER CONTROL

The FILT_CTRL register (see Table 65 and Table 66) provides

configuration settings for the 32-tap, FIR filters. When the FILT_

CTRL pin contains the factory default value, the ADcmXL1021-1

does not use any of the FIR filters on the output. For example,

set DIN = 0xB871, then set DIN = 0xB901 to write 0x0171 to

the FILT_CTRL register. This code (0x0171) selects Filter Bank 5

for the accelerometer output.

Table 61. ALM_S_MAG Register Definition

Addresses

0x32, 0x33

Default

Access

Flash Backup

0x0000

R/W

No

Table 62. ALM_S_MAG Bit Descriptions

Bits

Description

[15:0]

System alarm setting

Table 65. FILT_CTRL Register Definition

Addresses

Default

Access

Flash Backup

0x38, 0x39

0x0000

R/W

Yes

Rev. 0 | Page 34 of 42

Data Sheet

ADcmXL1021-1

Table 66. FILT_CTRL Bit Descriptions

with the bin widths and noise predictions that come with those

settings. The information in Table 69 also applies to the SR1

(AVG_CNT register, Bits[7:4]), SR2 (AVG_CNT register, Bits[11:8]),

and SR3 (AVG_CNT register, Bits[15:12]) settings as well.

Bits

[15:11] Don’t care.

[10:8] Output FIR filter selection.

Description

110: FIR Filter Bank F (high-pass filter, 10 kHz).

101: FIR Filter Bank E (high-pass filter, 5 kHz).

100: FIR Filter Bank D (high-pass filter, 1 kHz).

011: FIR Filter Bank C (low-pass filter, 10 kHz).

010: FIR Filter Bank B (low-pass filter, 5 kHz).

001: FIR Filter Bank A (low-pass filter, 1 kHz).

000: no FIR selection.

Table 69. SR0 Sample Rate Settings and Bin Widths

AVG_CNT, Bits[3:0]

Sample Rate (SPS) Bin Width (Hz)

0

Not applicable

220000

110000

55000

27500

13750

Not applicable

53.8

26.9

13.4

6.71

3.35

1.68

0.839

1 (Default)

2

3

4

5

6

7

[7:0]

Reserved.

6875

3438.5

AVG_CNT, DECIMATION CONTROL

The AVG_CNT register (see Table 67 and Table 68) provides

four different sample rate settings (SR0, SR1, SR2, and SR3) that

users can enable using Bits[11:8] in the REC_CTRL register (see

Table 47). These sample rate settings only apply to MFFT, AFFT,

and MTC mode.

DIAG_STAT, STATUS, AND ERROR FLAGS

The DIAG_STAT (see Table 70 and Table 71) register contains a

number of status flags.

Table 70. DIAG_STAT Register Definition

Table 67. AVG_CNT Register Definition

Addresses

Default

Access

Flash Backup

Addresses

Default

Access

Flash Backup

0x3C, 0x3D

0x0000

R

No

0x3A, 0x3B

0x7421

R/W

Yes

Table 71. DIAG_STAT Bit Descriptions

Table 68. AVG_CNT Bit Descriptions

Bits Description

[15:12] SR3 sample rate scale factor (1 to 7), SR3 sample rate =

220,000 ÷ 2^{AVG_CNT[15:12]}

Bits

Description

15

Not used (don’t care).

14

System alarm flag. The temperature or power supply

exceeded the user configured alarm.

[11:8]

[7:4]

[3:0]

SR2 sample rate scale factor (1 to 7), SR2 sample rate =

220,000 ÷ 2^{AVG_CNT[11:8]}

13

12

11

10

9

Spectral Alarm 2 flag.

Reserved.

SR1 sample rate scale factor (1 to 7), SR1 sample rate =

220,000 ÷ 2^AVG_CNT[7:4]

Reserved.

Spectral Alarm 1 flag.

SR0 sample rate scale factor (1 to 7), SR0 sample rate =

220,000 ÷ 2^AVG_CNT[3:0]

Reserved.

8

Reserved.

Each nibble in the AVG_CNT register offers a setting for each

sample rate setting: SR0, SR1, SR2, and SR3. The following

formula demonstrates one of the sample rates (SR1) derived

from the factory default value (0x7421) in the AVG_CNT

register:

7

Data ready/busy indicator (0 = busy, 1 = data ready).

Flash test result, checksum flag (0 = no error, 1 = error).

Self test diagnostic error flag.

6

5

4

Recording escape flag. Indicates use of the SPI driven

interruption command, 0x00E8. This flag is reset

automatically after the first successful recording.

SR1 = 220,000 ÷ 2²= 55,000 SPS

To change one of the sample rate values, write the control value

to the specific nibble in the AVG_CNT register. For example, set

DIN = 0xBB35 to set the upper byte of the AVG_CNT register

to 0x35, which causes the SR2 sample rate to be 27,500 SPS and

the SR3 sample rate to be 6,875 SPS.

3

2

1

0

SPI communication failure (SCLKs ≠ even multiple of 16).

Flash update failure.

Power supply > 3.625 V.

Power supply < 2.975 V.

In MFFT and AFFT mode, the sample rate settings in the

AVG_CNT register influence the bin widths of each FFT result,

which has an impact on the noise in each bin. Table 69 lists the SR0

sample rate settings (see the AVG_CNT register, Bits[3:0]), along

Rev. 0 | Page 35 of 42

ADcmXL1021-1

Data Sheet

Table 75. ALM_STAT Bit Descriptions

GLOB_CMD, GLOBAL COMMANDS

Bits

15

14

13

12

11

10

9

Description

The GLOB_CMD (see Table 72 and Table 73) register contains a

number of global commands. To start any of these processes, set

the corresponding bit to 1. For example, set Bit 0 to logic high to

execute the autonull function and the bit self clears.

Alarm 2 on Band 6; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 6; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 5; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 5; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 4; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 4; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 3; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 3; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 2; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 2; 1 = alarm set, 0 = no alarm

Alarm 2 on Band 1; 1 = alarm set, 0 = no alarm

Alarm 1 on Band 1; 1 = alarm set, 0 = no alarm

Not used

Table 72. GLOB_CMD Register Definition

Addresses

Default

Access

Flash Backup

0x3E, 0x3F

Not applicable

W

No

8

Table 73. GLOB_CMD Bit Descriptions

Bits Description

7

6

15

14

Clear autonull correction.

5

Retrieve spectral alarm band information from the

ALM_PNTR setting.

4

3

13

12

11

10

9

Retrieve record data from flash memory.

Save spectral alarm band registers to flash memory.

Record start or stop.

[2:0]

Most critical alarm condition, spectral band; range = 1 to 6

ALM_PEAK, ALARM PEAK LEVEL

Set BUF_PNTR = 0x0000.

The ALM_PEAK (see Table 76 and Table 77) register contains the

magnitude of the FFT bin, which contains the peak alarm value.

Clear spectral alarm band registers from flash memory.

Clear all records.

8

7

Software reset.

Table 76. ALM_PEAK Register Definition

6

Save registers to flash memory.

Addresses

Default

Access

Flash Backup

Yes

5

Flash test, compare sum of flash memory with factory value.

Clear DIAG_STAT register once.

0x4A, 0x4B

0x0000

R

4

Table 77. ALM_PEAK Bit Descriptions

3

Restore factory register settings and clear the capture buffers.

Bits

Description

2

Self test. Executes the automatic self test method. If test

does not pass, then the self test diagnostic flag is set in

the status register (Bit 5).

[15:0]

Alarm peak, accelerometer data format

1

Power-down (wake with CS toggle). Powers down sensor

and puts embedded microcontroller in sleep mode. The

device wakes up with a toggle of CS or if the automatic

timer triggers a new capture (automatic mode).

TIME_STAMP_L AND TIME_STAMP_H, DATA

RECORD TIMESTAMP

The TIME_STAMP_L (see Table 78 and Table 79) and

TIME_STAMP_H (see Table 80 and Table 81) registers contain a

relative timestamp for the most recent data capture event.

0

Autonull.

ALM_STAT, ALARM STATUS

Table 78. TIME_STAMP_L Register Definition

The ALM_STAT (see Table 74 and Table 75) register contains

status flags for alarm.

Addresses

Default

Access

Flash Backup

0x4C, 0x4D

0x0000

R

Yes

Table 74. ALM_STAT Register Definition

Addresses

Default

Access

Flash Backup

Table 79. TIME_STAMP_L Bit Descriptions

0x44, 0x45

0x0000

R

Yes

Bits

Description

[15:0]

Timestamp, seconds, lower word

Table 80. TIME_STAMP_H Register Definition

Addresses

Default

Access

Flash Backup

0x4E, 0x4F

0x0000

R

Yes

Table 81. TIME_STAMP_H Bit Descriptions

Bits

Description

[15:0]

Timestamp, seconds, upper word

Rev. 0 | Page 36 of 42

Data Sheet

ADcmXL1021-1

DAY_REV, DAY AND REVISION

USER_SCRATCH

The DAY_REV (see Table 82 and Table 83) contains part of the

factory programming date (day) and the revision of the firmware.

The USER_SCRATCH register allows end users to store a device

number to identify the sensor. The register is readable and writable.

Last written value is nonvolatile allowing for data recovery upon

reset.

Table 82. DAY_REV Register Definition

Addresses

Default

Access

Flash Backup

Table 90. USER_SCRATCH Register Definition

0x52, 0x53

0x0000

R

N/A

Addresses

Default

Access

Flash Backup

Table 83. DAY_REV Bit Descriptions

Bits Description

[15:12] Day of the month, most significant digit

0x5A, 0x5B

N/A

R/W

Yes

Table 91. USER_SCRATCH Bit Descriptions

Bits

Description

[11:8]

[7:4]

[3:0]

Day of the month, least significant digit

Firmware revision, most significant digit

Firmware revision, least significant digit

[15:0]

Optional user ID

REC_FLASH_CNT, RECORD FLASH ENDURANCE

YEAR_MON, YEAR AND MONTH

The REC_FLASH_CNT (see Table 92 and Table 93) provides a

tool for tracking the endurance of the flash memory bank, which

support the 10 record storage locations. The value in the REC_

FLASH_CNT register increments after clearing the user record

(GLOB_CMD) and each time the record storage fills up (tenth

location contains event data)

The YEAR_MON (see Table 84 and Table 85) contains the factory

programming date (month and year).

Table 84. YEAR_MON Register Definition

Addresses

Default

Access

Flash Backup

0x54, 0x55

Not applicable

R

N/A

Table 92. REC_FLASH_CNT Register Definition

Table 85. YEAR_MON Bit Descriptions

Bits Description

[15:12] Year, most significant digit

Addresses

Default

Access

Flash Backup

0x5C, 0x5D

0x0000

R

N/A

Table 93. REC_FLASH_CNT Bit Descriptions

[118]

[7:4]

[3:0]

Year, least significant digit

Bits

Description

Month of the year, most significant digit

Month of the year, least significant digit

[15:0]

Endurance counter for the record flash memory

MISC_CTRL, MISCELLANEOUS CONTROL

PROD_ID, PRODUCT IDENTIFICATION

The MISC_CTRL register (see Table 94 and Table 95) enables the

saving of MTC mode statistic values to memory, enable sensor self

test, and enable SYNC pin to external control.

The PROD_ID (see Table 86 and Table 87) register contains the

numerical portion of the model number.

Table 86. PROD_ID Register Definition

Table 94. MISC_CTRL Register Definition

Addresses

Default

Access

Flash Backup

Addresses

Default

Access

Flash Backup

0x56, 0x57

0x03FD

R

N/A

0x64, 0x65

0x0000

W/R

No

Table 87. PROD_ID Bit Descriptions

Table 95. MISC_CTRL Bit Descriptions

Bits Description

[15:13] Unused.

Bits

Description

[15:0]

Binary representation of the numerical portion of the

model number: 0x03FD = 1,021

12

Enable sensitivity to SYNC pin to start a capture. Must be

enabled for external trigger for manual capture modes.

SERIAL_NUM, SERIAL NUMBER

The SERIAL_NUM (see Table 88 and Table 89) contains the serial

number of the unit, within a particular manufacturing lot.

11

10

Unused.

Transfer statistics record from flash memory to SRAM.

REC_PNTR must point to the appropriate time domain

statistic record.

Table 88. SERIAL_NUM Register Definition

Addresses

Default

Access

Flash Backup

9

Transfers statistics from SRAM to flash record.

0x58, 0x59

0x0000

R

N/A

8

Clear time domain statistics.

Unused.

[7:4]

3

Table 89. SERIAL_NUM Bit Descriptions

Set self test on.

Clear self test.

Unused.

Bits

Description

2

[15:0]

Lot specific serial number

[1:0]

Rev. 0 | Page 37 of 42

ADcmXL1021-1

Data Sheet

REC_INFO1, RECORD INFORMATION

REC_CNTR, RECORD COUNTER

The REC_INFO1 register (see Table 96 and Table 97) contains the

sample rate (SRx), window function, and FFT average settings

associated with the spectral record in the user data buffer. The

contents of this register are only relevant for results that come from

MFFT and AFFT mode (see the REC_CTRL register in Table 47).

The REC_CNTR (see Table 100 and Table 101) register contains

the record counter, which contains the number of records currently

in use.

Table 100. REC_CNTR Register Definition

Addresses

Default

Access

Flash Backup

Table 96. REC_INFO1 Register Definition

0x6A, 0x6B

0x0000

R

N/A

Addresses

Default

Access

Flash Backup

Table 101. REC_CNTR Bit Descriptions

0x66, 0x67

0x0000

R

Yes

Bits

Description

Table 97. REC_INFO1 Bit Descriptions

Bits Description

[15:4]

[3:0]

Not used

Record counter range: 0 through 9

[15:14] Sample rate option

00 = SR0

ALM_FREQ, SEVERE ALARM FREQUENCY

The ALM_FREQ register (see Table 102 and Table 103) contains

the frequency bin that is associated with the value in the ALM_

PEAK (see Table 77) register.

01 = SR1

10 = SR2

11 = SR3

[13:12] Window setting

00 = rectangular

01 = Hanning

Table 102. ALM_FREQ Register Definition

Addresses

Default

Access

Flash Backup

0x70, 0x71

0x0000

R

Yes

10 = flat top

11 = not applicable

Table 103. ALM_FREQ Bit Descriptions

Bits Description

[15:12] Not used

[11:8]

[7:0]

Not used (don’t care)

FFT averages; range = 1 to 2047

[11:0]

Alarm frequency for peak alarm level, FFT bin number;

range = 0 to 2047

REC_INFO2, RECORD INFORMATION,

The REC_INFO2 (see Table 98 and Table 99) register contains the

contents of the AVG_CNT register, which relate to the sample rate

(SRx) in use for the spectral record in the user data buffer. The

contents of this register are only relevant for results that come from

MFFT and AFFT mode (see the REC_CTRL register in Table 47).

STAT_PNTR, STATISTIC RESULT POINTER

The STAT_PNTR register (see Table 104 and Table 105) controls

which statistic loads to the statistic register (see Table 107). For

example, set DIN = 0xF202 to write 0x02 to the lower byte of the

STAT_PNTR, which causes the Kurtosis results to load to the

statistic register.

Table 98. REC_INFO2 Register Definition

Addresses

Default

Access

Flash Backup

Table 104. STAT_PNTR Register Definition

0x68, 0x69

0x0000

R

Yes

Addresses

Default

Access

Flash Backup

Table 99. REC_INFO2 Bit Descriptions

0x72, 0x73

0x0000

R/W

No

Bits

Description

Table 105. STAT_PNTR Bit Descriptions

[15:4]

[3:0]

Not used (don’t care)

AVG_CNT setting

Bits

Description

[15:3]

[2:0]

Don’t care

110 = skewness

101 = Kurtosis

100 = crest factor

011 = peak-to-peak

010 = peak

001 = standard deviation

000 = mean value

Rev. 0 | Page 38 of 42

Data Sheet

ADcmXL1021-1

Table 110. FUND_FREQ Bit Descriptions

STATISTIC, STATISTIC RESULT

Bits

Description

The statistic register (see Table 106 and Table 107) contains the

statistical metric that represents the settings in the STAT_

PNTR register (see Table 105). The data format for this register

depends on the metric that it contains. When the lower byte of the

STAT_PNTR register is equal to 0x00, 0x04, 0x05, or 0x06, the data

format is the same as the OUT_BUF register (MTC mode). See

Table 40 and Table 41 for a definition and some examples of this

data format. When the lower byte of the STAT_PNTR register is

equal to 0x01, 0x02, or 0x03, the statistic register uses the binary

coded decimal (BCD) format shown in Table 107. Table 108

provides some numerical examples of this format.

[15:0]

Fundamental frequency setting, f_F. Offset binary format,

1 LSB = 1 Hz. 0x0000 = no influence on alarm settings.

Table 111. Statistic Data Format Examples

Alarm

Band

Start

Frequency

Stop

Frequency

Alarm 1

Level

Alarm 2

Level

1

2

3

4

5

6

0.2 × f_F

0.8 × f_F

1.8 × f_F

2.8 × f_F

3.8 × f_F

10.2 × f_F

0.8 × f_F

1.8 × f_F

2.8 × f_F

3.8 × f_F

10.2 × f_F

f_MAX

20% × 0.5 g

90% × 0.5 g

30% × 0.5 g

25% × 0.5 g

20% × 0.5 g

15% × 0.5 g

0.5 g

Table 106. Statistic Register Definition

Addresses

Default

Access

Flash Backup

FLASH_CNT_L, FLASH MEMORY ENDURANCE

0x78, 0x79

0x0000

R

Yes

FLASH_CNT_L (see Table 112 and Table 113) contains the lower

16 bits of a 32-bit counter. This counter tracks the total number of

update cycles that the flash memory bank experiences.

Table 107. Statistic Bit Descriptions for Crest Factor,

Kurtosis and Skewness results

Bits

Description

Table 112. FLASH_CNT_L Register Definition

[15:8]

[7:0]

Integer, offset binary format, 1 LSB = 1

Decimal, 1 LSB = 1/256 = 0.00390625

Addresses

Default

Access

Flash Backup

0x7C, 0x7D

Not applicable

R

N/A

Table 108. Statistic Data Format Examples for Crest Factor,

Kurtosis and Skewness results

Table 113. FLASH_CNT_L Bit Descriptions

Bits

Description

Hex.

Integer

Decimal

Result

[15:0]

Flash update counter, lower word

0x0000

0x0001

0x0002

0x000A

0x00FE

0x00FF

0x0100

0x016A

0x020A

0x069A

0

1

2

6

0

1/256 = 0.00390625

2/256 = 0.0078125

10/256 = 0.0390625

254/256 = 0.9921875

255/256 = 0.99609375

0

106/256 = 0.4140625

10/256 = 0.0390625

154/256 = 0.6015625

242/256 = 0.9453125

255/256 = 0.99609375

0.00390625

0.0078125

0.0390625

0.9921875

0.99609375

1

1.4140625

2.0390625

6.6015625

26. 9453125

255.99609375

FLASH_CNT_U, FLASH MEMORY ENDURANCE

The FLASH_CNT_U register (see Table 114 and Table 115)

contains the upper 16 bits of a 32-bit counter. This counter tracks

the total number of update cycles that the flash memory bank

experiences.

Table 114. FLASH_CNT_U Register Definition

Addresses

Default

Access

Flash Backup

0x7E, 0x7F

0x0000

R

N/A

0x1AF2 26

0xFFFF 255

Table 115. FLASH_CNT_U Bit Descriptions

Bits

Description

FUND_FREQ, FUNDAMENTAL FREQUENCY

[15:0]

Flash update counter, upper word

The FUND_FREQ register (see Table 109 and Table 110) provides

a simple way to configure the spectral alarms to monitor the

fundamental vibration frequency on a platform, along with the

subsequent harmonic frequencies. Table 111 provides the start

and stop frequency settings for each alarm band, which

600

450

300

automatically loads after writing to the upper byte of the

FUND_FREQ register, the units are Hz. Default is disabled.

Table 109. FUND_FREQ Register Definition

150

0

Addresses

Default

Access

Flash Backup

0x7A, 0x7B

0x0000

R/W

Yes

30

40

55

70

85

100

125

135

150

JUNCTION TEMPERATURE (°C)

Figure 44. Flash/EE Memory Data Retention

Rev. 0 | Page 39 of 42

ADcmXL1021-1

Data Sheet

FIR Filter Design Guidelines

FIR FILTER REGISTERS

User defined, 32 tap digital filtering can be programmed and

stored. This filter uses 16-bit coefficients. Register Page 1 through

Register Page 6 contain filter bank coefficients for Filter A to

Filter F, respectively. Each of the 32 coefficients has a 16-bit

register. User filters (as well as other register settings) can be

stored internally in the ADcmXL1021-1.

The ADcmXL1021-1 signal chain includes a 32-tap, FIR filter.

Register Page 1 through Register Page 6 provide user configuration

access to the coefficients for six different FIR filter banks. The

FILT_CTRL (see Table 66) register controls the enabling of the

FIR filters and allows the selection of the FIR filter banks. Each

FIR filter bank features factory default filter designs, and each

filter bank provides write access to support application specific

filter designs. To access one of the FIR filter banks, write the

corresponding page number to the PAGE_ID register. For

example, set DIN = 0x8003 to set PAGE_ID = 0x0003, which

provides access to FIR Filer Bank C. See Table 19 for a complete

listing of the FIR coefficient addresses and pages.

The numerical format for each coefficient is a 16-bit, twos

complement signed value. Signed values use the MSB to

identify the sign of the value. If the MSB is 1, the values are

negative. If the MSB is 0, the value is positive. The remaining

15 bits are the magnitude of the coefficient.

The 32 taps of the filter must sum to 0 to have unity gain. If

values are summed as unsigned binary values, the summed

value of 32,767 represents unity gain. By default, the FIR filters

are designed to have a linear phase response up to 10 kHz.

By default, the following filters are preconfigured in the

respective filter bank registers:

•

Filter Band A is a 32 tap, low-pass filter at 1 kHz.

Filter Band B is a 32 tap, low-pass filter at 5 kHz.

Filter Band C is a 32 tap, low-pass filter at 10 kHz.

Filter Band D is a 32 tap, high-pass filter at 1 kHz.

Filter Band E is a 32 tap, high-pass filter at 5 kHz.

Filter Band F is a 32 tap, high-pass filter at 10 kHz.

Rev. 0 | Page 40 of 42

Data Sheet

ADcmXL1021-1

APPLICATIONS INFORMATION

some cases, improve mechanical coupling and frequency response.

Application of these additional adhesives are mechanical design

and processes dependent. Therefore, the application of these

additional adhesives must be evaluated thoroughly during

product development.

MECHANICAL INTERFACE

For the best performance, follow the guidelines described in

this section when installing the ADcmXL1021-1 in a system.

Eliminate potential translational forces by aligning the module

in a well defined orientation.

A minimum bend radius of the flex tail of 1 mm is allowed. At

a lower bend radius, delamination or conductor failure may occur.

The connector at the end of the flex tail is the DF12(3.0)-14DS-

0.5V(86) from Hirose Electric Co. Ltd. The mating connector that

must be used is the DF12(3.0)–14DP–0.5V(86) from Hirose

Electric Co. Ltd.

Use uniform mounting force on all four corners of the module.

Use all four mounting holes and M2.5 screws at a torque of

5 inch-pounds.

Additional mechanical adhesives (cyanoacrylate adhesive and

epoxies such as Dymax 652A gel adhesive) can be used to, in

Rev. 0 | Page 41 of 42

ADcmXL1021-1

Data Sheet

OUTLINE DIMENSIONS

27.10

27.00

26.90

21.75

21.70

21.65

BOTTOM VIEW

TOP VIEW

Ø 2.65

(for M2.5

SS316 screws)

12.55

12.50

12.45

23.80

23.70

23.60

Hirose 14 Pin

ctor)

36.00

35.80

35.60

(0.5 mm Pitch Conne

86)

DF12(3.0)-14DS-05V (

3.80

3.60

3.40

4.55 BSC

3.50 BSC

PIN 1

9.20

9.10

8.90

5.80

5.60

5.40

FRONT VIEW

12.50

12.40

12.30

4.60

4.50

4.40

Figure 45. 14-Lead Module with Integrated Flex Connector [MODULE]

(ML-14-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +105°C

g Range Package Description

Package Option

ADcmXL1021-1BMLZ

EVAL-ADCM-1

50 g

14-Lead Module with Integrated Flex Connector [MODULE]

ADcmXL1021-1 Evaluation Kit

ML-14-7

ADCMXL_BRKOUT/PCBZ

ADcmXL1021-1 Breakout Interface Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D21125-0-11/19(0)

Rev. 0 | Page 42 of 42


型号：	ADCMXL-BRKOUT
厂家：	ADI
描述：	Wide Bandwidth, Low Noise, Vibration Sensor
文件：	总42页 (文件大小：776K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADCMXL-BRKOUT [ADI]

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