ADDI9020 [ADI]
60 MHz CCD Signal Processor with V-Driver and Precision Timing Generator; 60 MHz的CCD信号处理器， V型驱动器和精确定时发生器
| 型号： | ADDI9020 |
| 厂家： | 
ADI |
| 描述： | 60 MHz CCD Signal Processor with V-Driver and Precision Timing Generator |
| 文件： | 总2页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
60 MHz CCD Signal Processor with
V-Driver and Precision Timing Generator
Data Sheet
ADDI9020
FEATURES
GENERAL DESCRIPTION
1.8 V analog/digital core
The ADDI9020 is a complete 60 MHz front-end solution for digital
still cameras and other charge-coupled device (CCD) imaging
applications. The ADDI9020 includes the analog front end (AFE),
a fully programmable timing generator (TG), and a 12-channel
V-driver. A Precision Timing® core allows adjustment of high
Integrated 12-channel vertical driver (V-driver)
12-bit, 60 MHz analog-to-digital converter (ADC)
Complete on-chip timing generator
Precision Timing core with ~260 ps resolution
Correlated double sampler (CDS) with variable gain
0 dB to 36 dB, 10-bit variable gain amplifier (VGA)
Black level clamp with variable level control
On-chip 3 V horizontal and reset gate (RG) drivers
2-phase and 4-phase H-clock modes
Electronic and mechanical shutter support
On-chip 1.8 V LDO
On-chip driver for external crystal
speed clocks with approximately 260 ps resolution at 60 MHz
operation.
The on-chip V-driver supports up to 12 channels for use with
multifield CCDs.
The analog front end includes black level clamping, CDS, VGA,
and a 12-bit ADC. The timing generator and V-driver provide
all the necessary CCD clocks: RG, H-clocks, vertical clocks, sensor
gate pulses, a substrate clock, and substrate bias control. The
internal registers are programmed using a 3-wire serial interface.
On-chip sync generator with external sync input
APPLICATIONS
Packaged in a 7 mm × 7 mm CSP_BGA, the ADDI9020 is specified
over an operating temperature range of −25°C to +85°C.
High speed digital cameras
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
ADDI9020
0dB TO 18dB
CDS
VREF
12
12-BIT
ADC
VGA
CCDIN
D0 TO D11
DCLK
0dB TO 36dB
CLAMP
LDOIN (3V)
LDO
REG
LDOOUT (1.8V)
INTERNAL CLOCKS
RG
HL
HORIZONTAL
DRIVERS
Precision
Timing
GENERATOR
4
H1 TO H4
3
INTERNAL
SCK, SL, SDATA
20
REGISTERS
12
V1 TO V8 (3-LEVEL)
V9 TO V12 (2-LEVEL)
VERTICAL
DRIVER
ISATG
6
2
SUBCK
XSUBCK,
XSUBCNT
SYNC
GPO1 TO GPO6 HD VD
CLI CLO
Figure 1.
For more information about the ADDI9020, contact Analog Devices, Inc. via email at: afe.ccd@analog.com
Rev. SpA
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADDI9020
NOTES
Data Sheet
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10643F-0-4/13(SpA)
Rev. SpA | Page 2 of 2
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