ADE7166ACPZF16-RL1 [ADI]
Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver; 单相电能计量IC，具有8052 MCU ， RTC和LCD驱动器
| 型号： | ADE7166ACPZF16-RL1 |
| 厂家： | 
ADI |
| 描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 文件： | 总148页 (文件大小：1687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single-Phase Energy Measurement IC with
8052 MCU, RTC and LCD driver
Preliminary Technical Data
ADE75xx/ADE71xx
GENERAL FEATURES
MICROPROCESSOR FEATURES
8052 based core
Wide supply voltage operation 2.4 to 3.7V
Battery supply input with Automatic switch-over
Reference 1.2 V 1% (drift 50 ppm/°C Maximum)
64-Lead Quad Flat (LQFP) or Chip Scale (LCSP) Lead Free
Packages1
Single-cycle 4MIPS 8052 core
8052 compatible instruction set
32.768 kHz external crystal with on-chip PLL
Two external interrupt sources
External reset pin
Operating Temperature -40°C to 85°C
Real Time Clock
Counter for seconds, minutes and hours
Automatic battery switchover for RTC back up
Ultra-Low Battery Supply Current < 1μA
Software clock calibration with temperature and offset
compensation
ENERGY MEASUREMENT FEATURES
High accuracy active, reactive energy measurement IC,
supports IEC 62053-21, 62053-22, 62053-23
Two differential inputs with PGAs to support Shunt, Current
Transformer and di/dt current sensors
Selectable Digital integrator to support di/dt current sensor
Digital parameters for Gain, offset and phase compensation
Selectable No-load threshold level for Watt, VA, and VAR
anti-creep
Less than 0.1% error on active energy over a dynamic range
of 1000 to 1 @ 25C
Less than 0.5% error on reactive energy over a dynamic
range of 1000 to 1 @ 25C
Integrated LCD driver
104-segment with 2, 3 or 4 Multiplexer
3V/5V driving capability
Internally generated LCD drive voltages
Temperature and Supply compensated drive voltages
Low power battery mode
Wake-up from I/O and UART
LCD driver capability
On-chip peripherals
UART, SPI or I2C
Less than 0.5% error on rms measurements over a dynamic
range of 1000 to 1 for current and 100:1 for voltage @ 25C
Auto-calibration of offsets
Watch-Dog timer
High frequency outputs supply proportional to Irms, active,
reactive or apparent power
Proprietary ADCs and DSP provide high accuracy over large
variations in environmental conditions and time
Power Supply Monitoring with User Selectable Levels
Memory: 16kBytes Flash Memory, 512 Bytes RAM
Development tools
Temperature monitoring
Single pin emulation
IDE based assembly and C source debugging
1 Please contact your Analog Devices representative to check availability of
this package
GENERAL DESCRIPTION
The ADE75xx/ADE71xx integrates Analog Devices Energy (ADE) Metering IC analog front end and fixed function DSP solution
with an enhanced 8052 MCU core, a RTC, an LCD driver and all the peripherals to make an electronic energy meter with LCD
display with a single part.
The ADE Energy Measurement core includes Active, Reactive, Apparent Energy calculations, as well as voltage and current rms
measurements. This information is ready to use for energy billing by using built-in energy scalars. Many power line
supervisory features like SAG, Peak, Zero-crossing are also included in the energy measurement DSP to simplify energy meter
design.
The microprocessor functionality includes a single cycle 8052 core, a Real Time Clock with a power supply back-up pin, a
UART, and a SPI or I2C interface. The ready to use information from the ADE core reduces the program memory size
requirement thus making it easy to integrate complicated design in 16k Bytes of Flash memory.
The ADE75xx/ADE71xx also includes a 108/104-segment LCD driver respectively. This driver generates voltages capable of
driving 5V LCDs.
Rev. PrE 01/07
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Specifications subject to change without notice. No license is granted by implication
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2007 Analog Devices, Inc. All rights reserved.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
ADE75xx/ADE71xx
Preliminary Technical Data
FUNCTIONAL BLOCK DIAGRAM
12
P2.0 (FP18)
13
P2.1 (FP17)
14 P2.2 (FP16)
44
P2.3 (SDEN)
1.20V
REF
19
LCDVP1
16
LCDVP2
LCDVA
LCDVB
LCDVC
COM0
...
COM3
52
IPA
18
PGA1
PGA1
PGA2
ADC
ADC
ADC
3V/5V LCD
CHARGE PUMP
17
53
55
IN
ENERGY
MEASUREMENT
DSP
15
4
IPB
49
50
VP
VN
1
FP0
35
...
63
54
DGND
AGND
20
14
13
12
11
10
9
FP15
FP16
FP17
TEMP
SENSOR
TEMP
ADC
FP18
DOWNLOADER
DEBUGGER
FP19
FP20
FP21
FP22
FP23
FP24
BATTERY
ADC
58
VBAT
V
SW
ADC
PLL
8
POWER SUPPLY
CONTROL &
UART
POR
7
UART
TIMER
SERIAL
PORT
RTC
MONITORING
6
OSC
LDO
LDO
5
FP25
Figure 1. ADE75xx/ADE71xx Functional Block Diagram
Rev. PrE | Page 2 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
TABLE OF CONTENT
FUNCTIONAL BLOCK DIAGRAM .............................................2
3.3V Peripherals and Wakeup Events.......................................33
Transitioning Between Operating Modes................................33
Automatic Battery Switchover (PSM0 to PSM1)................33
Entering Sleep Mode (PSM1 to PSM2)................................34
Servicing Wakeup Events (PSM2 to PSM1) ........................34
Automatic Switch to VDD (PSM2 to PSM0).........................34
Automatic Switch to VDD (PSM1 to PSM0).........................34
Using the power management features....................................34
Energy Measurement......................................................................35
Access to energy measurement sfr............................................35
Access to internal energy measurement registers...................35
Writing to Internal energy measurement registers ............35
Reading Internal energy measurement registers...............35
Energy measurement REGISTERS...........................................36
Energy measurement internal registers details.......................38
Analog Inputs ..............................................................................43
Analog to Digital Conversion ...................................................44
Anti-aliasing Filter..................................................................44
ADC Transfer Function .........................................................45
Current Channel ADC...........................................................45
Voltage Channel ADC............................................................45
Channel Sampling...................................................................46
Fault Detection............................................................................46
Channel selection Indication ................................................46
Fault Indication.......................................................................47
Fault with Active Input Greater than Inactive Input..........47
Fault with Inactive Input Greater than Active Input..........47
Calibration Concerns .............................................................47
di/dt Current Sensor and Digital Integrator............................47
Power quality measurements.....................................................49
Zero-Crossing Detection .......................................................49
Table of content .................................................................................3
ADE75xx/ADE71xx—Specifications..............................................7
Timing Specifications .....................................................................11
Absolute Maximum Ratings ..........................................................18
ESD Caution ................................................................................18
Terminology.....................................................................................19
Measurement Error.....................................................................19
Phase Error between Channels .................................................19
Power Supply Rejection..............................................................19
ADC Offset Error........................................................................19
Gain Error ....................................................................................19
Pin Descriptions ..............................................................................20
SFR Mapping....................................................................................22
Power Management ........................................................................23
Power management register details ..........................................23
Power Supply Architecture ........................................................26
Battery Switchover ......................................................................26
Switching from VDD to VBAT ...................................................27
Switching from VBAT to VDD....................................................27
Power Supply Monitor Interrupt (PSM) ..................................27
Battery Switchover and Power Supply Restored PSM
Interrupt...................................................................................28
VDCIN ADC PSM Interrupt ....................................................28
VBAT Monitor PSM Interrupt .................................................28
VDCIN Monitor PSM Interrupt................................................28
SAG Monitor PSM Interrupt.................................................28
Using the power supply features ...............................................28
Operating modes.............................................................................32
PSM0 (Normal mode)................................................................32
PSM1 (Battery mode).................................................................32
PSM2 (Sleep mode) ....................................................................32
Rev. PrE | Page 3 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Zero-Crossing Timeout......................................................... 49
Period or Frequency Measurements.................................... 49
Line Voltage Sag Detection ................................................... 50
Peak Detection........................................................................ 50
Peak Level Record .................................................................. 51
Phase Compensation.................................................................. 51
ADE75XX/ADE71XX RMS Calculation................................. 51
Current Channel RMS Calculation...................................... 52
Current channel RMS Offset Compensation ..................... 52
Voltage channel RMS Calculation ....................................... 53
Voltage channel RMS Offset Compensation ...................... 53
Active Power Calculation .......................................................... 53
Active power gain calibration............................................... 54
Active power offset calibration............................................. 54
Active power sign detection.................................................. 54
Active power no-Load detection.......................................... 55
Active Energy Calculation .................................................... 55
Integration time under steady Load .................................... 56
Active energy accumulation modes..................................... 56
Active energy Pulse output ................................................... 57
Line cycle active energy accumulation mode..................... 57
Reactive Power Calculation....................................................... 59
Reactive gain automatic compenstation.............................. 59
Reactive power gain calibration ........................................... 59
Reactive power offset calibration ......................................... 59
Sign of Reactive Power Calculation..................................... 60
Reactive power sign detection.............................................. 60
Reactive power no-Load detection ...................................... 60
Reactive Energy Calculation................................................. 61
Integration time under steady Load .................................... 61
Reactive energy accumulation modes ................................. 61
Reactive energy Pulse output................................................ 62
Line cycle reactive energy accumulation mode ................. 62
Apparent Power Calculation..................................................... 63
Apparent Power Offset Calibration ..................................... 63
Apparent Energy Calculation............................................... 63
Integration Times under Steady Load................................. 64
Apparent energy Pulse output.............................................. 64
Line Apparent Energy Accumulation.................................. 64
Apparent power no-Load detection .................................... 65
Energy-to-Frequency Conversion ........................................... 65
Pulse output configuration ................................................... 66
Pulse output characteristic.................................................... 66
Energy register scaling............................................................... 66
Energy measurement interrupts............................................... 67
Temperature, Battery and External Voltage Measurements...... 68
Temperature measurement ....................................................... 70
Single Temperature Measurement ....................................... 70
Background Temperature Measurements........................... 70
Temperature ADC in PSM1 and PSM2............................... 70
Temperature ADC interrupt................................................. 71
Battery measurement................................................................. 71
Single Battery Measurement................................................. 71
Background Battery measurements..................................... 71
Battery ADC in PSM1 and PSM2 ........................................ 71
Battery ADC interrupt........................................................... 71
External Voltage Measurement................................................. 72
Single External voltage Measurement ................................. 72
Background External Voltage Measurements .................... 72
External voltage ADC in PSM1 and PSM2......................... 72
External voltage ADC interrupt........................................... 72
8052 MCU CORE Architecture.................................................... 73
MCU registers............................................................................. 73
Basic 8052 Registers................................................................... 74
Standard 8052 SFRs.................................................................... 75
Memory Overview ..................................................................... 76
Rev. PrE | Page 4 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Addressing Modes.......................................................................77
Instruction set..............................................................................78
Read-Modify-Write Instructions ..............................................81
Instructions that Affect Flags ....................................................81
Interrupt System..............................................................................84
Standard 8051 Interrupt Architecture......................................84
ADE75XX/ADE71XX Interrupt Architecture ........................84
Interrupt SFR register list...........................................................84
Interrupt Priority.........................................................................87
Interrupt Flags .............................................................................87
Interrupt Vectors .........................................................................90
Interrupt Latency ........................................................................90
Context Saving.............................................................................90
Watchdog Timer..............................................................................91
Watchdog Timer Interrupt ....................................................92
LCD Driver ......................................................................................93
LCD SFR Register list .................................................................93
LCD Setup....................................................................................98
LCD Timing and Waveforms.....................................................98
BLINK mode................................................................................98
Software Controlled Blink Mode..........................................98
Automatic Blink Mode...........................................................98
Display Element Control............................................................98
Writing to LCD Data registers ..............................................99
Reading LCD Data registers ..................................................99
Voltage generation ......................................................................99
Power Consumption...............................................................99
Contrast control ......................................................................99
Lifetime Performance.............................................................99
LCD External Circuitry........................................................... 100
LCD Function in PSM2........................................................... 100
Example LCD Setup................................................................. 100
Flash memory ............................................................................... 102
Flash memory Overview..........................................................102
Flash/EE Memory Reliability ..............................................102
Flash memory organization.....................................................102
Using the Flash Memory..........................................................103
ECON—Flash/EE Memory Control SFR ..........................103
Flash functions......................................................................106
Protecting the Flash..................................................................106
Enabling Flash Protection by Code....................................107
Enabling Flash Protection by emulator commands.........107
Notes on Flash Protection....................................................108
Flash memory timing...........................................................108
In circuit programming............................................................108
Serial Downloading..............................................................108
Timers.............................................................................................109
Timer sfr register list ................................................................109
Timer 0 and Timer 1.................................................................112
Timer/Counter 0 and 1 Data Registers..............................112
Timer/Counter 0 and 1 Operating Modes ........................112
Timer 2 .......................................................................................113
Timer/Counter 2 Data Registers.........................................113
Timer/Counter 2 Operating Modes...................................113
PLL ..................................................................................................115
PLL SFR register list..................................................................115
RTC - Real Time Clock ................................................................117
RTC SFR register list.................................................................117
Read and Write operations ......................................................120
Writing the RTC Registers...................................................120
Reading the RTC Counter SFRs .........................................120
RTC Modes ................................................................................121
RTC Interrupts ..........................................................................121
Interval Timer Alarm ...........................................................121
RTC Calibration........................................................................121
UART serial interface ...................................................................123
Rev. PrE | Page 5 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
UART SFR register list............................................................. 123
UART operation modes........................................................... 126
(Slave Select Pin)............................................................. 133
SS
SPI Master Operating Modes.................................................. 133
SPI Interrupt and Status Flags ................................................ 134
I2C COMPATIBLE INTERFACE ............................................... 136
Serial Clock Generation .......................................................... 136
Slave addresses.......................................................................... 136
I2C SFR register list.................................................................. 136
Read and Write Operations..................................................... 137
I2C Receive and Transmit FIFOs........................................... 138
Dual Data Pointers ....................................................................... 139
I/O Ports ........................................................................................ 141
Parallel I/O ................................................................................ 141
Weak Internal Pullups Enabled.......................................... 141
Open Drain (Weak Internal Pull-ups Disabled).............. 141
38 kHz Modulation.............................................................. 141
I/O SFR register list.................................................................. 142
Port 0.......................................................................................... 145
Port 1.......................................................................................... 146
Port 2.......................................................................................... 146
Outline Dimensions..................................................................... 147
selection Guide ............................................................................. 148
Ordering Guide............................................................................. 148
Mode 0 (Shift Register with baud rate fixed at Fcore /12)
................................................................................................. 126
Mode 1 (8-Bit UART, Variable Baud Rate)........................ 126
Mode 2 (9- bit UART with baud fixed at Fcore/64 or Fcore/32)
................................................................................................. 126
Mode 3 (9-Bit UART with Variable Baud Rate) ............... 127
UART Baud Rate Generation.................................................. 127
Mode 0 Baud Rate Generation ........................................... 127
Mode 2 Baud Rate Generation ........................................... 127
Modes 1 and 3 Baud Rate Generation............................... 127
Timer 1 Generated Baud Rates........................................... 127
Timer 2 Generated Baud Rates........................................... 127
UART Timer Generated Baud Rates.................................. 128
UART additional features........................................................ 129
Enhanced Error Checking................................................... 129
UART TxD signal modulation ........................................... 129
Serial Peripheral Interface Interface (SPI)................................. 130
SPI SFR register list .................................................................. 130
SPI pins ...................................................................................... 132
MISO (Master In, Slave Out Data I/O Pin) ...................... 132
MOSI (Master Out, Slave In Pin) ....................................... 132
SCLK (Serial Clock I/O Pin)............................................... 132
Rev. PrE | Page 6 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
ADE75XX/ADE71XX—SPECIFICATIONS
Table 1. (VDD = 3.3 V ꢀ5, AGND = DGND = 0 V, On-Chip Reference, XTAL = 32.768kHz, TMIN to TMAX = –40°C to +8ꢀ°C)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ENERGY METERING
MEASUREMENT ACCURACY1
Phase Error between Channels
(PF = 0.8 Capacitive)
(PF = 0.5 Inductive)
Active Energy Measurement Error2
0.05
0.05
0.1
°
°
Phase lead 37°
Phase lag 60°
Over a dynamic range of 1000 to 1 @25C
% of
reading
AC Power Supply Rejection2
Output Frequency Variation
DC Power Supply Rejection2
VDD = 3.3 V + 100 mV rms/120 Hz
IP = VP = 100 mV rms
0.01
%
VDD = 3.3 V 117 mV dc
IP = VP = 100 mV rms
Output Frequency Variation
Active Energy Measurement Bandwidth1, 2
Reactive Energy Measurement Error2
0.01
14
0.5
%
kHz
% of
reading
Over a dynamic range of 1000 to 1 @25C
Over a dynamic range of 100 to 1 @25C
VRMS Measurement Error2
0.5
% of
reading
kHz
% of
VRMS Measurement Bandwidth1, 2
IRMS Measurement Error2
14
0.5
Over a dynamic range of 1000 to 1 @25C
reading
kHz
IRMS Measurement Bandwidth1, 2
ANALOG INPUTS
14
VP – VN, IA – IN and IB – IN
Maximum Signal Levels
Input Impedance (DC)
Bandwidth (–3 dB)1
500 mV peak Differential input
TBD
kΩ
kHz
mV
14
ADC Offset Error2
1
Gain Error2
Current channel
Range = 0.5 V Full scale
Range = 0.25 V Full scale
Range = 0.125 V Full scale
Voltage channel
4
4
4
4
3
%
%
%
%
%
Current channel = 0.5V dc
Current channel = 0.25V dc
Current channel = 0.125V dc
Voltage channel = 0.5V dc
Gain Error Match2
CF1 and CF2 pulse output
Maximum output frequency
Duty cycle
Active High pulse width
FAULT Detection
21.1
50
90
kHz
%
ms
VP-VN = IAP-IN=500mV peak sine wave
If CF1 or CF2 frequency > 5.55Hz
If CF1 or CF2 frequency < 5.55Hz
Fault Detection Threshold
Inactive Input <> Active Input
6.25
6.25
%, of
larger
IA or IB active
IA or IB active
Input Swap Threshold
Inactive Input <> Active Input
% of
larger
Accuracy Fault Mode Operation
IA Active, IB = AGND
0.1
0.1
% of
reading
% of
Over a dynamic range of 500 to 1
Over a dynamic range of 500 to 1
IB Active, IA = AGND
reading
Fault Detection Delay
Swap Delay
3
3
Seconds
Seconds
ANALOG PERIPHERALS
Rev. PrE | Page 7 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Internal ADCs (Battery, Temperature, VDD)
Power supply operating range
No missing codes1
AC Power Supply Rejection
DC Power Supply Rejection
Integral Linearity Error
2.2
8
3.7
V
Measured on VSWOUT
bits
dB
dB
LSB3
LSB
ms
°C
TBD
TBD
-1
-1
1
1
Differential Linearity Error
Conversion Delay4
1
Temperature sensor accuracy
-1
-4
1
4
at 25°C
between -40°C and 85°C
°C
VDCIN ANALOG INPUT
Maximum Signal Levels
Input Impedance (DC)
Low VDCIN detection threshold
Power-On Reset (POR)
VDD POR
0
VSWOUT
V
MΩ
V
1
1.2
1.08
1.32
Voltage operating range
Detection threshold
POR active Time-out period
1
1.6
3.7
2.9
V
V
ms
Ms
TBD
TBD
Strobe period in Battery
operation
VSWOUT POR
Voltage operating range (VSWOUT
)
)
1
1.8
3.7
2.2
V
V
ms
Detection threshold
POR active Time-out period
VINTA and VINTD POR
Voltage operating range (VSWOUT
Detection threshold
POR active Time-out period
BATTERY SWITCH OVER
TBD
TBD
1
2.25
3.7
2.4
V
V
ms
Voltage operating range (VSWOUT
)
2.4
3.7
V
2.75
TBD
V
V
DD Î VBAT switching threshold (VSWOUT
)
TBD
TBD
ms
V
ms
nA
V
V
V
V
DD Î VBAT switching delay
BAT Î VDD switching threshold (VDD)
BAT Î VDD switching delay
2.75
TBD
1
SWOUT to VBAT leakage current
LCD – Charge pump active
LCDVP1 – LCDVP2 charge pump
capacitance
LCDVA, LCDVB, LCDVC decoupling
capacitance
200
470
nF
nF
LCDVA
LCDVB
LCDVB
LCDVC
0
0
0
0
1.7
4.0
3.4
5.1
V
V
V
V
1/2 bias modes
1/3 bias modes
1/3 bias mode
LCD stand-by current
V1 Segment line voltage
V2 Segment line voltage
V3 Segment line voltage
100
nA
V
1/2 and 1/3 bias modes
Current on segment line = -2μA
Current on segment line = -2μA
Current on segment line = -2μA
LCDVA-0.1 LCDVA
LCDVB-0.1 LCDVB
LCDVC-0.1 LCDVC
V
V
DC voltage across Segment and COM pin
50
mV
LCDVC-LCDVB, LCDVC-LCDVA or LCDVB-
LCDVA
LCD – Resistor ladder active
Rev. PrE | Page 8 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Parameter
Min
Typ
Max
Unit
nA
V
Test Conditions/Comments
Leakage current
1/2 and 1/3 bias modes – No load
Current on segment line = -2μA
Current on segment line = -2μA
Current on segment line = -2μA
±20
LCDVA
V1 Segment line voltage
V2 Segment line voltage
V3 Segment line voltage
LCDVA-0.1V
LCDVB-0.1V
LCDVC-0.1V
LCDVB
LCDVC
V
V
ON-CHIP REFERENCE
Reference Error
12
mV
Power supply rejection
Temperature Coefficient
DIGITAL INTERFACE
LOGIC INPUTS
80
dB
ppm/°C
50
All inputs except XTAL1, XTAL2, BCTRL,
INT0, INT1, RESET
Input High Voltage, VINH
Input Low Voltage, VINL
BCTRL, INT0, INT1, RESET
Input High Voltage, VINH
Input Low Voltage, VINL
Input currents
2.0
1.3
V
V
0.4
0.4
V
V
RESET
RESET = 0V
±10
100
±10
-250
μA
μA
μA
μA
RESET = VSWOUT = 3.3V
Port 0, 1 , 2
Internal pull-up disabled, input – 0V or VOUT
Internal pull-up enabled, input = 2V,
VSWOUT=3.3V
-50
Internal pull-up enabled, input = 0.4V,
VSWOUT=3.3V
μA
Input capacitance
10
pF
All digital input
CRYSTAL OSCILLATOR
Crystal Equivalent Series Resistance
Crystal frequency
XTAL1 Input Capacitance
XTAL2 Output Capacitance
MCU CLOCK RATE - Fcore
30
32
50
33.5
kΩ
kHz
pF
32.768
12
12
pF
4.096
32
MHz
kHz
Crystal = 32.768kHz and CD[2:0]=0
Crystal = 32.768kHz and CD[2:0]=0b111
LOGIC OUTPUTS
Output High Voltage, VOH
ISOURCE
2.4
V
VDD = 3.3 V 5%
VDD = 3.3 V 5%
80
0.4
2
μA
V
mA
μA
pF
Output Low Voltage, VOL
ISINK
Floating state Leakage current
Floating state Output Capacitance
STARTUP TIME5
±10
TBD
At Power-On
From Power Saving Mode 2 (PSM2)
From Power Saving Mode 1 (PSM1)
TBD
TBD
TBD
ms
μs
μs
POWER SUPPLY INPUTS
VDD
VBAT
3.0
2.4
3.3
3.3
3.6
3.7
V
V
POWER SUPPLY OUTPUTS
VBAT to VSWOUT ON-Resistance
VDD to VSWOUT ON-Resistance
VSWOUT output current drive
VINTA, VINTD
25
6.1
1
VBAT = 2.4V
VDD = 3V
Ω
Ω
mA
V
2.25
2.75
Rev. PrE | Page 9 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Parameter
Min
Typ
80
60
Max
Unit
dB
dB
Test Conditions/Comments
VINTA power supply rejection
VINTD power supply rejection
POWER SUPPLY CURRENTS
Current in Normal Mode (PSM0)
Current in Normal Mode (PSM0)
Current in PSM1 with VINTA disabled
Current in PSM2
3.5
2.1
880
1.5
mA
mA
μA
Fcore = 4.096 MHz
Fcore = 1.024 MHz
Fcore = 1.024 MHz
μA
1 These numbers are not production tested but are guaranteed by design and/or characterization data on production release
2 See Terminology section for explanation of specifications.
3 LSB means Least Significant Bit
4 Delay between ADC conversion request and interrupt set
5 Delay between power supply valid and execution of first instruction by 8052 core
Rev. PrE | Page 10 of 148
Preliminary Technical Data
TIMING SPECIFICATIONS
ADE75xx/ADE71xx
AC inputs during testing are driven at VSWOUT – 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements are made at VIH min for
Logic 1 and VIL max for Logic 0 as shown in Figure 2.
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a
100 mV change from the loaded VOH/VOL level occurs as shown in Figure 2.
CLOAD for all outputs = 80 pF, unless otherwise noted.
VDD = 2.7 V to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. CLOCK INPUT (External Clock Driven XTAL1) Parameter
32.768 kHz External Crystal
Min
Typ
30.52
6.26
6.26
9
Max
Unit
μs
μs
μs
ns
tCK
XTAL1 Period
tCKL
tCKH
tCKR
tCKF
1/tCORE
XTAL1 Width Low
XTAL1 Width High
XTAL1 Rise Time
XTAL1 Fall Time
Core Clock Frequency1
9
ns
TBD
TBD
4.096
MHz
1 ADE75xx/ADE71xx internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 12.58 MHz internal clock for the
system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
DV – 0.5V
DD
V
– 0.1V
+ 0.1V
V
– 0.1V
LOAD
LOAD
0.2DV + 0.9V
DD
TIMING
REFERENCE
POINTS
V
V
LOAD
TEST POINTS
LOAD
0.2DV
– 0.1V
DD
V
V
– 0.1V
LOAD
LOAD
0.45V
Figure 2. Timing Waveform Characteristics
Rev. PrE | Page 11 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Table 3. I2C COMPATIBLE INTERFACE TIMING Parameter
Parameter
Min
1.95
1.95
TBD
TBD
Max
Unit
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
tL
tH
SCLOCK Low Pulse Width
SCLOCK High Pulse Width
Start Condition Hold Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Stop Condition Setup Time
Bus Free Time between a Stop Condition and a Start Condition
Rise Time of Both SCLOCK and SDATA
Fall Time of Both SCLOCK and SDATA
Pulse Width of Spike Suppressed
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
TBD
TBD
TBD
TBD
300
300
50
tF
1
tSUP
____________________________________________
1 Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns.
tBUF
tSUP
tR
SDATA (I/O)
MSB
LSB
ACK
MSB
tDSU
tDSU
tF
tDHD
tDHD
tR
tRSU
tH
tPSU
SCLK (I)
tSHD
1
2-7
8
9
1
tSUP
tL
S(R)
PS
tF
STOP
START
REPEATED
START
CONDITION CONDITION
Figure 3. I2C Compatible Interface Timing
Rev. PrE | Page 12 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Table 4. SPI MASTER MODE TIMING (CPHA = 1) Parameter
Min
977
977
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SCLOCK Low Pulse Width1
SCLOCK High Pulse Width1
Data Output Valid after SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
tDAV
tDSU
tDHD
tDF
tDR
tSR
TBD
TBD
TBD
10
10
10
10
25
25
25
25
tSF
ns
____________________________________________
1 Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 in POWCON SFR set to 0, 0, and 0, respectively, that is, core clock frequency = 4.096/8 MHz.
b. SPI bit-rate selection bits SPIR1 and SPR0 in SPI2CMOD SFR set to 0 and 0, respectively.
SCLOCK
(CPOL = 0)
tSH
tSL
tSR
tSF
SCLOCK
(CPOL = 1)
tDAV
tDF
tDR
MOSI
MISO
MSB
BITS 6–1
LSB
LSB IN
MSB IN
BITS 6–1
tDSU
tDHD
Figure 4. SPI Master Mode Timing (CPHA = 1)
Rev. PrE | Page 13 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Table ꢀ. SPI MASTER MODE TIMING (CPHA = 0) Parameter
Min
977
977
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SCLOCK Low Pulse Width1
SCLOCK High Pulse Width1
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
Data Output Valid after SCLOCK Edge
Data Output Setup before SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
TBD
TBD
TBD
TBD
10
10
10
10
25
25
25
25
1 Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 in POWCON SFR set to 0, 0, and 0, respectively, that is, core clock frequency = 4.096/8 MHz.
b. SPI bit-rate selection bits SPIR1 and SPR0 in SPI2CMOD SFR set to 0 and 0, respectively.
SCLOCK
(CPOL = 0)
tSH
tSL
tSR
tSF
SCLOCK
(CPOL = 1)
tDAV
tDOSU
tDF
tDR
MOSI
MISO
MSB
BITS 6–1
LSB
LSB IN
MSB IN
BITS 6–1
tDSU tDHD
Figure 5. SPI Master Mode Timing (CPHA = 0)
Rev. PrE | Page 14 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Table 6. SPI SLAVE MODE TIMING (CPHA = 1) Parameter
Min
0
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSS
SS to SCLOCK Edge
tSL
tSH
SCLOCK Low Pulse Width
SCLOCK High Pulse Width
Data Output Valid after SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
MISO disable after SS rising edge
977
977
tDAV
tDSU
tDHD
tDF
tDR
tSR
TBD
TBD
TBD
10
10
10
10
25
25
25
25
tSF
tDIS
TBD
0
tSFS
SS High after SCLOCK Edge
ns
1
SS
tSFS
tSS
SCLOCK
(CPOL = 0)
tSH
tSL
tSR
tSF
SCLOCK
(CPOL = 1)
tDIS
tDAV
tDF
tDR
MISO
BITS 6–1
BITS 6–1
LSB
MSB
MOSI
MSB IN
LSB IN
tDSU
tDHD
Figure 6. SPI Slave Mode Timing (CPHA = 1)
Rev. PrE | Page 15 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Table 7. SPI SLAVE MODE TIMING (CPHA = 0) Parameter
Min
0
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSS
SS to SCLOCK Edge
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOSS
tDIS
SCLOCK Low Pulse Width
977
977
SCLOCK High Pulse Width
Data Output Valid after SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
Data Output Valid after SS Edge
MISO disable after SS rising edge
TBD
TBD
TBD
10
10
10
10
25
25
25
25
20
TBD
0
tSFS
SS High after SCLOCK Edge
ns
SS
tSFS
tSS
SCLOCK
(CPOL = 0)
tSH
tSL
tSF
tSR
SCLOCK
(CPOL = 1)
tDAV
tDOSS
tDIS
tDF
tDR
MISO
MOSI
BITS 6–1
LSB
MSB
BITS 6–1
LSB IN
MSB IN
tDSU
tDHD
Figure 7. SPI Slave Mode Timing (CPHA = 0)
Rev. PrE | Page 16 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Table 8. UART Timing (Shift Register Mode) Parameter
4.09612.58 MHz Core_Clk
Variable Core_Clk
Min
Typ
Max
Min
Typ
Max
Unit
μs
TXLXL
Serial Port Clock Cycle Time
Output Data Setup to Clock
Input Data Setup to Clock
Input Data Hold after Clock
Output Data Hold after Clock
2.93
12tcore
TQVXH
TDVXH
TXHDX
TXHQX
TBD
TBD
TBD
TBD
μs
μs
μs
μs
tXLXL
TxD
(OUTPUT CLOCK)
SET RI
OR
tQVXH
SET TI
tXHQX
RxD
(OUTPUT DATA)
LSB
BIT 1
BIT 6
tDVXH
tXHDX
RxD
(INPUT DATA)
LSB
BIT 1
BIT 6
MSB
Figure 8. UART Timing in Shift Register Mode
CS
t1
t13
t9
t10
SCLK
0
0
A2
A5
A4
A3
A0
A1
DIN
t12
t11
t11
DB0
DOUT
DB7
DB7
DB0
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
COMMAND BYTE
02875-0-083
Rev. PrE | Page 17 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 9. Absolute Maximum Rating
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VDD to DGND
VBAT to DGND
VDCIN to DGND
Input LCD voltage to AGND
LCDVA, LCDVB, LCDVC2
Analog Input Voltage to AGND
VP, VN, IAP, IBPN and IN
–0.3 V to +3.7 V
–0.3 V to +3.7 V
–0.3 V to VSWOUT + 0.3 V
–0.3 V to VSWOUT + 0.3 V
–2 V to +2 V
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature
64-Lead LQFP, Power Dissipation
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (TBD sec)
Infrared (TBD sec)
64-Lead CSP, Power Dissipation
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (TBD sec)
Infrared (TBD sec)
–0.3 V to VSWOUT + 0.3 V
–0.3 V to VSWOUT + 0.3 V
–40°C to +85°C
–65°C to +150°C
TBD°C
TBD
TBD°C/W
TBD°C
TBD°C
TBD
TBD°C/W
TBD°C
TBD°C
2 When used with external resistor divider
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrE | Page 18 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
TERMINOLOGY
MEASUREMENT ERROR
The error associated with the energy measurement made by the ADE75xx/ADE71xx is defined by the following formula:
⎛
⎞
Energy Re gister −True Energy
⎜
⎜
⎟
⎟
Percentage Error =
×100%
True Energy
⎝
⎠
PHASE ERROR BETWEEN CHANNELS
The digital integrator and the high-pass filter (HPF) in the current channel have a non-ideal phase response. To offset this phase response
and equalize the phase response between channels, two phase-correction networks are placed in the current channel: one for the digital
integrator and the other for the HPF. The phase correction networks correct the phase response of the corresponding component and
ensure a phase match between current channel and voltage channel to within 0.1° over a range of 45 Hz to 65 Hz with the digital
integrator off. With the digital integrator on, the phase is corrected to within 0.4°
over a range of 45 Hz to 65 Hz.
POWER SUPPLY REJECTION
This quantifies the ADE75xx/ADE71xx measurement error as a percentage of reading when the power supplies are varied. For the ac PSR
measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac
(100 mV rms/120 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of
reading—see the Measurement Error definition.
For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal
levels when the supplies are varied 5ꢀ. Any error introduced is again expressed as a percentage of the reading.
ADC OFFSET ERROR
The dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see
a dc analog input signal. The magnitude of the offset depends on the gain and input range selection—see the Typical Performance
Characteristics section. However, when HPF1 is switched on, the offset is removed from the current channel and the power calculation is
not affected by this offset. The offsets can be removed by performing an offset calibration—see the Analog Inputs section.
GAIN ERROR
The difference between the measured ADC output code (minus the offset) and the ideal output code—see the Current Channel ADC and
Voltage Channel ADC sections. It is measured for each of the input ranges on the current channel (0.5 V, 0.25 V, and 0.125 V). The
difference is expressed as a percentage of the ideal code.
Rev. PrE | Page 19 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
PIN DESCRIPTIONS
Table 10. Pin Function Descriptions
Pin No. Mnemonic
Description
Common output, COM3 is used for LCD backplane / LCD segment outputs 27
1
COM3/ FP27
COM2/ FP28
COM1
2
Common output, COM2 is used for LCD backplane / LCD segment outputs 28
Common output, COM1 is used for LCD backplanes
3
4
COM0
Common output, COM0 is used for LCD backplanes
5
P1.2/FP25
P1.3/T2EX/FP24
P1.4/T2/FP23
P1.5/FP22
P1.6/FP21
P1.7/FP20
P0.1/FP19
P2.0/FP18
P2.1/FP17
P2.2/FP16
LCDVC
General-purpose digital I/O / LCD segment outputs 25
6
General-purpose digital I/O / Timer 2 control input / LCD segment outputs 24
General-purpose digital I/O / Timer 2 input / LCD segment outputs 23
General-purpose digital I/O / LCD segment outputs 22
7
8
9
General-purpose digital I/O / LCD segment outputs 21
10
11
12
13
14
15
16
General-purpose digital I/O / LCD segment outputs 20
General-purpose digital I/O / LCD segment outputs 19
General-purpose digital I/O / LCD segment outputs 18
General-purpose digital I/O / LCD segment outputs 17
General-purpose digital I/O / LCD segment outputs 16
Output port for LCD levels. This pin should be decoupled with a 470nF capacitor.
LCDVP2
This pin is an analog output. A capacitor of 470nF should be connected between this pin and LCDVP1
for internal LCD charge pump device.
17, 18
19
LCDVB, LCDVA
LCDVP1
Output ports for LCD levels. These pins should be decoupled with a 470nF capacitor.
This pin is an analog output. A capacitor of 470nF should be connected between this pin and LCDVP2for
internal LCD charge pump device.
35-20
36
FP0-15
LCD segment outputs 0-15
P1.1/TxD
General-purpose digital I/O / Transmitter Data Output 1 (Asynchronous)
General-purpose digital I/O / Receiver Data Input 1 (Asynchronous)
General-purpose digital I/O / Slave select when SPI is in Slave mode / Timer 1 input
37
P1.0/RxD
38
P0.7 /SS/T1
P0.6/SCLK/T0
P0.5/MISO
P0.4/MOSI/SDATA
P0.3/CF2
39
General-purpose digital I/O / Clock output for I2C or SPI port / Timer 0 input
40
General-purpose digital I/O / Data In for SPI port
41
General-purpose digital I/O / Data Line I2C compatible or Data Out for SPI port
General-purpose digital I/O / Calibration Frequency Logic Output.
42
The CF2 logic output gives instantaneous active, reactive or apparent power information.
General-purpose digital I/O / Calibration Frequency Logic Output/ RTC calibration output..
The CF1 logic output gives instantaneous active, reactive or apparent power information.
The RTCCAL output provides a way to calibrate the RTC to within 2ppm, or 0.17s/day –see the RTC
Calibration section.
43
44
P0.2/CF1/RTCCAL
SDEN/P2.3
This pin is used to enable serial download mode when pulled low through a resistor on power-up or
reset. On reset this pin will momentarily become an input and the status of the pin is sampled. If there is
no pulldown resistor in place, the pin will go momentarilly high and then user code will execute. If a
pull-down resistor is in place, the embedded serial download/debug kernel will execute and this pin
remains low during internal program execution. This pin can also be used as a general purpose output.
45
46
47
48
BCTRL/INT1/ P0.0
XTAL2
Digital Input for Battery control. This logic input connects VDD or VBAT to VSW internally when set to logic
High or Low respectively. When left open, the connection between VDD or VBAT to VSW is selected
internally / External Interrupt input / General-purpose digital I/O
A crystal can be connected across this pin andXTAL1 as described above to provide a clock source for
the ADE75xx/ADE71xx.The XTAL2 pin can drive one CMOS load when an external clock is supplied at
XTAL1 or by the gate oscillator circuit.
XTAL1
An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be
connected across XTAL1 and XTAL2 to provide a clock source for the ADE75xx/ADE71xx.The clock
frequency for specified operation is 32.768 kHz.
INT0
General-purpose digital I/O / Interrupt input
Rev. PrE | Page 20 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Pin No. Mnemonic
Description
49, 50
VP, VN
Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500mV for specified operation. This channel also has an internal PGA.
51
EA
This pin is used as an input for emulation. When held high, this input enables the device to fetch code
from internal program memory locations.The ADE75xx/ADE71xx does not support external code
memory. This pin should not be left floating.
52, 53
IP, IN
Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500mV for specified operation. This channel also has an internal PGA.
54
55
AGND
IPB
This pin provides the ground reference for the analog circuitry
Analog Inputs for second Current Channel. This input is fully differential with a maximum differential
level of ±500mVrefered to IN for specified operation. This channel also has an internal PGA.
56
57
RESET
Reset input, Active low
REFIN/OUT
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
1.2 V 8% and a typical temperature coefficient of 50 ppm/°C maximum
58
59
VBAT
3.3V Power supply input from Battery. This pin is connected internally to VDD when the Battery is
selected as the power supply for the ADE75xx/ADE71xx.
VINTA
This pin provides access to the on-chip 2.5V analog LDO. No external active circuitry should be
connected to this pin. This pin should be decoupled with a 10μF capacitor in parallel with a ceramic
100nF capacitor.
60
61
62
VDD
3.3V Power supply input from regulator. This pin is connected internally to VDD when the regulator is
selected as the power supply for the ADE75xx/ADE71xx. This pin should be decoupled with a 10μF
capacitor in parallel with a ceramic 100nF capacitor.
VSWOUT
3.3V Power supply output from ADE75xx/ADE71xx. This pin provides the supply voltage for the LDOs
and internal cicuitry of the ADE75xx/ADE71xx. This pin should be decoupled with a 10μF capacitor in
parallel with a ceramic 100nF capacitor.
VINTD
This pin provides access to the on-chip 2.5V digital LDO. No external active circuitry should be
connected to this pin. This pin should be decoupled with a 10μF capacitor in parallel with a ceramic
100nF capacitor.
63
64
DGND
VDCIN
This pin provides the ground reference for the digital circuitry
Analog input for dc voltage monitoring. The maximum input voltage on this pin is xxxmV with respect
to AGND. This pin is used to monitor the pre-regulated dc voltage. A dedicated ADC measures the
voltage on this pin—see the External Voltage Measurement section.
Rev. PrE | Page 21 of 148
ADE75xx/ADE71xx
SFR MAPPING
Preliminary Technical Data
IPSMF
Table 13
STRBPER
xF9 Table 46
BATVTH
xFA Table 49
SCRATCH1
SCRATCH2
xFC Table 18
SCRATCH3
xFD Table 19
SCRATCH4
INTPR
xFF Table 12
xF8
xFB
Table 17
xFE
Table 20
B
DIFFPROG
PERIPH
BATPR
Table 14
RTCCOMP
TEMPCAL
xF0
xF3
Table 47
xF4
Table 15
xF5
xF6 Table 116
xF7 Table 117
SPIMOD1
I2CMOD
SPIMOD2
I2CADR
SPISTAT
I2CSTAT
IPSME
LCDSEGE2
VDCINADC
Table 132
Table 137
Table 130
Table 13ꢀ
Table 131
xE8
xE8
xE9
xE9
xEA
xEC
xEC
Table 16
Table 16
xED
Table 84
Table 84
xEF
xEF
Table 50
Table 50
Table 136
Table 130
Table 13ꢀ
Table 131
xEA Table 132
xED
xE5
Table 136
ACC
WAV 1L
WAV 1M
WAV 1H
WAV 2L
WAV 2M
WAV 2H
xE0
xD8
xD0
xC8
xC0
xE2
Table 27
xE3
Table 27
xE4
xDC
xD4
Table 27
Table 27
xE6
Table 27
xE7
Table 27
ADCGO
MIRQENL
MIRQENM
MIRQENH
MIRQSTL
MIRQSTM
MIRQSTH
BATADC
48
xD9
Table 39
xDA
Table 40
xDB
Table 41
Table 36
xDD
Table 37
xDE
Table 38
xDF
Table 51
PSW
VRMSL
xD1 Table 27
VRMSM
VRMSH
IRMSL
Table 27
IRMSM
IRMSH
TEMPADC
Table 54
T2CON
Table 99
WDCON
Table 71
xD2
Table 27
xD3
Table 27
xD5
Table 27
xD6
Table 27
xD7
Table 52
RCAP2L
RCAP2H
TL2
TH2
xCA Table 107
xCB Table 106
xCC Table 105
xCD Table 104
KYREG
POWCON
EADRL
EADRH
xC1 Table 109
xC5
Table 22
xC6
Table 94
xC7
Table 95
IP
Table 64
ECON
FLSHKY
PROTKY
EDATA
PROTB0
PROTB1
PROTR
xB8
xB9
Table 87
xBA
Table 88
xBB
Table 89
xBC
Table 90
xBD
Table 91
xBE
Table 92
xBF
Table 93
LCDCONY
PINMAP0
PINMAP1
PINMAP2
xB1
xA9
Table 77
xB2 Table 141
xB3
Table 142
xB4 Table 143
IE
Table 63
P2
Table 146
SCON
Table 122
P1
Table 14ꢀ
TCON
IEIP2
Table 65
LCDPTR
LCDDAT
CFG
Table 59
xA8
xA0
x98
x90
xAC
Table 82
xAE
Table 83
xAF
TIMECON
HTHSEC
SEC
MIN
HOUR
INTVAL
DPCON
xA1 Table 110
xA2 Table 111
xA3 Table 112
xA4 Table 113
xA5 Table 114
xA6 Table 115
xA7 Table 138
SBUF
SPI2CTx
SPI2CRx
LCDCONX
SBAUDF
SBAUDT
EPCFG
x99 Table 123
x9A Table 128
x9B Table 129
x9C
Table 75
x9D Table 125
x9E Table 124
x9F Table 140
MADDPT
MDATL
MDATM
MDATH
LCDCON
LCDCLK
LCDSEGE
x91
x89
x81
Table 27
x92
x8A
x82
Table 27
x93
Table 27
x94
Table 27
x95
Table 74
x96
Table 78
x97
x87
Table 81
TMOD
Table 97
TL0
TL1
TH0
TH1
x8D Table 102
Table
101
Table
100
x88
x80
Table 98
x8B Table 103
x8C
P0
Table 144
SP
Table 58
DPL
Table 56
DPH
PCON
Table 55
x83
Table 57
Mnemonic
WDCON
xC0
Address
Table 71
Link to detailed table
Rev. PrE | Page 22 of 148
Preliminary Technical Data
POWER MANAGEMENT
ADE75xx/ADE71xx
Table 11. Power Management SFRs
The ADE75XX/ADE71XX has an elaborate power management
circuitry that manages the regular power supply to Battery
switch over and power supply failures. The power management
functionalities can be accessed directly through the 8052 SFR –
see Table 11.
SFR
address
(hex)
R/W
Name
Description
0xC1
0xC5
R/W
R/W
KYREG
Key Register
POWCON
Power Management
Configuration
0xEC
0xF4
0xF5
0xF8
R/W
R/W
R/W
R/W
IPSME
PERIPH
BATPR
IPSMF
Power Management
Interrupt enable
Power Management
Configuration
Battery Switchover
configuration
Power Management
Interrupt Flag
0xFB
0xFC
0xFD
0xFE
0xFF
R/W
R/W
SCRATCH1
SCRATCH2
Scratch pad register
Scratch pad register
Scratch pad register
Scratch pad register
R/W SCRATCH3
R/W
R/W
SCRATCH4
INTPR
Interrupt Wake-up
Configuration
POWER MANAGEMENT REGISTER DETAILS
Table 12. Interrupt pins configuration SFR (INTPR, 0xFF)
Bit
Bit
Default
Value
0
Description
Location Mnemonic
7
RTCCAL
Control RTC calibration output
When set, the RTC calibration frequency selected by FSEL[1:0] is output on the
P0.2/CF1/RTCCAL pin.
6-5
FSEL[1:0]
Sets RTC calibration output frequency and calibration window
FSEL[1:0]
Calibration window, frequency
30.5 seconds, 1Hz
0
0
1
1
0
1
0
1
30.5 seconds, 512 Hz
0.244 seconds, 500Hz
0.244 seconds, 16.384 kHz
4
Reserved
3-1
INT1PRG[2:0]
000
Controls the function of INT1T
INT1PRG[2:0]
Function
GPIO
x
0
0
x
0
1
0
1
1
1
x
x
BCTRL
INT1 input disabled
INT1 input enabled
Rev. PrE | Page 23 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
0
INT0PRG
0
Controls the function of INT0
INT0PRG
Function
0
1
INT0 input disabled
INT0 input enabled
Table 13. Power Management Interrupt Flag SFR (IPSMF, 0xF8)
Bit
Location
Bit
Addr.
Bit Name
Default
Value
Description
7
0xFF
FPSR
0
Power Supply Restored Interrupt flag.
Set when the VDD power supply has been restored. This occurs when the source
of VSW changes from VBAT to VDD.
6
5
0xFE
0xFD
FPSM
FSAG
0
0
PSM Interrupt flag.
Set when an enabled PSM interrupt condition occurs.
Voltage SAG Interrupt flag.
Set when an ADE energy measurement SAG condition occurs.
This bit must be kept cleared for proper operation
VDCIN ADC interrupt flag.
4
3
0xFC
0xFB
RESERVED
FVADC
0
0
Set when VDCIN changes by VDCINDIF or when a VDCIN measurement is ready.
VBAT Monitor interrupt flag.
Set when VBAT falls below BATVTH or when the VBAT measurement is ready.
Battery Switchover interrupt flag.
Set when VSW switches from VDD to VBAT.
VDCIN Monitor interrupt flag.
2
1
0
0xFA
0xF9
0xF8
FBAT
FBSO
FVDC
0
0
0
Set when VDCIN falls below 1.2V.
Table 14. Battery Switchover Configuration SFR (BATPR, 0xFꢀ)
Bit
Bit
Default
Value
00
Description
Location Mnemonic
7-2
1-0
Reserved
These bits must be kept to 0 for proper operation
Control bits for Battery Switchover.
BATPRG [1:0]
00
BATPRG [1:0]
Function
0
0
1
0
1
X
Battery Swichover Enabled on Low VDD
Battery Swichover Enabled on Low VDD and Low VDCIN
Battery Switchover Disabled
Table 1ꢀ. Peripheral Configuration SFR (PERIPH, 0xF4)
Bit
Bit
Default
Description
Location Mnemonic
Value
7
6
RXFLAG
0
1
If set, indicates that a RX Edge event triggered wakeup from PSM2
Indicates the power supply that is connected internally to VSW.
0 VSW=VBAT
VSWSOURCE
1 VSW=VDD
5
4
VDD_OK
PLL_FLT
1
0
If set, indicates that VDD power supply is ok for operation
If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLL_FLT_ACK bit in the
Start ADC Measurement SFR (ADCGO, 0xD8) SFR to acknowledge the fault and clear the
PLL_FLT bit
3
REF_BAT_EN
0
If set, Internal voltage reference enabled in PSM2 mode. This bit should be set to maintain the
LCD in PSM2 mode.
2
Reserved
0
This bit should be kept to zero
Controls the function of the P1.0/RX pin.
RXPROG [1:0] Function
1-0
RXPROG[1:0]
00
0
0
GPIO
Rev. PrE | Page 24 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
0
1
1
1
RX with wakeup disabled
RX with wakeup enabled
Table 16. Power Management Interrupt Enable SFR (IPSME, 0xEC)
Bit
Location
Bit
Mnemonic
Default Description
Value
7
6
5
4
3
2
1
0
EPSR
RESERVED
ESAG
RESERVED
EVADC
EBAT
0
0
0
0
0
0
0
0
Enables a PSM interrupt when the Power Supply Restored flag is set.
Reserved
Enables a PSM interrupt when the voltage sag flag (FSAG) is set.
This bit must be kept cleared for proper operation
Enables a PSM interrupt when the VDCIN ADC flag (FVADC) is set.
Enables a PSM interrupt when the VBAT monitor flag (FBAT) is set.
Enables a PSM interrupt when the Battery Switchover flag (FBSO) is set.
Enables a PSM interrupt when the VDCIN monitor flag (FVDCIN) is set.
EBSO
EVDCIN
Table 17. Scratch Pad 1 SFR (SCRATCH1, 0xFB)
Bit
Location
Bit
Mnemonic
Default Description
Value
7-0
SCRATCH1
0
Value can be written/read in this register. This value will be maintained in all the power
saving modes of the ADE75xx/ADE71xx
Table 18. Scratch Pad 2 SFR (SCRATCH2, 0xFC)
Bit
Location
Bit
Mnemonic
Default Description
Value
7-0
SCRATCH2
0
Value can be written/read in this register. This value will be maintained in all the power
saving modes of the ADE75xx/ADE71xx
Table 19. Scratch Pad 3 SFR (SCRATCH3, 0xFD)
Bit
Location
Bit
Mnemonic
Default Description
Value
7-0
SCRATCH3
0
Value can be written/read in this register. This value will be maintained in all the power
saving modes of the ADE75xx/ADE71xx
Table 20. Scratch Pad 4 SFR (SCRATCH4, 0xFE)
Bit
Location
Bit
Mnemonic
Default Description
Value
7-0
SCRATCH4
0
Value can be written/read in this register. This value will be maintained in all the power
saving modes of the ADE75xx/ADE71xx
Table 21. Key SFR (KYREG, 0xC1)
Bit
Location
7-0
Bit
Mnemonic
KYREG
Default
Value
Description
0
Write 0xA7 to the KYREG SFR before writing the POWCON SFR, to unlock it
Write 0xEA to the KYREG SFR before writing to the HTHSEC, SEC, MIN, or
HOUR timekeeping register to unlock it..
Table 22. Power Control SFR (POWCON, 0xCꢀ)
Bit
Location Mnemonic
RESERVED
Bit
Default
Value
X
Description
7
Rev. PrE | Page 25 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
6
METER_OFF
0
Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if
metering functions are not needed in PSM0
5
4
RESERVED
COREOFF
0
0
Set this bit to shut down the core if in the PSM1 operating mode.
Controls the core clock frequency, Fcore. Fcore=4.096MHz/2CD
3
RESERVED
CD[2:0]
2-0
010
CD[2:0]
Fcore (MHz)
4.096
2.048
1.024
0.512
0.256
0.128
0.064
0.032
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Note: The POWCON register must be unlocked by first writing to the KYREG key register. The KYREG SFR is set to 0xA7 to unlock the
POWCON SFR and then the POWCON SFR can be modified. For example:
MOV KYREG,#0A7h
;Write KYREG to 0xA7 to get write access to the POWCON SFR
;Shutdown the core
MOV POWCON, #10H
VDCIN VDD VBAT VSWOUT
POWER SUPPLY ARCHITECTURE
ADE75XX/ADE71XX has two power supply inputs, VDD and
VBAT, and requires only a single 3.3V power supply at VDD for
full operation. A battery backup, or secondary power supply,
with a maximum of 3.6V can be connected to the VBAT input.
Internally, the ADE75XX/ADE71XX connects VDD or VBAT to
VSW, which is used to derive the power for the
ADC
VINTD
VINTA
MCU
LDO
LDO
POWER SUPPLY
MANAGEMENT
BCTRL
VSW
ADE
SPI/I2C
ADC
ADE75XX/ADE71XX circuitry. The VSWOUT output pin reflects
the voltage at VSW, and has a maximum output current of TBD
mA. This pin may also be used to power a limited number of
peripheral components. The 2.5V analog supply, VINTA and the
2.5V supply for the core logic, VINTD, are derived by on-chip
linear regulators from VSW. Figure 9 shows the power supply
architecture of ADE75XX/ADE71XX.
LCD
TEMPERATURE ADC
RTC
SCRATCHPAD
UART
3.3V
2.5V
Figure 9: Power Supply Architecture
BATTERY SWITCHOVER
ADE75XX/ADE71XX monitors VDD, VBAT, and VDCIN
.
The ADE75XX/ADE71XX provides automatic battery
switchover between VDD and VBAT based on the voltage level
detected at VDD or VDCIN. Additionally, the BCTRL input can
also be used to trigger a battery switchover. The conditions for
switching VSW from VDD to VBAT and back to VDD are described
in the Battery Switchover section.
Automatic battery switchover from VDD to VBAT can be
configured based on the status of VDD, VDCIN, or the BCTRL pin.
Battery switchover is enabled by default. Setting bit 1 in the
Battery Switchover Configuration SFR (BATPR, 0xF5), disables
battery switchover so that VDD is always connected to VSW. The
source of VSW is indicated by bit 6 in the Peripheral
Configuration SFR (PERIPH, 0xF4), which is set when VSW is
VDCIN is an input pin that can be connected to a 0V to 3.3V DC
signal. This input is intended for power supply supervisory
purposes and does not provide power to the
connected to VDD and cleared when VSW is connected to VBAT
.
The battery switchover functionality provided by the
ADE75XX/ADE71XX circuitry - see Battery Switchover section.
ADE75XX/ADE71XX allows a seamless transition from VDD to
VBAT. An automatic battery switchover option ensures a stable
power supply to the ADE75XX/ADE71XX, as long as the
external battery voltage is above TBD V. It allows continuous
code execution even while the internal power supply is
switching from VDD to VBAT and back. Note that the energy
metering ADCs are not available when VBAT is being used for
Rev. PrE | Page 26 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
VSW.
configuration SFR (INTPR, 0xFF) enables the battery
control pin.
Power supply monitor (PSM) interrupts can be enabled to
indicate when battery switchover occurs and when the VDD
power supply is restored - see the Power Supply Monitor
Interrupt (PSM) section.
Switching from VBAT to VDD
To switch VSW back from VBAT to VDD all of the events that are
enabled to force battery switchover must be false:
Switching from VDD to VBAT
There are three events that can be enabled to switch the internal
power supply, VSW, from VDD to VBAT
1. (VDCIN < 1.2 V) and (VDD < TBD V) Enabled: If the
low VDCIN condition is enabled, VSW switches to VDD
after VDCIN remains above TBD V for TBD seconds
and VDD remains above TBD V for TBD seconds.
:
1. (VDCIN < 1.2 V): When VDCIN falls below 1.2V VSW
switches from VDD to VBAT. This event is enabled when
the BATTPROG[1:0] bits in the Battery Switchover
Configuration SFR (BATPR, 0xF5) are clear. Setting
this bit will disable switchover based on VDCIN. Battery
switchover on low VDCIN is disabled by default.
2. (VDD < TBD V) Enabled: VSW switches back to VDD
after VDD has been above TBD V for TBD seconds.
3. BCTRL Enabled: VSW switches back to VDD after
BCTRL is low and number 1 or number 2 are satisfied.
POWER SUPPLY MONITOR INTERRUPT (PSM)
2. (VDD < TBD V): When VDD falls below TBD V VSW
switches from VDD to VBAT. This event is enabled when
BATTPROG[1] in the Battery Switchover
The Power Supply Monitor Interrupt (PSM) alerts the 8052 core
of power supply events. The PSM interrupt is disabled by
default. Setting the EPSM bit in the Interrupt Enable and
Priority 2 SFR (IEIP2, 0xA9) enables the PSM interrupt. The
Power Management Interrupt Enable SFR (IPSME, 0xEC)
controls the events that result in a PSM interrupt. Figure 10 is a
diagram illustrating how the PSM interrupt vector is shared
among the PSM interrupt sources. The PSM interrupt flags are
latched and must be cleared by writing to the flag register.
Configuration SFR (BATPR, 0xF5) is cleared.
3. Rising edge on BCTRL: When the battery control
pin, BCTRL, goes high, VSW switches from VDD to VBAT
This external switchover signal can trigger a
switchover to VBAT at any time. Setting bits
INT1PRG[4:2] to 0bx01 in the Interrupt pins
.
EPSR
FPSR
ESAG
FSAG
EVSW
FVSW
FPSM
EPSM
TRUE?
Pending PSM interrupt
EBAT
FBAT
EBSO
FBSO
EVDCIN
FVDCIN
ESAG
EVDCIN
ADEAUTOCLR
FPSM
reserved
EBAT
FBAT
EBSO
EPSR
FPSR
EVSW
IPSME Addr. 0ECh
IPSMF Addr. 0F8h
IEIP2 Addr. 0A9h
FSAG
reserved
PSI
FBSO
EPSM
FVDCIN
ESI
FVSW
EADE
reserved
ETI
PTI
reserved
: Not involved in PSM Interrupt signal chain
Figure 10: PSM Interrupt Sources
Rev. PrE | Page 27 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE75XX/ADE71XX can be configured to generate a PSM
VBAT Monitor PSM Interrupt
The VBAT voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to
check the change in VBAT. The BATTF bit is set when the battery
level is lower than the threshold set in the Battery detection
threshold SFR (BATVTH, 0xFA) or when a new measurement is
ready in the Battery ADC value SFR (BATADC, 0xDF) - see
Battery measurement section. Setting the EBATT bit in the
Power Management Interrupt Enable SFR (IPSME, 0xEC)
enables this event to generate a PSM interrupt.
interrupt when the source of VSW changes from VDD to VBAT
indicating battery switchover. Setting the EBSO bit in the
Power Management Interrupt Enable SFR (IPSME, 0xEC)
enables this event to generate a PSM interrupt.
,
The ADE75XX/ADE71XX can also be configured to generate
an interrupt when the source of VSW changes from VBAT to VDD,
indicating that the VDD power supply has been restored. This
event is enabled to generate a PSM interrupt by setting the
EPSR bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC).
VDCIN Monitor PSM Interrupt
The VDCIN voltage is monitored by a comparator. The FVDC bit
in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is
set when the VDCIN input level is lower than 1.2 V. Setting the
EVDCIN bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
This event associated with the SAG monitoring can be used to
detect a power supply - VDD - being compromised and trigger
The flags in the Power Management Interrupt Flag SFR (IPSMF,
0xF8) for these interrupts, BSOF and PSRF are set regardless of
whether the respective enable bits have been set. The battery
switchover and power supply restore event flags, BSOF and
PSRF, are latched. These events must be cleared by writing a
zero to these bits. Bit 6 in the Peripheral Configuration SFR
(PERIPH, 0xF4), VSWSOURCE, tracks the source of VSW. The
bit is set when VSW is connected to VDD and cleared when VSW is
further actions prior to decide a switch of VDD to VBAT
.
SAG Monitor PSM Interrupt
The ADE75XX/ADE71XX energy measurement DSP monitors
the ac voltage input at the VP and VN input pins. The SAGLVL
register is used to set the threshold for a line voltage sag event.
The SAGF bit in the Power Management Interrupt Flag SFR
(IPSMF, 0xF8) is set if the line voltage stays below the level set
in the SAGLVL register for the number of line cycles set in the
SAGCYC register, - see Line Voltage Sag Detection section.
Setting the ESAG bit in the Power Management Interrupt
Enable SFR (IPSME, 0xEC) enables this event to generate a PSM
interrupt.
connected to VBAT
.
VDCIN ADC PSM Interrupt
The ADE75XX/ADE71XX can be configured to generate a PSM
interrupt when VDCIN changes magnitude by more than a
configurable threshold. This threshold is set in the Temperature
and Voltage ADC Delta SFR (DIFFPROG, 0xF3) –see External
Voltage Measurement section. Setting the EVADC bit in the
Power Management Interrupt Enable SFR (IPSME, 0xEC)
enables this event to generate a PSM interrupt.
USING THE POWER SUPPLY FEATURES
The VDCIN voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to
check the change in VDCIN. Conversions can also be initiated by
writing to the Start ADC Measurement SFR (ADCGO, 0xD8).
The FVADC flag will indicate that a VDCIN measurement is ready.
See the External Voltage Measurement section for details on
how VDCIN is measured.
In an energy meter application, VDD, the 3.3V power supply, is
typically generated from the ac line voltage and regulated to
3.3V by a voltage regulator IC. The pre-regulated DC voltage,
typically 5V to 12V, can be connected to VDCIN through a resistor
divider. A 3.6V battery can be connected to VBAT. Figure 11
shows how the ADE75XX/ADE71XX power supply inputs
would be set up in this application.
Rev. PrE | Page 28 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
(240, 220, 110V typical)
ac input
BCTRL
VP
VN
SAG
Detection
5 - 12V dc
VDCIN
Voltage
Supervisory
IPSMF SFR
(Addr. 0xF8)
Power Supply
Management
Voltage
Supervisory
VDD
3.3V
Regulator
PSU
VSW
VSWOUT
VBAT
Figure 11. Power Supply Management for Energy Meter Application
the power supply.
Figure 12 shows the sequence of events that will be generated
for the power meter application in Figure 11 if the main power
supply generated by the PSU starts to fail. The sag detection can
provide the earliest warning of a potential problem on VDD.
When a sag event occurs, the user code can be configured to
backup data and prepare for battery switchover if desired. The
relative spacing of these interrupts will depend on the design of
Figure 13 shows the sequence of events that will be generated
for the power meter application shown in Figure 11 if the main
power supply starts to fail, with battery switchover on low VDCIN
or low VDD enabled.
VP -VN
SAG LEVEL trip point
SAGCYC=1
VDCIN
1.2V
VDD
t
1
2.75V
t
2
If switchover on low VDD is enabled,
VDCIN Event
(FVDC=1)
SAG Event
(FSAG=1)
Automatic Battery switchover
VSW connected to VBAT
BSO Event
(FBSO=1)
Figure 12: Power Supply Management Interrupts and Battery Switchover with only VDD enabled for battery switchover
Rev. PrE | Page 29 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
VP -VN
SAG LEVEL trip point
SAGCYC=1
VDCIN
1.2V
VDD
t
1
t
3
2.75V
VDCIN Event
(FVDC=1)
SAG Event
(FSAG=1)
If switchover on low VDCIN is enabled,
Automatic Battery switchover
VSW connected to VBAT
BSO Event
(FBSO=1)
Figure 13: Power Supply Management Interrupts and Battery Switchover with VDD or VDCIN enabled for battery switchover
Time
TBD
Comment
t1
t2
t3
Time between when VDCIN goes below 1.2 V and when FVDCIN is raised.
TBD
TBD
Time between when VDD falls below TBD V and when battery switchover occurs.
Time between when VDCIN falls below 1.2 V and when battery switchover occurs, if
VDCIN is enabled to cause battery switchover. VDCIN_OPT[1:0] in the Battery
Switchover Configuration SFR (BATPR, 0xF5) sets this timeout
Table 23: Power Supply Event Timings Operating Modes
Finally, the transition between VDD and VBAT and the different Power Supply Modes (see Operating modessection) is represented in Figure
15.
Rev. PrE | Page 30 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
VP -VN
SAG LEVEL
Trip point
VDCIN
SAG EVENT
VDCIN EVENT
VDCIN EVENT
1.2V
30ms min.
30ms min.
V
BAT
DD
2.75V
V
V
SW
PSM0
PSM0
Battery switch
enabled
PSM1 or PSM2
PSM1 or PSM2
on low VDCIN
V
SW
PSM0
PSM0
Battery switch
enabled
on low VDD
Figure 14: Power Supply Management transitions between modes
Rev. PrE | Page 31 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Table 24. SFR maintained in PSM2
OPERATING MODES
PSM0 (NORMAL MODE)
I/O configuration Power Supply monitoring
In PSM0, normal operating mode, VSW is connected to VDD. All
of the analog and digital circuitries powered by VINTD and VINTA
are enabled by default. The default clock frequency for PSM0,
Interrupt pins configuration SFR Battery detection threshold SFR
(INTPR, 0xFF) (BATVTH, 0xFA)
F
core, established during a power-on-reset or software reset, is
Peripheral Configuration SFR Battery Switchover
TBD MHz.
(PERIPH, 0xF4)
Configuration SFR (BATPR,
0xF5)
PSM1 (BATTERY MODE)
Port 0 Weak pull-up enable SFR
(PINMAP0, 0xB2)
Battery ADC value SFR
(BATADC, 0xDF)
In PSM1, VSW is connected to VBAT. In this operating mode, the
8052 core and all of the digital circuitry are enabled by default.
The analog circuitry for the ADE energy metering DSP
powered by VINTA is disabled. This analog circuitry will
automatically start up again once the VDD supply is above TBD
V if the PWRDN bit in the MODE1 register (0x0B) is cleared.
The default Fcore for PSM1, established during a power-on-reset
or software reset, is 1.024 MHz.
Port 1 Weak pull-up enable SFR
(PINMAP1, 0xB3)
Peripheral ADC Strobe Period
SFR (STRBPER, 0xF9)
Port 2 Weak pull-up enable SFR
(PINMAP2, 0xB4)
Temperature and Voltage ADC
Delta SFR (DIFFPROG, 0xF3)
Scratch Pad 1 SFR (SCRATCH1,
0xFB)
VDCIN ADC value SFR
(VDCINADC, 0xEF)
PSM2 (SLEEP MODE)
Scratch Pad 2 SFR (SCRATCH2,
0xFC)
PSM2 is a low power consumption sleep mode for use in battery
operation. In this mode, VSW is connected to VBAT. All of the
2.5V digital and analog circuitry powered through VINTA and
VINTD is disabled, including the MCU core, resulting in the
following:
Temperature ADC value SFR
(TEMPADC, 0xD7)
Scratch Pad 3 SFR (SCRATCH3,
0xFD)
Scratch Pad 4 SFR (SCRATCH4,
0xFE)
1. The RAM in the MCU is no longer valid.
2. The program counter for the 8052, also held in volatile
memory, becomes invalid when the 2.5V supply is shut
down. Therefore, the program will not resume from where
it left off but will always start from the power on reset
vector when the ADE75XX/ADE71XX comes out of PSM2.
Peripherals – RTC
Peripherals - LCD
RTC Nominal Compensation
SFR (RTCCOMP, 0xF6)
LCD Segment Enable 2 SFR
(LCDSEGE2, 0xED)
RTC Temperature
LCD Configuration Y SFR
The 3.3V peripherals Temperature ADC, VBAT ADC, VDCIN ADC,
RTC and LCD are active in PSM2. They can be enabled or
disabled to reduce power consumption and are configured for
PSM2 operation when the MCU core is active—see the
individual peripherals for more information on their PSM2
configuration. The ADE75XX/ADE71XX remains in PSM2
until an event occurs to wake it up.
Compensation SFR (TEMPCAL, (LCDCONY, 0xB1)
0xF7)
LCD Configuration X SFR
RTC Configuration SFR
(TIMECON, 0xA1)
(LCDCONX, 0x9C)
LCD Configuration SFR
(LCDCON, 0x95)
Hundredths of a Second
Counter SFR (HTHSEC, 0xA2)
LCD Clock SFR (LCDCLK,
0x96)
In PSM2, the ADE75XX/ADE71XX provides 4 scratch pad
RAM SFR that are maintained during this mode. These SFRs
can be used to save data from PSM0 or PSM1 modes when
entering PSM2 modes - see Table 16 to Table 20.
Seconds Counter SFR (SEC,
0xA3)
LCD Segment Enable SFR
(LCDSEGE, 0x97)
Minutes Counter SFR (MIN,
0xA4)
In PSM2, the ADE75XX/ADE71XX maintains some SFRs – see
Table 24. The SFRs that are not listed in this table should be
restored when the part enters PSM0 or PSM1 frm PSM2 mode.
Hours Counter SFR (HOUR,
0xA5)
Alarm Interval SFR (INTVAL,
0xA6)
Rev. PrE | Page 32 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
the ADE75XX/ADE71XX to wake from PSM2 are listed in the
Wakeup Events column in Table 25.
3.3V PERIPHERALS AND WAKEUP EVENTS
Some of the 3.3V peripherals are capable of waking the
ADE75XX/ADE71XX from PSM2. The events that can cause
Table 2ꢀ. 3.3V Peripherals and Wakeup Events
3.3V
Peripheral
Wakeup
Event
Wakeup
Enable
Bits
Flag
Interrupt Vector
Comments
Temperature
ADC
Maskable
-
ITADC
The temperature ADC can wake-up the 8052 if the
ITADC flag is set . This flag is set according to the
description in the Temperature measurement
section. This wakeup event can be disabled by
disabling temperature measurements in the
Temperature and Voltage ADC Delta SFR
(DIFFPROG, 0xF3) in PSM2.
ΔT
VDCIN ADC
Maskable
FVADC
IPSM
IPSM
The VDCIN measurement can wake-up the 8052. The
FVADC is set according to the description in the
External Voltage Measurement section. This
wakeup event can be disabled by clearing the
EVADC in the Power Management Interrupt Enable
SFR (IPSME, 0xEC).
ΔV
Power Supply
Management
PSR
Non-
maskable
PSR
The 8052 will wake up if the power supply is
restored (if VSW switches to be connected to VDD).
The VSWSOURCE flag, bit 6 of the Peripheral
Configuration SFR (PERIPH, 0xF4) SFR, is set to
indicate that VSW is connected to VDD.
This is a nonmaskable wakeup event.
RTC
Midnight
Alarm
Non-
maskable
Midnight
Alarm
IRTC
IRTC
The ADE75XX/ADE71XX will wake up at midnight
every day to update its calendar.
This event is a nonmaskable wakeup event.
Maskable
Set an alarm to wake the ADE75XX/ADE71XX after
the desired amount of time.
The RTC Alarm is enabled by setting the alarm bit in
the RTC Configuration SFR (TIMECON, 0xA1).
I/O Ports
All I/O pins are treated as inputs. The weak pull-up on each I/O pin can be disabled individually in the Port 0 Weak pull-
up enable SFR (PINMAP0, 0xB2), Port 1 Weak pull-up enable SFR (PINMAP1, 0xB3) and Port 2 Weak pull-up enable SFR
(PINMAP2, 0xB4) to decrease current consumption and also avoid powering up disabled peripheral through the internal
pull-up through the I2C port for example. The interrupts can be enabled/disabled.
INT0
INT0PROG
=1
-
IE0
The edge of the interrupt is selected by TCON.IT0
The IE0 flag bit in the TCON register will not be affected.
The edge of the interrupt is selected by TCON.IT1
The IE1 flag bit in the TCON register will not be affected.
INT1
INT1PROG
[2:0 ]= 11X
-
IE1
RX Edge
RXPROG [1:0] PERIPH.7
-
An RX Edge event will occur if a rising or falling edge is
detected on the RX line
= 11
(RXFG)
-
External Reset
LCD
RESET
Non-
-
-
-
If the RESET pin is brought low while the ADE75XX/ADE71XX
is in PSM2, it will wake up to PSM1.
maskable
-
-
-
-
-
The LCD can be enabled/disabled in PSM2. The LCD data
memory will remain intact.
Scratchpad
-
The 4 SCRATCHx registers will remain intact in PSM2.
section describes events that change the operating mode.
TRANSITIONING BETWEEN OPERATING MODES
Automatic Battery Switchover (PSM0 to PSM1)
The operating mode of the ADE75XX/ADE71XX is determined
by the power supply connected to VSW. Therefore a change in
the power supply such as when VSW switches from VDD to VBAT
or when VSW switches to VDD changes the operating mode. This
If any of the enabled battery switchover events occur (see the
Battery Switchover section), VSW switches to VBAT. This
switchover results in a transition from the PSM0 to PSM1
Rev. PrE | Page 33 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
operating mode. When battery switchover occurs, the analog
circuitry used in the ADE energy measurement DSP is disabled.
To reduce power consumption, the user code can initiate a
transition to PSM2.
that code execution will continue normally. A software reset can
be performed to start PSM0 code execution at the power on
reset vector.
USING THE POWER MANAGEMENT FEATURES
Entering Sleep Mode (PSM1 to PSM2)
Since program flow is different for each operating mode, the
status of VSW must be known at all times. The VSWSOURCE bit
in the Power Management Interrupt Flag SFR (IPSMF, 0xF8)
indicates what VSW is connected to. This bit can be used to
control program flow on wakeup. Since code execution always
starts at the power on reset vector, bit 6 of the Peripheral
Configuration SFR (PERIPH, 0xF4) can be tested to determine
which power supply is being used and to branch to normal code
execution or to wakeup event code execution. Power supply
events can also occur when the MCU core is active. To be aware
of events that change what VSW is connected to:
To reduce power consumption when VSW is connected to VBAT
,
user code can initiate sleep mode, PSM2, by setting bit 4 in the
Power Control SFR (POWCON, 0xC5) to shut down the MCU
core. Events capable of waking the MCU can be enabled—see
the 3.3V Peripherals and Wakeup Events section.
Servicing Wakeup Events (PSM2 to PSM1)
The ADE75XX/ADE71XX may need to wake up from PSM2 to
service wakeup events – see the 3.3V Peripherals and Wakeup
Events section. PSM1 code execution will begin at the power on
reset vector. After servicing the wakeup event, the
ADE75XX/ADE71XX can return to PSM2 by setting bit 4 in the
Power Control SFR (POWCON, 0xC5) to shut down the MCU
core.
¾
Enable the battery switchover interrupt (EBSO) if VSW=VDD
at power up.
¾
Enable the power supply restored interrupt (EPSR) if
VSW=VBAT at power up.
Automatic Switch to VDD (PSM2 to PSM0)
If the conditions to switch VSW from VBAT to VDD occur (see the
Battery Switchover section), the operating mode will switch to
PSM0. When this switch occurs, the MCU core and the analog
circuitry used in the ADE energy measurement DSP will start
up again automatically. PSM0 code execution will begin at the
power on reset vector.
An early warning that battery switchover is about to occur is
provided by SAG detection and possibly low VDCIN detection—
see the Battery Switchover section.
For a user controlled battery switchover, enable automatic
battery switchover on low VDD only. Then enable the low VDCIN
event to generate the PSM interrupt. When a low VDCIN event
occurs, start data backup. Upon completion of the data backup,
enable battery switchover on low VDCIN. Then battery switchover
will occur TBDms later.
Automatic Switch to VDD (PSM1 to PSM0)
If the conditions to switch VSW from VBAT to VDD occur (see the
Battery Switchover section), the operating mode will switch to
PSM0. When this switch occurs, the analog circuitry used in the
ADE energy measurement DSP will start up automatically. Note
Power Supply
Restored
PSM0
PSM1
Automatic Battery
Switchover
Normal Mode
Battery Mode
V
V
V
V
SW connected to DD
SW connected to BAT
User code directs MCU
to shutdown core after
servicing wakeup event
Wakeup
Event
Power Supply
Restored
PSM2
Sleep Mode
V
V
SW connected to BAT
Figure 15: Transitioning between Operating Modes
Rev. PrE | Page 34 of 148
Preliminary Technical Data
ENERGY MEASUREMENT
ADE75xx/ADE71xx
When bit7 of MADDPT SFR is set, the content of the MDATA
SFRs (MDATL, MDATM and MDATH) is transferred to the
internal energy measurement register designated by the address
in MADDPT SFR. If the internal register is one byte long, only
MDATL SFR content is copied to the internal register while
MDATM and MDATH SFR contents are ignored.
The ADE75xx/ADE71xx provides a fixed function energy
measurement Digital Processing core that provides all the
information needed to measure energy in a single phase energy
meters. The ADE75xx/ADE71xx provides two ways to access
the energy measurements: Direct access through SFR for time
sensitive information and indirect access through address and
data SFR registers for the majority of the energy measurements.
The IRMS, VRMS, interrupts and waveform registers are readily
available through SFRs as shown in Table 26. Other energy
measurement information is mapped to a page of memory that
is accessed indirectly through. The address and data registers
act as pointers to the energy measurement internal registers.
The energy measurement core functions with an internal clock
of 4.096 MHz/5 or 819.2 kHz. As the 8052 core functions with
another clock, 4.096MHz / 2CD, synchronization between the
two clock environments when CD = 0 or 1 is an issue. When
data is written to the internal energy measurement a small wait
period need to be implemented before another read or write to
these registers is implemented.
Sample 8051 code to write 0x0155 to the two bytes SAGLVL
register, located at 14h in the energy measurement memory
space is shown below:
ACCESS TO ENERGY MEASUREMENT SFR
Access to the energy measurement SFRs is achieved by reading
or writing to the SFR addresses detailed in Table 27. The
internal data for the MIRQx SFRs are latched byte by byte into
the SFR when the SFR is read.
MOV MDATM,#01h
MOV MDATL,#55h
MOV MADDPT,#SAGLVL_W (address 0x94)
The WAV1x, WAV2x, VRMSx and IRMSx registers are all 3
bytes SFRs. The 24-bit data is latched into these SFRs when the
High byte is read. Reading the Low or Medium byte before the
High byte results in reading the date from the previous latched
sample.
MOV A, #05h
DJNZ ACC, $
;Next Write or read to Energy Measurement SFR can
be done after this.
Reading Internal energy measurement
registers
Sample 8051 code to read the VRMS register is shown below:
MOV R1, VRMSH //latches data in VrmsH, VrmsM and
VrmsL SFR
MOV R2, VRMSM
When bit7 of MADDPT SFR is cleared, the content of the
internal energy measurement register designated by the address
in MADDPT is transferred to the MDATA SFRs (MDATL,
MDATM and MDATH). If the internal register is one byte long,
only the MDATL SFR content is updated with a new value while
MDATM and MDATH SFR content are reset to 00h.
MOV R3, VRMSL
ACCESS TO INTERNAL ENERGY MEASUREMENT
REGISTERS
The energy measurement core functions with an internal clock
of 4.096 MHz/5 or 819.2 kHz. As the 8052 core functions with
another clock, 4.096MHz / 2CD, synchronization between the
two clock environments when CD = 0 or 1 is an issue. When
data is read from the internal energy measurement, a small wait
period need to be implemented before the MDATx SFRs are
transferred to another SFR.
Access to the internal energy measurement registers is achieved
by writing to the Energy Measurement pointer address (SFR
address 91h). The MADDPT register selects the energy
measurement register to be accessed and determines if a read or
a write is performed—see Table 26.
Table 26. Energy Measurement pointer address SFR
(MADDPT, 0x91)
Sample 8051 code to read the peak voltage in the 2-byte
VPKLVL register, located at 0x16, into the data pointer is shown
below:
Bit
7
6
5
4
3
2
1
0
Description
1: Write
0: Read
Energy Measurement internal
register address
MOV MADDPT,#VPKLVL_R (address 0x16)
MOV A, #05h
DJNZ ACC, $
MOV DPH, MDATM
MOV DPL, MDATL
Writing to Internal energy measurement
registers
Rev. PrE | Page 35 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Table 27. Energy measurement SFRs
SFR
address
(hex)
R/W
Name
Description
0x91
0x92
R/W
R/W
R/W
R/W
R
MADDPT
MDATL
Energy Measurement Pointer Address
Energy Measurement Pointer Data LSByte
Energy Measurement Pointer Data Middle byte
Energy Measurement Pointer Data MSByte
Vrms measurement LSByte
0x93
MDATM
MDATH
VRMSL
0x94
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
R
VRMSM
VRMSH
IRMSL
Vrms measurement Middle byte
R
Vrms measurement MSByte
R
Irms measurement LSByte
R
IRMSM
Irms measurement Middle byte
R
IRMSH
Irms measurement MSByte
R/W
R/W
R/W
R/W
R/W
R/W
R
MIRQENL
MIRQENM
MIRQENH
MIRQSTL
MIRQSTM
MIRQSTH
WAV1L
Energy measurement interrupt enable LSByte
Energy measurement interrupt enable Middle byte
Energy measurement interrupt enable MSByte
Energy measurement interrupt status LSByte
Energy measurement interrupt status Middle byte
Energy measurement interrupt status MSByte
Selection 1 sample LSByte
R
WAV1M
WAV1H
WAV2L
Selection 1 sample Middle byte
R
Selection 1 sample MSByte
R
Selection 2 sample LSByte
R
WAV2M
WAV2H
Selection 2 sample Middle byte
R
Selection 2 sample MSByte
ENERGY MEASUREMENT REGISTERS
Table 28. Energy Measurement Register List
Address
MADDPT[6:0]
Name
R/W
Length
Signed
/Unsigned
Default
Value
Description
0x00
0x01
0x02
0x03
Reserved
WATTHR
RWATTHR
LWATTHR
-
-
-
-
-
R
R
R
24
24
24
S
S
S
0
0
0
Read Watt-hour accumulator without reset
Read Watt-hour accumulator with reset
Read Watt-hour accumulator synchronous to line
cycle
Rev. PrE | Page 36 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Address
MADDPT[6:0]
Name
R/W
Length
Signed
/Unsigned
Default
Value
Description
0x04
0x05
0x06
VARHR
R
R
R
24
24
24
S
S
S
0
0
0
Read VAR-hour accumulator without reset3
Read VAR-hour accumulator with reset1
RVARHR
LVARHR
Read VAR-hour accumulator synchronous to line
cycle1
0x07
0x08
0x09
0x0A
VAHR
R
R
R
R
24
24
24
16
S
S
0
0
0
0
Read VA-hour accumulator without reset
Read VA-hour accumulator with reset
RVAHR
LVAHR
PER_FREQ
S
Read VA-hour accumulator synchronous to line cycle
U
Read Line Period or Frequency register depending on
Mode2 register
0x0B
0x0C
0x0D
MODE1
R/W
R/W
R/W
8
8
8
U
U
U
0x06
0x40
0
Set basic configuration of energy measurement – see
Table 29
MODE2
Set basic configuration of energy measurement – see
Table 30
WAVMODE
Set configuration of waveform sample 1 and
waveform sample 2 – see Table 31
0x0E
0x0F
NLMODE
R/W
R/W
8
8
U
U
0
0
Set level of energy no-load thresholds - Table 32
ACCMODE
Set configuration of Watt, VAR accumulation and
various tamper alarms – see Table 33
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
PHCAL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
8
S
0x40
Set phase calibration register – see Phase
Compensation section
ZXTOUT
LINCYC
SAGCYC
SAGLVL
IPKLVL
12
16
8
0x0FFF
Set time out for Zero-crossing time out detection –
see Zero-Crossing Timeout
U
U
U
U
U
U
U
U
U
0xFFFF
Set number of half line cycles for LWATTHR, LVARHR
and LVAHR accumulators
0xFF
Set number of half line cycles for SAG detection – see
Line Voltage Sag Detection
16
16
16
24
24
16
16
0
Set detection level for SAG detection - see Line
Voltage Sag Detection
0xFFFF
Set peak detection level for current peak detection –
see Peak Detection
VPKLVL
IPEAK
0xFFFF
Set peak detection level for voltage peak detection–
see Peak Detection
0
0
0
0
Read current peak level without reset – see Peak
Detection
RSTIPEAK
VPEAK
R
Read current peak level with reset – see Peak
Detection
R
Read voltage peak level without reset – see Peak
Detection
RSTVPEAK
R
Read voltage peak level with reset – see Peak
Detection
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
GAIN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
U
S
S
S
S
S
S
S
S
U
0
0
0
0
0
0
0
0
0
0
Set PGA gain of analog inputs – see Table 34
Set Matching Gain for IB current input
Set Watt gain register
IBGAIN4
WGAIN
VARGAIN
VAGAIN
WATTOS
VAROS
IRMSOS
VRMSOS
WDIV
12
12
12
12
16
16
12
12
8
Set VAR gain register
Set VA gain register
Set Watt offset register
Set VAR offset register
Set current rms offset register
Set voltage rms offset register
Set Watt energy scaling register
3 This function is not available in ADE7566 and ADE7166 products.
4 This function is not available in ADE7566 and ADE7569 products.
Rev. PrE | Page 37 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Address
MADDPT[6:0]
Name
R/W
Length
Signed
/Unsigned
Default
Value
Description
0x25
0x26
0x27
0x28
0x29
0x2A
0x3D
VARDIV
VADIV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
U
U
U
U
U
U
U
0
Set VAR energy scaling register
Set VA energy scaling register
Set CF1 numerator register
Set CF1 denominator register
Set CF2 numerator register
Set CF2 denominator register
Set Calibration Mode
8
0
CF1NUM
CF1DEN
CF2NUM
CF2DEN
CALMODE
16
16
16
16
8
0
0x003F
0
0x003F
0
ENERGY MEASUREMENT INTERNAL REGISTERS DETAILS
Table 29. MODE1 register (0x0B)
Bit
Location
Bit
Mnemonic
SWRST
Default
Value
Description
7
0
Setting this bit will reset all of the energy measurement registers to their
default values
6
5
4
3
2
1
0
DISZXLPF
INTE1
0
0
0
0
1
1
0
Setting this bit disables the zero-crossing lowpass filter
Setting this bit enables the digital integrator for use with a di/dt sensor
Setting this bit swaps CH1 & CH2 ADCs
SWAPBITS
PWRDN
DISCF2
DISCF1
DISHPF
Setting this bit powers down voltage and current ADC’s
Setting this bit disables Frequency output CF2
Setting this bit disables Frequency output CF1
Setting this bit disables the HPFs in voltage and current channels
Table 30. MODE2 register (0x0C)
Bit
Location
7-6
Bit
Mnemonic
CF2SEL[1:0]
Default
Value
Description
01
00
0
Configuration bits for CF2 output
CF2SEL[1:0] Source
00
01
1x
CF2 frequency is proportional to active power
CF2 frequency is proportional to reactive power5
CF2 frequency is proportional to apparent power or
IRMS
5-4
CF1SEL[1:0]
Configuration bits for CF1 output
CF1SEL[1:0] Source
00
01
1x
CF1 frequency is proportional to active power
CF1 frequency is proportional to reactive power1
CF1 frequency is proportional to apparent power or
IRMS
3
VARMSCFCON
Configuration bits for apparent power or IRMS for CF1 and CF2 outputs
0
If CF1SEL[1:0]=1x, CF1 is proportional to VA
If CF2SEL[1:0]=1x, CF2 is proportional to VA
If CF1SEL[1:0]=1x, CF1 is proportional to IRMS
If CF2SEL[1:0]=1x, CF2 is proportional to IRMS
1
Note that CF1 cannot be proportional to VA if CF2 is proportional to IRMS
and vice versa
2
1
ZXRMS
0
0
Logic one enables update of RMS values synchronously to voltage ZX
FREQSEL
Configuration bits to select PERIOD or FREQUENCY measurement for
PER_FREQ register (0Ah)
0
PER_FREQ register holds a period measurement
5 This function is not available in ADE7566 and ADE7166 products.
Rev. PrE | Page 38 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
1
PER_FREQ register holds a frequency measurement
0
Reserved
1
This bit should be kept to one
Table 31. WAVMODE register (0x0D)
Bit
Location
7-5
Bit
Default
Value
Description
Mnemonic
WAV2SEL[2:0]
0
0
0
Waveform 2 selection for samples mode
WAV2SEL[2:0] Source
000
001
010
011
100
101
others
Current
Voltage
Active Power multiplier output
Reactive Power multiplier output6
VA multiplier output
IRMS LPF output
Reserved
4-2
WAV1SEL[2:]
Waveform 1 selection for samples mode
WAV1SEL[2:0] Source
000
001
010
011
100
101
others
Current
Voltage
Active Power multiplier output
Reactive Power multiplier output1
VA multiplier output
IRMS LPF output (low 24-bit)
Reserved
1-0
DTRT[1:0]
Waveform samples output data rate
DTRT[1:0]
Update rate (clock=MCLK/5=819.2kHz)
00
01
10
11
25.6Ksps(clock/32)
12.8Ksps(clock/64)
6.4Ksps(clock/128)
3.2Ksps(clock/256)
Table 32. NLMODE register (0x0E)
Bit
Location
Bit
Default
Value
Description
Mnemonic
DISVARCMP1
7
0
Setting this bit disables fundamental VAR gain compensation over line
frequency
6
IRMSNOLOAD
0
0
Logic one enables IRMS no-load thresold detection. The level is defined by
the setting of the VANOLOADbits.
5-4
VANOLOAD[1:0]
Apparent Power No-load threshold
[1:0]
00
01
10
11
No-load detection disabled
No-load enabled with threshold = 0.030% of Full scale
No-load enabled with threshold = 0.015% of Full scale
No-load enabled with threshold = 0.0075% of Full scale
3-2
1-0
VARNOLOAD[1:0] 1
0
0
Reactive Power No-load threshold
[1:0]
00
01
10
11
No-load detection disabled
No-load enabled with threshold = 0.015% of Full scale
No-load enabled with threshold = 0.0075% of Full scale
No-load enabled with threshold = 0.0037% of Full scale
APNOLOAD[1:0]
Active Power No-load threshold
6 This function is not available in ADE7566 and ADE7166 products.
Rev. PrE | Page 39 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
[1:0]
00
No-load detection disabled
01
10
11
No-load enabled with threshold = 0.015% of Full scale
No-load enabled with threshold = 0.0075% of Full scale
No-load enabled with threshold = 0.0037% of Full scale
Table 33. ACCMODE register (0x0F)
Bit
Location
Bit
Mnemonic
ICHANNEL7
Default
Value
Description
7
0
This bit indicate the current channel used to measure energy in anti-
tampering mode.
0 – Channel A
1 – Channel B
6
5
FAULTSIGN1
VARSIGN8
0
0
Configuration bit to select event that will trigger a Fault interrupt
0 – FAULT interrupt occurs when part enters Fault Mode
1 – FAULT interrupt occurs when part enters Normal Mode
Configuration bit to select event that will trigger an reactive power sign
interrupt
0 – VARSIGN interrupt occurs when reactive power changes from positive
to negative
1 - VARSIGN interrupt occurs when reactive power changes from negative
to positive
4
APSIGN
0
Configuration bit to select event that will trigger an active power sign
interrupt
0 – APSIGN interrupt occurs when active power changes from positive to
negative
1 - APSIGN interrupt occurs when active power changes from negative to
positive
3
2
ABSVARM2
SAVARM2
0
0
Logic one enables absolute value accumulation of Reactive power in
energy register and pulse output
Logic one enables reactive power accumulation depending on the sign of
the active power:
If Active Power is positive, VAR is accumulated as it is;
If Active Power is negative, the sign of the VAR is reversed for the
accumulation.
This accumulation mode affects both the VAR registers and the VARCF
output.
1
0
POAM
0
0
Logic one enables positive only accumulation of Active power in energy
register and pulse output
ABSAM
Logic one enables absolute value accumulation of Active power in energy
register and pulse output
Table 34. GAIN register (0x1B)
Bit
Location
7 - 5
Bit
Mnemonic
PGA2[2:0]
Default
Value
Description
0
These bits define the voltage channel input gain
[2:0]
000 Gain = 1
001 Gain = 2
010 Gain = 4
011 Gain = 8
7 This function is not available in ADE7566 and ADE7569 products.
8This function is not available in ADE7566 and ADE7166 products.
Rev. PrE | Page 40 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
100 Gain = 16
Reserved
4
3
Reserved
0
0
CFSIGN_OPT
This bit defines where the CF change of sign, APSIGN or VARSIGN,
detection is implemented.
0
1
Filtered power signal
On a per CF pulse basis
2 - 0
PGA1[2:0]
0
These bits define the current channel input gain
[2:0]
000 Gain = 1
001 Gain = 2
010 Gain = 4
011 Gain = 8
100 Gain = 16
Table 3ꢀ. CALMODE register (0x3D)
Bit
Location
Bit
Mnemonic
Default
Value
Description
7 – 6
5 - 4
Reserved
SEL_I_CH[1:0]9
0
0
These bits should be kept cleared for proper operation
These bits define the current channel used for energy measurements
[1:0]
00 Current channel automatically selected by the tampering condition
01 Current channel connected to IA
10 Current channel connected to IB
11 Current channel automatically selected by the tampering condition
Logic one short voltage channel to ground
3
V_CH_SHORT
I_CH_SHORT
Reserved
0
0
2
Logic one short Current channels to ground
1 - 0
Table 36. Interrupt Status Register 1 SFR (MIRQSTL, 0xDC)
Bit
Interrupt Flag
Description
Location
7
ADEIRQFLAG
This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt
are set. This bit is automatically cleared when all of the enabled ADE status flags are
cleared.
6
5
Reserved
FAULTSIGN1
Reserved.
Logic one indicates that the Fault mode has changed according to the configuration of
the ACCMODE register
4
3
2
VARSIGN10
APSIGN
Logic one indicates that the reactive power sign changed according to the configuration
of ACCMODE register
Logic one indicates that the active power sign changed according to the configuration of
ACCMODE register
VANOLOAD
Logic one indicates that an interrupt was caused by apparent power no-load detected.
This interrupt is also used to reflect the part entering the IRMS No load mode.
1
0
RNOLOAD2
APNOLOAD
Logic one indicates that an interrupt was caused by reactive power no-load detected.
Logic one indicates that an interrupt was caused by active power no-load detected.
Table 37. Interrupt Status Register 2 SFR (MIRQSTM, 0xDD)
Bit
Interrupt Flag
Description
Location
9 This function is not available in ADE7566 and ADE7569 products.
10 This function is not available in ADE7566 and ADE7166 products.
Rev. PrE | Page 41 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
7
CF2
Logic one indicates that a pulse on CF2 has been issued. The flag is set even if CF2 pulse
output is not enabled by clearing bit 2 of MODE1 register.
6
CF1
Logic one indicates that a pulse on CF1 has been issued. The flag is set even if CF1 pulse
output is not enabled by clearing bit 1 of MODE1 register.
5
4
3
2
1
0
VAEOF
REOF11
AEOF
Logic one indicates that the VAHR register has overflowded
Logic one indicates that the VARHR register has overflowded
Logic one indicates that the WATTHR register has overflowded
Logic one indicates that the VAHR register is half full
Logic one indicates that the VARHR register is half full
Logic one indicates that the WATTHR register is half full
VAEHF
REHF1
AEHF
Table 38. Interrupt Status Register 3 SFR (MIRQSTH, 0xDE)
Bit
Interrupt Flag
Description
Location
7
6
5
4
3
2
RESET
-
Indicates the end of a reset (for both sofware or hardware reset).
Reserved
WFSM
PKI
Logic one indicates that new data is present in the Waveform Registers
Logic one indicates that current channel has exceeded the IPKLVL value
Logic one indicates that voltage channel has exceeded the VPKLVL value.
PKV
CYCEND
Logic one indicates the end of the energy accumulation over an integer number of half
line cycles.
1
0
ZXTO
ZX
Logic one indicates that no zero crossing on the line voltage happened for the last
ZXTOUT half line cycles.
Logic one indicates detection of a zero crossing in the voltage channel.
Table 39. Interrupt Enable Register 1 SFR (MIRQENL, 0xD9)
Bit
Interrupt Flag
Description
Location
7-6
5
Reserved
FAULTSIGN12
Reserved.
When this bit is set, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052
core.
4
3
2
VARSIGN1
APSIGN
When this bit is set, the VARSIGN bit set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the APSIGN bit set creates a pending ADE interrupt to the 8052 core.
VANOLOAD
When this bit is set, the VANOLOAD bit set creates a pending ADE interrupt to the 8052
core.
1
0
RNOLOAD1
APNOLOAD
When this bit is set, the RNOLOAD bit set creates a pending ADE interrupt to the 8052
core.
When this bit is set, the APNOLOAD bit set creates a pending ADE interrupt to the 8052
core.
Table 40. Interrupt Enable Register 2 SFR (MIRQENM, 0xDA)
Bit
Interrupt Flag
Description
Location
7
6
5
4
3
2
1
CF2
When this bit is set, a CF2 pulse issued creates a pending ADE interrupt to the 8052 core.
When this bit is set, a CF1 pulse issued creates a pending ADE interrupt to the 8052 core.
When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core.
CF1
VAEOF
REOF1
AEOF
VAEHF
REHF1
11 This function is not available in ADE7566 and ADE7166 products.
12 This function is not available in ADE7566 and ADE7569 products.
Rev. PrE | Page 42 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
0
AEHF
When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
Table 41. Interrupt Enable Register 3 SFR (MIRQENH, 0xDB)
Bit
Interrupt Flag
Description
Location
7-6
5
-
Reserved
WFSM
PKI
When this bit is set, the WFSM flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the PKI flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the PKV flag set creates a pending ADE interrupt to the 8052 core..
When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core.
4
3
PKV
2
CYCEND
ZXTO
ZX
1
0
GAIN[7:0]
ANALOG INPUTS
7
0
6
0
5
0
4
3
2
0
1
0
0
0
The ADE75XX/ADE71XX has two fully differential voltage
input channels. The maximum differential input voltage for
input pairs VP/VN and IP/IN are 0.5 V. In addition, the
maximum signal level on analog inputs for VP/VN and IP/ IN
is 0.5 V with respect to AGND.
0
0
GAIN (K)
SELECTION
V1P
Each analog input channel has a PGA (programmable gain
amplifier) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the GAIN register in the
Energy Measurement Register List—see Table 34 and
V
IN
K ⋅ V
IN
GAIN REGISTER*
CURRENT AND VOLTAGE CHANNELS PGA CONTROL
7
6
5
4
3
2
1
0
V1N
0
0
0
0
0
0
0
0
ADDR:
1BH
Figure 16. PGA in current channel
PGA 2 GAIN SELECT
000 = x 1
001 = x 2
010 = x 4
011 = x 8
PGA 1 GAIN SELECT
000 = x 1
001 = x 2
010 = x 4
011 = x 8
In addition to the PGA, Channel 1 also has a full-scale input range selection
for the ADC. The ADC analog input range selection is also made using the
gain register—see
GAIN REGISTER*
100 = x 16
100 = x 16
CURRENT AND VOLTAGE CHANNELS PGA CONTROL
RESERVED
7
6
5
4
3
2
1
0
*REGISTER CONTENTS
SHOW POWER-ON DEFAULTS
0
0
0
0
0
0
0
0
ADDR:
1BH
Figure 17. Bits 0 to 2 select the gain for the PGA in the current
channel, and the gain selection for the PGA in voltage channel is
made via Bits 5 to 7. Figure 16 shows how a gain selection for
the current channel is made using the gain register.
PGA 2 GAIN SELECT
000 = x 1
001 = x 2
010 = x 4
011 = x 8
PGA 1 GAIN SELECT
000 = x 1
001 = x 2
010 = x 4
011 = x 8
100 = x 16
100 = x 16
RESERVED
*REGISTER CONTENTS
SHOW POWER-ON DEFAULTS
Figure 17. As mentioned previously, the maximum differential
input voltage is 0.5 V.
Rev. PrE | Page 43 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
GAIN REGISTER*
CURRENT AND VOLTAGE CHANNELS PGA CONTROL
sampled at a rate (frequency), which is many times higher than
the bandwidth of interest. For example, the sampling rate in the
ADE75xx/ADE71xx is MCLK/5 (819.2 kHz) and the band of
interest is 40 Hz to 2 kHz. Oversampling has the effect of
spreading the quantization noise (noise due to sampling) over a
wider bandwidth. With the noise spread more thinly over a
wider bandwidth, the quantization noise in the band of interest
is lowered — see Figure 19. However, oversampling alone is not
efficient enough to improve the signal-to-noise ratio (SNR) in
the band of interest. For example, an oversampling ratio of 4 is
required just to increase the SNR by only 6 dB (1 bit). To keep
the oversampling ratio at a reasonable level, it is possible to
shape the quantization noise so that the majority of the noise
lies at the higher frequencies. In the Σ-Δ modulator, the noise is
shaped by the integrator, which has a high-pass-type response
for the quantization noise. The result is that most of the noise is
at the higher frequencies where it can be removed by the digital
low-pass filter. This noise shaping is shown in Figure 19.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
ADDR:
1BH
PGA 2 GAIN SELECT
000 = x 1
PGA 1 GAIN SELECT
000 = x 1
001 = x 2
010 = x 4
011 = x 8
100 = x 16
001 = x 2
010 = x 4
011 = x 8
100 = x 16
RESERVED
*REGISTER CONTENTS
SHOW POWER-ON DEFAULTS
Figure 17. ADE75XX/ADE71XX Analog Gain Register
ANALOG TO DIGITAL CONVERSION
The ADE75XX/ADE71XX has two sigma-delta Analog to
Digital Converters (ADC). The outputs of these ADCs are
mapped directly to waveform sampling SFRs (address 0xE2 to
0xE7) and are used for the energy measurement internal digital
signal processing. In PSM1 (Battery mode)and PSM2 (Sleep
mode), the ADCs are powered down to minimize power
consumption.
ANTILALIAS
FILTER (RC)
DIGITAL
FILTER
SAMPLING
FREQUENCY
SIGNAL
SHAPED
NOISE
For simplicity, the block diagram in Figure 18 shows a first-
order Σ-Δ ADC. The converter is made up of the Σ-Δ
modulator and the digital low-pass filter.
NOISE
MCLK/5
0
2
409.6
FREQUENCY (kHz)
819.2
ANALOG
DIGITAL
LOW-PASS FILTER
INTEGRATOR
LOW-PASS
FILTER
LATCHED
COMPARATOR
+
R
HIGH RESOLUTION
OUTPUT FROM DIGITAL
LPF
+
–
–
SIGNAL
C
24
V
REF
NOISE
.....10100101.....
1-BIT DAC
0
2
409.6
FREQUENCY (kHz)
819.2
02875-0-047
Figure 19. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
Figure 18. First-Order Σ-∆ ADC
A Σ-∆ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE75xx/ADE71xx, the sampling clock is equal to
MCLK/5. The 1-bit DAC in the feedback loop is driven by the
serial data stream. The DAC output is subtracted from the input
signal. If the loop gain is high enough, the average value of the
DAC output (and therefore the bit stream) can approach that of
the input signal level. For any given input value in a single
sampling interval, the data from the 1-bit ADC is virtually
meaningless. Only when a large number of samples are averaged
is a meaningful result obtained. This averaging is carried out in
the second part of the ADC, the digital low-pass filter. By
averaging a large number of bits from the modulator, the low-
pass filter can produce 24-bit data-words that are proportional
to the input signal level.
Anti-aliasing Filter
Figure 18 also shows an analog low-pass filter (RC) on the input
to the modulator. This filter is present to prevent aliasing.
Aliasing is an artifact of all sampled systems. Aliasing means
that frequency components in the input signal to the ADC,
which are higher than half the sampling rate of the ADC,
appear in the sampled signal at a frequency below half the
sampling rate. Figure 20 illustrates the effect. Frequency
components (arrows shown in black) above half the sampling
frequency (also know as the Nyquist frequency, i.e., 409.6 kHz)
are imaged or folded back down below 409.6 kHz. This happens
with all ADCs regardless of the architecture. In the example
shown, only frequencies near the sampling frequency, i.e., 819.2
kHz, move into the band of interest for metering, i.e., 40 Hz to 2
kHz. This allows the use of a very simple LPF (low-pass filter)
to attenuate high frequency (near 819.2 kHz) noise, and
prevents distortion in the band of interest. For conventional
current sensors, a simple RC filter (single-pole LPF) with a
The Σ-Δ converter uses two techniques to achieve high
resolution from what is essentially a 1-bit conversion technique.
The first is oversampling. Oversampling means that the signal is
Rev. PrE | Page 44 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
corner frequency of 10 kHz produces an attenuation of
approximately 40 dB at 819.2 kHz — see Figure 20. The 20 dB
per decade attenuation is usually sufficient to eliminate the
effects of aliasing for conventional current sensors. However, for
a di/dt sensor such as a Rogowski coil, the sensor has a 20 dB
per decade gain. This neutralizes the –20 dB per decade
attenuation produced by one simple LPF. Therefore, when using
a di/dt sensor, care should be taken to offset the 20 dB per
decade gain. One simple approach is to cascade two RC filters to
produce the –40 dB per decade attenuation needed.
Both ADCs in the ADE75xx/ADE71xx are designed to produce
the same output code for the same input signal level. With a
full-scale signal on the input of 0.5 V and an internal reference
of 1.2 V, the ADC output code is nominally 2,684,354 or
28F5C2h. The maximum code from the ADC is 4,194,304; this
is equivalent to an input signal level of 0.794 V. However, for
specified performance, it is recommended that the full-scale
input signal level of 0.5 V not be exceeded.
Current Channel ADC
ALIASING EFFECTS
Figure 21 shows the ADC and signal processing chain for the
current channel. In waveform sampling mode, the ADC outputs
a signed twos complement 24-bit data-word at a maximum of
25.6 kSPS (MCLK/160). With the specified full-scale analog
input signal of 0.5 V (or 0.25 V or 0.125 V—see the Analog
Inputs section) the ADC produces an output code that is
approximately between 0x28F5C2 (+2,684,354d) and
0xD70A3E (–2,684,354d)—see Figure 21.
SAMPLING
FREQUENCY
IMAGE
FREQUENCIES
0
2
409.6
819.2
FREQUENCY (kHz)
Figure 20. ADC and Signal Processing in current channel Outline Dimensions
ADC Transfer Function
x1, x2, x4,
x8, x16
REFERENCE
MODE1[5]
CURRENT RMS (IRMS)
CALCULATION
{GAIN[2:0]}
IAP
HPF
WAVEFORM SAMPLE
DIGITAL
INTEGRATOR*
PGA1
PGA1
I
ADC
ADC
REGISTER
ACTIVE AND REACTIVE
POWER CALCULATION
IN
dt
HPF
IBP
CURRENT CHANNEL
WAVEFORM
50Hz
DATA RANGE AFTER
INTEGRATOR (50Hz)
0x342CD0
V1
0.5V, 0.25V,
0.125V, 62.5mV,
31.3mV
0x000000
CURRENT CHANNEL
WAVEFORM
0V
DATA RANGE
0xCBD330
0x28F5C2
CURRENT CHANNEL
WAVEFORM
DATA RANGE AFTER
INTEGRATOR (60Hz)
ANALOG
INPUT
RANGE
0x000000
0xD70A3E
60Hz
0x2B7850
0x000000
0xD487B0
*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED
DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE
FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED.
Figure 21. ADC and Signal Processing in Current Channel
output code that is approximately between 0x28F5 (+10,485d)
and 0xD70B (–10,485d)—see Figure 22.
Voltage Channel ADC
Figure 21 shows the ADC and signal processing chain for the
Voltage Channel. In waveform sampling mode, the ADC
outputs a signed twos complement 24-bit data-word at a
maximum of 25.6 kSPS (MCLK/160). The ADC produces an
Rev. PrE | Page 45 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
ACTIVE AND REACTIVE
POWER CALCULATION
x1, x2, x4,
x8, x16
{GAIN[7:5]}
VP
REFERENCE
ADC
VOLTAGE RMS (VRMS)
CALCULATION
HPF
WAVEFORM SAMPLE
REGISTER
PGA2
V2
VOLTAGE PEAK DETECT
V2
0.5V, 0.25V,
ZX DETECTION
0.125V, 62.5mV,
31.3mV
LPF1
= 63.7Hz
3dB
f
–
0V
VOLTAGE CHANNEL
WAVEFORM
ZX SIGNAL
DATA RANGE for 60Hz signal
DATA RANGE
0x1DD0
ANALOG
INPUT
MODE1[6]
0x28F5
RANGE
0x0000
0xE230
0x0000
0xD70B
ZX SIGNAL
DATA RANGE for 50Hz signal
0x2037
0x0000
0xDFC9
Figure 22. ADC and Signal Processing in Voltage Channel
6.25ꢀ of the active channel. If a fault condition is detected and
the inactive channel is larger than the active channel, the
ADE75xx/ADE71xx automatically switches to current
measurement to the inactive channel. During a fault, the active,
reactive, current rms and apparent powers are generated using
the larger of the two currents. On power-up, IA is the current
input selected for Active, Reactive, and Apparent power and
Irms calculations.
Channel Sampling
The waveform samples of the current ADC and voltage ADC
can also be routed to the waveform registers to be read by the
MCU core. The active, reactive, apparent power, and energy
calculation remain uninterrupted during waveform sampling.
When in waveform sampling mode, one of four output sample
rates can be chosen by using Bits 0 and 1 of the WAVMODE
register (WAVSEL1,0). The output sample rate can be 25.6 kSPS,
12.8kSPS, 6.4 kSPS, or 3.2 kSPS—see Table 31. If the WFSM
enable bit is set in the Interrupt Enable Register 3 SFR
(MIRQENH, 0xDB), the 8052 core has a pending ADE
interrupt. The sampled signals selected in the WAVMODE
register will be latched into the Waveform SFRs when the
waveform high byte (WAV1H or WAV2H) is read.
To prevent false alarm, averaging is done for the fault detection
and a fault condition is detected approximately 1 second after
the event. The fault detection is automatically disabled when the
voltage signal is less than 0.3ꢀ of the full-scale input range. This
eliminates false detection of a fault due to noise at light loads.
Because the ADE75xx/ADE71xx looks for a difference between
the voltage signals on IA and IB, it is important that both current
transducers be closely matched.
The ADE interrupt stays active until the WFSM status bit is
cleared—see Energy measurement interrupts section.
FAULT DETECTION13
Channel selection Indication
The current channel selected for measurement is indicated by
bit 7 (ICHANNEL) in the ACCMODE register (0x0F). When
this bit is cleared, IA is selected and when it is set, IB is selected.
The ADE75xx/ADE71xx automatically switches from one
channel to the other and reports the channel configuration in
the ACCMODE register (0x0F).
The ADE75xx/ADE71xx incorporates a fault detection scheme
that warns of fault conditions and allows the
ADE75xx/ADE71xx to continue accurate measurement during
a fault event. The ADE75xx/ADE71xx does this by continuously
monitoring both current inputs (IA and IB). These currents will
be referred for ease of understanding as phase and neutral
(return) currents. In the ADE75xx/ADE71xx, a fault condition
is defined when the difference between IA and IB is greater than
The current channel selected for measurement can also be
forced. Setting one of the SELCH1A and SELCH1B bits in the
CALMODE register (0x3D) selects IA and IB respectively. When
13 This function is not available in ADE7566 and ADE7569 products.
Rev. PrE | Page 46 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
both bits are cleared or set, the current channel used for
measurement is selected automatically based on the Fault
detection.
chatter between IA and IB.
Calibration Concerns
Typically, when a meter is being calibrated, the voltage and
current circuits are separated as shown in Figure 23. This means
that current passes through only the phase or neutral circuit.
Figure 23 shows current being passed through the phase circuit.
This is the preferred option, because the ADE75xx/ADE71xx
starts billing on the input IA on power-up. The phase circuit CT
is connected to IA in the diagram. As the current sensors are not
perfectly matched, it is important to match current inputs. The
ADE75xx/ADE71xx provides a gain calibration register for IB,
IBGAIN (address 0x1C). IBGAIN is a 12-bit signed 2-
complement register that provides a gain resolution of
0.0244ꢀ/LSB.
Fault Indication
The ADE75xx/ADE71xx provides an indication of the part
going in or out of a fault condition. The new fault condition is
indicated by the FAULTSIGN flag (bit5) in the Interrupt Status
Register 1 SFR (MIRQSTL, 0xDC).
When FAULTSIGN bit (bit 6) of ACCMODE register (0x0F) is
cleared, the FAULTSIGN flag in the Interrupt Status Register 1
SFR (MIRQSTL, 0xDC) will be set when the part is entering
fault condition.
When FAULTSIGN bit (bit 6) of ACCMODE register (0x0F) is
set, the FAULTSIGN flag in the Interrupt Status Register 1 SFR
(MIRQSTL, 0xDC) will be set when the part is entering normal
condition.
For calibration, a first measurement should be done on IA by
setting SEL_I_CH bits to 0b01 in the CALMODE register
(0x3D). This measurement should be compared to the
measurement on IB. Measuring IB can be forced by setting
SEL_I_CH bits to 0b10 in the CALMODE register (0x3D). The
Gain error between these two measurements can be evaluated
When the FAULTSIGN bit is set in the Interrupt Enable
Register 1 SFR (MIRQENL, 0xD9), and the FAULTSIGN flag in
the Interrupt Status Register 1 SFR (MIRQSTL, 0xDC) is set, the
8052 core has a pending ADE interrupt.
Measurement
(
I B
)
− Measurement
I A
)
using:
Error
(
% =
)
Measurement
(
I A
)
Fault with Active Input Greater than Inactive
Input
The two channels IA and IB can then be matched by writing: –
Error(ꢀ) / (1 + Error (ꢀ)) * 212 to IBGAIN register. This
matching adjustment will be valid for all energy measurements,
Active power, reactive power, Irms, and Apparent power, made
by the ADE75xx/ADE71xx.
If IA is the active current input (that is, being used for billing),
and the voltage signal on IB (inactive input) falls below 93.75ꢀ
of IA, and the FAULTSIGN bit (bit 6) of ACCMODE register
(0x0F) is cleared, the FAULTSIGN flag in the Interrupt Status
Register 1 SFR (MIRQSTL, 0xDC) is set. Both analog inputs are
filtered and averaged to prevent false triggering of this logic
output. As a consequence of the filtering, there is a time delay of
approximately 3 s on the logic output after the fault event. The
FAULTSIGN flag is independent of any activity. Because IA is
the active input and it is still greater than IB, billing is
maintained on IA, that is, no swap to the IB input occurs. IA
remains the active input.
I
R
F
A
IB
CT
0
RB
RB
C
V
F
F
A
AGND
I
I
N
B
0V
C
TEST
CURRENT
CT
R
F
V
V
RA
P
Fault with Inactive Input Greater than Active
Input
C
F
R
F
N
RF
C
T
If the difference between IB, the inactive input, and IA, the active
input (that is, being used for billing), becomes greater than
6.25ꢀ of IB, and the FAULTSIGN bit (bit 6) of ACCMODE
register (0x0F) is cleared, the FAULTSIGN flag in the Interrupt
Status Register 1 SFR (MIRQSTL, 0xDC) is set. The analog
input IB becomes the active input. Again, a time constant of
about 3 s is associated with this swap. IA does not swap back to
the active channel until IA is greater than IB and the difference
between IA and IB—in this order—becomes greater than 6.25ꢀ
of IB. However, if FAULTSIGN bit (bit 6) of ACCMODE
register (0x0F) is set, the FAULTSIGN flag in the Interrupt
Status Register 1 SFR (MIRQSTL, 0xDC) will be set as soon as
IA is within 6.25ꢀ of IB. This threshold eliminates potential
V
240V RMS
Figure 23. Fault Conditions for Inactive Input Greater than Active Input
di/dt CURRENT SENSOR AND
DIGITAL INTEGRATOR14
A di/dt sensor detects changes in magnetic field caused by ac
current. Figure 24 shows the principle of a di/dt current sensor.
14 This function is not available in ADE7566 and ADE7166 products.
Rev. PrE | Page 47 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
–88.0
MAGNETIC FIELD CREATED BY CURRENT
(DIRECTLY PROPORTIONAL TO CURRENT)
–88.5
–89.0
+ EMF (ELECTROMOTIVE FORCE)
– INDUCED BY CHANGES IN
MAGNETIC FLUX DENSITY (di/dt)
–89.5
–90.0
–90.5
02875-0-035
Figure 24. Principle of a di/dt Current Sensor
The flux density of a magnetic field induced by a current is
directly proportional to the magnitude of the current. The
changes in the magnetic flux density passing through a
conductor loop generate an electromotive force (EMF) between
the two ends of the loop. The EMF is a voltage signal, which is
proportional to the di/dt of the current. The voltage output
from the di/dt current sensor is determined by the mutual
inductance between the current-carrying conductor and the
di/dt sensor. The current signal needs to be recovered from the
di/dt signal before it can be used. An integrator is therefore
necessary to restore the signal to its original form. The
ADE75xx/ADE71xx has a built-in digital integrator to recover
the current signal from the di/dt sensor. The digital integrator
on the Current Channel is switched off by default when the
ADE75xx/ADE71xx is powered up. Setting INTE bit in the
MODE1 register (0x0B) turns on the integrator. Figure 25 to
Figure 28 show the magnitude and phase response of the digital
integrator.
2
3
10
10
FREQUENCY (Hz)
02875-0-037
Figure 26. Combined Phase Response of the
Digital Integrator and Phase Compensator
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
10
40
45
50
55
60
65
70
02875-0-038
FREQUENCY (Hz)
0
Figure 27. Combined Gain Response of the
Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
–10
–89.70
–89.75
–89.80
–89.85
–89.90
–89.95
–90.00
–20
–30
–40
–50
2
3
10
10
FREQUENCY (Hz)
02875-0-036
Figure 25. Combined Gain Response of the
Digital Integrator and Phase Compensator
–90.05
40
45
50
55
60
65
70
FREQUENCY (Hz)
02875-0-039
Figure 28. Combined Phase Response of the
Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
Note that the integrator has a –20 dB/dec attenuation and an
approximately –90° phase shift. When combined with a di/dt
Rev. PrE | Page 48 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
sensor, the resulting magnitude and phase response should be a
flat gain over the frequency band of interest. The di/dt sensor
has a 20 dB/dec gain associated with it. It also generates signifi-
cant high frequency noise, therefore a more effective anti-
aliasing filter is needed to avoid noise due to aliasing—see the
Anti-aliasing Filter section.
of the voltage channel and ZX detection.
The zero-crossing detection also drives the ZX flag in the
Interrupt Status Register 3 SFR (MIRQSTH, 0xDE). If the ZX
bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) is
set, the 8052 core has a pending ADE interrupt.
The ADE interrupt stays active until the ZX status bit is
cleared—see Energy measurement interrupts section.
When the digital integrator is switched off, the
ADE75xx/ADE71xx can be used directly with a conventional
current sensor such as a current transformer (CT) or with a low
resistance current shunt.
Zero-Crossing Timeout
The zero-crossing detection also has an associated timeout
register, ZXTOUT. This unsigned, 12-bit register is decremented
(1 LSB) every 160/MCLK seconds. The register is reset to its
user programmed full-scale value every time a zero crossing is
detected on the voltage channel. The default power on value in
this register is 0xFFF. If the internal register decrements to 0
before a zero crossing is detected and the ZXTOUT flag in the
Interrupt Status Register 3 SFR (MIRQSTH, 0xDE) is set. If the
ZXTO bit in the Interrupt Enable Register 3 SFR (MIRQENH,
0xDB) is set, the 8052 core has a pending ADE interrupt.
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
The ADE75xx/ADE71xx has a zero-crossing detection circuit
on the voltage channel. This zero crossing is used to produce an
external zero-crossing signal (ZX), and it is also used in the
calibration mode.
The zero-crossing is generated, by default, from the output of
LPF1. As explained in the following paragraph, this filter has a
low cut-off frequency and is intended for use for 50 and 60Hz
system. If needed this filter can be disabled to allow a higher
frequency signal to be detected or to limit the group delay of the
detection. If the voltage input fundamental frequency is below
60Hz and a time delay in ZX detection is acceptable, it is
recommended to enable LPF1. Enabling LPF1 will limit the
variability in the ZX detection by eliminating the high
frequency components.
The ADE interrupt stays active until the ZXTO status bit is
cleared—see Energy measurement interrupts section.
The ZXOUT register (Address 0x11) can be written or read by
the user—see Energy Measurement Register List. The resolution
of the register is 160/MCLK seconds per LSB. Thus the maxi-
mum delay for an interrupt is 0.16 second (128/MCLK × 212)
when MCLK = 4.096MHz.
Figure 30 shows the mechanism of the zero-crossing timeout
detection when the line voltage stays at a fixed dc level for more
than CLKIN/160 × ZXTOUT seconds.
Figure 29 shows how the zero-crossing signal is generated.
x1, x2, x4,
x8, x16
REFERENCE
ADC 2
VP
VN
{GAIN [7:5]}
HPF
12-BIT INTERNAL
REGISTER VALUE
ZXTOUT
PGA2
V2
ZERO
CROSS
ZX
LPF1
f
–
= 63.7Hz
3dB
VOLTAGE
CHANNEL
MODE1[6]
43.24° @ 60Hz
1.0
0.73
ZXTO
FLAG
BIT
ZX
Figure 30. Zero-Crossing Timeout Detection
LPF1
V2
Period or Frequency Measurements
Figure 29. Zero-Crossing Detection on Voltage channel
The ADE75XX/ADE71XX provides the period or frequency
measurement of the line. The period or frequency measurement
is selected by clearing or setting FREQSEL bit in the MODE2
register (0x0C). The period/frequency register is an unsigned
16-bit register and is updated every period. If LPF1 is enabled, a
settling time of 1.8 seconds is associated with this filter before
the measurement is stable.
The zero-crossing signal ZX is generated from the output of
LPF1 (bypassed or not). LPF1 has a single pole at 63.7 Hz (at
MCLK = 4.096 MHz). As a result, there is a phase lag between
the analog input signal V2 and the output of LPF1. The phase
lag response of LPF1 results in a time delay of approximately
2 ms (@ 60 Hz) between the zero crossing on the analog inputs
Rev. PrE | Page 49 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
When the period measurement is selected, the measurement
has a 2.44 μs/LSB (MCLK/10) when MCLK = 4.096 MHz,
which represents 0.014ꢀ when the line frequency is 60 Hz.
When the line frequency is 60 Hz, the value of the period
register is approximately 0d6827. The length of the register
enables the measurement of line frequencies as low as 12.5 Hz.
The period register is stable at 1 LSB when the line is
established and the measurement does not change.
Sag Level Set
The contents of the sag level register (2 bytes) are compared to
the absolute value of the output from LPF1. Therefore, when
LPF1 is enabled, writing 0x2038 to the SAG level register puts
the sag detection level at full scale – see Figure 22. Writing 0x00
or 0x01 puts the sag detection level at 0. The SAG level register
is compared to the input of the ZX detection and detection is
made when the contents of the sag level register are greater.
When the frequency measurement is selected, the measurement
has a 0.0625 Hz/LSB resolution when MCLK = 4.096MHz
which represents 0.104ꢀ when the line frequency is 60Hz.
When the line frequency is 60Hz, the value of the frequency
register is 0d960. The frequency register is stable at 4 LSB
when the line is established and the measurement does not
change.
Peak Detection
The ADE75XX/ADE71XX can also be programmed to detect
when the absolute value of the voltage or current channel
exceeds a specified peak value. Figure 32 illustrates the behavior
of the peak detection for the voltage channel. Both Voltage and
Current Channels are monitored at the same time.
V
2
Line Voltage Sag Detection
VPKLVL[15:0]
In addition to the detection of the loss of the line voltage signal
(zero crossing), the ADE75XX/ADE71XX can also be
programmed to detect when the absolute value of the line
voltage drops below a certain peak value for a number of line
cycles. This condition is illustrated in Figure 31.
PKV RESET LOW
WHEN RSTSTATUS
REGISTER IS READ
VOLTAGE CHANNEL
FULL SCALE
PKV INTERRUPT
FLAG
SAGLVL [15:0]
READ RSTSTATUS
REGISTER
SAG RESET LOW
WHEN VOLTAGE CHANNEL
EXCEEDS SAGLVL [15:0] AND
Figure 32. ADE75XX/ADE71XX Peak Level Detection
SAG FLAG RESET
Figure 32 shows a line voltage exceeding a threshold that is set
in the voltage peak register (VPKLVL[15:0]). The voltage peak
event is recorded by setting the PKV flag in the Interrupt Status
Register 3 SFR (MIRQSTH, 0xDE). If the PKV enable bit is set
in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB), the
8052 core has a pending ADE interrupt. Similarly, the current
peak event is recorded by setting the PKI flag in Interrupt Status
Register 3 SFR (MIRQSTH, 0xDE). The ADE interrupt stays
active until the PKV or PKI status bits are cleared—see Energy
measurement interrupts section.
SAGCYC [7:0] = 0x04
3 LINE CYCLES
SAG FLAG
Figure 31. ADE75XX/ADE71XX Sag Detection
Figure 31 shows the line voltage falling below a threshold that is
set in the sag level register (SAGLVL[15:0]) for three line cycles.
The quantities 0 and 1 are not valid for the SAGCYC register,
and the contents represent one more than the desired number
of full line cycles. For example, when the sag cycle (SAGCYC[7:0])
contains 0x04, the SAG flag in the Power Management Interrupt
Flag SFR (IPSMF, 0xF8) is set at the end of the third line cycle
for which the line voltage falls below the threshold. If the SAG
enable bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) is set the 8052 core has a pending Power Supply
Monitoring interrupt. The PSM interrupt stays active until the
SAG status bit is cleared—see Power Supply Monitor Interrupt
(PSM) section.
Peak Level Set
The contents of the VPKLVL and IPKLVL registers are
respectively compared to the absolute value of the voltage and
current channels two most significant bytes. Thus, for example,
the nominal maximum code from the Current Channel ADC
with a full-scale signal is 0x28F5C2—see the Current Channel
ADC section. Therefore, writing 0x28F5 to the IPKLVL register,
for example, puts the current channel peak detection level at full
scale and sets the current peak detection to its least sensitive
value. Writing 0x00 puts the Current channel detection level at
0. The detection is done by comparing the contents of the
IPKLVL register to the incoming Current channel sample. The
PKI flag indicates that the peak level is exceeded if the PKI or
On Figure 31, the SAG flag is set as soon as the fifth line cycle
from the time when the signal on the Voltage channel first
dropped below the threshold level.
Rev. PrE | Page 50 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
PKV bits are set in Interrupt Enable Register 3 SFR
(MIRQENH, 0xDB), the 8052 core has a pending ADE
interrupt.
lead is achieved by introducing a time advance into Voltage
channel. A time advance of 4.88 μs is made by writing −4
(0x3C) to the time delay block, thus reducing the amount of
time delay by 4.88 μs, or equivalently, a phase lead of
approximately 0.1° at line frequency of 60 Hz. 0x3C represents –4
because the register is centered with 0 at 0x40.
Peak Level Record
The ADE75XX/ADE71XX records the maximum absolute value
reached by the voltage and current channels in two different
registers—IPEAK and VPEAK, respectively.VPEAK and IPEAK
are 16-bit unsigned registers. These registers are updated each
time the absolute value of the waveform sample from the
corresponding channel is above the value stored in the VPEAK
or IPEAK register. The contents of the VPEAK register
correspond to the maximum absolute value observed on the
voltage channel input. The contents of IPEAK and VPEAK
represent the maximum absolute value observed on the Current
and Voltage input respectively. Reading the RSTVPEAK and
RSTIPEAK registers clears their respective contents after the read
operation.
IPA
HPF
24
PGA1
ADC 1
I
IN
LPF2
24
VP
V
CHANNEL 2 DELAY
REDUCED BY 4.48μs
(0.1°LEAD AT 60Hz)
0Bh IN PHCAL [5.0]
1
DELAY BLOCK
1.22μs/LSB
PGA2
V
ADC 2
0.1°
V
7
1
0
1
V
I
0
0 1 0 1 1
PHCAL [7:0]
--231.93μs TO +48.83μs
I
60Hz
PHASE COMPENSATION
60Hz
The ADE75XX/ADE71XX must work with transducers, which
could have inherent phase errors. For example, a phase error of
0.1° to 0.3° is not uncommon for a current transformer (CT).
These phase errors can vary from part to part, and they must be
corrected in order to perform accurate power calculations. The
errors associated with phase mismatch are particularly
noticeable at low power factors. The ADE75XX/ADE71XX
provides a means of digitally calibrating these small phase
errors. The ADE75XX/ADE71XX allows a small time delay or
time advance to be introduced into the signal processing chain
to compensate for small phase errors. Because the
Figure 33. Phase Calibration
ADE75XX/ADE71XX RMS CALCULATION
Root mean square (rms) value of a continuous signal V(t) is
defined as
T
1
VRMS = Vrms
=
× V 2 (t)dt
(2)
∫
T
0
For time sampling signals, rms calculation involves squaring the
signal, taking the average and obtaining the square root. The
ADE75XX/ADE71XX implements this method by serially
squaring the input, averaging them and then taking the root
square of the average. The averaging part of this signal
processing is done by implementing a Low Pass filter (LPF3 in
Figure 35 and Figure 36). This LPF has a -3dB cut-off frequency
of 2Hz when MCLK = 4.096MHz.
compensation is in time, this technique should be used only for
small phase errors in the range of 0.1° to 0.5°. Correcting large
phase errors using a time shift technique can introduce
significant phase errors at higher harmonics.
The phase calibration register (PHCAL[7:0]) is a twos comple-
ment signed single-byte register that has values ranging from
0x82 (–126d) to 0x68 (104d).
V(t) = 2 ×V sin(ωt) where: V is the rms voltage.
The register is centered at 0x40, so that writing 0x40 to the
register gives 0 delay. By changing the PHCAL register, the time
delay in the Voltage channel signal path can change from –
231.93 μs to +48.83 μs (MCLK = 4.096 MHz). One LSB is
equivalent to 1.22 μs (MCLK/5) time delay or advance. A line
frequency of 60 Hz gives a phase resolution of 0.026° at the
fundamental (i.e., 360° × 1.22 μs × 60 Hz)) or 0.00732ꢀ of the
line period. Similarly, a line frequency of 50Hz gives a phase
resolution of 0.022° at the fundamental or 0.0061ꢀ of the line
period. Figure 33 illustrates how the phase compensation is
used to remove a 0.1° phase lead in Current channel due to the
external transducer. To cancel the lead (0.1°) in Current
channel, a phase lead must also be introduced into Voltage
channel. The resolution of the phase adjustment allows the
introduction of a phase lead in increment of 0.026°. The phase
V 2 (t) =V 2 −V 2 cos
2ωt
)
When this signal goes through LPF3, the cos(2ωt) term is
attenuated and only the DC term Vrms2 goes through – see
Figure 34.
V 2 (t) = V 2 −V 2 cos
(
2ωt
)
V(t)=
2 ⋅ V sin(ωωt)
LPF3
INPUT
V
V 2 (t) = V 2
Rev. PrE | Page 51 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Figure 34. ADE75XX/ADE71XX RMS Signal Processing
channel waveform sampling mode. The current channel rms
value is stored in an unsigned 24-bit register (IRMS). One LSB
of the current channel rms register is equivalent to one LSB of a
current channel waveform sample.
The rms signals can be read from the waveform register by
setting the WAVMODE register (0x0D) and setting the WFSM
bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB).
Like the current and voltage channels waveform sampling
modes, the waveform date is available at sample rates of 27.9
kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS.
The update rate of the current channel rms measurement is
MCLK/5. To minimize noise in the reading of the register, the
Irms register can also be configured to be updated only with the
zero crossing of the voltage input. This configuration is done by
setting ZXRMS bit in the MODE2 register (0x0C).
Important: When the current input is larger than 40ꢀ of Full
scale, the Irms waveform sample register does not represent the
true rms value processed. The rms value processed with this
level of input is larger than the 24 bit read by the waveform
register making the value read truncated on the high end.
With the specified full-scale analog input signal of 0.5 V, the
ADC produces an output code that is approximately
0d2,684,354—see the Current Channel ADC section. The
equivalent rms value of a full-scale ac signal is 0d1,898,124
(0x1CF68C). The current rms measurement provided in the
ADE75XX/ADE71XX is accurate to within 0.5ꢀ for signal
input between full scale and full scale/1000. The conversion
from the register value to amps must be done externally in the
microprocessor using an amps/LSB constant.
Current Channel RMS Calculation
The ADE75XX/ADE71XX simultaneously calculates the rms
values for the Current and Voltage channel in different registers.
The current channel rms calculation is done on the channel
selected by SEL_I_CH bits in the CALMODE register (0x3D).
Figure 35 shows the detail of the signal processing chain for the
rms calculation on the current channel. The current channel
rms value is processed from the samples used in the current
CURRENT CHANNEL
WAVEFORM
60Hz
DATA RANGE WITH
INTEGRATOR ON (60Hz)
0x2B7850
0x000000
0xD487B0
IRMSOS[11:0]
I
(t)
RMS
MODE1[5]
25 26 27
sgn 2
18 17 16
2 2
2
2
2
HPF
HPF
IA
IB
0x00
24
DIGITAL
INTEGRATOR*
HPF1
24
LPF3
+
IRMS[23:0]
dt
CURRENT CHANNEL
WAVEFORM
DATA RANGE WITH
INTEGRATOR OFF
0x28F5C2
0x000000
0xD70A3E
Figure 35. Current channel RMS Signal Processing
The offset calibration allows the content of the IRMS register to
be maintained at 0 when no input is present on current channel.
Current channel RMS Offset Compensation
The ADE75XX/ADE71XX incorporates a current channel rms
offset compensation register (IRMSOS). This is a 12-bit signed
register that can be used to remove offset in the current channel
rms calculation. An offset could exist in the rms calculation due
to input noises that are integrated in the dc component of V2(t).
One LSB of the current channel rms offset is equivalent to
16,384 LSB of the square of the current channel rms register.
Assuming that the maximum value from the current channel
rms calculation is 0d1,898,124 with full-scale ac inputs, then 1
Rev. PrE | Page 52 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
LSB of the current channel rms offset represents 0.23ꢀ of
measurement error at –60 dB down of full scale.
measurement provided in the ADE75XX/ADE71XX is accurate
to within 0.5ꢀ for signal input between full scale and full
scale/20. The conversion from the register value to volts must be
done externally in the microprocessor using a volts/LSB
constant.
2
IRMS =
(4)
IRMS0 + IRMSOS ×32768
where IRMS0 is the rms measurement without offset correction.
Voltage channel RMS Offset Compensation
Voltage channel RMS Calculation
The ADE75XX/ADE71XX incorporates a voltage channel rms
offset compensation register (VRMSOS). This is a 12-bit signed
register that can be used to remove offset in the voltage channel
rms calculation. An offset could exist in the rms calculation due
to input noises and dc offset in the input samples. The offset
calibration allows the contents of the VRMS register to be
maintained at 0 when no voltage is applied. One LSB of the
voltage channel rms offset is equivalent to 64 LSB of the rms
register. Assuming that the maximum value from the voltage
channel rms calculation is 0d1,898,124 with full-scale ac inputs,
then one LSB of the voltage channel rms offset represents 3.37ꢀ
of measurement
Figure 36 shows the details of the signal processing chain for
the rms calculation on Voltage channel. The Voltage channel
rms value is processed from the samples used in the Voltage
channel waveform sampling mode. Voltage channel rms value is
stored in the unsigned 24-bit VRMS register.
The update rate of the Voltage channel rms measurement is
MCLK/5. To minimize noise in the reading of the register, the
Vrms register can also be configured to be updated only with
the zero crossing of the voltage input. This configuration is
done by setting ZXRMS bit in the MODE2 register (0x0C).
error at –60 dB down of full scale.
With the specified full-scale ac analog input signal of 0.5 V, the
output from the LPF1 swings between 0x28F5 and 0xD70B at
60 Hz—see the Voltage Channel ADC section. The equivalent
rms value of this full-scale ac signal is approximately
VRMS = VRMS0 + 64 x VRMSOS
(6)
where VRMS0 is the rms measurement without offset correction.
0d1,898,124 (0x1CF68C) in the VRMS register. The voltage rms
VOLTAGE SIGNAL (V(t))
0x28F5
VRMOS[11:0]
0x0
16 15
sgn 2
8
7
6
2
2
2
2
VRMS[23:0]
0xD70B
0x28F5C2
0x00
LPF1
LPF3
+
+
VOLTAGE CHANNEL
Figure 36. Voltage channel RMS Signal Processing
The average power over an integral number of line cycles (n) is
given by the expression in Equation 10.
ACTIVE POWER CALCULATION
Active power is defined as the rate of energy flow from source
to load. It is defined as the product of the voltage and current
waveforms. The resulting waveform is called the instantaneous
power signal and is equal to the rate of energy flow at every
instant of time. The unit of power is the watt or joules/sec.
Equation 9 gives an expression for the instantaneous power
signal in an ac system.
nT
1
P =
p(t)dt =VI
(10)
∫
nT
0
where:
T is the line cycle period.
P is referred to as the active or real power.
v(t) = 2 ×V sin(ωt)
i(t) = 2 × I sin(ωt)
(7)
(8)
Note that the active power is equal to the dc component of the
instantaneous power signal p(t) in Equation 9, i.e., VI. This is
the relationship used to calculate active power in the
where:
ADE75XX/ADE71XX. The instantaneous power signal p(t) is
generated by multiplying the current and voltage signals. The dc
component of the instantaneous power signal is then extracted
by LPF2 (low-pass filter) to obtain the active power
V is the rms voltage.
I is the rms current.
p(t) = v(t)× i(t)
information. This process is illustrated in Figure 37.
p(t) = VI −VI cos(2ωt)
(9)
Rev. PrE | Page 53 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
INSTANTANEOUS
POWER SIGNAL
p(t) = v×i-v×i×cos(2ωt)
⎛
⎞
WGAIN
212
⎧
⎫
⎬
⎭
⎜
⎟
⎟
Output WGAIN = Active Power × 1+
(11)
0x19999A
⎨
⎜
⎩
⎝
⎠
ACTIVE REAL POWER
SIGNAL = v
×
i
For example, when 0x7FF is written to the watt gain register, the
power output is scaled up by 50ꢀ. 0x7FF = 2047d, 2047/212 =
0.5. Similarly, 0x800 = –2048d (signed twos complement) and
power output is scaled by –50ꢀ. Each LSB scales the power
output by 0.0244ꢀ. The minimum output range is given when
the watt gain register contents are equal to 0x800, and the
maximum range is given by writing 0x7FF to the watt gain
register. This can be used to calibrate the active power (or
energy) calculation in the ADE75XX/ADE71XX.
VI
0xCCCCD
0x00000
CURRENT
i(t) =
2×i×sin(ωt)
VOLTAGE
v(t) =
2
×v×sin(ωt)
Active power offset calibration
02875-0-060
The ADE75XX/ADE71XX also incorporates an active power
offset register (WATTOS[15:0]). This is a signed twos
complement 16-bit register that can be used to remove offsets in
the active power calculation—see Figure 37. An offset could
exist in the power calculation due to crosstalk between channels
on the PCB or in the IC itself. The offset calibration allows the
contents of the active power register to be maintained at 0 when
no power is being consumed.
Figure 37. Active Power Calculation
Since LPF2 does not have an ideal “brick wall” frequency
response—see Figure 38, the active power signal has some
ripple due to the instantaneous power signal. This ripple is
sinusoidal and has a frequency equal to twice the line frequency.
Because the ripple is sinusoidal in nature, it is removed when
the active power signal is integrated to calculate energy—see the
Active Energy Calculation section.
The 256 LSBs (WATTOS = 0x0100) written to the active power
offset register are equivalent to 1 LSB in the waveform sample
register. Assuming the average value, output from LPF2 is
0xCCCCD (838,861d) when inputs on the voltage and current
channels are both at full scale. At −60 dB down on the current
channel (1/1000 of the current channel full-scale input), the
average word value output from LPF2 is 838.861
0
–4
–8
(838,861/1,000). One LSB in the LPF2 output has a
measurement error of 1/838.861 × 100ꢀ = 0.119ꢀ of the
average value. The active power offset register has a resolution
equal to 1/256 LSB of the waveform register, therefore the power
offset correction resolution is 0.000464ꢀ/LSB (0.119ꢀ/256) at
–60 dB.
–12
–16
–20
Active power sign detection
–24
1
3
10
30
100
The ADE75XX/ADE71XX detects a change of sign in the active
power. A sign change can be monitored on the filtered active
power signal or on a per CF pulse basis, depending on the
configuration of the CFSIGN_OPT bit in the GAIN register
(0x1B). The APSIGN flag in the Interrupt Status Register 1 SFR
(MIRQSTL, 0xDC) record when a change of sign according to
bit APSIGN in the ACCMODE register (0x0F) has occurred. If
the APSIGN bit is set in the Interrupt Enable Register 1 SFR
(MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt.
The ADE interrupt stays active until the APSIGN status bit is
cleared—see Energy measurement interrupts section.
FREQUENCY (Hz)
02875-0-061
Figure 38. Frequency Response of LPF2
Active power gain calibration
Figure 39 shows the signal processing chain for the active power
calculation in the ADE75XX/ADE71XX. As explained, the
active power is calculated by low-pass filtering the
instantaneous power signal. Note that when reading the
waveform samples from the output of LPF2, the gain of the
active energy can be adjusted by using the multiplier and watt
gain register (WGAIN[11:0]). The gain is adjusted by writing a
twos complement 12-bit word to the watt gain register. Equation
11 shows how the gain adjustment is related to the contents of
the watt gain register:
When APSIGN in the ACCMODE register (0x0F) is cleared
(default), the APSIGN flag in the Interrupt Status Register 1 SFR
(MIRQSTL, 0xDC) will be set when a transition from positive
to negative active power has occurred.
Rev. PrE | Page 54 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
When APSIGN in the ACCMODE register (0x0F) is set, the
APSIGN flag in the Interrupt Status Register 1 SFR (MIRQSTL,
0xDC) will be set when a transition from negative to positive
active power has occurred.
stays active until the APNOLOAD status bit is cleared—see
Energy measurement interrupts section.
The No-load threshold level is selectable by setting bits
APNOLOAD in the NLMODE register (0x0E). Setting these
bits to 0b00 disable the no-load detection and setting them to
0b01, 0b10 or 0b11 set the no-load detection threshold to
0.015ꢀ, 0.0075ꢀ and 0.0037ꢀ of the full-scale output frequency
of the multiplier respectively. The IEC62053-21 specification,
states that the meter must start up with a load equal to or less
than 0.4ꢀ Ib. If the nominal voltage input and the maximum
current represent 50ꢀ of the full scale ADC input and Imax =
400ꢀ of Ib, the ADE75XX/ADE71XX no-load threshold
options translate to 0.24ꢀ of Ib, 0.12ꢀ of Ib and 0.06ꢀ of Ib
respectively.
Active power no-Load detection
The ADE75XX/ADE71XX includes a no-load threshold feature
on the active energy that eliminates any creep effects in the
meter. The ADE75XX/ADE71XX accomplishes this by not
accumulating energy if the multiplier output is below the no-
load threshold. When the active power is below the no-load
threshold, the APNOLOAD flag in the Interrupt Status Register
1 SFR (MIRQSTL, 0xDC) is set. If the APNOLOAD bit is set in
the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), the
8052 core has a pending ADE interrupt. The ADE interrupt
UPPER 24 BITS ARE
FOR WAVEF0RM
SAMPLING
ACCESSIBLE THROUGH
WATTHR[23:0] REGISTER
WATTHR[23:0]
23
0
WATTOS[15:0]
-6 -7 -8
6
5
sgn
2
2
2
2
2
WDIV[7:0]
CURRENT
CHANNEL
LPF2
48
0
+
+
+
%
+
VOLTAGE
CHANNEL
WGAIN[11:0]
OUTPUTS FROM THE LPF2 ARE
ACCUMULATED (INTEGRATED) IN
THE INTERNAL ACTIVE ENERGY REGISTER
ACTIVE POWER
SIGNAL
TO
DIGITAL TO FREQUENCY
CONVERTER
5
T
CLKIN
WAVEFORM
REGISTER
VALUES
TIME (nT)
Figure 39. ADE75XX/ADE71XX Active Energy Calculation
power signal by continuously accumulating the active power
Active Energy Calculation
As stated earlier, power is defined as the rate of energy flow.
This relationship can be expressed mathematically in Equation 12.
signal in an internal non-readable 49-bit energy register. The
active energy register (WATTHR[23:0]) represents the upper 24
bits of this internal register. This discrete time accumulation or
summation is equivalent to integration in continuous time.
Equation 14 expresses the relationship.
dE
P =
(12)
dt
∞
where:
⎧
⎨
⎩
⎫
⎬
⎭
(14)
E = p(t)dt = Lim
p(nT) ×T
∑
∫
t→0
n=1
P is power.
E is energy.
where:
Conversely, energy is given as the integral of power.
n is the discrete time sample number.
T is the sample period.
E = Pdt
(13)
∫
The discrete time sample period (T) for the accumulation
register in the ADE75XX/ADE71XX is 1.22μs (5/MCLK). As
The ADE75XX/ADE71XX achieves the integration of the active
Rev. PrE | Page 55 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
WATTHR [23:0]
0x7F,FFFF
well as calculating the energy, this integration removes any
sinusoidal components that might be in the active power signal.
Figure 39 shows this discrete time integration or accumulation.
The active power signal in the waveform register is
WGAIN = 0x7FF
WGAIN = 0x000
WGAIN = 0x800
0x3F,FFFF
0x00,0000
0x40,0000
continuously added to the internal active energy register.
The Active Energy accumulation depends on the setting of the
POAM and ABSAM bits in the ACCMODE register (0x0F).
When both bits are cleared, the addition is signed and therefore
negative energy is subtracted from the active energy contents.
When both bits are set, the ADE75XX/ADE71XX is set to be in
the more restrictive mode, the Positive Only Accumulation
mode.
TIME (minutes)
13.7
3.41 6.82
10.2
0x80,0000
When POAM bit in the ACCMODE register (0x0F) is set, only
positive power contributes to the active energy accumulation —
see the Watt positive-only accumulation mode section.
Figure 40. Energy Register Rollover Time for Full-Scale Power
(Minimum and Maximum Power Gain)
Note that the energy register contents rolls over to full-scale
negative (0x800000) and continues to increase in value when
the power or energy flow is positive—see Figure 40. Conversely,
if the power is negative, the energy register underflows to full-
scale positive (0x7FFFFF) and continues to decrease in value.
When ABSAM bit in the ACCMODE register (0x0F) is set, the
absolute active power is used for the active energy accumulation
— see the Watt absolute accumulation mode section.
The output of the multiplier is divided by WDIV. If the value in
the WDIV register is equal to 0, then the internal active energy
register is divided by 1. WDIV is an 8-bit unsigned register.
After dividing by WDIV, the active energy is accumulated in a
49-bit internal energy accumulation register. The upper 24 bits
of this register are accessible through a read to the active energy
register (WATTHR[23:0]). A read to the RWATTHR register
returns the content of the WATTHR register and the upper 24
bits of the internal register are cleared. As shown in Figure 39, the
active power signal is accumulated in an internal 49-bit signed
register. The active power signal can be read from the waveform
register by setting the WAVMODE register (0x0D) and setting
the WFSM bit in the Interrupt Enable Register 3 SFR
(MIRQENH, 0xDB). Like the current and voltage channels
waveform sampling modes, the waveform date is available at
sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or
By using the interrupt enable register, the ADE75XX/ADE71XX
can be configured to issue an ADE interrupt to the 8052 core
when the active energy register is half-full (positive or negative)
or when an overflow or underflow occurs.
Integration time under steady Load
As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 1.22 μs (5/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
WGAIN register set to 0x000, the average word value from each
LPF2 is 0xCCCCD—see Figure 37. The maximum positive
value that can be stored in the internal 49-bit register is 248 or
0xFFFF,FFFF,FFFF before it overflows. The integration time
under these conditions with WDIV = 0 is calculated as follows:
0xFFFF,FFFF,FFFF
3.5 kSPS.
Time =
× 1.22 μs = 409.6 s = 6.82 min(15)
0xCCCCD
Figure 40 shows this energy accumulation for full-scale signals
(sinusoidal) on the analog inputs. The three curves displayed
illustrate the minimum period of time it takes the energy register
to roll over when the active power gain register contents are
0x7FF, 0x000, and 0x800. The watt gain register is used to carry
out power calibration in the ADE75XX/ADE71XX. As shown,
the fastest integration time occurs when the watt gain register is
set to maximum full scale, i.e., 0x7FF.
When WDIV is set to a value different from 0, the integration
time varies, as shown in Equation 16.
Time = TimeWDIV =0 ×WDIV
(16)
Active energy accumulation modes
Watt signed accumulation mode
The ADE75XX/ADE71XX active energy default accumulation
mode is a signed accumulation based on the active power
information.
Watt positive-only accumulation mode
The ADE75XX/ADE71XX is placed in positive-only
accumulation mode by setting the POAM bit in the
Rev. PrE | Page 56 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
ACCMODE register (0x0F). In positive-only accumulation
mode, the energy accumulation is done only for positive power,
ignoring any occurrence of negative power above or below the
no-load threshold, as shown in Figure 41. The CF pulse also
reflects this accumulation method when in this mode. The
default setting for this mode is off. Detection of the transitions
in the direction of power flow, and no-load threshold are active
in this mode.
ACTIVE ENERGY
NO-LOAD
THRESHOLD
ACTIVE POWER
NO-LOAD
THRESHOLD
ACTIVE ENERGY
APSIGN Flag
NO-LOAD
APNOLOAD
POS
NEG POS
APNOLOAD
THRESHOLD
INTERRUPT STATUS REGISTERS
ACTIVE POWER
Figure 42. Energy Accumulation in Absolute Accumulation Mode
NO-LOAD
THRESHOLD
Active energy Pulse output
ADE75XX/ADE71XX also provides all the circuitry to have a
pulse output that frequency is proportional to Active power –
see Active Power Calculation section. This pulse frequency
output uses the calibrated signal after WGAIN and its behavior
is consistent with the setting of the active energy accumulation
mode in the ACCMODE register (0x0F). The pulse output is
active low and should be preferably connected to an LED as
shown on Figure 53.
APSIGN Flag
POS
NEG POS
INTERRUPT STATUS REGISTERS
Figure 41. Energy Accumulation in Positive-Only Accumulation Mode
Watt absolute accumulation mode
The ADE75XX/ADE71XX is placed in absolute accumulation
mode by setting the ABSAM bit in the ACCMODE register
(0x0F). In absolute accumulation mode, the energy
accumulation is done using the absolute active power, ignoring
any occurrence of power below the no-load threshold, as shown
in Figure 42. The CF pulse also reflects this accumulation
method when in this mode. The default setting for this mode is
off. Detection of the transitions in the direction of power flow,
and no-load threshold are active in this mode.
Line cycle active energy accumulation mode
In line cycle energy accumulation mode, the energy accumula-
tion of the ADE75XX/ADE71XX can be synchronized to the
voltage channel zero crossing so that active energy can be
accumulated over an integral number of half line cycles. The
advantage of summing the active energy over an integer
number of line cycles is that the sinusoidal component in the
active energy is reduced to 0. This eliminates any ripple in the
energy calculation. Energy is calculated more accurately and in
a shorter time because the integration period can be shortened.
By using the line cycle energy accumulation mode, the energy
calibration can be greatly simplified, and the time required to
calibrate the meter can be significantly reduced. In line cycle
energy accumulation mode, the ADE75XX/ADE71XX
accumulates the active power signal in the LWATTHR register
for an integral number of line cycles, as shown in Figure 44. The
number of half line cycles is specified in the LINCYC register.
The ADE75XX/ADE71XX can accumulate active power for up
to 65,535 half line cycles. Because the active power is integrated
on an integral number of line cycles, at the end of a line cycle
energy accumulation cycle the CYCEND flag in the Interrupt
Status Register 3 SFR (MIRQSTH, 0xDE) is set. If the CYCEND
enable bit in the Interrupt Enable Register 3 SFR (MIRQENH,
Rev. PrE | Page 57 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
0xDB) is set, the 8052 core has a pending ADE interrupt. The
ADE interrupt stays active until the CYCEND status bit is
cleared—see Energy measurement interrupts section. Another
calibration cycle will start as soon as the CYCEND flag is set. If
the LWATTHR register is not read before a new CYCEND flag
is set, the LWATTHR register will be overwritten by a new
value.
From Equations 13 and 18,
⎧
⎪
⎫
⎪
nT
nT
⎪
⎪
⎪
⎪
VI
E(t) = VIdt −
cos (2πft)dt
(20)
⎨
⎪
⎪
⎬
⎪
2
∫
∫
f
⎛
⎜
⎞
0
⎟ ⎪ 0
1+
8.9
⎪
⎩
⎪
⎭
⎝
⎠
When a new half line cycles is written in LINECYC register, the
LWATTHR register is reset and a new accumulation start at the
next zero-crossing. The number of half line cycles is then
counted until LINCYC is reached . This implementation
provides a valid measurement at the first CYCEND interrupt
after writing to the LINCYC register – see Figure 43. The line
active energy accumulation uses the same signal path as the
active energy accumulation. The LSB size of these two registers
is equivalent.
where:
n is an integer.
T is the line cycle period.
Since the sinusoidal component is integrated over an integer
number of line cycles, its value is always 0. Therefore,
nT
E = VIdt + 0
(21)
(22)
∫
0
E(t) = VInT
LWATTHR REGISTER
CYCEND IRQ
LINECYC
VALUE
Figure 43. Energy Accumulation when LINECYC changed
TO
DIGITAL TO FREQUENCY
CONVERTER
WGAIN[11:0]
48
0
+
OUTPUT
FROM
LPF2
+
%
WATTOS[15:0]
WDIV[7:0]
ACCUMULATE ACTIVE
ENERGY IN INTERNAL
REGISTER AND UPDATE
THE LWATTHR REGISTER
AT THE END OF LINCYC
HALF LINE CYCLES
23
0
LPF1
LWATTHR [23:0]
FROM VOLTAGE
CHANNEL
ADC
ZERO CROSS
DETECTION
CALIBRATION
CONTROL
LINCYC [15:0]
Figure 44. Line Cycle Active Energy Accumulation
a maximum duration over 65,535 half line cycles. At 60 Hz line
frequency, it translates to a total duration of 65,535/120 Hz =
546 seconds.
Note that in this mode, the 16-bit LINCYC register can hold a
maximum value of 65,535. In other words, the line energy
accumulation mode can be used to accumulate active energy for
Rev. PrE | Page 58 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
REACTIVE POWER CALCULATION15
The frequency response of the LPF in the reactive signal path is
identical to that of the LPF2 used in the average active power
calculation. Since LPF2 does not have an ideal “brick wall”
frequency response—see Figure 38, the reactive power signal
has some ripple due to the instantaneous reactive power signal.
This ripple is sinusoidal and has a frequency equal to twice the
line frequency. Because the ripple is sinusoidal in nature, it is
removed when the reactive power signal is integrated to
calculate energy—see the Reactive Power Calculation section.
Reactive power is defined as the product of the voltage and
current waveforms when one of these signals is phase-shifted by
90°. The resulting waveform is called the instantaneous reactive
power signal. Equation 25 gives an expression for the instanta-
neous reactive power signal in an ac system when the phase of
the current channel is shifted by +90°.
v(t) = 2V sin(ωt + θ)
i(t) = 2I sin(ωt)
(23)
The reactive power signal can be read from the waveform
register by setting the WAVMODE register (0x0D) and setting
the WFSM bit in the Interrupt Enable Register 3 SFR
(MIRQENH, 0xDB). Like the current and voltage channels
waveform sampling modes, the waveform date is available at
sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or
3.5 kSPS.
π
2
⎛
⎞
⎟
′
i (t) = 2 I sin ωt +
(24)
⎜
⎝
⎠
where:
θ is the phase difference between the voltage and current
channel.
V is the rms voltage.
I is the rms current.
Reactive gain automatic compenstation
The ADE75XX/ADE71XX reactive power calculation has a
20dB/decade attenuation over frequency. In order to attenuate
this effect for the line frequency, the ADE75XX/ADE71XX has
a dynamic compensation of the line frequency to maintain a
constant gain over the fundamental line frequency between 45
and 65Hz. However, this automatic compensation can be
disabled by setting bit 7 of the NLMODE register (0x0E).
q(t) = v(t) × i’(t)
(25)
q(t) = VI sin (θ) + VI sin (2ωt + θ)
The average reactive power over an integral number of lines (n)
is given in Equation 26.
Reactive power gain calibration
nT
1
Figure 45 shows the signal processing chain for the reactive
power calculation in the ADE75XX/ADE71XX. As explained,
the reactive power is calculated by low-pass filtering the
instantaneous reactive power signal. Note that when reading the
waveform samples from the output of LPF2, the gain of the
reactive energy can be adjusted by using the multiplier and var
gain register (VARGAIN[11:0]). The gain is adjusted by writing
a twos complement 12-bit word to the var gain register.
Equation 11 shows how the gain adjustment is related to the
contents of the watt gain register:
(26)
Q =
q(t)dt =VI sin(θ)
∫
nT
0
where:
T is the line cycle period.
q is referred to as the reactive power.
Note that the reactive power is equal to the dc component of the
instantaneous reactive power signal q(t) in Equation 25. This is
the relationship used to calculate reactive power in the
ADE75XX/ADE71XX. The instantaneous reactive power signal
q(t) is generated by multiplying Voltage and Current channels.
In this case, the phase of Current channel is shifted by +90°. The
dc component of the instantaneous reactive power signal is then
extracted by a low-pass filter in order to obtain the reactive
power information – see Figure 45.
⎛
VARGAIN ⎞
⎧
⎩
⎫
⎭
(11)
Output VARGAIN = ⎜Reactive Power× 1+
⎟
⎟
⎨
⎬
212
⎜
⎝
⎠
The resolution of the VARGAIN register is the same as the
WGAIN register – see Active power gain calibration section.
VARGAIN can be used to calibrate the reactive power (or
energy) calculation in the ADE75XX/ADE71XX.
In addition, the phase shifting filter has a non-unity magnitude
response. Because the phase-shift filter has a large attenuation at
high frequency, the reactive power is primarily for the
calculation at line frequency. The effect of harmonics is largely
ignored in the reactive power calculation. Note that because of
the magnitude characteristic of the phase shifting filter, the
weight of the reactive power is slightly different from the active
power calculation – see Energy register scaling.
Reactive power offset calibration
The ADE75XX/ADE71XX also incorporates a reactive power
offset register (VAROS[15:0]). This is a signed twos
complement 16-bit register that can be used to remove offsets in
the reactive power calculation—see Figure 45. An offset could
exist in the reactive power calculation due to crosstalk between
channels on the PCB or in the IC itself. The offset calibration
allows the contents of the reactive power register to be
15 This function is not available in ADE7566 and ADE7166products
Rev. PrE | Page 59 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
maintained at 0 when no power is being consumed.
VARSIGN status bit is cleared—see Energy measurement
interrupts section.
The 256 LSBs (VAROS = 0x100) written to the reactive power
offset register are equivalent to 1 LSB in the waveform sample
register.
When VARSIGN in the ACCMODE register (0x0F) is cleared
(default), the VARSIGN flag in the Interrupt Status Register 1
SFR (MIRQSTL, 0xDC) will be set when a transition from
positive to negative reactive power has occurred.
Sign of Reactive Power Calculation
Note that the average reactive power is a signed calculation. The
phase shift filter has –90° phase shift when the integrator is
enabled, and +90° phase shift when the integrator is disabled.
Table 42 summarizes the relationship between the phase differ-
ence between the voltage and the current and the sign of the
resulting VAR calculation.
When VARSIGN in the ACCMODE register (0x0F) is set, the
VARSIGN f lag in the Interrupt Status Register 1 SFR
(MIRQSTL, 0xDC) will be set when a transition from negative
to positive reactive power has occurred.
Reactive power no-Load detection
Table 42. Sign of Reactive Power Calculation
The ADE75XX/ADE71XX includes a no-load threshold feature
on the reactive energy that eliminates any creep effects in the
meter. The ADE75XX/ADE71XX accomplishes this by not
accumulating reactive energy if the multiplier output is below
the no-load threshold. When the reactive power is below the
no-load threshold, the RNOLOAD flag in the Interrupt Status
Register 1 SFR (MIRQSTL, 0xDC) is set. If the RNOLOAD bit is
set in the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9),
the 8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the RNOLOAD status bit is cleared—see
Energy measurement interrupts section.
Angle
Integrator
Sign
Off
Off
On
On
Positive
Negative
Positive
Negative
Between 0° to 90°
Between –90° to 0°
Between 0° to 90°
Between –90° to 0°
Reactive power sign detection
The ADE75XX/ADE71XX detects a change of sign in the
reactive power. A sign change can be monitored on the filtered
reactive power signal or on a per CF pulse basis, depending on
the configuration of the CFSIGN_OPT bit in the GAIN register
(0x1B). The VARSIGN flag in the Interrupt Status Register 1
SFR (MIRQSTL, 0xDC) record when a change of sign according
to bit VARSIGN in the ACCMODE register (0x0F) has
occurred. If the VARSIGN bit is set in the Interrupt Enable
Register 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending
ADE interrupt. The ADE interrupt stays active until the
The No-load threshold level is selectable by setting bits
RNOLOAD in the NLMODE register (0x0E). Setting these bits
to 0b00 disable the no-load detection and setting them to 0b01,
0b10 or 0b11 set the no-load detection threshold to 0.015ꢀ,
0.0075ꢀ and 0.0037ꢀ of the full-scale output frequency of the
multiplier respectively.
UPPER 24 BITS ARE
FOR WAVEF0RM
SAMPLING
ACCESSIBLE THROUGH
VARHR[23:0] REGISTER
VARHR[23:0]
23
0
VAROS[15:0]
90° PHASE
SHIFTING FILTER
HPF
CURRENT
CHANNEL
6
5
-6 -7 -8
2 2 2
sgn
2
2
VARDIV[7:0]
Π
2
LPF2
48
0
+
+
+
%
+
VOLTAGE
CHANNEL
PHCAL[7:0]
VARGAIN[11:0]
OUTPUTS FROM THE LPF2 ARE
ACCUMULATED (INTEGRATED) IN
THE INTERNALREACTIVE ENERGY REGISTER
REACTIVE POWER
SIGNAL
TO
DIGITAL TO FREQUENCY
CONVERTER
5
T
CLKIN
WAVEFORM
REGISTER
VALUES
TIME (nT)
Figure 45. ADE75XX/ADE71XX Reactive Energy Calculation
Rev. PrE | Page 60 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
(sinusoidal) on the analog inputs. These curves also apply for
the reactive energy accumulation
Reactive Energy Calculation
As for active energy, the ADE75XX/ADE71XX achieves the
integration of the reactive power signal by continuously
accumulating the reactive power signal in an internal non-
readable 49-bit energy register. The reactive energy register
(VARHR[23:0]) represents the upper 24 bits of this internal
register.
Note that the energy register contents rolls over to full-scale
negative (0x800000) and continues to increase in value when
the power or energy flow is positive. Conversely, if the power is
negative, the energy register underflows to full-scale positive
(0x7FFFFF) and continues to decrease in value.
The discrete time sample period (T) for the accumulation
register in the ADE75XX/ADE71XX is 1.22μs (5/MCLK). As
well as calculating the energy, this integration removes any
sinusoidal components that might be in the active power signal.
Figure 45 shows this discrete time integration or accumulation.
The reactive power signal in the waveform register is
By using the interrupt enable register, the ADE75XX/ADE71XX
can be configured to issue an ADE interrupt to the 8052 core
when the reactive energy register is half-full (positive or
negative) or when an overflow or underflow occurs.
Integration time under steady Load
continuously added to the internal reactive energy register.
As mentioned in the active energy section, the discrete time
sample period (T) for the accumulation register is 1.22 μs
(5/CLKIN). With full-scale sinusoidal signals on the analog
inputs and the VARGAIN and VARDIV registers set to 0x000,
the integration time before the reactive energy register
overflows is calculated as follows:
The reactive Energy accumulation depends on the setting of the
SAVARM and ABSVARM bits in the ACCMODE register
(0x0F). When both bits are cleared, the addition is signed and
therefore negative energy is subtracted from the reactive energy
contents. When both bits are set, the ADE75XX/ADE71XX is
set to be in the more restrictive mode, the Absolute
Accumulation mode.
0xFFFF,FFFF,FFFF
Time =
× 1.22 μs = 409.6 s = 6.82 min(15)
0xCCCCD
When SAVARM bit in the ACCMODE register (0x0F) is set,
the reactive power is accumulated depending on the sign of the
active power. When active power is positive, the reactive power
is added as it is to the reactive energy register. When active
power is negative, the reactive power is subtracted to the
reactive energy accumulator – see VAR anti-tamper
accumulation mode.
When VARDIV is set to a value different from 0, the integration
time varies, as shown in Equation 16.
Time = Time
× VARDIV
(16)
WDIV = 0
Reactive energy accumulation modes
VAR signed accumulation mode
When ABSVARM bit in the ACCMODE register (0x0F) is set,
the absolute reactive power is used for the reactive energy
accumulation—see the VAR absolute accumulation mode
section.
The ADE75XX/ADE71XX reactive energy default accumulation
mode is a signed accumulation based on the reactive power
information.
VAR anti-tamper accumulation mode
The output of the multiplier is divided by VARDIV. If the value
in the VARDIV register is equal to 0, then the internal reactive
energy register is divided by 1. VARDIV is an 8-bit unsigned
register. After dividing by VARDIV, the reactive energy is
accumulated in a 49-bit internal energy accumulation register.
The upper 24 bits of this register are accessible through a read
to the reactive energy register (VARHR[23:0]). A read to the
RVARHR register returns the content of the VARHR register
and the upper 24 bits of the internal register are cleared. As
shown in Figure 45, the reactive power signal is accumulated in
an internal 49-bit signed register. The reactive power signal can
be read from the waveform register by setting the WAVMODE
register (0x0D) and setting the WFSM bit in the Interrupt
Enable Register 3 SFR (MIRQENH, 0xDB). Like the current and
voltage channels waveform sampling modes, the waveform date
is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or
3.5 kSPS.
The ADE75XX/ADE71XX is placed in VAR anti-tamper
accumulation mode by setting the SAVARM bit in the
ACCMODE register (0x0F). In this mode, the reactive power is
accumulated depending on the sign of the active power. When
active power is positive, the reactive power is added as it is to
the reactive energy register. When active power is negative, the
reactive power is subtracted to the reactive energy accumulator
– see Figure 46. The CF pulse also reflects this accumulation
method when in this mode. The default setting for this mode is
off. Transitions in the direction of power flow, and no-load
threshold are active in this mode.
Figure 40 shows this energy accumulation for full-scale signals
Rev. PrE | Page 61 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Figure 47. Reactive Energy Accumulation in Absolute Accumulation Mode
Reactive energy Pulse output
ADE75XX/ADE71XX also provides all the circuitry to have a
pulse output those frequency is proportional to reactive power
– see Energy-to-Frequency Conversion section. This pulse
frequency output uses the calibrated signal after VARGAIN and
its behavior is consistent with the setting of the reactive energy
accumulation mode in the ACCMODE register (0x0F). The
pulse output is active low and should be preferably connected to
an LED as shown on Figure 53.
REACTIVE ENERGY
NO-LOAD
THRESHOLD
REACTIVE POWER
NO-LOAD
THRESHOLD
Line cycle reactive energy accumulation mode
In line cycle energy accumulation mode, the energy accumula-
tion of the ADE75XX/ADE71XX can be synchronized to the
voltage channel zero crossing so that reactive energy can be
accumulated over an integral number of half line cycles. The
advantage of this mode is similar to the ones explained in the
Active energy Line cycle accumulation mode – see Line cycle
active energy accumulation mode section. In line cycle energy
accumulation mode, the ADE75XX/ADE71XX accumulates the
reactive power signal in the LVARHR register for an integral
number of line cycles, as shown in Figure 48. The number of
half line cycles is specified in the LINCYC register. The
NO-LOAD
THRESHOLD
ACTIVE POWER
NO-LOAD
THRESHOLD
APSIGN Flag
ADE75XX/ADE71XX can accumulate active power for up to
65,535 half line cycles. Because the reactive power is integrated
on an integral number of line cycles, at the end of a line cycle
energy accumulation cycle the CYCEND flag in the Interrupt
Status Register 3 SFR (MIRQSTH, 0xDE). If the CYCEND
enable bit in the Interrupt Enable Register 3 SFR (MIRQENH,
0xDB) is set, the 8052 core has a pending ADE interrupt. The
ADE interrupt stays active until the CYCEND status bit is
cleared—see Energy measurement interrupts section. Another
calibration cycle will start as soon as the CYCEND flag is set. If
the LVARHR register is not read before a new CYCEND flag is
set, the LVARHR register will be overwritten by a new value.
POS
NEG POS
INTERRUPT STATUS REGISTERS
Figure 46. Reactive Energy Accumulation in Anti-tamper Accumulation Mode
VAR absolute accumulation mode
The ADE75XX/ADE71XX is placed in absolute accumulation
mode by setting the ABSVARM bit in the ACCMODE register
(0x0F). In absolute accumulation mode, the reactive energy
accumulation is done using the absolute reactive power,
ignoring any occurrence of power below the no-load threshold,
as shown in Figure 42 for the active energy. The CF pulse also
reflects this accumulation method when in this mode. The
default setting for this mode is off. Transitions in the direction
of power flow, and no-load threshold are active in this mode.
As for LWATTHR, when a new half line cycles is written in
LINCYC register, the LVARHR register is reset and a new
accumulation start at the next zero-crossing. The number of
half line cycles is then counted until LINCY is reached. This
implementation provides a valid measurement at the first
CYCEND interrupt after writing to the LINCYC register. The
line reactive energy accumulation uses the same signal path as
the reactive energy accumulation. The LSB size of these two
registers is equivalent.
REACTIVE ENERGY
NO-LOAD
THRESHOLD
REACTIVE POWER
NO-LOAD
THRESHOLD
Rev. PrE | Page 62 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
TO
DIGITAL TO FREQUENCY
CONVERTER
VARGAIN[11:0]
48
0
+
OUTPUT
FROM
LPF2
+
%
VAROS[15:0]
LPF1
VARDIV[7:0]
ACCUMULATE REACTIVE
23
0
ENERGY IN INTERNAL
REGISTER AND UPDATE
THE LVARHR REGISTER
AT THE END OF LINCYC
HALF LINE CYCLES
LVARHR [23:0]
FROM VOLTAGE
CHANNEL
ADC
ZERO CROSS
DETECTION
CALIBRATION
CONTROL
LINCYC [15:0]
Figure 48 Line Cycle . Reactive Energy Accumulation Mode
(MIRQENH, 0xDB). Like the current and voltage channels
waveform sampling modes, the waveform date is available at
sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS.
APPARENT POWER CALCULATION
The apparent power is defined as the maximum power that can
be delivered to a load. Vrms and Irms are the effective voltage and
current delivered to the load; the apparent power (AP) is defined
as Vrms × Irms. Equation 28 gives an expression of the
The gain of the apparent energy can be adjusted by using the
multiplier and VAGAIN register (VAGAIN[11:0]). The gain is
adjusted by writing a twos complement, 12-bit word to the
VAGAIN register. Equation 29 shows how the gain adjustment
is related to the contents of the VAGAIN register.
instantaneous power signal in an ac system with a phase shift.
v(t) = 2 Vrms sin(ωt)
i(t) = 2 Irms sin(ωt + θ)
(27)
⎛
⎞
VAGAIN
⎧
⎫
⎬
⎭
⎜
⎟
⎟
OutputVAGAIN = Apparent Power × 1+
(29)
⎨
⎜
212
⎩
⎝
⎠
p(t) = v(t)×i(t)
For example, when 0x7FF is written to the VAGAIN register, the
power output is scaled up by 50ꢀ. 0x7FF = 2047d, 2047/212 =
0.5. Similarly, 0x800 = –2047d (signed twos complement) and
power output is scaled by –50ꢀ. Each LSB represents 0.0244ꢀ
of the power output. The apparent power is calculated with the
current and voltage rms values obtained in the rms blocks of
the ADE75XX/ADE71XX.
p(t) = Vrms Irms cos(θ) −VrmsIrms cos(2ωt + θ)
The apparent power is defined as Vrms × Irms. This expression is
independent from the phase angle between the current and the
voltage.
(28)
Figure 49 illustrates the signal processing in each phase for the
calculation of the apparent power in the ADE75XX/ADE71XX.
Apparent Power Offset Calibration
APPARENT POWER
I
rms
Each rms measurement includes an offset compensation
register to calibrate and eliminate the dc component in the rms
value—see Current Channel RMS Calculation and Voltage
channel RMS Calculation sections. The voltage and current
channels rms values are then multiplied together in the
apparent power signal processing. Since no additional offsets
are created in the multiplication of the rms values, there is no
specific offset compensation in the apparent power signal
processing. The offset compensation of the apparent power
measurement is done by calibrating each individual rms
measurement.
SIGNAL(P)
CURRENT RMS SIGNAL – i(t)
MULTIPLIER
0x1A36E2
0x1CF68C
0x00
V
VAGAIN
rms
VOLTAGE RMS SIGNAL – v(t)
0x1CF68C
TO
DIGITAL TO FREQUENCY
CONVERTER
0x00
Figure 49. Apparent Power Signal Processing
The apparent power signal can be read from the waveform
register by setting the WAVMODE register (0x0D) and setting
the WFSM bit in the Interrupt Enable Register 3 SFR
Apparent Energy Calculation
The apparent energy is given as the integral of the apparent
power.
Rev. PrE | Page 63 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Note that the apparent energy register is unsigned. By setting the
VAEHF and VAEOF bits in the Interrupt Enable Register 2 SFR
(MIRQENM, 0xDA), the ADE75XX/ADE71XX can be con-
figured to issue an ADE interrupt to the 8052 core when the
apparent energy register is half full or when an overflow occurs.
The half full interrupt for the unsigned apparent energy register
is based on 24 bits as opposed to 23 bits for the signed active
energy register.
Apparent Energy = Apparent Power(t) dt
(30)
∫
The ADE75XX/ADE71XX achieves the integration of the
apparent power signal by continuously accumulating the
apparent power signal in an internal 48-bit register. The
apparent energy register (VAHR[23:0]) represents the upper 24
bits of this internal register. This discrete time accumulation or
summation is equivalent to integration in continuous time.
Equation 31 expresses the relationship
Integration Times under Steady Load
As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 1.22 μs (5/MCLK).
With full-scale sinusoidal signals on the analog inputs and the
VAGAIN register set to 0x000, the average word value from
apparent power stage is 0x1A36E2—see the section. The
maximum value that can be stored in the apparent energy
register before it overflows is 224 or 0xFF,FFFF. The average
word value is added to the internal register, which can store 248
or 0xFFFF,FFFF,FFFF before it overflows. Therefore, the
integration time under these conditions with VADIV = 0 is
calculated as follows:
∞
⎧
⎪
⎫
⎪
(31)
Apparent Energy = Lim
Apparent Power(nT )×T
⎨
⎬
∑
T →0
⎪
⎩
⎪
⎭
n=0
where:
n is the discrete time sample number.
T is the sample period.
The discrete time sample period (T) for the accumulation
register in the ADE75XX/ADE71XX is 1.22 μs (5/MCLK).
Figure 50 shows this discrete time integration or accumulation.
The apparent power signal is continuously added to the internal
register. This addition is a signed addition even if the apparent
energy remains theoretically always positive.
0xFFFF,FFFF,FFFF
Time =
× 1.22 μs = 199 s = 3.33 min (32)
0xD055
When VADIV is set to a value different from 0, the integration
time varies, as shown in Equation 33.
The 49 bits of the internal register are divided by VADIV. If the
value in the VADIV register is 0, then the internal apparent
energy register is divided by 1. VADIV is an 8-bit unsigned
register. The upper 24 bits are then written in the 24-bit
apparent energy register (VAHR[23:0]). RVAHR register (24
bits long) is provided to read the apparent energy. This register
is reset to 0 after a read operation.
Time = TimeWDIV = 0 × VADIV
(33)
Apparent energy Pulse output
ADE75XX/ADE71XX also provides all the circuitry to have a
pulse output those frequency is proportional to apparent power
– see Energy-to-Frequency Conversion section. This pulse
frequency output uses the calibrated signal after VAGAIN. This
output can also be used to output a pulse those frequency is
proportional to Irms.
VAHR[23:0]
23
0
48
0
The pulse output is active low and should be preferably
connected to an LED as shown on Figure 53.
Line Apparent Energy Accumulation
%
VADIV
The ADE75XX/ADE71XX is designed with a special apparent
energy accumulation mode, which simplifies the calibration
process.
By using the on-chip zero-crossing detection, the
ADE75XX/ADE71XX accumulates the apparent power signal
in the LVAHR register for an integral number of half cycles, as
shown in Figure 51. The line apparent energy accumulation
mode is always active.
48
0
+
APPARENT POWER
+
APPARENT POWER
SIGNAL = P
APPARENT POWER ARE
ACCUMULATED (INTEGRATED) IN
THE APPARENT ENERGY REGISTER
T
The number of half line cycles is specified in the LINCYC
register, which is an unsigned 16-bit register. The
TIME (nT)
ADE75XX/ADE71XX can accumulate apparent power for up to
65535 combined half cycles. Because the apparent power is
integrated on the same integral number of line cycles as the line
Figure 50. ADE75XX/ADE71XX Apparent Energy Calculation
Rev. PrE | Page 64 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
active and reactive energy register, these values can be
compared easily. The energies are calculated more accurately
because of this precise timing control and provide all the
information needed for reactive power and power factor
calculation. At the end of an energy calibration cycle, the
CYCEND flag in the Interrupt Status Register 3 SFR
(MIRQSTH, 0xDE) is set. If the CYCEND enable bit in the
Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) is enabled,
the 8052 core has a pending ADE interrupt.
LINECYC register, the LVAHR register is reset and a new
accumulation start at the next zero-crossing. The number of
half line cycles is then counted until LINCY is reached. This
implementation provides a valid measurement at the first
CYCEND interrupt after writing to the LINCYC register. The
line apparent energy accumulation uses the same signal path as
the apparent energy accumulation. The LSB size of these two
registers is equivalent.
As for LWATTHR, when a new half line cycles is written in
48
0
+
+
APPARENT
%
POWER
LVAHR REGISTER IS
UPDATED EVERY LINCYC
ZERO CROSSINGS WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
VADIV[7:0]
23
0
LPF1
LVAHR [23:0]
FROM
VOLTAGE CHANNEL
ADC
ZERO-CROSSING
DETECTION
CALIBRATION
CONTROL
LINCYC [15:0]
Figure 51. ADE75XX/ADE71XX Line cycle Apparent Energy Accumulation
Apparent power no-Load detection
ADE75XX/ADE71XX also provides two energy-to-frequency
conversions for calibration purposes. After initial calibration at
manufacturing, the manufacturer or end customer often verify
the energy meter calibration. One convenient way to verify the
meter calibration is for the manufacturer to provide an output
frequency, which is proportional to the active, reactive, apparent
power or Irms under steady load conditions. This output
frequency can provide a simple, single-wire, optically isolated
interface to external calibration equipment. Figure 52 illustrates
the energy-to-frequency conversion in the
The ADE75XX/ADE71XX includes a no-load threshold feature
on the apparent energy that eliminates any creep effects in the
meter. The ADE75XX/ADE71XX accomplishes this by not
accumulating energy if the multiplier output is below the no-
load threshold. When the apparent power is below the no-load
threshold, the VANOLOAD flag in the Interrupt Status Register
1 SFR (MIRQSTL, 0xDC) is set. If the VANOLOAD bit is set in
the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), the
8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the APNOLOAD status bit is cleared—see
Energy measurement interrupts section.
ADE75XX/ADE71XX.
MODE2 Register 0x0C
The No-load threshold level is selectable by setting bits
VANOLOAD in the NLMODE register (0x0E). Setting these
bits to 0b00 disable the no-load detection and setting them to
0b01, 0b10 or 0b11 set the no-load detection threshold to
0.030ꢀ, 0.015ꢀ and 0.0075ꢀ of the full-scale output frequency
of the multiplier respectively.
CFxSEL[1:0]
VARMSCFCON
Irms
CFxNUM
VA
CFx
Pulse
output
DFC
VAR
This no-load threshold can also be applied to the Irms pulse
output when selected. The level of no-load threshold is the same
as for the Apparent energy in this case.
WATT
CFxDEN
Figure 52. ADE75XX/ADE71XX Energy-to-Frequency Conversion
ENERGY-TO-FREQUENCY CONVERSION
Two digital-to-frequency converters (DFC) are used to generate
Rev. PrE | Page 65 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
the pulsed outputs. When WDIV =0 or 1, the DFC generates a
pulse each time 1 LSB in the energy register is accumulated. An
output pulse is generated when CFxDEN/CFxNUM number of
pulses are generated at the DFC output. Under steady load
conditions, the output frequency is proportional to the active,
reactive, Apparent power or Irms depending on the CFxSEL bit
in the MODE2 register (0x0C).
scale the output frequency by 1/216 to 1 with a step of 1/216.
If the value 0 is written to any of these registers, the value 1
would be applied to the register. The ratio CFxNUM / CFxDEN
should be smaller than 1 to ensure proper operation. If the ratio
of the registers CFxNUM / CFxDEN is greater than 1, the register
values would be adjusted to a ratio of 1. For example, if the
output frequency is 1.562 kHz while the contents of CFxDEN
are 0 (0x000), then the output frequency can be set to 6.1 Hz by
writing 0xFF to the CFxDEN register.
Both pulse outputs can be enabled or disabled by clearing or
setting respectively bits DISCF1 and DISCF2 in the MODE1
register (0x0B).
ENERGY REGISTER SCALING
Both pulse outputs set a separate flag in the Interrupt Status
Register 2 SFR (MIRQSTM, 0xDD), CF1 and CF2. If CF1 and
CF2 enable bits in the Interrupt Enable Register 2 SFR
(MIRQENM, 0xDA) are set, the 8052 core has a pending ADE
interrupt. The ADE interrupt stays active until the CF1 or CF2
status bits are cleared—see Energy measurement interrupts
section.
The ADE75XX/ADE71XX provides measurements of active,
reactive, and apparent energies that use separate paths and
filtering for calculation. The difference in data paths can result
in small differences in LSB weight between active, reactive and
apparent energy registers. These measurements are internally
compensated so the scaling is nearly one to one. The
relationship between the registers is show in Table 43. In Table
44, the relationship between WATTGAIN, VARGAIN and
VAGAIN is given. These relationships can be used for
calibration and simplify the adjustment of VAR and VA gains.
As VAR and VA gains can be deducted from WGAIN, there is
no need to do reactive or apparent gai adjustment.
Pulse output configuration
The two pulse outputs circuitry have separate configuration bits
in the MODE2 register (0x0C). Setting CFxSEL bits to 0b00,
0b01 or 0b1x configure the DFC to create a pulse output
proportional to Active power, reactive power, or Apparent/Irms
respectively.
Table 43. Energy Registers scaling
Line Frequency = ꢀ0Hz
Integrator OFF
Line Frequency = 60Hz
The selection between Irms and Apparent power is done by the
VARMSCFCON bit in the MODE2 register (0x0C). With this
selection, CF2 cannot be proportional to apparent power if CF1
is proportional to Irms and vice-versa.
VAR = 0.9952 × WATT
VA = 0.9978 × WATT
Integrator ON16
VAR = 0.9949 × WAT T
VA = 1.0015 × WAT T
Pulse output characteristic
The pulse output for both DFC stays low for 90ms if the pulse
period is larger than 180ms (5.56Hz). If the pulse period is
smaller than 180ms, the duty cycle of the pulse output is 50ꢀ.
The pulse output is active low and should be preferably
connected to an LED as shown on Figure 53.
VAR = 0.9997 × WATT
VA = 0.9977 × WATT
VAR = 0.9999 × WAT T
VA = 1.0015 × WAT T
V
DD
Table 44. Gain compensation adjustments
CF
Line Frequency = ꢀ0Hz
Integrator OFF
Line Frequency = 60Hz
VARGAIN = 19.76 +
WGAIN/0.9952
VARGAIN = 21 +
WGAIN/0.9949
Figure 53. CF Pulse output
The maximum output frequency, with ac input signals at full
scale and CFxNUM = 0x00 and CFxDEN = 0x00, is
approximately 21.1 kHz.
VAGAIN = 9.03 +
WGAIN/0.9978
VAGAIN = -60.53 +
WGAIN/1.0015
Integrator ON1
The ADE75XX/ADE71XX incorporates two registers,
CFxNUM[15:0] and CFxDEN[15:0] per DFC, to set the CFx
frequency. These are unsigned 16-bit registers, which can be
used to adjust the CFx frequency to a wide range of values.
These frequency-scaling registers are 16-bit registers, which can
VARGAIN = 1.23 +
VARGAIN = 0.41 +
16 This function is not available in ADE7166 and ADE7566 products
Rev. PrE | Page 66 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Enable Register 2 SFR (MIRQENM, 0xDA), and Interrupt
Enable Register 3 SFR (MIRQENH, 0xDB) enables the energy
measurement interrupts that are allowed to interrupt the 8052
core. If an event is not enabled, it cannot create a system
interrupt.
WGAIN/0.9997
WGAIN/0.9999
WGAIN/1.0015
VAGAIN = 9.44 +
WGAIN/0.9977
VAGAIN = -60.53 +
The ADE interrupt stays active until the status bit that has
created the interrupt is cleared. A status bit of the ADE irq
status register (1, 2 or 3) is cleared when a zero is written the bit
to clear and acknowledge the event.
ENERGY MEASUREMENT INTERRUPTS
The Energy Measurement part of the ADE75XX/ADE71XX has
its own interrupt vector for the 8052 core – Vector address
0x004B – see Interrupt Vectors section. The bits set in the
Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), Interrupt
Rev. PrE | Page 67 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
measurements allow low battery detection to be performed. All
ADC measurements are configured through the SFR detailed in
Table 45.
TEMPERATURE, BATTERY AND EXTERNAL
VOLTAGE MEASUREMENTS
The temperature, battery and external voltage measurements
can be configured to still be functional in PSM1 and PSM2.
This is done bit setting bit RTCEN in the RTC Configuration
SFR (TIMECON, 0xA1). Maintaining the temperature
measurement active ensures that it is not necessary to wait for
the temperature measurement to settle before using it for
compensation.
The ADE75XX/ADE71XX includes temperature measurements
as well as battery and an external voltage measurements. These
measurements enable many forms of compensation. The
temperature measurements can be used to compensate external
circuitry. The RTC can be calibrated over temperature to ensure
that it doesn’t drift. External voltage measurements allow the
VDCIN voltage to be monitored, which is especially useful if
the VDCIN voltage tracks the bulk voltage. Battery
Table 4ꢀ. Temperature, Battery and External voltage measurement SFRs
SFR
address
(hex)
R/W
Name
Description
0xF9
0xF3
0xD8
0xFA
0xEF
0xDF
0xD7
R/W
R/W
R/W
R/W
STRBPER
DIFFPROG
ADCGO
Strobing period configuration
Temperature and supply Delta configuration
ADC start configuration
BATVTH
Battery threshold configuration
VDCIN ADC value
R/W VDCINADC
R/W
R/W
BATADC
Battery ADC value
TEMPADC
Temperature ADC value
Table 46. Peripheral ADC Strobe Period SFR (STRBPER, 0xF9)
Note: The strobing option only work when the RTCEN bit in RTC Configuration SFR (TIMECON, 0xA1) is set.
Bit
Location
7-6
Bit
Mnemonic
Reserved
Default
Value
Description
-
Reserved
5-4
VDCIN_PERIOD[1:0]
0
Period for background external voltage measurements
VDCIN_PERIOD[1:0]
0
0
1
1
0
1
0
1
No VDCIN measurement
8 minutes
2 minutes
1 minute
3-2
1-0
BATT_PERIOD[1:0]
TEMP_PERIOD[1:0]
0
0
Period for background battery level measurements
BATT_PERIOD[1:0]
0
0
1
1
0
1
0
1
No Battery measurement
16 minutes
4 minutes
1 minute
Period for background temperature measurements
TEMP_PERIOD[1:0]
0
0
0
1
No Temperature measurements
8 minutes
Rev. PrE | Page 68 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
1
1
0
1
2 minutes
1 minute
Table 47. Temperature and Voltage ADC Delta SFR (DIFFPROG, 0xF3)
Bit
Location
7-6
Bit
Default
Value
Description
Mnemonic
Reserved
TEMP_DIFF[2:0]
0
0
Reserved
5-3
Difference threshold between last temperature measurement interrupting 8052
and new temperature measurement that should interrupt 8052
TEMP_DIFF[2:0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No Interrupt
1 LSB (≈ 0.8°C)
2 LSB (≈ 1.6°C)
3 LSB (≈ 2.4°C)
4 LSB (≈ 3.2°C)
5 LSB (≈ 4.0°C)
6 LSB (≈ 4.8°C)
Every Temperature measurement
2-0
VDCIN_DIFF[2:0]
0
Difference threshold between last external voltage measurement interrupting
8052 and new external voltage measurement that should interrupt 8052
VDCIN_DIFF[2:0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No Interrupt
1 LSB (≈ 120 mV)
2 LSB (≈ 240 mV)
3 LSB (≈ 360 mV)
4 LSB (≈ 480 mV)
5 LSB (≈ 600 mV)
6 LSB (≈ 720 mV)
Every VDCIN measurement
48. Start ADC Measurement SFR (ADCGO, 0xD8)
Bit
Location
Bit
Addr.
Bit
Name
PLLACK
Default Description
Value
7
0xDF
0
0
0
0
0
Set this bit to clear the PLL fault bit, PLL_FLT in the PERIPH register. A PLL
fault is generated if a reset was caused because the PLL lost lock.
6-3
2
0xDE – Reserved
0xDB
Reserved
0xDA
0xD9
0xD8
VADC
TADC
BTADC
Set this bit to initiate an externalvoltage measurement. This bit will be
cleared when the measurement request is received by the ADC.
1
Set this bit to initiate a temperature measurement. This bit will be cleared
when the measurement request is received by the ADC.
0
Set this bit to initiate a battery measurement. This bit will be cleared when
the measurement request is received by the ADC.
Table 49. Battery detection threshold SFR (BATVTH, 0xFA)
Bit
Bit
Default
Value
Description
Rev. PrE | Page 69 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Location
Mnemonic
7-0
BATVTH
0
The battery ADC value is compared to this register, the battery threshold
register. If BATADC is lower than the threshold, an interrupt is generated.
Table ꢀ0. VDCIN ADC value SFR (VDCINADC, 0xEF)
Bit
Location
7-0
Bit
Mnemonic
VDCINADC
Default
Value
Description
0
The external voltage ADC value in this register is updated when a
VDCINADC interrupt occurs.
Table ꢀ1. Battery ADC value SFR (BATADC, 0xDF)
Bit
Location
7-0
Bit
Mnemonic
BATADC
Default
Value
Description
0
The battery ADC value in this register is updated when a BATADC interrupt
occurs.
Table ꢀ2. Temperature ADC value SFR (TEMPADC, 0xD7)
Bit
Location
7-0
Bit
Mnemonic
TEMPADC
Default
Value
Description
0
The temperature ADC value in this register is updated when a TEMPADC
interrupt occurs.
ADC Delta SFR (DIFFPROG, 0xF3), a TEMPADC interrupt is
generated. This allows temperature measurements to take place
completely in the background, only requiring MCU activity if
TEMPERATURE MEASUREMENT
To provide a digital temperature measurement, the
ADE75XX/ADE71XX includes a dedicated ADC. An 8-bit
Temperature ADC value SFR (TEMPADC, 0xD7) holds the
results of the temperature conversion. The resolution of the
temperature measurement is TBD˚C/LSB. There are two ways to
initiate a temperature conversion:
the temperature has changed more than a configurable delta.
To set up background temperature measurements:
1. Initiate a single temperature measurement by setting
the TADC bit in the Start ADC Measurement SFR
(ADCGO, 0xD8).
- Single Temperature Measurement
- Background Temperature Measurements
2. Upon completion of this measurement, configure the
TEMP_DIFF[2:0] bits to establish the change in
temperature that will trigger an interrupt.
Single Temperature Measurement
Set the TADC bit in the Start ADC Measurement SFR
(ADCGO, 0xD8) to get a temperature measurement. An
interrupt will be generated when the conversion is done and the
temperature measurement is available in the Temperature ADC
value SFR (TEMPADC, 0xD7).
3. Set up the interval for background temperature
measurements by configuring the
TEMP_PERIOD[1:0] bits.
Background Temperature Measurements
Temperature ADC in PSM1 and PSM2
Background temperature measurements are disabled by default.
To configure the background temperature measurement mode,
set a temperature measurement interval in the Peripheral ADC
Strobe Period SFR (STRBPER, 0xF9). Then temperature
measurements will be performed periodically in the
background – see Table 46. When a temperature conversion
completes, the new temperature ADC value is compared to the
last temperature ADC value that created an interrupt. If the
absolute difference between the two values is greater than the
setting in the TEMP_DIFF bits in the Temperature and Voltage
Depending on the operating mode of the
ADE75XX/ADE71XX, a temperature conversion is initiated
only by certain actions:
PSM0: In this operating mode, the 8052 is active. Temperature
measurements are available in the background measurement
mode and by initiating a single measurement.
PSM1: In this operating mode, the 8052 is active and the part is
powered from battery. Single temperature measurements can be
Rev. PrE | Page 70 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
initiated by setting the TADC bit in the Start ADC
Measurement SFR (ADCGO, 0xD8). Background temperature
measurements are not available.
SFR (IPSMF, 0xF8), used for power supply monitoring. This low
battery flag can be enabled to generate the PSM interrupt by
setting the EBATT bit in the Power Management Interrupt
Enable SFR (IPSME, 0xEC). This method allows battery
measurements to take place completely in the background, only
requiring MCU activity if the battery drops below a user
specified threshold.
PSM2: In this operating mode, the 8052 is not active.
Temperature conversions are available through the background
measurement mode only.
The Temperature ADC value SFR (TEMPADC, 0xD7) is
updated with a new value only when a temperature ADC
interrupt occurs.
To set up background battery measurements:
1. Configure the Battery detection threshold SFR
(BATVTH, 0xFA) to establish a low battery threshold.
If the BATADC measurement is below this threshold,
the BATTFLAG in the Power Management Interrupt
Flag SFR (IPSMF, 0xF8) will be set.
Temperature ADC interrupt
The temperature ADC can generate an ADC interrupt when at
least one of the following conditions occurs:
- The difference between the new temperature ADC value and
the last temperature ADC value generating an ADC interrupt is
larger than the value set in the TEMP_DIFF bits.
2. Set up the interval for background battery
measurements by configuring the
BATT_PERIOD[1:0] bits.
- The Temperature ADC conversion, initiated by setting TADC
in the Start ADC Measurement SFR (ADCGO, 0xD8), is
finished.
Battery ADC in PSM1 and PSM2
Depending on the operating mode, a battery conversion is
initiated only by certain actions:
When the ADC interrupt occurs, a new value is available in the
Temperature ADC value SFR (TEMPADC, 0xD7). Note that
there is no flag associated with this interrupt.
PSM0: In this operating mode, the 8052 is active. Battery
measurements are available in the background measurement
mode and by initiating a single measurement.
BATTERY MEASUREMENT
PSM1: In this operating mode, the 8052 is active and the part is
powered from battery. Single battery measurements can be
initiated by setting the BTADC bit in the Start ADC
Measurement SFR (ADCGO, 0xD8). Background battery
measurements are not available.
To provide a digital battery measurement, the
ADE75XX/ADE71XX includes a dedicated ADC. The battery
measurement is available in an 8-bit SFR (Battery ADC value
SFR (BATADC, 0xDF). The battery measurement has a
resolution of 15 mV/LSB. A battery conversion can be initiated
by two methods:
PSM2: In this operating mode, the 8052 is not active. Battery
conversions are available through the background measurement
mode only.
- Single Battery Measurement
Battery ADC interrupt
- Background Battery Measurements
The battery ADC can generate an ADC interrupt when at least
one of the following conditions occurs:
Single Battery Measurement
Set the BTADC bit in the Start ADC Measurement SFR
(ADCGO, 0xD8) to get a battery measurement. An interrupt
will be generated when the conversion is done and the battery
measurement is available in the Battery ADC value SFR
(BATADC, 0xDF).
- The new battery ADC value is smaller than the value set in the
Battery detection threshold SFR (BATVTH, 0xFA), indicating a
battery voltage loss.
- A single battery measurement, initiated by setting the
BATT_ADC_GO bit, is finished.
Background Battery measurements
To configure background measurements for the battery,
establish a measurement interval in the Peripheral ADC Strobe
Period SFR (STRBPER, 0xF9). Then battery measurements will
be performed periodically in the background – see Table 46.
When a battery conversion completes, the battery ADC value is
compared to the low battery threshold, established in the
Battery detection threshold SFR (BATVTH, 0xFA). If it is below
this threshold, a low battery flag is set. This low battery flag is
the BATTFLAG bit in the Power Management Interrupt Flag
When the battery flag is set in the Power Management Interrupt
Flag SFR (IPSMF, 0xF8), a new ADC value is available in the
Battery ADC value SFR (BATADC, 0xDF). This battery flag can
be enabled as a source of the PSM interrupt to generate a PSM
interrupt every time the battery drops below a set voltage
threshold or after a single conversion initiated by setting the
BATT_ADC_GO bit is ready.
The Battery ADC value SFR (BATADC, 0xDF) is updated with a
Rev. PrE | Page 71 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
new value only when the Battery flag is set in the Power
Management Interrupt Flag SFR (IPSMF, 0xF8).
SFR (ADCGO, 0xD8).
2. Upon completion of this measurement, configure the
VDCIN_DIFF[2:0] bits to establish the change in
voltage that will set the FVADC in the Power
EXTERNAL VOLTAGE MEASUREMENT
The ADE75XX/ADE71XX includes a dedicated ADC to provide
a digital measurement of an external voltage, on the VDCIN pin.
An 8-bit SFR (Table 50. VDCIN ADC value SFR (VDCINADC,
0xEF)) holds the results of the conversion. The resolution of the
external voltage measurement is TBD V/LSB. There are two
ways to initiate an external voltage conversion:
Management Interrupt Flag SFR (IPSMF, 0xF8).
3. Set up the interval for background external voltage
measurements by configuring the
VDCIN_PERIOD[1:0] bits.
External voltage ADC in PSM1 and PSM2
- Single External Voltage Measurement
Depending on the operating mode of the
ADE75XX/ADE71XX, an external voltage conversion is
initiated only by certain actions:
- Background ExternalVoltage Measurements
Single External voltage Measurement
PSM0: In this operating mode, the 8052 is active. External
voltage measurements are available in the background
measurement mode and by initiating a single measurement.
Set the VADC bit in the Start ADC Measurement SFR
(ADCGO, 0xD8) to get an external voltage measurement. An
interrupt will be generated when the conversion is done and the
external voltage measurement is available in the Table 50.
VDCIN ADC value SFR (VDCINADC, 0xEF).
PSM1: In this operating mode, the 8052 is active and the part is
powered from battery. Single external voltage measurements
can be initiated by setting the VADC bit in the Start ADC
Measurement SFR (ADCGO, 0xD8). Background external
voltage measurements are not available.
Background External Voltage Measurements
Background external voltage measurements are disabled by
default. To configure the background external voltage
measurement mode, set an external voltage measurement
interval in the Peripheral ADC Strobe Period SFR (STRBPER,
0xF9). Then external voltage measurements will be performed
periodically in the background – see Table 46. When an external
voltage conversion completes, the new external voltage ADC
value is compared to the last external voltage ADC value that
created an interrupt. If the absolute difference between the two
values is greater than the setting in the VDCIN_DIFF bits in the
Temperature and Voltage ADC Delta SFR (DIFFPROG, 0xF3), a
VDCIN ADC flag is set. This VDCIN ADC flag is the FVADC
in the Power Management Interrupt Flag SFR (IPSMF, 0xF8),
used for power supply monitoring. This VDCIN ADC flag can
be enabled to generate a PSM interrupt by setting the EVADC
bit in the Power Management Interrupt Enable SFR (IPSME,
0xEC). This method allows external voltage measurements to
take place completely in the background, only requiring MCU
activity if the external voltage has changed more than a
configurable delta.
PSM2: In this operating mode, the 8052 is not active. External
voltage conversions are available through the background
measurement mode only.
The external voltage ADC, VDCIN ADC value SFR
(VDCINADC, 0xEF), is updated with a new value only when an
external voltage ADC interrupt occurs.
External voltage ADC interrupt
The external voltage ADC can generate an ADC interrupt when
at least one of the following conditions occurs:
- The difference between the new external voltage ADC value
and the last external voltage ADC value generating an ADC
interrupt is larger than the value set in the VDCIN_DIFF bits.
- The External voltage ADC conversion, initiated by setting
TEMP_ADC_GO, is finished.
When the ADC interrupt occurs, a new value is available in the
VDCIN ADC value SFR (VDCINADC, 0xEF). Note that there
is no flag associated with this interrupt.
To set up background external voltage measurements:
1. Initiate a single external voltage measurement by
setting the VADC bit in the Start ADC Measurement
Rev. PrE | Page 72 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
in the SFR area. The SFR registers include control,
configuration, and data registers that provide an interface
between the CPU and all on-chip peripherals.
8052 MCU CORE ARCHITECTURE
The ADE75XX/ADE71XX has an 8052 MCU core and uses the
8051 instruction set. Some of the standard 8052 peripherals,
such as the UART, have been enhanced. This section describes
the standard 8052 core and enhancements that have been made
to it in the ADE75XX/ADE71XX.
16-kBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
ENERGY MEASUREMENT
POWER MANAGEMENT
RTC
FLASH/EE PROGRAM/DATA
MEMORY
256 BYTES
GENERAL
PURPOSE
RAM
The special function register (SFR) space is mapped into the
upper 128 bytes of internal data memory space and is accessed
by direct addressing only. It provides an interface between the
CPU and all on-chip peripherals. A block diagram showing the
programming model of the ADE75XX/ADE71XX via the SFR
area is shown in Figure 54.
LCD DRIVER
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
8051
COMPATIBLE
CORE
STACK
TEMPERATURE ADC
REGISTER
BANKS
PC
IR
BATTERY ADC
OTHER ON-CHIP
PERIPHERALS:
SERIAL I/O
WDT
256 BYTES XRAM
TIMERS
All registers except the program counter (PC), instruction
register (IR) and the four general-purpose register banks reside
Figure 54: ADE75XX/ADE71XX Block Diagram
MCU REGISTERS
The registers used by the MCU are summarized hereafter.
Table ꢀ3. 80ꢀ1 SFRs
SFR
A
Address Bit Addressable Description
0xE0
0xF0
0xD0
Yes
Yes
Yes
No
No
No
No
No
Accumulator
B
Auxiliary Math register
Program status word - see Table 54
PSW
PCON 0x87
Power Control register – see Table 55
Data pointer LSByte – see Table 56
Data pointer MSbyte – see Table 57
Stack pointer LSB byte – see Table 58
Configuration register – see Table 59
DPL
DPH
SP
0x82
0x83
0x81
0xAF
CFG
Table ꢀ4. Program Status Word SFR (PSW, 0xD0)
Bit Location Bit Addr. Bit Name Description
7
0xD7
0xD6
0xD5
0xD4,
0xD3
CY
Carry Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
6
AC
Auxiliary Carry Flag. Modified by ADD, and ADDC instructions.
General-Purpose Flag availble to the user
Register Bank Select Bits.
5
F0
4-3
RS1, RS0
RS1 RS0 Selected Bank
0
0
1
1
0
1
0
1
0
1
2
3
2
1
0
0xD2
0xD1
0xD0
OV
F1
P
Overflow Flag. Modified by ADD, ADDC, SUBB, MUL and DIV instructions.
General-Purpose Flag availble to the user.
Parity Bit. The number of bits set in the Accumulator added to the value of the parity bit
will always be an even number.
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ADE75xx/ADE71xx
Preliminary Technical Data
Table ꢀꢀ. Program Control SFR (PCON, 0x87)
Bit Location Default Description
7
0
0
Double baud rate control
6-0
Reserved, should be left cleared
Table ꢀ6. Data Pointer Low SFR (DPL, 0x82)
Bits Default Description
7-0
0
Contain the low byte of the data pointer
Table ꢀ7. Data Pointer High SFR (DPH, 0x83)
Bits Default Description
7-0
0
Contain the high byte of the data pointer
Table ꢀ8. Stack Pointer SFR (SP, 0x81)
Bits Default Description
7-0
7
Contain the 8 LSB of the pointer for the stack
Table ꢀ9. Configuration SFR (CFG, 0xAF)
Bit
Bit Mnemonic Description
Location
7
6
Reserved.. This bit should be left set for proper operation.
EXTEN
Enhanced UART enable bit
0
1
Standard 8052 UART without enhanced error checking features
Enhanced UART with enhanced error checking—see the UART additional features
section.
5
4
SCPS
Synchronous communication selection bit
0
1
I2C port is selected for control of the shared I2C/SPI pins and SFRs
SPI port is selected for control of the shared I2C/SPI pins and SFRs
MOD38EN
38kHz modulation enable bit
0
1
38kHz modulation is disabled.
38kHz modulation is enabled on the pins selected by the MOD38[7:0] bits in the
EP_CFG SFR.
3-2
1-0
Reserved
XREN[1:0]
XREN[1] OR
XREN[0] =1
Enable MOVX instruction to use 256 bytes of Extended RAM.
Disable MOVX instruction
XREN[1] AND
XREN[0] =0
opcode of the instruction being executed. The opcode is the
binary code that results from assembling an instruction. This
register is not directly accessible to the user.
BASIC 8052 REGISTERS
Program Counter (PC): The Program Counter holds the two
byte address of the next instruction to be fetched. The PC is
initialized with 0x00 at Reset and is incremented after each
instruction is performed. Note that the amount that is added to
the PC depends on the number of bytes in the instruction, so
the increment can range from one to three bytes. The program
counter is not directly accessible to the user but can be directly
modified by CALL and JMP instructions that change which
part of the program is active.
Register Banks: There are four banks containing 8 byte-wide
registers each, for a total of 32 bytes of registers. These registers
are convenient for temporary storage of mathematical operands.
An instruction involving the accumulator and a register can be
executed in 1 clock cycle as opposed to 2 clock cycles to
perform an instruction involving the accumulator and a literal
or a byte of general purpose RAM. The register banks are
located in the first 32 bytes of RAM.
Instruction Register (IR): The Instruction Register holds the
Rev. PrE | Page 74 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
The active register bank is selected by the RS0 and RS1 bits in
the Program Status Word SFR (PSW, 0xD0).
Stack Pointer (SP): The Stack Pointer keeps track of the current
address of the top of the stack. To push a byte of data onto the
stack, the stack pointer is incremented and the data is moved to
the new top of the stack. To pop a byte of data off of the stack,
the top byte of data is moved into the awaiting address and the
stack pointer is decremented. The stack is a last in first out
(LIFO) method of data storage because the most recent
addition to the stack is the first to come off it.
Accumulator: The accumulator is a working register, storing
the results of many arithmetic or logical operations. The
accumulator is used in more than half of the 8052 instructions
where it is usually referred to as A. The status register (PSW)
constantly monitors the number of bits that are set in the
accumulator to determine if it has even or odd parity. The
accumulator is stored in the SFR space - see Table 53.
The stack is utilized during CALL and RET instructions to keep
track of the address to move into the PC when returning from
the function call. The stack is also manipulated when vectoring
for interrupts, to keep track of the prior state of the PC.
B Register: The B register is used by the multiply and divide
instructions, MUL AB and DIV AB to hold one of the operands.
Since it isn’t used for many instructions, it can be used as a
scratchpad register like those in the register banks. The B
register is stored in the SFR space - see Table 53.
The stack resides into the extended internal RAM and the SP
register holds the address of the stack into the externded RAM.
The advantage of this solution is that the stack is segregated to
the extended internal RAM. The use of the general purpose
RAM can be limited to data storing and the use of the extended
internal RAM limited to the stack pointer. This separation limits
the chance of corruption of the data RAM with the stack
pointer overflowing in data RAM.
Program Status Word (PSW): The PSW register reflects the
status of arithmetic and logical operations through carry,
auxiliary carry and overflow flags. The parity flag reflects the
parity of the contents of the accumulator, which can be helpful
for communication protocols. The PSW bits are described in
Table 54. The Program Status Word SFR (PSW, 0xD0) is bit
addressable.
Data can still be stored in extended RAM by using the MOVX
command.
Data Pointer (DPTR): The data pointer is made up of two 8-bit
registers: DPH (high byte), and DPL (low byte). These provide
memory addresses for internal code and data access. The DPTR
can be manipulated as a 16-bit register (DPTR = DPH, DPL), or
as two independent 8-bit registers (DPH, DPL) – see Table 56
and Table 57.
To change the default starting address for the stack, move a
value into the stack pointer, SP. For example, to enable the
extended stack pointer and initialize it at the beginning of the
XRAM space, use this code:
MOV SP,#00H
The ADE75XX/ADE71XX supports dual data pointers. See the
Dual Data Pointers section.
FFH
FFH
00H
256 BYTES OF
256 BYTES OF
ON-CHIP X-RAM
RAM
DATA+STACK
(DATA)
00H
Figure 55. Extended Stack Pointer Operation
function as event counters. Timer2 has a capture feature where
STANDARD 8052 SFRS
the value of the timer can be captured in two 8-bit registers
upon the assertion of an external input signal - see Table 96 and
Timers section.
The standard 8052 special function registers include the
Accumulator, B, PSW, DPTR and SP SFRs described in the Basic
8052 Registers section. The 8052 also defines standard timers,
serial port interface, interrupts, I/O ports and power down
modes.
Serial Port SFRs: The full-duplex serial port peripheral requires
two registers, one for setting up the baud rate and other
communication parameters, and another byte for the
Timer SFRs: The 8052 contains 3 16-bit timers, the identical
Timer0 and Timer1 as well as a Timer2. These timers can also
transmit/receive buffer. The ADE75XX/ADE71XX also provides
Rev. PrE | Page 75 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
enhanced serial port functionality with a dedicated timer for
baud rate generation with a fractional divisor and additional
error detection. See Table 121 and UART serial interface
section.
•
•
•
SPI/I2C communication
Flash Memory controller
Watchdog Timer
Interrupt SFRs: There is a two-tiered interrupt system standard
in the 8052 core. The priority level for each interrupt source is
individually selectable as high or low. The
MEMORY OVERVIEW
The ADE75XX/ADE71XX contains three memory blocks:
ADE75XX/ADE71XX enhances this interrupt system by
creating in essence a third interrupt tier for a highest priority
power supply management interrupt, PSM - See Interrupt
System section.
•
•
•
16 kbytes of on-chip Flash/EE program and data memory
256 bytes of general-purpose RAM
256 bytes of internal extended RAM (XRAM)
I/O Port SFRs: The 8052 core supports four I/O ports, P0
through P3 where Ports 0 and 2 are typically used for access to
external code and data spaces. The ADE75XX/ADE71XX,
unlike standard 8052 products, provides internal nonvolatile
Flash memory so that an external code space is unnecessary.
The on-chip LCD driver requires many pins, some of which are
dedicated for LCD functionality and others that can be
configured at LCD or general purpose I/O. Due to the limited
number of I/O pins, the ADE75XX/ADE71XX does not allow
access to external code and data spaces.
The 256 bytes of general-purpose RAM shares the upper 128
bytes of its address space with Special Function Registers. All of
the memory spaces are shown in Figure 54. The addressing
mode specifies which memory space to access.
General Purpose RAM: General purpose RAM resides in
memory locations 0x00 through 0xFF. It contains the register
banks.
7FH
GENERAL-PURPOSE
AREA
The ADE75XX/ADE71XX provides 20 pins that can be used for
general purpose I/O. These pins are mapped to Ports 0, 1 and 2
and are accessed through three bit-addressable 8052 SFRs P0,
P1 and P2. Another enhanced feature of the
ADE75XX/ADE71XX is that the weak pull-ups standard on
8052 Ports 1, 2 and 3 can be disabled to make open drain
outputs, as is standard on Port 0. The weak pull-ups can be
enabled on a pin by pin basis. See the I/O Ports section.
30H
2FH
BIT-ADDRESSABLE
(BIT ADDRESSES)
BANKS
SELECTED
VIA
20H
18H
10H
BITS IN PSW
1FH
17H
0FH
07H
11
10
01
00
FOUR BANKS OF EIGHT
REGISTERS
R0 TO R7
Power Control Register (PCON, 0x87): The 8052 core defines
two power down modes; power down and idle. The
ADE75XX/ADE71XX enhances the power control capability
of the traditional 8052 MCU with additional power
08H
00H
RESET VALUE OF
STACK POINTER
management functions. The POWCON register is used to
define power control specific functionality for the
Figure 56. Lower 128 Bytes of Internal Data Memory
ADE75XX/ADE71XX. The Program Control SFR (PCON,
0x87) is not bit addressable. See the Power Management section.
Addresses 0x80 through 0xFF of General Purpose RAM are
shared with the Special Function Registers. The mode of
addressing determines which memory space is accessed as
shown in Figure 57.
The ADE75XX/ADE71XX provides many other peripherals not
standard to the 8052 core.
FFh
•
•
•
•
•
•
ADE Energy Measurement DSP
RTC
ACCESSIBLE BY
INDIRECT ADDRESSING
ONLY
ACCESSIBLE BY
DIRECT ADDRESSING
ONLY
80h
7Fh
LCD driver
ACCESSIBLE BY
DIRECT AND INDIRECT
ADDRESSING
Battery Switchover/Power Management
Temperature ADC
Battery ADC
00h
GENERAL PURPOSE RAM
SPECIAL FUNCTION REGISTERS (SFRs)
Rev. PrE | Page 76 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Figure 57: General Purpose RAM and SFR memory address overlap
labeled as bit-addressable and the bit addresses are given in the
SFR Mapping.
Both direct and indirect addressing can be used to access
General Purpose RAM from 0x00 through 0x7F but indirect
addressing must be used to access General Purpose RAM with
addresses in the range from 0x80 through 0xFF because they
share the same address space with the Special Function
Registers (SFRs).
Extended Internal RAM (XRAM): The ADE75XX/ADE71XX
provides 256 bytes of extended on-chip RAM. No external
RAM is supported. This RAM is located in addresses 0x0000
through 0x00FF in the Extended RAM space. To select the
Extended RAM memory space, the extended indirect
addressing modes are used. The internal XRAM is enabled in
the Configuration SFR (CFG, 0xAF) by writing 01 to CFG[1:0].
The 8052 core also has the means to access individual bits of
certain addresses in the General Purpose RAM and Special
Function Memory spaces. The individual bits of General
Purpose RAM addresses 0x20 through 0x2F can be accessed
through their bit addresses 0x00 through 0x7F. The benefit of
bit addressing is that the individual bits can be accessed quickly,
without the need for bit masking, which takes more code
memory and execution time. The bit addresses for General
Purpose RAM addresses 0x20 through 0x2F can be seen in
Figure 58.
FFh
256 BYTES OF
EXTENDED INTERNAL
RAM (XRAM)
00h
Figure 59: Extended Internal RAM (XRAM) Space
Code Memory: Code and data memory are stored in the
16kbyte Flash memory space. No external code memory is
supported. To access Code memory, Code Indirect addressing is
used.
Byte Address
Bit Addresses (hexa)
7F
77
6F
67
5F
7D 7C 7B 7A 79 78
7E
0x2F
0x2E
0x2D
76 75 74 73 72 71 70
6D 6B 6A 69 68
ADDRESSING MODES
6E
66 65 64 63 62 61 60
5D 5C 5B 5A 59 58
6C
The 8052 core provides several addressing modes. The
addressing mode determines how the core will interpret the
memory location or data value specified in assembly language
code. There are six addressing modes as shown in Table 60:
0x2C
0x2B
5E
57 56 55 54 53 52 51 50
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
Table 60. 80ꢀ2 Addressing Modes
4F
4D
4B 4A 49 48
4C
4E
47 46 45 44 43 42 41 40
3F
Addressing
Mode
Example
Bytes
Core Clock
Cycles
3D 3C 3B 3A 39 38
3E
Immediate
MOV A, #A8h
MOV DPTR,#A8h
MOV A, A8h
2
3
2
2
1
1
1
2
3
2
2
1
2
4
37 36 35 34 33 32 31 30
2F
27
1F
2D
2B 2A 29 28
2C
2E
26 25 24 23 22 21 20
1D 1B 1A 19 18
Direct
1E
1C
MOV A, IE
17 16 15 14 13 12 11 10
MOV A, R0
0F
07
0D
0B 0A 09 08
0C
0E
06 05 04 03 02 01 00
Indirect
MOV A,@R0
MOVX A, @DPTR
Figure 58: Bit Addressable Area of General Purpose RAM
Extended
Direct
Bit addressing can be used for instructions that involve Boolean
variable manipulation and program branching—see the
Instruction set.
Extended
Indirect
MOVX A, @R0
1
4
Special Function Registers: Special Function Registers are
registers that affect the function of the 8051 core or its
peripherals. These registers are located in RAM with addresses
0x80 through 0xFF. They are only accessible through direct
addressing as shown in Figure 57 .
Code
Indirect
MOVC A, @A+DPTR
MOVC A, @A+PC
JMP @A+DPTR
1
1
1
4
4
3
Immediate Addressing: In Immediate Addressing, the
expression entered after the number sign (#) will be evaluated
The individual bits of some of the SFRs can be accessed for use
in Boolean and program branching instructions. These SFRs are
Rev. PrE | Page 77 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
by the assembler and stored in the memory address specified.
This number is referred to as a literal because it refers only to a
value and not to a memory location. Instructions using this
addressing mode will be slower than those between two
registers since the literal must be stored and fetched from
memory. The expression can be entered as a symbolic variable
or an arithmetic expression; the value will be computed by the
assembler.
The two instructions above require a total of seven clock cycles
and four bytes of storage in the program memory.
Extended Indirect Addressing: The internal extended RAM is
accessed through a pointer to the address in indirect addressing
mode. The ADE75XX/ADE71XX provides 256 bytes of internal
extended RAM, accessed through MOVX instructions. External
memory is not supported on this device.
In extended indirect addressing mode, a register holds the
address of the byte of extended RAM. The following code will
move the contents of extended RAM address 80h to the
accumulator:
Direct Addressing: With Direct Addressing, the value at the
source address is moved to the destination address. Direct
Addressing provides the fastest execution time of all the
addressing modes when an instruction is performed between
registers using direct addressing. Note that indirect or direct
addressing modes can be used to access general purpose RAM
addresses 0x00 through 0x7F. An instruction with direct
addressing that uses an address between 0x80 and 0xFF is
referring to a special function memory location.
MOV R0,#80h
MOVX A,@R0
The two instructions above require six clock cycles and three
bytes of storage.
Note that there are 256 bytes of extended RAM, so both
extended direct and extended indirect addressing can cover the
whole address range. There is a storage and speed advantage to
using extended indirect addressing because the additional byte
of addressing available through the DPTR register that is not
needed is not stored.
Indirect Addressing: With Indirect Addressing, the value
pointed to by the register is moved to the destination address.
For example, to move the contents of internal RAM address 82h
to the accumulator:
MOV R0,#82h
MOV A,@R0
From the three examples demonstrating the access of internal
RAM from 80h through FFh and extended internal RAM from
00h through FFh, it can be seen that it is most efficient to use
the entire internal RAM accessible through indirect access
before moving to extended RAM.
The two instructions above require a total of four clock cycles
and three bytes of storage in the program memory.
Indirect addressing allows addresses to be computed, and is
useful for indexing into data arrays stored in RAM.
Code Indirect Addressing: The internal code memory can be
accessed indirectly. This can be useful for implementing lookup
tables and other arrays of constants that are stored in Flash. For
example, to move the data stored in Flash memory at address
8002h into the Accumulator:
Note that an instruction that refers to addresses 00 through 7Fh
is referring to internal RAM and indirect or direct addressing
modes can be used. An instruction with indirect addressing that
uses an address between 80h and FFh is referring to internal
RAM, not to a SFR.
MOV DPTR,#8002h
Extended Direct Addressing: The DPTR register is used to
access internal extended RAM in extended indirect addressing
mode. The ADE75XX/ADE71XX provides 256 bytes of internal
extended RAM (XRAM), accessed through MOVX instructions.
External memory spaces are not supported on this device.
CLR
A
MOVX A,@A+DPTR
The Accumulator can be used as a variable index into the array
of Flash memory located at DPTR.
In extended direct addressing mode, the DPTR register points
to the address of the byte of extended RAM. The following code
will move the contents of extended RAM address 100h to the
accumulator:
INSTRUCTION SET
Table 61 documents the number of clock cycles required for
eachinstruction. Most instructions are executed in one or two
clock cycles,resulting in a 4 MIPS peak performance.
MOV DPTR,#100h
MOVX A,@DPTR
Table 61. Instruction Set
Mnemonic
Description
Bytes
Cycles
Arithmetic
ADD A,Rn
ADD A,@Ri
Add register to A
Add indirect memory to A
1
1
1
2
Rev. PrE | Page 78 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Mnemonic
ADD A,dir
ADD A,#data
ADDC A,Rn 1 1
ADDC A,@Ri
ADDC A,dir
ADD A,#data
SUBB A,Rn
SUBB A,@Ri
SUBB A,dir
SUBB A,#data
INC A
Description
Bytes
Cycles
Add direct byte to A
Add immediate to A
2
2
1
1
2
2
1
1
2
2
1
1
1
2
1
1
1
1
2
1
1
1
2
2
1
2
2
2
1
2
2
2
1
1
2
2
3
1
1
2
2
9
9
2
Add register to A with carry
Add indirect memory to A with carry
Add direct byte to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract indirect memory from A with borrow
Subtract direct from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Ri Increment indirect memory
Increment direct byte
Increment data pointer
Decrement A
Decrement register
INC Rn
INC @
INC dir
INC DPTR
DEC A
DEC Rn
DEC @Ri
DEC dir
MUL AB
Decrement indirect memory
Decrement direct byte
Multiply A by B
Divide A by B
Decimal adjust A
DIV AB
DA A A
Logic
ANL A,Rn
AND register to A
1
1
2
2
2
3
1
1
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
3
ANL A,@Ri
ANL A,dir
AND indirect memory to A
AND direct byte to A
ANL A,#data
ANL dir,A
AND immediate to A
AND A to direct byte
ANL dir,#data
ORL A,Rn
AND immediate data to direct byte
OR register to A
ORL A,@Ri
ORL A,dir
OR indirect memory to A
OR direct byte to A
ORL A,#data
ORL dir,A
OR immediate to A
OR A to direct byte
ORL dir,#data
XRL A,Rn
OR immediate data to direct byte
Exclusive-OR register to A
Exclusive-OR indirect memory to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
dir Exclusive-OR indirect memory to A
Exclusive-OR immediate data to direct
XRL A,@Ri
XRL A,#data
XRL dir,A
XRL A,
XRL dir,#data
CLR A
CPL A
SWAP A
RL A
RLC A
RR A
Clear A
Complement A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RRC A
Rotate A right through carry
Rev. PrE | Page 79 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Mnemonic
Description
Bytes
Cycles
Data Transfer
MOV A,Rn
Move register to A
1
1
1
1
2
2
2
2
2
2
2
2
2
3
3
3
1
1
1
1
1
1
2
2
1
1
1
2
1
2
1
2
2
2
2
2
2
2
2
2
2
3
3
3
4
4
4
4
4
4
2
2
1
2
2
2
MOV A,@Ri
Move indirect memory to A
Move A to register
MOV Rn,A
MOV @Ri,A
Move A to indirect memory
Move direct byte to A
MOV A,dir
MOV A,#data
MOV Rn,#data
MOV dir,A
Move immediate to A
Move register to immediate
Move A to direct byte
MOV Rn,dir
MOV dir,Rn
MOV @Ri,#data
MOV dir,@Ri
MOV @Ri,dir
MOV dir,dir
MOV dir,#data
MOV DPTR,#data
MOVC A,@A+DPTR
MOVC A,@A+PC
MOVX A,@Ri
MOVX A,@DPTR
MOVX @Ri,A
MOVX @DPTR,A
PUSH dir
Move register to direct byte
Move direct to register
Move immediate to indirect memory
Move indirect to direct memory
Move direct to indirect memory
Move direct byte to direct byte
Move immediate to direct byte
Move immediate to data pointer
Move code byte relative DPTR to A
Move code byte relative PC to A 1
Move external (A8) data to A
Move external (A16)data to A
Move A to external data (A8)
Move A to external data (A16)
Push direct byte onto stack
Pop direct byte from stack
Exchange A and register
POP dir
XCH A,Rn
XCH A,@Ri
Exchange A and indirect memory
Exchange A and indirect memory nibble
Exchange A and direct byte
XCHD A,@Ri
XCH A,dir
Boolean
CLR C
Clear carry
1
2
1
2
1
2
2
2
2
2
2
2
1
2
1
2
1
2
2
2
2
2
2
2
CLR bit
Clear direct bit
SETB C
Set carry
SETB bit
CPL C
Set direct bit
Complement carry
Complement direct bit
AND direct bit and carry
AND direct bit inverse to carry
OR direct bit and carry
direct bit inverse to carry
Move direct bit to carry
Move carry to direct bit
CPL bit
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit OR
MOV C,bit
MOV bit,C
Branching
Rev. PrE | Page 80 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Mnemonic
Description
Bytes
Cycles
JMP @A+DPTR
Jump indirect relative to DPTR
1
3
RET
Return from subroutine
1
1
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
4
4
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
RETI
Return from interrupt
ACALL addr11
AJMP addr11
SJMP rel
Absolute jump to subroutine
Absolute jump unconditional
Short jump (relative address)
Jump on carry equal to 1
JC rel
JNC rel
Jump on carry equal to 0
JZ rel
Jump on accumulator =0
JNZ rel
Jump on accumulator not equal to 0
Decrement register,JNZ relative
Long jump unconditional
DJNZ Rn,rel
LJMP
LCALL addr16
JB bit,rel
Long jump to subroutine
Jump on direct bit =1
JNB bit,rel
JBC bit,rel
CJNE A,dir,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
CJNE @Ri,#data,rel
DJNZ dir,rel
Jump on direct bit =0
Jump on direct bit =1 and clear
Compare A,direct JNE relative
Compare A,immediate JNE relative
Compare register,immediate JNE relative
Compare indirect,immediate JNE relative
Decrement direct byte,JNZ relative
Miscellaneous
NOP
No operation
1
1
ANL
ANL P0, A
ORL P1, A
XRL P2, A
JBC P1.1, LABEL
CPL P2.0
Logical AND
READ-MODIFY-WRITE INSTRUCTIONS
ORL
XRL
JBC
Logical OR
Some 8051 instructions read the latch while others read the pin.
The state of the pin is read for instructions that input a port bit.
Instructions that read the latch rather than the pins are the ones
that read a value, possibly change it, and rewrite it to the latch.
Since these instructions involve modifying the port, it is
assumed that the pins being modified are outputs, so the output
state of the pin is read from the latch. This prevents a possible
misinterpretation of the voltage level of a pin. For example, if a
port pin is used to drive the base of a transistor, a 1 is written to
the bit, to turn the transistor on. If the CPU reads the same port
bit at the pin rather than the latch, it reads the base voltage of
the transistor and interprets it as Logic 0. Reading the latch
rather than the pin returns the correct value of 1.
Logical EX-OR
Jump if Bit = 1 and clear bit
Complement bit
Increment
CPL
INC
INC P2
DEC
DJNZ
DEC P2
Decrement
DJNZ P0, LABEL Decrement and jump if not
zero
MOV PX.Y, C1
MOV P0.0,C
Move Carry to Bit Y of Port
X
CLR PX.Y1
CLR P0.0
Clear Bit Y of Port X
Set Bit Y of Port X
SETB PX.Y1
SETB P0.0
___________________________________________
1 These instructions read the port byte (all 8 bits), modify the addressed bit,
and write the new byte back to the latch.
The instructions that read the latch rather than the pins are
called read-modify-write instructions, and are listed in Table 62.
When the destination operand is a port or a port bit, these
instructions read the latch rather than the pin.
INSTRUCTIONS THAT AFFECT FLAGS
Many instructions explicitly modify the Carry bit such as the
MOV C, bit and CLR C instructions. Other instructions that
affect status flags are listed in this section.
Table 62. Read-Modify-Write Instructions
Instruction
Example
Description
Rev. PrE | Page 81 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
ADD
A, source
operands are unsigned.
Function: Adds the source to the Accumulator.
OV
Set if there is a borrow is needed for bit 6 or bit 7 but
not for both. Used to indicate an overflow for signed
subtraction. This flag will be set if a negative number
subtracted from a positive yields a negative result or it
a positive number subtracted from a negative number
yields a positive result.
Status Flags Referenced by Instruction: None
Status Flags Affected:
Status
Flag
Description
C
Set if there is a carry out of bit 7. Cleared otherwise.
Used to indicate an overflow if the operands are
unsigned.
AC
Set if a borrow is needed for bit 3. Cleared otherwise.
MUL
AB
OV
Set if there is a carry out of bit 6 or a carry out of bit 7
but not if both are set. Used to indicate an overflow
for signed addition. This flag will be set if two positive
operands yield a negative result or two negative
operands yield a positive result.
Function: Multiplies the Accumulator by the B register. This
operation is unsigned. The lower byte of the 16-bit product is
stored in the Accumulator and the higher byte is left in the B
register.
AC
Set if there is a carry out of bit 3. Cleared otherwise.
Status Flags Referenced by Instruction: None
Status Flags Affected: None
Status
Flag
Description
ADDC A, source
Function: Adds the source and the Carry bit to the Accumulator
C
Cleared
Status Flags Referenced by Instruction: Carry
Status Flags Affected:
OV
Set if the result is greater than 255. Cleared
otherwise.
Status
Flag
Description
DIV
AB
C
Set if there is a carry out of bit 7. Cleared otherwise.
Used to indicate an overflow if the operands are
unsigned.
Function: Divides the Accumulator by the B register. This
operation is unsigned. The integer part of the quotient is stored
in the Accumulator and the remainder goes into the B register.
OV
Set if there is a carry out of bit 6 or a carry out of bit 7
but not if both are set. Used to indicate an overflow
for signed addition. This flag will be set if two positive
operands yield a negative result or two negative
operands yield a positive result.
Status Flags Referenced by Instruction: None
Status Flags Affected:
Status
Flag
Description
AC
Set if there is a carry out of bit 3. Cleared otherwise.
C
Cleared
OV
Cleared unless the B register was equal to 0, in which
case the results of the division are undefined and the
OV flag is set.
SUBB A, source
Function: Subtract the source byte and the carry (borrow) flag
from the Accumulator.
DA
A
Status Flags Referenced by Instruction: Carry (Borrow)
Status Flags Affected:
Function: Adjusts the Accumulator to hold two four bit digits
after the addition of two binary coded decimals (BCDs) with
the ADD or ADDC instructions. If the AC bit is set or if the
value of bits 0-3 exceed 9, 0x06 is added to the accumulator to
correct the lower four bits. If the carry bit was set when the
instruction began, or if 0x06 was added to the accumulator in
the first step, 0x60 is added to the accumulator to correct the
higher four bits.
Status Description
Flag
C
Set if there is a borrow needed for of bit 7. Cleared
otherwise. Used to indicate an overflow if the
Rev. PrE | Page 82 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Status Flags Referenced by Instruction: Carry, AC
Status Flags Affected:
Status
Flag
Description
C
Set if the result is greater than 99h. Cleared
otherwise.
RRC
A
Function: Rotates the accumulator to the right through the
carry flag. The old LSB of the Accumulator becomes the new
carry flag and the old carry flag is loaded into the new MSB of
the Accumulator.
Status Flags Referenced by Instruction: Carry
Status Flags Affected:
Status
Flag
Description
C
Equal to the state of ACC.0 before execution of the
instruction
RLC
A
Function: Rotates the accumulator to the left through the carry
flag. The old MSB of the Accumulator becomes the new carry
flag and the old carry flag is loaded into the new LSB of the
Accumulator.
Status Flags Referenced by Instruction: Carry
Status Flags Affected:
Status
Flag
Description
C
Equal to the state of ACC.7 before execution of the
instruction
CJNE destination, source, relative jump
Function: Compares the value of the source to the value of the
destination and branches to the location set by the relative jump
if they are not equal. If the values are equal, program execution
continues with the instruction after the CJNE instruction.
Status Flags Referenced by Instruction: None
Status Flags Affected:
Status
Flag
Description
C
Set if the source value is greater than the destination
value. Cleared otherwise.
Rev. PrE | Page 83 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
INTERRUPT SYSTEM
Figure 60: Standard 8051 Interrupt Priority Levels
The unique power management architecture of the
ADE75XX/ADE71XX includes an operating mode where the
8052 MCU core is shut down, PSM2. There are events that can
be configured to wake the 8052 MCU core from the PSM2
operating mode where the MCU core is shut down. A
distinction is drawn here between events that can trigger the
wakeup of the 8052 MCU core and events that can trigger an
interrupt when the MCU core is active. Events that can wake the
core are referred to as wakeup events while events that can
interrupt the program flow when the MCU is active are called
interrupts. See the 3.3V Peripherals and Wakeup Events section
to learn more about events that can wake the 8052 core from
PSM2.
A Priority 1 interrupt can interrupt the service routine of a
Priority 0 interrupt, and if two interrupts of different priorities
occur at the same time, the Priority 1 interrupt is serviced first.
An interrupt cannot be interrupted by another interrupt of the
same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed. See the
Interrupt Priority section.
ADE75XX/ADE71XX INTERRUPT ARCHITECTURE
The ADE75XX/ADE71XX provides advanced power supply
monitoring features. To ensure a fast response to time critical
power supply issues, such as a loss of line power, the power
supply monitoring interrupt should be able to interrupt any
interrupt service routine. In order to enable the user to make
full use of the standard 8051 interrupt priority levels, an
additional priority level was added for the power supply
management, PSM, interrupt. The PSM interrupt is the only
interrupt at this highest interrupt priority level.
The ADE75XX/ADE71XX provides 12 interrupt sources with
three priority levels. The power management interrupt is alone
at the highest priority level. The other two priority levels are
configurable through the Interrupt priority SFR (IP, 0xB8) and
Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9).
STANDARD 8051 INTERRUPT ARCHITECTURE
High
PSM
The 8051 standard interrupt architecture includes two tiers of
interrupts, where some interrupts are assigned a high priority
and others are assigned a low priority.
Priority 1
Priority 0
Low
Figure 61: ADE75XX/ADE71XX Interrupt Architecture
High
Priority 1
See the Power Supply Monitor Interrupt (PSM) section for
more information on the PSM interrupt.
Priority 0
Low
INTERRUPT SFR REGISTER LIST
The control and configuration of the interrupt system is carried out through three interrupt-related SFRs:
SFR
Address
Default
Value
Bit
Description
Addressable
IE
IP
IEIP2
0xA8
0xB8
0xA9
0x00
0x00
0xA0
Yes
Yes
No
Interrupt Enable Register
Interrupt Priority Register
Secondary Interrupt Enable
Register
INTPR
0xFF
0x00
No
Interrupt Pins Configuration SFR
Table 63. Interrupt Enable SFR (IE, 0xA8)
Bit Location Bit Addr. Bit Name Description
7
0xAF
EA
Set by the user to enable all interrupt sources.
Cleared by the user to disable all interrupt sources.
Set by the user to enable the temperature ADC interrupt.
Set by the user to enable the Timer 2 interrupt.
Set by the user to enable the UART serial port interrupt.
Set by the user to enable the Timer 1 interrupt.
Set by the user to enable External Interrupt 1 (INT1).
6
5
4
3
2
1
0xAE
0xAD
0xAC
0xAB
0xAA
0xA9
ETEMP
ET2
ES
ET1
EX1
ET0
Set by the user to enable the Timer 0 interrupt.
Rev. PrE | Page 84 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
0
0xA8
EX0
Set by the user to enable External Interrupt 0 (INT0).
Table 64. Interrupt priority SFR (IP, 0xB8)
Bit Location
Bit
Addr.
Bit Name
Description
7
0xBF
PADE
ADE Energy Measurement Interrupt Priority (1 = High; 0 =
Low).
6
5
4
3
2
1
0
0xBE
0xBD
0xBC
0xBB
0xBA
0xB9
0xB8
PTEMP
PT2
PS
Temperature ADC Interrupt Priority (1 = High; 0 = Low).
Timer 2 Interrupt Priority (1 = High; 0 = Low).
UART Serial Port Interrupt Priority (1 = High; 0 = Low).
Timer 1 Interrupt Priority (1 = High; 0 = Low).
PT1
PX1
PT0
PX0
INT1 (External Interrupt 1) priority (1 = High; 0 = Low).
Timer 0 Interrupt Priority (1 = High; 0 = Low).
INT0 (External Interrupt 0) Priority (1 = High; 0 = Low).
Table 6ꢀ. Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9)
Bit
Location
Bit
Mnemonic
Description
7
6
5
4
3
2
1
0
PTI
RTC Interrupt Priority (1 = High; 0 = Low).
PSI
SPI/I2C Interrupt Priority (1 = High; 0 = Low).
EADE
ETI
Set by the user to enable the Energy Metering Interrupt (ADE)
Set by the user to enable the RTC interrupt.
EPSM
ESI
Set by the user to enable the PSM Power Supply Management interrupt.
Set by the user to enable the SPI/I2C interrupt.
Interrupt pins configuration SFR (INTPR, 0xFF)
Bit
Bit
Default
Value
0
Description
Location Mnemonic
7
RTCCAL
Control RTC calibration output
When set, the RTC calibration frequency selected by FSEL[1:0] is
output on the P0.2/CF1/RTCCAL pin.
6-5
FSEL[1:0]
Sets RTC calibration output frequency and calibration window
FSEL[1:0]
Calibration window, fRTCCAL calibration frequency
30.5 seconds, 1Hz
0
0
1
1
0
1
0
1
30.5 seconds, 512 Hz
0.244 seconds, 500Hz
0.244 seconds, 16.384 kHz
4
Reserved
3-1
INT1PRG[2:0]
000
Controls the function of INT1
INT1PRG[2:0]
Function
GPIO
x
0
0
x
0
1
0
1
1
1
x
x
BCTRL
INT1 input disabled
INT1 input enabled
0
INT0PRG
0
Controls the function of INT0
INT0PRG
Function
0
1
INT0 input disabled
INT0 input enabled
Rev. PrE | Page 85 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Table 66. WatchDog Timer SFR (WDCON, 0xC0)
Bit
Location
7-4
Bit
Addr.
Bit
Name
PRE[3:0]
Default Description
Value
0xC7 –
0xC4
7
Watchdog pre-scaler. In normal mode, the 16-bit watchdog timer is clocked by the
input clock (32.768kHz). The PRE bits set which of the upper bits of the counter are
29
twatchdog = 2PRE
×
used as the watchdog output following:
CLKIN
[3:0]
Watchdog Timeout
0000 15.6ms
0001 31.2ms
0010 62.5ms
0011 125ms
0100 250ms
0101 500ms
0110 1s
0111 2s
1000
1001
1010 to 1111
0
0
Automatic Reset
Serial download reset
Not a valid selection
3
2
1
0xC3
0xC2
0xC1
WDIR
WDS
WDE
0
0
1
Watchdog interrupt response bit.
When clear, watchdog will generate a system reset when the watchdog time out
period has expired
When set, the watchdog will generate a interrupt when the watchdog time out
period has expired.
WDS Watchdog status bit.
This bit is set to indicate that a watchdog timeout has occurred.
WDS is cleared by writing a zero or by an external hardware reset. A watchdog
reset will not clear WDS. The bit can therefore be used to distinguish between a
watchdog reset and a hardware reset from the RESET pin.
WDE Watchdog enable bit.
When set, enables the watchdog and clears its counter (e.g. 2 above). The
watchdog counter is subsequently cleared again whenever the WDE bit is set. If
the watchdog is not cleared within its selected timeout period it will generate a
system reset or watchdog interrupt, depending on the WDIR bit. The watchdog is
disabled (and WDE cleared) by any of the following:
Write zero to WDE
Watchdog reset (WDIR = 0)
Hardware reset
PSM interrupt
LOCK interrupt.
0
0xC0
WDWR
0
WDWR Watchdog write enable bit. To write data into the WDCON SFR involves a
double instruction sequence. The WDWR bit must be set and the following
instruction must be a write instruction to the WDCON SFR. This sequence is
necessary so that the WDCON SFR is protected from code execution upsets that
might unintentionally modify this SFR. Interrupts should be disabled during this
operation due to the consecutive instruction cycles.
e.g. Disable Watch dog
1 write to WDCON e.g. 2 Clear WDE bit
CLR EA
SETB WDWR
CLR WDE
SETB EA
Rev. PrE | Page 86 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
INTERRUPT PRIORITY
If two interrupts of the same priority level occur simultaneously, the polling sequence, as shown in
Table 67, is observed.
Table 67. Priority within Interrupt Level
Source
IPSM
IRTC
Priority
Description
0 (Highest)
Power Supply Monitor Interrupt
RTC interrupt
1
IADE
WDT
ITEMP
IE0
2
ADE Energy measurement interrupt
Watchdog Timer Overflow Interrupt
Temperature ADC interrupt
External Interrupt 0
3
4
5
TF0
6
Timer/Counter 0 Interrupt
External Interrupt 1
IE1
7
TF1
8
Timer/Counter 1 Interrupt
SPI/I2C Interrupt
ISPI/I2CI
RI/TI
9
10
UART Serial Port Interrupt
Timer/Counter 2 Interrupt
TF2/EXF2
11 (Lowest)
INTERRUPT FLAGS
The interrupt and status flags associated with the interrupt vectors are shown in Table 68 and Table 69. Most of the interrupts have flags
associated with them.
Table 68. Interrupt Flags
Interrupt Source
Flags
Bit
Address
Details
IE0
TCON.1
IE0
External Interrupt 0
Note: The INT0PRG bit must be set in the Interrupt pins configuration SFR
(INTPR, 0xFF) to allow the INT0 signal into the chip
TF0
IE1
TCON.5
TCON.3
TF0
IE1
Timer 0
External Interrupt 1
Note: The INT1PRG[2] bit must be set in the Interrupt pins configuration SFR
(INTPR, 0xFF) to allow the INT1 signal into the chip
TF1
TCON.7
SCON.1
SCON.0
T2CON.7
T2CON.6
-
TF1
TI
Timer 1
RI + TI
Transmit Interrupt
Receive Interrupt
Timer 2 overflow flag
Timer 2 external flag
RI
TF2 + EXF2
TF2
EXF2
ITEMP (Temperature
ADC)
The Temperature ADC interrupt does not have an interrupt flag associated with
it.
IPSM (Power Supply)
IPSMF.6
FPSM
PSM interrupt flag
IADE (Energy
Measurement DSP)
MIRQSTL.7
Read MIRQSTH, MIRQSTM, MIRQSTL. Write a “0” to a bit to clear and
acknowledge the event.
Table 69. Status Flags
Interrupt Source
Flags
Bit
Address
Details
ITEMP (Temperature ADC)
ISPI/I2CI
-
The Temperature ADC interrupt does not have an status flag associated with it.
SPI Interrupt Status register
SPISTAT
Rev. PrE | Page 87 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
I2CSTAT
I2C Interrupt Status register
RTC Midnight flag
IRTC
TIMECON.7
TIMECON.2
WDCON.2
RTC Alarm flag
WDT (Watchdog Timer)
WDS
Watchdog Timeout flag
interrupt. Similarly, clearing the I2C/SPI status bits in the SPI
Interrupt Status Register SFR (SPISTAT, 0xEA) will not cancel a
pending I2C/SPI interrupt. These interrupts will remain
pending until the RTC or I2C/SPI interrupt vectors are enabled.
Their respective interrupt service routines will be entered
shortly thereafter.
A functional block diagram of the interrupt system is shown in
Figure 62. Note that the PSM interrupt is the only interrupt in
the highest priority level.
If an external wakeup event occurs to wake the
ADE75XX/ADE71XX from PSM2, a pending external interrupt
will be generated. When the EX0 or EX1 bits are set in the
Interrupt Enable SFR (IE, 0xA8) to enable external interrupts,
the program counter will be loaded with the IE0 or IE1
interrupt vector. The IE0 and IE1 interrupt flags in the TCON
register will not be affected by events that occur when the 8052
MCU core is shut down during PSM2 — see the Power Supply
Monitor Interrupt (PSM) section.
Figure 62 shows how the interrupts are cleared when the
interrupt service routines are entered. Some interrupts with
multiple interrupt sources are not automatically cleared,
specifically the PSM, ADE, UART and Timer 2 interrupt
vectors. Note that the INT0 and INT1 interrupts are only
cleared if the external interrupt is configured to be triggered by
a falling edge, by setting IT0 in the Timer/Counter 0 and 1
Control SFR (TCON, 0x88). If INT0 or INT1 is configured to
interrupt on a low level, the interrupt service routine will be
reentered until the respective pin goes high.
The RTC, temperature ADC and I2C/SPI interrupts are latched
such that pending interrupts cannot be cleared without entering
their respective interrupt service routines. Clearing the RTC
Midnight and Alarm flags will not clear a pending RTC
Rev. PrE | Page 88 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
IP/IEIP2 REGISTERS
PRIORITY LEVEL
IE/IEIP2 REGISTERS
LOW
HIGH
HIGHEST
IPSMF
IPSME
FPSM
(IPSMF.6)
PSM
RTC
IN OUT
LATCH
MIDNIGHT
ALARM
RESET
MIRQSTH MIRQSTM MIRQSTL
MIRQENHMIRQENM MIRQENL
ADE
MIRQSTL.7
WATCHDOG TIMEOUT
WDIR
WATCHDOG
IN OUT
LATCH
TEMPADC INTERRUPT
TEMP ADC
RESET
PSM2
IT0
0
INT0
EXTERNAL
INTERRUPT 0
IE0
1
IT0
INTERRUPT
POLLING
SEQUENCE
TF0
TIMER 0
PSM2
IE1
IT1
0
EXTERNAL
INTERRUPT 1
INT1
1
IT1
TF1
TIMER 1
I2C/SPI
CFG.5
SPI INTERRUPT
1
IN OUT
LATCH
I2C INTERRUPT
0
RESET
RI
TI
UART
TF2
TIMER 2
EXF2
INDIVIDUAL INTERRUPT
ENABLES
LEGEND
AUTOMATIC
CLEAR SIGNAL
GLOBAL INTERRUPT
ENABLE (EA)
Rev. PrE | Page 89 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Figure 62: Interrupt System Functional Block Diagram
with a clock of 4.096MHz. The longest interrupt latency for a
high priority interrupt results when a pending interrupt is
generated during a low priority interrupt RETI, followed by a
multiply instruction. This results in a maximum interrupt
latency of 16.25 instruction cycles, 4us with a clock of
4.096MHz.
INTERRUPT VECTORS
When an interrupt occurs, the program counter is pushed onto
the stack, and the corresponding interrupt vector address is
loaded into the program counter. When the interrupt service
routine has been completed, the program counter is popped off
the stack by a RETI instruction. This allows program execution
to resume from where it was interrupted. The interrupt vector
addresses are shown in Table 70.
CONTEXT SAVING
When the 8052 vectors to an interrupt, only the program
counter is saved on the stack. Therefore the interrupt service
routine must be written to ensure that registers that are used in
the main program are restored to their pre-interrupt state.
Common registers that may be modified in the ISR are the
accumulator, and the PSW register. Any general purpose
registers that are used as scratchpads in the ISR should also be
restored before exiting the interrupt. The example 8051 code
shown below shows how to restore some commonly used
registers:
Table 70. Interrupt Vector Addresses
Source
Vector Address
0x0003
0x000B
0x0013
0x001B
0x0023
0x002B
0x0033
0x003B
0x0043
0x004B
0x0053
0x005B
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
ITEMP (Temperature ADC)
ISPI/I2CI
GeneralISR:
; save the current Accumulator value
PUSH ACC
; save the current status and register bank selection
PUSH PSW
IPSM (Power Supply)
IADE (Energy Measurement DSP)
IRTC
WDT (Watchdog Timer)
; service interrupt
…
INTERRUPT LATENCY
The 8051 architecture requires that at least one instruction
executes between interrupts. To ensure this, the 8051 MCU core
hardware prevents the program counter from jumping to an ISR
immediately after completing a RETI instruction or an access of
the IP and IE registers.
; restore the status and register bank selection
POP
PSW
; restore the accumulator
POP
ACC
RETI
The shortest interrupt latency is 3.25 instruction cycles, 800ns
Rev. PrE | Page 90 of 148
Preliminary Technical Data
WATCHDOG TIMER
ADE75xx/ADE71xx
described in Table 71 is initiated on every write access to the
WDCON SFR.
The watchdog timer generates a device reset or interrupt within a
reasonable amount of time if the ADE75XX/ADE71XX enters
an erroneous state, possibly due to a programming error or
electrical noise. The watchdog is enabled by default with a time
out of 2 seconds and will create a system reset if not cleared
within 2 seconds. The watchdog function can be disabled by
clearing the WDE (watchdog enable) bit in the watchdog
control (WatchDog Timer SFR (WDCON, 0xC0).
In order to prevent any code from inadverdently disabling the
watchdog, a watchdog protection can be activated. This
watchdog protection locks in the watchdog enable and event
settings so that they cannot be changed by user code. The
protection is activated by clearing a watchdog protection bit in
the Flash memory. The watchdog protection bit is the most
significant bit at the address 0x3FFA of the Flash memory.
When this bit is cleared, the WDIR bit is forced to 0 and the
WDE bit is forced to 1. Note that the sequence for configuring
the flash protection bits must be followed to modify the
watchdog protection bit at 0x3FFA—see the Protecting the
Flash section.
The watchdog circuit generates a system reset or interrupt
(WDS) if the user program fails to set the WDE bit within a
predetermined amount of time (see the PRE3…0 bits in
WatchDog Timer SFR (WDCON, 0xC0)). The watchdog timer
is clocked from the 32.768 kHz external crystal connected
between the CLKIN and CLKOUT pins. The WDCON SFR can
be written only by user software if the double write sequence
Table 71. WatchDog Timer SFR (WDCON, 0xC0)
Bit
Location
7-4
Bit
Addr.
Bit
Name
PRE[3:0]
Default Description
Value
0xC7 –
0xC4
7
Watchdog pre-scaler. In normal mode, the 16-bit watchdog timer is clocked by the
input clock (32.768kHz). The PRE bits set which of the upper bits of the counter are
29
twatchdog = 2PRE
×
used as the watchdog output following:
CLKIN
[3:0]
Watchdog Timeout
0000 15.6ms
0001 31.2ms
0010 62.5ms
0011 125ms
0100 250ms
0101 500ms
0110 1s
0111 2s
1000
1001
1010 to 1111
0
0
Automatic Reset
Serial download reset
Not a valid selection
3
2
0xC3
0xC2
WDIR
WDS
0
0
Watchdog interrupt response bit.
When clear, watchdog will generate a system reset when the watchdog time out
period has expired
When set, the watchdog will generate a interrupt when the watchdog time out
period has expired.
WDS Watchdog status bit.
This bit is set to indicate that a watchdog timeout has occurred.
WDS is cleared by writing a zero or by an external hardware reset. A watchdog
reset will not clear WDS. The bit can therefore be used to distinguish between a
watchdog reset and a hardware reset from the RESET pin.
1
0
0xC1
0xC0
WDE
1
0
WDE Watchdog enable bit.
When set, enables the watchdog and clears its counter (e.g. 2 above). The
watchdog counter is subsequently cleared again whenever the WDE bit is set. If
the watchdog is not cleared within its selected timeout period it will generate a
system reset or watchdog interrupt, depending on the WDIR bit.
WDWR
WDWR Watchdog write enable bit. To write data into the WDCON SFR involves a
double instruction sequence. The WDWR bit must be set and the following
instruction must be a write instruction to the WDCON SFR. This sequence is
Rev. PrE | Page 91 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
necessary so that the WDCON SFR is protected from code execution upsets that
might unintentionally modify this SFR. Interrupts should be disabled during this
operation due to the consecutive instruction cycles.
e.g. Disable Watch dog
CLR EA
SETB WDWR
CLR WDE
SETB EA
Table 72. WatchDog and Flash protection byte in Flash (Flash Address = 0x3FFA)
Bit
Bit
Default Value
Description
Location
Name
7
WDPROT_PROTKY7
1
This bit holds the protection for the Watchdog timer and the 7th bit of
the Flash protection key.
When this bit is cleared, the watchdog enable and event, selected by
WDE and WDIR cannot be changed by user code. The watchdog
configuration is then fixed to WDIR=0 and WDE=1. The watchdog
timeout in PRE[3:0] can still be modified by user code.
The value of this bit is also used to set the Flash protection key. If this
bit is cleared to protect the watchdog, then the default value for the
Flash protection key is 0x7F instead of 0xFF—see the Protecting the
Flash section for more information on how to clear this bit.
7-0
PROTKY[7:0]
0xFF
These bits hold the flash protection key. The content of this Flash
address is compared to the Flash Protection Key SFR (PROTKY, 0xBB)
when the protection is being set or changed. If the two values match,
the new protection is written to the Flash addresses 0x3FFF to 0x3FFB.
see the Protecting the Flash section for more information on how to
configure these bits.
Watchdog Timer Interrupt
If the watchdog timer is not cleared within the watchdog
timeout period, a system reset will occur unless the watchdog
timer interrupt is enabled. The watchdog timer interrupt enable
bit is located in the WatchDog Timer SFR (WDCON, 0xC0).
Enabling the watchdog timer interrupt allows the program to
examine the stack or other variables that could have led the
program astray. The watchdog timer interrupt also allows the
watchdog to be used as a long interval timer.
Note that the Watchdog Timer Interrupt is automatically
configured as a high priority interrupt. This interrupt cannot be
disabled by the EA bit in the IE register. Even if all of the other
interrupts are disabled, the watchdog is kept active to watch
over the program.
Rev. PrE | Page 92 of 148
Preliminary Technical Data
LCD DRIVER
ADE75xx/ADE71xx
LCD SFR REGISTER LIST
There are six LCD control registers that configure the driver for
the specific type of LCD in the end system and set up the user
display preferences. The LCD Configuration SFR (LCDCON,
0x95), LCD Configuration X SFR (LCDCONX, 0x9C) and LCD
Configuration Y SFR (LCDCONY, 0xB1) SFRs contains general
LCD driver configuration information including the LCD
enable and reset, as well as method of LCD voltage generation
and the multiplex level. The LCD Clock SFR (LCDCLK, 0x96)
configures timing settings for LCD frame rate and blink rate.
LCD pins are configured for LCD functionality in the LCD
Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment
Enable 2 SFR (LCDSEGE2, 0xED).
The LCD module is capable of directly driving an LCD panel of
24 x 4 segments without compromising any
ADE75XX/ADE71XX functionalities. Using shared pins, the
driver can accommodate an LCD with up to 26 x 4 segments. It
is capable of driving LCDs with 2x, 3x and 4x multiplexing.
LCD waveform voltages generated through internal charge
pump circuitry support up to 5V LCDs. An external resistor
ladder for LCD waveform voltage generation is also supported.
The ADE75XX/ADE71XX has an embedded LCD control
circuit, LCD driver and power supply circuit. The LCD module
is functional in all Operating modes.
Table 73. LCD Driver SFRs
SFR
address
(hex)
R/W
Name
Description
0x95
0x96
0x97
0x9C
0xAC
0xAE
0xB1
0xED
0xF4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCDCON
LCDCLK
LCDSEGE
LCDCONX
LCDPTR
LCD Configuration SFR
LCD Clock
LCD Segment Enable
LCD Configuration X
LCD Pointer
LCDDAT
LCDCONY
LCDSEGE2
PERIPH
LCD Data
LCD Configuration Y
LCD Segment Enable 2
Peripheral Configuration
Table 74. LCD Configuration SFR (LCDCON, 0x9ꢀ)
Bit
Location
Bit
Mnemonic
LCDEN
Default
Value
Description
7
0
0
0
LCD enable.
If this bit is set, the LCD driver is enabled.
LCD data registers are reset to zero.
If this bit is set, the LCD data registers will be reset to zero.
Blink Mode enable bit.
6
5
LCDRST
BLINKEN
If this bit is set, blink mode is enabled. The blink mode is configured by the
BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96)
4
3
2
LCDPSM2
CLKSEL
BIAS
0
0
0
Force LCD off when in PSM2 (Sleep mode).
0
1
The LCD is disabled or enabled in PSM2 by LCDEN bit.
The LCD is disabled in PSM2 regarless of LCDEN setting.
LCD clock selection
fLCDCLK
0
1
2048Hz
128Hz
Bias Mode
0
1/2
Rev. PrE | Page 93 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
1
1/3
1-0
LMUX[1:0]
0
LCD Multiplex level
LMUX[1:0]
0
0
0
1
Reserved
2x
FP27/COM3 is used as FP27
FP28/COM2 is used as FP28
3x
FP27/COM3 is used as FP27
FP28/COM2 is used as COM2
4x
1
1
0
1
FP27/COM3 is used as COM3
FP28/COM2 is used as COM2
Table 7ꢀ. LCD Configuration X SFR (LCDCONX, 0x9C)
Bit
Location
Bit
Default
Value
Description
Mnemonic
Reserved
EXTRES
7
6
0
0
Reserved
External Resistor Ladder selection bit.
0
1
External resistor ladder is disabled. Charge pump is enabled.
External resistor ladder is enabled. Charge pump is disabled.
5-0
BIASLVL[5:0]
0
Bias Level Selection bits. See Table 76.
Table 76. LCD bias voltage when contrast control is enabled
BLVL[5] VA (V) 1/2 Bias
1/3 Bias
VB
VC
VB
VC
0
1
BLVL
[
4:0
]
Vref
×
31
VB = VA
VC = 2 x VA
VB = 2 x VA
VC = 3 x VA
BLVL
[
4:0
]
⎛
⎝
⎞
⎟
Vref × 1+
⎜
31
⎠
Table 77. LCD Configuration Y SFR (LCDCONY, 0xB1)
Bit
Location
Bit
Default
Value
Description
Mnemonic
Reserved
INV_LVL
7
6
0
0
This bit should be kept cleared for proper operation
Frame Inversion Mode Enable bit
If this bit is set, frames are inverted every other frame
If this bit is cleared, frames are not inverted
5-2
1
Reserved
0
0
These bits should be kept cleared for proper operation
UPDATEOVER
Update finished flag bit. This bit is updated by LCD driver.
When set, indicates that the LCD memory has been updated and a new
frame has begun.
0
REFRESH
0
Refresh LCD data memory bit, this bit should be set by user.
When set, the LCD driver does not use the data in the LCD data registers to
update display. The LCD data registers can be updated by the 8052.
When clear, the LCD driver will use the data in the LCD data registers to
update display at the next frame.
Rev. PrE | Page 94 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Table 78. LCD Clock SFR (LCDCLK, 0x96)
Bit
Location
7-6
Bit
Default
Value
Description
Mnemonic
BLKMOD[1:0]
0
Blink Mode Clock Source Configuration bits
BLKMOD[1:0]
0
0
1
1
0
1
0
1
The blink rate is controlled by software. The display is OFF.
The blink rate is controlled by software. The display is ON.
The blink rate is 2 Hz
The blink rate is set by BLKFREQ[1:0]
5-4
BLKFREQ[1:0]
0
Blink Rate Configuration bits
These bits control LCD blink rate if BLKMOD[1:0]=11
BLKFREQ[1: Blink rate (Hz)
0]
0
0
1
1
0
1
0
1
1
1/2
1/3
1/4
3-0
FD[3:0]
0
LCD Frame Rate Selection bits. See Table 79 and Table 80.
Table 79. LCD frame rate selection for fLCDCLK=2048Hz (LCDCON[3]=0)
2x multiplexing 3x multiplexing
FD3 FD2 FD1 FD0 fLCD(Hz) Frame Rate (Hz) fLCD(Hz) Frame Rate (Hz) fLCD(Hz) Frame Rate (Hz)
4x multiplexing
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
256
170.7
128
102.4
85.3
73.1
64
128
85.3
64
512
170.7
113.8
85.3
68.3
56.9
48.8
42.7
37.9
34.1
31
512
128
85.3
64
341.3
256
341.3
256
51.2
42.7
36.6
32
204.8
170.7
146.3
128
204.8
170.7
146.3
128
51.2
42.7
36.6
32
56.9
51.2
46.5
42.7
39.4
36.6
34.1
32
28.5
25.6
23.25
21.35
19.7
18.3
17.05
16
113.8
102.4
93.1
85.3
78.8
73.1
68.3
64
113.8
102.4
93.1
85.3
78.8
73.1
68.3
64
28.5
25.6
23.25
21.35
19.7
18.3
17.05
16
28.4
26.3
24.4
22.8
21.3
10.7
16
8
32
32
8
Rev. PrE | Page 95 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Table 80. LCD frame rate selection for fLCDCLK=128Hz (LCDCON[3]=1)
2x multiplexing
3x multiplexing
4x multiplexing
FD3 FD2 FD1 FD0 fLCD(Hz) Frame Rate (Hz) Frame Rate (Hz) Frame Rate (Hz)
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
128
64
64
32
16
10.6
8
42.7
21.3
10.7
10.7
10.7
32
16
8
32
21.3
16
8
8
: Boxes shaded in grey are not within the range of typical LCD frame rates
Table 81. LCD Segment Enable SFR (LCDSEGE, 0x97)
Bit
Location
Bit
Mnemonic
FP25EN
Default
Value
Description
7
0
0
0
0
0
0
0
FP25 Function Select bit
0
1
General Purpose I/O
LCD Function
6
FP24EN
FP23EN
FP22EN
FP21EN
FP20EN
FDELAY
FP24 Function Select bit
0
1
General Purpose I/O
LCD Function
5
FP23 Function Select bit
0
1
General Purpose I/O
LCD Function
4
FP22 Function Select bit
0
1
General Purpose I/O
LCD Function
3
FP21 Function Select bit
0
1
General Purpose I/O
LCD Function
2
FP20 Function Select bit
0
1
General Purpose I/O
LCD Function
1-0
Delay before powerdown?
FDELAY[1:0]
0
0
1
1
0
1
0
1
No timeout
2 cycles
4 cycles
8 cycles
Table 82. LCD Pointer SFR (LCDPTR, 0xAC)
Bit
Location
Bit
Mnemonic
Default
Value
Description
Rev. PrE | Page 96 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
7
W/R
0
Read or Write LCD bit
If this bit is set, the data in LCDDAT will be written to the address
indicated by the bits LCDPTR[5 :0]
6
RESERVED
ADDRESS
0
0
Reserved
5-0
LCD Memory Address - See Table 85.
Table 83. LCD Data SFR (LCDDAT, 0xAE)
Bit
Location
7-0
Bit
Mnemonic
LCDDATA
Default
Value
Description
0
Data to be written into or read out of the LCD Memory SFRs.
Table 84. LCD Segment Enable 2 SFR (LCDSEGE2, 0xED)
Bit
Location
7-4
Bit
Mnemonic
RESERVED
Default
Value
Description
0
0
0
0
0
Reserved
3
2
1
0
FP19EN
FP18EN
FP17EN
FP16EN
FP19 Function Select bit
0
1
General Purpose I/O
LCD Function
FP18 Function Select bit
0
1
General Purpose I/O
LCD Function
FP17 Function Select bit
0
1
General Purpose I/O
LCD Function
FP16 Function Select bit
0
1
General Purpose I/O
LCD Function
Peripheral Configuration SFR (PERIPH, 0xF4)
Bit
Bit
Default
Description
Location Mnemonic
Value
7
6
RXFLAG
0
1
If set, indicates that a RX Edge event triggered wakeup from PSM2
Indicates the power supply that is connected internally to VSW.
0 VSW=VBAT
VSWSOURCE
1 VSW=VDD
5
4
3
VDD_OK
1
0
0
If set, indicates that VDD power supply is ok for operation
PLL_FLT
If set, indicates that PLL is not locked
REF_BAT_EN
If set, Internal voltage reference enabled in PSM2 mode. This bit should be set if LCD On in
PSM2 mode.
2
Reserved
0
1-0
RXPROG[1:0]
00
Controls the function of the P1.0/RX pin.
RXPROG [1:0] Function
0
0
1
0
1
1
GPIO
RX with wakeup disabled
RX with wakeup enabled
Rev. PrE | Page 97 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
multiplexing. There are fewer options available with
LCDCLK=128Hz, ranging from 8 to 32Hz for a 4x multiplexed
LCD. The 128Hz clock is beneficial for battery operation
because it consumes less power than the 2048Hz clock. The
frame rate is set by the FD[3:0] bits in the LCD Clock SFR
(LCDCLK, 0x96)—see Table 79 and Table 80.
LCD SETUP
f
The LCD Configuration SFR (LCDCON, 0x95) configures the
LCD module to drive the type of LCD in the user end system.
The BIAS and LMUX[1:0] bits in this SFR should be set
according to the LCD specifications.
The COM2/FP28 and COM3/FP27 pins default to LCD
segment lines. Selecting the 3x multiplex level in the LCD
Configuration SFR (LCDCON, 0x95) by setting LMUX[1:0] to
2d, changes the FP28 pin functionality to COM2. The 4x
multiplex level selection, LMUX[1:0]=3d, changes the FP28 pin
to COM2 and the FP27 pin to COM3.
The LCD waveform is inverted at twice the LCD waveform
frequency, fLCD. This way each frame has an average DC offset of
zero. ADC offset would degrade the lifetime and performance
of the LCD.
BLINK MODE
Blink mode is enabled by setting the BLINKEN bit in the LCD
Configuration SFR (LCDCON, 0x95). This mode is used to
alternate between LCD on and off states so that the LCD screen
appears to blink. There are two blinking modes: a software
controlled blink mode and an automatic blink mode.
LCD segments FP0-FP15 are enabled by default. Additional
pins are selected for LCD functionality in the LCD Segment
Enable SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR
(LCDSEGE2, 0xED) where there are individual enable bits for
segment pins FP16-25. The LCD pins do not have to be enabled
sequentially. For example, if the alternate function of FP23, the
timer 2 input, is required, then any of the other shared pins,
FP16-25, could be enabled instead.
Software Controlled Blink Mode
The LCD blink rate can be controlled by user code with the
BLKMOD[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96) by
toggling the bits to turn the display on and off at a rate
determined by the MCU code.
The Display Element Control section contains details about
setting up the LCD data memory to turn individual LCD
segments ON and OFF. Setting the LCDRST bit in the LCD
Configuration SFR (LCDCON, 0x95) will reset the LCD data
memory to its default, zero. A power on reset also clears the
LCD data memory.
Automatic Blink Mode
There are five blink rates available if the RTC peripheral is
enabled (enable the RTC by…xxx). These blink rates are
selected by the BLKMOD[1:0] and BLKFREQ[1:0] bits in the
LCD Clock SFR (LCDCLK, 0x96) – see Table 78.
LCD TIMING AND WAVEFORMS
An LCD segment acts like a capacitor that is charged and
discharged at a certain rate. The rate at which these capacitors
are charged and discharged, the refresh rate, determines the
visual characteristics of the LCD. A slow refresh rate will result
in the user being able to see the LCD blink on and off in
between refreshes. A fast refresh rate will present a screen that
appears to be lit up continuously. However, a faster refresh rate
consumes more power.
DISPLAY ELEMENT CONTROL
A bank of 15 bytes of data memory located in the LCD module
controls the on or off state of each segment of the LCD. The
LCD data memory is stored in addresses 0 through 14 in the
LCD module. Each byte configures the on and off states of two
segment lines. The LSBs store the state of the even numbered
segment lines and the MSBs store the state of the odd
numbered segment lines. For example, LCD data address zero
refers to segment lines one and zero—see Table 85. Note that
the LCD data memory is maintained in the PSM2 operating
mode.
The frame rate, or refresh rate, for the LCD module is derived
from the LCD clock, fLCDCLK. The LCD clock is selected as
2048Hz or 128Hz by the CLKSEL bit in the LCD Configuration
X SFR (LCDCONX, 0x9C). The minimum refresh rate that is
needed for the LCD to appear solid, without blinking, is
independent of the multiplex level.
Table 8ꢀ. LCD Data Memory accessed indirectly through
LCD Pointer SFR (LCDPTR, 0xAC) and LCD Data SFR
(LCDDAT, 0xAE)
COM3
COM2
COM1
COM0
COM3
COM2
COM1
COM0
LCD Memory
Address
The LCD waveform frequency, fLCD, is the frequency at which
the LCD switches which common line is active. Thus the LCD
waveform frequency depends heavily on the multiplex level.
The frame rate and LCD waveform frequency are set by fLCDCLK
the multiplex level and the FD[3:0] frame rate selection bits in
the LCD Clock SFR (LCDCLK, 0x96).
FP28
FP26
FP24
FP22
FP20
FP28
FP26
FP24
FP22
FP20
FP28
FP26
FP24
FP22
FP20
FP28
FP26
FP24
FP22
FP20
0Eh
0Dh
0Ch
0Bh
0Ah
,
FP27
FP25
FP23
FP21
FP27
FP25
FP23
FP21
FP27
FP25
FP23
FP21
FP27
FP25
FP23
FP21
The LCD module provides 16 different frame rates for
fLCDCLK=2048Hz, ranging from 8 to 128Hz for an LCD with 4x
Rev. PrE | Page 98 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
VOLTAGE GENERATION
FP19
FP17
FP15
FP13
FP11
FP9
FP19
FP17
FP15
FP13
FP11
FP9
FP19
FP17
FP15
FP13
FP11
FP9
FP19
FP17
FP15
FP13
FP11
FP9
FP18
FP16
FP14
FP12
FP10
FP8
FP18
FP16
FP14
FP12
FP10
FP8
FP18
FP16
FP14
FP12
FP10
FP8
FP18
FP16
FP14
FP12
FP10
FP8
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
The ADE75XX/ADE71XX provides two ways to generate the
LCD waveform voltage levels. The on-chip charge pump option
can generate 5V. This makes it possible to use 5V LCDs with the
3.3V ADE75XX/ADE71XX. There is also an option to use an
external resistor ladder with a 3.3V LCD. The EXTRES bit in
the LCD Configuration X SFR (LCDCONX, 0x9C) selects the
resistor ladder or charge pump option.
FP7
FP7
FP7
FP7
FP6
FP6
FP6
FP6
When selecting how to generate the LCD waveform voltages,
the following should be considered:
FP5
FP5
FP5
FP5
FP4
FP4
FP4
FP4
FP3
FP3
FP3
FP3
FP2
FP2
FP2
FP2
•
•
•
Power Consumption
Contrast Control
FP1
FP1
FP1
FP1
FP0
FP0
FP0
FP0
COM# designates the common lines
FP# designates the segment lines
Lifetime Performance
Power Consumption
The LCD data memory is accessed indirectly through the LCD
Pointer SFR (LCDPTR, 0xAC)and Table 83. LCD Data SFR
(LCDDAT, 0xAE). Moving a value to the LCD Pointer SFR
(LCDPTR, 0xAC) selects the LCD data byte to be accessed and
initiates a read or write operation—see Table 82.
In most LCDs, a high amount of current is required when the
LCD waveforms change state. The external resistor ladder
option draws a constant amount of current whereas the charge
pump circuitry allows dynamic current consumption. If the
LCD module is used with the internal charge pump option,
when the display is disabled, the voltage generation is disabled,
so that no power is consumed by the LCD function. This feature
will result in significant power savings if the display is turned
off in battery operation.
Writing to LCD Data registers
To update the LCD data memory, first set the LSB of the LCD
Configuration Y SFR (LCDCONY, 0xB1) to freeze the data
being displayed on the LCD while updating it. Then, move the
data to the LCD Data SFR (LCDDAT, 0xAE) prior to accessing
the LCD Pointer SFR (LCDPTR, 0xAC). When the MSB of the
LCD Pointer SFR (LCDPTR, 0xAC) is set, the content of the
LCD Data SFR (LCDDAT, 0xAE) is transferred to the internal
LCD data memory designated by the address in the LCD
Pointer SFR (LCDPTR, 0xAC). Clear the LSB of the LCD
Configuration Y SFR (LCDCONY, 0xB1) when all of the data
memory has been updated to allow to use the new LCD set up
for display.
Contrast control
The electrical characteristics of the liquid in the LCD change
over temperature, requiring adjustments in the LCD waveform
voltages to ensure a readable display. An added benefit of the
internal charge pump voltage generation is a configurable bias
voltage that can be compensated over temperature to maintain
contrast on the LCD. These compensations can be performed
based on the ADE75XX/ADE71XX temperature
measurements—see the Temperature, Battery and External
Voltage Measurements section. This dynamic contrast control is
not easily implemented with external resistor ladder voltage
generation.
Sample 8052 code to update the segments attached to pins FP10
and FP11 on is shown below:
ORL
MOV LCDDATA,#FFh
MOV LCDPTR,#80h OR 05h
LCDCONY,#01h
; start updating the data
The LCD bias voltage sets the contrast of the display when the
charge-pump provides the LCD waveform voltages. The
ADE75XX/ADE71XX provides 64 bias levels selectable using
the BLVL bits in the LCD Configuration X SFR (LCDCONX,
0x9C). The voltage level on LCDVA, LCDVB and LCDVC
depend on the the Interntal voltage reference value (Vref),
BLVL[5:0] selection and the biasing selected as described in
Table 76.
ANL
LCDCONY,#0FEh ; update finished
Reading LCD Data registers
When the MSB of the LCD Pointer SFR (LCDPTR, 0xAC) is
cleared, the content of the LCD Data memory address
designated by LCDPTR are transferred to the LCD Data SFR
(LCDDAT, 0xAE).
Sample 8052 code to read the contents of LCD data memory
address 07h, which holds the on and off state of the segments
attached to FP14 and FP15, is shown below:
Lifetime Performance
DC offset on a segment will degrade its performance over time.
The voltages generated through the internal charge pump
MOV LCDPTR,#NOT 80h AND 07h
MOV R1, LCDDATA
Rev. PrE | Page 99 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
switch faster than those generated by the external resistor
ladder, reducing the likelihood of a DC voltage being applied to
a segment and increasing the lifetime of the LCD.
LCD FUNCTION IN PSM2
The LCDPSM2 bit in the LCD Configuration SFR (LCDCON,
0x95) and the LCDEN bit in the LCD Configuration SFR
(LCDCON, 0x95) control LCD functionality in the PSM2
operating mode. The voltage reference must be enabled during
battery mode for the charge pump voltage generation to work.
Ensure this by setting REF_BAT_EN in the Peripheral
Configuration SFR (PERIPH, 0xF4).
LCD EXTERNAL CIRCUITRY
The voltage generation selection is made by bit EXTRES in the
LCD Configuration X SFR (LCDCONX, 0x9C). This bit is clear
by default for charge pump voltage generation but can be set to
enable an external resistor ladder.
LCDPSM2
LCDEN
Comments
Charge Pump:
0
0
The display is OFF in PSM2.
Voltage generation through the charge pump requires external
capacitors to store charge. The external connections to VA, VB,
and VC as well as VP1 and VP2 are shown in LCD
Configuration X SFR (LCDCONX, 0x9C).
0
1
1
The display is ON in PSM2.
The display is OFF in PSM2.
X
Note that the LCD configuration and data memory is retained
when the display is turned off.
LCDVC
470nF
LCDVB
470nF
EXAMPLE LCD SETUP
LCDVA
An example to set up the LCD peripheral for a specific LCD is
described below.
470nF
Charge Pump
LCDVP1
100nF
and
Type of LCD: 5V, 4x multiplexed with 1/3 bias, 96 segments
Voltage Generation: Internal Charge Pump
Refresh Rate: 64Hz
LCDVP2
LCD Waveform
Circuitry
A 96 segment LCD with 4x multiplexing requires 96/4=24
segment lines. There are 16 pins that automatically dedicated
for use as LCD segments, FP0 to FP15. Eight more pins must be
chosen for the LCD function. Since the LCD has 4x
multiplexing, all four common lines are used so COM2/FP28
and COM3/FP27 cannot be utilized as segment lines. Based on
the alternate functions of the pins used for FP16 through FP25,
FP16-23 are chosen for the seven remaining segment lines.
These pins will be enabled for LCD functionality in the LCD
Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment
Enable 2 SFR (LCDSEGE2, 0xED).
Figure 63: External circuitry for Charge Pump option
External Resistor Ladder:
To enable the external resistor ladder option, set the EXTRES
bit in the LCD Configuration X SFR (LCDCONX, 0x9C). When
EXTRES=1, the LCD waveform voltages are supplied by the
external resistor ladder. Since the LCD voltages are not being
generated on-chip, the LCD bias compensation implemented to
maintain contrast over temperature and supply is not possible.
The external circuitry needed for the resistor ladder option is
shown in Figure 64. The resistors required should be in the
range of 10k to 100k and based on the current required by the
LCD being used.
To determine contrast setting for this 5V LCD, look in Table 76
to find the BIASLVL[5:0] setting that corresponds to a VC of 5V
in 1/3 Bias Mode. The nominal bias level setting for this LCD is
BIASLVL[5:0]=[111111].
LCDVC
LCDVB
LCDVA
The LCD is setup with the following 8052 code:
; setup LCD pins to have LCD functionality
MOV
MOV
LCDSEGE, # 00111100b
LCDSEGE2, #00001111b
LCD Waveform
LCDVP1
; setup LCDCON for fLCDCLK=2048Hz, 1/3 bias and 4x multiplexing
MOV LCDCON, #00000111b
; setup LCDCONX for charge pump and BIASLVL[110111]
MOV LCDCONX, #00110111b
; set up refresh rate for 64Hz with fLCDCLK=2048Hz, from Table 79
MOV LCDCLK, #00000011b
Circuitry
LCDVP2
; set up LCD data registers with data to be displayed using
; LCDPTR and LCDDATA registers
Figure 64: External circuitry for External Resistor Ladder option
Rev. PrE | Page 100 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
; turn all segments on FP25 ON and FP26 OFF
ORL
MOV
MOV
ANL
ORL
LCDCONY,#01h
LCDDAT, #F0H
LCDPTR, #80h OR 0DH
LCDCONY,#0FEh
LCDCON,#080h ; enable LCD
; start data memory refresh
; end of data memory refresh
To setup the same 3.3V LCD for use with an external resistor
ladder:
; setup LCD pins to have LCD functionality
MOV
MOV
LCDSEGE, # 00111100b
LCDSEGE2, #00001111b
; setup LCDCON for fLCDCLK=2048Hz, 1/3 bias and 4x multiplexing
MOV LCDCON, #00000111b
; setup LCDCONX for external resistor ladder
MOV LCDCONX, #01000000b
; set up refresh rate for 64Hz with fLCDCLK=2048Hz, from Table 79
MOV LCDCLK, #00000011b
; set up LCD data registers with data to be displayed using
; LCDPTR and LCDDATA registers
; turn all segments on FP25 ON and FP26 OFF
ORL
MOV
MOV
ANL
ORL
LCDCONY,#01h
LCDDAT, #F0H
LCDPTR, #80h OR 0DH
LCDCONY,#0FEh
LCDCON,#080h ; enable LCD
; start data memory refresh
; end of data memory refresh
Rev. PrE | Page 101 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
supply and temperature of 100,000 cycles, with a minimum
endurance figure of 20,000 cycles of operation at 25°C.
FLASH MEMORY
FLASH MEMORY OVERVIEW
Retention is the ability of the Flash memory to retain its
programmed data over time.Again, the parts have been qualified
in accordance with the formal JEDEC Retention Lifetime
Specification (A117) at a specific junction temperature (TJ =
55°C). As part of this qualification procedure, the Flash memory
is cycled to its specified endurance limit described previously,
before data retention is characterized. This means that the Flash
memory is guaranteed to retain its data for its full specified
retention lifetime every time the Flash memory is
Flash memory is a type of non-volatile memory that is in-
circuit programmable. The default, erased, state of a byte of
flash memory is 0xFF. When a byte of flash memory is
programmed, the required bits change from one to zero. The
flash memory must be erased to turn the zeros back to ones.
However, a byte of flash memory cannot be erased individually.
The entire segment, or page, of flash memory that contains the
byte must be erased.
reprogrammed. It should also be noted that retention lifetime,
based on an activation energy of 0.6 eV, derates with TJ as shown
in Figure 65.
The ADE75XX/ADE71XX provides 8 or 16kbytes of flash
program/information memory. This memory is segmented into
32 pages of 512 bytes each. So, to reprogram one byte of flash
memory, the 511 bytes in that page must be erased. The flash
memory can be erased by page or all at once in a mass erase.
There is a command to verify that a flash write operation has
completed successfully. The ADE75XX/ADE71XX flash
memory controller also offers configurable flash memory
protection.
300
250
200
ADI SPECIFICATION
100 YEARS MIN.
AT T = 55°C
J
150
100
50
The 8 or 16 kbytes of flash memory are provided on-chip to
facilitate code execution without any external discrete ROM
device requirements. The program memory can be programmed
in-circuit, using the serial download mode provided or using
conventional third party memory programmers.
0
40
50
60
70
80
90
100
110
Flash/EE Memory Reliability
T
JUNCTION TEMPERATURE (°C)
J
The Flash memory arrays on the ADE75XX/ADE71XX are fully
qualified for two key Flash/EE memory characteristics:
Flash/EE memory cycling endurance and Flash/EE memory
data retention.
Figure 65. Flash/EE Memory Data Retention
FLASH MEMORY ORGANIZATION
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of four
independent, sequential events:
The 8 or 16kbytes of flash memory provided by the
ADE75XX/ADE71XX are segmented into 32 pages of 512 bytes
each. It is up to the user to decide which Flash memory he
would like to allocate for data memory. It is recommended that
each page be dedicated solely to program or data memory so
that an instance does not arise where the program counter is
loaded with data memory instead of an opcode from the
program memory or where program memory is erased to
update a byte of data memory.
1. Initial page erase sequence
2. Read/verify sequence
3. Byte program sequence
4. Second read/verify sequence
In reliability qualification, every byte in both the program and
data Flash/EE memory is cycled from 00H to FFH until a first
fail is recorded, signifying the endurance limit of the on-chip
Flash/EE memory.
As indicated in the specification table, the ADE75XX/ADE71XX
flash memory endurance qualification has been carried out in
accordance with JEDEC Specification A117 over the industrial
temperature range of –40°C, +25°C and +85°C. The results
allow the specification of a minimum endurance figure over
Rev. PrE | Page 102 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
0x3FFF
0x1FFF
USING THE FLASH MEMORY
PAGE 31
PAGE 30
PAGE 29
PAGE 28
PAGE 27
PAGE 26
PAGE 25
PAGE 24
PAGE 23
PAGE 22
PAGE 21
PAGE 20
PAGE 19
PAGE 18
PAGE 17
PAGE 16
PAGE 15
PAGE 14
PAGE 13
PAGE 12
PAGE 11
PAGE 10
PAGE 9
PAGE 8
PAGE 7
PAGE 6
PAGE 5
PAGE 4
PAGE 3
PAGE 2
PAGE 1
PAGE 0
0x3E00
0x3DFF
0x1E00
0x1DFF
The 8k or 16 kbytes of Flash memory are configured as 16 or 32
pages, each of 512 bytes. As with the other
ADE75XX/ADE71XX peripherals, the interface to this memory
space is via a group of registers mapped in the SFR space – see .
A data register, EDATA, holds the byte of data to be accessed.
The byte of flash memory is addressed via the EADRH and
EADRL registers. The Flash SFRs
READ
PROTECT
BIT 7
READ
PROTECT
BIT 3
0x3C00
0x3BFF
0x1C00
0x1BFF
0x3A00
0x39FF
0x1A00
0x19FF
0x3800
0x37FF
0x1800
0x17FF
0x3600
0x35FF
0x1600
0x15FF
READ
PROTECT
BIT 6
READ
PROTECT
BIT 2
0x3400
0x33FF
0x1400
0x13FF
Table 86. Flash SFRs
0x3200
0x31FF
0x1200
0x11FF
SFR
Address Default Bit
Description
Value
Addressable
0x3000
0x2FFF
0x1000
0x0FFF
ECON
0xB9
0x00
No
Flash
0x2E00
0x2DFF
0x0E00
0x0DFF
Control
Flash Key
Flash
Protection
Key
READ
PROTECT
BIT 5
READ
PROTECT
BIT 1
0x2C00
0x2BFF
0x0C00
0x0BFF
FLSHKY
PROTKY
0xBA
0xBB
0xFF
0xFF
No
No
0x2A00
0x29FF
0x0A00
0x09FF
0x2800
0x27FF
0x0800
0x07FF
0x2600
0x25FF
0x0600
0x05FF
EDATA
0xBC
0xBD
0x00
0xFF
No
No
Flash Data
READ
PROTECT
BIT 4
READ
PROTECT
BIT 0
0x2400
0x23FF
0x0400
0x03FF
PROTB0
Flash W/E
Protection 0
0x2200
0x21FF
0x0200
0x01FF
PROTB1
PROTR
EADRL
EADRH
0xBE
0xBF
0xC6
0xC7
0xFF
0xFF
0x00
0x00
Flash W/E
Protection 1
No
No
0x2000
0x0000
CONTAINS
PROTECTION
SETTINGS
Flash Read
protection
Figure 66: Flash Memory Organization
No
No
Flash Low
address
The flash memory can be protected from read or write/erase
access. The protection is implemented in part of the last page of
the flash memory, Page 31. Four of the bytes from this page are
used to set up write/erase protection for each of the pages.
Another byte is used for configuring read protection of the flash
memory. The read protection is selected for groups of four
pages. Finally, there is a byte used to store the key required for
modifying the protection scheme. If any code protection is
required, the last page of flash memory must be write/erase
protected at a minimum. The implication of write/erase
protecting the last page is that the content of the 506 bytes in
this page that are available to the user must not change.
Flash High
address
Finally, ECON is an 8-bit control register that can be written to
with one of seven Flash memory access commands to trigger
various read, write, erase, and verify functions. Figure 67
demonstrates the steps required for access to the flash memory.
ECON
Command
Address
PROTECTION
DECODER
ADDRESS
DECODER
ACCESS
ALLOWED?
EADRH EADRL
TRUE: ACCESS ALLOWED
ECON=0
Thus it is recommended that if code protection is enabled, this
last page should be used for program memory only if the
firmware does not need to be updated in the field. If the
firmware must be protected and can be updated at a future date,
the last page should be used only for constants used by the
program code that will not need to be read during emulation or
debug.
Flash Protection Key
FLSHKY
FALSE: ACCESS DENIED
ECON=1
FLSHKY=0x3B?
Figure 67: Flash Memory Read/Write/Erase Protection Block Diagram
ECON—Flash/EE Memory Control SFR
Therefore, Pages 0 through 30 are for general program and data
memory use. It is recommended that Page 31 is used for
constants or code that will not need to be updated. Note that the
last 6 bytes of Page 31 are reserved for protecting the flash
memory.
Programming Flash memory is done through the Flash
memory control Flash Control SFR (ECON, 0xB9). This SFR
allows the user to read, write, erase, or verify the 16 or 32 kbytes
of Flash memory. As a method of security, a key must be
written to the FLSHKY register to initiate any user access to the
Rev. PrE | Page 103 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
flash memory. Upon completion of the flash memory operation,
the FLSHKY register is reset such that it must be written prior
to another flash memory operation. Requiring the key to be set
before an access to the flash memory decreases the likelihood of
user code or data being overwritten by a program that has run
amuck.
done performing the requested operation. Then the PC
increments to continue with the next instruction. Any
interrupts requests that occur while the flash controller is
performing an operation are not handled until the flash
operation is complete. All peripherals, such as timers and
counters, will continue to operate as configured throughout the
flash memory access.
The program counter, PC, is held on the instruction where the
ECON register is written to until the flash memory controller is
Table 87. Flash Control SFR (ECON, 0xB9)
Bit
Location
7-0
Bit
Mnemonic
ECON
Default
Value
Description
0
1
2
3
Write byte: The value in EDATA is written to the Flash memory, at
the page address given by EADRH and EARDL. Note that the byte
being addressed must be pre-erased
Erase page: A 512-byte page of Flash memory address is erased.
The page is selected by the address in EADRH/L. Any address in
the page can be written to EADRH/L to select it for erasure.
Erase all: All 16 or 32kbytes of the Flash memory are erased.
Note: This command is used during serial and parallel download
modes but should not be executed by user code.
4
5
Read byte: The byte in the Flash memory, addressed by
EADRH/L, is read into EDATA.
Erase page and write byte: The page that holds the byte
addressed by EADRH/L is erased. Then, data in EDATA is written
to the byte of flash memory addressed by EADRH/L.
8
Protect code: See Protecting the Flash.
Table 88. Flash Key SFR (FLSHKY, 0xBA)
Bit
Location
7-0
Bit
Mnemonic
FLSHKY
Default
Value
Description
0xFF
The content of this SFR is compared to the Flash key – 0x3B. If the two
values match the next ECON operation is allowed - see Protecting the
Flash.
Table 89. Flash Protection Key SFR (PROTKY, 0xBB)
Bit
Location
7-0
Bit
Mnemonic
PROTKY
Default
Value
Description
0xFF
The content of this SFR is compared to the Flash memory location at
address 0x3FFA. If the two values match, the update of the Write/Erase
and Read protection set up is allowed - see Protecting the Flash.
If the protection Key in the flash is 0xFF, PROTKY SFR value is not used for
comparison. The PROTKY SFR is also used to write the protection key in
the flash. This is done by writing the desired value in PROTKY and write
0x08 in the ECON SFR. This operation can only be done once.
Table 90. Flash Data SFR (EDATA, 0xBC)
Bit
Location
7-0
Bit
Mnemonic
EDATA
Default
Value
Description
0
Flash pointer data
Table 91. Flash Write/Erase Protection 0 SFR (PROTB0, 0xBD)
Bit Bit Default Description
Rev. PrE | Page 104 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Value
Location
Mnemonic
7-0
PROTB0
0xFF
This SFR is used to write the write/erase protection bits for pages 0 to 7 of
the Flash memory – see Protecting the Flash. Clearing the bit enables the
protection.
PROTB0.7: Page 7
PROTB0.6: Page 6
PROTB0.5: Page 5
PROTB0.4: Page 4
PROTB0.3: Page 3
PROTB0.2: Page 2
PROTB0.1: Page 1
PROTB0.0: Page 0
Table 92. Flash Write/Erase Protection 1 SFR (PROTB1, 0xBE)
Bit
Location
7-0
Bit
Mnemonic
PROTB1
Default
Value
Description
0xFF
This SFR is used to write the write/erase protection bits for pages 8 to 15 of
the Flash memory – see Protecting the Flash. Clearing the bit enables the
protection.
PROTB1.7: Page 15
PROTB1.6: Page 14
PROTB1.5: Page 13
PROTB1.4: Page 12
PROTB1.3: Page 11
PROTB1.2: Page 10
PROTB1.1: Page 9
PROTB1.0: Page 8
Table 93. Flash Read Protection SFR (PROTR, 0xBF)
Bit
Location
7-0
Bit
Mnemonic
PROTR
Default
Value
Description
0xFF
This SFR is used to write the read protection bits for pages 0 to 31 of the
Flash memory – see Protecting the Flash. Clearing the bit enables the
protection.
PROTR.7: Page 28 to 31
PROTR.6: Page 24 to 27
PROTR.5: Page 20 to 23
PROTR.4: Page 16 to 19
PROTR.3: Page 12 to 15
PROTR.2: Page 8 to 11
PROTR.1: Page 4 to 7
PROTR.0: Page 0 to 3
Table 94. Flash Low Byte Address SFR (EADRL, 0xC6)
Bit
Location
7-0
Bit
Mnemonic
EADRL
Default
Value
Description
0
Flash pointer low byte address
This SFR is also used to write the write/erase protection bits for pages 16
to 23 of the Flash memory – see Protecting the Flash. Clearing the bit
enables the protection.
EADRL.7: Page 23
EADRL.6: Page 22
EADRL.5: Page 21
Rev. PrE | Page 105 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
EADRL.4: Page 20
EADRL.3: Page 19
EADRL.2: Page 18
EADRL.1: Page 17
EADRL.0: Page 16
Table 9ꢀ. Flash High Byte Address SFR (EADRH, 0xC7)
Bit
Location
7-0
Bit
Mnemonic
EADRH
Default
Value
Description
0
Flash pointer high byte address
This SFR is also used to write the write/erase protection bits for pages 24
to 31 of the Flash memory – see Protecting the Flash. Clearing the bit
enables the protection.
EADRH.7: Page 31
EADRH.6: Page 30
EADRH.5: Page 29
EADRH.4: Page 28
EADRH.3: Page 27
EADRH.2: Page 26
EADRH.1: Page 25
EADRH.0: Page 24
MOV ECON, #04H
; Data is ready in EDATA register
; Read Byte
Flash functions
Sample 8051 code is provided below to demonstrate how to use
the Flash functions. For these examples, the byte of flash
memory, 0x3C00 is accessed.
Erase Page and Write Byte: Erase the page containing flash
memory byte 0x3C00 and then write F3H to that address. Note
that the other 511 bytes in this page will be erased.
Write Byte: Write F3H into flash memory byte 0x3C00.
MOV EDATA, #F3h
MOV EADRH, #3Ch
MOV EADRL, #00h
MOV FLSHKY, #3Bh
MOV ECON, #01H
; Data to be written
; Setup byte address
MOV EDATA, #F3h
MOV EADRH, #3Ch
MOV EADRL, #00h
MOV FLSHKY, #3Bh
MOV ECON, #05H
; Data to be written
; Setup byte address
; Write Flash security key.
; Write Byte
; Write Flash security key.
; Erase page and then write byte
PROTECTING THE FLASH
Erase Page: Erase the page containing flash memory byte
Two forms of protection are offered for this flash memory: read
protection and write/erase protection. The read protection
ensures that any pages that are read protected will not be able to
be read by the end user. The write protection ensures that the
flash memory cannot be erased or written over. This protects
the end system from tampering and can prevent the code from
being overwritten in the event of a runaway program.
0x3C00.
MOV EADRH, #3Ch
MOV EADRL, #00h
MOV FLSHKY, #3Bh
MOV ECON, #02H
; Select page through byte address
; Write Flash security key.
; Erase Page
Erase All: Erase all of the 16 or 32kbyte flash memory
Write/erase protection is individually selectable for all of the 16
or 32 pages. Read protection is selected in groups of 4 pages. See
Figure 66 for the groupings. The protection bits are stored in the
last flash memory locations, addresses 0x3FFA through
0x3FFF– see Figure 68. 4 bytes are reserved for write/erase
protection, 1 byte for read protection and another byte to set the
protection security key. The user must enable write/erase
protection for the last page at a minimum for the entire
protection scheme to work.
MOV FLSHKY, #3Bh
MOV ECON, #03H
; Write Flash security key.
; Erase All
Read Byte: Read flash memory byte 0x3C00.
MOV EADRH, #3Ch
MOV EADRL, #00h
MOV FLSHKY, #3Bh
; Setup byte address
; Write Flash security key.
Rev. PrE | Page 106 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Remark: The read protection does not prevent MOVC
commands from being executed within the code.
Note that once the protection key is configured, it
cannot be modified. Also note that the most
significant bit of 0x3FFA is used to enable a lock
mechanism for the watchdog settings—see the
Watchdog Timer section for more information.
There is an additional layer of protection offered by a protection
security key. The user can setup a protection security key so that
the protection scheme cannot be changed without this key.
Once the protection key has been configured, it may not be
modified.
4. Run the protection command by writing 08H to the
ECON register.
Enabling Flash Protection by Code
5. Reset the chip to activate the new protection.
The protection byts in the Flash can be programmed using
Flash controller command and programming ECON to 0x08.
The EADRH, EADRL, PROTB1 and PROTB0 bytes are used in
this case to store the data to be written to the 32 bits of write
protection. Note that the EADRH and EADRL registers are not
used as data pointers here, but to store write protection data.
To enable read and write/erase protection for the last page only,
use the following 8051 code. Writing the flash protection
command to the ECON register initiates programming the
protection bits in the flash.
; enable write/erase protection on the last page only
MOV EADRH, #07FH
MOV EADRL, #0FFH
MOV PROTB1, #FFH
MOV PROTB0, #FFH
WP WP WP WP WP WP WP WP
EADRH
31
WP WP WP WP WP WP WP WP
23 22 21 20
19 18 17 16
WP WP WP WP WP WP WP WP
15 14 13 12
11 10
WP WP WP WP WP WP WP WP
30
29
28
27
26
25
24
0x3FFF
0x3FFE
0x3FFD
EADRL
PROTB1
9
9
; enable read protection on the last four pages only
MOV PROTR, #07FH
PROTB0
7
6
5
4
3
2
1
0
0x3FFC
0x3FFB
RP
RP
RP
RP
RP
RP
RP
RP
3-0
PROTR
31-28 27-24 23-20 19-16 15-12 11-8 7-4
; set up a protection key of 0A3H. This command can be
; omitted to use the default protection key of 0xFF
MOV PROTKY, #0A3H
WDOG
LOCK
PROTECTION KEY[7:0]
PROTKY
0x3FFA
0x3FF9
; write the flash key to the FLSHKY register to enable flash
; access. The flash access key is not configurable.
MOV FLSHKY, #3BH
0x3E00
Figure 68: Flash Protection in Page 31
; write flash protection command to the ECON register
MOV ECON, #08H
The sequence for writing the protection bits is:
1. Set up the EADRH, EADRL, PROTB1 and PROTB0
registers with the write/erase protection bits. When
erased, the protection bits default to 1, like any other
bit of Flash memory. The default protection setting is
for no protection. To enable protection, write a 0 to the
bits corresponding to the pages that should be
protected.
Enabling Flash Protection by emulator
commands
Another way to set the Flash protection bytes is to use some
reserved emulator commands available only in download mode.
These commands write directly to the SFRs and can be used to
duplicate the operation mentioned in the Enabling Flash
Protection by Code paragraph. Once these Flash bytes are
written, the part can exit emulation mode by reset and the
protections will be effective. This method can be used in
production and implemented after downloading the program.
The commands used for this operation are an extension of the
commands listed in the application note uC004 –
2. Set up the PROTR register with the read protection
bits. Note that every read protection bit protects four
pages. To enable the read protection bit, write a 0 to
the bits that should be read protected.
3. To enable the protection key, write to the PROTKY
register. If enabled, the protection key will be required
to modify the protection scheme. The protection key,
flash memory address 0x3FFA defaults to FFH so if
the PROTKY register is not written to, it will remain
0xFFH. If the protection key is written to, the
Understanding the Serial Download Protocol:
- Command with ASCII code ‘I’ or 0x49 write the data into R0
- Command with ASCII code ‘F’ or 0x46 write R0 into the SFR
address defined in the data of this command
PROTKY register must be written with this value
every time the protection functionality is accessed.
Omitting the protocol defined in uC004, the sequence to load
Rev. PrE | Page 107 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
protections are similar to the sequence presented mentioned in
the Enabling Flash Protection by Code paragraph.except that
two emulator commands are necessary to replace one assembly
command. For example to write the protection value in
EADRH the two following commands need to be executed:
requested flash memory operation is complete. In practice, this
means that even though the Flash operation is typically initiated
with a two-machine-cycle MOV instruction (to write to the
Flash Control SFR (ECON, 0xB9)), the next instruction is not
executed until the Flash/EE operation is complete. This means
that the core cannot respond to interrupt requests until the
Flash/EE operation is complete, although the core peripheral
functions such as counter/ timers continue to count as
configured throughout this period.
-
-
Command ‘I ‘ with Data = Value of protection byte 0x3FFF
Command ‘F’ with Data = 0xC7
Following this protocol, the protection can be written to the
Flash using the same sequence as mentioned in the Enabling
Flash Protection by Code paragraph. When the part is reset the
protection will be effective.
IN CIRCUIT PROGRAMMING
Serial Downloading
The ADE75XX/ADE71XX facilitates code download via the
standard UART serial port. The parts enter serial download
Notes on Flash Protection
mode after a reset or a power cycle if the
pin is pulled low
SDEN
The flash protection scheme is disabled by default so that none
of the pages of the flash are protected from reading or
writing/erasing.
through an external 1 kΩ resistor. Once in serial download
mode, the hidden embedded download kernel executes. This
allows the user to download code to the full 16 or 32 kbytes of
Flash memory while the device is in circuit in its target
application hardware.
The last page must be write/erase protected for the protection
scheme to work.
Protection configured in the last page of the
To activate the protection settings, the ADE75XX/ADE71XX
must be reset after configuring the protection.
ADE75xx/ADE71xx affects whether flash memory can be
accessed in serial download mode. Read protected pages cannot
be read. Write/erase protected pages cannot be written or
erased. The configuration bits cannot be programmed in serial
download mode.
After configuring protection on the last page and resetting the
part, protections that have been enabled can only be removed
by mass erasing the flash memory. The protection bits are read
and erase protected by enabling read and write/erase protection
the last page, but the protection bits are never truly write
protected. Protection bits can be programmed modified from a
1 to a 0, even after the last page has been protected. In this way,
more protection can be added but none can be removed.
The protection scheme is intended to protect the end system.
Protection should be disabled while developing and emulating
code.
Flash memory timing
Typical program and erase times for the flash memory are as
follows:
Command
Bytes Affected
1 byte
Flash Memory Timing
WRITE BYTE
ERASE PAGE
ERASEALL
30us
512 bytes
16 or 32kbytes
1 bytes
20ms
200ms
100ns
21ms
READ BYTE
ERASEPAGE and
WRITE BYTE
512 bytes
VERIFY BYTE
1 byte
100ns
Note that the core microcontroller operation is idled until the
Rev. PrE | Page 108 of 148
Preliminary Technical Data
TIMERS
ADE75xx/ADE71xx
When functioning as a counter, the TLx register is incremented
by a 1-to-0 transition at its corresponding external input pin:
T0, T1, or T2. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. Because it takes
two machine cycles (two core clock periods) to recognize a
1-to-0 transition, the maximum count rate is half the core clock
frequency.
The ADE75XX/ADE71XX has three 16-bit timer/ counters:
Timer 0, Timer 1, and Timer 2. The timer/counter hardware is
included on-chip to relieve the processor core of the overhead
inherent in implementing timer/counter functionality in
software. Each timer/counter consists of two 8-bit registers:
THx and TLx (x = 0, 1, or 2). All three can be configured to
operate either as timers or as event counters.
There are no restrictions on the duty cycle of the external input
signal, but, to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via the SFRs in Table 96.
When functioning as a timer, the TLx register is incremented
every machine cycle. Thus, one can think of it as counting
machine cycles. Because a machine cycle on a single-cycle core
consists of one core clock period, the maximum count rate is
the core clock frequency.
Table 96. Timer SFRs
SFR
Address Bit Addressable Description
TCON
TMOD
TL0
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0xC8
Yes
No
No
No
No
No
Yes
No
No
No
No
Timer0 and Timer1 Control Register – see Table 98
Timer Mode register– see Table 97
Timer0 LSB– see Table 101
TL1
Timer1 LSB– see Table 103
TH0
Timer0 MSB– see Table 100
TH1
Timer1 MSB– see Table 102
T2CON
Timer2 Control Register – see Table 99
Timer2 Reload/Capture LSB – see Table 107
Timer2 Reload/Capture MSB – see Table 106
Timer2 LSB – see Table 105
RCAP2L 0xCA
RCAP2H 0xCB
TL2
0xCC
0xCD
TH2
Timer2 MSB – see Table 104
TIMER SFR REGISTER LIST
Table 97. Timer/Counter 0 and 1 Mode SFR (TMOD, 0x89)
Bit
Location Mnemonic Value
Bit
Default
Description
7
Gate1
0
Timer 1 Gating Control.
Set by software to enable Timer/Counter 1 only while the INT1 pin is high and the TR1 control is
set.
Cleared by software to enable Timer 1 whenever the TR1control bit is set.
6
C_T1
0
Timer 1 Timer or Counter Select Bit.
Set by software to select counter operation (input from T1 pin).
Cleared by software to select the timer operation (input from internal system clock).
Timer 1 Mode Select bits
5-4
T1_M1,
T1_M0
00
M1
M0
Description
0
0
0
1
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
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ADE75xx/ADE71xx
Preliminary Technical Data
1
1
0
1
8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into
TL1 each time it overflows.
Timer/Counter 1 Stopped.
3
Gate0
C_T0
0
Timer 0 Gating Control.
Set by software to enable Timer/Counter 0 only while the INT0 pin is high and the TR0 control bit
is set.
Cleared by software to enable Timer 0 whenever the TR0 control bit is set.
2
0
Timer 0 Timer or Counter Select Bit.
Set by software to the select counter operation (input from T0 pin).
Cleared by software to the select timer operation (input from internal system clock).
Timer 0 Mode Select Bits
1-0
T0_M1,
T0_M0
00
M1
0
M0
0
Description
TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
0
1
1
0
8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into
TL0 each time it overflows.
1
1
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
Table 98. Timer/Counter 0 and 1 Control SFR (TCON, 0x88)
Bit
Location
Bit
Addr.
Bit
Name
Default
Value
Description
7
0x8F
TF1
0
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the program counter (PC) vectors to the interrupt service
routine.
6
5
4
3
0x8E
0x8D
0x8C
0x8B
TR1
TF0
TR0
IE11
0
0
0
0
Timer 1 Run Control Bit.
Set by the user to turn on Timer/Counter 1.
Cleared by the user to turn off Timer/Counter 1.
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
Timer 0 Run Control Bit.
Set by the user to turn on Timer/Counter 0.
Cleared by the user to turn off Timer/Counter 0.
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or by a zero level applied to the external interrupt pin,
INT1, depending on the state of Bit IT1.
Cleared by hardware when the PC vectors to the interrupt service routine only if the
interrupt was transition-activated. If level-activated, the external requesting source controls
the request flag rather than the on-chip hardware.
2
1
0x8A
0x89
IT11
IE01
0
0
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.
Cleared by software to specify level-sensitive detection, that is, zero level.
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or by a zero level being applied to the external interrupt
pin, INT0, depending on the statue of Bit IT0.
Cleared by hardware when the PC vectors to the interrupt service routine only if the
interrupt was transition-activated. If level-activated, the external requesting source controls
the request flag rather than the on-chip hardware.
0
0x88
IT01
0
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.
Cleared by software to specify level-sensitive detection, that is, zero level.
__________________________________________
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Preliminary Technical Data
ADE75xx/ADE71xx
INT0
INT1
interrupt pins.
2
These bits are not used to control Timer/Counters 0 and 1, but are used instead to control and monitor the external
and
Table 99. Timer/Counter 2 Control SFR (T2CON, 0xC8)
Bit
Location
Bit
Addr.
Bit
Name
Default
Value
Description
7
0xCF
TF2
0
Timer 2 Overflow Flag.
Set by hardware on a Timer 2 overflow. TF2 cannot be set when either RCLK = 1 or TCLK = 1.
Cleared by user software.
Timer 2 External Flag.
6
0xCE
EXF2
0
Set by hardware when either a capture or reload is caused by a negative transition on T2EX
and EXEN2 = 1.
Cleared by user software.
Receive Clock Enable Bit.
Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in
serial port Modes 1 and 3.
Cleared by the user to enable Timer 1 overflow to be used for the receive clock.
Transmit Clock Enable Bit.
Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in
serial port Modes 1 and 3.
5
4
3
0xCD
0xCC
0xCB
RCLK
TCLK
0
0
0
Cleared by the user to enable Timer 1 overflow to be used for the transmit clock.
Timer 2 External Enable Flag.
EXEN2
Set by the user to enable a capture or reload to occur as a result of a negative transition on
T2EX if Timer 2 is not being used to clock the serial port.
Cleared by the user for Timer 2 to ignore events at T2EX.
Timer 2 Start/Stop Control Bit.
Set by the user to start Timer 2.
2
1
0
0xCA
0xC9
0xC8
TR2
0
0
0
Cleared by the user to stop Timer 2.
CNT2
CAP2
Timer 2 Timer or Counter Function Select Bit.
Set by the user to select the counter function (input from external T2 pin).
Cleared by the user to select the timer function (input from on-chip core clock).
Timer 2 Capture/Reload Select Bit.
Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1.
Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at
T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is
forced to autoreload on Timer 2 overflow.
Table 100. Timer 0 High byte SFR (TH0, 0x8C)
Bit
Location
7-0
Bit
Mnemonic
TH0
Default
Value
Description
0
Timer 0 Data high byte
Table 101. Timer 0 Low byte SFR (TL0, 0x8A)
Bit
Location
7-0
Bit
Mnemonic
TL0
Default
Value
Description
0
Timer 0 Data high byte
Table 102. Timer 1 High byte SFR (TH1, 0x8D)
Bit Location
Bit Mnemonic
Default
Value
Description
7-0
TH1
0
Timer 1 Data high byte
Table 103. Timer 1 Low byte SFR (TL1, 0x8B)
Bit Location
Bit Mnemonic
Default
Value
Description
7-0
TL1
0
Timer 1 Data high byte
Rev. PrE | Page 111 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Table 104. Timer 2 High byte SFR (TH2, 0xCD)
Bit Location
Bit Mnemonic
Default
Value
Description
7-0
TH2
0
Timer 2 Data high byte
Table 10ꢀ. Timer 2 Low byte SFR (TL2, 0xCC)
Bit Location
Bit Mnemonic
Default
Value
Description
7-0
TL2
0
Timer 2 Data high byte
Table 106. Timer 2 Reload/capture High byte SFR (RACP2H, 0xCB)
Bit Location
Bit Mnemonic
Default
Value
Description
7-0
TH2
0
Timer 2 Reload/capture high byte
Table 107. Timer 2 Reload/capture Low byte SFR (RACP2L, 0xCA)
Bit Location
Bit Mnemonic
Default
Value
Description
7-0
TL2
0
Timer 2 Reload/capture low byte
As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag, TF0. TF0 can then be used to request an interrupt.
The counted input is enabled to the timer when TR0 = 1 and
TIMER 0 AND TIMER 1
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers: Timer 0 High byte
SFR (TH0, 0x8C), Timer 0 Low byte SFR (TL0, 0x8A), Timer 1
High byte SFR (TH1, 0x8D) and Timer 1 Low byte SFR (TL1,
0x8B) These can be used as independent registers or combined
into a single 16-bit register, depending on the timers’ mode
configuration – see Table 100 to Table 103.
either Gate = 0 or
= 1. Setting Gate = 1 allows the timer to
INT0
be controlled by external input
to facilitate pulse-width
INT0
measurements. TR0 is a control bit in the Timer/Counter 0 and
1 Control SFR (TCON, 0x88); the Gate bit is in Timer/Counter
0 and 1 Mode SFR (TMOD, 0x89). The 13-bit register consists
of all 8 bits of Timer 0 High byte SFR (TH0, 0x8C) and the
lower 5 bits of Timer 0 Low byte SFR (TL0, 0x8A). The upper 3
bits of Timer 0 Low byte SFR (TL0, 0x8A) are indeterminate
and should be ignored. Setting the run flag (TR0) does not clear
the registers.
Timer/Counter 0 and 1 Operating Modes
This section describes the operating modes for Timer/Counters
0 and 1. Unless otherwise noted, these modes of operation are
the same for both Timer 0 and Timer 1.
Mode 1 (16-Bit Timer/Counter)
Mode 0 (13-Bit Timer/Counter)
Mode 1 is the same as Mode 0 except that the Mode 1 timer
register runs with all 16 bits. Mode 1 is shown in Figure 70.
Mode 0 configures an 8-bit timer/counter. Figure 69 shows
Mode 0 operation. Note that the divide-by-12 prescaler is not
present on the single-cycle core.
F
CORE
C/T = 0
C/T = 1
F
CORE
INTERRUPT
TL0
TH0
TF0
(8 BITS) (8 BITS)
C/T = 0
INTERRUPT
TL0
TH0
TF0
(5 BITS) (8 BITS)
P0.6/T0
C/T = 1
CONTROL
TR0
P0.6/T0
CONTROL
TR0
GATE
INT0
GATE
INT0
Figure 70. Timer/Counter 0, Mode 1
Figure 69. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit register.
Rev. PrE | Page 112 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Mode 2 (8-Bit Timer/Counter with Autoreload)
cycles) and takes over the use of TR1 and TF1 from Timer 1.
Therefore, TH0 then controls the Timer 1 interrupt. Mode 3 is
provided for applications requiring an extra 8-bit timer or
counter.
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload as shown in Figure 71. Overflow from
TL0 not only sets TF0, but also reloads TL0 with the contents of
TH0, which is preset by software. The reload leaves TH0
unchanged.
When Timer 0 is in Mode 3, Timer 1 can be turned on and off
by switching it out of and into its own Mode 3, or it can still be
used by the serial interface as a baud rate generator. In fact, it
can be used in any application not requiring an interrupt from
Timer 1 itself.
F
CORE
C/T = 0
C/T = 1
INTERRUPT
TL0
(8 BITS)
TF0
CORE
CLK/12
F
CORE
P0.6/T0
C/T = 0
CONTROL
INTERRUPT
TL0
TF0
TR0
(8 BITS)
C/T = 1
RELOAD
TH0
(8 BITS)
P0.6/T0
CONTROL
TR0
GATE
INT0
Figure 71. Timer/Counter 0, Mode 2
GATE
INT0
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 72.
INTERRUPT
TH0
TF1
FCORE/12
(8 BITS)
TR1
TL0 uses the Timer 0 control bits C/ , Gate, TR0,
, and
T
INT0
Figure 72. Timer/Counter 0, Mode 3
TF0. TH0 is locked into a timer function (counting machine
TIMER 2
16-Bit Autoreload Mode
Timer/Counter 2 Data Registers
Autoreload mode has two options that are selected by bit
EXEN2 in Timer/Counter 2 Control SFR (T2CON, 0xC8). If
EXEN2 = 0, when Timer 2 rolls over, it not only sets TF2 but
also causes the Timer 2 registers to be reloaded with the 16-bit
value in registers Timer 2 Reload/capture High byte SFR
(RACP2H, 0xCB) and Timer 2 Reload/capture Low byte SFR
(RACP2L, 0xCA), which are preset by software. If EXEN2 = 1,
Timer 2 still performs the above, but with the added feature that
a 1-to-0 transition at external input T2EX also triggers the 16-
bit reload and sets EXF2. Autoreload mode is shown in Figure
73.
Timer/Counter 2 also has two pairs of 8-bit data registers
associated with it: Timer 2 High byte SFR (TH2, 0xCD), Timer
2 Low byte SFR (TL2, 0xCC), Timer 2 Reload/capture High byte
SFR (RACP2H, 0xCB) and Timer 2 Reload/capture Low byte
SFR (RACP2L, 0xCA). These are used as both timer data
registers and as timer capture/reload registers – see Table 104 to
Table 107.
Timer/Counter 2 Operating Modes
The following sections describe the operating modes for
Timer/Counter 2. The operating modes are selected by bits in
the Timer/Counter 2 Control SFR (T2CON, 0xC8) as shown in
Table 99 and Table 108.
16-Bit Capture Mode
Capture mode has two options that are selected by Bit EXEN2
in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter
that, upon overflowing, sets bit TF2, the Timer 2 overflow bit,
which can be used to generate an interrupt. If EXEN2 = 1,
Timer 2 still performs the above, but a l-to-0 transition on
external input T2EX causes the current value in the Timer 2
registers, TL2 and TH2, to be captured into registers RCAP2L
and RCAP2H, respectively. In addition, the transition at T2EX
causes bit EXF2 in T2CON to be set, and EXF2, like TF2, can
generate an interrupt. Capture mode is shown in Figure 74. The
Table 108. T2CON Operating Modes
RCLK (or) TCLK
CAP2
TR2
Mode
0
0
1
X
0
1
X
X
1
1
1
0
16-Bit Autoreload
16-Bit Capture
Baud Rate
Off
Rev. PrE | Page 113 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
baud rate generator mode is selected by RCLK = 1 and/or
TCLK = 1.
the EXF2 flag can, however, still cause interrupts, which can be
used as a third external interrupt. Baud rate generation is
described as part of the UART serial port operation in UART
serial interface section.
In either case, if Timer 2 is used to generate the baud rate, the
TF2 interrupt flag does not occur. Therefore, Timer 2 interrupts
do not occur, so they do not have to be disabled. In this mode,
F
CORE
C/T2 = 0
TL2
(8 BITS)
TH2
(8 BITS)
C/T2 = 1
P1.4/T2
CONTROL
RELOAD
TR2
TRANSITION
DETECTOR
RCAP2L
RCAP2H
TF2
TIMER
INTERRUPT
P1.3/T2EX
EXF2
CONTROL
EXEN2
Figure 73. Timer/Counter 2, 16-Bit Autoreload Mode
F
CORE
C/T2 = 0
C/T2 = 1
TL2
(8 BITS)
TH2
(8 BITS)
TF2
P1.4/T2
CONTROL
TR2
TIMER
INTERRUPT
CAPTURE
TRANSITION
DETECTOR
RCAP2L
RCAP2H
EXF2
P1.3/T2EX
CONTROL
EXEN2
Figure 74. Timer/Counter 2, 16-Bit Capture Mode
Rev. PrE | Page 114 of 148
Preliminary Technical Data
PLL
ADE75xx/ADE71xx
The ADE75xx/ADE71xx is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a
stable 4.096 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power saving when
maximum core performance is not required. The default core clock is the PLL clock divided by 4 or 1.024 MHz. The ADE energy
measurement clock is derived from the PLL clock and is maintained at 4.096/5 MHz, 819.2 kHz across all CD settings. The PLL is
controlled by the CD[2:0] bits in the Power Control SFR (POWCON, 0xC5). To protect erroneous changes to the Power Control SFR
(POWCON, 0xC5), a key is required to modify the register. First the Key SFR (KYREG, 0xC1) is written with the key, 0xA7, and then a
new value is written to the Power Control SFR (POWCON, 0xC5).
If the PLL loses lock, the MCU is reset and the PLLFAULT bit is set in the Peripheral Configuration SFR (PERIPH, 0xF4). Set the
PLLACK bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the PLL fault, clearing the PLL_FLT flag.
PLL SFR REGISTER LIST
Power Control SFR (POWCON, 0xCꢀ)
Bit
Bit
Default
Value
X
Description
Location Mnemonic
7
6
RESERVED
Reserved
METER_OFF
0
Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if
metering functions are not needed in PSM0
5
4
RESERVED
COREOFF
0
0
Reserved
Set this bit to shut down the core if in the PSM1 operating mode.
3
RESERVED
CD[2:0]
Reserved
2-0
010
Controls the core clock frequency, Fcore. Fcore=4.096MHz/2CD
CD[2:0]
Fcore (MHz)
4.096
2.048
1.024
0.512
0.256
0.128
0.064
0.032
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 109.Key SFR (KYREG, 0xC1)
Bit
Location
7-0
Bit
Mnemonic
KYREG
Default
Value
Description
0
Write 0xA7 to the KYREG SFR before writing the POWCON SFR, to unlock it
Write 0xEA to the KYREG SFR before writing to the HTHSEC, SEC, MIN, or
HOUR timekeeping register to unlock it.
Peripheral Configuration SFR (PERIPH, 0xF4)
Bit
Bit
Default
Description
Location Mnemonic
Value
7
6
RXFLAG
0
1
If set, indicates that a RX Edge event triggered wakeup from PSM2
VSWSOURCE
Indicates the power supply that is connected internally to VSW.
0 VSW=VBAT
1 VSW=VDD
5
VDD_OK
0
If set, indicates that VDD power supply is ok for operation
Rev. PrE | Page 115 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
4
3
PLL_FLT
0
If set, indicates that PLL is not locked
RESERVED
2
EXTREFEN
0
Set this bit if an external reference is connected to the REFIN pin.
Controls the function of the P1.0/RX pin.
1-0
RXPROG[1:0]
00
RXPROG [1:0] Function
0
0
1
0
1
1
GPIO
RX with wakeup disabled
RX with wakeup enabled
Start ADC Measurement SFR (ADCGO, 0xD8)
Bit
Location
Bit
Addr.
Bit
Name
Default Description
Value
7
0xDF
PLL_FTL_ACK
0
0
0
0
0
Set this bit to clear the PLL fault bit, PLL_FLT in the PERIPH register. A PLL
fault is generated if a reset was caused because the PLL lost lock.
6-3
2
0xDE – Reserved
0xDB
Reserved
0xDA
0xD9
0xD8
VDCIN_ADC_GO
Set this bit to initiate an external voltage measurement. This bit will be
cleared when the measurement request is received by the ADC.
1
TEMP_ADC_GO
BATT_ADC_GO
Set this bit to initiate a temperature measurement. This bit will be cleared
when the measurement request is received by the ADC.
0
Set this bit to initiate a battery measurement. This bit will be cleared when
the measurement request is received by the ADC.
Rev. PrE | Page 116 of 148
Preliminary Technical Data
RTC - REAL TIME CLOCK
ADE75xx/ADE71xx
The ADE75XX/ADE71XX has an embedded Real Time Clock (RTC) – see Figure 75. The external 32.768 kHz crystal is used as the clock
source for the RTC. Calibration is provided to compensate the nominal crystal frequency and for variations in the external crystal
frequency over temperature. By default, the RTC is maintained active in all the Power Saving Modes. The RTC counters retain their
values through watchdog resets and external resets and are only reset during a power on reset.
32.768kHz
CRYSTAL
RTCCOMP
TEMPCAL
CALIBRATION
CALIBRATED
32.768kHz
RTCEN
ITS1 ITS0
8-BIT
PRESCALER
HUNDREDTHS COUNTER
HTHSEC
INTERVAL
TIMEBASE
SELECTION
MUX
ITEN
SECOND COUNTER
SEC
MINUTE COUNTER
MIN
HOUR COUNTER
HOUR
MIDNIGHT EVENT
8-BIT
INTERVAL COUNTER
ALARM EVENT
EQUAL?
INTVAL SFR
Figure 75: RTC implementation
RTC SFR REGISTER LIST
SFR
Address Bit Addressable Description
TIMECON 0xA1
No
No
No
No
No
No
No
RTC configuration
Hundredth of a second counter
Seconds counter
HTHSEC
SEC
0xA2
0xA3
0xA4
0xA5
0xA6
MIN
Minutes counter
HOUR
INTVAL
Hours counter
Alarm interval
RTCCOMP 0xF6
RTC nominal compensation
Rev. PrE | Page 117 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
TEMPCAL 0xF7
No
RTC temperature compensation
RTC Calibration output options
Key Register
INTPR
0xFF
0xC1
No
No
KYREG
Table 110. RTC Configuration SFR (TIMECON, 0xA1)
Bit
Location
Bit
Mnemonic
MIDNIGHT
Default
Value
Description
7
0
Midnight Flag
This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by
the user to indicate that the midnight event has been serviced. In twenty-
four hour mode, the midnight flag is raised once a day at midnight.
6
TFH
0
Twenty-four hour mode
0
1
256 Hour mode. The HOUR register will roll over from 255 to 0.
24 Hour mode. The HOUR register will roll over from 23 to 0.
Note: This bit is retained during a watchdog reset or an external reset. It is
reset after a power on reset (POR).
5-4
ITS[1:0]
0
0
Interval Timer Timebase Selection
ITS[1:0]
Timebase
1/128 second
Second
0
0
1
1
0
1
0
1
Minute
Hour
3
SIT
Interval Timer One-Time Alarm
0
The ALARM flag will be set after INTVAL counts and then another
interval count will start.
1
The ALARM flag will be set after one time interval.
2
1
ALARM
ITEN
0
0
Interval Timer Alarm Flag
This bit is set when the configured time interval has elapsed. It can be
cleared by the user to indicate that the alarm event has been serviced.
Interval Timer Enable
0
The interval timer is disabled. The 8-bit interval timer counter is
reset.
1
Set this bit to enable the interval timer. The RTCEN bit must also
be set to enable the interval timer.
0
RTCEN
1
RTC Enable. Also Temperature, Battery and Supply ADC Background
Strobe Enable
Note: The RTC is always enabled.
Table 111. Hundredths of a Second Counter SFR (HTHSEC, 0xA2)
Bit
Location
7-0
Bit
Mnemonic
HTHSEC
Default
Value
Description
0
This counter updates every 1/128 second, referenced from the calibrated
32kHz clock. It overflows from 127 to 00, incrementing the seconds
counter, SEC.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
Rev. PrE | Page 118 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Table 112. Seconds Counter SFR (SEC, 0xA3)
Bit
Location
7-0
Bit
Mnemonic
SEC
Default
Value
Description
0
This counter updates every second, referenced from the calibrated 32kHz
clock. It overflows from 59 to 00, incrementing the minutes counter, MIN.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
Table 113. Minutes Counter SFR (MIN, 0xA4)
Bit
Location
7-0
Bit
Mnemonic
MIN
Default
Value
Description
0
This counter updates every minute, referenced from the calibrated 32kHz
clock. It overflows from 59 to 00, incrementing the hours counter, HOUR.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
Table 114. Hours Counter SFR (HOUR, 0xAꢀ)
Bit
Location
7-0
Bit
Mnemonic
HOUR
Default
Value
Description
0
This counter updates every hour, referenced from the calibrated 32kHz
clock. If the TFH bit in the RTC Configuration SFR (TIMECON, 0xA1) is set,
the HOUR SFR overflows from 23 to 00, setting the MIDNIGHT bit and
creating a pending RTC interrupt. If the TFH bit in the RTC Configuration
SFR (TIMECON, 0xA1) is clear, the HOUR SFR overflows from 255 to 00,
setting the MIDNIGHT bit and creating a pending RTC interrupt.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
Table 11ꢀ. Alarm Interval SFR (INTVAL, 0xA6)
Bit
Location
7-0
Bit
Mnemonic
INTVAL
Default
Value
Description
0
The interval timer counts according to the timebase established in the
ITS[1:0] bits of the RTC Configuration SFR (TIMECON, 0xA1). Once the
number of counts is equal to INTVAL, the ALARM flag is set and a pending
RTC interrupt is created. Note that the interval counter is 8-bits so it could
count up to 255 seconds, for example.
Table 116. RTC Nominal Compensation SFR (RTCCOMP, 0xF6)
Bit
Location
7-0
Bit
Mnemonic
RTCCOMP
Default
Value
Description
0
The RTCCOMP SFR holds the nominal RTC compensation value at 25°C.
Note: This register is reset after a watchdog reset, an external reset or a
power on reset (POR).
Table 117. RTC Temperature Compensation SFR (TEMPCAL, 0xF7)
Bit
Location
7-0
Bit
Mnemonic
TEMPCAL
Default
Value
Description
0
The TEMPCAL SFR is adjusted based on the temerature read in the
TEMPADC to calibrate the RTC over temperature. This allows the external
crystal shift to be compensated over temperature.
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ADE75xx/ADE71xx
Preliminary Technical Data
Note: This register is reset after a watchdog reset, an external reset or a
power on reset (POR).
Table 118. Interrupt pins configuration SFR (INTPR, 0xFF)
Bit
Bit
Default
Value
0
Description
Location Mnemonic
7
RTCCAL
Control RTC calibration output
When set, the RTC calibration frequency selected by FSEL[1:0] is output on the
P0.2/CF1/RTCCAL pin.
6-5
FSEL[1:0]
Sets RTC calibration output frequency and calibration window
FSEL[1:0]
Calibration window, frequency
30.5 seconds, 1Hz
0
0
1
1
0
1
0
1
30.5 seconds, 512 Hz
0.244 seconds, 500Hz
0.244 seconds, 16.384 kHz
4
Reserved
3-1
INT1PRG[2:0]
000
Controls the function of INT1T
INT1PRG[2:0]
Function
GPIO
x
0
0
x
0
1
0
1
1
1
x
x
BCTRL
INT1 input disabled
INT1 input enabled
0
INT0PRG
0
Controls the function of INT0
INT0PRG
Function
0
1
INT0 input disabled
INT0 input enabled
Table 119. Key SFR (KYREG, 0xC1)
Bit
Location
7-0
Bit
Mnemonic
KYREG
Default
Value
Description
0
Write 0xA7 to the KYREG SFR before writing the POWCON SFR, to unlock it
Write 0xEA to the KYREG SFR before writing to the HTHSEC, SEC, MIN, or
HOUR timekeeping register to unlock it..
MOV RTCKey, #0EAh
CALL UpdateRTC
…
READ AND WRITE OPERATIONS
Writing the RTC Registers
The RTC circuitry runs off a 32.768kHz clock. The timekeeping
registers, HTHSEC, SEC, MIN, HOUR are updated with a
32.768 kHz clock. However, the TIMECON and INTVAL SFRs
are updated with a 128Hz clock. It takes up to two 128Hz clock
cycles from when the MCU writes the TIMECON or INTVAL
register until it is successfully updated in the RTC.
UpdateRTC:
MOV KYREG, RTCKey
MOV SEC, #30
MOV KYREG, RTCKey
MOV MIN, #05
MOV KYREG, RTCKey
MOV HOUR, #04
RET
To protect the RTC timekeeping registers from runaway code, a
key must be written to the KYREG register to obtain write
access to the HTHSEC, SEC, MIN and HOUR registers. The
KYREG should be set to 0xEA to unlock the timekeeping
registers and is reset to zero after a timekeeping register is
written to. The RTC registers can be written using the following
8052 assembly code:
Reading the RTC Counter SFRs
The RTC cannot be stopped to read the current time because
stopping the RTC would introduce an error in its timekeeping.
So the RTC is read on the fly. Therefore the counter registers
Rev. PrE | Page 120 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
must be checked for overflow. This can be accomplished
through the following 8052 assembly code:
Configuration SFR (TIMECON, 0xA1), the interval timer clock
source selected by the ITS1 and ITS0 bits is passed through to
an 8-bit counter. This counter increments on every interval
timer clock pulse until the 8-bit counter is equal to the value in
the Alarm Interval SFR (INTVAL, 0xA6). Then an alarm event
is generated, setting the ALARM flag and creating a pending
RTC interrupt. If the SIT bit in the RTC Configuration SFR
(TIMECON, 0xA1) is clear then the 8-bit counter is cleared and
starts counting again. If the SIT bit is set then the 8-bit counter
is held in reset after the alarm occurs.
ReadAgain:
MOV R0, HTHSEC
MOV R1, SEC
; using Bank 0
MOV R2, MIN
MOV R3, HOUR
MOV A, HTHSEC
CJNE A, 00h, ReadAgain
; 00h is R0 in Bank 0
Take care when changing the interval timer timebase. The
recommended prodedure is as follows:
RTC MODES
The RTC can be configured in a 24 hour mode or a 256 hour
mode. A midnight event is generated when the RTC hour
counter rolls over from 23 to 0 or 255 to 0, depending on
whether the TFH bit is set in the RTC Configuration SFR
(TIMECON, 0xA1). The midnight event sets the MIDNIGHT
flag in the RTC Configuration SFR (TIMECON, 0xA1) and a
pending RTC interrupt is created. The RTC midnight event will
wake the 8052 MCU core if the MCU is asleep in PSM2 when
the midnight event occurs. To acknowledge the midnight event,
service the RTC interrupt.
1. If the INTVAL SFR is going to be modified, write
this register first. Then wait for one 128Hz clock
cycle, to synchronize with the RTC, 64000 cycles
at a 4.096MHz instruction cycle clock.
2. Disable the interval timer by clearing the ITEN
bit in the TIMECON SFR. Then wait for one
128Hz clock cycle, to synchronize with the RTC,
64000 cycles at a 4.096MHz instruction cycle
clock.
In the 24 hour mode, the midnight event is generated once a
day, at midnight. The 24 hour mode is useful for updating a
software calendar to keep track of the current day. The 256 hour
mode will result in power savings during extended operation in
PSM2 because the MCU core will be awoken less frequently.
3. Read the TIMECON SFR to ensure that the ITEN
bit is clear. If it is not, wait for another 128Hz
clock cycle.
4. Set the timebase bits, ITS[1:0] in the TIMECON
SFR to configure the interval. Wait for a 128Hz
clock cycle for this change to take effect.
RTC INTERRUPTS
The RTC Midnight and Alarm Interrupts are enabled by setting
the ETI bit in the Interrupt Enable and Priority 2 SFR (IEIP2,
0xA9). When a midnight or alarm event occurs, a pending RTC
interrupt is generated. If the RTC interrupt is enabled, the
program will vector to the RTC interrupt address and the
pending interrupt will be cleared. If the RTC interrupt is
disabled, then the RTC interrupt will remain pending until the
RTC interrupt is enabled. Then the program will vector to the
RTC interrupt address.
The RTC alarm event will wake the 8052 MCU core if the MCU
is in PSM2 when the alarm event occurs.
RTC CALIBRATION
The RTC provides registers to calibrate the nominal external
crystal frequency and its variation over temperature. Up to
248ppm frequency error can be calibrated out by the RTC
circuitry, which adds or subtracts pulses from the external
crystal signal.
The MIDNIGHT and ALARM flags are set when the midnight
and alarm events occur, respectively. The user should manage
these flags to keep track of which event caused an RTC
interrupt by servicing the event and clearing the appropriate
flag in the RTC ISR.
The nominal crystal frequency should be calibrated with the
RTCCOMP register so that the clock going into the RTC is
precisely 32.768 kHz at 25°C. The RTC Temperature
Compensation SFR (TEMPCAL, 0xF7) is used to compensate
for the external crystal drift over temperature by adding or
subtracting additional pulses based on temperature.
Note that if the ADE7100/7500 is awakened by an RTC event,
either the MIDNIGHT or ALARM, then the pending RTC
interrupt must be serviced before the ADE7100/7500 can go
back to sleep again. The ADE7100/7500 will keep waking up
until this interrupt has been serviced.
The LSB of each RTC compensation register represents a
±2ppm, or 0.17s/day, frequency error. The RTC compensation
circuitry adds the RTC Temperature Compensation SFR
(TEMPCAL, 0xF7) and the RTC Nominal Compensation SFR
(RTCCOMP, 0xF6) to determine how much compensation is
required and the sum of these two registers is limited to
248ppm, or 42.85s/day.
Interval Timer Alarm
The RTC can be used as an interval timer. When the interval
timer is enabled by setting the ITEN bit in the RTC
Rev. PrE | Page 121 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Calibration Flow:
of these two registers is limited to ±248ppm.
During calibration, user software writes the RTC with the
current time. Refer to the RTC Read and Write operations
section for more information on how to read and write the RTC
timekeeping registers.
A RTC calibration pulse output is provided on the
P0.2/CF1/RTCCAL pin. Enable the RTC output by setting the
RTCCAL bit in the INTPR SFR.
The RTC calibration is accurate to within ±2ppm over a 30.5
second window in all operational modes: PSM0, PSM1 and
PSM2. Two output frequencies are offered for the normal RTC
mode: 1Hz with FSEL[1:0]=00 and 512Hz with FSEL[1:0]=01 in
the INTPR register.
A shorter window of 0.244 seconds is offered for fast calibration
during PSM0 or PSM1. Two output frequencies are offered for
this RTC calibration output mode: 500Hz with FSEL[1:0]=01
and 16.384kHz with FSEL[1:0]=11 in the INTPR register. Note
that for the 0.244s calibration window, the RTC is clocked 125
times faster than in the normal mode, resulting in timekeeping
registers that represent seconds/125, minutes/125 and
hours/125 instead of seconds, minutes and hours. Therefore this
mode should be used for calibration only.
Option
FSEL[1:0] Calibration
Window (s)
F
RTCCAL (Hz)
Normal Mode 0
Normal Mode 1
00
01
10
30.5
30.5
0.244
1
512
500
Calibration
Mode 0
Calibration
Mode 1
11
0.244
16384
Table 120: RTC calibration options
When no RTC compensation is applied, when RTCCOMP and
TEMPCAL equal to zero, the nominal compensation required
to account for the error in the external crystal can be
determined. In this case, it is not necessary to wait for an entire
calibration window to determine the error in the pulse output.
Calculating at the error in frequency between two consecutive
pulses on the P0.2/CF1/RTCCAL pin is enough.
The value to write to the RTCCOMP register is calculated from
the ꢀ error or seconds per day error on the frequency output.
Each LSB of the RTCCOMP SFR represents 2ppm of correction
where1s/day error is equal to 11.57ppm.
RTCCOMP = 5000×(% Error)
1
RTCCOMP =
× (s / day Error)
2×11.57
to determine how much compensation is required and the sum
Rev. PrE | Page 122 of 148
Preliminary Technical Data
UART SERIAL INTERFACE
ADE75xx/ADE71xx
physical interface to the UART is provided via the RxD (P1.0)
and TxD (P1.1) pins, while the firmware interface is through
the SFRs presented in Table 121.
The ADE75XX/ADE71XX UART can be configured in one of
four modes:
Both the serial port receive and transmit registers are accessed
through the SBUF SFR (SFR address = 0x99). Writing to SBUF
loads the transmit register, and reading SBUF accesses a
physically separate receive register.
- Shift register with baud rate fixed at Fcore/12
- 8-bit UART with variable baud rate
- 9- bit UART with baud rate fixed at Fcore/64 or Fcore/32
- 9 bit UART with variable baud rate
An enhanced UART mode is offered by using UART Timer and
providing enhanced frame error, break error and overwrite
error detection. This mode is enabled by setting the EXTEN bit
in the CFG SFR—see the UART additional features section. The
SBAUDT and SBAUDF SFR are used to configure UART Timer
and to indicate the enhanced UART errors.
Variable baud rates are defined by using an internal timer to
generate any rate between 300 and 115200 bauds/s.
The UART serial interface provided in the
ADE75XX/ADE71XX is a full-duplex serial interface. It is also
receive buffered, by storing the first received byte in a receive
buffer until the reception of the second byte is complete. The
UART SFR REGISTER LIST
Table 121. Serial port SFRs
SFR
Address Bit Addressable Description
SCON
SBUF
0x98
0x99
Yes
No
No
No
Serial Communications Control register – see Table 122
Serial Port Buffer – see Table 123
SBAUDT 0x9E
SBAUDF 0x9D
Enhanced error checking – see Table 124
Enhanced Fractional Divider – see Table 125
Table 122. SCON SFR Bit Description SFR (SCON, 0x98)
Bit
Location
Bit
Addr.
Bit
Name
Default
Value
Description
7-6
0x9F,
0x9E
SM0,
SM1
00
UART Serial Mode Select Bits. These bits select the serial port operating mode as
follows:
SM0
SM1
Selected Operating Mode.
0
0
1
1
0
1
0
1
Mode 0: Shift register, fixed baud rate (Fcore/12).
Mode 1: 8-bit UART, variable baud rate.
Mode 2: 9-bit UART, fixed baud rate (Fcore/32) or (Fcore/16).
Mode 3: 9-bit UART, variable baud rate.
5
0x9D
SM2
0
Multiprocessor Communication Enable Bit.
Enables multiprocessor communication in Modes 2 and 3 and framing error detection
in Mode 1.
In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is
Rev. PrE | Page 123 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
cleared, RI is set as soon as the byte of data is received.
In Modes 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is
0. If SM2 is cleared, RI is set as soon as the byte of data is received.
4
0x9C
REN
0
Serial Port Receive Enable Bit.
Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
Serial Port Transmit (Bit 9).
3
2
0x9B
0x9A
TB8
RB8
0
0
The data loaded into TB8 is the ninth data bit transmitted in Modes 2 and 3.
Serial Port Receiver Bit 9.
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop
bit is latched into RB8.
1
0
0x99
0x98
TI
RI
0
0
Serial Port Transmit Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop
bit in Modes 1, 2, and 3.
TI must be cleared by user software.
Serial Port Receive Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit
in Modes 1, 2, and 3.
RI must be cleared by user software.
Table 123. Serial port Buffer SFR (SBUF, 0x99)
Bit Bit Default Description
Location Mnemonic Value
7-0 SBUF
0
Serial port data buffer
Table 124. Enhanced Serial baud rate control SFR (SBAUDT, 0x9E)
Bit
Location
Bit
Mnemonic
Default
Value
Description
7
OWE
0
Overwrite Error. This bit is set when new data is received and RI=1. It indicates that
SBUF was not read before the next character was transferred in, causing the prior
SBUF data to be lost. Write a zero to this bit to clear it..
6
5
FE
BE
0
0
Frame Error. This bit is set when the received frame did not have a valid stop bit. This
bit is read only and updated every time a frame is received.
Break Error. This bit is set whenever the receive data line (Rx) is low for longer than a
full transmission frame, the time required for a start bit, 8 data bits, a parity bit and half
a stop bit. This bit is updated every time a frame is received.
4-3
SBTH1, SBTH0
0
0
Extended divider ratio for baud rate setting as shown in Table 126
Binary Divider
2, 1, 0
DIV2, DIV1,
DIV0
DIV2 DIV1
DIV0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Divide by 1. See Table 126.
Divide by 2. See Table 126.
Divide by 4. See Table 126.
Divide by 8. See Table 126.
Divide by 16. See Table 126.
Divide by 32. See Table 126.
Divide by 64. See Table 126.
Rev. PrE | Page 124 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
1
1
1
Divide by 128. See Table 126.
Table 12ꢀ. UART Timer Fractional Divider SFR (SBAUDF, 0x9D)
Bit Location
Bit Mnemonic Default value Description
7
UARTBAUDEN
0
UART Baud Rate Enable
Set to enable UART Timer to generate the baud rate. When set, PCON.7,
T2CON.4, and T2CON.5 are ignored. Cleared to let the baud rate be generated
as per a standard 8052.
6
5
4
3
2
1
0
----
Not Implemented. Write Don’t Care.
UART Timer Fractional Divider Bit 5.
UART Timer Fractional Divider Bit 4.
UART Timer Fractional Divider Bit 3.
UART Timer Fractional Divider Bit 2.
UART Timer Fractional Divider Bit 1.
UART Timer Fractional Divider Bit 0.
SBAUDF.5
SBAUDF.4
SBAUDF.3
SBAUDF.2
SBAUDF.1
SBAUDF.0
0
0
0
0
0
0
Table 126. Common Baud Rates Using UART Timer with a 4.096 MHz FLL Clock
Ideal Baud
CD
SBTH
DIV
SBAUDT
SBAUDF
87H
87H
% Error
+ 0.16
+ 0.16
115200
115200
0
1
0
0
1
0
01H
00H
57600
57600
0
1
0
0
2
1
02H
01H
87H
87H
+ 0.16
+ 0.16
38400
38400
38400
0
1
2
0
0
0
2
1
0
02H
01H
00H
ABH
ABH
ABH
- 0.31
- 0.31
- 0.31
19200
19200
19200
19200
0
1
2
3
0
0
0
0
3
2
1
0
03H
02H
01H
00H
ABH
ABH
ABH
ABH
- 0.31
- 0.31
- 0.31
- 0.31
9600
9600
9600
9600
9600
0
1
2
3
4
0
0
0
0
0
4
3
2
1
0
04H
03H
02H
01H
00H
ABH
ABH
ABH
ABH
ABH
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
4800
4800
4800
4800
4800
4800
0
1
2
3
4
5
0
0
0
0
0
0
5
4
3
2
1
0
05H
04H
03H
02H
01H
00H
ABH
ABH
ABH
ABH
ABH
ABH
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
2400
2400
2400
2400
2400
2400
0
1
2
3
4
5
0
0
0
0
0
0
6
5
4
3
2
1
06H
05H
04H
03H
02H
01H
ABH
ABH
ABH
ABH
ABH
ABH
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
Rev. PrE | Page 125 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
2400
6
0
0
00H
ABH
- 0.31
300
300
300
300
300
300
300
300
0
1
2
3
4
5
6
7
2
1
0
0
0
0
0
0
7
7
7
6
5
4
3
2
17H
0FH
07H
06H
05H
04H
03H
02H
ABH
ABH
ABH
ABH
ABH
ABH
ABH
ABH
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
UART OPERATION MODES
Mode 0 (Shift Register with baud rate fixed at
Fcore /12)
Figure 77. 8-Bit Variable Baud Rate
Mode 0 is selected when the SM0 and SM1 bits in the SCON
SFR are clear. In this shift register mode, serial data enters and
exits through RxD. TxD outputs the shift clock. The baud rate is
fixed at Fcore/12. Eight data bits are transmitted or received.
Reception is initiated when a 1-to-0 transition is detected on
RxD. Assuming that a valid start bit is detected, character
reception continues. The 8 data bits are clocked into the serial
port shift register.
Transmission is initiated by any instruction that writes to SBUF.
The data is shifted out of the RxD line. The 8 bits are
transmitted with the least significant bit (LSB) first.
All of the following conditions must be met at the time the final
shift pulse is generated to receive a character:
•
•
If the extended UART is disabled (EXTEN=0 in the CFG
SFR), RI must be zero to receive a character. This ensures
that the data in SBUF will not be overwritten if the last
received character has not been read.
Reception is initiated when the receive enable bit (REN) is 1
and the receive interrupt bit (RI) is 0. When RI is cleared, the
data is clocked into the RxD line, and the clock pulses are
output from the TxD line as shown in Figure 76.
If frame error checking is enabled by setting SM2, the
received stop bit must be set to receive a character. This
ensures that every character received comes from a valid
frame, with both a start and a stop bit)
RxD
(DATA OUT)
DATA BIT 0
DATA BIT 1
DATA BIT 6
DATA BIT 7
TxD
(SHIFT CLOCK)
Figure 76. 8-Bit Shift Register Mode
If any of these conditions are not met, the received frame is
irretrievably lost, and the receive interrupt flag, RI, is not set.
Mode 1 (8-Bit UART, Variable Baud Rate)
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit (0) and followed by a
stop bit (1). Therefore, each frame consists of 10 bits
transmitted on TxD or received on RxD.
If the received frame has met the above criteria, the following
events occur:
•
•
•
The 8 bits in the receive shift register are latched into SBUF.
The 9th bit (stop bit) is clocked into RB8 in SCON.
The receiver interrupt flag (RI) is set.
The baud rate is set by a timer overflow rate. Timer 1 or Timer 2
can be used to generate baud rates or both timers can be used
simultaneously where one generates the transmit rate and the
other generates the receive rate. There is also a dedicated timer
for baud rate generation, UART Timer, which has a fractional
divisor to precisely generate any baud rate—see the UART
Timer Generated Baud Rates section.
Mode 2 (9- bit UART with baud fixed at Fcore/64
or Fcore/32)
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode, the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at Fcore/64 by default, although by setting
the SMOD bit in PCON, the frequency can be doubled to
Transmission is initiated by a write to SBUF. Next a stop bit (a
1) is loaded into the 9th bit position of the transmit shift
register. The data is output bit-by-bit until the stop bit appears
on TxD and the transmit interrupt flag (TI) is automatically set
as shown in Figure 77.
F
core/32. Eleven bits are transmitted or received: a start bit (0), 8
data bits, a programmable 9th bit, and a stop bit (1). The 9th bit
is most often used as a parity bit or as part of a multiprocessor
communication protocol, although it can be used for anything,
including a ninth data bit if required.
STOP BIT
START
BIT
D0 D1 D2 D3 D4 D5 D6
D7
TxD
TI
(SCON.1)
SET INTERRUPT
I.E., READY FOR MORE DATA
Rev. PrE | Page 126 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
To use the 9th data bit as part of a communication protocol for a
multiprocessor network such as RS-485, the 9th bit is set to
indicate that the frame contains the address of the device that
the master would like to communicate with. The devices on the
network are always listening for a packet with the 9th bit set and
are configured such that if the 9th bit is clear, the frame will not
be valid and a receive interrupt will not be generated. If the 9th
bit is set, all of the devices on the network will receive the
address and get a receive character interrupt. The devices will
examine the address and if it matches a device’s preprogrammed
address, the device will configure itself to listen to all incoming
frames, even those with the 9th bit clear. Since the master has
initiated communication with that device, all the following
packets with the 9th bit clear are intended specifically for the
addressed device until another packet with the 9th bit set is
received. If the address does not match, the device will continue
listening for address packets.
baud rate. The baud rate is set by a timer overflow rate. Timer 1
or Timer 2 can be used to generate baud rates or both timers
can be used simultaneously where one generates the transmit
rate and the other generates the receive rate. There is also a
dedicated timer for baud rate generation, UART Timer, which
has a fractional divisor to precisely generate any baud rate—see
the UART Timer Generated Baud Rates section. The operation
of the 9-bit UART is the same as for Mode 2, but the baud rate
can be varied.
In all four modes, transmission is initiated by any instruction
that uses SBUF as a destination register. Reception is initiated in
Mode 0 when RI = 0 and REN = 1. Reception is initiated in the
other modes by the incoming start bit if REN = 1.
UART BAUD RATE GENERATION
Mode 0 Baud Rate Generation
The baud rate in Mode 0 is fixed:
To transmit, the 8 data bits must be written into SBUF. The
ninth bit must be written to TB8 in SCON. When transmission
is initiated, the 8 data bits from SBUF are loaded into the
transmit shift register (LSB first). The 9th data bit, held in TB8, is
loaded into the 9th bit position of the transmit shift register.
The transmission starts at the next valid baud rate clock. The
transmit interrupt flag, TI, is set as soon as the transmission has
completed, when the stop bit appears on TxD.
F
⎛
⎜
⎞
⎟
core
Mode 0 Baud Rate =
12
⎝
⎠
Mode 2 Baud Rate Generation
The baud rate in Mode 2 depends on the value of the SMOD bit
in the PCON SFR. If SMOD = 0, the baud rate is 1/32 of the
core clock. If SMOD = 1, the baud rate is 1/16 of the core clock:
2SMOD
All of the following conditions must be met at the time the final
shift pulse is generated to receive a character:
Mode 2 Baud Rate =
× Fcore
32
Modes 1 and 3 Baud Rate Generation
•
•
If the extended UART is disabled (EXTEN=0 in the CFG
SFR), RI must be zero to receive a character. This ensures
that the data in SBUF will not be overwritten if the last
received character has not been read.
The baud rates in Modes 1 and 3 are determined by the overflow
rate of the timer generating the baud rate: either Timer 1 or
Timer 2 or the dedicated baud rate generator, UART Timer,
which has an integer and fractional divisor.
If multiprocessor communication is enabled by setting
SM2, the received 9th bit must be set to receive a character.
This ensures that only frames with the 9th bit set, frames
that contain addresses, generate a receive interrupt.
Timer 1 Generated Baud Rates
When Timer 1 is used as the baud rate generator, the baud rates
in Modes 1 and 3 are determined by the Timer 1 overflow rate
and the value of SMOD as follows:
If any of these conditions are not met, the received frame is
irretrievably lost, and the receive interrupt flag, RI, is not set.
2SMOD
Modes 1 and 3 Baud Rate =
× Timer 1 Overflow Rate
32
Reception for Mode 2 is similar to that of Mode 1. The 8 data
bytes are input at RxD (LSB first) and loaded onto the receive
shift register. If the received frame has met the above criteria,
the following events occur:
The Timer 1 interrupt should be disabled in this application.
The timer itself can be configured for either timer or counter
operation, and in any of its three running modes. In the most
typical application, it is configured for timer operation in
autoreload mode (high nibble of TMOD = 0010 binary). In that
case, the baud rate is given by the formula
•
•
•
The 8 bits in the receive shift register are latched into SBUF.
The 9th data bit is latched into RB8 in SCON.
The receiver interrupt flag (RI) is set.
2SMOD
Fcore
Modes 1 and 3 Baud Rate =
×
32
(256 −TH1)
Timer 2 Generated Baud Rates
Mode 3 (9-Bit UART with Variable Baud Rate)
Mode 3 is selected by setting both SM0 and SM1. In this mode,
the 8051 UART serial port operates in 9-bit mode with a variable
Baud rates can also be generated by using Timer 2. Using Timer 2
is similar to using Timer 1 in that the timer must overflow 16
times before a bit is transmitted or received. Because Timer 2
Rev. PrE | Page 127 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
has a 16-bit autoreload mode, a wider range of baud rates is
possible.
Timer 2 is selected as the baud rate generator by setting the
TCLK and/or RCLK in T2CON. The baud rates for transmit
and receive can be simultaneously different. Setting RCLK
and/or TCLK puts Timer 2 into its baud rate generator mode as
shown in Figure 78.
1
Modes 1 and 3 Baud Rate =
× Timer 2 Overflow Rate
16
Therefore, when Timer 2 is used to generate baud rates, the
timer increments every two clock cycles rather than every core
machine cycle as before. It increments six times faster than
Timer 1, and, therefore, baud rates six times faster are possible.
Because Timer 2 has 16-bit autoreload capability, very low baud
rates are still possible.
In this case, the baud rate is given by the formula
Modes 1 and 3 Baud Rate =
Fcore
(
16×
[
65536−
(
RCAP2H : RCAP2L
)])
TIMER 1
OVERFLOW
2
0
1
SMOD
CONTROL
F
CORE
C/T2 = 0
C/T2 = 1
TIMER 2
OVERFLOW
1
1
0
0
TL2
(8 BITS)
TH2
(8 BITS)
RCLK
16
T2
PIN
RX
CLOCK
TR2
TCLK
16
NOTE: AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
RELOAD
TX
CLOCK
RCAP2H
RCAP2L
TIMER 2
INTERRUPT
T2EX
PIN
EXF 2
CONTROL
TRANSITION
DETECTOR
EXEN2
Figure 78. Timer 2, UART Baud Rates
UART Timer Generated Baud Rates
F
CORE
TIMER 1/TIMER 2
Tx CLOCK
The high integer dividers in a UART block mean that high
speed baud rates are not always possible. Also, generating baud
rates requires the exclusive use of a timer, rendering it unusable
for other applications when the UART is required. To address
this problem, the ADE75XX/ADE71XX has a dedicated baud
rate timer (UART Timer) specifically for generating highly
accurate baud rates. UART Timer can be used instead of Timer
1 or Timer 2 for generating very accurate high speed UART
baud rates including 115200. UART Timer also allows a much
wider range of baud rates to be obtained. In fact, every desired
bit rate from 12 bps to 393216 bps can be generated to within an
error of 0.8ꢀ. UART Timer also frees up the other three
timers, allowing them to be used for different applications. A
block diagram of UART Timer is shown in Figure 79.
FRACTIONAL
DIVIDER
⎟
(1 + SBAUDF/64)
TIMER 1/TIMER 2
Rx CLOCK
1
0
⎟ 2D IV+SBTH
Rx CLOCK
1
0
⎟ 32
UARTBAUDEN
Tx CLOCK
UART Timer
Rx/Tx CLOCK
Figure 79. UART Timer, UART Baud Rate
Two SFRs Enhanced Serial baud rate control SFR (SBAUDT,
0x9E) and UART Timer Fractional Divider SFR (SBAUDF,
0x9D) are used to control UART Timer. SBAUDT is the baud
rate control SFR; it sets up the integer divider (DIV) and the
extended divider (SBTH) for UART Timer.
Rev. PrE | Page 128 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
bit UART through the SM2 and RB8 bits. Setting the SM2 bit
prevent frames without a stop bit from being received. The stop
bit is latched into the RB8 bit in the SCON register. This bit can
be examined to determine if a valid frame was received. The
8052 does not however, provide frame error checking for a 9-bit
UART. This enhanced error checking functionality is available
through the frame error bit, FE in the SBAUDT SFR. The FE bit
will be set on framing errors for both 8-bit and 9-bit UARTs.
The appropriate value to write to the DIV[2:0] and SBTH[1:0]
bits can be calculated using the following formula where Fcore is
defined in POWCON SFR. Note that the DIV value must be
rounded down to the nearest integer.
DIV+ SBTH =
⎛
⎞
F
core
⎜
⎜
⎟
⎟
log
16× Baud Rate
⎝
⎠
log
2
( )
START
RX
STOP
D0
D1
D2
D3
D4
D5
D6
D7
SBAUDF is the fractional divider ratio required to achieve the
required baud rate. The appropriate value for SBAUDF can be
calculated with the following formula:
RI
FE
EXTEN=1
SBAUDF =
Figure 80: UART Timing in Mode 1
START
RX
RI
⎛
⎜
⎜
⎞
⎟
⎟
Fcore
D8
STOP
D0
D1
D2
D3
D4
D5
D6
D7
64 ∗
−1
DIV +SBTH
16 ⋅ 2
× Baud Rate
⎝
⎠
Note that SBAUDF should be rounded to the nearest integer.
Once the values for DIV and SBAUDF are calculated, the actual
baud rate can be calculated with the following formula:
FE
EXTEN=1
Figure 81: UART Timing in Modes 2 and 3
Actual Baud Rate =
The 8052 standard UART does not provide break error
detection. However for an 8-bit UART, it can be determined that
a break error occurred if the received character is zero, a NUL
character, and there was no stop bit because the RB8 bit is low.
Break error detection is not possible for a 9-bit 8052 UART
because the stop bit is not recorded. The ADE75XX/ADE71XX
enhanced break error detection is available through the BE bit
in the SBAUDT SFR.
Fcore
SBAUDF
⎛
⎞
⎟
16⋅2DIV +SBTH ⋅ 1+
⎜
64
⎝
⎠
For example, to get a baud rate of 9600 while operating at a core
clock frequency of 4.096 MHz, with the PLL CD bits equal to
zero,
The 8052 standard UART prevents overwrite errors by not
allowing a character to be received if the RI, receive interrupt
flag, is set. However, it does not indicate if a character has been
lost because the RI bit was set when the frame was received.
The enhanced UART overwrite error detection provides this
information. When the enhanced 8052 UART is enabled, a
frame will be received regardless of the state of the RI flag. If
RI=1 when a new byte is received, the byte in SCON is
overwritten, and the overwrite error flag will be set. The
overwrite error flag will be cleared when SBUF is read.
DIV + SBTH = log(4096000/(16 × 9600))/log2 = 4.74 = 4
Note that the DIV result is rounded down.
SBAUDF = 64*(4096000/(16*23*9600)-1) = 42.67 = 2BH
Therefore, the actual baud rate is 9570 bps, which gives an error
of 0.31ꢀ.
UART ADDITIONAL FEATURES
Enhanced Error Checking
The extended UART provides frame error, break error and
overwrite error detection. Framing errors occur when a stop bit
is not present at the end of the frame. A missing stop bit implies
that the data in the frame may not have been received properly.
Break error detection indicates if the Rx line has been low for
longer than a 9-bit frame. It indicates that the data just received,
a zero, or NUL character, is not valid because the master has
disconnected. Overwrite error detection indicates if the
received data isn’t read fast enough and as result, a byte of data
has been lost.
The extended UART is enabled by setting the EXTEN bit in the
CFG SFR.
UART TxD signal modulation
There is an internal 38 kHz signal which can be ORed with the
UART transmit signal for use in remote control applications—
see the 38 kHz Modulation section.
One of the events that can wake the MCU from sleep mode is
activity on the UART RX pin—see the 3.3V Peripherals and
Wakeup Events section.
The 8052 standard UART offers frame error checking for an 8-
Rev. PrE | Page 129 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
The SPI port can be configured for Master or Slave operation.
The physical interface to the SPI is done via MISO (P0.3), MOSI
(P0.2), SCLK (P0.4) and SS (P0.5) pins, while the firmware
interface is done via the SPI Configuration Register SFR
(SPIMOD1, 0xE8), SPI Configuration Register SFR (SPIMOD2,
0xE9), SPI Interrupt Status Register SFR (SPISTAT, 0xEA), SPI/I2C
Transmit Buffer SFR (SPI2CTx, 0x9A) and SPI Receive Buffer SFR
(SPI2CRx, 0x9B).
Note that the SPI pins are shared with the I2C pins. Therefore,
the user can enable only one interface at a time. The SCPS bit in
the CFG SFR selects which peripheral is active.
SERIAL PERIPHERAL INTERFACE
INTERFACE (SPI)
The ADE75XX/ADE71XX integrates a complete hardware
serial peripheral interface on-chip. The SPI interface is full
duplex so that eight bits of data are synchronously transmitted
and received simultaneously. This SPI implementation is double
buffered. This allows the user to read the last byte of received
data while a new byte is shifted in. The next byte to be
transmitted can be loaded while the current byte is shifted out.
SPI SFR REGISTER LIST
SFR Address
Name
R/W Length
Default Description
Value
0x9A
0x9B
0xE8
0xE9
0xEA
SPI2CTx
SPI2CRx
SPIMOD1
SPIMOD2
SPISTAT
W
8
8
8
8
8
SPI Data out register
R
0
SPI Data in register
R/W
R/W
R/W
0x10
SPI configuration register
SPI configuration register
SPI Interrupt Status register
0
0
Table 127: SPI SFR register list
Table 128. SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A)
Bit
Location
7-0
Bit
Mnemonic
SPI2CTx
Default
Value
Description
0
SPI or I2C transmit buffer
When SPI2CTx SFR is written, its content is transfered to the transmit FIFO input.
When a write is requested, the FIFO output is sent on the SPI or I2C bus.
Table 129. SPI Receive Buffer SFR (SPI2CRx, 0x9B)
Bit
Location
7-0
Bit
Mnemonic
SPI2CRx
Default
Value
Description
0
SPI or I2C receive buffer
When SPI2CRx SFR is read, one byte from the Receive FIFO output is transfered to
SPI2CRx SFR. A new data from the SPI or I2C bus is written to the FIFO input.
Table 130. SPI Configuration Register SFR (SPIMOD1, 0xE8)
Bit
Location
7-5
Bit
Addr.
Bit
Name
Default Description
Value
0xEF – Reserved
0xEE
0
Reserved
5
0xED
INTMOD
0
SPI Interrupt mode
0: SPI Interrupt set when SPI Rx buffer full
1: SPI interrupt set when SPI Tx buffer empty
Master Mode: SS output control. See Figure 82.
4
0xEC
AUTO_SS
1
0
0
The SS is held low while this bit is clear. This allows manual chip select
control using the SS pin.
1
Single Byte Read or Write: The SS will go low during a single byte
transmission and then return high.
Continuous Transfer: The SS will go low during the duration of the multi-
byte continuous transfer and then return high.
3
0xEB
SSE
Slave Mode: SS input enable
Rev. PrE | Page 130 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
When this bit is set to logic one, the SS pin is defined as the Slave Select input pin
for the SPI slave interface
2
0xEA
RxOFW
0
0
Receive buffer overflow write enable
0
If the SPI2CRX SFR has not been read when a new data byte is
received, the new byte will be discarded.
1
If the SPI2CRX SFR has not been read when a new data byte is
received, the new byte will overwrite the old data.
1-0
0xE9 – SPIR[1:0]
0xE8
Master Mode: SPI SCLK frequency
[1:0]
00
01
10
11
Fcore / 8 = 512kHz if Fcore = 4.096MHz
Fcore / 16 = 256kHz if Fcore = 4.096MHz
Fcore / 32 = 128kHz if Fcore = 4.096MHz
Fcore / 64 = 64kHz if Fcore = 4.096MHz
Table 131. SPI Configuration Register SFR (SPIMOD2, 0xE9)
Bit
Location
Bit
Mnemonic
SPICONT
Default
Value
Description
7
0
SPI continuous transfer mode enable bit
0
1
The SPI interface will stop after one byte is transferred and SS will
be deasserted. A new data transfer can be intiated after a stalled
period.
The SPI interface will continue transferring data until no valid data is
availbale in the SPI2CTx SFR. SS will remain asserted until SPI2CTx
SFR and the transmit shift register is empty.
6
5
SPIEN
0
0
SPI interface enable bit
0
1
The SPI interface is disabled.
The SPI interface is enabled
SPIODO
SPI Open Drain Outputs configuration bit
0
Internal pull-up resistors are connected to the SPI outputs
1
The SPI outputs are open-drain and need external pull-up resistors
4
3
SPIMS_b
SPICPOL
0
0
SPI Master Mode enable bit
0
1
The SPI interface is defined as a Slave
The SPI interface is defined as a Master
SPI clock polarity configuration bit – see Figure 84.
0
The default state of SCLK is low and the first SCLK edge is rising.
Depending on SPICPHA bit, the SPI data output changes state on
the falling or rising edge of SCLK while the SPI data input is sampled
on the rising or falling edge of SCLK.
1
The default state of SCLK is high and the first SCLK edge is falling.
Depending on SPICPHA bit, the SPI data output changes state on
the rising or falling edge of SCLK while the SPI data input is sampled
on the falling or rising edge of SCLK.
2
SPICPHA
0
SPI clock phase configuration bit – see Figure 84.
0
The SPI data output changes state when SS goes low, at the second
edge of SCLK and then every two subsequent edges while the SPI
data input is sampled at the first SCLK edge and then every two
subsequent edges.
1
The SPI data output changes state at the first edge of SCLK and then
every two subsequent edges while the SPI data input is sampled at
the second SCLK edge and then every two subsequent edges.
1
SPILSBF
0
Master Mode: LSB first configuration bit
Rev. PrE | Page 131 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
0
1
The MSB of the SPI outputs is transmitted first
The LSB of the SPI outputs is transmitted first
0
Reserved
1
This bit must be kept as 1.
Table 132. SPI Interrupt Status Register SFR (SPISTAT, 0xEA)
Bit
Location
Interrupt Flag
Default
Value
Description
7
BUSY
0
SPI Peripheral Busy Flag
0
1
The SPI peripheral is idle
The SPI peripheral is busy transferring data in slave or master mode.
6
5
MMERR
SPIRxOF
0
SPI Multi-Master Error Flag
0
1
A multiple master error has not occurred.
If the SS_EN bit is set, enabling the Slave Select input and the SS is asserted
while the SPI peripheral is transferring data as a master, then this flag is raised
to indicate the error. Write a zero to this bit to clear it..
0
SPI Receive Overflow Error Flag.
Reading the SPI2CRx SFR will clear this bit.
SPIRxOF
0
1
The SPI2CRX register contains valid data
This bit is set if the SPI2CRX register is not read before the end of the
next byte transfer. If the RxOF_EN bit is set and this condition occurs,
SPI2CRX will be overwritten.
4
3
Reserved
SPIRxBF
Reserved
0
0
Status bit for SPI Rx buffer. When set the Rx FIFO is full. Reading the SPI2CRx SFR will
clear this bit.
2
1
SPITxUF
SPITxIRQ
Status bit for SPI Tx buffer. When set the Tx FIFO is underflowing and data can be write
into SPI2CTx. Write a zero to this bit to clear it.
0
SPI Transmit Interrupt Flag.
SPITxIRQ
0
1
The SPI2CTX register is full.
This bit is set when the SPI2CTX register is empty. If the SPI/I2C
interrupt is enabled, an interrupt will be generated when this bit is set.
If new data isn’t written into the SPI2CTX SFR before the end of the
current byte transfer, the transfer will stop and the SS will be
deasserted. Write a zero to this bit to clear it..
0
SPITxBF
0
Status bit for SPI Tx buffer. When set, the SPI Tx buffer is full. Write a zero to this bit to
clear it..
SCLK (Serial Clock I/O Pin)
SPI PINS
The master serial clock (SCLK) is used to synchronize the data
MISO (Master In, Slave Out Data I/O Pin)
The MISO pin is configured as an input line in master mode
and as an output line in slave mode. The MISO line on the
master (data in) should be connected to the MISO line in the
slave device (data out).The data is transferred as byte-wide (8-
bit) serial data, MSB first.
being transmitted and received through the MOSI and MISO
data lines. The SCLK pin is configured as an output in master
mode and as an input in slave mode.
In master mode, the bit rate, polarity, and phase of the clock are
controlled by the SPI Configuration Register SFR (SPIMOD1,
0xE8) and SPI Configuration Register SFR (SPIMOD2, 0xE9).
In slave mode, the SPI Configuration Register SFR (SPIMOD2,
0xE9) must be configured with the phase and polarity of the
expected input clock.
In both master and slave modes, the data is transmitted on one
edge of the SCLK signal and sampled on the other. It is
MOSI (Master Out, Slave In Pin)
The MOSI pin is configured as an output line in master mode
and as an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in).The data is transferred as byte-wide (8-bit)
serial data, MSB first.
Rev. PrE | Page 132 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
important, therefore, that CPHA and CPOL are configured the
same for the master and slave devices.
SPI MASTER OPERATING MODES
The double buffered receive and transmit registers can be used
to maximize the throughput of the SPI peripheral by
(Slave Select Pin)
SS
continuously streaming out data in master mode. The
continuous transmit mode is designed to use the full capacity
of the SPI. In this mode, the master will transmit and receive
data until the SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A)
register is empty at the start of a byte transfer. Continuous mode
is enabled by setting the SPICONT bit in the SPI Configuration
Register SFR (SPIMOD2, 0xE9).The SPI peripheral also offers a
single byte read and a single byte write function.
In master mode, the type of transfer is handled automatically
depending on the configuration of bits 0 and 7 of the SPI
Configuration Register SFR (SPIMOD2, 0xE9). Table 133 shows
the sequence of events that should be performed for each
master operating mode. Based on the SS configuration, some of
these events will take place automatically.
In SPI slave mode, a transfer is initiated by the assertion of SS
low. The SPI port will then transmit and receive 8-bit data until
the data is concluded by deassertion of SS. In slave mode, SS is
always an input.
In SPI master mode, the can be used to control data transfer
SS
to a slave device. In the automatic slave select control mode, the
is asserted low to select the slave device and then raised to
SS
deselect the slave device after the transfer is complete.
Automatic slave select control is enabled by setting the
AUTO_SS bit in the SPI Configuration Register SFR (SPIMOD1,
0xE8).
In a multi-master system, the can be configured as an input
SS
so that the SPI peripheral can operate as a slave in some
situations and as a master in other situations. In this case, the
slave selects for the slaves controlled by this SPI peripheral
should be generated with general I/O pins.
Table 133. Procedures for using SPI as a Master
Mode
SPIMOD[7]
= SPICONT
bit
Description of operation
Single Byte
Write
0
Step 1: Write to SPI2CTx SFR
Step 2: SS is asserted low and write routine is initiated
Step 3: SPITxIRQ Interrupt Flag is set when SPI2CTx register is empty
Step 4: SS is deasserted high
Step 5: Write to SPI2CTx SFR to clear SPI2CTxIRQ Interrupt flag
Step 1: Write to SPI2CTx SFR
Continuous
1
Step 2: SS is asserted low and write routine is initiated
Step 3: Wait for SPI2CTxIRQ Interrupt flag to write to SPI2CTx SFR. Transfer will
continue until the SPI2CTX register and transmit shift registers are empty.
Step 4: SPITxIRQ Interrupt Flag is set when SPI2CTx register is empty
Step 5: SS is deasserted high
Step 6: Write to SPI2CTx SFR to clear SPITxIRQ Interrupt flag
Figure 82 shows the SPI output for certain automatic chip select
and continuous mode selections. Note that if the continuous
mode is not used, a short delay is inserted between transfers.
Rev. PrE | Page 133 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
The SPI interface has several status flags that indicate the status
of the double buffered receive and transmit registers. Figure 83
shows when the status and interrupt flags are raised. The
transmit interrupt occurs when the transmit shift register is
loaded with the data in the SPI/I2C Transmit Buffer SFR
(SPI2CTx, 0x9A) register. If the SPI/I2C Transmit Buffer SFR
(SPI2CTx, 0x9A) register has not been written with new data by
the beginning of the next byte transfer, the transmit operation
stops.
SS
SCLK
AUTO_SS=1
SPICONT=1
DIN
DIN1
DIN2
DOUT
DOUT1
DOUT2
When a new byte of data is received in the SPI Receive Buffer
SFR (SPI2CRx, 0x9B) register, the SPI receive interrupt flag is
raised. If the data in the SPI Receive Buffer SFR (SPI2CRx,
0x9B) register is not read before new data is ready to be loaded
into the SPI Receive Buffer SFR (SPI2CRx, 0x9B), an overflow
condition has occurred. This overflow condition, indicated by
the SPIRxOF flag, will force the new data to be discarded or
overwritten if the RxOF_EN bit is set.
SS
SCLK
AUTO_SS=1
SPICONT=0
DIN
DIN1
DIN2
DOUT
DOUT1
DOUT2
SPITX
SPIRX
SPITxIRQ=1
SPIRxIRQ=1
SS
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
SCLK
SPITX (empty)
SPIRX (full)
Stops Transfer if TIMODE=1
TRANSMIT SHIFT REGISTER
SPIRxOF=1
RECEIVE SHIFT REGISTER
AUTO_SS=0
SPICONT=0
(manual SS control)
DIN
DIN1
DIN2
Figure 83: SPI Receive and Transmit Interrupt and Status Flags
DOUT
DOUT1
DOUTz2
Figure 82: Automatic Chip Select and Continuous Mode Output
SPI INTERRUPT AND STATUS FLAGS
Rev. PrE | Page 134 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL = 0)
SS_b
?
?
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MISO
MOSI
SPICPHA = 1
SPIRx1 and
SPITx1 Flags
SPIRx0 and
SPITx0 Flags
?
MISO
MOSI
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
?
SPICPHA = 0
SPIRx1 and
SPITx1 Flags
SPIRx0 and
SPITx0 Flags
Figure 84. SPI timing configurations
Rev. PrE | Page 135 of 148
Preliminary Technical Data
I2C COMPATIBLE INTERFACE
ADE75xx/ADE71xx
is initiated. This continues until the master issues a STOP
condition and the bus becomes idle.
The ADE75XX/ADE71XX supports a fully licensed* I2C
interface. The I2C interface is implemented as a full hardware
master.
SERIAL CLOCK GENERATION
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
Fast mode (256 kHz) or Standard mode (32 kHz).
SDATA is the data I/O pin, and SCLK is the serial clock. These
two pins are shared with the MOSI and SCLK pins of the on-
chip SPI interface. Therefore, the user can enable only one
interface or the other on these pins at any given time. The SCPS
bit in the CFG SFR selects which peripheral is active.
The bit-rate is defined in the I2CMODE SFR as follow:
fcore
16× 2SCLDIV [1:0]
fSCL
=
The two pins used for data transfer, SDA and SCL are
configured in a Wired-AND format that allows arbitration in a
multi-master system.
SLAVE ADDRESSES
The I2CADR SFR contains the slave device ID. The LSB of this
register contains a read/write request. A write to this SFR will
start the I2C communication.
The transfer sequence of a I2C system consists of a master
device initiating a transfer by generating a START condition
while the bus is idle. The master transmits the address of the
slave device and the direction of the data transfer in the initial
address transfer. If the slave acknowledges then the data transfer
I2C SFR REGISTER LIST
The I2C peripheral interface consists of five SFRs:
-
-
-
-
-
I2CMOD
I2CSTAT
I2CADR
SPI2CTx
SPI2CRx.
As the SPI and I2C serial interfaces share the same pins, I2CMOD, I2CADR, I2CSTAT, SPI2CTx and SPI2CRx SFRs are also shared with
SPIMOD1, SPIMOD2, SPISTAT, SPI2CTx and SPI2CRx SFRs respectively.
SFR Address
Name
R/W Length
Default Description
Value
0x9A
0x9B
0xE8
0xE9
0xEA
SPI2CTx
SPI2CRx
I2CMOD
I2CADR
I2CSTAT
W
8
8
8
8
8
SPI Data out register
R
0
0
0
0
SPI Data in register
R/W
R/W
R/W
SPI configuration register
SPI configuration register
SPI/I2C Interrupt Status register
Table 134: SPI SFR register list
Table 13ꢀ. I2C Mode Register SFR (I2CMOD, 0xE8)
Bit
Location
Bit
Addr.
Bit
Name
I2CEN
Default Description
Value
7
0xEF
0
I2C enable bit
When this bit is set to logic one, the I2C interface is enabled. A write to the
I2CADR SFR will start a communication
6-5
0xEE – I2CR[1:0]
0xED
0
I2C SCLK frequency
[1:0]
Rev. PrE | Page 136 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
00
01
10
11
Fcore / 16 = 256kHz if Fcore = 4.096MHz
Fcore / 32 = 128kHz if Fcore = 4.096MHz
Fcore / 64 = 64Hz if Fcore = 4.096MHz
Fcore / 128= 32kHz if Fcore = 4.096MHz
4-0
0xEC – I2CRCT[4:0]
oxE8
0
Configures the length of the I2C received FIFO buffer. The I2C peripheral
will stop when I2CRCT[4:0] + 1 bytes have been read or if an error has
occured
Table 136. I2C Slave Address SFR (I2CADR, 0xE9)
Bit
Location
7-1
Bit
Mnemonic
I2CSLVADR
Default
Value
Description
0
Address of the I2C slave being adressed
Writing to this register start the I2C transmission (Read or write)
Command bit for Read or Write
0
I2CR_W
0
When this bit is set to logic one, a read command will be transmitted on
the I2C bus. Data from slave in SPI2CRx SFR is expected after command
byte
When this bit is set to logic zero, a write command will be transmitted on
the I2C bus. Data to slave is expected in SPI2CTx SFR
Table 137. I2C Interrupt Status Register SFR (I2CSTAT, 0xEA)
Bit
Location
Bit
Mnemonic
I2CBUSY
Default
Value
Description
7
0
This bit is set to logic one when the I2C interface is used. When this bit is
set by user code, the Tx FIFO is emptied
6
I2CNOACK
0
I2C no acknlowledgement transmit interrupt
This bit is set to logic one when the slave device did not send an
acknlowledgement. The I2C communication is stopped after this event.
Write a zero to this bit to clear it.
5
I2CRxIRQ
0
0
0
I2C receive interrupt
This bit is set to logic one when the receive FIFO is not empty
Write a zero to this bit to clear it.
4
I2CTxIRQ
I2C transmit interrupt
This bit is set to logic one when the transmit FIFO is empty
Write a zero to this bit to clear it.
3-2
I2CFIFOSTAT[1:0]
Status bit for 3 or 4 bytes deep I2C FIFO. The FIFO monitored in these 2
bits is the one currently used in I2C communication (Receive or Transmit)
as only one of them is active at a time
[1:0]
00
01
10
11
FIFO empty
Reserved
FIFO Half full
FIFO Full
1
0
I2CACC_ERR
0
0
Set when trying to write and read at the same time. Write a zero to this bit
to clear it.
I2CTxWR_ERR
Set when write was attempted when I2C transmit FIFO was full. Write a
zero to this bit to clear it.
An I2C interrupt occurs
*
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use the ADE7XXX in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
READ AND WRITE OPERATIONS
Rev. PrE | Page 137 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Figure 85 and Figure 86 depict I2C read and write operations, respectively. Note that the LSB of the I2CADR register is used to select
whether a read or write operation is performed on the slave device. During the read operation, the master acknowledges are generated
automatically by the I2C peripheral. The master generated NACK before the end of a read operation is also generated automatically after
I2CRCT[4:0] bytes have been read from the slave. If the I2CADR register is updated during a transmission, instead of generating a STOP
at the end of the read or write operation, the master will generate a START condition and continue with the next communication.
1
9
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
ACK BY
SLAVE
ACK BY
MASTER
NACK BY
STOP BY
MASTER MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE 1 FROM SLAVE
FRAME N+1
DATA BYTE N FROM SLAVE
Figure 85: I2C Read operation
1
9
1
9
SCL
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
SDA
START BY
ACK BY
SLAVE
ACK BY
SLAVE
STOP BY
MASTER
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE 1 FROM MASTER
Figure 86: I2C Write operation
full. If the peripheral is reading from a slave address, the
communication will stop once the number of received bytes
equals the number set in the I2CRCT[4:0] bits. An error such as
not receiving an acknowledge will also cause the
communication to terminate.
I2C RECEIVE AND TRANSMIT FIFOS
The I2C peripheral has a four byte receive FIFO and a four byte
transmit FIFO. The buffers reduce the overhead associated with
using the I2C peripheral. Figure 87 shows the operation of the
I2C receive and transmit FIFOs.
Code to read RX FIFO:
Code to fill TX FIFO:
MOV A, I2CRX
MOV A, I2CRX
MOV A, I2CRX
MOV A, I2CRX
; Result: A=RXDATA1
; Result: A=RXDATA2
; Result: A=RXDATA3
; Result: A=RXDATA4
MOV I2CTX, TXDATA1
MOV I2CTX, TXDATA2
MOV I2CTX, TXDATA3
MOV I2CTX, TXDATA4
The TX FIFO can be loaded with four bytes to be transmitted to
the slave at the beginning of a write operation. When the
transmit FIFO is empty, the I2C transmit interrupt flag will be
set and the PC will vector to the I2C interrupt vector if this
interrupt is enabled. If a new byte is not loaded into the TX
FIFO before it is needed in the transmit shift register, the
communication will stop. An error such as not receiving an
acknowledge will also cause the communication to terminate. In
case of an error during a write operation, the TX FIFO will be
flushed.
I2CRX
I2CTX
TXDATA4
TXDATA3
RXDATA1
RXDATA2
RXDATA3
RXDATA4
4 Byte FIFO
4 Byte FIFO
TXDATA2
TXDATA1
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
Figure 87: I2C FIFO operation
The RX FIFO allows four bytes to be read in from the slave
before the MCU has to read the data. A receive interrupt can be
generated after each byte is received or when the RX FIFO is
Rev. PrE | Page 138 of 148
Preliminary Technical Data
DUAL DATA POINTERS
ADE75xx/ADE71xx
the data pointer control SFR (DPCON). DPCON features
automatic hardware post-increment and post-decrement as well
as an automatic data pointer toggle.
The ADE75XX/ADE71XX incorporates two data pointers. The
second data pointer is a shadow data pointer and is selected via
Table 138. Data Pointer Control SFR SFR (DPCON, 0xA7)
Bit
Bit
Default
Value
Description
Location Mnemonic
7
6
----
0
0
Not Implemented. Write Don’t Care.
DPT
Data Pointer Automatic Toggle Enable.
Cleared by the user to disable auto swapping of the DPTR.
Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC
instruction.
5, 4
DP1m1,
DP1m0
0
Shadow Data Pointer Mode. These bits enable extra modes of the shadow data pointer
operation, allowing more compact and more efficient code size and execution.
DP1m1 DP1m0 Behavior of the Shadow Data Pointer
0
0
1
1
0
1
0
1
8052 behavior.
DPTR is post-incremented after a MOVX or a MOVC instruction.
DPTR is post-decremented after a MOVX or MOVC instruction.
DPTR LSB is toggled after a MOVX or MOVC instruction. (This
instruction can be useful for moving 8-bit blocks to/from 16-bit
devices.)
3, 2
DP0m1,
DP0m0
0
Main Data Pointer Mode. These bits enable extra modes of the main data pointer operation,
allowing more compact and more efficient code size and execution.
DP0m1 DP0m0 Behavior of the Main Data Pointer
0
0
1
1
0
1
0
1
8052 behavior.
DPTR is post-incremented after a MOVX or a MOVC instruction.
DPTR is post-decremented after a MOVX or MOVC instruction.
DPTR LSB is toggled after a MOVX or MOVC instruction. (This
instruction is useful for moving 8-bit blocks to/from 16-bit devices.)
1
0
----
0
0
Not Implemented. Write Don’t Care.
Data Pointer Select.
DPSEL
Cleared by the user to select the main data pointer. This means that the contents of this 16-
bit register are placed into the DPL, and DPH SFRs.
Set by the user to select the shadow data pointer. This means that the contents of a separate
16-bit register appear in the DPL, and DPH SFRs.
Note the following:
•
The Dual Data Pointer section is the only place in which
main and shadow data pointers are distinguished.
Rev. PrE | Page 139 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
Whenever the DPTR is mentioned elsewhere in this data
sheet, active DPTR is implied.
•
Only the MOVC/MOVX @DPTR instructions
automatically post-increment and post-decrement the
DPTR. Other MOVC/MOVX instructions, such as MOVC
PC or MOVC @Ri, do not cause the DPTR to automatically
post-increment and post-decrement.
To illustrate the operation of DPCON, the following code copies
256 bytes of code memory at Address D000H into XRAM,
starting from Address 0000H.
MOV DPTR,#0
;Main DPTR = 0
MOV DPCON,#55H
;Select shadow DPTR
;DPTR1 increment mode
;DPTR0 increment mode
;DPTR auto toggling ON
MOV DPTR,#0D000H ;DPTR = D000H
MOVELOOP: CLR A
MOVC A,@A+DPTR
;Get data
;Post Inc DPTR
;Swap to Main DPTR(Data)
;Put ACC in XRAM
MOVX @DPTR,A
;Increment main DPTR
;Swap Shadow DPTR(Code)
MOV A, DPL
JNZ MOVELOOP
Rev. PrE | Page 140 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Figure 88 shows a typical bit latch and I/O buffer for an I/O pin.
The bit latch (one bit in the port’s SFR) is represented as a Type
D flip-flop, which clocks in a value from the internal bus in
response to a write to latch signal from the CPU. The Q output
of the flip-flop is placed on the internal bus in response to a
read latch signal from the CPU. The level of the port pin itself is
placed on the internal bus in response to a read pin signal from
the CPU. Some instructions that read a port activate the read
latch signal, and others activate the read pin signal. See the
Read-Modify-Write Instructions section for details.
I/O PORTS
PARALLEL I/O
The ADE75XX/ADE71XX uses three input/output ports to
exchange data with external devices. In addition to performing
general-purpose I/O, some are capable of driving an LCD or
performing other alternate functions for the peripheral
functions available on-chip. In general, when a peripheral is
enabled, the pins associated with it cannot be used as a general-
purpose I/O. The I/O port can be configured through the SFRs
in Table 139.
Weak Internal Pullups Enabled
Table 139. I/O port SFRs
A pin with the weak internal pull-up enabled is used as an input
by writing a 1 is written to the pin. The pin will be pulled high
by the internal pull-ups and the pin will be read using the
circuitry shown in Figure 88. If the pin is driven low externally,
it will source current because of the internal pull-ups.
SFR
Address Bit
Addressable
Description
P0
0x80
0x90
0xA0
0x9F
Yes
Port 0 register
Port 1 register
Port 2 register
P1
Yes
Yes
No
If used as an output, a pin with an internal pull-up enabled, will
be written with a 1 or a 0 to control the level of the output. If a 0
is written to the pin, it will drive a logic low output voltage (VOL)
and is capable of sinking TBD mA.
P2
EPCFG
Extended Port
Configuration
Open Drain (Weak Internal Pull-ups Disabled)
When the weak internal pull-up on a pin is disabled, the pin
becomes open drain. To use this open-drain pin as a high
impedance input, a 1 is written to the pin. The pin will be read
using the circuitry shown in Figure 88. The open drain option
is preferable for inputs because it draws less current than the
internal pull-ups were enabled.
PINMAP0 0xB2
PINMAP1 0xB3
PINMAP2 0xB4
No
No
No
No
Port 0 weak pull-up
enable
Port 1 weak pull-up
enable
Port 2 weak pull-up
enable
To use an open-drain pin as a general purpose output, an
external pull-up resistor is required. Open drain outputs are
convenient for changing the voltage to a logic high. The
ADE75XX/ADE71XX is a 3.3V device so an external resistor
pulled up to 5V may ease interfacing to a 5V IC although most
5V ICs are tolerant of 3.3V inputs. Pins with 0s written to them
drive a logic low output voltage (VOL) and are capable of sinking
1.6 mA.
INTPR
0xFF
Interrupt pin
configuration
The three bidirectional I/O ports have internal pull-ups that can
be enabled or disabled individually for each pin. The internal
pull-ups are enabled by default. Disabling an internal pull-up
causes a pin to become open-drain. Weak internal pull-ups are
configured through PINMAPx SFRs.
38 kHz Modulation
DV
DD
The ADE75XX/ADE71XX provides a 38 kHz modulation
signal. The 38 kHz modulation is accomplished by internally
ORing the level written to the MOD38 pin with a 38 kHz square
wave. Then when a zero is written to the MOD38 pin, it is
modulated as shown in Figure 89.
INTERNAL
PULL-UP
ALTERNATE
OUTPUT
FUNCTION
READ
LATCH
Closed: PINMAPx.x=0
Open: PINMAPx.x=1
Px.x
PIN
INTERNAL
BUS
D
Q
Q
Level written to MOD38
WRITE
TO LATCH
CL
LATCH
38kHz Modulation Signal
Output at MOD38 Pin
READ
PIN
ALTERNATE
INPUT
FUNCTION
Figure 89: 38 kHz Modulation
Figure 88. Port 0 Bit Latch and I/O Buffer
Uses for this 38 kHz modulation include IR modulation of a
Rev. PrE | Page 141 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
UART transmit signal or a low power signal to drive a LED. The
modulation can be enabled or disabled with the MOD38EN bit
in the CFG SFR. The 38 kHz modulation is available on eight
pins, selected by the MOD38[7:0] bits in the Extended Port
Configuration SFR (EPCFG, 0x9F).
I/O SFR REGISTER LIST
Table 140. Extended Port Configuration SFR (EPCFG, 0x9F)
Bit
Location
Bit
Default
Value
Description
Mnemonic
MOD38_FP21
MOD38_FP22
MOD38_FP23
MOD38_TxD
MOD38_CF1
MOD38_SSb
7
6
5
4
3
2
0
0
0
0
0
0
0
0
Enable 38kHz modulation on P1.6/FP21 pin
Enable 38kHz modulation on P1.5/FP22 pin
Enable 38kHz modulation on P1.4/FP23/T2 pin
Enable 38kHz modulation on P1.1/Tx pin
Enable 38kHz modulation on P0.2/CF1/RTCCAL pin
Enable 38kHz modulation on P0.7/SS/T1pin
Enable 38kHz modulation on P0.5/MISO pin
Enable 38kHz modulation on P0.3/CF2 pin
1
0
MOD38_MISO
MOD38_CF2
Table 141. Port 0 Weak pull-up enable SFR (PINMAP0, 0xB2)
Bit
Location
Bit
Default
Value
Description
Mnemonic
PINMAP0.7
PINMAP0.6
PINMAP0.5
PINMAP0.4
PINMAP0.3
PINMAP0.2
PINMAP0.1
PINMAP0.0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
The weak pull-up on P0.7 is disabled when this bit is set
The weak pull-up on P0.6 is disabled when this bit is set
The weak pull-up on P0.5 is disabled when this bit is set
The weak pull-up on P0.4 is disabled when this bit is set
The weak pull-up on P0.3 is disabled when this bit is set
The weak pull-up on P0.2 is disabled when this bit is set
The weak pull-up on P0.1 is disabled when this bit is set
The weak pull-up on P0.0 is disabled when this bit is set
Table 142. Port 1 Weak pull-up enable SFR (PINMAP1, 0xB3)
Bit
Location
Bit
Default
Value
Description
Mnemonic
PINMAP1.7
PINMAP1.6
PINMAP1.5
PINMAP1.4
PINMAP1.3
PINMAP1.2
PINMAP1.1
PINMAP1.0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
The weak pull-up on P1.7 is disabled when this bit is set
The weak pull-up on P1.6 is disabled when this bit is set
The weak pull-up on P1.5 is disabled when this bit is set
The weak pull-up on P1.4 is disabled when this bit is set
The weak pull-up on P1.3 is disabled when this bit is set
The weak pull-up on P1.2 is disabled when this bit is set
The weak pull-up on P1.1 is disabled when this bit is set
The weak pull-up on P1.0 is disabled when this bit is set
Table 143. Port 2 Weak pull-up enable SFR (PINMAP2, 0xB4)
Bit
Location
Bit
Default
Value
Description
Mnemonic
Reserved
PINMAP2.5
Reserved
PINMAP2.3
PINMAP2.2
PINMAP2.1
PINMAP2.0
7 - 6
5
0
0
0
0
0
0
0
Reserved. Should be left cleared
The weak pull-up on Reset is disabled when this bit is set
The weak pull-up on EA is disabled when this bit is set
Reserved. Should be left cleared
4
3
2
The weak pull-up on P2.2 is disabled when this bit is set
The weak pull-up on P2.1 is disabled when this bit is set
The weak pull-up on P2.0 is disabled when this bit is set
1
0
Rev. PrE | Page 142 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Table 144. Port 0 SFR (P0, 0x80)
Note: When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set
Bit Location Bit
Addr.
Bit
Name
Default
Value
Description
7
6
5
4
3
2
1
0
0x87
0x86
0x85
0x84
0x83
0x82
0x81
0x80
T1
T0
1
1
1
1
1
1
1
1
This bit reflects the state of P0.7/SS/T1 pin. It can be written or read.
This bit reflects the state of P0.6/SCLK/T0 pin. It can be written or read.
This bit reflects the state of P0.5/MISO pin. It can be written or read.
This bit reflects the state of P0.4/MOSI/SDATA pin. It can be written or read.
This bit reflects the state of P0.3/CF2 pin. It can be written or read.
This bit reflects the state of P0.2/CF1/RTCCAL pin. It can be written or read.
This bit reflects the state of P0.1 pin. It can be written or read.
CF2
CF1
INT1
This bit reflects the state of P0.0/INT1/BCTRL pin. It can be written or read.
Table 14ꢀ. Port 1 SFR (P1, 0x90)
Note: When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set
Bit Location Bit
Addr.
Bit
Name
Default Description
value
7
6
5
4
3
2
1
0
0x97
0x96
0x95
0x94
0x93
0x92
0x91
0x90
1
1
1
1
1
1
1
1
This bit reflects the state of P1.7 pin. It can be written or read.
This bit reflects the state of P1.6 pin. It can be written or read.
This bit reflects the state of P1.5 pin. It can be written or read.
This bit reflects the state of P1.4/T2 pin. It can be written or read.
This bit reflects the state of P1.3/T2EX pin. It can be written or read.
This bit reflects the state of P1.2 pin. It can be written or read.
This bit reflects the state of P1.1/TxD pin. It can be written or read.
This bit reflects the state of P1.0/RxD pin. It can be written or read.
T2
T2EX
TxD
RxD
Table 146. Port 2 SFR (P2, 0xA0)
Note: When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set
Bit Location Bit
Addr.
Bit
Name
Default Description
Value
7 - 2
0x97 –
0x92
0x3F
These bits are unused and should be left set
1
0
0x91
0x90
P2.1
P2.0
1
1
This bit reflects the state of P2.1 pin. It can be written or read.
This bit reflects the state of P2.0 pin. It can be written or read.
Interrupt pins configuration SFR (INTPR, 0xFF)
Bit
Bit
Default
Value
0
Description
Location Mnemonic
7
RTCCAL
Control RTC calibration output
When set, the RTC calibration frequency selected by FSEL[1:0] is
output on the P0.2/CF1/RTCCAL pin.
6-5
FSEL[1:0]
Sets RTC calibration output frequency and calibration window
FSEL[1:0]
Calibration window, frequency
30.5 seconds, 1Hz
0
0
1
1
0
1
0
1
30.5 seconds, 512 Hz
0.244 seconds, 500Hz
0.244 seconds, 16.384 kHz
4
Reserved
3-1
INT1PRG[2:0]
000
Controls the function of INT1T
INT1PRG[2:0] Function
Rev. PrE | Page 143 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
x
0
0
GPIO
x
0
1
0
1
1
1
x
x
BCTRL
INT1 input disabled
INT1 input enabled
0
INT0PRG
0
Controls the function of INT0
INT0PRG
Function
0
1
INT0 input disabled
INT0 input enabled
Table 147.Table 148. Port 0 Alternate Functions
Pin
No.
Alternate Function
Alternate Function Enable
P0.0
BCTRL external battery control input
Set INT1PROG[2:0]=X01 in the Interrupt pins configuration
SFR (INTPR, 0xFF)
INT1 external interrupt
Set EX1 in the Interrupt Enable SFR (IE, 0xA8).
INT1 wakeup from PSM2 operating mode
FP19 LCD Segment Pin
Set INT1PROG[2:0]=11X in the Interrupt pins configuration
SFR (INTPR, 0xFF)
P0.1
P0.2
Set FP19EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED)
CF1 ADE Calibration Frequency output
RTC Calibration output
Clear the DISCF1 bit in the ADE energy measurement
internal MODE1 register (0x0B)
Select the calibration window and frequency options and
then set the RTCCAL bit in the Interrupt pins configuration
SFR (INTPR, 0xFF)
Note: The RTC Calibration output has priority over the CF1 output, so if the DISCF1 in the MODE1 register
(0x0B) is clear and RTCCAL bit in the Interrupt pins configuration SFR (INTPR, 0xFF) is set, the P0.2/CF1/RTCCAL
pin will follow the RTC Calibration output.
P0.2
P0.3
P0.4
CF1 ADE Calibration Frequency output
CF2 ADE Calibration Frequency output
MOSI SPI Data line
Clear the DISCF1 bit in the ADE energy measurement
internal MODE1 register (0x0B)
Clear the DISCF2 bit in the ADE energy measurement
internal MODE1 register (0x0B)
Set the SCPS bit in the CFG SFR and set the SPIEN bit in the
SPI Configuration Register SFR (SPIMOD1, 0xE8).
SDATA I2C Data line
Clear the SCPS bit in the Configuration SFR (CFG, 0xAF) and
set the I2CEN bit in the I2C Mode Register SFR (I2CMOD,
0xE8).
P0.5
P0.6
MISO SPI Data line
Set the SCPS bit in the Configuration SFR (CFG, 0xAF) and set
the SPIEN bit in the SPI Configuration Register SFR
(SPIMOD2, 0xE9)
SCLK serial clock for I2C or SPI
Set the I2CEN bit in the I2CMOD SFR or the SPIEN bit in the
SPI Configuration Register SFR (SPIMOD2, 0xE9) to enable
the I2C or SPI interface
T0 Timer0 input
Set the CNT0 bit in the Timer/Counter 0 and 1 Mode SFR
(TMOD, 0x89) to enable T0 as an external event counter
P0.7
SS SPI slave select input for SPI in slave mode
Set the SS_EN bit in the SPI Configuration Register SFR
(SPIMOD1, 0xE8)
SS SPI slave select output for SPI in master
mode
Set the SPIMS_b bit in the SPI Configuration Register SFR
(SPIMOD2, 0xE9)
T1 Timer 1 input
Set the CNT1 bit in the Timer/Counter 0 and 1 Mode SFR
(TMOD, 0x89) to enable T1 as an external event counter
Rev. PrE | Page 144 of 148
Preliminary Technical Data
ADE75xx/ADE71xx
Table 149. Port 1 Alternate Functions
Pin
No.
Alternate Function
Alternate Function Enable
P1.0
RxD Receiver Data Input for UART
RX Edge wakeup from PSM2 operating mode
Set the REN bit in the SCON SFR Bit Description SFR (SCON,
0x98).
Set RXPROG[1:0]=11 in the Peripheral Configuration SFR
(PERIPH, 0xF4)
P1.1
P1.2
P1.3
TxD Transmitter Data Output for UART
FP25 LCD Segment Pin
FP24 LCD Segment Pin
T2EX Timer 2 control input
FP23 LCD Segment Pin
T2 Timer 2 input
Set FP25EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set FP24EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set EXEN2 in the Timer/Counter 2 Control SFR (T2CON, 0xC8)
Set FP23EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
P1.4
Set the CNT2 bit in the Timer/Counter 2 Control SFR (T2CON,
0xC8) to enable T2 as an external event counter
P1.5
P1.6
P1.7
FP22 LCD Segment Pin
FP21 LCD Segment Pin
FP20 LCD Segment Pin
Set FP22EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set FP21EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set FP20EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Table 1ꢀ0. Port 2 Alternate Functions
Pin
No.
Alternate Function
Alternate Function Enable
P2.0
P2.1
P2.2
P2.3
FP18 LCD Segment Pin
FP17 LCD Segment Pin
FP16 LCD Segment Pin
Set FP18EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED)
Set FP17EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED)
Set FP16EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED)
SDEN Serial Download pin sampled on reset.
P2.3 is an output only.
Enabled by default.
PORT 0
Port 0 is controlled directly through the bit-addressable Port 0 SFR (80H). The weak internal pull-ups for Port 0 are configured through
the Port 0 Weak pull-up enable SFR (PINMAP0, 0xB2); they are enabled by default. Disable the weak internal pull-up by writing a one to
P0CFG..x.
Port 0 pins also have various secondary functions as described in Interrupt pins configuration SFR (INTPR, 0xFF)
Bit
Bit
Default
Value
0
Description
Location Mnemonic
7
RTCCAL
Control RTC calibration output
When set, the RTC calibration frequency selected by FSEL[1:0] is
output on the P0.2/CF1/RTCCAL pin.
6-5
FSEL[1:0]
Sets RTC calibration output frequency and calibration window
FSEL[1:0]
Calibration window, frequency
30.5 seconds, 1Hz
0
0
1
1
0
1
0
1
30.5 seconds, 512 Hz
0.244 seconds, 500Hz
0.244 seconds, 16.384 kHz
4
Reserved
3-1
INT1PRG[2:0]
000
Controls the function of T
INT1PRG[2:0] Function
GPIO
x
0
0
Rev. PrE | Page 145 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
x
0
1
0
1
1
1
x
x
BCTRL
input disabled
input enabled
0
INT0PRG
0
Controls the function of
INT0PRG
Function
0
1
input disabled
input enabled
Table 147.Table 148. The alternate functions of Port 0 pins can be activated only if the corresponding bit latch in the P0 SFR contains a 1.
Otherwise, the port pin remains at 0.
PORT 1
Port 1 is an 8-bit bidirectional port controlled directly through the bit-addressable Port 1 SFR (90H). The weak internal pull-ups for Port
1 are configured through the Port 1 Weak pull-up enable SFR (PINMAP1, 0xB3); they are enabled by default. Disable the weak internal
pull-up by writing a one to P1CFG..x.
Port 1 pins also have various secondary functions as described in Table 149. The alternate functions of Port 1 pins can be activated only if
the corresponding bit latch in the P1 SFR contains a 1. Otherwise, the port pin remains at 0.
PORT 2
Port 2 is a 4-bit bidirectional port controlled directly through the bit-addressable Port 2 SFR (A0H). Note that P2.3 can be used as an
output only. The weak internal pull-ups for Port 2 are configured through the Port 2 Weak pull-up enable SFR (PINMAP2, 0xB4); they are
enabled by default. Disable the weak internal pull-up by writing a one to P2CFG..x.
Port 2 pins also have various secondary functions as described in Table 150. The alternate functions of Port 2 pins can be activated only if
the corresponding bit latch in the P2 SFR contains a 1. Otherwise, the port pin remains at 0.
Rev. PrE | Page 146 of 148
Preliminary Technical Data
OUTLINE DIMENSIONS
ADE75xx/ADE71xx
LQFP package
LFCSP package17
Dimensions shown in millimeters
17 Please contact your Analog Devices representative to check availability of this package
Rev. PrE | Page 147 of 148
ADE75xx/ADE71xx
Preliminary Technical Data
SELECTION GUIDE
Table 1ꢀ1. Selection Guide
Part Number
ADE7166
ADE7169
ADE7566
ADE7569
Antitamper
W + VA + rms
VAR
No
5V LCD
Yes
RTC
Yes
Yes
Yes
Yes
Flash (kB)
Package
Yes
Yes
No
No
Yes
Yes
Yes
Yes
8/16
16
64-LQFP or LFCSP
64-LQFP or LFCSP
64-LQFP or LFCSP
64-LQFP or LFCSP
Yes
No
Yes
Yes
8/16
16
Yes
Yes
ORDERING GUIDE
Table 1ꢀ2. Ordering Guide
Model
Package Description
Package Option*
LQFP-64
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
ADE7169ASTZF16
64-Lead Lead Free LQFP
ADE7169ASTZF16-RL
ADE7169ACPZF161
ADE7169ACPZF16-RL1
ADE7166ASTZF16
64-Lead Lead Free LQFP in Reel
64-Lead Lead Free CSP
LQFP-64
LFCSP-641
LFCSP-641
LQFP-64
64-Lead Lead Free CSP in Reel
64-Lead Lead Free LQFP
ADE7166ASTZF16-RL
ADE7166ACPZF161
ADE7166ACPZF16-RL1
ADE7166ASTZF8
64-Lead Lead Free LQFP in Reel
64-Lead Lead Free CSP
LQFP-64
LFCSP-641
LFCSP-641
LQFP-64
64-Lead Lead Free CSP in Reel
64-Lead Lead Free LQFP
ADE7166ASTZF8-RL
ADE7166ACPZF81
ADE7166ACPZF8-RL1
64-Lead Lead Free LQFP in Reel
64-Lead Lead Free CSP
LQFP-64
LFCSP-641
LFCSP-641
LQFP-64
64-Lead Lead Free CSP in Reel
64-Lead Lead Free LQFP
ADE7569ASTZF16
ADE7569ASTZF16-RL
ADE7569ACPZF161
ADE7569ACPZF16-RL1
ADE7566ASTZF16
64-Lead Lead Free LQFP in Reel
64-Lead Lead Free CSP
LQFP-64
LFCSP-641
LFCSP-641
LQFP-64
64-Lead Lead Free CSP in Reel
64-Lead Lead Free LQFP
ADE7566ASTZF16-RL
ADE7566ACPZF161
ADE7566ACPZF16-RL1
ADE7566ASTZF8
64-Lead Lead Free LQFP in Reel
64-Lead Lead Free CSP
LQFP-64
LFCSP-641
LFCSP-641
LQFP-64
64-Lead Lead Free CSP in Reel
64-Lead Lead Free LQFP
ADE7566ASTZF8-RL
ADE7566ACPZF81
ADE7566ACPZF8-RL1
64-Lead Lead Free LQFP in Reel
64-Lead Lead Free CSP
LQFP-64
LFCSP-641
LFCSP-641
64-Lead Lead Free CSP in Reel
ADE7169 Evaluation Board
EVAL-ADE7169F16EB
1 Please contact your Analog Devices representative to check availability of this package
©
2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06717-0-1/07(PrE)
Rev. PrE | Page 148 of 148
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