ADE7761BARS-RL_技术文档

Energy Metering IC with On-Chip Fault and

Missing Neutral Detection

ADE7761B

FEATURES

GENERAL DESCRIPTION

High accuracy, active energy measurement IC supports

IEC 62053-21

Less than 0.1% error over a dynamic range of 1000 to 1

Supplies active power on the frequency outputs, F1 and F2

High frequency output CF is intended for calibration and

supplies instantaneous active power

Continuous monitoring of the phase and neutral current

allows fault detection in 2-wire distribution systems

Current channel input level best suited for shunt and current

transformer sensors

Uses the larger of the two currents (phase or neutral) to bill,

even during a fault condition

Continuous monitoring of the voltage and current inputs

allows missing neutral detection

Uses one current input (phase or neutral) to bill when

missing neutral is detected

Two logic outputs (FAULT and REVP) can be used to indicate

a potential miswiring, fault, or missing neutral condition

Direct drive for electromechanical counters and 2-phase

stepper motors (F1 and F2)

Proprietary ADCs and DSP provide high accuracy over large

variations in environmental conditions and time

Reference 2.5 V 8% (drift 30 ppm/°C typical) with external

overdrive capability

The ADE7761B is a high accuracy, fault-tolerant, electrical energy

measurement IC intended for use with 2-wire distribution systems.

The part specifications surpass the accuracy requirements as

quoted in the IEC 62053-21 standard. The only analog circuitry

used on the ADE7761B is in the ADCs and reference circuit.

All other signal processing (such as multiplication and filtering)

is carried out in the digital domain. This approach provides

superior stability and accuracy over extremes in environmental

conditions and over time. The ADE7761B incorporates a fault

detection scheme similar to the ADE7751 by continuously

monitoring both phase and neutral currents. A fault is indicated

when the currents differ by more than 6.25%.

The ADE7761B incorporates a missing neutral detection scheme

by continuously monitoring the input voltage. When a missing

neutral condition is detected (no voltage input), the ADE7761B

continues billing based on the active current signal (see the

Missing Neutral Mode section). The missing neutral condition

is indicated when the FAULT pin goes high. The ADE7761B

supplies average active power information on the low frequency

outputs, F1 and F2. The CF logic output gives instantaneous

active power information.

The ADE7761B includes a power supply monitoring circuit on

the V_DDsupply pin. Internal phase matching circuitry ensures

that the voltage and current channels are matched. An internal

no-load threshold ensures that the ADE7761B does not exhibit

any creep when there is no load.

Single 5 V supply, low power

FUNCTIONAL BLOCK DIAGRAM

V

PGA AGND

FAULT

15

DD

1

13

8

POWER

SUPPLY MONITOR

V

2

4

1A

1N

1B

ADE7761B

SIGNAL PROCESSING

BLOCK

ADC

HPF

A > B

LPF

B > A

A ≠ B

3

7

ZERO-CROSSING

DETECTION

MISSING NEUTRAL

GAIN ADJUST

MISCAL

6

5

V

2P

MISSING NEUTRAL

DETECTION

2N

3kΩ

2.5V

REFERENCE

INTERNAL

OSCILLATOR

DIGITAL-TO-FREQUENCY CONVERTER

9

14

17

10

11

12

16

18

19

20

REF

RCLKIN

DGND

SCF S1 S0 REVP CF F2 F1

IN/OUT

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADE7761B

TABLE OF CONTENTS

Features .............................................................................................. 1

Analog Inputs ............................................................................. 11

Internal Oscillator ...................................................................... 12

Analog-to-Digital Conversion.................................................. 13

Active Power Calculation.......................................................... 14

Digital-to-Frequency Conversion............................................ 16

Transfer Function....................................................................... 16

Fault Detection ........................................................................... 17

Missing Neutral Mode............................................................... 18

Applications Information.............................................................. 21

Interfacing to a Microcontroller for Energy Measurement.. 21

Selecting a Frequency for an Energy Meter Application ...... 21

Negative Power Information..................................................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

Performance Issues That May Affect Billing Accuracy........... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 8

Test Circuit ........................................................................................ 9

Terminology .................................................................................... 10

Theory of Operation ...................................................................... 11

Power Supply Monitor ............................................................... 11

REVISION HISTORY

8/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADE7761B

SPECIFICATIONS

V_DD= 5 V 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, T_MINto T_MAX= −40°C to +85°C.

Table 1.

Parameter

Value

Unit

Test Conditions/Comments

ACCURACY¹

Measurement Error²

0.1

% of reading, typ

Over a dynamic range of 1000 to 1

Phase Error Between Channels

PF = 0.8 Capacitive

PF = 0.ꢀ Inductive

0.0ꢀ

Degrees, max

Phase lead 37°

Phase lag 60°

AC Power Supply Rejection²

Output Frequency Variation

DC Power Supply Rejection²

Output Frequency Variation

FAULT DETECTION^{2, 3}

0.01

%, typ

V_1A= V_1B= V_2P

=

100 mV rms

V_1A= V_1B= V_2P

=

See the Fault Detection section

Fault Detection Threshold

Inactive Input ≠ Active Input

Input Swap Threshold

Inactive Input ≠ Active Input

Accuracy Fault Mode Operation

V_1AActive, V_1B= AGND

V_1BActive, V_1A= AGND

Fault Detection Delay

6.2ꢀ

%, typ

V_1Aor V_1Bactive

% of larger, typ

V_1Aor V_1Bactive

0.1

3

% of reading, typ

Seconds, typ

Over a dynamic range of 1000 to 1

Swap Delay

3

Seconds, typ

MISSING NEUTRAL MODE^{2, 4}

Missing Neutral Detection Threshold

V_2P− V_2N

See the Missing Neutral Detection section

ꢀ9.4

mV peak, min

Accuracy Missing Neutral Mode

V_1AActive, V_1B= V_2P= AGND

V_1BActive, V_1A= V_2P= AGND

Missing Neutral Detection Delay

ANALOG INPUTS

0.1

3

% of reading, typ

Seconds, typ

Over a dynamic range of ꢀ00 to 1

V_1A− V_1N, V_1B− V_1N, V_2P− V_2N

Differential input

Differential input MISCAL − V_2N

Maximum Signal Levels

660

790

7

1ꢀ

4

mV peak, max

kΩ, min

kHz, typ

mV, typ

Input Impedance (DC)

Bandwidth (−3 dB)

ADC Offset Error²

Uncalibrated error, see the Terminology section for details

External 2.ꢀ V reference

Gain Error

%, typ

Gain Error Match²

REFERENCE INPUT

REF_IN/OUTInput Voltage Range

3

%, typ

External 2.ꢀ V reference

2.7

2.3

3

V, max

V, min

kΩ, min

pF, max

2.ꢀ V + 8%

2.ꢀ V − 8%

Input Impedance

Input Capacitance

10

ON-CHIP REFERENCE

Reference Error

Temperature Coefficient

Current Source

200

30

10

mV, max

ppm/°C, typ

μA, max

Specification assures that V_REFis within 8%

ON-CHIP OSCILLATOR

Oscillator Frequency

Oscillator Frequency Tolerance

Temperature Coefficient

4ꢀ0

12

30

kHz

% of reading, typ

ppm/°C, typ

Specification achieved with 2ꢀ ppm/°C max resistor on the

RCLKIN pin

Rev. 0 | Page 3 of 24

ADE7761B

Parameter

LOGIC INPUTS^ꢀ

Value

Unit

Test Conditions/Comments

PGA, SCF, S1, and S0

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

Input Capacitance, C_IN

LOGIC OUTPUTS^ꢀ

CF, REVP, and FAULT

Output High Voltage, V_OH

Output Low Voltage, V_OH

F1 and F2

2.4

0.8

3

V, min

V_DD= ꢀ V ꢀ%

Typical 10 nA, V_IN= 0 V to V_DD

V, max

μA, max

pF, max

10

4

1

V, min

V, max

V_DD= ꢀ V ꢀ%

Output High Voltage, V_OH

Output Low Voltage, V_OH

POWER SUPPLY

4

1

V, min

V, max

V_DD= ꢀ V ꢀ%, I_SOURCE= 10 mA

V_DD= ꢀ V ꢀ%, I_SINK= 10 mA

For specified performance

ꢀ V − ꢀ%

V_DD

4.7ꢀ

ꢀ.2ꢀ

3.6ꢀ

V, min

V, max

mA, max

ꢀ V + ꢀ%

I_DD

¹See plots in the Typical Performance Characteristics section.

²See the Terminology section for explanation of specifications.

³See the Fault Detection section for explanation of fault detection functionality.

⁴See the Missing Neutral Detection section for explanation of missing neutral detection functionality.

^ꢀSample tested during initial release and after any redesign or process change that might affect this parameter.

TIMING CHARACTERISTICS

V_DD= 5 V 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, T_MINto T_MAX= −40°C to +85°C. Sample tested during

initial release and after any redesign or process change that might affect this parameter. See Figure 2.

Table 2.

Parameter

Value

Unit

ms

Test Conditions/Comments

1

t₁

120

F₁and F₂pulse width (logic high)

t₂

t₃

t₄

See Table 8

1/2 t₂

90

sec

ms

Output pulse period (see the Transfer Function section)

Time between F₁falling edge and F₂falling edge

CF pulse width (logic high)

1

t_ꢀ

t₆

See Table 8

CLKIN/4

sec

CF pulse period (see the Transfer Function section)

Minimum time between F₁pulse and F₂pulse

¹The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Transfer Function section.

Timing Diagram

t₁

F1

t₆

t₂

t₃

F2

t₄

t₅

CF

Figure 2. Timing Diagram for Frequency Outputs

Rev. 0 | Page 4 of 24

ADE7761B

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

PERFORMANCE ISSUES THAT MAY AFFECT

BILLING ACCURACY

Table 3.

Parameter

Rating

The ADE7761B provides pulse outputs, CF, F1, and F2, that are

intended to be used for the billing of active energy. Pulses are

generated at these outputs in two different situations.

V_DDto AGND

Analog Input Voltage to AGND

−0.3 V to +7 V

−6 V to +6 V

V

_1A, V_1B, V_1N, V_2N, V_2P, MISCAL

Reference Input Voltage to AGND

Digital Input Voltage to DGND

Digital Output Voltage to DGND

Operating Temperature Range

Industrial

Storage Temperature Range

Junction Temperature

20-Lead SSOP, Power Dissipation

θ_JAThermal Impedance

Lead Temperature, Soldering

Vapor Phase (60 sec)

−0.3 V to V_DD+ 0.3 V

Case 1

When the analog input V_2P− V_2Ncomplies with the conditions

described in Figure 34, the CF, F₁, and F₂frequencies are

proportional to active power and can be used to bill active energy.

−40°C to +8ꢀ°C

−6ꢀ°C to +1ꢀ0°C

1ꢀ0°C

4ꢀ0 mW

112°C/W

Case 2

When the analog input V_2P− V_2Ndoes not comply with the

conditions described in Figure 34, the ADE7761B does not

measure active energy but a quantity proportional to kiloampere-

hours (kAh). This quantity is used to generate pulses on the

same CF, F1, and F2. This situation is indicated when the

FAULT pin is high.

21ꢀ°C

220°C

Infrared (1ꢀ sec)

Analog Devices, Inc., cautions users of the ADE7761B about the

following:

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

• Billing active energy in Case 1 is consistent with the under-

standing of the quantity represented by pulses on the CF, F1,

and F2 outputs (watthour).

• Billing active energy while the ADE7761B is in Case 2 must

be decided knowing that the entity measured by the ADE7761B

in this case is ampere-hour and not watthour. Users should

be aware of this limitation and decide if the ADE7761B is

appropriate for their application.

ESD CAUTION

Rev. 0 | Page ꢀ of 24

ADE7761B

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

V

20

19

18

17

16

15

14

13

12

11

F1

DD

V

F2

1A

1B

1N

2N

CF

DGND

REVP

FAULT

RCLKIN

PGA

S0

ADE7761B

TOP VIEW

(Not to Scale)

V

2P

MISCAL

AGND

REF

IN/OUT

SCF 10

S1

Figure 3. Pin Configuration (SSOP)

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

V_DD

Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7761B. The supply voltage

should be maintained at ꢀ V ꢀ% for specified operation. This pin should be decoupled with a 10 μF capacitor

in parallel with a ceramic 100 nF capacitor.

2, 3

V_1A, V_1B

Analog Inputs for Channel V1 (Current Channel). These inputs are fully differential voltage inputs with maximum

differential input signal levels of 660 mV with respect to V_1Nfor specified operation. The maximum signal level

at these pins is 1 V with respect to AGND. Both inputs have internal ESD protection circuitry, and an overvoltage

of 6 V can also be sustained on these inputs without risk of permanent damage.

4

ꢀ

6

7

V_1N

Negative Input for Differential Voltage Inputs, V_1Aand V_1B. The maximum signal level at this pin is 1 V with respect

to AGND. The input has internal ESD protection circuitry, and an overvoltage of 6 V can also be sustained on this

input without risk of permanent damage. The input should be directly connected to the burden resistor and held

at a fixed potential, that is, AGND. See the Analog Inputs section.

Negative Input for Differential Voltage Inputs, V_2Pand MISCAL. The maximum signal level at this pin is 1 V with

respect to AGND. The input has internal ESD protection circuitry, and an overvoltage of 6 V can also be sustained

on this input without risk of permanent damage. The input should be held at a fixed potential, that is, AGND. See

the Analog Inputs section.

Analog Input for Channel V2 (Voltage Channel). This input is a fully differential voltage input with maximum

differential input signal levels of 660 mV with respect to V_2Nfor specified operation. The maximum signal level at

this pin is 1 V with respect to AGND. This input has internal ESD protection circuitry, and an overvoltage of 6 V

can also be sustained on this input without risk of permanent damage.

Analog Input for Missing Neutral Calibration. This pin can be used to calibrate the CF, F₁, and F₂frequencies in the

missing neutral condition. This input is a fully differential voltage input with maximum differential input signal

levels of 660 mV with respect to V_2Nfor specified operation. The maximum signal level at this pin is 1 V with respect

to AGND. This input has internal ESD protection circuitry, and an overvoltage of 6 V can also be sustained on this

input without risk of permanent damage.

V_2N

V_2P

MISCAL

8

9

AGND

Analog Ground. This pin provides the ground reference for the analog circuitry in the ADE7761B, that is, ADCs and

reference. This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground

reference for all analog circuitry such as antialiasing filters and current and voltage transducers. For good noise

suppression, the analog ground plane should be connected to the digital ground plane only at the DGND pin.

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

2.ꢀ V 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source can also be

connected at this pin. In either case, this pin should be decoupled to AGND with a 1 ꢁF ceramic capacitor and

100 nF ceramic capacitor.

REF_IN/OUT

10

SCF

Select Calibration Frequency. This logic input is used to select the frequency on the Calibration Output CF.

Table 7 shows how the calibration frequencies are selected.

11, 12

S1, S0

These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion.

This offers the designer greater flexibility when designing the energy meter. See the Selecting a Frequency for an

Energy Meter Application section.

13

14

PGA

RCLKIN

This logic input is used to select the gain for the analog inputs, V_1Aand V_1B. The possible gains are 1 and 16.

To enable the internal oscillator as a clock source on the chip, a precise low temperature drift resistor at

a nominal value of 6.2 kΩ must be connected from this pin to DGND.

Rev. 0 | Page 6 of 24

ADE7761B

Pin No. Mnemonic Description

1ꢀ

FAULT

This logic output goes active high when a fault or missing neutral condition occurs. A fault is defined as a

condition under which the signals on V_1Aand V_1Bdiffer by more than 6.2ꢀ%. A missing neutral condition is

defined when the chip is powered up with no voltage at the input. The logic output is reset to 0 when a fault or

missing neutral condition is no longer detected. See the Fault Detection section and the Missing Neutral Mode

section.

16

17

REVP

This logic output goes logic high when negative power is detected, that is, when the phase angle between the

voltage and current signals is greater than 90°. This output is not latched and is reset when positive power is once

again detected. The output goes high or low at the same time that a pulse is issued on CF.

Digital Ground. This pin provides the ground reference for the digital circuitry in the ADE7761B, that is, multiplier,

filters, and digital-to-frequency converters. This pin should be tied to the digital ground plane of the PCB. The

digital ground plane is the ground reference for all digital circuitry, such as counters (mechanical and digital),

MCUs, and indicator LEDs. For good noise suppression, the analog ground plane should be connected to the digital

ground plane only at the DGND pin.

DGND

18

CF

Calibration Frequency Logic Output. The CF logic output, active high, gives instantaneous active power information.

This output is used for operational and calibration purposes. See the Digital-to-Frequency Conversion section.

19, 20

F2, F1

Low Frequency Logic Outputs. F1 and F2 supply average active power information. The logic outputs can be

used to directly drive electromechanical counters and 2-phase stepper motors.

Rev. 0 | Page 7 of 24

ADE7761B

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

PF = 1

GAIN = 16

ON-CHIP REFERENCE

0.8

0.6

–40°C

0.4

PF = –0.5

0.2

+25°C

0

–0.2

–0.4

–0.6

–0.8

–1.0

+85°C

PF = +1

PF = +0.5

–0.4

–0.6

–0.8

–1.0

0.1

1

10

100

0.1

1

10

100

CURRENT (% of Full Scale)

Figure 4. Active Power Error As a Percentage of Reading

with Gain = 1 and Internal Reference

Figure 7. Active Power Error As a Percentage of Reading

over Power Factor with Gain = 16 and Internal Reference

1.0

0.8

GAIN = 16

ON-CHIP REFERENCE

PF = 1

ON-CHIP REFERENCE

0.8

0.6

–40°C; PF = 0.5

+85°C; PF = 0.5

0.4

5.25V

0.2

5.00V

4.75V

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

+25°C; PF = 1

+25°C; PF = 0.5

0.1

1

10

100

0.1

1

10

100

CURRENT (% of Full Scale)

Figure 8. Active Power Error As a Percentage of Reading

over Power Supply with Gain = 1 and Internal Reference

Figure 5. Active Power Error As a Percentage of Reading

over Power Factor with Gain = 1 and Internal Reference

1.0

0.8

0.6

0.4

0.2

1.0

0.8

PF = 1, GAIN = 16

ON-CHIP REFERENCE

–40°C

0.6

+25°C

0.4

–40°C

0.2

+25°C

+85°C

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

–0.2

–0.4

–0.6

–0.8

–1.0

+85°C

0.1

1

10

100

0.1

1

10

100

CURRENT (% of Full Scale)

Figure 6. Active Power Error As a Percentage of Reading

with Gain = 16 and Internal Reference

Figure 9. Ampere Hour Error As a Percentage of Reading

in Missing Neutral Mode with Gain = 1 and Internal Reference

Rev. 0 | Page 8 of 24

ADE7761B

TEST CIRCUIT

V

DD

+

10µF

RB

100nF

1

PS2501-1

40A TO 80mA

I

2kΩ

18

CF

DD

1kΩ

1

4

2

V

1A

19

20

16

F2

F1

TO FREQ.

COUNTER

33nF

ADE7761B

REVP

2

3

1kΩ

33nF

1kΩ

2kΩ

3

V

1B

1N

2N

15

14

FAULT

RB

6.2kΩ

RCLKIN

4

5

RB = 18Ω

33nF

10kΩ

1kΩ

12

11

10

S0

S1

33nF

SCF

1MΩ

1kΩ 33nF

REF

6

7

9

V

IN/OUT

2P

+

220V

100nF

10µF

560kΩ

MISCAL

PGA AGND DGND

13 17

100kΩ 33nF

8

Figure 10. Test Circuit for Performance Curves

Rev. 0 | Page 9 of 24

ADE7761B

TERMINOLOGY

For the dc PSR measurement, a reading at nominal supplies (5 V)

is taken. A second reading is obtained with the same input signal

levels when the power supplies are varied 5%. Any error

introduced is again expressed as a percentage of reading.

Measurement Error

The error associated with the energy measurement made by the

ADE7761B is defined by

Percentage Error =

ADC Offset Error

⎛

⎜

⎝

⎞

⎟

⎠

Energy Registered by ADE7761B −True Energy

This is the dc offset associated with the analog inputs to the ADCs.

With the analog inputs connected to AGND, the ADCs still see

a dc analog input signal. The magnitude of the offset depends on

the input gain and range selection (see the Typical Performance

Characteristics section). However, when HPFs are switched on,

the offset is removed from the current channels and the power

calculation is not affected by this offset.

× 100%

True Energy

Phase Error Between Channels

The high-pass filter (HPF) in the current channel has a phase

lead response. To offset this phase response and equalize the

phase response among channels, a phase correction network is

also placed in the current channel. The phase correction network

ensures a phase match between the current channels and the

voltage channels to within 0.1° over a range of 45 Hz to

65 Hz and 0.2° over a range of 40 Hz to 1 kHz.

Gain Error

The gain error in the ADE7761B ADCs is defined as the difference

between the measured output frequency (minus the offset) and

the ideal output frequency. It is measured with a gain of 1 in

Channel V_1A. The difference is expressed as a percentage of the

ideal frequency, which is obtained from the transfer function

(see the Transfer Function section).

Power Supply Rejection (PSR)

PSR quantifies the ADE7761B measurement error as a percentage

of reading when the power supplies are varied. For the ac PSR

measurement, a reading at nominal supplies (5 V) is taken.

A second reading is obtained with the same input signal levels

when an ac signal (175 mV rms/100 Hz) is introduced onto the

supplies. Any error introduced by this ac signal is expressed as

a percentage of reading (see the Measurement Error definition).

Gain Error Match

The gain error match is defined as the gain error (minus the offset)

obtained when switching between a gain of 1 or 16. It is expressed

as a percentage of the output ADC code obtained under a gain of 1.

Rev. 0 | Page 10 of 24

ADE7761B

THEORY OF OPERATION

V

1A

DIFFERENTIAL INPUT A

±660mV MAX PEAK

POWER SUPPLY MONITOR

V

, V

1A 1B

V1

+660mV

GAIN

The ADE7761B continuously monitors the power supply (V_DD)

with its on-chip power supply monitor. If the supply is less than

4 V 5%, the ADE7761B goes into an inactive state; that is, no

energy is accumulated, and the CF, F1, and F2 outputs are disabled.

This is useful to ensure correct device operation at power-up

and during power-down. The power supply monitor has built-in

hysteresis and filtering that provide a high degree of immunity

to false triggering due to noisy supplies.

+ V

CM

1N

COMMON MODE

V

CM

±100mV MAX

V

CM

AGND

–660mV

GAIN

+ V

CM

DIFFERENTIAL INPUT B

±660mV MAX PEAK

V

1B

Figure 12. Maximum Signal Levels, Channel V1

Channel V2 (Voltage Channel)

The power supply and decoupling for the part should be such

that the ripple at V_DDdoes not exceed 5 V 5%, as specified for

normal operation.

The output of the line voltage transducer is connected to the

ADE7761B at this analog input. Channel V2 is a single-ended

voltage input. The maximum peak differential signal on

Channel V2 is 660 mV with respect to V_2N. Figure 13 shows the

maximum signal levels that can be connected to Channel V2.

V

DD

5V

4V

V2

V

2P

2N

+660mV + V

CM

V2

DIFFERENTIAL INPUT

±660mV MAX PEAK

0V

V

CM

TIME

V

COMMON MODE

±100mV MAX

CM

ADE7761B

REVP - FAULT - CF -

F1 - F2 OUTPUTS

–660mV + V

CM

INACTIVE

ACTIVE

INACTIVE

Figure 11. On-Chip, Power Supply Monitoring

Figure 13. Maximum Signal Levels, Channel V2

ANALOG INPUTS

The differential voltage V_2P− V_2Nmust be referenced to a

common mode (usually AGND). The analog inputs of the

ADE7761B can be driven with common-mode voltages of up

to 100 mV with respect to AGND. However, the best results

are achieved using a common mode equal to AGND.

Channel V1 (Current Channel)

The voltage outputs from the current transducers are connected

to the ADE7761B at Channel V1. It has two voltage inputs, V_1A

and V_1B. These inputs are fully differential with respect to V_1N.

However, at any one time, only one input is selected to perform

the power calculation (see the Fault Detection section).

MISCAL Input

The input for the power calibration in missing neutral mode

is connected to the ADE7761B at this analog input. MISCAL

is a single-ended, voltage input. It is recommended to use a dc

signal derived from the voltage reference to drive this pin. The

maximum peak differential signal on MISCAL is 660 mV with

respect to V_2N. Figure 14 shows the maximum signal levels that

can be connected to the MISCAL pin.

The maximum peak differential signal on V_1A− V_1Nand V_1B− V_1N

is 660 mV. However, Channel V1 has a programmable gain

amplifier (PGA) with user-selectable gains of 1 and 16 (see

Table 5). This gain facilitates easy transducer interfacing.

Table 5. Channel V1 Dynamic Range

PGA

Gain

Maximum Differential Signal (mV)

0

1

16

660

41

MISCAL

+660mV + V

CM

DIFFERENTIAL INPUT

±660mV MAX PEAK

Figure 12 shows the maximum signal levels on V_1A, V_1B, and

V_1N. The maximum differential voltage is 660 mV divided by

the gain selection. The differential voltage signal on the inputs

must be referenced to a common mode (usually AGND).

V

2N

V

CM

COMMON MODE

±100mV MAX

V

CM

AGND

Figure 14. Maximum Signal Levels, MISCAL

The differential voltage, MISCAL − V_2N, must be referenced

to a common mode (usually AGND). The analog inputs of the

ADE7761B can be driven with common-mode voltages of up to

100 mV with respect to AGND. However, best results are achieved

using a common mode equal to AGND.

Rev. 0 | Page 11 of 24

ADE7761B

Typical Connection Diagrams

Adjusting the level of MISCAL to calibrate the meter in missing

neutral mode can be done by changing the ratio of RC and

RD + VR1. When the internal reference is used, the values of RC,

RD, and VR1 must be chosen to limit the current sourced by

the internal reference sourcing current to below the specified

10 μA. Therefore, because V_REFinternal = 2.5 V, RC + RD +

VR1 > 600 kΩ.

Figure 15 shows a typical connection diagram for Channel V1.

The analog inputs are used to monitor both the phase and

neutral currents. Because of the large potential difference

between the phase and neutral, two current transformers (CTs)

must be used to provide the isolation. Note that both CTs are

referenced to analog ground (AGND); therefore, the common-

mode voltage is 0 V. The CT turn ratio and burden resistor (RB)

are selected to give a peak differential voltage of 660 mV/gain.

INTERNAL OSCILLATOR

The nominal internal oscillator frequency is 450 kHz when

used with the recommended R_OSCresistor value of 6.2 kΩ

between RCLKIN and DGND (see Figure 18).

V

R

1A

F

CT

±660mV

GAIN

RB

C

F

ADE7761B

IP

IN

AGND

V

1N

1B

±660mV

GAIN

3kΩ

2.5V

INTERNAL

C

REFERENCE

OSCILLATOR

CT

R

F

9

14

17

REF

RCLKIN

DGND

IN/OUT

Figure 15. Typical Connection for Channel V1

R

OSC

Figure 16 shows two typical connections for Channel V2.

The first option uses a potential transformer (PT) to provide

complete isolation from the main voltage. In the second option,

the ADE7761B is biased around the neutral wire, and a resistor

divider is used to provide a voltage signal that is proportional to

the line voltage. Adjusting the ratio of RA and RB + VR is a

convenient way to carry out a gain calibration on the meter.

Figure 18. Internal Oscillator Connection

The internal oscillator frequency is inversely proportional to the

value of this resistor. Although the internal oscillator operates

when used with an R_OSCresistor value between 5 kΩ and 12 kΩ,

it is recommended that a value be chosen within the range of

the nominal value.

V

R

2P

F

C

±660mV

AGND

F

The output frequencies on CF, F1, and F2 are directly propor-

tional to the internal oscillator frequency; therefore, Resistor R_OSC

must have a low tolerance and low temperature drift. A low

tolerance resistor limits the variation of the internal oscillator

frequency. A small variation of the clock frequency and, conse-

quently, of the output frequencies from meter to meter contributes

to a smaller calibration range of the meter.

V

R

2N

F

C

1

RA

C

F

1

RB

V

2P

VR

R

2N

F

A low temperature drift resistor directly limits the variation of

the internal clock frequency over temperature. The stability of

the meter to external variation is then better ensured by design.

C

T

1

RB + VR = RF.

Figure 16. Typical Connections for Channel V2

Figure 17 shows a typical connection for the MISCAL input.

The voltage reference input (REF_IN/OUT) is used as a dc reference

to set the MISCAL voltage.

REF

IN/OUT

RC

C

F

RD

MISCAL

VR1

V

R

2N

F

C

F

Figure 17. Typical Connection for MISCAL

Rev. 0 | Page 12 of 24

ADE7761B

ANTIALIAS FILTER (RC)

DIGITAL FILTER

ANALOG-TO-DIGITAL CONVERSION

SAMPLING FREQUENCY

SHAPED NOISE

SIGNAL

NOISE

The analog-to-digital conversion in the ADE7761B is carried

out using second-order, Σ-Δ ADCs. Figure 19 shows a first-

order, Σ-Δ ADC (for simplicity). The converter is made up of

two parts: the Σ-Δ modulator and the digital low-pass filter.

MCLK

0

1

225

FREQUENCY (kHz)

450

ANALOG

LOW-PASS FILTER

LATCHED

COMPAR-

ATOR

INTEGRATOR

DIGITAL

LOW-PASS FILTER

HIGH RESOLUTION

OUTPUT FROM

DIGITAL LFP

SIGNAL

NOISE

R

V

REF

1

24

C

....10100101....

1-BIT DAC

0

1

225

FREQUENCY (kHz)

450

Figure 19. First-Order, Σ-Δ ADC

Figure 20. Noise Reduction Due to Oversampling and

Noise Shaping in the Analog Modulator

A Σ-Δ modulator converts the input signal into a continuous

serial stream of 1s and 0s at a rate determined by the sampling

clock. In the ADE7761B, the sampling clock is equal to CLKIN.

The 1-bit DAC in the feedback loop is driven by the serial data

stream. The DAC output is subtracted from the input signal.

If the loop gain is high enough, the average value of the DAC

output (and, therefore, the bit stream) approaches that of the

input signal level. For any given input value in a single sampling

interval, the data from the 1-bit ADC is virtually meaningless.

Only when a large number of samples are averaged is a meaningful

result obtained. This averaging is carried out in the second part

of the ADC, the digital low-pass filter. By averaging a large

number of bits from the modulator, the low-pass filter can

produce 24-bit data-words that are proportional to the input

signal level.

Antialias Filter

Figure 20 also shows an analog low-pass filter, RC, on input to

the modulator. This filter is present to prevent aliasing. Aliasing

is an artifact of all sampled systems, which means that frequency

components in the input signal to the ADC that are higher than

half the sampling rate of the ADC appear in the sampled signal

frequency below half the sampling rate. Figure 21 illustrates

the effect.

ANTIALIASING EFFECTS

SAMPLING

FREQUENCY

IMAGE

FREQUENCIES

The Σ-Δ converter uses two techniques to achieve high resolution

from what is essentially a 1-bit conversion technique. The first is

oversampling, which means that the signal is sampled at a rate

(frequency) that is many times higher than the bandwidth of

interest. For example, the sampling rate in the ADE7761B is

CLKIN (450 kHz) and the band of interest is 40 Hz to 1 kHz.

Oversampling has the effect of spreading the quantization noise

(noise due to sampling) over a wider bandwidth. With the noise

spread more thinly over a wider bandwidth, the quantization

noise in the band of interest is lowered (see Figure 20).

0

1

225

450

FREQUENCY (kHz)

Figure 21. ADC and Signal Processing in Current Channel or Voltage Channel

In Figure 21, frequency components (arrows shown in black)

above half the sampling frequency (also known as the Nyquist

frequency), that is, 225 kHz, are imaged or folded back down

below 225 kHz (arrows shown in gray). This happens with all

ADCs, no matter what the architecture. In Figure 21, only

frequencies near the sampling frequency (450 kHz) move into

the band of interest for metering (40 Hz to 1 kHz). This fact

allows the use of a very simple low-pass filter to attenuate these

frequencies (near 250 kHz) and, thereby, prevent distortion in the

band of interest. A simple RC filter (single pole) with a corner

frequency of 10 kHz produces an attenuation of approximately

33 dB at 450 kHz (see Figure 21). This is sufficient to eliminate

the effects of aliasing.

However, oversampling alone is not an efficient enough method

to improve the signal-to-noise ratio (SNR) in the band of interest.

For example, an oversampling ratio of 4 is required just to increase

the SNR by only 6 dB (1 bit). To keep the oversampling ratio at

a reasonable level, it is possible to shape the quantization noise so

the majority of the noise lies at the higher frequencies. This is what

happens in the Σ-Δ modulator; the noise is shaped by the inte-

grator, which has a high-pass type response for the quantization

noise. The result is that most of the noise is at higher frequencies,

where it can be removed by the digital low-pass filter. This noise

shaping is also shown in Figure 20.

Rev. 0 | Page 13 of 24

ADE7761B

Power Factor Considerations

ACTIVE POWER CALCULATION

The method used to extract the active power information from

the instantaneous power signal (by low-pass filtering) is still valid

even when the voltage and current signals are not in phase.

The ADCs digitize the voltage signals from the current and

voltage transducers. A high-pass filter in the current channel

removes any dc component from the current signal. This eliminates

any inaccuracies in the active power calculation due to offsets in

the voltage or current signals (see the HPF and Offset Effects

section).

Figure 23 displays the unity power factor condition and a

displacement power factor (DPF = 0.5), that is, current signal

lagging the voltage by 60°.

INSTANTANEOUS

POWER SIGNAL

INSTANTANEOUS

ACTIVE POWER SIGNAL

The active power calculation is derived from the instantaneous

power signal. The instantaneous power signal is generated by

a direct multiplication of the current and voltage signals.

To extract the active power component (dc component), the

instantaneous power signal is low-pass filtered. Figure 22 illustrates

the instantaneous active power signal and shows how the active

power information can be extracted by low-pass filtering the

instantaneous power signal. This scheme correctly calculates

active power for nonsinusoidal current and voltage waveforms

at all power factors. All signal processing is carried out in the

digital domain for superior stability over temperature and time.

V × I

2

0V

CURRENT

VOLTAGE

INSTANTANEOUS

POWER SIGNAL

INSTANTANEOUS

ACTIVE POWER SIGNAL

DIGITAL-TO-

FREQUENCY

V × I

2

F1

F2

× cos(60°)

0V

CH1

CH2

PGA

ADC

HPF

MULTIPLIER

DIGITAL-TO-

FREQUENCY

LPF

VOLTAGE

CURRENT

CF

60°

Figure 23. Active Power Calculation over PF

INSTANTANEOUS

POWER SIGNAL –p(t)

ACTIVE POWER SIGNAL

If one assumes that the voltage and current waveforms are

sinusoidal, the active power component of the instantaneous

power signal (dc term) is given by

V × I

p(t) = i(t) × v(t)

WHERE:

v(t) = V × cos(ωt)

V × I

2

i(t) = I × cos(ωt)

(V × I/2) × cos(60°)

V × I

2

p(t) =

{1 + cos (2ωt)}

This is the correct active power calculation.

Nonsinusoidal Voltage and Current

TIME

Figure 22. Signal Processing Block Diagram

The active power calculation method also holds true for

nonsinusoidal current and voltage waveforms. All voltage

and current waveforms in practical applications have some

harmonic content. Using the Fourier transform, instantaneous

voltage and current waveforms can be expressed in terms of

their harmonic content.

The low frequency output of the ADE7761B is generated by

accumulating this active power information. This low frequency

inherently means a long accumulation time between output

pulses. The output frequency is, therefore, proportional to the

average active power. This average active power information

can, in turn, be accumulated (for example, by a counter) to

generate active energy information. Because of its high output

frequency and, therefore, shorter integration time, the CF

output is proportional to the instantaneous active power. This is

useful for system calibration purposes that take place under

steady load conditions.

v(t) = V + 2 × ^∞V ×sin(hωt + α )

(1)

∑

O

h

h ≠0

where:

v(t) is the instantaneous voltage.

V_Ois the average value.

V_his the rms value of Voltage Harmonic h.

α_his the phase angle of the voltage harmonic.

Rev. 0 | Page 14 of 24

ADE7761B

∞

The HPF in Channel V1 has an associated phase response that

is compensated for on-chip. Figure 25 and Figure 26 show the

phase error between channels with the compensation network

activated. The ADE7761B is phase compensated up to 1 kHz as

shown, which ensures a correct active harmonic power calculation

even at low power factors.

(2)

i(t) = I_O+ 2 × I ×sin(hωt +β )

∑

h

h ≠0

where:

i(t) is the instantaneous current.

I_Ois the dc component.

I_his the rms value of Current Harmonic h.

β_his the phase angle of the current harmonic.

DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR ACTIVE

POWER CALCULATION

Using Equation 1 and Equation 2, the Active Power P can be

expressed in terms of its fundamental active power (P₁) and

harmonic active power (P_H).

V

× I

1

2

P = P₁+ P_H

where:

V

× I

1

0

P₁= V₁× I₁cos(Φ₁)

Φ₁= α₁− β₁

(3)

(4)

0

1

2ω

FREQUENCY (Rad/s)

0ω

and

∞

Figure 24. Effect of Channel Offsets on the Active Power Calculation

P = V × I ×cos(Φ )

∑

H

h

h=2

Φ_h= α_h− β_h

0.30

0.25

0.20

0.15

As can be seen in Equation 4, a harmonic active power component

is generated for every harmonic provided that the harmonic is

present in both the voltage and current waveforms. The power

factor calculation was previously shown to be accurate in the

case of a pure sinusoid; therefore, the harmonic active power

must also correctly account for the power factor because it is

made up of a series of pure sinusoids.

0.10

0.05

0

Note that the input bandwidth of the analog inputs is 7 kHz

with an internal oscillator frequency of 450 kHz.

–0.05

–0.10

HPF and Offset Effects

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (Hz)

Equation 5 shows the effect of offsets on the active power

calculation. Figure 24 shows the effect of offsets on the active

power calculation in the frequency domain.

Figure 25. Phase Error Between Channels (0 Hz to 1 kHz)

V(t) × I(t) =

0.30

0.25

0.20

0.15

0.10

(5)

(V₀+V₁× cos(ωt))×(I₀+ I₁× cos(ωt)) =

V₁× I₁

V₀× I₁+

+V₀× I₁× cos(ωt) +V₁× I₀× cos(ωt)

2

As shown in Equation 5 and Figure 24, an offset on Channel V1

and Channel V2 contributes a dc component after multiplication.

Because this dc component is extracted by the LPF and used to

generate the active power information, the offsets contribute

a constant error to the active power calculation. This problem is

easily avoided in the ADE7761B with the HPF in Channel V1. By

removing the offset from at least one channel, no error component

can be generated at dc by the multiplication. Error terms at cos(ωt)

are removed by the LPF and the digital-to-frequency conversion

(see the Digital-to-Frequency Conversion section).

0.05

0

–0.05

–0.10

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 26. Phase Error Between Channels (40 Hz to 70 Hz)

Rev. 0 | Page 1ꢀ of 24

ADE7761B

The output frequency on CF can be up to 2048 times higher

than the frequency on F1 and F2. This higher output frequency

is generated by accumulating the instantaneous active power

signal over a much shorter time while converting it to a frequency.

This shorter accumulation period means less averaging of the

cos(2ωt) component. As a consequence, some of this instantaneous

power signal passes through the digital-to-frequency conversion.

This is not a problem in the application.

DIGITAL-TO-FREQUENCY CONVERSION

As described in the Active Power Calculation section, the digital

output of the low-pass filter after multiplication contains the

active power information. However, because this LPF is not an

ideal brick wall filter implementation, the output signal also

contains attenuated components at the line frequency and its

harmonics, that is, cos(hωt), where h = 1, 2, 3, …, and so on.

The magnitude response of the filter is given by

Where CF is used for calibration purposes, the frequency should

be averaged by the frequency counter, which removes any ripple.

If CF is being used to measure energy, such as in a microprocessor-

based application, the CF output should also be averaged to calcu-

late power. Because the F1 and F2 outputs operate at a much

lower frequency, much more averaging of the instantaneous active

power signal is carried out. The result is a greatly attenuated

sinusoidal content and a virtually ripple-free frequency output.

1

H( f ) =

(6)

1 = ( f /4.5Hz)²

For a line frequency of 50 Hz, this gives an attenuation of the 2ω

(100 Hz) component of approximately −26.9 dB. The dominating

harmonic is at twice the line frequency, cos(2ωt), due to the

instantaneous power signal.

Figure 27 shows the instantaneous active power signal output of

the LPF, which still contains a significant amount of instantaneous

power information, cos(2ωt). This signal is then passed to the

digital-to-frequency converter, where it is integrated (accumulated)

over time to produce an output frequency. This accumulation of

the signal suppresses or averages out any non-dc components in

the instantaneous active power signal. The average value of a

sinusoidal signal is zero. Therefore, the frequency generated by

the ADE7761B is proportional to the average active power.

TRANSFER FUNCTION

Frequency Output F1 and Frequency Output F2

The ADE7761B calculates the product of two voltage signals

(on Channel V1 and Channel V2) and then low-pass filters this

product to extract active power information. This active power

information is then converted to a frequency. The frequency

information is output on F1 and F2 in the form of active high

pulses. The pulse rate at these outputs is relatively low, for

example, 0.37 Hz maximum for ac signals with S0 = S1 = 0

(see Table 8). This means that the frequency at these outputs

is generated from active power information accumulated over

a relatively long period. The result is an output frequency that

is proportional to the average active power. The averaging of the

active power signal is implicit to the digital-to-frequency conver-

sion. The output frequency or pulse rate is related to the input

voltage signals by

F

1

DIGITAL-TO-

FREQUENCY

F

1

2

V

TIME

MULTIPLIER

CF

DIGITAL-TO-

FREQUENCY

LPF

I

CF

LPF TO EXTRACT

ACTIVE POWER

(DC TERM)

6.13×Gain×V1_rms×V2_rms× f₁₋₄

(7)

F , F Frequency =

1

2

V_REF

where:

F₁, F₂Frequency is the output frequency on F1 and F2 (Hz).

V1_rmsis the differential rms voltage signal on Channel V1 (V).

V2_rmsis the differential rms voltage signal on Channel V2 (V).

Gain is 1 or 16, depending on the PGA gain selection made

using Logic Input PGA.

TIME

0

ω

2ω

FREQUENCY (Rad/s)

INSTANTANEOUS ACTIVE POWER SIGNAL (FREQUENCY DOMAIN)

Figure 27. Active Power to Frequency Conversion

V_REFis the reference voltage (2.5 V 8%) (V).

f_1–4is one of four possible frequencies selected by using Logic

Input S0 and Logic Input S1 (see Table 6).

Figure 27 also shows the digital-to-frequency conversion for

steady load conditions: constant voltage and current. As can be

seen in Figure 27, the frequency output CF varies over time,

even under steady load conditions. This frequency variation is

primarily due to the cos(2ωt) component in the instantaneous

active power signal.

Rev. 0 | Page 16 of 24

ADE7761B

Note that if the on-chip reference is used, actual output

frequencies may vary from device to device due to a reference

tolerance of 8%.

Table 6. f_1–4Frequency Selection

S1

S0

f_1–4(Hz)¹

1.72

f₁₋₄= OSC/2ⁿ²

OSC/2¹⁸

0

1

3.44

OSC/2¹⁷

6.13 × 0.66 × 0.66 ×1.72Hz

F , F Frequency =

= 0.367Hz

1

2

1

0

6.86

OSC/2¹⁶

OSC/2^1ꢀ

2 × 2 × 2.5²

1

13.7

CF Frequency = F₁, F₂× 64 = 23.5 Hz

¹Values are generated using the nominal frequency of 4ꢀ0 kHz.

²f_1–4are a binary fraction of the master clock and, therefore, vary with the

internal oscillator frequency (OSC).

As can be seen from these two example calculations, the maximum

output frequency for ac inputs is always half of that for dc input

signals. Table 8 shows a complete listing of all maximum output

frequencies for ac signals.

Frequency Output CF

The pulse output calibration frequency (CF) is intended for use

during calibration. The output pulse rate on CF can be up to

2048 times the pulse rate on F1 and F2. The lower the f_1–4

frequency selected, the higher the CF scaling. Table 7 shows

how the two frequencies are related, depending on the states of

Logic Input S0, Logic Input S1, and Logic Input SCF. Because of

its relatively high pulse rate, the frequency at this logic output is

proportional to the instantaneous active power. As with F₁and

F₂, the frequency is derived from the output of the low-pass filter

after multiplication. However, because the output frequency is high,

this active power information is accumulated over a much shorter

time. Therefore, less averaging is carried out in the digital-to-

frequency conversion. With much less averaging of the active

power signal, the CF output is much more responsive to power

fluctuations (see Figure 22).

Table 8. Maximum Output Frequencies on CF, F1, and F2 for

AC Inputs

F₁, F₂Maximum CF Maximum

Frequency (Hz), Frequency (Hz),

CF-to-F₁

Ratio

SCF S1 S0 1/t₂

1/t₅

1

0

1

0

1

0

1

0

1

0

1

0

1

0.37

0.73

1.47

2.94

46.98

23.49

46.98

23.49

46.98

23.49

46.98

6013

128

64

32

16

2048

FAULT DETECTION

Table 7. Relationship Between CF and F1, F2 Frequency

Outputs

The ADE7761B incorporates a novel fault detection scheme

that warns of fault conditions and allows the ADE7761B to

continue accurate billing during a fault event. The ADE7761B

does this by continuously monitoring both the phase and neutral

(return) currents. A fault is indicated when these currents differ

by more than 6.25%. However, even during a fault, the output

pulse rate on F1 and F2 is generated using the larger of the two

currents. Because the ADE7761B looks for a difference between

the voltage signals on V_1Aand V_1B, it is important that both

current transducers be closely matched.

SCF

S1

S0

f_1–4(Hz)

1.72

3.44

6.86

13.7

CF Frequency Output

128 × F₁, F₂

64 × F₁, F₂

32 × F₁, F₂

16 × F₁, F₂

2048 × F₁, F₂

1

0

1

0

1

0

1

0

1

0

1

0

1

On power-up, the output pulse rate of the ADE7761B is propor-

tional to the product of the voltage signals on V_1Aand Channel V2.

If the difference between V_1Aand V_1Bon power-up is greater than

6.25%, the fault indicator (FAULT) becomes active after about

1 second. In addition, if V_1Bis greater than V_1A, the ADE7761B

selects V_1Bas the input. Fault detection is automatically disabled

when the voltage signal on Channel V1 is less than 0.3% of the

full-scale input range. This eliminates false detection of a fault

due to noise at light loads.

Example

In this example, if ac voltages of 660 mV peak are applied to

Channel V1 and Channel V2, the expected output frequency on

CF, F1, and F2 is calculated as

Gain = 1, PGA = 0

f_1–4= 1.7 Hz, SCF = S1 = S0 = 0

V1_rms= rms of 660 mV peak ac = 0.66/√2 V

V2_rms= rms of 660 mV peak ac = 0.66/√2 V

V_REF= 2.5 V (nominal reference value)

Rev. 0 | Page 17 of 24

ADE7761B

Fault with Active Input Greater Than Inactive Input

Calibration Concerns

If V_1Ais the active current input (that is, being used for billing),

and the voltage signal on V_1B(inactive input) falls below 93.75%

of V_1A, the fault indicator becomes active. Both analog inputs

are filtered and averaged to prevent false triggering of this logic

output. As a consequence of the filtering, there is a time delay of

approximately 3 sec on the Logic Output FAULT after the fault

event. The FAULT logic output is independent of any activity on

the F1 or F2 outputs. Figure 28 shows one condition under

which FAULT becomes active. Because V_1Ais the active input

and it is still greater than V_1B, billing is maintained on V_1A; that

is, no swap to the V_1Binput occurs. V_1Aremains the active input.

Typically, when a meter is being calibrated, the voltage and current

circuits are separated, as shown in Figure 30. This means that

current passes through only the phase or neutral circuit. Figure 30

shows current being passed through the phase circuit. This is

the preferred option because the ADE7761B starts billing on the

input V_1Aon power-up. The Phase Circuit CT is connected to

V_1Ain Figure 30. Because there is no current in the neutral circuit,

the FAULT indicator comes on under these conditions. However,

this does not affect the accuracy of the calibration and can be

used as a means to test the functionality of the fault detection.

V

R

1A

F

IB

CT

FAULT

FILTER

V

1A

AND

RB

V

COMPARE

C

A

1B

V

F

1A

V

TO

1A

1B

AGND

MULTIPLIER

0V

V

1N

V

1N

1B

IB

0V

AGND

C

B

TEST

CURRENT

V

< 93.75% OF V

1A

1B

CT

R

F

1B

1

RA

FAULT

<0

C

F

1

RB

V

2P

>0

VR

ACTIVE POINT – INACTIVE INPUT

R

F

2N

6.25% OF ACTIVE INPUT

V

C

T

Figure 28. Fault Conditions for Active Input Greater Than Inactive Input

240V rms

1

RB + VR = RF.

Fault with Inactive Input Greater Than Active Input

Figure 30. Conditions for Calibration of Channel B

Figure 29 illustrates another fault condition. If the difference

between V_1B, the inactive input, and V_1A, the active input (that

is, being used for billing), becomes greater than 6.25% of V_1B,

the FAULT indicator becomes active and a swap over to the V_1B

input occurs. The Analog Input V_1Bbecomes the active input.

Again, a time constant of about 3 sec is associated with this swap.

V_1Adoes not swap back to the active channel until V_1Ais greater

than V_1B, and the difference between V_1Aand V_1B, in this order,

becomes greater than 6.25% of V_1A. However, the FAULT indi-

cator becomes inactive as soon as V_1Ais within 6.25% of V_1B. This

threshold eliminates potential chatter between V_1Aand V_1B.

If the neutral circuit is chosen for the current circuit in the

arrangement shown in Figure 30, this may have implications for

the calibration accuracy. The ADE7761B powers up with the

V_1Ainput active as normal. However, because there is no current

in the phase circuit, the signal on V_1Ais zero. This causes a fault

to be flagged and the active input to be swapped to V_1B(neutral).

The meter can be calibrated in this mode, but the phase and

neutral CTs may differ slightly. Because under no-fault conditions

all billing is carried out using the phase CT, the meter should be

calibrated using the phase circuit. Of course, both phase and

neutral circuits can be calibrated.

FAULT

FILTER

AND

V

1A

MISSING NEUTRAL MODE

A

V

COMPARE

1B

V

TO

1A

1B

The ADE7761B integrates a novel fault detection scheme that

warns and allows the ADE7761B to continue to bill in case a

meter is connected to only one wire (see Figure 31). For correct

operation of the ADE7761B in this mode, the V_DDpin of the

ADE7761B must be maintained within the specified range

(5 V 5%). The missing neutral detection algorithm is designed

to work over a line frequency of 45 Hz to 55 Hz.

MULTIPLIER

0V

V

1N

1B

AGND

B

V

< 93.75% OF V

1B

1A

FAULT + SWAP

<0

>0

ACTIVE POINT – INACTIVE INPUT

6.25% OF INACTIVE INPUT

Figure 29. Fault Conditions for Inactive Input Greater Than Active Input

Rev. 0 | Page 18 of 24

ADE7761B

V

R

V

1A

F

Analog Devices cautions users of the ADE7761B about the

following:

CT

IB

RB

C

244V rms

POWER

GENERATOR

F

• Billing active energy in Case 1 is consistent with the under-

standing of the quantity represented by pulses on the CF, F1,

and F2 outputs (watthour).

1A

V

1N

0V

C

F

• Billing active energy while the ADE7761B is in Case 2 must

be decided knowing that the entity measured by the ADE7761B

in this case is ampere-hour and not watthour. Users should

be aware of this limitation and decide if the ADE7761B is

appropriate for their application.

CT

1

R

V

1B

F

LOAD

RA

C

F

1

RB

V

2P

VR

R

2N

Missing Neutral Detection

C

F

The ADE7761B continuously monitors the voltage input and

detects a missing neutral condition when the voltage input peak

value is smaller than 9% of the analog full scale or when no zero

crossings are detected on this input (see Figure 33).

1

RB + VR = RF.

Figure 31. Missing Neutral System Diagram

The ADE7761B detects a missing neutral condition by continu-

ously monitoring the voltage channel input (V_2P− V_2N). The

FAULT pin is held high when a missing neutral condition is

detected. In this mode, the ADE7761B continues to bill the energy

based on the signal level on the current channel (see Figure 32).

The billing rate or frequency outputs can be adjusted by changing

the dc level on the MISCAL pin.

V

MISSING

2P

NEUTRAL

FILTER AND

THRESHOLD

V2

ADC

V

2N

AGND

|V2|

< 9% OF FULL SCALE

OR

NO ZERO CROSSING ON V2

PEAK

V

1A

1N

1B

ADC

V

– V

2N

V

– V

2N

V – V

2P 2N

2P

A > B

HPF

FS

ADC

ZERO

CROSSING

DETECTION

B > A

A ≠ B

9% OF FS

0V

LPF

MISSING NEUTRAL

GAIN ADJUSMTENT

MISCAL

ADC

DIGITAL-TO-

FREQUENCY

CONVERTERS

Figure 33. Missing Neutral Detection

The ADE7761B leaves the missing neutral mode for normal

operation when both conditions are no longer valid; that is,

a voltage peak value of greater than 9% of full scale and zero

crossing on the voltage channel is detected (see Figure 34).

F1 F2

CF

Figure 32. Energy Calculation in Missing Neutral Mode

Important Note for Billing of Active Energy

V

MISSING

2P

NEUTRAL

The ADE7761B provides pulse outputs, CF, F1, and F2, that are

intended to be used for the billing of active energy. Pulses are

generated at these outputs in two different situations.

FILTER AND

THRESHOLD

V2

ADC

V

2N

AGND

Case 1

|V2|

PEAK

> 9% OF FULL SCALE

AND

When the analog input V_2P− V_2Ncomplies with the conditions

described in Figure 34, the CF, F₁, and F₂frequencies are propor-

tional to active power and can be used to bill active energy.

ZERO CROSSING ON V2

V

– V

2N

2P

FS

Case 2

+9% OF FS

–9% OF FS

When the analog input V_2P− V_2Ndoes not comply with the

conditions described in Figure 34, the ADE7761B does not

measure active energy but a quantity proportional to kAh. This

quantity is used to generate pulses on the same CF, F1, and F2.

This situation is indicated when the FAULT pin is high.

Figure 34. Return to Normal Mode After Missing Neutral Detection

Rev. 0 | Page 19 of 24

ADE7761B

Missing Neutral Gain Calibration

Example

When the ADE7761B is in missing neutral mode, the energy is

billed based on the active current input signal level. The frequency

outputs in this mode can be calibrated with the MISCAL analog

input pin. In this mode, applying a dc voltage of 330 mV on

MISCAL is equivalent to applying, in normal mode, a pure sine

wave on the voltage input with a peak value of 330 mV. The

MISCAL input can vary from 0 V to 660 mV (see the Analog

Inputs section). When set to 0 V, the frequency outputs are

close to zero. When set to 660 mV dc, the frequency outputs are

twice that when MISCAL is at 330 mV dc. In other words,

Equation 7 can be used in missing neutral mode by replacing

V2_rmsby MISCAL_rms/√2.

In normal mode, ac voltages of 330 mV peak are applied to

Channel V1 and Channel V2, and then the expected output

frequency on F1 and F2 is calculated as follows:

Gain =1; PGA =0

F_1–4= 1.7 Hz, SCF = S1 = S0 = 0

V1 = rms of 330 mV peak ac = 0.33/√2 V

V2 = rms of 330 mV peak ac = 0.33/√2 V

V_REF= 2.5 V (nominal reference value)

6.13× 0.33× 0.33×1.7Hz

F , F₂Frequency =

= 0.0917Hz

1

2 × 2 × 2.5²

F , F Frequency =

1

2

CF Frequency = F₁, F₂Frequency × 64 = 5.87 Hz

(8)

6.13×Gain×V1_rms× MISCAL_rms/ 2 × f₁₋₄

In missing neutral mode, the ac voltage of 330 mV peak is

applied to Channel V1, no signal is connected on Channel V2,

and a 330 mV dc input is applied to MISCAL. With the ADE7761B

in the same configuration as the previous example, the expected

output frequencies on CF, F1, and F2 are

2

V_REF

where:

F₁, F₂Frequency is the output frequency on F1 and F2 (Hz).

Gain is 1 or 16, depending on the PGA gain selection made

using Logic Input PGA.

6.13× 0.33× 0.33/ 2 ×1.7Hz

F₁, F₂Frequency =

= 0.0917Hz

V1_rmsis the differential rms voltage signal on Channel V1 (V).

MISCAL_rmsis the differential rms voltage signal on the MISCAL

pin (V).

2 × 2.5²

CF Frequency = F₁, F₂Frequency × 64 = 5.87 Hz

V_REFis the reference voltage (2.5 V 8%) (V).

f_1-4is one of four possible frequencies selected by using Logic

Input S0 and Logic Input S1 (see Table 6).

Rev. 0 | Page 20 of 24

ADE7761B

APPLICATIONS INFORMATION

INTERFACING TO A MICROCONTROLLER FOR

ENERGY MEASUREMENT

SELECTING A FREQUENCY FOR AN ENERGY

METER APPLICATION

The easiest way to interface the ADE7761B to a microcontroller

is to use the CF high frequency output with the output frequency

scaling set to 2048 × F₁, F₂. This is done by setting SCF = 0

and S0 = S1 = 1 (see Table 8). With full-scale ac signals on the

analog inputs, the output frequency on CF is approximately

5.5 kHz. Figure 35 illustrates one scheme that could be used to

digitize the output frequency and carry out the necessary

averaging mentioned in the Frequency Output CF section.

As shown in Table 6, the user can select one of four frequencies.

This frequency selection determines the maximum frequency

on F1 and F2. These outputs are intended to be used to drive

the energy register (electromechanical or other). Because only

four different output frequencies can be selected, the available

frequency selection was optimized for a meter constant of

100 impulses/kWh with a maximum current of between 10 A

and 120 A. Table 9 shows the output frequency for several

maximum currents (I_MAX) with a line voltage of 240 V. In all

cases, the meter constant is 100 impulses/kWh.

CF

FREQUENCY

RIPPLE

Table 9. F₁and F₂Frequency at 100 Impulses/kWh

AVERAGE

FREQUENCY

±10%

I_MAX(A)

12.ꢀ

2ꢀ

F₁and F₂(Hz)

0.083

0.166

0.266

0.4

40

TIME

60

MCU

80

0.ꢀ33

0.8

ADE7761B

COUNTER

120

CF

1

The f_1–4frequencies allow complete coverage of this range of

output frequencies on F1 and F2. When designing an energy

meter, the nominal design voltage on Channel V2 (voltage)

should be set to half-scale to allow for calibration of the meter

constant. The current channel should also be no more than half-

scale when the meter sees maximum load, which accommodates

overcurrent signals and signals with high crest factors. Table 10

shows the output frequency on F1 and F2 when both analog

inputs are half-scale. The frequencies listed in Table 10 align

well with those listed in Table 9 for maximum load.

UP/DOWN

REVP

2

FAULT

LOGIC

1

REVP MUST BE USED IF THE METER IS BIDIRECTIONAL OR

DIRECTION OF ENERGY FLOW IS NEEDED.

FAULT MUST BE USED TO RECORD ENERGY IN FAULT CONDITION.

2

Figure 35. Interfacing the ADE7761B to an MCU

As shown in Figure 35, the frequency output CF is connected to

an MCU counter or port that counts the number of pulses in a

given integration time, determined by an MCU internal timer.

The average power, proportional to the average frequency, is

Table 10. F₁and F₂Frequency with Half-Scale AC Inputs

Frequency on F1 and F2, Channel V1 and

S0 S1 f_1–4(Hz) Channel V2, Half-Scale AC Inputs (Hz)

Counter

Average Frequency = Average Active Power =

Timer

The energy consumed during an integration period is

Counter

0

1

0

1

0

1

1.72

3.44

6.86

13.ꢀ

0.092

0.183

0.337

0.734

Energy = Average Power ×Time =

×Time = Counter

Time

When selecting a suitable f_1–4frequency for a meter design, the

frequency output at I_MAX(maximum load) with a meter constant

of 100 impulses/kWh should be compared with Column 4 of

Table 10. The frequency that is closest in Table 10 determines

the best choice of frequency (f_1-4). For example, if a meter with

a maximum current of 40 A is being designed, the output

frequency on F1 and F2 with a meter constant of 100 impulses

per kWh is 0.266 Hz at 40 A and 240 V (see Table 9).

For the purpose of calibration, this integration time could be

10 sec to 20 sec to accumulate enough pulses to ensure correct

averaging of the frequency. In normal operation, the integration

time could be reduced to 1 sec or 2 sec, depending on, for

example, the required update rate of a display. With shorter

integration times on the MCU, the amount of energy in each

update may still have a small amount of ripple, even under

steady load conditions. However, over a minute or more, the

measured energy has no ripple.

Looking at Table 10, the closest frequency to 0.266 Hz

in Column 4 is 0.183 Hz. Therefore, F₂(3.4 Hz; see Table 6)

is selected for this design.

Rev. 0 | Page 21 of 24

ADE7761B

Frequency Outputs

For example, with an energy meter with a meter constant of

100 impulses per kWh on F1, F2 using SCF = 1, S1 = 0, and

S0 = 1, the maximum output frequency at F1 or F2 is 0.68 Hz

and 43.52 Hz on CF. The minimum output frequency at F1

or F2 is 0.0045% of 0.68 Hz or 3.06 × 10^–5Hz. This is 1.96 ×

10^–3Hz at CF (64 × F₁Hz).

Figure 2 is a timing diagram for the various frequency outputs.

The high frequency CF output is intended for communication

and calibration purposes. CF produces a 90 ms wide, active high

pulse (t₄) at a frequency that is proportional to active power. The

CF output frequencies are given in Table 8. As with F₁and F₂,

if the period of CF (t₅) falls below 180 ms, the CF pulse width is set

to half the period. For example, if the CF frequency is 20 Hz,

the CF pulse width is 25 ms.

In this example, the no-load threshold is equivalent to 1.1 W of

load or a startup current of 4.6 mA at 240 V. Compare this value

to the IEC 62053-21 specification, which states that the meter must

start up with a load equal to or less than 0.4% of I_B. For a 5 A (I_B)

meter, 0.4% of I_Bis equivalent to 20 mA.

No-Load Threshold

The ADE7761B includes a no-load threshold and start-up current

feature that eliminate creep effects in the meter. The ADE7761B

is designed to issue a minimum output frequency. Any load

generating a frequency lower than this minimum frequency

does not cause a pulse to be issued on F1, F2, or CF. The minimum

output frequency is given as 0.0045% of the full-scale output

frequency (see Table 8 for maximum output frequencies for

ac signals).

Note that the no-load threshold is not enabled when using the

high CF frequency mode: SCF = 0, S1 = S0 = 1.

NEGATIVE POWER INFORMATION

The ADE7761B detects when the current and voltage channels

have a phase shift greater than 90°. This mechanism can detect

a wrong connection of the meter or the generation of negative

power. The REVP pin output goes active high when negative

power is detected and active low when positive power is detected.

The REVP pin output changes state as a pulse is issued on CF.

Rev. 0 | Page 22 of 24

ADE7761B

OUTLINE DIMENSIONS

7.50

7.20

6.90

11

20

5.60

5.30

5.00

8.20

7.80

7.40

1

10

0.25

0.09

1.85

1.75

1.65

2.00 MAX

8°

4°

0°

0.95

0.75

0.55

0.38

0.22

0.05 MIN

SEATING

PLANE

COPLANARITY

0.10

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-150-AE

Figure 36. 20-Lead Shrink Small Outline Package [SSOP]

(RS-20)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADE7761BARS

ADE7761BARS-RL

ADE7761BARSZ¹

ADE7761BARSZ-RL¹

ADE7761BARS-REF

Temperature Range

–40°C to +8ꢀ°C

Package Description

Package Option

20-Lead Shrink Small Outline Package (SSOP)

Reference Board

RS-20

¹Z = RoHS Compliant Part.

Rev. 0 | Page 23 of 24

ADE7761B

NOTES

registered trademarks are the property of their respective owners.

D06797-0-8/07(0)

Rev. 0 | Page 24 of 24


型号：	ADE7761BARS-RL
厂家：	ADI
描述：	Energy Metering IC with On-Chip Fault and Missing Neutral Detection 电能计量IC ，带有片上故障和中性丢失检测模拟IC 信号电路光电二极管
文件：	总24页 (文件大小：528K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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