ADE7769ARZ_技术文档

Energy Metering IC with Integrated

Oscillator and No-Load Indication

ADE7769

The ADE7769 specifications surpass the accuracy require-

ments of the IEC62053-21 standard. The AN-679 Application

Note can be used as a basis for a description of an IEC61036

(equivalent to IEC62053-21) low cost, watt-hour meter

reference design.

FEATURES

On-chip oscillator as clock source

High accuracy, supports 50 Hz/60 Hz IEC62053-21

Less than 0.1% error over a dynamic range of 500 to 1

Supplies average real power on frequency outputs F1 and F2

High frequency output CF calibrates and supplies

instantaneous real power

CF output remains logic high when ADE7769 is under

no-load threshold

Logic output REVP indicates a potential miswiring or

negative power

The only analog circuitry used in the ADE7769 is in the Σ-Δ

ADCs and reference circuit. All other signal processing, such as

multiplication and filtering, is carried out in the digital domain.

This approach provides superior stability and accuracy over

time and extreme environmental conditions.

Direct drive for electromechanical counters and 2-phase

stepper motors (F1 and F2)

Proprietary ADCs and DSPs provide high accuracy over

large variations in environmental conditions and time

On-chip power supply monitoring

On-chip creep protection (no-load threshold)

The ADE7769 supplies average real power information on the

low frequency outputs, F1 and F2. These outputs can be used to

directly drive an electromechanical counter or interface with an

MCU. The high frequency CF logic output, ideal for calibration

purposes, provides instantaneous real power information.

On-chip reference 2.45 V (20 ppm/°C typical) with external

overdrive capability

Single 5 V supply, low power (20 mW typical)

Low cost CMOS process

The ADE7769 includes a power supply monitoring circuit on

the V_DDsupply pin. The ADE7769 remains inactive until the

supply voltage on V_DDreaches approximately 4 V. If the supply

falls below 4 V, the ADE7769 also remains inactive and the F1,

F2, and CF outputs are in their nonactive modes.

GENERAL DESCRIPTION

The ADE7769¹is a high accuracy electrical energy metering IC.

It is a pin reduction version of the ADE7755 with an enhanced,

precise oscillator circuit that serves as a clock source to the chip.

The ADE7769 eliminates the cost of an external crystal or

resonator, thus reducing the overall cost of a meter built with

this IC. The chip directly interfaces with the shunt resistor.

Internal phase matching circuitry ensures that the voltage and

current channels are phase matched, while the HPF in the

current channel eliminates dc offsets. An internal no-load

threshold ensures that the ADE7769 does not exhibit creep

when no load is present. During a no-load condition, the CF

pin stays logic high.

¹U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.

The ADE7769 has a 16-lead, narrow body SOIC package.

FUNCTIONAL BLOCK DIAGRAM

V

AGND

DGND

DD

1

6

13

ADE7769

POWER

SUPPLY MONITOR

SIGNAL

PROCESSING

BLOCK

V2P

V2N

2

3

...110101...

+

Σ-Δ

ADC

MULTIPLIER

PHASE

LPF

CORRECTION

...11011001...

4

5

V1N

V1P

Σ-Δ

ADC

Φ

HPF

DIGITAL-TO-FREQUENCY

CONVERTER

INTERNAL

OSCILLATOR

4kΩ

2.5V

REFERENCE

7

11

8

10

9

12

14

16

15

REF

RCLKIN

REVP CF

F1

SCF S0

S1

F2

IN/OUT

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADE7769

TABLE OF CONTENTS

Specifications..................................................................................... 3

Internal Oscillator (OSC).......................................................... 14

Transfer Function....................................................................... 14

Selecting a Frequency for an Energy Meter Application ...... 15

No-Load Threshold.................................................................... 16

Negative Power Information..................................................... 16

Evaluation Board and Reference Design Board..................... 16

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Terminology ...................................................................................... 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Functional Description.................................................................. 10

Theory of Operation .................................................................. 10

Analog Inputs.............................................................................. 11

Power Supply Monitor ............................................................... 12

REVISION HISTORY

8/05—Sp0 to Rev. A

Rev. A | Page 2 of 20

ADE7769

SPECIFICATIONS

V_DD= 5 V 5ꢀ, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 kΩ, 0.5ꢀ 50 ppm/°C, T_MINto T_MAX= −40°C to +85°C,

unless otherwise noted.

Table 1.

Parameter

Value

Unit

Test Conditions/Comments

ACCURACY^{1, 2}

Measurement Error¹on Channel V1

0.1

% reading typ

Channel V2 with full-scale signal ( 165 mVꢀ,

25°C over a dynamic range 500 to 1,

line frequency = 45 Hz to 65 Hz

Phase Error¹Between Channels

V1 Phase Lead 37° (PF = 0.8 Capacitiveꢀ

V1 Phase Lag 60° (PF = 0.5 Inductiveꢀ

AC Power Supply Rejection¹

0.1

Degrees (°ꢀ max

Output Frequency Variation (CFꢀ

0.2

0.3

% reading typ

S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms @

50 Hz, ripple on V_DDof 200 mV rms @ 100 Hz

DC Power Supply Rejection¹

Output Frequency Variation (CFꢀ

S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms,

V_DD= 5 V 250 mV

ANALOG INPUTS

See the Analog Inputs section

Channel V1 Maximum Signal Level

Channel V2 Maximum Signal Level

Input Impedance (DCꢀ

Bandwidth (–3 dBꢀ

30

165

320

7

mV max

kΩ min

kHz nominal

mV max

V1P and V1N to AGND

V2P and V2N to AGND

OSC = 450 kHz, RCLKIN = 6.2 kΩ, 0.5% 50 ppmꢁ°C

See the Terminology and Typical Performance

Characteristics sections

ADC Offset Error^{1, 2}

18

Gain Error¹

4

% ideal typ

External 2.5 V reference, V1 = 21.2 mV rms,

V2 = 116.7 mV rms

OSCILLATOR FREQUENCY (OSCꢀ

Oscillator Frequency Tolerance¹

Oscillator Frequency Stability¹

REFERENCE INPUT

450

12

30

kHz nominal

% reading typ

ppmꢁ°C typ

RCLKIN = 6.2 kΩ, 0.5% 50 ppmꢁ°C

REF_INꢁOUTInput Voltage Range

2.65

2.25

10

V max

V min

pF max

2.45 V nominal

Input Capacitance

ON-CHIP REFERENCE

Reference Error

Temperature Coefficient

LOGIC INPUTS³

2.45 V nominal

200

20

mV max

ppmꢁ°C typ

SCF, S0, S1

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.4

0.8

1

V min

V_DD= 5 V 5%

Typically 10 nA, V_IN= 0 V to V_DD

V max

μA max

pF max

Input Capacitance, C_IN

LOGIC OUTPUTS³

10

F1 and F2

Output High Voltage, V_OH

Output Low Voltage, V_OL

CF

Output High Voltage, V_OH

Output Low Voltage, V_OL

Frequency Output Error^{1, 2}(CFꢀ

4.5

0.5

V min

V max

I_SOURCE= 10 mA, V_DD= 5 V, I_SINK= 10 mA, V_DD= 5 V

I_SOURCE= 5 mA, V_DD= 5 V, I_SINK= 5 mA, V_DD= 5 V

4

0.5

10

V min

V max

% ideal typ

External 2.5 V reference, V1 = 21.2 mV rms,

V2 = 116.7 mV rms

Rev. A | Page 3 of 20

ADE7769

Parameter

POWER SUPPLY

V_DD

Value

Unit

Test Conditions/Comments

For specified performance

5 V – 5%

5 V + 5%

Typically 4 mA

4.75

5.25

5

V min

V max

mA max

I_DD

¹See the Terminology section for an explanation of specifications.

²See the figures in the Typical Performance Characteristics section.

³Sample tested during initial release and after any redesign or process change that may affect this parameter.

TIMING CHARACTERISTICS

V_DD= 5 V 5ꢀ, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 kΩ, 0.5ꢀ 50 ppm/°C, T_MINto T_MAX= −40°C to +85°C,

unless otherwise noted. Sample tested during initial release and after any redesign or process change that may affect this parameter.

See Figure 2.

Table 2.

Parameter

Specifications

Unit

Test Conditions/Comments

1

120

F1 and F2 pulse width (logic lowꢀ.

t₁

t₂

t₃

t₄

t₅

ms

sec

ms

sec

μs

See Table 6

1ꢁ2 t₂

90

See Table 7

2

Output pulse period. See the Transfer Function section.

Time between the F1 and F2 falling edges.

CF pulse width (logic highꢀ.

CF pulse period. See the Transfer Function section.

Minimum time between the F1 and F2 pulses.

1, 2

t₆

¹The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.

²The CF pulse is always 35 μs in high frequency mode. See the Frequency Outputs section and Table 7.

t₁

F1

t₆

t₂

F2

t₃

t₄

t₅

CF

Figure 2. Timing Diagram for Frequency Outputs

Rev. A | Page 4 of 20

ADE7769

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 3.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Value

V_DDto AGND

V_DDto DGND

−0.3 V to +7 V

–0.3 V to +7 V

Analog Input Voltage to AGND,

V1P, V1N, V2P, and V2N

–6 V to +6 V

Reference Input Voltage to AGND

Digital Input Voltage to DGND

Digital Output Voltage to DGND

Operating Temperature Range

Storage Temperature Range

Junction Temperature

–0.3 V to V_DD+ 0.3 V

–40°C to +85°C

–65°C to +150°C

150°C

16-Lead Plastic SOIC, Power Dissipation

θ_JAThermal Impedance¹

Package Temperature Soldering

350 mW

124.9°CꢁW

See J-STD-20

¹JEDEC 1S standard (2-layerꢀ board data.

ESD CAUTION

ESD (electrostatic dischargeꢀ sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-

tion or loss of functionality.

Rev. A | Page 5 of 20

ADE7769

TERMINOLOGY

Measurement Error

ADC Offset Error

The error associated with the energy measurement made by the

ADE7769 is defined by the following formula:

This refers to the small dc signal (offset) associated with the

analog inputs to the ADCs. However, the HPF in Channel V1

eliminates the offset in the circuitry. Therefore, the power

calculation is not affected by this offset.

Energy Registered by ADE7769 −True Energy

%Error =

× 100%

True Energy

Frequency Output Error (CF)

The frequency output error of the ADE7769 is defined as the

difference between the measured output frequency (minus the

offset) and the ideal output frequency. The difference is

expressed as a percentage of the ideal frequency. The ideal

frequency is obtained from the ADE7769 transfer function.

Phase Error Between Channels

The high-pass filter (HPF) in the current channel (Channel V1)

has a phase-lead response. To offset this phase response and

equalize the phase response between channels, a phase-

correction network is also placed in Channel V1. The phase-

correction network matches the phase to within 0.1° over a

range of 45 Hz to 65 Hz, and 0.2° over a range 40 Hz to 1 kHz

(see Figure 23 and Figure 24).

Gain Error

The gain error of the ADE7769 is defined as the difference

between the measured output of the ADCs (minus the offset)

and the ideal output of the ADCs. The difference is expressed as

a percentage of the ideal of the ADCs.

Power Supply Rejection (PSR)

This quantifies the ADE7769 measurement error as a

percentage of reading when the power supplies are varied.

Oscillator Frequency Tolerance

The oscillator frequency tolerance of the ADE7769 is defined as

the part-to-part frequency variation in terms of percentage

at room temperature (25°C). It is measured by taking the

difference between the measured oscillator frequency and the

nominal frequency defined in the Specifications section.

For the ac PSR measurement, a reading at nominal supplies

(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced

onto the supplies, and a second reading is obtained under the

same input signal levels. Any error introduced is expressed as a

percentage of reading—see the Measurement Error definition.

Oscillator Frequency Stability

For the dc PSR measurement, a reading at nominal supplies

(5 V) is taken. The supplies are then varied 5ꢀ and a second

reading is obtained with the same input signal levels. Any error

introduced is again expressed as a percentage of the reading.

Oscillator frequency stability is defined as frequency variation

in terms of the parts-per-million drift over the operating

temperature range. In a metering application, the temperature

range is −40°C to +85°C. Oscillator frequency stability is

measured by taking the difference between the measured

oscillator frequency at −40°C and +85°C and the measured

oscillator frequency at +25°C.

Rev. A | Page 6 of 20

ADE7769

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

1

2

3

4

5

6

7

8

16 F1

DD

V2P

V2N

15 F2

14 CF

ADE7769

V1N

13 DGND

12 REVP

11 RCLKIN

10 S0

TOP VIEW

(Not to Scale)

V1P

AGND

REF

IN/OUT

SCF

9

S1

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

V_DD

Power Supply. This pin provides the supply voltage for the circuitry in the ADE7769. The supply voltage

should be maintained at 5 V 5% for specified operation. This pin should be decoupled with a 10 μF

capacitor in parallel with a 100 nF ceramic capacitor.

2, 3

V2P, V2N

Analog Inputs for Channel V2 (Voltage Channelꢀ. These inputs provide a fully differential input pair. The

maximum differential input voltage is 165 mV for specified operation. Both inputs have internal ESD

protection circuitry; an overvoltage of 6 V can be sustained on these inputs without risk of permanent

damage.

4, 5

6

V1N, V1P

AGND

Analog Inputs for Channel V1 (Current Channelꢀ. These inputs are fully differential voltage inputs with a

maximum signal level of 30 mV with respect to the V1N pin for specified operation. Both inputs have

internal ESD protection circuitry and, in addition, an overvoltage of 6 V can be sustained on these inputs

without risk of permanent damage.

This pin provides the ground reference for the analog circuitry in the ADE7769, that is, the ADCs and

reference. This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the

ground reference for all analog circuitry, such as antialiasing filters, current and voltage sensors, and so forth.

For accurate noise suppression, the analog ground plane should be connected to the digital ground plane at

only one point. A star ground configuration helps to keep noisy digital currents away from the analog

circuits.

7

REF_INꢁOUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.45 V

and a typical temperature coefficient of 20 ppmꢁ°C. An external reference source may also be connected at

this pin. In either case, this pin should be decoupled to AGND with a 1 μF tantalum capacitor and a 100 nF

ceramic capacitor. The internal reference cannot be used to drive an external load.

8

SCF

Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. See

Table 7.

9, 10

S1, S0

These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion.

With this logic input, designers have greater flexibility when designing an energy meter. See the Selecting a

Frequency for an Energy Meter Application section.

11

12

RCLKIN

REVP

To enable the internal oscillator as a clock source to the chip, a precise low temperature drift resistor at a

nominal value of 6.2 kΩ must be connected from this pin to DGND.

This logic output goes high when negative power is detected, that is, when the phase angle between the

voltage and current signals is greater than 90°. This output is not latched and is reset when positive power is

once again detected. The output goes high or low at the same time that a pulse is issued on CF.

13

DGND

This pin provides the ground reference for the digital circuitry in the ADE7769, that is, the multiplier, filters,

and digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digital

ground plane is the ground reference for all digital circuitry, such as the counters (mechanical and digitalꢀ,

MCUs, and indicator LEDs. For accurate noise suppression, the analog ground plane should be connected to

the digital ground plane at one point only—a star ground.

14

CF

Calibration Frequency Logic Output. The CF logic output provides instantaneous real power information. This

output is intended for calibration purposes. See the SCF pin description. This output stays high when the part

is in a no-load condition.

15, 16

F2, F1

Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can be

used to directly drive electromechanical counters and 2-phase stepper motors. See the Transfer Function

section.

Rev. A | Page 7 of 20

ADE7769

TYPICAL PERFORMANCE CHARACTERISTICS

V

DD

+

100nF

10μF

1

K7

K8

V

DD

U3

602kΩ

200Ω

F1 16

4

1

2

3

V2P

150nF

15

14

220V

F2

U1

ADE7769

CF

2

3

200Ω

V2N

40A TO

PS2501-1

150nF

40mA

820Ω

12

11

REVP

200Ω

6.2kΩ

5

4

V1P

V1N

RCLKIN

+

150nF

V

DD

350μΩ

200Ω

10kΩ

150nF

100nF

10

9

S0

S1

7

REF

IN/OUT

+

8

SCF

1μF

10nF

AGND DGND

13

6

Figure 4. Test Circuit for Performance Curves

1.0

0.8

0.6

0.4

0.2

0

1.0

PF = 1

ON-CHIP REFERENCE

PF = 1

EXTERNAL REFERENCE

0.8

0.6

0.4

0.2

0

+85°C

–40°C

+25°C

+85°C

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–40°C

0.1

1

10

100

0.1

1

10

100

CURRENT CHANNEL (% of Full Scale)

Figure 7. Error as a % of Reading over Temperature

with External Reference (PF = 1)

Figure 5. Error as a % of Reading over Temperature

with On-Chip Reference (PF = 1)

1.0

0.8

0.6

0.4

0.2

0

1.0

0.8

0.6

0.4

0.2

0

PF = 0.5 IND

EXTERNAL REFERENCE

PF = 0.5 IND

ON-CHIP REFERENCE

+85°C, PF = 0.5 IND

+25°C, PF = 1

–40°C, PF = 0.5 IND

+25°C, PF = 1

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

+25°C, PF = 0.5 IND

+85°C, PF = 0.5 IND

–40°C, PF = 0.5 IND

+25°C, PF = 0.5 IND

0.1

1

10

100

0.1

1

10

100

CURRENT CHANNEL (% of Full Scale)

Figure 6. Error as a % of Reading over Temperature

with On-Chip Reference (PF = 0.5 IND)

Figure 8. Error as a % of Reading over Temperature

with External Reference (PF = 0.5 IND)

Rev. A | Page 8 of 20

ADE7769

0.5

0.4

40

DISTRIBUTION CHARACTERISTICS

MEAN = 2.247828

EXTERNAL REFERENCE

TEMPERATURE = 25°C

SDs = 1.367176

MIN = –2.09932

MAX = +5.28288

0.3

30 NO. OF POINTS = 100

0.2

PF = 0.5 IND

PF = 1

0.1

0

20

10

0

–0.1

–0.2

–0.3

–0.4

–0.5

PF = 0.5 CAP

–5 –4 –3 –2 –1

0

1

2

3

4

5

6

7

8

9

45

50

55

FREQUENCY (Hz)

60

65

CHANNEL V1 OFFSET (mV)

Figure 12. Channel V1 Offset Distribution

Figure 9. Error as a % of Reading over Input Frequency

1.0

50

40

30

20

10

0

PF = 1

DISTRIBUTION CHARACTERISTICS

MEAN = –1.563484

0.8

0.6

0.4

0.2

0

ON-CHIP REFERENCE

SDs = 2.040699

EXTERNAL REFERENCE

TEMPERATURE = 25°C

MIN = –6.82969

MAX = +2.6119

NO. OF POINTS = 100

5.25V

5V

4.75V

–0.2

–0.4

–0.6

–0.8

–1.0

0.1

1

10

100

–12 –10 –8 –6 –4 –2

0

2

4

6

8

10 12

CURRENT CHANNEL (% of Full Scale)

CHANNEL V2 OFFSET (mV)

Figure 10. PSR with On-Chip Reference, PF = 1

Figure 13. Channel V2 Offset Distribution

1.0

0.8

0.6

0.4

0.2

0

1000

800

600

400

200

0

DISTRIBUTION CHARACTERISTICS

MEAN = 0%

PF = 1

EXTERNAL REFERENCE

SDs = 1.55%

TEMPERATURE = 25°C

MIN = –11.79%

MAX = +6.08%

NO. OF POINTS = 3387

5.25V

5V

–0.2

–0.4

–0.6

–0.8

–1.0

4.75V

0.1

1

10

100

–10 –8 –6 –4 –2

0

2

4

6

8

10 12

CURRENT CHANNEL (% of Full Scale)

DEVIATION FROM MEAN (%)

Figure 11. PSR with External Reference, PF = 1

Figure 14. Part-to-Part CF Deviation from Mean

Rev. A | Page 9 of 20

ADE7769

FUNCTIONAL DESCRIPTION

THEORY OF OPERATION

Power Factor Considerations

The method used to extract the real power information from

the instantaneous power signal, that is, by low-pass filtering, is

still valid even when the voltage and current signals are not in

phase. Figure 16 shows the unity power factor condition and a

displacement power factor (DPF) = 0.5, that is, current signal

lagging the voltage by 60°. Assuming that the voltage and

current waveforms are sinusoidal, the real power component of

the instantaneous power signal (that is, the dc term) is given by

The two ADCs in the ADE7769 digitize the voltage signals from

the current and voltage sensors. These ADCs are 16-bit Σ-Δs

with an oversampling rate of 450 kHz. This analog input

structure greatly simplifies sensor interfacing by providing a

wide dynamic range for direct connection to the sensor and by

simplifying the antialiasing filter design. A high-pass filter in

the current channel removes any dc component from the

current signal. This eliminates any inaccuracies in the real

power calculation due to offsets in the voltage or current

signals.

V × I

⎛

⎜

⎞

⎟

× cos

(

60°

)

(1)

2

⎝

⎠

The real power calculation is derived from the instantaneous

power signal. The instantaneous power signal is generated by

a direct multiplication of the current and voltage signals. To

extract the real power component (the dc component), the

instantaneous power signal is low-pass filtered. Figure 15

illustrates the instantaneous real power signal and shows how

the real power information can be extracted by low-pass

filtering the instantaneous power signal. This scheme correctly

calculates real power for sinusoidal current and voltage

waveforms at all power factors. All signal processing is carried

out in the digital domain for superior stability over temperature

and time.

This is the correct real power calculation.

INSTANTANEOUS

POWER SIGNAL

INSTANTANEOUS REAL

POWER SIGNAL

POWER

V × I

2

0V

TIME

CURRENT

VOLTAGE

INSTANTANEOUS REAL

POWER SIGNAL

POWER

INSTANTANEOUS

POWER SIGNAL

DIGITAL-TO-

FREQUENCY

F1

CH1

CH2

ADC

F2

V × I

2

HPF

COS (60°)

0V

MULTIPLIER

DIGITAL-TO-

FREQUENCY

TIME

LPF

ADC

CF

VOLTAGE

CURRENT

60°

INSTANTANEOUS

POWER SIGNAL – p(t)

INSTANTANEOUS REAL

POWER SIGNAL

Figure 16. DC Component of Instantaneous Power Signal Conveys

Real Power Information, PF < 1

Nonsinusoidal Voltage and Current

The real power calculation method also holds true for

nonsinusoidal current and voltage waveforms. All voltage

and current waveforms in practical applications have some

harmonic content. Using the Fourier transform, instantaneous

voltage and current waveforms can be expressed in terms of

their harmonic content.

TIME

Figure 15. Signal Processing Block Diagram

The low frequency outputs (F1 and F2) are generated by

accumulating this real power information. This low frequency

inherently means a long accumulation time between output

pulses. Consequently, the resulting output frequency is propor-

tional to the average real power. This average real power

information is then accumulated (by a counter) to generate real

energy information. Conversely, due to its high output frequen-

cy and shorter integration time, the CF output frequency is

proportional to the instantaneous real power. This is useful for

system calibration, which can be done faster under steady load

conditions.

v(t) = V₀+ 2 × ^∞V × sin

(

hωt + α_h

)

(2)

∑

h

h≠0

where:

v(t) is the instantaneous voltage.

V₀is the average value.

V_his the rms value of voltage harmonic h.

α_his the phase angle of the voltage harmonic.

Rev. A | Page 10 of 20

ADE7769

∞

Figure 17 shows the maximum signal levels on V1P and V1N.

The maximum differential voltage is 30 mV. The differential

voltage signal on the inputs must be referenced to a common

mode, for example, AGND. The maximum common-mode

signal is 6.25 mV, as shown in Figure 17.

i(t) = I + 2 × I × sin

(

hωt + β_h

)

(3)

∑

O

h

h≠o

where:

i(t) is the instantaneous current.

I₀is the dc component.

I_his the rms value of current harmonic h.

Channel V2 (Voltage Channel)

The output of the line voltage sensor is connected to the

ADE7769 at this analog input. Channel V2 is a fully differential

voltage input with a maximum peak differential signal of

165 mV. Figure 18 shows the maximum signal levels that can

be connected to the ADE7769 Channel V2.

β_his the phase angle of the current harmonic.

Using Equations 2 and 3, the real power (P) can be expressed in

terms of its fundamental real power (P₁) and harmonic real

power (P_H) as P = P₁+ P_H

V2

where:

+165mV

P = V₁× I₁cos φ₁

(4)

1

V2P

V2N

DIFFERENTIAL INPUT

V2

φ₁= α₁− β₁

±165mV MAX PEAK

V

CM

COMMON-MODE

V

and

CM

±25mV MAX

∞

AGND

–165mV

P = V × I cos φ

(5)

∑

H

h

h≠1

Figure 18. Maximum Signal Levels, Channel V2

φ_h= α_h− β_h

Channel V2 is usually driven from a common-mode voltage,

that is, the differential voltage signal on the input is referenced

to a common mode (usually AGND). The analog inputs of the

ADE7769 can be driven with common-mode voltages of up to

25 mV with respect to AGND. However, best results are

achieved using a common mode equal to AGND.

In Equation 5, a harmonic real power component is generated

for every harmonic, provided that harmonic is present in both

the voltage and current waveforms. The power factor calcu-

lation has previously been shown to be accurate in the case of a

pure sinusoid. Therefore, the harmonic real power must also

correctly account for the power factor because it is made up of

a series of pure sinusoids.

Typical Connection Diagrams

Figure 19 shows a typical connection diagram for Channel V1.

A shunt is the current sensor selected for this example because

of its low cost compared to other current sensors, such as the

current transformer (CT). This IC is ideal for low current meters.

Note that the input bandwidth of the analog inputs is 7 kHz at

the nominal internal oscillator frequency of 450 kHz.

ANALOG INPUTS

R

V1P

F

Channel V1 (Current Channel)

C

F

The voltage output from the current sensor is connected to the

ADE7769 here. Channel V1 is a fully differential voltage input.

V1P is the positive input with respect to V1N.

SHUNT

V1N

±30mV

C

R

F

AGND

The maximum peak differential signal on Channel V1 should

be less than 30 mV (21 mV rms for a pure sinusoidal signal)

for specified operation.

PHASE NEUTRAL

Figure 19. Typical Connection for Channel V1

Figure 20 shows a typical connection for Channel V2. Typically,

the ADE7769 is biased around the phase wire, and a resistor

divider is used to provide a voltage signal that is proportional to

the line voltage. Adjusting the ratio of R_A, R_B, and R_Fis also a

convenient way of carrying out a gain calibration on a meter.

V1

+30mV

V1P

V1N

DIFFERENTIAL INPUT

V1

±30mV MAX PEAK

V

CM

COMMON-MODE

V

CM

±6.25mV MAX

AGND

–30mV

Figure 17. Maximum Signal Levels, Channel V1

Rev. A | Page 11 of 20

ADE7769

R

B

R

*

V2P

V2N

A

Equation 6 shows how the power calculation is affected by the

dc offsets in the current and voltage channels.

±165mV

R

C

F

R

C

F

{V cos

(

ωt

)

+V_OS}×{I cos

(

ωt

)

+ I_OS

}

(6)

V × I

2

*R >> R + R

F

NEUTRAL PHASE

(

)

(

)

=

+V_OS× I_OS+V_OS× I cos ωt + I_OS×V cos ωt

A

B

Figure 20. Typical Connections for Channel V2

V × I

2

+

× cos 2ωt

( )

POWER SUPPLY MONITOR

The ADE7769 contains an on-chip power supply monitor. The

power supply (V_DD) is continuously monitored by the ADE7769.

If the supply is less than 4 V, the ADE7769 becomes inactive.

This is useful to ensure proper device operation at power-up

and power-down. The power supply monitor has built-in

hysteresis and filtering, which provide a high degree of

immunity to false triggering from noisy supplies.

DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR REAL

POWER CALCULATION

V

× I

OS

V × I

2

I

× V

OS

V

× I

OS

In Figure 21, the trigger level is nominally set at 4 V. The toler-

ance on this trigger level is within 5ꢀ. The power supply and

decoupling for the part should be such that the ripple at V_DD

does not exceed 5 V 5ꢀ, as specified for normal operation.

0

FREQUENCY (RAD/s)

Figure 22. Effect of Channel Offset on the Real Power Calculation

The HPF in Channel V1 has an associated phase response that

is compensated for on chip. Figure 23 and Figure 24 show the

phase error between channels with the compensation network

activated. The ADE7769 is phase compensated up to 1 kHz as

shown. This ensures correct active harmonic power calculation

even at low power factors.

V

DD

5V

4V

0V

0.30

0.25

0.20

0.15

0.10

0.05

0

TIME

INTERNAL

ACTIVATION

INACTIVE

ACTIVE

INACTIVE

Figure 21. On-Chip Power Supply Monitor

HPF and Offset Effects

Figure 22 shows the effect of offsets on the real power calcula-

tion. As can be seen, offsets on Channel V1 and Channel V2

contribute a dc component after multiplication. Because this dc

component is extracted by the LPF and used to generate the real

power information, the offsets contribute a constant error to the

real power calculation. This problem is easily avoided by the

built-in HPF in Channel V1. By removing the offsets from at

least one channel, no error component can be generated at dc

by the multiplication. Error terms at the line frequency (ω) are

removed by the LPF and the digital-to-frequency conversion

(see the Digital-to-Frequency Conversion section).

–0.05

–0.10

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (Hz)

Figure 23. Phase Error Between Channels (0 Hz to 1 kHz)

Rev. A | Page 12 of 20

ADE7769

0.30

0.25

0.20

0.15

0.10

0.05

0

F1

DIGITAL-TO-

FREQUENCY

F1

V

F2

TIME

MULTIPLIER

DIGITAL-TO-

FREQUENCY

LPF

CF

I

CF

LPF TO EXTRACT

REAL POWER

(DC TERM)

V × I

2

COS (2ω)

–0.05

–0.10

ATTENUATED BY LPF

40

45

50

55

60

65

70

FREQUENCY (Hz)

ω

0

2ω

FREQUENCY (RAD/s)

INSTANTANEOUS REAL POWER SIGNAL

(FREQUENCY DOMAIN)

Figure 24. Phase Error Between Channels (40 Hz to 70 Hz)

Digital-to-Frequency Conversion

Figure 25. Real Power-to-Frequency Conversion

As previously described, the digital output of the low-pass

filter after multiplication contains the real power information.

However, because this LPF is not an ideal brick wall filter

implementation, the output signal also contains attenuated

components at the line frequency and its harmonics, that is,

cos(hωt) where h = 1, 2, 3, … and so on.

In Figure 25, the frequency output, CF, varies over time, even

under steady load conditions. This frequency variation is

primarily due to the cos(2ωt) component in the instantaneous

real power signal. The output frequency on CF can be up to

2048 times higher than the frequency on F1 and F2. This higher

output frequency is generated by accumulating the instan-

taneous real power signal over a much shorter time while

converting it to a frequency. This shorter accumulation period

means less averaging of the cos(2ωt) component. Consequently,

some of this instantaneous power signal passes through the

digital-to-frequency conversion. This is not a problem in the

application. Where CF is used for calibration purposes, the

frequency should be averaged by the frequency counter, which

removes any ripple. If CF is being used to measure energy, for

example in a microprocessor based application, the CF output

should also be averaged to calculate power.

The magnitude response of the filter is given by

1

H

(

f

)

=

(7)

f ²

1 +

4.45²

For a line frequency of 50 Hz, this gives an attenuation of

the 2ω (100 Hz) component of approximately 22 dB. The

dominating harmonic is twice the line frequency (2ω) due to

the instantaneous power calculation.

Figure 25 shows the instantaneous real power signal at the

output of the LPF that still contains a significant amount of

instantaneous power information, that is, cos(2ωt). This

signal is then passed to the digital-to-frequency converter

where it is integrated (accumulated) over time to produce an

output frequency. The accumulation of the signal suppresses or

averages out any non-dc components in the instantaneous real

power signal. The average value of a sinusoidal signal is zero.

Thus, the frequency generated by the ADE7769 is proportional

to the average real power. Figure 25 shows the digital-to-

frequency conversion for steady load conditions, that is,

constant voltage and current.

Because the F1 and F2 outputs operate at a much lower

frequency, much more averaging of the instantaneous real

power signal is carried out. The result is a greatly attenuated

sinusoidal content and a virtually ripple-free frequency output.

Connecting to a Microcontroller for Energy

Measurement

The easiest way to interface the ADE7769 to a microcontroller

is to use the CF high frequency output with the output

frequency scaling set to 2048 × F1, F2. This is done by setting

SCF = 0 and S0 = S1 = 1 (see Table 7). With full-scale ac

signals on the analog inputs, the output frequency on CF is

approximately 2.867 kHz. Figure 26 shows one scheme that

could be used to digitize the output frequency and carry out

the necessary averaging mentioned in the previous section.

Rev. A | Page 13 of 20

ADE7769

CF

INTERNAL OSCILLATOR (OSC)

FREQUENCY

RIPPLE

The nominal internal oscillator frequency is 450 kHz when

used with RCLKIN, with a nominal value of 6.2 kΩ. The

frequency outputs are directly proportional to the oscillator

frequency, thus RCLKIN must have low tolerance and low

temperature drift to ensure stability and linearity of the chip.

The oscillator frequency is inversely proportional to the

RCLKIN, as shown in Figure 27. Although the internal

oscillator operates when used with RCLKIN values between

5.5 kΩ and 20 kΩ, choosing a value within the range of the

nominal value, as shown in Figure 27, is recommended.

AVERAGE

±10%

FREQUENCY

TIME

MCU

ADE7769

COUNTER

CF

490

480

470

460

450

440

430

420

410

400

TIMER

Figure 26. Interfacing the ADE7769 to an MCU

As shown in Figure 26, the frequency output, CF, is connected

to an MCU counter or port. This counts the number of pulses

in a given integration time, which is determined by an MCU

internal timer. The average power proportional to the average

frequency is given by

Counter

Time

Average Frequency = Average Power =

(8)

The energy consumed during an integration period is given by

5.8

5.9

6.0

6.1

6.2

6.3

6.4

6.5

6.6

6.7

RESISTANCE (kΩ)

Counter

Time

Energy = Average Power ×Time =

× Time = Counter (9)

Figure 27. Effect of RCLKIN on Internal Oscillator Frequency (OSC)

TRANSFER FUNCTION

For the purpose of calibration, this integration time could be

10 seconds to 20 seconds to accumulate enough pulses to

Frequency Outputs F1 and F2

ensure correct averaging of the frequency. In normal operation,

the integration time could be reduced to 1 or 2 seconds,

depending, for example, on the required update rate of a

display. With shorter integration times on the MCU, the

amount of energy in each update may still have some small

amount of ripple, even under steady load conditions. However,

over a minute or more the measured energy has no ripple.

The ADE7769 calculates the product of two voltage signals

(on Channel V1 and Channel V2) and then low-pass filters this

product to extract real power information. This real power

information is then converted to a frequency. The frequency

information is output on F1 and F2 in the form of active low

pulses. The pulse rate at these outputs is relatively low, for

example, 0.175 Hz maximum for ac signals with S0 = S1 = 0

(see Table 6). This means that the frequency at these outputs is

generated from real power information accumulated over a

relatively long period of time. The result is an output frequency

that is proportional to the average real power. The averaging of

the real power signal is implicit to the digital-to-frequency

conversion. The output frequency or pulse rate is related to the

input voltage signals by the following equation:

Power Measurement Considerations

Calculating and displaying power information always has some

associated ripple, which depends on the integration period used

in the MCU to determine average power and also on the load.

For example, at light loads, the output frequency may be 10 Hz.

With an integration period of 2 seconds, only about 20 pulses

are counted. The possibility of missing one pulse always exists,

because the ADE7769 output frequency is running asynchro-

nously to the MCU timer. This results in a 1-in-20, or 5ꢀ, error

in the power measurement.

494.75×V1_rms×V2_rms× F₁₋₄

Freq =

(10)

2

V_REF

where:

Freq is the output frequency on F1 and F2 (Hz).

V1_rmsis the differential rms voltage signal on Channel V1 (V).

V2_rmsis the differential rms voltage signal on Channel V2 (V).

V

F

_REF= is the reference voltage (2.45 V 200 mV) (V).

_1–4= are one of four possible frequencies selected by using

the S0 and S1logic inputs (see Table 5).

Rev. A | Page 14 of 20

ADE7769

Table 5. F_1–4Frequency Selection

Table 7. Maximum Output Frequency on CF

S1

S0

OSC Relation¹

OSCꢁ2₁₉

F_1–4at Nominal OSC (Hz)²

SCF

S1

S0

CF Max for AC Signals (Hz)¹

0

0.86

1.72

3.43

6.86

1

0

1

0

1

0

1

0

1

0

1

0

1

128 × F1, F2 = 22.4

64 × F1, F2 = 11.2

64 × F1, F2 = 22.4

32 × F1, F2 = 11.2

32 × F1, F2 = 22.4

16 × F1, F2 = 11.2

16 × F1, F2 = 22.4

2048 × F1, F2 = 2.867 kHz

0

1

OSCꢁ2₁₈

1

0

OSCꢁ2₁₇

1

OSCꢁ2₁₆

¹F_1–4is a binary fraction of the internal oscillator frequency.

²Values are generated using the nominal frequency of 450 kHz.

Example

In this example, with ac voltages of 30 mV peak applied to

V1 and 165 mV peak applied to V2, the expected output

frequency is calculated as

¹Values are generated using the nominal frequency of 450 kHz.

SELECTING A FREQUENCY FOR AN ENERGY

METER APPLICATION

F

_1–4= OSC/2¹⁹Hz, S0 = S1 = 0

V1_rms= 0.03/√2 V

V2_rms= 0.165/√2 V

As shown in Table 5, the user can select one of four frequencies.

This frequency selection determines the maximum frequency

on F1 and F2. These outputs are intended for driving an energy

register (electromechanical or other). Because only four

different output frequencies can be selected, the available

frequency selection has been optimized for a meter constant

of 100 imp/kWh with a maximum current of between 10 A

and 120 A. Table 8 shows the output frequency for several

maximum currents (I_MAX) with a line voltage of 220 V. In all

cases, the meter constant is 100 imp/kWh.

V

_REF= 2.45 V (nominal reference value)

If the on-chip reference is used, actual output frequencies

may vary from device to device due to the reference tolerance

of 200 mV.

494.75 × 0.03× 0.165× F₁

2 × 2 × 2.45²

(11)

Freq =

= 0.204 × F₁= 0.175

Table 6. Maximum Output Frequency on F1 and F2

S1 S0 OSC Relation

Max Frequency¹or AC Inputs (Hz)

Table 8. F1 and F2 Frequency at 100 imp/kWh

I_MAX(A)

F1 and F2 (Hz)

0

1

0

1

0

1

0.204 × F₁

0.204 × F₂

0.204 × F₃

0.204 × F₄

0.175

0.35

0.70

1.40

12.5

25.0

40.0

0.076

0.153

0.244

60.0

0.367

¹Values are generated using the nominal frequency of 450 kHz.

80.0

120.0

0.489

0.733

Frequency Output CF

The pulse output CF (calibration frequency) is intended for

calibration purposes. The output pulse rate on CF can be up to

2048 times the pulse rate on F1 and F2. The lower the F_1–4

frequency selected, the higher the CF scaling (except for the

high frequency mode SCF = 0, S1 = S0 = 1). Table 7 shows how

the two frequencies are related, depending on the states of the

logic inputs S0, S1, and SCF. Due to its relatively high pulse

rate, the frequency at the CF logic output is proportional to the

instantaneous real power. As with F1 and F2, CF is derived

from the output of the low-pass filter after multiplication.

However, because the output frequency is high, this real

power information is accumulated over a much shorter time.

Therefore, less averaging is carried out in the digital-to-

frequency conversion. With much less averaging of the real

power signal, the CF output is much more responsive to power

fluctuations (see the signal processing block diagram shown in

Figure 15).

The F_1–4frequencies allow complete coverage of this range of

output frequencies (F1, F2). When designing an energy meter,

the nominal design voltage on Channel V2 (voltage) should be

set to half-scale to allow for calibration of the meter constant.

The current channel should also be no more than half scale

when the meter sees maximum load. This allows overcurrent

signals and signals with high crest factors to be accommodated.

Table 9 shows the output frequency on F1 and F2 when both

analog inputs are half scale. The frequencies in Table 9 align

very well with those in Table 8 for maximum load.

Table 9. F1 and F2 Frequency with Half-Scale AC Inputs

Frequency on F1 and F2—

S1 S0 F_1–4(Hz) CH1 and CH2 Half-Scale AC Input¹

0

1

0

1

0

1

0.86

1.72

3.43

6.86

0.044 Hz

0.088 Hz

0.176 Hz

0.352 Hz

0.051 × F₁

0.051 × F₂

0.051 × F₃

0.051 × F₄

¹Values are generated using the nominal frequency of 450 kHz.

Rev. A | Page 15 of 20

ADE7769

When selecting a suitable F_1–4frequency for a meter design, the

frequency output at I_MAX(maximum load) with a meter constant

of 100 imp/kWh should be compared with Column 4 of Table 9.

The closest frequency in Table 9 determines the best choice of

frequency (F_1–4). For example, if a meter with a maximum

current of 25 A is being designed, the output frequency on F1

and F2 with a meter constant of 100 imp/kWh is 0.153 Hz at 25

A and 220 V (from Table 8). In Table 9 the closest frequency to

0.153 Hz in Column 4 is 0.176 Hz. Therefore, as shown in Table

5, F3 (3.43 Hz) is selected for this design.

The no-load condition is indicated with CF output pulse

remaining logic high, as shown in Figure 28.

ACTIVE POWER

NO-LOAD

THRESHOLD

TIME

0W

CF FREQUENCY PROPORTIONAL TO POWER

Frequency Outputs

CF

Figure 2 shows a timing diagram for the various frequency

outputs. The F1 and F2 outputs are the low frequency

outputs that can be used to directly drive a stepper motor or

electromechanical impulse counter. The F1 and F2 outputs

provide two alternating low frequency pulses. The F1 and F2

pulse widths (t₁) are set such that if they fall below 240 ms

(0.24 Hz), they are set to half of their period. The maximum

output frequencies for F1 and F2 are shown in Table 6.

Figure 28. No-Load Indication Using ADE7769

NEGATIVE POWER INFORMATION

The ADE7769 detects when the current and voltage channels

have a phase shift greater than 90°. This mechanism can detect

an incorrect meter connection or the generation of negative

power. The REVP pin output goes active high when negative

power is detected and active low if positive power is detected.

The REVP pin output changes state as a pulse is issued on CF.

The high frequency CF output is intended to be used for

communications and calibration purposes. CF produces a

90-ms-wide active high pulse (t₄) at a frequency proportional to

active power. The CF output frequencies are given in Table 7.

As with F1 and F2, if the period of CF (t₅) falls below 180 ms,

the CF pulse width is set to half the period. For example, if the

CF frequency is 20 Hz, the CF pulse width is 25 ms.

EVALUATION BOARD AND REFERENCE DESIGN

BOARD

An evaluation board can be used to verify the functionality and

the performance of the ADE7769. Download the documenta-

tion for the board from http://www.analog.com/ADE7769.

When high frequency mode is selected (that is, SCF = 0,

S1 = S0 = 1), the CF pulse width is fixed at 35 μs. Therefore,

t₄is always 35 μs, regardless of output frequency on CF.

In addition, the reference design board ADE7769ARN-REF

and Application Note AN-679 can be used in the design

of a low cost watt-hour meter that surpasses IEC62053-21

accuracy specifications. The application note can be

downloaded from http://www.analog.com/ADE7769.

NO-LOAD THRESHOLD

The ADE7769 includes a no-load threshold and start-up

current feature, which eliminates any creep effects in the meter.

The ADE7769 is designed to issue a minimum output

frequency. Any load generating a frequency lower than this

minimum frequency does not cause a pulse to be issued on F1

or F2. The minimum output frequency is given as 0.00244ꢀ for

each of the F_1–4frequency selections (see Table 5).

For example, for an energy meter with a meter constant of

100 imp/kWh on F1, F2 using F₃(3.43 Hz), the minimum

output frequency at F1 or F2 would be 0.00244ꢀ of 3.43 Hz or

8.38 × 10^–5Hz. This would be 2.68 × 10^–3Hz at CF (32 × F1 Hz)

when SCF = S0 = 1, S1 = 0. In this example, the no-load

threshold would be equivalent to 3 W of load or a start-up

current of 13.72 mA at 220 V. Compare this value to the

IEC62053-21 specification which states that the meter must

start up with a load equal to or less than 0.4ꢀ Ib. For a 5 A (Ib)

meter, 0.4ꢀ of Ib is equivalent to 20 mA.

Rev. A | Page 16 of 20

ADE7769

OUTLINE DIMENSIONS

10.00 (0.3937)

9.80 (0.3858)

16

1

9

8

6.20 (0.2441)

5.80 (0.2283)

4.00 (0.1575)

3.80 (0.1496)

1.75 (0.0689)

1.35 (0.0531)

1.27 (0.0500)

BSC

0.50 (0.0197)

0.25 (0.0098)

× 45°

0.25 (0.0098)

0.10 (0.0039)

8°

0°

0.51 (0.0201)

0.31 (0.0122)

SEATING

PLANE

1.27 (0.0500)

0.40 (0.0157)

COPLANARITY

0.10

0.25 (0.0098)

0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 29. 16-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADE7769AR

−40°C to +85°C

16-Lead Standard Small Outline Package [SOIC_N]

16-Lead Standard Small Outline Package [SOIC_N] REEL

16-Lead Standard Small Outline Package [SOIC_N]

16-Lead Standard Small Outline Package [SOIC_N] REEL

Evaluation Board

R-16

ADE7769AR-RL

ADE7769ARZ¹

ADE7769ARZ-RL¹

EVAL-ADE7769EB

ADE7769AR-REF

Reference Design Board

¹Z = Pb-free part.

Rev. A | Page 17 of 20

ADE7769

NOTES

Rev. A | Page 18 of 20

ADE7769

NOTES

Rev. A | Page 19 of 20

ADE7769

NOTES

registered trademarks are the property of their respective owners.

D05332–0–8/05(A)

Rev. A | Page 20 of 20


型号：	ADE7769ARZ
厂家：	ADI
描述：	Energy Metering IC with Integrated Oscillator and No-Load Indication 电能计量IC，集成振荡器和无负载指示振荡器电源电路电源管理电路光电二极管
文件：	总20页 (文件大小：386K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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