ADF4107BCP [ADI]
PLL Frequency Synthesizer; PLL频率合成器
| 型号： | ADF4107BCP |
| 厂家： | 
ADI |
| 描述： | PLL Frequency Synthesizer |
| 文件： | 总20页 (文件大小：752K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL Frequency Synthesizer
ADF4107
FEATURES
GENERAL DESCRIPTION
7.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulsewidth
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
The ADF4107 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low-noise digital PFD (phase frequency detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual-modulus prescaler (P/P + 1). The
A (6-bit) and B (13-bit) counters, in conjunction with the dual-
modulus prescaler (P/P + 1), implement an N divider
(N = BP + A). In addition, the 14-bit reference counter
(R counter), allows selectable REFIN frequencies at the PFD
input. A complete PLL (phase-locked loop) can be implemented
if the synthesizer is used with an external loop filter and VCO
(voltage controlled oscillator). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio
FUNCTIONAL BLOCK DIAGRAM
AV
DV
R
SET
V
CPGND
DD
DD
P
REFERENCE
14-BIT
PHASE
REF
CHARGE
PUMP
IN
R COUNTER
CP
FREQUENCY
DETECTOR
14
R COUNTER
LATCH
LOCK
CURRENT
SETTING 2
CURRENT
SETTING 1
DETECT
CLK
DATA
LE
24-BIT INPUT
REGISTER
FUNCTION
LATCH
CPI6 CPI5 CPI4
HIGH Z
CPI3 CPI2 CPI1
22
A, B COUNTER
LATCH
FROM
SD
19
OUT
AV
FUNCTION
LATCH
DD
MUXOUT
MUX
13
N = BP + A
13-BIT
SD
OUT
B COUNTER
LOAD
RF
RF
A
B
PRESCALER
P/P + 1
IN
IN
LOAD
M3 M2 M1
6-BIT
A COUNTER
ADF4107
6
CE
AGND DGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
ADF4107
TABLE OF CONTENTS
ADF4107—Specifications................................................................ 3
Latch Summary........................................................................... 11
Reference Counter Latch Map.................................................. 12
AB Counter Latch Map ............................................................. 13
Function Latch Map................................................................... 14
Initialization Latch Map ............................................................ 15
Function Latch............................................................................ 16
Initialization Latch ..................................................................... 17
Applications..................................................................................... 18
Local Oscillator for LMDS Base Station Transmitter............ 18
Interfacing ................................................................................... 19
PCB Design Guidelines for Chip Scale Package .................... 19
Outline Dimensions....................................................................... 20
ESD Caution.................................................................................... 20
Ordering Guide............................................................................... 20
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 5
Pin Configurations and Functional Descriptions ........................ 6
Typical Performance Characteristics ............................................. 7
Functional Description.................................................................... 9
Reference Input Stage................................................................... 9
RF Input Stage............................................................................... 9
Prescaler (P/P + 1)........................................................................ 9
A and B Counters ......................................................................... 9
R Counter ...................................................................................... 9
Phase Frequency Detector and Charge Pump........................ 10
MUXOUT and Lock Detect...................................................... 10
Input Shift Register..................................................................... 10
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADF4107
ADF4107—SPECIFICATIONS
Table 1. (AVDD = DVDD = 3 V 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA =
TMAX to TMIN, unless otherwise noted.)
Parameter
B
B Chips2 Unit
(Typ)
Test Conditions/Comments
Version1
RF CHARACTERISTICS
RF Input Frequency (RFIN)3
RF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency4
1.0/7.0
–5/+5
300
1.0/7.0
–5/+5
300
GHz min/max
dBm min/max
MHz max
See Figure 18 for input circuit.
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity5
20/250
0.8/VDD
20/250
0.8/VDD
MHz min/max
V p-p min/max
For f < 20 MHz, use dc-coupled square wave (0 to VDD).
AC-coupled; when dc-coupled, 0 to VDD, max (CMOS
compatible).
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency6
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
10
100
10
100
pF max
µA max
104
104
MHz max
Programmable; see Figure 25.
With RSET = 5.1 kΩ
5
5
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
625
2.5
3.0/11
1
625
2.5
3.0/11
1
With RSET = 5.1 kΩ
See Figure 25.
ICP Three-State Leakage
Sink and Source Current
Matching
2
2
0.5 V ≤ VCP ≤ VP – 0.5 V
ICP vs. VCP
1.5
2
1.5
2
% typ
% typ
0.5 V ≤ VCP ≤ VP – 0.5 V
VCP = VP/2
ICP vs. Temperature
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOH, Output High Voltage
IOH
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD7 (AIDD + DIDD)
1.4
0.6
1
1.4
0.6
1
V min
V max
µA max
pF max
10
10
1.4
VDD – 0.4
100
1.4
V min
Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V.
CMOS output chosen.
VDD – 0.4 V min
100
0.4
µA max
V max
0.4
IOL = 500 µA
2.7/3.3
AVDD
AVDD/5.5
17
2.7/3.3
AVDD
AVDD/5.5 V min/V max
15
0.4
10
V min/V max
AVDD ≤ VP ≤5.5V
15 mA typ
TA = 25°C
mA max
mA max
µA typ
IP
0.4
Power-Down Mode8 (AIDD + DIDD) 10
Rev. 0 | Page 3 of 20
ADF4107
Parameter
B
B Chips2 Unit
(Typ)
Test Conditions/Comments
Version1
NOISE CHARACTERISTICS
ADF4107 Phase Noise Floor9
–174
–166
–159
–174
–166
–159
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 1 MHz PFD Frequency
Phase Noise Performance10
900 MHz Output11
6400 MHz Output12
6400 MHz Output13
Spurious Signals
@ VCO Output
–93
–76
–83
–93
–76
–83
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 1 kHz offset and 200 kHz PFD Frequency
@ 1 kHz offset and 200 kHz PFD Frequency
@ 1 kHz offset and 1 MHz PFD Frequency
900 MHz Output11
6400 MHz Output12
6400 MHz Output13
–90/–92
–65/–70
–70/–75
–90/–92
–65/–70
–70/–75
dBc typ
dBc typ
dBc typ
@ 200 kHz/400kHz and 200 kHz PFD Frequency
@ 200 kHz/400kHz and 200 kHz PFD Frequency
@ 1 MHz/2MHz and 1 MHz PFD Frequency
1 Operating temperature range (B Version) is –40°C to +85°C.
2 The B Chip specifications are given as typical values.
3 Use a square wave for lower frequencies, below the minimum stated.
4 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
5 AVDD = DVDD = 3 V.
6 Guaranteed by design. Sample tested to ensure compliance.
7 TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 7.0 GHz.
8 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz.
9 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
10 The phase noise is measured with the EVAL-ADF4107EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the
synthesizer (fREFOUT = 10 MHz @ 0 dBm).
11
f
f
f
= 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.
= 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 6400 MHz; N = 32000; Loop B/W = 20 kHz.
= 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; fRF = 6400 MHz; N = 6400; Loop B/W = 100 kHz.
REFIN
REFIN
REFIN
12
13
Rev. 0 | Page 4 of 20
ADF4107
TIMING CHARACTERISTICS
Table 2. (AVDD = DVDD = 3 V 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω,
TA = TMAX to TMIN, unless otherwise noted.)1
Parameter
Limit2 (B Version)
Unit
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
t1
t2
t3
t4
t5
t6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
CLOCK to LE Setup Time
LE Pulsewidth
1 Guaranteed by design but not production tested.
2 Operating temperature range (B Version) is –40°C to +85°C.
t3
t4
CLOCK
t1
t2
DB1 (CONTROL
BIT C2)
DB0 (LSB)
DB2
DB23 (MSB)
DB22
DATA
(CONTROL BIT C1)
t6
LE
LE
t5
Figure 2. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
Table 3. (TA = 25°C, unless otherwise noted.)
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AVDD to GND1
–0.3 V to +3.6 V
–0.3 V to +0.3 V
–0.3 V to +5.8 V
–0.3 V to +5.8 V
–0.3 V to VDD + 0.3 V
–0.3 V to VP + 0.3 V
–0.3 V to VDD + 0.3 V
AVDD to DVDD
VP to GND
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFINA, RFINB to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
CSP θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
–40°C to +85°C
–65°C to +125°C
150°C
150.4°C/W
122°C/W
215°C
220°C
Transistor Count
CMOS
Bipolar
6425
303
1GND = AGND = DGND = 0 V.
Rev. 0 | Page 5 of 20
ADF4107
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
CSP
TSSOP
(Chip Scale Package)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
R
P
SET
CP
DV
DD
MUXOUT
LE
CPGND
AGND
ADF4107
TOP VIEW
PIN 1
15 MUXOUT
14 LE
CPGND 1
AGND 2
AGND 3
INDICATOR
RF
B
DATA
CLK
IN
(Not to Scale)
13 DATA
12 CLK
11 CE
ADF4107
TOP VIEW
RF
A
IN
RF B 4
IN
RF A 5
IN
CE
AV
DD
DGND
REF
IN
Figure 3. ADF4107 TSSOP (Top View)
Figure 4. ADF4107 Chip Scale Package
Table 4. Pin Functional Descriptions
Mnemonic Function
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage
potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
25.5
RSET
RSET
ICP MAX
=
so, with RSET = 5.1 kΩ, ICP MAX = 5 mA.
CP
Charge Pump Output. When enabled, this pin provides ICP to the external loop filter, which in turn drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
CPGND
AGND
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor,
typically 100 pF. See Figure 18.
RFINB
RFINA
AVDD
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This voltage may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should
be placed as close as possible to this pin. AVDD must be the same value as DVDD.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. See
Figure 17. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
REFIN
DGND
CE
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking
the pin high will power up the device, depending on the status of the power-down bit, F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift
register on the CLK rising edge. This input is a high impedance CMOS input.
CLK
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance
CMOS input.
DATA
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the
latch being selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed
externally.
MUXOUT
DVDD
VP
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed
as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This voltage should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5
V and used to drive a VCO with a tuning range of up to 5 V.
Rev. 0 | Page 6 of 20
ADF4107
TYPICAL PERFORMANCE CHARACTERISTICS
–40
–50
10dB/DIV
R
= –40dBc/Hz
L
RMS NOISE = 0.36o
–60
–70
–80
–90
–100
–110
–120
–130
–140
100Hz
1MHz
FREQUENCY OFFSET FROM 900MHz CARRIER
Figure 5. Parameter Data for the RF Input
Figure 8. Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz)
0
0
REF LEVEL = –14.0dBm
V
V
= 3V
= 3V
DD
P
V
= 3V, V = 5V
P
DD
–10
–20
–30
–40
–50
–60
–70
–80
I
= 5mA
CP
–5
–10
–15
–20
–25
–30
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30
T
= +85oC
A
T
= +25oC
A
–91.0dBc/Hz
–90
T
= –40oC
3
A
–100
0
1
2
4
5
6
7
–400kHz
–200kHz
900MHz
+200kHz
+400kHz
RF INPUT FREQUENCY – GHz
FREQUENCY
Figure 6. Input Sensitivity
Figure 9. Reference Spurs (900 MHz, 200 kHz, 20 kHz)
0
0
–10
–20
–30
–40
–50
–60
–70
–80
REF LEVEL = –10dBm
REF LEVEL = –14.3dBm
V
= 3V, V = 5V
P
DD
V
= 3V, V = 5V
–10
–20
–30
–40
–50
–60
–70
–80
DD
P
I
= 5mA
CP
I
= 5mA
CP
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10
–93.0dBc/Hz
–83.0dBc/Hz
–90
–90
–100
–100
–2kHz
–1kHz
6400MHz
+1kHz
+2kHz
–2kHz
–1kHz
900MHz
+1kHz
+2kHz
FREQUENCY
FREQUENCY
Figure 10. Phase Noise (6.4 GHz, 1 MHz, 100 kHz)
Figure 7. Phase Noise (900 MHz, 200 kHz, 20 kHz)
Rev. 0 | Page 7 of 20
ADF4107
–40
–50
–5
–15
–25
–35
–45
–55
–65
–75
–85
10dB/DIV
V
V
= 3V
DD
P
R
= –40dBc/Hz
L
= 5V
RMS NOISE = 1.85o
–60
–70
–80
–90
–100
–110
–120
–130
–95
–105
–140
100Hz
1MHz
0
1
2
3
4
5
FREQUENCY OFFSET FROM 6400MHz CARRIER
TUNING VOLTAGE – V
Figure 11. Integrated Phase Noise (6.4 GHz, 1 MHz, 100 kHz)
Figure 14. Reference Spurs vs. VTUNE (6.4 GHz, 1 MHz, 100 kHz)
0
–120
V
V
= 3V
REF LEVEL = –10dBm
DD
P
V
= 3V, V = 5V
P
DD
–10
–20
–30
–40
–50
–60
–70
–80
= 5V
I
= 5mA
CP
–130
–140
–150
–160
–170
–180
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1
–65.0dBc/Hz
–66.0dBc/Hz
–90
–100
–2MHz
–1MHz
6400MHz
+1MHz
+2MHz
10k
100k
1M
10M
100M
FREQUENCY
PHASE DETECTOR FREQUENCY – Hz
Figure 12. Reference Spurs (6.4 GHz, 1 MHz, 100 kHz)
Figure 15. Phase Noise (referred to CP output) vs. PFD Frequency
–60
–70
6
5
V
V
= 3V
DD
P
= 3V
4
3
V
CP
= 5V
SETTLING = 5mA
P
I
2
1
0
–80
–1
–2
–3
–4
–90
–5
–6
–100
0
0.5
1.0
1.5
2.0
2.5
– V
3.0
3.5
4.0
4.5 5.0
–40
–20
0
20
40
60
80
100
TEMPERATURE – o
C
CP
V
Figure 16. Charge Pump Output Characteristics
Figure 13. Phase Noise (6.4 GHz, 1 MHz, 100 kHz) vs. Temperature
Rev. 0 | Page 8 of 20
ADF4107
FUNCTIONAL DESCRIPTION
Reference Input Stage
synchronous 4/5 core. A minimum divide ratio is possible for
fully contiguous output frequencies. This minimum is
determined by P, the prescaler value, and is given by: (P2 – P).
The Reference Input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
A and B Counters
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
POWER-DOWN
CONTROL
100kΩ
NC
SW2
Pulse Swallow Function
TO R COUNTER
REF
IN
NC
SW1
BUFFER
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is as follows:
SW3
NO
Figure 17. Reference Input Stage
fREFIN
R
fVCO
= (P ×B)+ A ×
[ ]
RF Input Stage
fVCO Output frequency of external voltage controlled
oscillator (VCO).
The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
P
B
A
Preset modulus of dual-modulus prescaler
(8/9, 16/17, etc.).
Preset divide ratio of binary 13-bit counter
(3 to 8191).
BIAS
1.6V
GENERATOR
AV
DD
Preset divide ratio of binary 6-bit swallow counter
(0 to 63).
500Ω
500Ω
fREFIN External reference frequency oscillator.
RF
RF
A
B
IN
N = BP + A
IN
TO PFD
13-BIT B
COUNTER
LOAD
LOAD
FROM RF
PRESCALER
P/P + 1
INPUT STAGE
AGND
6-BIT A
COUNTER
MODULUS
CONTROL
Figure 18. RF Input Stage
N DIVIDER
Prescaler (P/P + 1)
Figure 19. A and B Counters
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A and B
counters. The prescaler is programmable. It can be set in
software to 8/9, 16/17, 32/33, or 64/65. It is based on a
R Counter
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
Rev. 0 | Page 9 of 20
ADF4107
The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected, this output will be high with
narrow, low-going pulses.
Phase Frequency Detector and Charge
Pump
The phase frequency detector (PFD) takes inputs from the R
counter and N counter (N = BP + A) and produces an output
proportional to the phase and frequency difference between
them. Figure 20 is a simplified schematic. The PFD includes a
programmable delay element that controls the width of the
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the reference counter latch, ABP2
and ABP1, control the width of the pulse. See Figure 23.
DV
DD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUX
CONTROL
MUXOUT
V
P
CHARGE
PUMP
UP
DGND
Q1
U1
D1
HI
Figure 21. MUXOUT Circuit
R DIVIDER
CLR1
PROGRAMMABLE
DELAY
U3
CP
Input Shift Register
ABP2
ABP1
The ADF4107 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs, DB1 and DB0, as
shown in the timing diagram of Figure 2. The truth table for
these bits is shown in Table 5. Figure 22 shows a summary of
how the latches are programmed.
CLR2
DOWN
HI
D2 Q2
U2
N DIVIDER
CPGND
Figure 20. PFD Simplified Schematic and Timing (in Lock)
MUXOUT and Lock Detect
The output multiplexer on the ADF4107 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Figure 25 shows the full truth table. Figure 21 shows the
MUXOUT section in block diagram form.
Table 5. C2, C1 Truth Table
Control Bits
Data Latch
C2
0
C1
0
R Counter
0
1
1
1
0
1
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When the lock detect precision
(LDP) bit in the R counter latch is set to 0, digital lock detect is
set high when the phase error on three consecutive phase
detector (PD) cycles is less than 15 ns. With LDP set to 1, five
consecutive cycles of less than 15 ns are required to set the lock
detect. It will stay set high until a phase error of greater than
25 ns is detected on any subsequent PD cycle.
Rev. 0 | Page 10 of 20
ADF4107
Latch Summary
REFERENCE COUNTER LATCH
ANTI-
BACKLASH
WIDTH
TEST
CONTROL
BITS
14-BIT REFERENCE COUNTER
RESERVED
MODE BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
R6
DB1
DB0
X
0
0
LDP
T2
T1 ABP2 ABP1 R14
R13 R12
R11
R10
R9
R8
R7
R5
R4
R3
R2
R1
C2 (0) C1 (0)
N COUNTER LATCH
CONTROL
BITS
RESERVED
13-BIT B COUNTER
6-BIT A COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
X
G1
B13 B12
B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A6
A5
A4
A3
A2
A1 C2(0)
C1 (1)
FUNCTION LATCH
CURRENT
CURRENT
SETTING
1
CONTROL
BITS
TIMER COUNTER
CONTROL
PRESCALER
VALUE
MUXOUT
SETTING
2
CONTROL
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1
DB0
P2
P1
PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2
TC1
F5
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1) C1 (0)
INITIALIZATION LATCH
CURRENT
SETTING
2
CURRENT
SETTING
1
CONTROL
BITS
MUXOUT
PRESCALER
VALUE
TIMER COUNTER
CONTROL
CONTROL
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
CPI5
F2
DB1
DB0
P2
P1
PD2 CPI6
CPI4 CPI3 CPI2 CPI1 TC4 TC3
TC2
TC1
F5
F4
F3
M3
M2
M1
PD1
F1
C2 (1) C1(1)
Figure 22. Latch Summary
Rev. 0 | Page 11 of 20
ADF4107
Reference Counter Latch Map
ANTI-
TEST
CONTROL
BITS
14-BIT REFERENCE COUNTER
BACKLASH
RESERVED
MODE BITS
WIDTH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB1
DB0
0
0
LDP
T2
T1 ABP2 ABP1 R14
R13
R12 R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1 C2 (0) C1 (0)
X
X = DON’T CARE
R14
R13
R12
..........
R3
R2
R1
DIVIDE RATIO
0
0
0
0
0
0
0
0
0
..........
..........
..........
0
0
0
0
1
1
1
0
1
1
2
3
0
0
0
..........
1
0
0
4
.
.
.
.
.
.
.
.
.
..........
..........
..........
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
..........
..........
..........
..........
1
1
1
1
0
0
1
1
0
1
0
1
16380
16381
16382
16383
ABP2
0
ABP1
0
ANTIBACKLASH PULSEWIDTH
2.9ns
0
1
1
0
1.3ns
6.0ns
1
1
2.9ns
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION.
LDP
0
OPERATION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION.
Figure 23. Reference Counter Latch Map
Rev. 0 | Page 12 of 20
ADF4107
AB Counter Latch Map
CONTROL
BITS
RESERVED
6-BIT A COUNTER
13-BIT B COUNTER
DB21
G1
DB19
B12
DB16 DB15 DB14
DB10 DB9
B3 B2
DB6
A5
DB5
A4
DB4
A3
DB3
A2
DB0
C2 (0) C1 (1)
DB23 DB22
DB20
B13
DB18 DB17
B11 B10
DB13 DB12 DB11
B6 B5 B4
DB8
B1
DB7
A6
DB2
A1
DB1
X
X
B9
B8
B7
X = DON’T CARE
A COUNTER
A6
A5
..........
A2
A1
DIVIDE RATIO
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
..........
..........
.
.
.
1
1
0
0
60
1
1
1
1
1
1
..........
..........
..........
0
1
1
1
0
1
61
62
63
B13
B12
B11
B3
B2
B1
B COUNTER DIVIDE RATIO
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
0
0
0
0
0
0
0
0
0
0
0
0
..........
..........
..........
..........
0
0
0
0
0
0
1
1
0
1
0
1
3
.
.
.
.
.
.
.
..........
..........
.
.
.
.
.
.
.
.
.
.
.
..........
..........
..........
..........
..........
.
.
.
8188
8189
8190
8191
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
CP GAIN OPERATION
0
0
1
1
0
1
0
1
CHARGE PUMP CURRENT
SETTING 1 IS PERMANENTLY USED.
CHARGE PUMP CURRENT
SETTING 2 IS PERMANENTLY USED.
CHARGE PUMP CURRENT
SETTING 1 IS USED.
CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION
LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR
CONTINUOUSLY ADJACENT VALUES OF (N
2
×
F
), AT THE
REF
OUTPUT, N
IS (P – P).
MIN
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.
Figure 24. AB Counter Latch Map
Rev. 0 | Page 13 of 20
ADF4107
Function Latch Map
CURRENT
CURRENT
SETTING
1
CONTROL
BITS
PRESCALER
TIMER COUNTER
CONTROL
MUXOUT
SETTING
2
VALUE
CONTROL
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5
DB4 DB3 DB2 DB1
DB0
P2
P1
PD2
CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2
TC1
F4
F3
F2
M3
M2
M1
F1
C2 (1) C1(0)
CPI6
F5
PD1
PHASE DETECTOR
POLARITY
COUNTER
F2
F1
OPERATION
0
1
NEGATIVE
0
1
NORMAL
POSITIVE
R, A, B COUNTERS
HELD IN RESET
CHARGE PUMP
F3 OUTPUT
NORMAL
0
THREE-STATE
1
F4
F5
FASTLOCK MODE
0
1
1
X
0
1
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
M3
M2
M1
OUTPUT
TIMEOUT
TC4
TC3
TC2
TC1
(PFD CYCLES)
0
0
0
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
0
0
1
0
0
0
0
3
0
0
0
1
7
0
0
1
1
1
1
0
0
0
1
0
1
N DIVIDER OUTPUT
0
0
1
0
11
DV
DD
0
0
0
1
1
0
1
0
15
19
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
0
0
1
1
0
1
1
0
23
27
LOCK DETECT
SERIAL DATA OUTPUT
DGND
1
1
1
1
0
1
0
1
1
0
1
0
1
0
31
35
1
0
0
1
39
1
1
0
0
1
1
0
1
43
47
1
1
1
1
0
0
0
1
51
55
1
1
1
1
1
1
0
1
59
63
CPI6
CPI5
CP14
I
(mA)
CP
CPI3
CPI2
CPI1
3kΩ
1.06
2.12
3.18
5.1kΩ
0.625
1.25
11kΩ
0
0
0
0
0
1
0
1
0
0.289
0.580
0.870
1.875
0
1
1
0
1
0
4.24
5.30
2.5
1.160
1.450
3.125
1
0
1
6.36
7.42
8.50
3.75
1.730
1
1
1
1
0
1
4.375
5.0
2.020
2.320
CE PIN
PD2
PD1
MODE
X
X
0
1
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
0
1
1
1
X
0
1
1
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
PRESCALER VALUE
P2
P1
0
0
1
1
0
1
0
1
8/9
16/17
32/33
64/65
Figure 25. Function Latch Map
Rev. 0 | Page 14 of 20
ADF4107
Initialization Latch Map
CURRENT
CURRENT
SETTING
1
CONTROL
BITS
PRESCALER
TIMER COUNTER
CONTROL
MUXOUT
SETTING
2
VALUE
CONTROL
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5
DB4 DB3 DB2 DB1
DB0
P2
P1
PD2
CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2
TC1
F4
F3
F2
M3
M2
M1
F1
C2 (1) C1(1)
CPI6
F5
PD1
PHASE DETECTOR
POLARITY
COUNTER
F2
F1
OPERATION
0
1
NEGATIVE
0
1
NORMAL
POSITIVE
R, A, B COUNTERS
HELD IN RESET
CHARGE PUMP
F3 OUTPUT
NORMAL
0
THREE-STATE
1
F4
F5
FASTLOCK MODE
0
1
1
X
0
1
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
M3
M2
M1
OUTPUT
TIMEOUT
TC4
TC3
TC2
TC1
(PFD CYCLES)
0
0
0
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
0
0
1
0
0
0
0
3
0
0
0
1
7
0
0
1
1
1
1
0
0
0
1
0
1
N DIVIDER OUTPUT
0
0
1
0
11
DV
DD
0
0
0
1
1
0
1
0
15
19
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
0
0
1
1
0
1
1
0
23
27
LOCK DETECT
SERIAL DATA OUTPUT
DGND
1
1
1
1
0
1
0
1
1
0
1
0
1
0
31
35
1
0
0
1
39
1
1
0
0
1
1
0
1
43
47
1
1
1
1
0
0
0
1
51
55
1
1
1
1
1
1
0
1
59
63
CPI6
CPI5
CP14
I
(mA)
CP
CPI3
CPI2
CPI1
3kΩ
1.06
2.12
3.18
5.1kΩ
0.625
1.25
11kΩ
0
0
0
0
0
1
0
1
0
0.289
0.580
0.870
1.875
0
1
1
0
1
0
4.24
5.30
2.5
1.160
1.450
3.125
1
0
1
6.36
7.42
8.50
3.75
1.730
1
1
1
1
0
1
4.375
5.0
2.020
2.320
CE PIN
PD2
PD1
MODE
X
X
0
1
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
0
1
1
1
X
0
1
1
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
PRESCALER VALUE
P2
P1
0
0
1
1
0
1
0
1
8/9
16/17
32/33
64/65
Figure 26. Initialization Latch Map
Rev. 0 | Page 15 of 20
ADF4107
Fastlock Mode Bit
Function Latch
DB10 of the function latch is the fastlock mode bit. When
fastlock is enabled, this bit determines which fastlock mode is
used. If the fastlock mode bit is 0, then Fastlock Mode 1 is
selected; and if the fastlock mode bit is 1, then Fastlock Mode 2
is selected.
The on-chip function latch is programmed with C2 and C1 set
to 1 and 0, respectively. Figure 25 shows the input data format
for programming the function latch.
Counter Reset
Fastlock Mode 1
DB2 (F1) is the counter reset bit. When this bit is 1, the R
counter and the AB counters are reset. For normal operation,
this bit should be 0. Upon powering up, the F1 bit needs to be
disabled (set to 0). Then, the N counter resumes counting in
close alignment with the R counter. (The maximum error is one
prescaler cycle).
The charge pump current is switched to the contents of Current
Setting 2.
The device enters fastlock by having a 1 written to the CP gain
bit in the AB counter latch. The device exits fastlock by having
a 0 written to the CP gain bit in the AB counter latch.
Fastlock Mode 2
Power-Down
DB3 (PD1) and DB21 (PD2) provide programmable power-
down modes. They are enabled by the CE pin.
The charge pump current is switched to the contents of Current
Setting 2.
The device enters fastlock by having a 1 written to the CP gain
bit in the AB counter latch. The device exits fastlock under the
control of the timer counter. After the timeout period
determined by the value in TC4–TC1, the CP gain bit in the AB
counter latch is automatically reset to 0 and the device reverts to
normal mode instead of fastlock. See Figure 25 for the timeout
periods.
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2 and PD1.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into the PD1 bit,
with the condition that PD2 has been loaded with a 0.
In the programmed synchronous power-down, the device
power-down is gated by the charge pump to prevent unwanted
frequency jumps. Once the power-down is enabled by writing
a 1 into PD1 (on condition that a 1 has also been loaded to
PD2), then the device will go into power-down on the
occurrence of the next charge pump event.
Timer Counter Control
The user has the option of programming two charge pump
currents. The intent is that Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is meant to be used when the system is dynamic and in
a state of change (i.e., when a new output frequency is
programmed).
When a power-down is activated (either synchronous or
asynchronous mode, including CE pin activated power-down),
the following events occur:
•
•
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RFIN input is debiased.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading and
latching data.
The normal sequence of events is as follows:
The user initially decides what the preferred charge pump
currents are going to be. For example, the choice may be 2.5 mA
as Current Setting 1 and 5 mA as Current Setting 2.
•
•
•
•
•
At the same time it must be decided how long the secondary
current is to stay active before reverting to the primary current.
This is controlled by the timer counter control bits, DB14–DB11
(TC4–TC1) in the function latch. The truth table is given in
Figure 25.
MUXOUT Control
Now, to program a new output frequency, the user simply
programs the AB counter latch with new values for A and B. At
the same time, the CP gain bit can be set to 1, which sets the
charge pump with the value in CPI6–CPI4 for a period of time
determined by TC4–TC1. When this time is up, the charge
pump current reverts to the value set by CPI3–CPI1. At the
same time the CP gain bit in the AB counter latch is reset to 0
and is now ready for the next time that the user wishes to
change the frequency.
The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4107. Figure 25 shows the truth table.
Fastlock Enable Bit
DB9 of the function latch is the fastlock enable bit. Fastlock is
enabled only when this bit is 1.
Rev. 0 | Page 16 of 20
ADF4107
Initialization Latch Method
Apply VDD
Program the initialization latch (11 in two LSBs of input word).
Make sure that the F1 bit is programmed to 0.
Note that there is an enable feature on the timer counter. It is
enabled when Fastlock Mode 2 is chosen by setting the fastlock
mode bit (DB10) in the function latch to 1.
.
Charge Pump Currents
Next, do a function latch load (10 in two LSBs of the control
word), making sure that the F1 bit is programmed to a 0.
Then do an R load (00 in two LSBs).
CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Figure 25.
Then do an AB load (01 in two LSBs).
When the Initialization Latch is loaded, the following occurs:
Prescaler Value
1. The function latch contents are loaded.
P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 300 MHz. Thus, with
an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but
a value of 8/9 is not valid.
2. An internal pulse resets the R, AB, and timeout counters to
load-state conditions and also three-states the charge
pump. Note that the prescaler band gap reference and the
oscillator input buffer are unaffected by the internal reset
pulse, allowing close phase alignment when counting
resumes.
3. Latching the first AB counter data after the initialization
word will activate the same internal reset pulse. Successive
AB loads will not trigger the internal reset pulse unless
there is another initialization.
PD Polarity
This bit sets the phase detector polarity bit. See Figure 25.
CP Three-State
CE Pin Method
This bit controls the CP output pin. With the bit set high, the CP
output is put into three-state. With the bit set low, the CP output
is enabled.
Apply VDD
.
Bring CE low to put the device into power-down. This is an
asychronous power-down in that it happens immediately.
Program the function latch (10).
Program the R counter latch (00).
Program the AB counter latch (01).
Initialization Latch
The initialization latch is programmed when C2 and C1 are set
to 1 and 1. This is essentially the same as the function latch
(programmed when C2, C1 = 1, 0).
Bring CE high to take the device out of power-down. The R and
AB counters will now resume counting in close alignment.
Note that after CE goes high, a duration of 1 µs may be required
for the prescaler band gap voltage and oscillator input buffer
bias to reach steady state.
However, when the initialization latch is programmed an
additional internal reset pulse is applied to the R and AB
counters. This pulse ensures that the AB counter is at load point
when the AB counter data is latched and the device will begin
counting in close phase alignment.
CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after VDD was
initially applied.
If the latch is programmed for synchronous power-down (CE
pin is high; PD1 bit is high; PD2 bit is low), the internal pulse
also triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse
and so close phase alignment is maintained when counting
resumes.
Counter Reset Method
Apply VDD
.
When the first AB counter data is latched after initialization, the
internal reset pulse is again activated. However, successive AB
counter loads after this will not trigger the internal reset pulse.
Do a Function Latch Load (10 in two LSBs). As part of this,
load 1 to the F1 bit. This enables the counter reset.
Do an R counter load (00 in two LSBs).
Do an AB counter load (01 in two LSBs).
Do a Function latch load (10 in two LSBs). As part of this,
load 0 to the F1 bit. This disables the counter reset.
Device Programming after Initial Power-Up
After initially powering up the device, there are three ways to
program the device.
This sequence provides the same close alignment as the
initialization method. It offers direct control over the internal
reset. Note that counter reset holds the counters at load point
and three-states the charge pump, but does not trigger
synchronous power-down.
Rev. 0 | Page 17 of 20
ADF4107
APPLICATIONS
Local Oscillator for LMDS Base Station
Transmitter
Figure 27 below shows the ADF4107 being used with a VCO to
produce the LO for an LMDS base station.
Other PLL system specifications are:
KD = 5.0 mA
KV = 80 MHz/V
Loop Bandwidth = 70 kHz
FPFD = 1 MHz
N = 6300
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 Ω. A typical base station
system would have either a TCXO or an OCXO driving the
reference input without any 50 Ω termination.
Extra Reference Spur Attenuation = 10 dB
All of these specifications are needed and used to derive the
loop filter component values shown in Figure 27.
To have a channel spacing of 1 MHz at the output, the 10 MHz
reference input must be divided by 10, using the on-chip
reference divider of the ADF4107.
Figure 27 gives a typical phase noise performance of
−83 dBc/Hz at 1 kHz offset from the carrier. Spurs are better
than −70 dBc.
The charge pump output of the ADF4107 (Pin 2) drives the
loop filter. In calculating the loop filter component values, a
number of items need to be considered. In this example, the
loop filter was designed so that the overall phase margin for the
system would be 45°.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives the
RF output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output, and the RFIN
terminal of the synthesizer.
In a PLL system, it is important to know when the system is in
lock. In Figure 27, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be
programmed to monitor various internal signals in the
synthesizer. One of these is the LD or lock detect signal.
V
V
P
DD
DD
RF
OUT
100pF
18Ω
18Ω
16
V
P
CP
7
AV
15
100pF
14
18Ω
DV
1.7kΩ
DD
10
V
CC
1000pF
51Ω
1000pF
2
2
FREF
8
IN
REFIN
47pF
100pF
7.5kΩ
V956ME01
ADF4107
1, 3, 4, 5, 7, 8,
9, 11, 12, 13
820pF
CE
LOCK
DETECT
MUXOUT
14
CLK
DATA
LE
100pF
6
5
RF
RF
A
B
IN
R
1
SET
51Ω
IN
5.1kΩ
100pF
3
4
9
NOTE
DECOUPLING CAPACITORS (0.1
OF THE ADF4107 AND ON V OF THE V956ME01 HAVE
µ
CC
F/10pF) ON AV , DV
,
DD
DD
V
P
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 27. 6.3 GHz Local Oscillator Using the ADF4107
Rev. 0 | Page 18 of 20
ADF4107
ADSP2181 Interface
Interfacing
Figure 29 shows the interface between the ADF4107 and the
ADSP21xx Digital Signal Processor. The ADF4107 needs a
24-bit serial word for each latch write. The easiest way to
accomplish this using the ADSP21xx family is to use the
autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 24-bit
word. To program each 24-bit latch, store the three 8-bit bytes,
enable the autobuffered mode, and then write to the transmit
register of the DSP. This last operation initiates the autobuffer
transfer.
The ADF4107 has a simple SPI™ compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When LE (Latch Enable) goes high, the 24 bits that
have been clocked into the input register on each rising edge of
CLK will get transferred to the appropriate latch. See Figure 2
for the timing diagram and Table 5 for the Latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
833 kHz or one update every 1.2 µs. This is certainly more than
adequate for systems that have typical lock times in hundreds of
microseconds.
ADuC812 Interface
SCLK
DT
CLK
Figure 28 shows the interface between the ADF4107 and the
ADuC812 MicroConverter®. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051 based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4107 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte has
been written, the LE input should be brought high to complete
the transfer.
DATA
TFS
LE
CE
ADSP21XX
ADF4107
I/O FLAGS
MUXOUT
(LOCK DETECT)
Figure 29. ADSP-21xx to ADF4107 Interface
PCB Design Guidelines for Chip Scale
Package
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the pad.
This will ensure that the solder joint size is maximized. The
bottom of the chip scale package has a central thermal pad.
On first applying power to the ADF4107, it needs four writes
(one each to the initialization latch, function latch, R counter
latch, and N counter latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When operating in the mode described, the maximum
SCLOCK rate of the ADuC812 is 4 MHz. This means that the
maximum rate at which the output frequency can be changed
will be 166 kHz.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This will ensure that
shorting is avoided.
SCLOCK
MOSI
CLK
DATA
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm and the via barrel should be plated with 1 oz. copper
to plug the via.
LE
CE
ADuC812
ADF4107
I/O PORTS
MUXOUT
(LOCK DETECT)
The user should connect the printed circuit board thermal pad
to AGND.
Figure 28. ADuC812 to ADF4107 Interface
Rev. 0 | Page 19 of 20
ADF4107
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
1
9
8
4.50
4.40
4.30
6.40
BSC
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)—Dimensions shown in millimeters
0.60
4.0
MAX
BSC SQ
0.60
MAX
16
15
20
1
PIN 1
2.25
INDICATOR
TOP
3.75
BOTTOM
VIEW
2.10 SQ
1.95
VIEW
BSC SQ
11
10
5
0.75
0.55
0.35
6
1.00 MAX
0.65 NOM
0.30
0.23
0.18
12° MAX
1.00
0.90
0.80
0.05
0.02
0.00
COPLANARITY
0.08
SEATING
0.50
BSC
0.20
REF
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 31. 20-Lead Frame Chip Scale Package [LFCSP] (CP-20)—Dimensions shown in millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ORDERING GUIDE
Model
Temperature Range
–40°C to + 85°C
–40°C to + 85°C
–40°C to + 85°C
–40°C to + 85°C
–40°C to + 85°C
–40°C to + 85°C
Package Option
RU-16
RU-16
RU-16
CP-20
ADF4107BRU
ADF4107BRU–REEL
ADF4107BRU–REEL7
ADF4107BCP
ADF4107BCP–REEL
ADF4107BCP–REEL7
CP-20
CP-20
RU = Thin Shrink Small Outline Package (TSSOP)
CP = Chip Scale Package
Contact the factory for chip availability.
Note that aluminum bond wire should not be used with the ADF4107 die.
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
C03338-0-5/03(0)
Rev. 0 | Page 20 of 20
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