ADF4110BCPZ_技术文档

RF PLL Frequency Synthesizers

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

FEATURES

GENERAL DESCRIPTION

ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz;

ADF4113: 4.0 GHz

2.7 V to 5.5 V power supply

Separate charge pump supply (V_P) allows extended tuning

voltage in 3 V systems

Programmable dual-modulus prescaler 8/9, 16/17, 32/33,

64/65

Programmable charge pump currents

Programmable antibacklash pulse width

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

The ADF4110 family of frequency synthesizers can be used to

implement local oscillators in the upconversion and downcon-

version sections of wireless receivers and transmitters. They

consist of a low noise digital PFD (phase frequency detector), a

precision charge pump, a programmable reference divider,

programmable A and B counters, and a dual-modulus prescaler

(P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction

with the dual-modulus prescaler (P/P + 1), implement an N

divider (N = BP + A). In addition, the 14-bit reference counter

(R counter) allows selectable REFIN frequencies at the PFD

input. A complete phase-locked loop (PLL) can be implemented

if the synthesizer is used with an external loop filter and voltage

controlled oscillator (VCO).

APPLICATIONS

Base stations for wireless radio (GSM, PCS, DCS, CDMA,

WCDMA)

Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANS

Communications test equipment

CATV equipment

Control of all the on-chip registers is via a simple 3-wire

interface. The devices operate with a power supply ranging

from 2.7 V to 5.5 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

R

AV

DV

V

P

CPGND

SET

DD

REFERENCE

14-BIT

R COUNTER

REF

IN

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

CP

14

R COUNTER

LATCH

CLK

DATA

LE

24-BIT

INPUT REGISTER

FUNCTION

LATCH

LOCK

DETECT

CURRENT

SETTING 1

CURRENT

SETTING 2

22

A, B COUNTER

LATCH

SD

OUT

CPI3 CPI2 CPI1 CPI6 CPI5 CPI4

19

FROM

FUNCTION

LATCH

HIGH Z

AV

DD

13

MUX

MUXOUT

N = BP + A

13-BIT

B COUNTER

SD

OUT

RF

A

B

LOAD

IN

PRESCALER

P/P +1

LOAD

IN

6-BIT

A COUNTER

M3 M2 M1

ADF4110/ADF4111

ADF4112/ADF4113

6

CE

AGND

DGND

Figure 1. Functional Block Diagram

Rev. F

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Tel: 781.329.4700

Technical Support

www.analog.com

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Phase Frequency Detector (PFD) and Charge Pump............ 13

Muxout and Lock Detect........................................................... 13

Input Shift Register .................................................................... 13

Function Latch............................................................................ 19

Initialization Latch ..................................................................... 20

Device Programming after Initial Power-Up ......................... 20

Resynchronizing the Prescaler Output.................................... 21

Applications..................................................................................... 22

Local Oscillator for GSM Base Station Transmitter .............. 22

Using a D/A Converter to Drive the R_SETPin......................... 23

Shutdown Circuit ....................................................................... 23

Wideband PLL............................................................................ 23

Direct Conversion Modulator .................................................. 25

Interfacing ................................................................................... 26

PCB Design Guidelines for Chip Scale Package .................... 26

Outline Dimensions....................................................................... 27

Ordering Guide............................................................................... 28

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

Transistor Count........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 12

Reference Input Section............................................................. 12

RF Input Stage............................................................................. 12

Prescaler (P/P + 1)...................................................................... 12

A and B Counters ....................................................................... 12

R Counter .................................................................................... 12

REVISION HISTORY

1/13—Rev. E to Rev. F

3/03—Data sheet changed from Rev. A to Rev. B.

Changes to Table 1.............................................................................4

Changes to Ordering Guide ...........................................................28

Edits to Specifications.......................................................................2

Updated OUTLINE DIMENSIONS .............................................24

8/12—Rev. D to Rev. E

1/01—Data sheet changed from Rev. 0 to Rev. A.

Changed CP-20-1 to CP-20-6 ...........................................Universal

Updated Outline Dimensions........................................................28

Changes to Ordering Guide ...........................................................28

Changes to DC Specifications in B Version, B Chips,

Unit, and Test Conditions/Comments Columns .....................2

Changes to Absolute Maximum Rating .........................................4

Changes to FR_INA Function Test .....................................................5

Changes to Figure 8...........................................................................7

New Graph Added—TPC 22 ...........................................................9

Change to PD Polarity Box in Table V .........................................15

Change to PD Polarity Box in Table VI........................................16

Change to PD Polarity Paragraph .................................................17

Addition of New Material

5/12—Rev. C to Rev. D

Changes to Figure 2...........................................................................5

Changes to Figure 4 and Table 4......................................................7

Updated Outline Dimensions........................................................28

Changes to Ordering Guide ...........................................................28

3/04—Data sheet changed from Rev. B to Rev. C.

(PCB Design Guidelines for Chip–Scale package) ................23

Replacement of CP-20 Outline with CP-20 [2] Outline ............24

Updated Format..................................................................Universal

Changes to Specifications .................................................................2

Changes to Figure 32.......................................................................22

Changes to the Ordering Guide.....................................................28

Rev. F | Page 2 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

SPECIFICATIONS

AV_DD= DV_DD= 3 V 10%, 5 V 10%; AV_DD≤V_P≤ 6.0 V; AGND = DGND = CPGND = 0 V; R_SET= 4.7 kΩ; dBm referred to 50 Ω;

T_A= T_MINto T_MAX, unless otherwise noted. Operating temperature range is as follows: B Version: −40°C to +85°C.

Table 1.

Parameter

B Version

−15/0

B Chips¹

−15/0

Unit

Test Conditions/Comments

RF CHARACTERISTICS (3 V)

RF Input Sensitivity

RF Input Frequency

ADF4110

See Figure 29 for input circuit.

dBm min/max

MHz min/max

80/550

For lower frequencies, ensure slew rate

(SR) > 30 V/µs.

ADF4110

ADF4111

ADF4112

ADF4113

50/550

0.08/1.2

0.2/3.0

0.1/3.0

0.2/3.7

50/550

0.08/1.2

0.2/3.0

0.1/3.0

0.2/3.7

MHz min/max

GHz min/max

Input level = −10 dBm.

For lower frequencies, ensure SR > 30 V/µs.

For lower frequencies, ensure SR > 75 V/µs.

Input level = −10 dBm.

Input level = −10 dBm. For lower frequencies,

ensure SR > 130 V/µs.

Maximum Allowable Prescaler Output

Frequency²

165

MHz max

RF CHARACTERISTICS (5 V)

RF Input Sensitivity

RF Input Frequency

ADF4110

−10/0

dBm min/max

80/550

0.08/1.4

0.1/3.0

0.2/3.7

0.2/4.0

80/550

0.08/1.4

0.1/3.0

0.2/3.7

0.2/4.0

MHz min/max

GHz min/max

For lower frequencies, ensure SR > 50 V/µs.

For lower frequencies, ensure SR > 75 V/µs.

For lower frequencies, ensure SR > 130 V/µs.

Input level = −5 dBm.

ADF4111

ADF4112

ADF4113

Maximum Allowable Prescaler Output

Frequency²

200

MHz max

REFIN CHARACTERISTICS

REFIN Input Frequency

Reference Input Sensitivity

5/104

0.4/AV_DD

3.0/AV_DD

10

5/104

0.4/AV_DD

3.0/AV_DD

10

MHz min/max

For f < 5 MHz, ensure SR > 100 V/µs.

V p-p min/max AV_DD= 3.3 V, biased at AV_DD/2. See Note 3.

V p-p min/max

pF max

AV_DD= 5 V, biased at AV_DD/2. See Note ³.

REFIN Input Capacitance

REFIN Input Current

PHASE DETECTOR FREQUENCY⁴

CHARGE PUMP

100

µA max

55

MHz max

I_CPSink/Source

Programmable (see Table 9).

With R_SET= 4.7 kΩ.

High Value

Low Value

Absolute Accuracy

R_SETRange

5

mA typ

µA typ

% typ

kΩ typ

nA typ

% typ

625

2.5

2.7/10

1

2

1.5

2

625

2.5

2.7/10

1

2

1.5

2

With R_SET= 4.7 kΩ.

See Table 9.

I_CP3-State Leakage Current

Sink and Source Current Matching

I_CPvs. V_CP

I_CPvs. Temperature

LOGIC INPUTS

0.5 V ≤ V_CP≤ V_P– 0.5 V.

V_CP= V_P/2.

V_INH, Input High Voltage

V_INL, Input Low Voltage

I_INH/I_INL, Input Current

C_IN, Input Capacitance

LOGIC OUTPUTS

0.8 × DV_DD

0.2 × DV_DD

1

10

0.8 × DV_DD

0.2 × DV_DD

1

10

V min

V max

µA max

pF max

V_OH, Output High Voltage

V_OL, Output Low Voltage

DV_DD– 0.4

0.4

DV_DD– 0.4

0.4

V min

V max

I_OH= 500 µA.

I_OL= 500 µA.

Rev. F | Page 3 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

Parameter

B Version

B Chips¹

Unit

Test Conditions/Comments

POWER SUPPLIES

AV_DD

DV_DD

V_P

2.7/5.5

AV_DD

AV_DD/6.0

2.7/5.5

AV_DD

AV_DD/6.0

V min/V max

AV_DD≤ V_P≤ 6.0 V. See Figure 25 and Figure 26.

I_DD⁵(AI_DD+ DI_DD)

ADF4110

ADF4111

ADF4112

ADF4113

5.5

7.5

11

0.5

1

4.5

6.5

8.5

0.5

1

mA max

µA typ

4.5 mA typical.

6.5 mA typical.

8.5 mA typical.

T_A= 25°C.

I_P

Low Power Sleep Mode

NOISE CHARACTERISTICS

ADF4113 Normalized Phase Noise Floor⁶−215

Phase Noise Performance⁷

−215

dBc/Hz typ

@ VCO output.

ADF4110: 540 MHz Output⁸

ADF4111: 900 MHz Output⁹

ADF4112: 900 MHz Output⁹

ADF4113: 900 MHz Output⁹

ADF4111: 836 MHz Output¹⁰

ADF4112: 1750 MHz Output¹¹

ADF4112: 1750 MHz Output¹²

ADF4112: 1960 MHz Output¹³

ADF4113: 1960 MHz Output¹³

ADF4113: 3100 MHz Output¹⁴

Spurious Signals

−91

−87

−90

−91

−78

−86

−66

−84

−85

−86

−91

−87

−90

−91

−78

−86

−66

−84

−85

−86

dBc/Hz typ

@ 1 kHz offset and 200 kHz PFD frequency.

@ 300 Hz offset and 30 kHz PFD frequency.

@ 1 kHz offset and 200 kHz PFD frequency.

@ 200 Hz offset and 10 kHz PFD frequency.

@ 1 kHz offset and 200 kHz PFD frequency.

@ 1 kHz offset and 1 MHz PFD frequency.

ADF4110: 540 MHz Output⁹

ADF4111: 900 MHz Output⁹

ADF4112: 900 MHz Output⁹

ADF4113: 900 MHz Output⁹

ADF4111: 836 MHz Output¹⁰

ADF4112: 1750 MHz Output¹¹

ADF4112: 1750 MHz Output¹²

ADF4112: 1960 MHz Output¹³

ADF4113: 1960 MHz Output¹³

ADF4113: 3100 MHz Output¹⁴

−97/−106

−98/−110

−91/−100

−97/−106

−98/−110

−91/−100

dBc typ

@ 200 kHz/400 kHz and 200 kHz PFD frequency.

@ 30 kHz/60 kHz and 30 kHz PFD frequency.

@ 200 kHz/400 kHz and 200 kHz PFD frequency.

@ 10 kHz/20 kHz and 10 kHz PFD frequency.

@ 200 kHz/400 kHz and 200 kHz PFD frequency.

@ 1 MHz/2 MHz and 1 MHz PFD frequency.

−100/−110 −100/−110 dBc typ

−81/−84

−88/−90

−65/−73

−80/−84

−80/−82

−81/−84

−88/−90

−65/−73

−80/−84

−82/−82

dBc typ

¹The B chip specifications are given as typical values.

²This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

³AC coupling ensures AV_DD/2 bias. See Figure 33 for a typical circuit.

⁴Guaranteed by design.

⁵T_A= 25°C; AV_DD= DV_DD= 3 V; P = 16; SYNC = 0; DLY = 0; RF_INfor ADF4110 = 540 MHz; RF_INfor ADF4111, ADF4112, ADF4113 = 900 MHz.

⁶The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN_TOT, and subtracting 20logN (where N is the N divider

value) and 10logF_PFD: PN_SYNTH= PN_TOT– 10logF_PFD– 20logN.

⁷The phase noise is measured with the EV-ADF411XSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the

synthesizer (f_REFOUT= 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (Table 7).

⁸f_REFIN= 10 MHz; f_PFD= 200 kHz; offset frequency = 1 kHz; f_RF= 540 MHz; N = 2700; loop B/W = 20 kHz.

⁹f_REFIN= 10 MHz; f_PFD= 200 kHz; offset frequency = 1 kHz; f_RF= 900 MHz; N = 4500; loop B/W = 20 kHz.

10

f

= 10 MHz; f_PFD= 30 kHz; offset frequency = 300 Hz; f_RF= 836 MHz; N = 27867; loop B/W = 3 kHz.

= 10 MHz; f_PFD= 200 kHz; offset frequency = 1 kHz; f_RF= 1750 MHz; N = 8750; loop B/W = 20 kHz

= 10 MHz; f_PFD= 10 kHz; offset frequency = 200 Hz; f_RF= 1750 MHz; N = 175000; loop B/W = 1 kHz.

= 10 MHz; f_PFD= 200 kHz; offset frequency = 1 kHz; f_RF= 1960 MHz; N = 9800; loop B/W = 20 kHz.

= 10 MHz; f_PFD= 1 MHz; offset frequency = 1 kHz; f_RF= 3100 MHz; N = 3100; loop B/W = 20 kHz.

REFIN

11

12

13

14

Rev. F | Page 4 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

TIMING CHARACTERISTICS

Guaranteed by design but not production tested. AV_DD= DV_DD= 3 V ꢀ10% ꢁ V ꢀ10ꢂ AV_DD≤ V_P≤ 6 Vꢂ

AGND = DGND = CPGND = 1 Vꢂ R_SET= 4.7 kΩꢂ T_A= T_MINto T_MAX% unless otherwise noted.

Table 2.

Parameter

Limit at T_MINto T_MAX(B Version)

Unit

Test Conditions/Comments

DATA to CLOCK setup time

DATA to CLOCK hold time

CLOCK high duration

CLOCK low duration

t₁

t₂

t₃

t₄

t₅

t₆

10

25

10

20

ns min

CLOCK to LE setup time

LE pulse width

t₃

t₄

CLOCK

t₁

t₂

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

DB23 (MSB)

DB22

DB2

DATA

LE

t₆

t₅

LE

Figure 2. Timing Diagram

Rev. F | Page 5 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

AV_DDto GND¹

Rating

−0.3 V to +7 V

−0.3 V to +0.3 V

−0.3 V to +7 V

−0.3 V to +5.5 V

−0.3 V to V_DD+ 0.3 V

−0.3 V to V_P+ 0.3 V

−0.3 V to V_DD+ 0.3 V

320 mV

AV_DDto DV_DD

V_Pto GND

V_Pto AV_DD

Digital I/O Voltage to GND

Analog I/O Voltage to GND

REF_IN, RF_INA, RF_INB to GND

RF_INA to RF_INB

This device is a high performance RF integrated circuit with an

ESD rating of <2 kV, and it is ESD sensitive. Proper precautions

should be taken for handling and assembly.

TRANSISTOR COUNT

Operating Temperature Range

Industrial (B Version)

Storage Temperature Range

Maximum Junction Temperature

TSSOP θ_JAThermal Impedance

LFCSP θ_JAThermal Impedance

(Paddle Soldered)

6425 (CMOS) and 303 (Bipolar).

−40°C to +85°C

−65°C to +150°C

150°C

150.4°C/W

122°C/W

LFCSP θ_JAThermal Impedance

(Paddle Not Soldered)

Lead Temperature, Soldering

Vapor Phase (60 sec)

Infrared (15 sec)

216°C/W

215°C

220°C

¹GND = AGND = DGND = 0 V.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. F | Page 6 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

R

V

P

SET

DV

CP

15 MUXOUT

14 LE

CPGND

AGND

1

2

3

4

5

DD

ADF4110

ADF4111

ADF4112

ADF4113

ADF4110

ADF4111

ADF4112

ADF4113

MUXOUT

LE

CPGND

AGND

13 DATA

12 CLK

11 CE

RF

B

A

IN

TOP VIEW

(Not to Scale)

DATA

CLK

RF

B

IN

A

TOP VIEW

(Not to Scale)

CE

AV

DD

DGND

REF

IN

NOTES

1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO AGND.

Figure 3. TSSOP Pin Configuration

Figure 4. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

TSSOP

Pin No.

LFCSP

Pin No.

Mnemonic Function

1

19

R_SET

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.

The nominal voltage potential at the R_SETpin is 0.56 V. The relationship between I_CPand R_SETis

23.5

R_SET

I_CPmax

=

So, with R_SET= 4.7 kΩ, I_CPmax= 5 mA.

2

20

CP

Charge Pump Output. When enabled, this provides I_CPto the external loop filter, which in turn

drives the external VCO.

3

4

5

1

2, 3

4

CPGND

AGND

RF_INB

Charge Pump Ground. This is the ground return path for the charge pump.

Analog Ground. This is the ground return path of the prescaler.

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with

a small bypass capacitor, typically 100 pF. See Figure 29.

6

7

5

6, 7

RF_INA

AV_DD

Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.

Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground

plane should be placed as close as possible to this pin. AV_DDmust be the same value as DV_DD.

8

REF_IN

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2, and an equivalent input

resistance of 100 kΩ. See Figure 28. This input can be driven from a TTL or CMOS crystal oscillator, or

can be ac-coupled.

9

10

9, 10

11

DGND

CE

Digital Ground.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into

three-state mode. Taking the pin high powers up the device depending on the status of the power-

down Bit F2.

11

12

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is

latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS

input.

12

13

14

15

16

13

DATA

LE

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This

input is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into

one of the four latches; the latch is selected using the control bits.

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.

Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground

plane should be placed as close as possible to this pin. DV_DDmust be the same value as AV_DD.

14

15

MUXOUT

DV_DD

V_P

16, 17

18

Charge Pump Power Supply. This should be greater than or equal to V_DD. In systems where V_DDis 3 V,

V_Pcan be set to 6 V and used to drive a VCO with a tuning range of up to 6 V. 1

EPAD

Exposed Pad (LFCSP Only). The exposed paddle should be connected to AGND.

Rev. F | Page 7 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

FREQ

–UNIT

PARAM

DATA

KEYWORD

IMPEDANCE

–OHMS

–TYPE –FORMAT

REFERENCE

LEVEL = –4.2dBm

V

= 3V, V = 5V

P

DD

= 5mA

GHz

S

MA

R

50

I

CP

FREQ MAGS11

ANGS11

–2.0571

–4.4427

–6.3212

–2.1393

–12.13

FREQ MAGS11

ANGS11

–40.134

–43.747

–44.393

–46.937

–49.6

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 s

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1.00

0.89207

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

0.9512

0.8886

0.93458

0.94782

0.96875

0.92216

0.93755

0.96178

0.94354

0.95189

0.97647

0.98619

0.95459

0.97945

0.98864

0.97399

0.97216

0.89022

0.96323

0.90566

0.90307

0.89318

0.89806

0.89565

0.88538

0.89699

0.89927

0.87797

0.90765

0.88526

0.81267

0.90357

0.92954

0.92087

0.93788

–13.52

–51.884

–51.21

AVERAGES = 19

–15.746

–18.056

–19.693

–22.246

–24.336

–25.948

–28.457

–29.735

–31.879

–32.681

–31.522

–34.222

–36.961

–39.343

–53.55

–56.786

–58.781

–60.545

–61.43

–61.241

–64.051

–66.19

–92.5dBc/Hz

–63.775

–2.0kHz

–1.0kHz

900MHz

FREQUENCY

1.0kHz

2.0kHz

Figure 5. S-Parameter Data for the ADF4113 RF Input (up to 1.8 GHz)

Figure 8. ADF4113 Phase Noise

(900 MHz, 200kHz, 20 kHz) with DLY and SYNC Enabled

0

–40

–50

V

= 3V

DD

= 3V

–5

–10

–15

–20

–25

–30

–35

P

–60

RMS NOISE = 0.52°

–70

R

= –40dBc/Hz

L

–80

T

= +25°C

A

–90

T

= +85°C

A

–100

–110

–120

–130

–140

T

= –40°C

2

A

0

1

3

4

5

100

1k

10k

100k

1M

RF INPUT FREQUENCY (GHz)

FREQUENCY OFFSET FROM 900MHz CARRIER (Hz)

Figure 9. ADF4113 Integrated Phase Noise

(900 MHz, 200 kHz, 20 kHz, Typical Lock Time: 400 µs)

Figure 6. Input Sensitivity (ADF4113)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–40

–50

REFERENCE

LEVEL = –4.2dBm

V

= 3V, V = 5V

P

DD

= 5mA

I

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 s

–60

RMS NOISE = 0.62°

–70

R

= –40dBc/Hz

L

–80

AVERAGES = 19

–90

–100

–110

–120

–130

–140

–91.0dBc/Hz

–2.0kHz

–1.0kHz

900MHz

FREQUENCY

1.0kHz

2.0kHz

100

1k

10k

100k

1M

FREQUENCY OFFSET FROM 900MHz CARRIER (Hz)

Figure 7. ADF4113 Phase Noise (900 MHz, 200 kHz, 20 kHz)

Figure 10. ADF4113 Integrated Phase Noise

(900 MHz, 200 kHz, 35 kHz, Typical Lock Time: 200 µs)

Rev. F | Page 8 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

0

–40

–50

REFERENCE

LEVEL = –4.2dBm

V

= 3V, V = 5V

P

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

DD

= 5mA

I

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5s

–60

RMS NOISE = 1.6°

–70

–80

R

= –40dBc/Hz

L

AVERAGES = 30

–90

–100

–110

–120

–130

–140

–90.2dBc/Hz

–400kHz

–200kHz

900MHz

FREQUENCY

200kHz

400kHz

100

1k

10k

100k

1M

FREQUENCY OFFSET FROM 1750MHz CARRIER (Hz)

Figure 11. ADF4113 Reference Spurs (900 MHz, 200 kHz, 20 kHz)

Figure 14. ADF4113 Integrated Phase Noise

(1750 MHz, 30 kHz, 3 kHz)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

REFERENCE

LEVEL = –4.2dBm

V

= 3V, V = 5V

P

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

DD

= 5mA

REFERENCE

LEVEL = –5.7dBm

V

= 3V, V = 5V

P

DD

= 5mA

I

CP

I

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 35kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5s

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 3Hz

VIDEO BANDWIDTH = 3Hz

SWEEP = 255s

AVERAGES = 30

POSITIVE PEEK DETECT

MODE

–79.6dBc/Hz

–89.3dBc/Hz

–400kHz

–200kHz

900MHz

FREQUENCY

200kHz

400kHz

–80kHz

–40kHz

1750MHz

FREQUENCY

40kHz

80kHz

Figure 12. ADF4113 (900 MHz, 200 kHz, 35 kHz)

Figure 15. ADF4113 Reference Spurs (1750 MHz, 30 kHz, 3 kHz)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

REFERENCE

LEVEL = –8.0dBm

REFERENCE

LEVEL = –4.2dBm

V

I

= 3V, V = 5V

P

V

I

= 3V, V = 5V

P

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

DD

= 5mA

DD

= 5mA

CP

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 10kHz

VIDEO BANDWIDTH = 10kHz

SWEEP = 477ms

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9s

AVERAGES = 10

AVERAGES = 45

–86.6dBc/Hz

–75.2dBc/Hz

–400Hz

–200Hz

1750MHz

FREQUENCY

200Hz

400Hz

–2.0kHz

–1.0kHz

3100MHz

FREQUENCY

1.0kHz

2.0kHz

Figure 13. ADF4113 Phase Noise (1750 MHz, 30 kHz, 3 kHz)

Figure 16. ADF4113 Phase Noise (3100 MHz, 1 MHz, 100 kHz)

Rev. F | Page 9 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

–60

–70

–40

–50

V

= 3V

DD

P

–60

RMS NOISE = 1.7°

–70

–80

R

= 40dBc/Hz

L

–80

–90

–100

–110

–90

–120

–130

–140

–100

2

3

4

5

6

–40

–20

0

20

40

60

80

100

10

TEMPERATURE (°C)

FREQUENCY OFFSET FROM 3100MHz CARRIER (Hz)

Figure 17. ADF4113 Integrated Phase Noise

(3100 MHz, 1 MHz, 100 kHz)

Figure 20. ADF4113 Phase Noise vs. Temperature

(900 MHz, 200 kHz, 20 kHz)

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

REFERENCE

LEVEL = –17.2dBm

V

= 3V, V = 5V

P

DD

= 5mA

V

= 3V

DD

= 5V

I

CP

PFD FREQUENCY = 1MHz

P

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 13s

AVERAGES = 1

–80

–80.6dBc/Hz

–90

–100

–40

–20

0

20

40

60

80

100

–2.0MHz

–1.0MHz

3100MHz

FREQUENCY

1.0MHz

2.0MHz

TEMPERATURE (°C)

Figure 18. Reference Spurs (3100 MHz, 1 MHz, 100 kHz)

Figure 21. ADF4113 Reference Spurs vs. Temperature

(900 MHz, 200 kHz, 20 kHz)

–120

–130

–140

–150

–160

–170

–180

–5

–15

–25

–35

–45

–55

–65

–75

–85

–95

–105

V

= 3V

DD

= 5V

V

= 3V

DD

= 5V

P

1

10

100

1000

10000

0

1

2

3

4

5

PHASE DETECTOR FREQUENCY (kHz)

TUNING VOLTAGE (V)

Figure 19. ADF4113 Phase Noise (Referred to CP Output)

vs. Phase Detector Frequency

Figure 22. ADF4113 Reference Spurs (200 kHz) vs. V_TUNE

(900 MHz, 200 kHz, 20 kHz)

Rev. F | Page 10 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

–60

3.0

V

= 3V

DD

= 3V

P

V

= 3V

DD

= 5V

2.5

2.0

1.5

1.0

0.5

0

P

–70

–80

–90

–100

–40

–20

0

20

40

60

80

100

0

50

100

150

200

TEMPERATURE (°C)

PRESCALER OUTPUT FREQUENCY (MHz)

Figure 23. ADF4113 Phase Noise vs. Temperature

(836 MHz, 30 kHz, 3 kHz)

Figure 26. DI_DDvs. Prescaler Output Frequency

(ADF4110, ADF4111, ADF4112, ADF4113)

–60

6

5

V

= 3V

DD

= 5V

V

= 5V

PP

= 5mA

4

P

I

CP

–70

–80

3

2

1

0

–1

–2

–3

–4

–5

–6

–90

–100

–40

–20

0

20

40

60

80

100

0

0.5

1.0

1.5

2.0

2.5

(V)

3.0

3.5

4.0

4.5

5.0

TEMPERATURE (°C)

V

CP

Figure 24. ADF4113 Reference Spurs vs. Temperature

(836 MHz, 30 kHz, 3 kHz)

Figure 27. Charge Pump Output Characteristics for ADF4110 Family

10

9

8

7

6

5

4

3

2

1

0

ADF4113

ADF4112

ADF4110

ADF4111

0

8/9

16/17

32/33

64/65

PRESCALER VALUE

Figure 25. AI_DDvs. Prescaler Value

Rev. F | Page 11 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

A AND B COUNTERS

The reference input stage is shown in Figure 28. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REF_INpin

on power-down.

The A and B CMOS counters combine with the dual-modulus

prescaler to allow a wide ranging division ratio in the PLL

feedback counter. The counters are specified to work when the

prescaler output is 200 MHz or less. Thus, with an RF input

frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a

value of 8/9 is not.

POWER-DOWN

CONTROL

Pulse Swallow Function

The A and B counters, in conjunction with the dual-modulus

prescaler, make it possible to generate output frequencies that

are spaced only by the reference frequency divided by R. The

equation for the VCO frequency is

100k

SW2

NC

REF

TO R COUNTER

IN

NC

SW1

BUFFER

SW3

NO

f_VCO= [(P × B) + A]f_REFIN/R

Figure 28. Reference Input Stage

where:

f_VCO= output frequency of external voltage controlled oscillator

(VCO)

RF INPUT STAGE

The RF input stage is shown in Figure 29. It is followed by a

two-stage limiting amplifier to generate the current mode logic

(CML) clock levels needed for the prescaler.

P = preset modulus of dual-modulus prescaler

B = preset divide ratio of binary 13-bit counter(3 to 8191)

A = preset divide ratio of binary 6-bit swallow counter (0 to 63)

f_REFIN= output frequency of the external reference frequency

oscillator

1.6V

BIAS

GENERATOR

AV

DD

R = preset divide ratio of binary 14-bit programmable reference

500

counter (1 to 16383)

RF

A

B

IN

R COUNTER

The 14-bit R counter allows the input reference frequency to be

divided down to produce the reference clock to the phase

frequency detector (PFD). Division ratios from 1 to 16,383 are

allowed.

IN

AGND

Figure 29. RF Input Stage

N = BP + A

TO PFD

PRESCALER (P/P + 1)

13-BIT B

COUNTER

Along with the A and B counters, the dual-modulus prescaler

(P/P + 1) enables the large division ratio, N, to be realized (N =

BP + A). The dual-modulus prescaler, operating at CML levels,

takes the clock from the RF input stage and divides it down to a

manageable frequency for the CMOS A and B counters. The

prescaler is programmable; it can be set in software to 8/9,

16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core.

FROM RF

INPUT STAGE

LOAD

PRESCALER

P/P + 1

LOAD

6-BIT A

MODULUS

CONTROL

COUNTER

Figure 30. A and B Counters

Rev. F | Page 12 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

Lock Detect

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

MUXOUT can be programmed for two types of lock detect:

digital lock detect and analog lock detect.

The PFD takes inputs from the R counter and N counter (N =

BP + A) and produces an output proportional to the phase and

frequency difference between them. Figure 31 is a simplified

schematic. The PFD includes a programmable delay element

that controls the width of the antibacklash pulse. This pulse

ensures that there is no dead zone in the PFD transfer function

and minimizes phase noise and reference spurs. Two bits in the

reference counter latch, ABP2 and ABP1, control the width of

the pulse. See Table 7.

Digital lock detect is active high. When LDP in the R counter

latch is set to 0, digital lock detect is set high when the phase

error on three consecutive phase detector (PD) cycles is less

than 15 ns. With LDP set to 1, five consecutive cycles of less

than 15 ns are required to set the lock detect. It stays high until

a phase error greater than 25 ns is detected on any subsequent

PD cycle.

The N-channel open-drain analog lock detect should be

operated with a 10 kΩ nominal external pull-up resistor. When

lock has been detected, this output is high with narrow low-

going pulses.

V

P

CHARGE

PUMP

UP

HI

D1

Q1

U1

DV

DD

R DIVIDER

CLR1

PROGRAMMABLE

DELAY

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

CP

U3

MUXOUT

MUX

CONTROL

ABP1

ABP2

CLR2

U2

DOWN

HI

D2

Q2

DGND

N DIVIDER

Figure 32. MUXOUT Circuit

CPGND

INPUT SHIFT REGISTER

R DIVIDER

N DIVIDER

CP OUTPUT

The ADF4110 family digital section includes a 24-bit input shift

register, a 14-bit R counter, and a 19-bit N counter comprised of

a 6-bit A counter and a 13-bit B counter. Data is clocked into

the 24-bit shift register on each rising edge of CLK MSB first.

Data is transferred from the shift register to one of four latches

on the rising edge of LE. The destination latch is determined by

the state of the two control bits (C2, C1) in the shift register.

These are the two LSBs, DB1 and DB0, as shown in Figure 2.

The truth table for these bits is shown in Table 5.

Figure 31. PFD Simplified Schematic and Timing (In Lock)

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4110 family allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 in the function

latch. Table 9 shows the full truth table. Figure 32 shows the

MUXOUT section in block diagram form.

Table 6 shows a summary of how the latches are programmed.

Table 5. C2, C1 Truth Table

Control Bits

C2

0

C1

0

Data Latch

R Counter

0

1

0

1

N Counter (A and B)

Function Latch (Including Prescaler)

Initialization Latch

Rev. F | Page 13 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

Table 6. ADF4110 Family Latch Summary

REFERENCE COUNTER LATCH

ANTI-

BACKLASH

WIDTH

TEST

MODE BITS

CONTROL

BITS

SYNC

14-BIT REFERENCE COUNTER, R

DLY

DB21 DB20

DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8 DB7

DB6 DB5

DB4 DB3

R3 R2

DB2

DB1

DB23 DB22

DB19

T2

DB0

DLY SYNC LDP

T1

ABP2 ABP1 R14

R13 R12

R11

R10

R9

R8

R7

R6

R5

R4

R1 C2 (0) C1 (0)

X

X = DON'T CARE

N COUNTER LATCH

CONTROL

BITS

RESERVED

13-BIT B COUNTER

6-BIT A COUNTER

DB5 DB4

DB23 DB22 DB21

DB19

B12

DB17

B10

DB15

B8

DB13 DB12 DB11 DB10

DB6

A5

DB3 DB2

A2 A1

DB1 DB0

DB20

B13

DB18

B11

DB16

B9

DB14

B7

DB9 DB8

B2 B1

DB7

A6

G1

B6

B5

B4

B3

A4

A3

C2 (0) C1 (1)

X

X = DON'T CARE

FUNCTION LATCH

CURRENT

SETTING

2

CURRENT

SETTING

1

TIMER COUNTER

CONTROL

MUXOUT

CONTROL

BITS

PRESCALER

VALUE

DB21 DB20

DB18

DB16

DB14

DB12 DB11 DB10 DB9 DB8

DB7 DB6

F2 M3

DB3 DB2

PD1 F1

DB1

DB23 DB22

P2 P1

DB19

DB17

DB15

DB13

DB5 DB4

DB0

PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4

TC3 TC2

TC1

F5

F4

F3

M2

M1

C2 (1) C1 (0)

INITIALIZATION LATCH

CURRENT

SETTING

2

CURRENT

SETTING

1

PRESCALER

VALUE

TIMER COUNTER

CONTROL

MUXOUT

CONTROL

BITS

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14

PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4

DB12 DB11 DB10 DB9 DB8

DB7 DB6

F2 M3

DB5 DB4

M2 M1

DB3 DB2

PD1 F1

DB1

C2 (1) C1 (1)

DB23 DB22

DB13

DB0

P2

P1

TC3 TC2

TC1

F5

F4

F3

Rev. F | Page 14 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

Table 7. Reference Counter Latch Map

ANTI-

BACKLASH

WIDTH

TEST

MODE BITS

CONTROL

BITS

DLY

SYNC

14-BIT REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

R7

DB7

R6

DB6

R5

DB5

R4

DB4

R3

DB3

R2

DB2

DB1

DB0

DLY SYNC LDP

T2

T1

ABP2 ABP1 R14

R13

R12

R11

R10

R9

R8

R1 C2 (0) C1 (0)

X

X = DON'T

CARE

R14

R13

0

R12

••••••••••

••••••••• •

R3

R2

R1

1

DIVIDE RATIO

1

0

•

0

•

0

1

•

0

1

0

•

0

•

••••••••• •

0

1

0

•

2

3

4

•

1

0

1

0

1

0

1

16380

16381

16382

16383

ABP2 ABP1 ANTIBACKLASH PULSE WIDTH

0

1

0

1

0

1

3.0ns

1.5ns

6.0ns

3.0ns

TEST MODE BITS SHOULD

BE SET TO 00 FOR NORMAL

OPERATION

LDP

0

THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

1

DLY SYNC

OPERATION

0

1

NORMAL OPERATION

OUTPUT OF PRESCALER IS RESYNCHRONIZED

WITH NONDELAYED VERSION OF RF INPUT

1

0

1

NORMAL OPERATION

OUTPUT OF PRESCALER IS RESYNCHRONIZED

WITH DELAYED VERSION OF RF INPUT

Rev. F | Page 15 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

Table 8. AB Counter Latch Map

CONTROL

BITS

RESERVED

DB23 DB22

13-BIT B COUNTER

6-BIT A COUNTER

DB21 DB20

G1 B13

DB18 DB17 DB16

DB14

B7

DB12 DB11 DB10 DB9

DB8

B1

DB7

A6

DB6

A5

DB3

A2

DB2

DB1

DB19

B12

DB15

B8

DB13

B6

DB5

A4

DB4

A3

DB0

B11 B10

B9

B5

B4

B3

B2

A1 C2 (0) C1 (1)

X

X = DON'T CARE

A COUNTER

DIVIDE RATIO

A6

0

•

A5

A2

0

1

•

A1

0

1

0

1

•

••••••••• •

0

•

0

1

2

3

•

1

0

1

0

1

0

1

60

61

62

63

B13

0

B12

0

B11

••••••••• •

B3

B2

B1

B COUNTER DIVIDE RATIO

NOT ALLOWED

0

•

0

1

•

0

1

0

•

0

1

0

1

0

•

0

•

0

•

••••••••• •

NOT ALLOWED

3

4

•

1

0

1

0

1

0

1

8188

8189

8190

8191

F4 (FUNCTION LATCH)

FASTLOCK ENABLE*

CP GAIN

OPERATION

0

1

0

1

0

1

CHARGE PUMP CURRENT SETTING 1

IS PERMANENTLY USED.

CHARGE PUMP CURRENT SETTING 2

IS PERMANENTLY USED.

CHARGE PUMP CURRENT SETTING 1

IS USED.

CHARGE PUMP CURRENT IS SWITCHED

TO SETTING 2. THE TIME SPENT IN

SETTING 2 IS DEPENDENT UPON WHICH

FASTLOCK MODE IS USED. SEE FUNCTION

LATCH DESCRIPTION.

N = BP + A, P IS PRESCALER VALUE SET IN THE

FUNCTION LATCH, B MUST BE GREATER THAN OR

EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES

*SEE TABLE 9

2

OF (N

F ), AT THE OUTPUT, N IS (P –P).

REF

MIN

X

THESE BITS ARE NOT USED

BY THE DEVICE AND ARE

DON'T CARE BITS

Rev. F | Page 16 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

Table 9. Function Latch Map

CURRENT

SETTING

2

CURRENT

SETTING

1

TIMER COUNTER

CONTROL

MUXOUT

CONTROL

BITS

PRESCALER

VALUE

DB17 DB16

DB14 DB13 DB12 DB11 DB10 DB9

DB8

F3

DB7

F2

DB6

M3

DB3

PD1

DB2

F1

DB1

C2(1) C1(0)

DB23 DB22 DB21 DB20 DB19 DB18

DB15

DB5

M2

DB4

M1

DB0

P2

P1

PD2

CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4

TC3

TC2

TC1

F5

F4

COUNTER

OPERATION

F1

0

NORMAL

PHASE DETECTOR

POLARITY

F2

0

1

R, A, B COUNTERS

HELD IN RESET

NEGATIVE

1

POSITIVE

F3

0

CHARGE PUMP OUTPUT

NORMAL

1

THREE-STATE

F4

0

F5

FASTLOCK MODE

FASTLOCK DISABLED

FASTLOCK MODE 1

FASTLOCK MODE 2

X

0

1

TIMEOUT

TC4

TC3

TC2

TC1

(PFD CYCLES)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

7

11

15

19

23

27

31

35

39

43

47

51

55

59

63

M3

M2

0

M1

OUTPUT

0

1

THREE-STATE OUTPUT

0

DIGITAL LOCK DETECT

(ACTIVE HIGH)

0

1

0

1

0

1

N DIVIDER OUTPUT

DV_DD

R DIVIDER OUTPUT

ANALOG LOCK DETECT

(N-CHANNEL OPEN-DRAIN)

SEE FUNCTION LATCH,

TIMER COUNTER CONTROL

SECTION

CPI6

CPI5

CPI4

I_CP(mA)

1

0

1

SERIAL DATA OUTPUT

DGND

2.7kΩ

4.7kΩ

10kΩ

CPI3

0

CPI2

0

CPI1

0

1.09

2.18

3.26

4.35

5.44

6.53

7.62

8.70

0.63

0.29

0

1

0

1

0

1

0

1

0

1

0

1

1.25

1.88

2.50

3.13

3.75

4.38

5.00

0.59

0.88

1.76

1.47

1.76

2.06

2.35

CE PIN PD2 PD1

MODE

0

1

X

0

1

X

0

1

ASYNCHRONOUS POWER-DOWN

NORMAL OPERATION

ASYNCHRONOUS POWER-DOWN

SYNCHRONOUS POWER-DOWN

P2

P1

0

PRESCALER VALUE

8/9

0

1

16/17

32/33

64/65

1

0

1

Rev. F | Page 17 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

Table 10. Initialization Latch Map

CURRENT

SETTING

2

CURRENT

SETTING

1

PRESCALER

VALUE

TIMER COUNTER

CONTROL

MUXOUT

CONTROL

BITS

DB13 DB12 DB11 DB10

DB9

F4

DB8

F3

DB7

F2

DB6

M3

DB5

M2

DB4

M1

DB3

PD1

DB2

F1

DB1

C2 (1) C1 (1)

DB0

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14

P2

P1

PD2

CPI6 CPI5 CPI4 CPI3 CPI2 CPI1

TC4

TC3

TC2

TC1

F5

COUNTER

OPERATION

F1

0

PHASE DETECTOR

POLARITY

NORMAL

F2

0

1

R, A, B COUNTERS

HELD IN RESET

NEGATIVE

POSITIVE

1

F3

0

CHARGE PUMP

OUTPUT NORMAL

THREE-STATE

1

F4

0

F5

FASTLOCK MODE

FASTLOCK DISABLED

FASTLOCK MODE 1

FASTLOCK MODE 2

X

0

1

TIMEOUT

TC4

TC3

TC2

TC1

(PFD CYCLES)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

7

11

15

19

23

27

31

35

39

43

47

51

55

59

63

M3

0

M2

0

M1

0

OUTPUT

THREE-STATE OUTPUT

0

1

DIGITAL LOCK DETECT

(ACTIVE HIGH)

0

1

0

1

0

1

N DIVIDER OUTPUT

DV

DD

R DIVIDER OUTPUT

ANALOG LOCK DETECT

(N-CHANNEL OPEN-DRAIN)

SEE FUNCTION LATCH,

TIMER COUNTER CONTROL

SECTION

CPI6

CPI5

CPI4

I

(mA)

CP

1

0

1

SERIAL DATA OUTPUT

DGND

2.7kΩ

4.7kΩ

10kΩ

CPI3

0

CPI2

0

CPI1

0

1.09

0.63

0.29

0.59

0.88

1.76

1.47

1.76

2.06

2.35

0

1

0

1

0

1

0

1

0

1

0

1

2.18

3.27

4.35

5.44

6.53

7.62

8.70

1.25

1.88

2.50

3.13

3.75

4.38

5.00

CE PIN PD2 PD1

MODE

0

1

X

0

1

X

0

1

ASYNCHRONOUS POWER-DOWN

NORMAL OPERATION

ASYNCHRONOUS POWER-DOWN

SYNCHRONOUS POWER-DOWN

P2

P1

0

PRESCALER VALUE

8/9

0

1

16/17

32/33

64/65

1

0

1

Rev. F | Page 18 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

FUNCTION LATCH

Fastlock Mode Bit

The on-chip function latch is programmed with C2, C1 set to 1.

Table 9 shows the input data format for programming the

function latch.

DB10 of the function latch is the fastlock enable bit. When

fastlock is enabled, this bit determines which fastlock mode is

used. If the fastlock mode bit is 0, fastlock mode 1 is selected; if

the fastlock mode bit is 1, fastlock mode 2 is selected.

Counter Reset

DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter

and the AB counters are reset. For normal operation, this bit

should be 0. Upon powering up, the F1 bit must be disabled,

and the N counter resumes counting in “close” alignment with

the R counter. (The maximum error is one prescaler cycle.)

Fastlock Mode 1

The charge pump current is switched to the contents of Current

Setting 2.

The device enters fastlock by having a 1 written to the CP gain

bit in the AB counter latch. The device exits fastlock by having a

0 written to the CP gain bit in the AB counter latch.

Power-Down

DB3 (PD1) and DB21 (PD2) on the ADF411x provide

program-mable power-down modes. They are enabled by the

CE pin.

Fastlock Mode 2

The charge pump current is switched to the contents of Current

Setting 2. The device enters fastlock by having a 1 written to the

CP gain bit in the AB counter latch. The device exits fastlock

under the control of the timer counter. After the timeout period

determined by the value in TC4 through TC1, the CP gain bit in

the AB counter latch is automatically reset to 0 and the device

reverts to normal mode instead of fastlock. See Table 9 for the

timeout periods.

When the CE pin is low, the device is immediately disabled

regardless of the states of PD2, PD1.

In the programmed asynchronous power-down, the device

powers down immediately after latching a 1 into Bit PD1,

provided PD2 has been loaded with a 0.

In the programmed synchronous power-down, the device

power-down is gated by the charge pump to prevent unwanted

frequency jumps. Once power-down is enabled by writing a 1

into Bit PD1 (provided a 1 has also been loaded to PD2), the

device goes into power-down on the next charge pump event.

Timer Counter Control

The user has the option of programming two charge pump cur-

rents. Current Setting 1 is meant to be used when the RF output

is stable and the system is in a static state. Current Setting 2 is

meant to be used when the system is dynamic and in a state of

change (i.e., when a new output frequency is programmed).

When a power-down is activated (either synchronous or

asynchronous mode including CE pin activated power-down),

the following events occur:

The normal sequence of events is as follows:

•

All active dc current paths are removed.

The user initially decides what the preferred charge pump

currents are going to be. For example, they may choose 2.5 mA

as Current Setting 1 and 5 mA as Current Setting 2.

The R, N, and timeout counters are forced to their load

state conditions.

•

The charge pump is forced into three-state mode.

The digital clock detect circuitry is reset.

The RFIN input is debiased.

At the same time, they must also decide how long they want the

secondary current to stay active before reverting to the primary

current. This is controlled by the timer counter control bits,

DB14 through DB11 (TC4 through TC1) in the function latch.

The truth table is given in Table 10.

The reference input buffer circuitry is disabled.

A user can program a new output frequency simply by pro-

gramming the AB counter latch with new values for A and B. At

the same time, the CP gain bit can be set to 1, which sets the

charge pump with the value in CPI6–CPI4 for a period deter-

mined by TC4 through TC1. When this time is up, the charge

pump current reverts to the value set by CPI3–CPI1. At the

same time, the CP gain bit in the AB counter latch is reset to 0

and is ready for the next time the user wishes to change the

frequency.

The input register remains active and capable of loading

and latching data.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1 on

the ADF4110 family. Table 9 shows the truth table.

Fastlock Enable Bit

DB9 of the function latch is the fastlock enable bit. Fastlock is

enables only when this is 1.

Rev. F | Page 19 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

Note that there is an enable feature on the timer counter. It is

enabled when Fastlock Mode 2 is chosen by setting the fastlock

mode bit (DB10) in the function latch to 1.

When the initialization latch is loaded, the following occurs:

1. The function latch contents are loaded.

2. An internal pulse resets the R, A, B, and timeout counters

to load state conditions and three-states the charge pump.

Note that the prescaler band gap reference and the oscil-

lator input buffer are unaffected by the internal reset pulse,

allowing close phase alignment when counting resumes.

Charge Pump Currents

CPI3, CPI2, and CPI1 program Current Setting 1 for the charge

pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the

charge pump. The truth table is given in Table 10.

Prescaler Value

3. Latching the first AB counter data after the initialization

word activates the same internal reset pulse. Successive AB

loads do not trigger the internal reset pulse unless there is

another initialization.

P2 and P1 in the function latch set the prescaler values. The

prescaler value should be chosen so that the prescaler output

frequency is always less than or equal to 200 MHz. Thus, with

an RF frequency of 2 GHz, a prescaler value of 16/17 is valid but

a value of 8/9 is not.

CE Pin Method

1. Apply V_DD

.

PD Polarity

2. Bring CE low to put the device into power-down. This is an

asynchronous power-down in that it happens immediately.

This bit sets the phase detector polarity bit. See Table 10.

CP Three-State

3. Program the function latch (10). Program the R counter

latch (00). Program the AB counter latch (01).

This bit controls the CP output pin. With the bit set high, the

CP output is put into three-state. With the bit set low, the CP

output is enabled.

4. Bring CE high to take the device out of power-down. The R

and AB counters now resume counting in close alignment.

INITIALIZATION LATCH

When C2, C1 = 1, 1, the initialization latch is programmed.

This is essentially the same as the function latch (programmed

when C2, C1 = 1, 0).

After CE goes high, a duration of 1 µs may be required for the

prescaler band gap voltage and oscillator input buffer bias to

reach steady state.

However, when the initialization latch is programmed, an addi-

tional internal reset pulse is applied to the R and AB counters.

This pulse ensures that the AB counter is at load point when the

AB counter data is latched, and the device begins counting in

close phase alignment.

CE can be used to power the device up and down in order to

check for channel activity. The input register does not need to

be reprogrammed each time the device is disabled and enabled

as long as it has been programmed at least once after V_DDwas

initially applied.

If the latch is programmed for synchronous power-down (CE

pin high; PD1 bit high; PD2 bit low), the internal pulse also

triggers this power-down. The prescaler reference and the

oscillator input buffer are unaffected by the internal reset pulse,

so close phase alignment is maintained when counting resumes.

Counter Reset Method

1. Apply V_DD

.

2. Do a function latch load (10 in 2 LSBs). As part of this,

load 1 to the F1 bit. This enables the counter reset.

3. Do an R counter load (00 in 2 LSBs). Do an AB counter

load (01 in 2 LSBs). Do a function latch load (10 in 2

LSBs). As part of this, load 0 to the F1 bit. This disables the

counter reset.

When the first AB counter data is latched after initialization, the

internal reset pulse is again activated. However, successive AB

counter loads after this will not trigger the internal reset pulse.

DEVICE PROGRAMMING AFTER INITIAL

POWER-UP

This sequence provides the same close alignment as the initiali-

zation method. It offers direct control over the internal reset.

Note that counter reset holds the counters at load point and

three states the charge pump but does not trigger synchronous

power-down. The counter reset method requires an extra

function latch load compared to the initialization latch method.

After initial power-up of the device, there are three ways to

program the device.

Initialization Latch Method

Apply V_DD. Program the initialization latch (11 in 2 LSBs of

input word). Make sure the F1 bit is programmed to 0. Then, do

an R load (00 in 2 LSBs). Then do an AB load (01 in 2 LSBs).

Rev. F | Page 20 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

RESYNCHRONIZING THE PRESCALER OUTPUT

Table 7 (the Reference Counter Latch Map) shows two bits,

DB22 and DB21, which are labeled DLY and SYNC,

respectively. These bits affect the operation of the prescaler.

If the SYNC feature is used on the synthesizer, some care must

be taken. At some point, (at certain temperatures and output

frequencies), the delay through the prescaler coincides with the

active edge on RF input; this causes the SYNC feature to break

down. It is important to be aware of this when using the SYNC

feature. Adding a delay to the RF signal, by programming

DLY = 1, extends the operating frequency and temperature

somewhat. Using the SYNC feature also increases the value of

the AI_DDfor the device. With a 900 MHz output, the ADF4113

AI_DDincreases by about 1.3 mA when SYNC is enabled and by

an additional 0.3 mA if DLY is enabled.

With SYNC = 1, the prescaler output is resynchronized with the

RF input. This has the effect of reducing jitter due to the

prescaler and can lead to an overall improvement in synthesizer

phase noise performance. Typically, a 1 dB to 2 dB

improvement is seen in the ADF4113. The lower bandwidth

devices can show an even greater improvement. For example,

the ADF4110 phase noise is typically improved by 3 dB when

SYNC is enabled.

All the typical performance plots in this data sheet, except for

Figure 8, apply for DLY and SYNC = 0, i.e., no resynchroniza-

tion or delay enabled.

With DLY = 1, the prescaler output is resynchronized with a

delayed version of the RF input.

Rev. F | Page 21 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

APPLICATIONS

LOCAL OSCILLATOR FOR GSM BASE STATION TRANSMITTER

Figure 33 shows the ADF4111/ADF4112/ADF4113 being used

with a VCO to produce the LO for a GSM base station

transmitter.

All of these specifications are needed and used to come up with

the loop filter component values shown in Figure 33.

The loop filter output drives the VCO, which in turn is fed back

to the RF input of the PLL synthesizer. It also drives the RF out-

put terminal. A T-circuit configuration provides 50 Ω matching

between the VCO output, the RF output, and the RF_INterminal

of the synthesizer.

The reference input signal is applied to the circuit at FREF_IN

and, in this case, is terminated in 50 Ω. A typical GSM system

would have a 13 MHz TCXO driving the reference input with-

out any 50 Ω termination. In order to have channel spacing of

200 kHz (GSM standard), the reference input must be divided

by 65, using the on-chip reference divider of the ADF4111/

ADF4112/ADF4113.

In a PLL system, it is important to know when the system is in

lock. In Figure 33, this is accomplished by using the MUXOUT

signal from the synthesizer. The MUXOUT pin can be pro-

grammed to monitor various internal signals in the synthesizer.

One of these is the LD or lock-detect signal.

The charge pump output of the ADF4111/ADF4112/ADF4113

(Pin 2) drives the loop filter. In calculating the loop filter

component values, a number of items need to be considered. In

this example, the loop filter was designed so that the overall

phase margin for the system would be 45 degrees. Other PLL

system specifications are

K_D= 5 mA

K_V= 12 MHz/V

Loop Bandwidth = 20 kHz

F

_REF= 200 kHz

N = 4500

Extra Reference Spur Attenuation = 10 dB

V

DD

P

RF

OUT

100pF

18Ω

16

7

15

100pF

B

18Ω

V

AV

DV

P

DD

3.3kΩ

P

V

CC

1000pF

2

C

CP

FREF

IN

8

REF

IN

620pF

1nF

5.6kΩ

1

VCO190-902T

51Ω

ADF4111

ADF4112

ADF4113

8.2nF

CE

LOCK

DETECT

MUXOUT

14

CLK

DATA

LE

100pF

6

5

RF

A

B

IN

R

2

51Ω

1

SET

IN

4.7kΩ

100pF

3

4

9

1

2

TO BE USED WHEN GENERATOR SOURCE IMPEDANCE IS 50Ω.

OPTIONAL MATCHING RESISTOR DEPENDING ON RF FREQUENCY.

OUT

DECOUPLING CAPACITORS ON AV , DV , AND V OF THE ADF411x

DD DD

P

AND ON THE POSITIVE SUPPLY OF THE VCO190-902T HAVE BEEN

OMITTED FROM THE DIAGRAM TO INCREASE CLARITY.

Figure 33. Local Oscillator for GSM Base Station

Rev. F | Page 22 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

RF

OUT

100pF

18Ω

VCO

100pF

18Ω

LOOP

FILTER

2

CP

FREF

IN

8

REF

IN

INPUT OUTPUT

ADF4111

ADF4112

ADF4113

GND

CE

CLK

DATA

LE

LOCK

DETECT

14

MUXOUT

1

R

SET

100pF

6

5

RF

A

B

IN

2.7kΩ

51Ω

IN

100pF

AD5320

12-BIT

V-OUT DAC

POWER SUPPLY CONNECTIONS AND DECOUPLING

CAPACITORS ARE OMITTED FOR CLARITY.

SPI COMPATIBLE SERIAL BUS

Figure 34. Driving the R_SETPin with a D/A Converter

a tuning range as wide as an octave. For example, cable TV

tuners have a total range of about 400 MHz. Figure 36 shows an

application where the ADF4113 is used to control and program

the Micronetics M3500-2235. The loop filter was designed for

an RF output of 2900 MHz, a loop bandwidth of 40 kHz, a PFD

frequency of 1 MHz, I_CPof 10 mA (2.5 mA synthesizer I_CP

multiplied by the gain factor of 4), VCO K_Dof 90 MHz/V

(sensitivity of the M3500-2235 at an output of 2900 MHz), and

a phase margin of 45°C.

USING A D/A CONVERTER TO DRIVE THE R_SETPIN

A D/A converter can be used to drive the R_SETpin of the

ADF4110 family, thus increasing the level of control over the

charge pump current, I_CP. This can be advantageous in wide-

band applications where the sensitivity of the VCO varies over

the tuning range. To compensate for this, the I_CPmay be varied

to maintain good phase margin and ensure loop stability. See

Figure 34.

SHUTDOWN CIRCUIT

In narrow-band applications, there is generally a small variation

in output frequency (generally less than 10%) and a small

variation in VCO sensitivity over the range (typically 10% to

15%). However, in wideband applications, both of these

parameters have a much greater variation. In Figure 36, for

example, there is a −25% and +17% variation in the RF output

from the nominal 2.9 GHz. The sensitivity of the VCO can vary

from 120 MHz/V at 2750 MHz to 75 MHz/V at 3400 MHz

(+33%, −17%). Variations in these parameters change the loop

bandwidth. This in turn can affect stability and lock time. By

changing the programmable I_CP, it is possible to get compensa-

tion for these varying loop conditions and ensure that the loop

is always operating close to optimal conditions.

The attached circuit in Figure 35 shows how to shut down both

the ADF4110 family and the accompanying VCO. The ADG701

switch goes closed circuit when a Logic 1 is applied to the IN

input. The low cost switch is available in both SOT-23 and

MSOP packages.

WIDEBAND PLL

Many of the wireless applications for synthesizers and VCOs in

PLLs are narrow band in nature. These applications include the

various wireless standards like GSM, DSC1800, CDMA, and

WCDMA. In each of these cases, the total tuning range for the

local oscillator is less than 100 MHz. However, there are also

wideband applications for which the local oscillator could have

Rev. F | Page 23 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

V

P

POWER-DOWN CONTROL

V

S

DD

RF

OUT

ADG701

IN

V

DD

D

GND

100pF

7

15

DV

16 10

V CE

P

18Ω

100pF

V

18Ω

CC

AV

DD

LOOP

FILTER

2

1

CP

FREF

IN

8

VCO

18Ω

REF

IN

R

SET

GND

4.7kΩ

ADF4110

ADF4111

ADF4112

ADF4113

100pF

RF

A

B

6

5

IN

51Ω

RF

IN

3

4

9

100pF

DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE

BEEN OMITTED FROM THE DIAGRAM TO INCREASE CLARITY.

Figure 35. Local Oscillator Shutdown Circuit

RF

OUT

20V

12V

V

7

V

DD

P

3kΩ

100pF

1kΩ

18Ω

V

CC

100pF

18Ω

15

DV

16

OUT

AD820

V_TUNE

3.3kΩ

AV

V

DD

P

2

1

1000pF

M3500-2235

GND

CP

8

REF

FREF

IN

2.8nF

19nF

130pF

R

51Ω

SET

680Ω

4.7kΩ

ADF4113

CE

LOCK

DETECT

CLK MUXOUT

DATA

LE

14

100pF

RF

A

B

IN

6

5

IN

51Ω

3

4

9

100pF

DECOUPLING CAPACITORS ON AV , DV , V OF THE ADF4113

DD DD

P

AND ON VCC OF THE M3500-2250 HAVE BEEN OMITTED FROM

THE DIAGRAM TO AID CLARITY.

Figure 36. Wideband Phase-Locked Loop

Rev. F | Page 24 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

DIRECT CONVERSION MODULATOR

Typical phase noise performance from this LO is −85 dBc/Hz at

a 1 kHz offset.

In some applications, a direct conversion architecture can be

used in base station transmitters. Figure 37 shows the combina-

tion available from ADI to implement this solution.

The LO port of the AD8346 is driven in single-ended fashion.

LOIN is ac-coupled to ground with the 100 pF capacitor; LOIP

is driven through the ac coupling capacitor from a 50 Ω source.

An LO drive level of between −6 dBm and −12 dBm is required.

The circuit of Figure 37 gives a typical level of −8 dBm.

The circuit diagram shows the AD9761 being used with the

AD8346. The use of dual integrated DACs such as the AD9761

with specified 0.02 dB and 0.004 dB gain and offset matching

characteristics ensures minimum error contribution (over

temperature) from this portion of the signal chain.

The RF output is designed to drive a 50 Ω load but must be ac-

coupled as shown in Figure 37. If the I and Q inputs are driven

in quadrature by 2 V p-p signals, the resulting output power is

around −10 dBm.

The local oscillator (LO) is implemented using the ADF4113. In

this case, the OSC 3B1-13M0 provides the stable 13 MHz

reference frequency. The system is designed for a 200 kHz

channel spacing and an output center frequency of 1960 MHz.

The target application is a WCDMA base station transmitter.

REFIO

IOUTA

IOUTB

IBBP

IBBN

100pF

LOW-PASS

FILTER

RF

OUT

VOUT

MODULATED

DIGITAL

DATA

AD9761

TxDAC

AD8346

QOUTA

QOUTB

QBBP

QBBN

LOW-PASS

FILTER

FS ADJ

2kΩ

LOIN

LOIP

100pF

4.7kΩ

100pF

OSC 3B1-13M0

TCXO

18Ω

R

100pF

18Ω

SET

3.3kΩ

REF

CP

IN

3.9kΩ

VCO190-1960T

910pF

ADF4113

620pF

SERIAL

DIGITAL

9.1nF

INTERFACE

18Ω

RF B

IN

RF A

IN

100pF

51Ω

POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS

ARE OMITTED FROM DIAGRAM TO INCREASE CLARITY.

Figure 37. Direct Conversion Transmitter Solution

Rev. F | Page 25 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

INTERFACING

ADSP-2181 Interface

The ADF4110 family has a simple SPI® compatible serial inter-

face for writing to the device. SCLK, SDATA, and LE control the

data transfer. When latch enable (LE) goes high, the 24 bits that

have been clocked into the input register on each rising edge of

SCLK get transferred to the appropriate latch. See Figure 2 for

the timing diagram and Table 5 for the latch truth table.

Figure 39 shows the interface between the ADF4110 family and

the ADSP-21xx digital signal processor. The ADF4110 family

needs a 24-bit serial word for each latch write. The easiest way

to accomplish this using the ADSP-21xx family is to use the

auto buffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block

of serial data before an interrupt is generated.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

833 kHz, or one update every 1.2 µs. This is certainly more than

adequate for systems that have typical lock times in the

hundreds of microseconds.

SCLK

DT

SDATA

ADSP-21xx

ADF4110

ADF4111

ADF4112

ADF4113

TFS

LE

ADuC812 Interface

CE

Figure 38 shows the interface between the ADF4110 family and

the ADuC812 MicroConverter®. Since the ADuC812 is based

on an 8051 core, this interface can be used with any 8051 based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4110 family

needs a 24-bit word. This is accomplished by writing three 8-bit

bytes from the MicroConverter to the device. When the third

byte has been written, the LE input should be brought high to

complete the transfer.

I/O FLAGS

MUXOUT

(LOCK DETECT)

Figure 39. ADSP-21xx to ADF4110 Family Interface

Set up the word length for 8 bits and use three memory

locations for each 24-bit word. To program each 24-bit latch,

store the three 8-bit bytes, enable the auto buffered mode, and

then write to the transmit register of the DSP. This last opera-

tion initiates the autobuffer transfer.

When power is first applied to the ADF4110 family, three writes

are needed (one each to the R counter latch, N counter latch,

and initialization latch) for the output to become active.

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

The lands on the chip scale package (CP-20) are rectangular.

The printed circuit board pad for these should be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. The land should be centered on the

pad. This ensures that the solder joint size is maximized.

I/O port lines on the ADuC812 are also used to control power-

down (CE input), and to detect lock (MUXOUT configured as

lock detect and polled by the port input).

When the ADuC812 is operating in the mode described above,

the maximum SCLOCK rate of the ADuC812 is 4 MHz. This

means that the maximum rate at which the output frequency

can be changed is 166 kHz.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be a clearance of at least 0.25 mm between the thermal

pad and the inner edges of the pad pattern. This ensures that

shorting is avoided.

SCLK

SDATA

LE

SCLOCK

MOSI

ADuC812

ADF4110

ADF4111

ADF4112

ADF4113

Thermal vias may be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias are

used, they should be incorporated in the thermal pad at 1.2 mm

pitch grid. The via diameter should be between 0.3 mm and

0.33 mm, and the via barrel should be plated with 1 oz. copper

to plug the via.

I/O PORTS

CE

MUXOUT

(LOCK DETECT)

Figure 38. ADuC812 to ADF4110 Family Interface

The user should connect the printed circuit board thermal pad

to AGND.

Rev. F | Page 26 of 28

Data Sheet

ADF4110/ADF4111/ADF4112/ADF4113

OUTLINE DIMENSIONS

4.10

4.00 SQ

3.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

16

15

20

0.50

BSC

1

EXPOSED

PAD

2.30

2.10 SQ

2.00

11

5

6

10

0.65

0.60

0.55

0.20 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.

Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-20-6)

Dimensions shown in millimeters

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

Rev. F | Page 27 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

ORDERING GUIDE

Model¹

Temperature Range

–40°C to +85°C

-40°C to +85°C

–40°C to +85°C

Package Description

Package Option²

ADF4110BCPZ

20-Lead Frame Chip Scale Package [LFCSP_WQ]

16-Lead Thin Shrink Small Outline Package [TSSOP]

20-Lead Frame Chip Scale Package [LFCSP_WQ]

16-Lead Thin Shrink Small Outline Package [TSSOP]

20-Lead Frame Chip Scale Package [LFCSP_WQ]

16-Lead Thin Shrink Small Outline Package [TSSOP]

20-Lead Frame Chip Scale Package [LFCSP_WQ]

16-Lead Thin Shrink Small Outline Package [TSSOP]

DIE

CP-20-6

RU-16

ADF4110BCPZ-RL

ADF4110BCPZ-RL7

ADF4110BRU

ADF4110BRU-REEL

ADF4110BRU-REEL7

ADF4110BRUZ

ADF4110BRUZ-RL

ADF4110BRUZ-RL7

ADF4111BCPZ

ADF4111BCPZ-RL

ADF4111BCPZ-RL7

ADF4111BRU

CP-20-6

RU-16

ADF4111BRUZ

ADF4111BRUZ-RL

ADF4111BRUZ-RL7

ADF4112BCPZ

ADF4112BCPZ-RL

ADF4112BCPZ-RL7

ADF4112BRU

ADF4112BRU-REEL7

ADF4112BRUZ

ADF4112BRUZ-REEL

ADF4112BRUZ-REEL7

ADF4113BCPZ

ADF4113BCPZ-RL

ADF4113BCPZ-RL7

ADF4113BRU

ADF4113BRU-REEL7

ADF4113BRUZ

ADF4113BRUZ-REEL

ADF4113BRUZ-REEL7

ADF4113BCHIPS

EVAL-ADF4113EBZ1

EVAL-ADF4113EBZ2

EV-ADF411XSD1Z

RU-16

CP-20-6

RU-16

CP-20-6

RU-16

Evaluation Board

¹Z = RoHS Compliant Part.

²CP-20-6 package was formerly CP-20-1 package.

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D03496-0-1/13(F)

Rev. F | Page 28 of 28


型号：	ADF4110BCPZ
厂家：	ADI
描述：	RF PLL Frequency Synthesizers 射频锁相环频率合成器射频
文件：	总28页 (文件大小：428K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADF4110BCPZ [ADI]

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ADF4110BCPZ-REEL7

ADF4110BCPZ-RL

ADF4110BCPZ-RL7

ADF4110BRU

ADF4110BRU-REEL

ADF4110BRU-REEL7

ADF4110BRUZ

ADF4110BRUZ-RL

ADF4110BRUZ-RL7

ADF4110_13

ADF4110_15