ADF4110BRU [ADI]
RF PLL Frequency Synthesizers; 射频锁相环频率合成器型号: | ADF4110BRU |
厂家: | ADI |
描述: | RF PLL Frequency Synthesizers |
文件: | 总24页 (文件大小:263K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
a
RF PLL Frequency Synthesizers
ADF4110/ADF4111/ADF4112/ADF4113
GENERAL DESCRIPTION
FEATURES
The ADF4110 family of frequency synthesizers can be used
to implement local oscillators in the upconversion and down-
conversion sections of wireless receivers and transmitters. They
consist of a low-noise digital PFD (Phase Frequency Detector),
a precision charge pump, a programmable reference divider,
programmable A and B counters and a dual-modulus prescaler
(P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction
with the dual modulus prescaler (P/P+1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter), allows selectable REFIN frequencies at the PFD
input. A complete PLL (Phase-Locked Loop) can be imple-
mented if the synthesizer is used with an external loop filter and
VCO (Voltage Controlled Oscillator).
ADF4110: 550 MHz
ADF4111: 1.2 GHz
ADF4112: 3.0 GHz
ADF4113: 4.0 GHz
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler 8/9, 16/17,
32/33, 64/65
Programmable Charge Pump Currents
Programmable Antibacklash Pulsewidth
3-Wire Serial Interface
Analog and Digital Lock Detect
Hardware and Software Power-Down Mode
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to
5.5 V and can be powered down when not in use.
APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP
RSET
CPGND
REFERENCE
14-BIT
R COUNTER
REFIN
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
14
R COUNTER
LATCH
CLK
DATA
LE
24-BIT
INPUT REGISTER
FUNCTION
LATCH
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
22
A, B COUNTER
LATCH
SDOUT
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
19
FROM
FUNCTION
LATCH
HIGH Z
AVDD
13
MUX
MUXOUT
N = BP + A
13-BIT
B COUNTER
SDOUT
RFIN
A
LOAD
LOAD
PRESCALER
P/P +1
RFINB
6-BIT
A COUNTER
M3 M2 M1
ADF4110/ADF4111
ADF4112/ADF4113
6
CE
AGND
DGND
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
ADF4110/ADF4111/ADF4112/ADF4113–SPECIFICATIONS1
(AVDD = DVDD = 3 V ؎ 10%, 5 V ؎ 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 k⍀; TA = TMIN to TMAX unless otherwise noted)
Parameter
B Version
B Chips2
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Frequency
ADF4110
See Figure 25 for Input Circuit.
Use a square wave for lower frequencies.
45/550
25/550
0.045/1.2
0.2/3.0
0.1/3.0
0.2/3.7
–15/0
45/550
25/550
0.045/1.2
0.2/3.0
0.1/3.0
0.2/3.7
–15/0
MHz min/max
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
dBm min/max
ADF4110
ADF4111
ADF4112
ADF4112
Input Level = –10 dBm
Input Level = –10 dBm
Input Level = –10 dBm
ADF4113
RF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency3
RF CHARACTERISTICS (5 V)
RF Input Frequency
ADF4110
ADF4111
ADF4112
ADF4113
ADF4113
RF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency3
165
165
MHz max
Use a square wave for lower frequencies.
Input Level = –5 dBm
25/550
0.025/1.4
0.1/3.0
0.2/3.7
0.2/4.0
–10/0
25/550
0.025/1.4
0.1/3.0
0.2/3.7
0.2/4.0
–10/0
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
dBm min/max
200
200
MHz max
REFIN CHARACTERISTICS
REFIN Input Frequency
0/100
–5/0
0/100
–5/0
MHz min/max
dBm min/max
Reference Input Sensitivity4
AC-Coupled. When DC-Coupled:
0 to VDD max (CMOS-Compatible)
REFIN Input Capacitance
REFIN Input Current
10
100
10
100
pF max
µA max
PHASE DETECTOR
Phase Detector Frequency5
55
55
MHz max
CHARGE PUMP
I
CP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
CP 3-State Leakage Current
Programmable: See Table V
With RSET = 4.7 kΩ
5
5
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
625
2.5
2.7/10
1
2
1.5
2
625
2.5
2.7/10
1
2
1.5
2
With RSET = 4.7 kΩ
See Table V
I
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
0.5 V ≤ VCP ≤ VP – 0.5
0.5 V ≤ VCP ≤ VP – 0.5
VCP = VP/2
LOGIC INPUTS
V
INH, Input High Voltage
VINL, Input Low Voltage
INH/IINL, Input Current
0.8 × DVDD
0.8 × DVDD
V min
0.2 × DVDD
0.2 × DVDD
V max
µA max
pF max
I
1
10
1
10
CIN, Input Capacitance
LOGIC OUTPUTS
V
OH, Output High Voltage
DVDD – 0.4
0.4
DVDD – 0.4
0.4
V min
V max
IOH = 500 µA
IOL = 500 µA
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
2.7/5.5
AVDD
AVDD/6.0
2.7/5.5
AVDD
AVDD/6.0
V min/V max
V min/V max
AVDD ≤ VP ≤ 6.0 V
See Figures 22 and 23
4.5 mA Typical
4.5 mA Typical
6.5 mA Typical
8.5 mA Typical
TA = 25°C
IDD6 (AIDD + DIDD
ADF4110
ADF4111
ADF4112
ADF4113
IP
)
5.5
5.5
7.5
11
0.5
1
4.5
4.5
6.5
8.5
0.5
1
mA max
mA max
mA max
mA max
mA max
µA typ
Low Power Sleep Mode
–2–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
Parameter
B Version
B Chips2
Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
ADF4113 Phase Noise Floor7
–171
–164
–171
–164
dBc/Hz typ
dBc/Hz typ
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
Phase Noise Performance8
ADF4110: 540 MHz Output9
ADF4111: 900 MHz Output10
ADF4112: 900 MHz Output10
ADF4113: 900 MHz Output10
ADF4111: 836 MHz Output11
ADF4112: 1750 MHz Output12
ADF4112: 1750 MHz Output13
ADF4112: 1960 MHz Output14
ADF4113: 1960 MHz Output14
ADF4113: 3100 MHz Output15
Spurious Signals
–91
–87
–90
–91
–78
–86
–66
–84
–85
–86
–91
–87
–90
–91
–78
–86
–66
–84
–85
–86
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 300 Hz Offset and 30 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 200 Hz Offset and 10 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 1 MHz PFD Frequency
ADF4110: 540 MHz Output9
ADF4111: 900 MHz Output10
ADF4112: 900 MHz Output10
ADF4113: 900 MHz Output10
ADF4111: 836 MHz Output11
ADF4112: 1750 MHz Output12
ADF4112: 1750 MHz Output13
ADF4112: 1960 MHz Output14
ADF4113: 1960 MHz Output14
ADF4113: 3100 MHz Output15
–97/–106
–98/–110
–91/–100
–100/–110
–81/–84
–88/–90
–65/–73
–80/–84
–80/–84
–80/–82
–97/–106
–98/–110
–91/–100
–100/–110
–81/–84
–88/–90
–65/–73
–80/–84
–80/–84
–82/–82
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 30 kHz/60 kHz and 30 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 10 kHz/20 kHz and 10 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 1 MHz/2 MHz and 1 MHz PFD Frequency
NOTES
1Operating temperature range is as follows: B Version: –40°C to +85°C.
2The B Chip specifications are given as typical values.
3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
which is less than this value.
4AVDD = DVDD = 3 V; For AVDD = DVDD = 5 V, use CMOS-compatible levels.
5Guaranteed by design.
6TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz.
7The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
8The phase noise is measured with the EVAL-ADF411XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (See Table III).
9fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; Loop B/W = 20 kHz.
10
11
12
13
14
15
f
f
f
f
f
f
= 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.
= 10 MHz; fPFD = 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop B/W = 3 kHz.
= 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.
= 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.
= 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.
= 10 MHz; fPFD = 1 MHz; Offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; Loop B/W = 20 kHz.
REFIN
REFIN
REFIN
REFIN
REFIN
REFIN
Specifications subject to change without notice.
(AVDD = DVDD = 3 V ؎ 10%, 5 V ؎ 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V;
RSET = 4.7 k⍀; TA = TMIN to TMAX unless otherwise noted)
TIMING CHARACTERISTICS1
Limit at TMIN to TMAX
Parameter
(B Version)
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
NOTES
1Guaranteed by design but not production tested.
Specifications subject to change without notice.
–3–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
t3
t4
CLOCK
t1
t2
DB1
DB0 (LSB)
DB20 (MSB)
DB19
DB2
DATA
LE
(CONTROL BIT C2)
(CONTROL BIT C1)
t6
t5
LE
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS1, 2
CSP θJA Thermal Impedance
(TA = 25°C unless otherwise noted)
(Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . 216°C/W
Lead Temperature, Soldering
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP θJA Thermal Impedance (Paddle Soldered) . . . 122°C/W
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3 GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
6425 (CMOS) and 303 (Bipolar).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu-
late on the human body and test equipment and can discharge without detection. Although the
ADF4110/ADF4111/ADF4112/ADF4113 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option*
ADF4110BRU
ADF4110BCP
ADF4111BRU
ADF4111BCP
ADF4112BRU
ADF4112BCP
ADF4113BRU
ADF4113BCP
ADF4113BCHIPS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package (CSP)
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package (CSP)
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package (CSP)
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package (CSP)
DICE
RU-16
CP-20
RU-16
CP-20
RU-16
CP-20
RU-16
CP-20
DICE
*Contact the factory for chip availability.
–4–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
Function
1
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the RSET pin is 0.56 V. The relationship between ICP and RSET is
23.5
ICP max
=
RSET
So, with RSET = 4.7 kΩ, ICPmax = 5 mA.
2
CP
Charge Pump Output. When enabled this provides
external VCO.
ICP to the external loop filter, which in turn drives the
3
4
5
CPGND
AGND
RFINB
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 25.
6
7
RFINA
AVDD
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD
.
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resis-
tance of 100 kΩ. See Figure 24. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
9
10
DGND
CE
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.
11
12
13
14
15
16
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches, the latch being selected using the control bits.
This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency
to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
DATA
LE
MUXOUT
DVDD
VP
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD
.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.
PIN CONFIGURATIONS
TSSOP
CHIP SCALE PACKAGE
1
2
3
4
5
6
7
8
V
P
R
16
SET
15 DV
DD
CP
ADF4110
ADF4111
ADF4112
ADF4113
14 MUXOUT
13 LE
CPGND
AGND
1
2
3
4
5
15
14
13
12
11
CPGND
AGND
AGND
MUXOUT
LE
ADF4110
ADF4111
ADF4112
ADF4113
TOP VIEW 12
(Not to Scale)
11
DATA
CLK
RF
B
A
IN
IN
DATA
CLK
TOP VIEW
RF
RF
IN
B
(Not to Scale)
10
9
CE
AV
DD
RF
IN
A
CE
DGND
REF
IN
–5–
REV. 0
–Typical Performance Characteristics
ADF4110/ADF4111/ADF4112/ADF4113
0
V
= 3V, V = 5V
P
FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCE – OHMS
DD
REFERENCE
LEVEL = –4.2dBm
GHz
S
MA
R
50
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
ICP = 5mA
FREQ
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
MAGS11
0.89207
0.8886
ANGS11
–2.0571
–4.4427
–6.3212
–2.1393
–12.13
FREQ
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
MAGS11
ANGS11
–40.134
–43.747
–44.393
–46.937
–49.6
–51.884
–51.21
–53.55
–56.786
–58.781
–60.545
–61.43
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 19
0.9512
0.93458
0.94782
0.96875
0.92216
0.93755
0.96178
0.94354
0.95189
0.97647
0.98619
0.95459
0.97945
0.98864
0.97399
0.97216
0.89022
0.96323
0.90566
0.90307
0.89318
0.89806
0.89565
0.88538
0.89699
0.89927
0.87797
0.90765
0.88526
0.81267
0.90357
0.92954
0.92087
0.93788
–13.52
–15.746
–18.056
–19.693
–22.246
–24.336
–25.948
–28.457
–29.735
–31.879
–32.681
–31.522
–34.222
–36.961
–39.343
–61.241
–64.051
–66.19
–92.5dBc/Hz
–63.775
–2kHz
–1kHz
900MHz
+1kHz
+2kHz
Figure 5. ADF4113 Phase Noise (900 MHz, 200 kHz,
20 kHz) with DLY and SYNC Enabled
Figure 2. S-Parameter Data for the ADF4113 RF Input (Up
to 1.8 GHz)
10dB/DIVISION
–40
R
= –40dBc/Hz
RMS NOISE = 0.52؇
L
0
–50
–60
V
V
= 3V
DD
= 3V
–5
–10
–15
–20
–25
–30
–35
P
0.52؇ rms
–70
–80
–90
T
= +85؇C
A
–100
–110
–120
–130
T
= +25؇C
A
T
= –40؇C
A
–140
100Hz
5
3
4
0
1
2
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
RF INPUT FREQUENCY – GHz
Figure 3. Input Sensitivity (ADF4113)
Figure 6. ADF4113 Integrated Phase Noise (900 MHz,
200 kHz, 20 kHz, Typical Lock Time: 400 µs)
10dB/DIVISION
–40
R
= –40dBc/Hz
RMS NOISE = 0.62؇
L
0
V
= 3V, V = 5V
P
DD
REFERENCE
LEVEL = –4.2dBm
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–50
–60
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 19
0.62؇ rms
–70
–80
–90
–100
–110
–120
–130
–91.0dBc/Hz
–140
100Hz
–2kHz
–1kHz
900MHz
+1kHz
+2kHz
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
Figure 4. ADF4113 Phase Noise (900 MHz, 200 kHz, 20 kHz)
Figure 7. ADF4113 Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz, Typical Lock Time: 200 µs)
–6–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
10dB/DIVISION
RL = –40dBc/Hz
RMS NOISE = 1.6؇
–40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
REFERENCE
V
= 3V, V = 5V
P
DD
–50
–60
LEVEL = –4.2dBm
I
= 5mA
CP
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 2.5 SECONDS
AVERAGES = 30
–70
1.6؇ rms
–80
–90
–100
–110
–120
–130
–90.2dBc
–140
100Hz
–400kHz
–200kHz
900MHz
+200kHz
+400kHz
FREQUENCY OFFSET FROM 1750MHz CARRIER
1MHz
Figure 8. ADF4113 Reference Spurs (900 MHz, 200 kHz,
20 kHz)
Figure 11. ADF4113 Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)
0
0
V
I
= 3V, V = 5V
P
DD
V
= 3V, V = 5V
P
DD
REFERENCE
REFERENCE
–10
–20
–30
–40
–50
–60
–70
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
= 5mA
LEVEL = –5.7dBm
CP
LEVEL = –4.2dBm
I
= 5mA
CP
PFD FREQUENCY = 30kHz
LOOP BANDWIDTH = 3kHz
RES. BANDWIDTH = 3Hz
VIDEO BANDWIDTH = 3Hz
SWEEP = 255 SECONDS
POSITIVE PEAK DETECT
MODE
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 35kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30
–79.6dBc
–80
–90
–89.3dBc
–100
–80kHz
–40kHz
1750MHz
+40kHz
+80kHz
–400kHz
–200kHz
900MHz
+200kHz
+400kHz
Figure 9. ADF4113 Reference Spurs (900 MHz, 200 kHz,
35 kHz)
Figure 12. ADF4113 Reference Spurs (1750 MHz, 30 kHz,
3 kHz)
0
0
V
= 3V, V = 5V
V
= 3V, V = 5V
P
DD
P
DD
I = 5mA
CP
REFERENCE
REFERENCE
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
LEVEL = –8.0dBm
LEVEL = –4.2dBm
I
= 5mA
CP
PFD FREQUENCY = 30kHz
LOOP BANDWIDTH = 3kHz
RES. BANDWIDTH = 10kHz
VIDEO BANDWIDTH = 10kHz
SWEEP = 477ms
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 45
AVERAGES = 10
–86.6dBc/Hz
–75.2dBc/Hz
–400Hz
–200Hz
1750MHz
+200Hz
+400Hz
–2kHz
–1kHz
3100MHz
+1kHz
+2kHz
Figure 10. ADF4113 Phase Noise (1750 MHz, 30 kHz,
3 kHz)
Figure 13. ADF4113 Phase Noise (3100 MHz, 1 MHz,
100 kHz)
–7–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
10dB/DIVISION
R
= –40dBc/Hz
RMS NOISE = 1.7؇
L
–40
–60
–70
–50
–60
V
V
= 3V
= 3V
DD
P
1.7؇ rms
–70
–80
–90
–80
–100
–110
–120
–130
–90
–140
100Hz
–100
–40
–20
0
20
40
60
80
100
FREQUENCY OFFSET FROM 3100MHz CARRIER
1MHz
TEMPERATURE – ؇C
Figure 14. ADF4113 Integrated Phase Noise (3100 MHz,
1 MHz, 100 kHz)
Figure 17. ADF4113 Phase Noise vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
0
–60
V
I
= 3V, V = 5V
P
DD
= 5mA
REFERENCE
LEVEL = –17.2dBm
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CP
V
V
= 3V
= 5V
DD
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1
P
–70
–80
–80.6dBc
–90
–100
–2MHz
–1MHz
3100MHz
+1MHz
+2MHz
–40
–20
0
20
40
60
80
100
TEMPERATURE – ؇C
Figure 15. ADF4113 Reference Spurs (3100 MHz, 1 MHz,
100 kHz)
Figure 18. ADF4113 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
–5
–120
V
V
= 3V
= 5V
DD
–15
P
V
V
= 3V
= 5V
DD
–130
–140
–150
–160
–170
–180
P
–25
–35
–45
–55
–65
–75
–85
–95
–105
1
10
100
1000
10000
0
1
2
3
4
5
PHASE DETECTOR FREQUENCY – kHz
TUNING VOLTAGE – Volts
Figure 16. ADF4113 Phase Noise (Referred to CP Output)
vs. PFD Frequency
Figure 19. ADF4113 Reference Spurs (200 kHz) vs.
VTUNE (900 MHz, 200 kHz, 20 kHz)
–8–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
10
–60
–70
9
V
V
= 3V
= 5V
DD
P
8
7
6
5
4
3
2
1
0
ADF4113
–80
ADF4112
–90
ADF4110
ADF4111
–100
0
8/9
16/17
PRESCALER VALUE
32/33
64/65
–40
–20
0
20
40
60
80
100
TEMPERATURE – ؇C
Figure 20. ADF4113 Phase Noise vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
Figure 22. AIDD vs. Prescaler Value
–60
3.0
V
V
= 3V
= 3V
DD
P
V
V
= 3V
= 5V
DD
2.5
P
–70
–80
2.0
1.5
1.0
0.5
0
–90
–100
–40
–20
0
20
40
60
80
100
0
50
100
150
200
TEMPERATURE – ؇C
PRESCALER OUTPUT FREQUENCY – MHz
Figure 21. ADF4113 Reference Spurs vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
Figure 23. DIDD vs. Prescaler Output Frequency
(ADF4110, ADF4111, ADF4112, ADF4113)
–9–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
Pulse Swallow Function
CIRCUIT DESCRIPTION
The A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 24. SW1 and SW2
are normally-closed switches. SW3 is normally-open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
f
VCO = [(P × B) + A] × fREFIN/R
fVCO
Output frequency of external voltage controlled oscilla-
tor (VCO).
POWER-DOWN
CONTROL
P
Preset modulus of dual modulus prescaler
100k⍀
B
A
Preset Divide Ratio of binary 13-bit counter (3 to 8191).
NC
SW2
Preset Divide Ratio of binary 6-bit swallow counter (0 to
63).
TO R COUNTER
REF
IN
NC
SW1
BUFFER
SW3
fREFIN Output frequency of the external reference frequency
NO
oscillator.
Figure 24. Reference Input Stage
RF INPUT STAGE
R
Preset divide ratio of binary 14-bit programmable refer-
ence counter (1 to 16383).
The RF input stage is shown in Figure 25. It is followed by a
2-stage limiting amplifier to generate the CML (Current Mode
Logic) clock levels needed for the prescaler.
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase fre-
quency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
1.6V
BIAS
GENERATOR
AV
DD
500⍀
500⍀
N = BP + A
TO PFD
13-BIT B
COUNTER
RF
RF
A
B
IN
FROM RF
INPUT STAGE
LOAD
LOAD
PRESCALER
P/P + 1
IN
6-BIT A
COUNTER
MODULUS
CONTROL
AGND
Figure 25. RF Input Stage
Figure 26. A and B Counters
PRESCALER (P/P+1)
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The dual-modulus prescaler (P/P+1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A and B counters.
The prescaler is programmable. It can be set in software to 8/9,
16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core.
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 27 is a simpli-
fied schematic. The PFD includes a programmable delay element
which controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
Reference Counter Latch, ABP2 and ABP1 control the width
of the pulse. See Table III.
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The counters are specified to work when the
prescaler output is 200 MHz or less. Thus, with an RF input
frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
–10–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10 kΩ nominal. When
lock has been detected this output will be high with narrow low-
going pulses.
V
P
CHARGE
PUMP
UP
HI
D1
Q1
U1
DV
DD
R DIVIDER
CLR1
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
PROGRAMMABLE
DELAY
CP
U3
MUX
CONTROL
MUXOUT
ABP1
ABP2
CLR2
U2
DOWN
HI
D2
Q2
DGND
Figure 28. MUXOUT Circuit
INPUT SHIFT REGISTER
N DIVIDER
CPGND
The ADF4110 family digital section includes a 24-bit input shift
register, a 14-bit R counter and a 19-bit N counter, comprising
a 6-bit A counter and a 13-bit B counter. Data is clocked into
the 24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs DB1, DB0 as
shown in the timing diagram of Figure 1. The truth table for
these bits is shown in Table VI. Table I shows a summary of
how the latches are programmed.
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 27. PFD Simplified Schematic and Timing
(In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4110 family allows the
Table I. C2, C1 Truth Table
Control Bits
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2 and M1 in the function
latch. Table V shows the full truth table. Figure 28 shows the
MUXOUT section in block diagram form.
C2
C1
Data Latch
0
0
1
1
0
1
0
1
R Counter
Lock Detect
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive Phase Detector cycles is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
are required to set the lock detect. It will stay set high until a
phase error of greater than 25 ns is detected on any subsequent
PD cycle.
–11–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
Table II. ADF4110 Family Latch Summary
REFERENCE COUNTER LATCH
ANTI-
BACKLASH
WIDTH
TEST
CONTROL
BITS
SYNC
MODE BITS
14-BIT REFERENCE COUNTER, R
DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
R13 R12 R11 R10 R9 R8 R7 R6
DLY
DB17
DB15
DB5
R4
DB4
R3
DB2
R1
DB23 DB22 DB21 DB20 DB19 DB18
DB16
DB6
R5
DB3
R2
DB1 DB0
DLY SYNC LDP
T2
T1
ABP2 ABP1 R14
C2 (0) C1 (0)
X
X = DON'T CARE
N COUNTER LATCH
CONTROL
BITS
RESERVED
13-BIT B COUNTER
6-BIT A COUNTER
DB23
X
DB19
DB13
B6
DB5
A4
DB0
DB22 DB21 DB20
G1 B13
DB18 DB17 DB16 DB15 DB14
DB12 DB11 DB10 DB9 DB8
B5 B4 B3 B2 B1
DB7 DB6
DB4
A3
DB3 DB2
DB1
B12 B11
B10
B9
B8
B7
A6
A5
A2
A1
C2 (0) C1 (1)
X
X = DON'T CARE
FUNCTION LATCH
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
PRESCALER
VALUE
DB21
DB6
M3
DB2
F1
DB1
DB23 DB22
P2 P1
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
F2
DB5 DB4
DB3
PD1
DB0
PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3
M2
M1
C2 (1) C1 (0)
INITIALIZATION LATCH
CURRENT
SETTING
2
CURRENT
SETTING
1
PRESCALER
VALUE
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB19
DB17
DB15
DB5 DB4
M2 M1
DB23 DB22 DB21 DB20
DB18
DB16
DB14 DB13 DB12 DB11 DB10 DB9 DB8
TC3 TC2 TC1 F5 F4 F3
DB7 DB6
F2 M3
DB3 DB2
PD1 F1
DB1 DB0
P2
P1
PD2
CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4
C2 (1) C1 (1)
–12–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
Table III. Reference Counter Latch Map
ANTI-
BACKLASH
WIDTH
TEST
CONTROL
BITS
DLY
SYNC
DB21
MODE BITS
14-BIT REFERENCE COUNTER
DB23 DB22
DB20 DB19 DB18
DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
DB5
R4
DB0
DB17
DB6
R5
DB4 DB3 DB2 DB1
X
DLY SYNC LDP
T2
T1
ABP2 ABP1 R14
R13 R12
R11 R10
R9
R8
R7
R6
R3
R2
R1 C2 (0) C1 (0)
X = DON'T
CARE
R14
0
R13
0
R12
••••••••••
••••••••••
R3
R2
R1
DIVIDE RATIO
1
0
0
0
0
•
0
0
0
1
•
0
1
1
0
•
1
0
1
0
•
0
0
0
•
0
0
0
•
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
2
3
4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16380
16381
16382
16383
ABP2 ABP1 ANTIBACKLASH PULSEWIDTH
0
0
1
1
0
1
0
1
3.0ns
1.5ns
6.0ns
3.0ns
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
OPERATION
LDP
0
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
DLY SYNC
OPERATION
0
0
0
1
NORMAL OPERATION
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH NONDELAYED VERSION OF RF INPUT
1
1
0
1
NORMAL OPERATION
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH DELAYED VERSION OF RF INPUT
–13–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
Table IV. AB Counter Latch Map
CONTROL
BITS
RESERVED
DB23 DB22
13-BIT B COUNTER
6-BIT A COUNTER
DB6
A5
DB21
G1
DB17
DB2 DB1
DB20 DB19 DB18
DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
DB5 DB4 DB3
DB0
X
X
B13
B12
B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A6
A4
A3
A2
A1 C2 (0) C1 (1)
X = DON'T CARE
A COUNTER
A6
0
0
0
0
•
A5
A2
0
0
1
1
•
A1
0
1
0
1
•
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
DIVIDE RATIO
0
0
0
0
•
0
1
2
3
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
60
61
62
63
B13
0
B12
0
B11
0
••••••••••
••••••••••
B3
B2
B1
B COUNTER DIVIDE RATIO
NOT ALLOWED
0
0
0
0
1
•
0
0
1
1
0
•
0
1
0
1
0
•
0
0
0
0
•
0
0
0
0
•
0
0
0
0
•
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
NOT ALLOWED
NOT ALLOWED
3
4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8188
8189
8190
8191
F4 (FUNCTION LATCH)
FASTLOCK ENABLE*
CP GAIN
OPERATION
0
0
1
1
0
1
0
1
CHARGE PUMP CURRENT
SETTTING 1 IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
2 IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
1 IS USED
CHARGE PUMP CURRENT IS SWITCHED
TO SETTING 2. THE TIME SPENT IN
SETTING 2 IS DEPENDENT UPON WHICH
FASTLOCK MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION
N = BP + A, P IS PRESCALER VALUE SET IN THE
FUNCTION LATCH B MUST BE GREATER THAN OR
EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES
*SEE TABLE 5
2
OF (N
F
), AT THE OUTPUT, N IS (P -P).
MIN
X
REF
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS
–14–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
Table V. Function Latch Map
CURRENT
SETTTING
2
CURRENT
SETTTING
1
TIMER COUNTER
CONTROL
CONTROL
BITS
MUXOUT
CONTROL
PRESCALER
VALUE
DB21
DB17
DB6
M3
DB2 DB1
DB23 DB22
DB20 DB19 DB18
DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
DB5 DB4 DB3
DB0
P2
P1
PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4
TC3
TC2 TC1
F5
F4
F3
F2
M2
M1
PD1
F1
C2 (1) C1 (0)
COUNTER
F1
0
OPERATION
NORMAL
F2
PD POLARITY
NEGATIVE
POSITIVE
1
R, A, B COUNTERS
HELD IN RESET
0
1
F3
0
CHARGE PUMP OUTPUT
NORMAL
1
THREE-STATE
F4
F5
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE2
0
1
1
X
0
1
TIMEOUT
TC4
TC3
TC2
TC1
(PFD CYCLES)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
7
11
15
19
23
27
31
M3
M2
M1
35
39
43
47
51
55
59
63
OUTPUT
THREE-STATE OUTPUT
0
0
0
0
0
DIGITAL LOCK DETECT
(ACTIVE HIGH)
1
N DIVIDER OUTPUT
0
0
1
1
1
1
0
0
0
DV
DD
1
0
1
R DIVIDER OUTPUT
ANALOG LOCK DETECT
(N-CHANNEL OPEN-DRAIN)
SEE PAGE 17
CPI6
CPI5
CPI4
I
(mA)
CP
SERIAL DATA OUTPUT
DGND
1
1
1
1
0
1
2.7k⍀
4.7k⍀
10k⍀
CPI3
0
CPI2
0
CPI1
0
1.09
2.18
3.26
4.35
5.44
6.53
7.62
8.70
0.63
0.29
0.59
0.88
1.76
1.47
1.76
2.06
2.35
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1.25
1.88
2.50
3.13
3.75
4.38
5.00
CE PIN PD2 PD1
MODE
0
1
1
1
X
X
0
1
X
0
1
1
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
P2
0
P1
0
PRESCALER VALUE
8/9
16/17
32/33
64/65
0
1
1
0
1
1
–15–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
Table VI. Initialization Latch Map
CURRENT
SETTTING
2
CURRENT
SETTTING
1
PRESCALER
VALUE
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB18
DB16
DB9 DB8 DB7
F4 F3 F2
DB23 DB22 DB21 DB20 DB19
DB17
DB15 DB14 DB13 DB12 DB11 DB10
DB6 DB5 DB4 DB3
DB2 DB1
DB0
P2
P1
PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4
TC3
TC2 TC1
F5
M3
M2
M1
PD1
F1
C2 (1) C1 (1)
COUNTER
F1
0
OPERATION
NORMAL
F2
PD POLARITY
NEGATIVE
POSITIVE
1
R, A, B
COUNTERS
HELD IN RESET
0
1
F3
0
CHARGE PUMP
OUTPUT NORMAL
THREE-STATE
1
F4
0
F5
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE2
X
0
1
1
1
TIMEOUT
TC4
TC3
TC2
TC1
(PFD CYCLES)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
M3
0
M2
0
M1
0
OUTPUT
THREE-STATE OUTPUT
0
0
1
DIGITAL LOCK DETECT
(ACTIVE HIGH)
0
0
1
1
1
1
0
0
0
1
0
1
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
ANALOG LOCK DETECT
(N-CHANNEL OPEN-DRAIN)
SEE PAGE 17
CPI6
CPI5
CPI4
I
(mA)
CP
SERIAL DATA OUTPUT
DGND
1
1
1
1
0
1
2.7k⍀
4.7k⍀
10k⍀
CPI3
0
CPI2
0
CPI1
0
1.09
2.18
3.27
4.35
5.44
6.53
7.62
8.70
0.63
0.29
0.59
0.88
1.76
1.47
1.76
2.06
2.35
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1.25
1.88
2.50
3.13
3.75
4.38
5.00
CE PIN PD2 PD1
MODE
ASYNCHRONOUS POWER-
DOWN
NORMAL OPERATION
0
1
1
1
X
X
0
1
X
0
1
1
ASYNCHRONOUS POWER-
DOWN
SYNCHRONOUS POWER-DOWN
P2
P1
0
PRESCALER VALUE
8/9
0
0
1
1
16/17
32/33
64/65
1
0
1
–16–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
THE FUNCTION LATCH
Fastlock Mode 2
With C2, C1 set to 1, 0, the on-chip function latch will be pro-
grammed. Table V shows the input data format for programming
the Function Latch.
The charge pump current is switched to the contents of Current
Setting 2.
The device enters Fastlock by having a “1” written to the CP
Gain bit in the AB counter latch. The device exits Fastlock under
the control of the Timer Counter. After the timeout period deter-
mined by the value in TC4–TC1, the CP Gain bit in the AB
counter latch is automatically reset to “0” and the device reverts
to normal mode instead of Fastlock. See Table V for the time-
out periods.
Counter Reset
DB2 (F1) is the counter reset bit. When this is “1,” the R counter
and the A, B counters are reset. For normal operation this bit
should be “0.” Upon powering up, the F1 bit needs to be disabled,
the N counter resumes counting in “close” alignment with the R counter.
(The maximum error is one prescaler cycle.)
Power-Down
Timer Counter Control
DB3 (PD1) and DB21 (PD2) on the ADF4110 family, provide
programmable power-down modes. They are enabled by the
CE pin.
The user has the option of programming two charge pump cur-
rents. The intent is that the Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is meant to be used when the system is dynamic
and in a state of change (i.e., when a new output frequency is
programmed).
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1.
In the programmed asynchronous power-down, the device pow-
ers down immediately after latching a “1” into bit PD1, with the
condition that PD2 has been loaded with a “0.”
The normal sequence of events is as follows:
The user initially decides what the preferred charge pump cur-
rents are going to be. For example, they may choose 2.5 mA as
Current Setting 1 and 5 mA as the Current Setting 2.
In the programmed synchronous power-down, the device power-
down is gated by the charge pump to prevent unwanted frequency
jumps. Once the power-down is enabled by writing a “1” into
bit PD1 (on condition that a “1” has also been loaded to PD2),
the device will go into power-down on the occurrence of the next
charge pump event.
At the same time, they must also decide how long they want the
secondary current to stay active before reverting to the primary
current. This is controlled by the Timer Counter Control Bits
DB14 to DB11 (TC4–TC1) in the Function Latch. The truth
table is given in Table V.
When a power-down is activated (either synchronous or asynchro-
nous mode including CE-pin-activated power-down), the
following events occur:
When the user wishes to program a new output frequency, he
can simply program the AB counter latch with new values for A
and B. At the same time, he can set the CP Gain bit to a “1,”
which sets the charge pump with the value in CPI6–CPI4 for a
period of time determined by TC4–TC1. When this time is up,
the charge pump current reverts to the value set by CPI3– CPI1.
At the same time the CP Gain bit in the A, B Counter latch is
reset to 0 and is now ready for the next time the user wishes
to change the frequency again.
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
The RFIN input is debiased.
Note that there is an enable feature on the Timer Counter. It is
enabled when Fastlock Mode 2 is chosen by setting the Fastlock
Mode bit (DB10) in the Function Latch to “1.”
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading and
latching data.
Charge Pump Currents
CPI3, CPI2, CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table V.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4110 family. Table V shows the truth table.
Prescaler Value
Fastlock Enable Bit
P2 and P1 in the Function Latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 200 MHz. Thus, with
an RF frequency of 2 GHz, a prescaler value of 16/17 is valid
but a value of 8/9 is not.
DB9 of the Function Latch is the Fastlock Enable Bit. Only
when this is “1” is Fastlock enabled.
Fastlock Mode Bit
DB10 of the Function Latch is the Fastlock Enable bit. When
Fastlock is enabled, this bit determines which Fastlock Mode is
used. If the Fastlock Mode bit is “0” then Fastlock Mode 1
is selected and if the Fastlock Mode bit is “1,” then Fastlock
Mode 2 is selected.
PD Polarity
This bit sets the PD Polarity Bit. See Table V.
CP Three-State
This bit the CP output pin. With the bit set high, the CP output
is put into three-state. With the bit set low, the CP output is
enabled.
Fastlock Mode 1
The charge pump current is switched to the contents of Current
Setting 2.
The device enters Fastlock by having a “1” written to the CP
Gain bit in the AB counter latch. The device exits Fastlock by
having a “0” written to the CP Gain bit in the AB counter latch.
–17–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
THE INITIALIZATION LATCH
CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after VDD was
initially applied.
When C2, C1 = 1, 1, the Initialization Latch is programmed.
This is essentially the same as the Function Latch (programmed
when C2, C1 = 1, 0).
However, when the Initialization Latch is programmed an addi-
tional internal reset pulse is applied to the R and AB counters.
This pulse ensures that the AB counter is at load point when the
AB counter data is latched and the device will begin counting in
close phase alignment.
The Counter Reset Method
Apply VDD
.
Do a Function Latch Load (“10” in 2 LSBs). As part of this, load
“1” to the F1 bit. This enables the counter reset.
If the Latch is programmed for synchronous power-down (CE
pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse
also triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse and
so close phase alignment is maintained when counting resumes.
Do an R Counter Load (“00” in 2 LSBs) Do an AB Counter Load
(“01” in 2 LSBs). Do a Function Latch Load (“10” in 2 LSBs).
As part of this, load “0” to the F1 bit. This disables the counter
reset.
This sequence provides the same close alignment as the initial-
ization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and three-
states the charge pump, but does not trigger synchronous power-
down. The counter reset method requires an extra function latch
load compared to the initialization latch method.
When the first AB counter data is latched after initialization, the
internal reset pulse is again activated. However, successive AB
counter loads after this will not trigger the internal reset pulse.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initially powering up the device, there are three ways to
program the device.
RESYNCHRONIZING THE PRESCALER OUTPUT
Table III (the Reference Counter Latch Map) shows two bits,
DB22 and DB21 that are labelled DLY and SYNC respectively.
These bits affect the operation of the prescaler.
Initialization Latch Method
Apply VDD. Program the Initialization Latch (“11” in 2 LSBs
of input word). Make sure that F1 bit is programmed to “0.”
Then do an R load (“00” in 2 LSBs). Then do an AB load (“01”
in 2 LSBs).
With SYNC = “1,” the prescaler output is resynchronized with
the RF input. This has the effect of reducing jitter due to the
prescaler and can lead to an overall improvement in synthesizer
phase noise performance. Typically, a 1 dB to 2 dB improve-
ment is seen in the ADF4113. The lower bandwidth devices can
show an even greater improvement. For example, the ADF4110
phase noise is typically improved by 3 dB when SYNC is enabled.
When the Initialization Latch is loaded, the following occurs:
1. The function latch contents are loaded.
2. An internal pulse resets the R, A, B, and timeout counters
to load state conditions and also three-states the charge pump.
Note that the prescaler bandgap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allow-
ing close phase alignment when counting resumes.
With DLY = “1,” the prescaler output is resynchronized with a
delayed version of the RF input.
If the SYNC feature is used on the synthesizer, some care must
be taken. At some point, (at certain temperatures and output
frequencies), the delay through the prescaler will coincide with
the active edge on RF input and this will cause the SYNC fea-
ture to break down. So, it is important when using the SYNC
feature to be aware of this. Adding a delay to the RF signal, by
programming DLY = “1,” will extend the operating frequency
and temperature somewhat. Using the SYNC feature will also
increase the value of the AIDD for the device. With a 900 MHz
output, the ADF4113 AIDD increases by about 1.3 mA when
SYNC is enabled and a further 0.3 mA if DLY is enabled.
3. Latching the first AB counter data after the initialization word
will activate the same internal reset pulse. Successive AB loads
will not trigger the internal reset pulse unless there is another
initialization.
The CE Pin Method
Apply VDD
.
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
Program the Function Latch (10). Program the R Counter Latch
(00). Program the AB Counter Latch (01).
All the typical performance plots on the data sheet except for
Figure 5 apply for DLY and SYNC = “0,” i.e., no resynchroniza-
tion or delay enabled.
Bring CE high to take the device out of power-down. The R
and AB counters will now resume counting in close alignment.
Note that after CE goes high, a duration of 1 µs may be required
for the prescaler bandgap voltage and oscillator input buffer bias
to reach steady state.
–18–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
APPLICATIONS SECTION
KD = 5 mA
Local Oscillator for GSM Base Station Transmitter
The following diagram shows the ADF4111/ADF4112/ADF4113
being used with a VCO to produce the LO for a GSM base station
transmitter.
KV = 12 MHz/V
Loop Bandwidth = 20 kHz
FREF = 200 kHz
N = 4500
Extra Reference Spur Attenuation = 10 dB
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 Ω. Typical GSM system
would have a 13 MHz TCXO driving the Reference Input
without any 50 Ω termination. In order to have a channel
spacing of 200 kHz (the GSM standard), the reference input
must be divided by 65, using the on-chip reference divider of
the ADF4111/ADF4112/ADF4113.
All of these specifications are needed and used to come up with
the loop filter components values shown in Figure 29.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives
the RF Output terminal. A T-circuit configuration provides
50 Ω matching between the VCO output, the RF output and
the RFIN terminal of the synthesizer.
The charge pump output of the ADF4111/ADF4112/ADF4113
(Pin 2) drives the loop filter. In calculating the loop filter com-
ponent values, a number of items need to be considered. In this
example, the loop filter was designed so that the overall phase
margin for the system would be 45 degrees. Other PLL system
specifications are:
In a PLL system, it is important to know when the system is in
lock. In Figure 29, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be pro-
grammed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.
V
V
DD
P
RF
OUT
100pF
7
15
DV
16
18⍀
18⍀
B
AV
DD
V
P
DD
100pF
V
1000pF
1000pF
18⍀
3.3k⍀
5.6k⍀
8.2nF
CC
2
C
FREF
IN
CP
REF
IN
P
8
VCO190-902T
51⍀
1nF
620pF
ADF4111
ADF4112
ADF4113
CE
14
CLK
DATA
LE
LOCK
DETECT
MUXOUT
100pF
6
5
RF
IN
A
1
R
SET
RF
B
51⍀
IN
4.7k⍀
100pF
3
4
9
DECOUPLING CAPACITORS ON AV , DV , V OF THE ADF411
AND ON THE POSITIVE SUPPLY OF THE VCO190-902T HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
X
DD
DD
P
Figure 29. Local Oscillator for GSM Base Station
–19–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
RF
OUT
100pF
18⍀
18⍀
100pF
18⍀
2
LOOP
OUTPUT
VCO
INPUT
CP
8
FILTER
FREF
IN
REF
IN
R
ADF4111SET
ADF4112
GND
CE ADF4113
CLK
14
LOCK
DATA
MUXOUT
DETECT
LE
1
R
SET
100pF
6
5
RF
IN
A
B
2.7k⍀
RF
IN
51⍀
100pF
AD5320
12-BIT
V-OUT DAC
POWER SUPPLY CONNECTIONS AND DECOUPLING
CAPACITORS ARE OMITTED FOR CLARITY.
SPI COMPATIBLE SERIAL BUS
Figure 30. Driving the RSET Pin with a D/A Converter
USING A D/A CONVERTER TO DRIVE RSET PIN
You can use a D/A converter to drive the RSET pin of the
ADF4110 family and thus increase the level of control over the
charge pump current ICP. This can be advantageous in wideband
applications where the sensitivity of the VCO varies over the
tuning range. To compensate for this, the ICP may be varied to
maintain good phase margin and ensure loop stability. See
Figure 30.
wide band applications where the local oscillator could have up
to an octave tuning range. For example, cable TV tuners have a
total range of about 400 MHz. Figure 32 shows an applica-
tion where the ADF4113 is used to control and program the
Micronetics M3500-2235. The loop filter was designed for an
RF output of 2900 MHz, a loop bandwidth of 40 kHz, a PFD
frequency of 1 MHz, ICP of 10 mA (2.5 mA synthesizer ICP
multiplied by the gain factor of 4), VCO KD of 90 MHz/V (sen-
sitivity of the M3500-2235 at an output of 2900 MHz) and a
phase margin of 45°C.
SHUTDOWN CIRCUIT
The attached circuit in Figure 31 shows how to shut down both
the ADF4110 family and the accompanying VCO. The ADG701
switch goes closed circuit when a Logic 1 is applied to the IN
input. The low-cost switch is available in both SOT-23 and
micro SO packages.
In narrow-band applications, there is generally a small variation
in output frequency (generally less than 10%) and also a small
variation in VCO sensitivity over the range (typically 10% to 15%).
However, in wide band applications both of these parameters
have a much greater variation. In Figure 32, for example, we have
–25% and +17% variation in the RF output from the nominal
2.9 GHz. The sensitivity of the VCO can vary from 120 MHz/V
at 2750 MHz to 75 MHz/V at 3400 MHz (+33%, –17%).
Variations in these parameters will change the loop bandwidth.
This in turn can affect stability and lock time. By changing the
programmable ICP, it is possible to get compensation for these
varying loop conditions and ensure that the loop is always operat-
ing close to optimal conditions.
WIDEBAND PLL
Many of the wireless applications for synthesizers and VCOs in
PLLs are narrowband in nature. These applications include
the various wireless standards like GSM, DSC1800, CDMA or
WCDMA. In each of these cases, the total tuning range for the
local oscillator is less than 100 MHz. However, there are also
–20–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
V
P
POWER-DOWN CONTROL
V
S
DD
RF
OUT
IN
V
ADG701
GND
DD
D
100pF
7
AV
15 16
18⍀
18⍀
DV
V
V
CC
100pF
CE
CP
DD
DD
P
18⍀
2
1
LOOP
FILTER
8
FREF
REF
IN
IN
VCO
R
SET
GND
4.7k⍀
ADF4110
ADF4111
ADF4112
ADF4113
100pF
6
5
RF
A
B
IN
RF
51⍀
IN
100pF
3
4
9
DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 31. Local Oscillator Shutdown Circuit
RF
OUT
20V
12V
V
V
P
DD
3k⍀
100pF
1k⍀
V
18⍀
18⍀
CC
100pF
15
16
7
18⍀
OUT
V_TUNE
AV
DD
DV
V
AD820
DD P
3.3k⍀
2
CP
1000pF
1000pF
M3500-2235
GND
REF
FREF
IN
IN
2.8nF
19nF
680⍀
130pF
8
R
SET
51⍀
4.7k⍀
ADF4113
CE
14
LOCK
DETECT
CLK
DATA
LE
MUXOUT
100pF
6
5
RF
IN
A
B
RF
IN
51⍀
100pF
3
9
4
DECOUPLING CAPACITORS ON AV , DV , V OF THE ADF4113
DD DD
P
AND ON VCC OF THE M3500-2250 HAVE BEEN OMITTED FROM
THE DIAGRAM TO AID CLARITY.
Figure 32. Wideband Phase Locked Loop
–21–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
DIRECT CONVERSION MODULATOR
The target application is a WCDMA base station transmitter.
Typical phase noise performance from this LO is –85 dBc/Hz at
a 1 kHz offset.
In some applications a direct conversion architecture can be used
in base station transmitters. Figure 33 shows the combination
available from ADI to implement this solution.
The LO port of the AD8346 is driven in single-ended fashion.
LOIN is ac-coupled to ground with the 100 pF capacitor and
LOIP is driven through the ac coupling capacitor from a 50 Ω
source. An LO drive level of between –6 dBm and –12 dBm is
required. The circuit of Figure 33 gives a typical level of –8 dBm.
The circuit diagram shows the AD9761 being used with the
AD8346. The use of dual integrated DACs such as the AD9761
with specified 0.02 dB and 0.004 dB gain and offset match-
ing characteristics ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The RF output is designed to drive a 50 Ω load but must be
ac-coupled as shown in Figure 33. If the I and Q inputs are
driven in quadrature by 2 V p-p signals, the resulting output
power will be around –10 dBm.
The Local Oscillator (LO) is implemented using the ADF4113.
In this case, the OSC 3B1-13M0 provides the stable 13 MHz
reference frequency. The system is designed for a 200 kHz
channel spacing and an output center frequency of 1960 MHz.
REFIO
IOUTA
IBBP
IBBN
100pF
LOW-PASS
FILTER
RF
OUT
VOUT
IOUTB
MODULATED
DIGITAL
DATA
AD9761
TxDAC
AD8346
QOUTA
QOUTB
QBBP
QBBN
LOW-PASS
FILTER
FS ADJ
2k⍀
LOIN
LOIP
100pF
4.7k⍀
100pF
OSC 3B1-13M0
TCXO
18⍀
R
SET
100pF
18⍀
3.3k⍀
REF
IN
CP
3.9k⍀
VCO190-1960T
910pF
ADF4113
620pF
SERIAL
DIGITAL
NTERFACE
9.1nF
18⍀
RF
IN
B
RF A
IN
100pF
100pF
51⍀
POWER SUPPLY CONNECTIONS AND DECOUPLING
CAPACITORS ARE OMITTED FROM DIAGRAM FOR CLARITY.
Figure 33. Direct Conversion Transmitter Solution
–22–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
INTERFACING
ADSP-2181 Interface
The ADF4110 family has a simple SPI-compatible serial inter-
face for writing to the device. SCLK, SDATA and LE control
the data transfer. When LE (Latch Enable) goes high, the 24 bits
which have been clocked into the input register on each rising
edge of SCLK will get transferred to the appropriate latch. See
Figure 1 for the Timing Diagram and Table I for the Latch
Truth Table.
Figure 35 shows the interface between the ADF4110 family and
the ADSP-21xx Digital Signal Processor. The ADF4110 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
Autobuffered Transmit Mode of operation with Alternate
Framing. This provides a means for transmitting an entire
block of serial data before an interrupt is generated.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz or
one update every 1.2 microseconds. This is certainly more than
adequate for systems that will have typical lock times in hundreds
of microseconds.
SCLK
SCLK
DT
SDATA
ADSP-21xx
ADF4110
ADF4111
ADF4112
ADF4113
TFS
LE
ADuC812 Interface
CE
I/O FLAGS
Figure 34 shows the interface between the ADF4110 family and
the ADuC812 microconverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4110 family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the microconverter to the device. When the third
byte has been written the LE input should be brought high to
complete the transfer.
MUXOUT
(LOCK DETECT)
Figure 35. ADSP-21xx to ADF4110 Family Interface
Set up the word length for 8 bits and use three memory loca-
tions for each 24-bit word. To program each 24-bit latch, store
the three 8-bit bytes, enable the Autobuffered mode and then
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
On first applying power to the ADF4110 family, it needs three
writes (one each to the R counter latch, the N counter latch and
the initialization latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be
166 kHz.
SCLK
SDATA
LE
SCLOCK
MOSI
ADuC812
ADF4110
ADF4111
ADF4112
ADF4113
I/O PORTS
CE
MUXOUT
(LOCK DETECT)
Figure 34. ADuC812 to ADF4110 Family Interface
–23–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Chip Scale
(CP-20)
0.159 (4.05)
0.157 (4.00)
0.156 (3.95)
0.079 (2.0) REF
0.014 (0.35)
؋
45° 0.018 (0.45)
0.016 (0.40)
0.014 (0.35)
16
20
15
1
0.159 (4.05)
0.157 (4.00)
0.156 (3.95)
0.079
(2.0)
REF
DETAIL E
TOP VIEW
0.020 (0.5) REF
LEAD PITCH
11
10
5
6
0.039 (1.00)
0.035 (0.90)
0.031 (0.80)
BOTTOM VIEW
(ROTATED 180؇)
0.0083 (0.211)
0.0079 (0.200)
0.0077 (0.195)
0.0079 (0.20)
REF
SEATING
PLANE
LEAD OPTION
DETAIL E
0.011 (0.275)
0.010 (0.250)
0.009 (0.225)
0.018 (0.45)
0.016 (0.40)
0.014 (0.35)
0.0059
(0.15)
REF
0.0059 (0.15)
REF
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
Thin Shrink Small Outline
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0؇
0.0256 (0.65) 0.0118 (0.30)
0.028 (0.70)
0.020 (0.50)
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
BSC
0.0075 (0.19)
–24–
REV. 0
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