ADF4116_15_技术文档

RF PLL Frequency Synthesizers

ADF4116/ADF4117/ADF4118

GENERAL DESCRIPTION

FEATURES

ADF4116: 550 MHz

ADF4117: 1.2 GHz

ADF4118: 3.0 GHz

The ADF411x family of frequency synthesizers can be used to

implement local oscillators (LO) in the upconversion and

downconversion sections of wireless receivers and transmitters.

They consist of a low noise digital phase frequency detector

(PFD), a precision charge pump, a programmable reference

divider, programmable A and B counters, and a dual-modulus

prescaler (P/P + 1). The A (5-bit) and B (13-bit) counters, in

conjunction with the dual-modulus prescaler (P/P + 1),

implement an N divider (N = BP + A). In addition, the 14-bit

reference counter (R counter) allows selectable REF_INfrequencies

at the PFD input. A complete phase-locked loop (PLL) can be

implemented if the synthesizer is used with an external loop

filter and voltage controlled oscillator (VCO).

2.7 V to 5.5 V power supply

Separate V_Pallows extended tuning voltage in 3 V systems

Y Grade: −40°C to +125°C

Dual-modulus prescaler

ADF4116: 8/9

ADF4117/ADF4118: 32/33

3-wire serial interface

Digital lock detect

Power-down mode

Fastlock mode

APPLICATIONS

All of the on-chip registers are controlled via a simple 3-wire

interface. The devices operate with a power supply ranging

from 2.7 V to 5.5 V and can be powered down when not in use.

Base stations for wireless radio

(GSM, PCS, DCS, CDMA, WCDMA)

Wireless handsets

(GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANs

Communications test equipment

CATV equipment

FUNCTIONAL BLOCK DIAGRAM

AV

DV

V

P

CPGND

DD

REFERENCE

ADF4116/ADF4117/ADF4118

14-BIT

R COUNTER

REF

IN

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

CP

14

R COUNTER

LATCH

CLK

DATA

LE

21-BIT

INPUT REGISTER

FUNCTION

LATCH

LOCK

DETECT

19

A, B COUNTER

LATCH

SD

OUT

18

HIGH Z

FROM

FUNCTION LATCH

AV

DD

13

MUX

MUXOUT

N = BP + A

13-BIT

B COUNTER

SD

OUT

RF

A

B

IN

LOAD

PRESCALER

P/P + 1

IN

5-BIT

A COUNTER

M3 M2 M1

FL

SWITCH

O

FL

O

5

CE

AGND

DGND

Figure 1.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

ADF4116/ADF4117/ADF4118

TABLE OF CONTENTS

Features .............................................................................................. 1

Latch Summaries........................................................................ 14

Latch Maps .................................................................................. 15

Function Latch................................................................................ 19

Counter Reset ............................................................................. 19

Power-Down ............................................................................... 19

MUXOUT Control..................................................................... 19

Phase Detector Polarity ............................................................. 19

Charge Pump Three-State......................................................... 19

Fastlock Enable Bit..................................................................... 19

Fastlock Mode Bit....................................................................... 19

Timer Counter Control ............................................................. 19

Initialization Latch ..................................................................... 20

Device Programming After Initial Power-Up ........................ 20

Applications Information.............................................................. 21

Local Oscillator for the GSM Base Station Transmitter........ 21

Shutdown Circuit ....................................................................... 21

Direct Conversion Modulator .................................................. 21

Interfacing ................................................................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 12

Reference Input Section............................................................. 12

RF Input Stage............................................................................. 12

Prescaler (P/P + 1)...................................................................... 12

A Counter and B Counter ......................................................... 12

R Counter .................................................................................... 12

Phase Frequency Detector (PFD) and Charge Pump............ 13

MUXOUT and Lock Detect...................................................... 13

Input Shift Register..................................................................... 13

REVISION HISTORY

9/04—Rev. A to Rev. B

4/07—Rev. C to Rev. D

Changes to Specifications.................................................................3

Changes to Ordering Guide.......................................................... 25

Changes to REF_INCharacteristics Section..................................... 3

Changes to Table 4............................................................................ 7

Changes to Figure 35...................................................................... 22

Changes to Ordering Guide .......................................................... 25

3/01—Rev. 0 to Rev. A

4/00—Rev. 0: Initial Version

11/05—Rev. B to Rev. C

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 5

Changes to Table 3............................................................................ 6

Changes to Table 4............................................................................ 7

Changed OSC 3B1-13M0 to FOX801BH-130............................ 21

Changes to Ordering Guide .......................................................... 25

Rev. D | Page 2 of 28

ADF4116/ADF4117/ADF4118

SPECIFICATIONS

AV_DD= DV_DD= 3 V 10ꢀ, 5 V 10ꢀꢁ AV_DD≤ V_P≤ 6.0 Vꢁ AGND = DGND = CPGND = 0 Vꢁ T_A= T_MINto T_MAX, unless otherwise

notedꢁ dBm referred to 50 Ω.

Table 1.

Parameter

B Version¹

Y Version²Unit

Test Conditions/Comments

RF CHARACTERISTICS

RF Input Sensitivity

−15 to 0

−10 to 0

dBm min to max

AV_DD= 3 V

AV_DD= 5 V

RF Input Frequency

ADF4116

See Figure 26 for input circuit

80 to 550

45 to 550

MHz min to max

Input level = −8 dBm; for lower frequencies,

ensure slew rate (SR) > 36 V/μs

ADF4117

ADF4118

0.1 to 1.2

0.1 to 3.0

0.2 to 3.0

165

GHz min to max

MHz max

0.1 to 3.0

Input level = −10 dBm

Input level = −15 dBm

AV_DD, DV_DD= 3 V

Maximum Allowable Prescaler

Output Frequency³

165

200

MHz max

AV_DD, DV_DD= 5 V

REF_INCHARACTERISTICS

Reference Input Frequency

Reference Input Sensitivity^4,5

5 to 100

0.4 to AV_DD

0.7 to AV_DD

10

5 to 100

MHz min to max

For f < 5 MHz, ensure SR > 100 V/μs

0.4 to AV_DDV p-p min to max AV_DD= 3.3 V, biased at AV_DD/2

0.7 to AV_DDV p-p min to max For f ≥ 10 MHz, AV_DD= 5 V, biased at AV_DD/2

10

100

REF_INInput Capacitance

REF_INInput Current

PHASE DETECTOR FREQUENCY⁵

CHARGE PUMP

pF max

μA max

MHz max

100

55

I_CPSink/Source

High Value

Low Value

Absolute Accuracy

I_CPThree-State Leakage Current

1

mA typ

μA typ

% typ

nA max

nA typ

% typ

250

2.5

3

1

3

250

2.5

25

16

3

Sink and Source Current Matching

I_CPvs. V_CP

0.5 V ≤ V_CP≤ V_P− 0.5

V_CP= V_P/2

2

% typ

I_CPvs. Temperature

2

% typ

LOGIC INPUTS

V_INH, Input High Voltage

V_INL, Input Low Voltage

I_INH/I_INL, Input Current

C_IN, Input Capacitance

Reference Input Current

LOGIC OUTPUTS

0.8 × DV_DD

0.2 × DV_DD

1

10

0.8 × DV_DD

0.2 × DV_DD

1

10

100

V min

V max

μA max

pF max

μA max

100

V_OH, Output High Voltage

V_OL, Output Low Voltage

DV_DD− 0.4

0.4

DV_DD− 0.4

0.4

V min

V max

I_OH= 500 μA

I_OL= 500 μA

Rev. D | Page 3 of 28

ADF4116/ADF4117/ADF4118

Parameter

B Version¹

Y Version²Unit

Test Conditions/Comments

POWER SUPPLIES

AV_DD

DV_DD

2.7 to 5.5

AV_DD

2.7 to 5.5

AV_DD

V min to V max

V_P

AV_DDto 6.0

AV_DDto 6.0 V min to V max

AV_DD≤ V_P≤ 6.0 V

I_DD(AI_DD+ DI_DD)⁶

ADF4116

ADF4117

ADF4118

5.5

7.5

0.4

1

mA max

μA typ

4.5 mA typical

6.5 mA typical

T_A= 25°C

7.5

0.4

1

I_P

Low-Power Sleep Mode

NOISE CHARACTERISTICS

ADF4118 Normalized Phase Noise

−213

dBc/Hz typ

Floor⁷

Phase Noise Performance⁸

ADF4116 540 MHz Output⁹

ADF4117 900 MHz Output¹⁰

ADF4118 900 MHz Output¹⁰

ADF4117 836 MHz Output¹¹

ADF4118 1750 MHz Output¹²

ADF4118 1750 MHz Output¹³

ADF4118 1960 MHz Output¹⁴

Spurious Signals

@ VCO output

−89

−87

−90

−78

−85

−65

−84

−89

−87

−90

−78

−85

−65

−84

dBc/Hz typ

@ 1 kHz offset and 200 kHz PFD frequency

@ 300 Hz offset and 30 kHz PFD frequency

@ 1 kHz offset and 200 kHz PFD frequency

@ 200 Hz offset and 10 kHz PFD frequency

@ 1 kHz offset and 200 kHz PFD frequency

ADF4116 540 MHz Output¹⁰

ADF4117 900 MHz Output¹⁰

ADF4118 900 MHz Output¹⁰

ADF4117 836 MHz Output¹¹

ADF4118 1750 MHz Output¹²

ADF4118 1750 MHz Output¹³

ADF4118 1960 MHz Output¹⁴

−88/−99

−90/−104

−91/−100

−80/−84

−88/−90

−65/−73

−80/−86

−88/−99

−90/−104

−91/−100

−80/−84

−88/−90

−65/−73

−80/−86

dBc typ

@ 200 kHz/400 kHz and 200 kHz PFD frequency

@ 30 kHz/60 kHz and 30 kHz PFD frequency

@ 200 kHz/400 kHz and 200 kHz PFD frequency

@ 10 kHz/20 kHz and 10 kHz PFD frequency

@ 200 kHz/400 kHz and 200 kHz PFD frequency

¹Operating temperature range for the B version is −40°C to +85°C.

²Operating temperature range for the Y version is −40°C to +125°C.

³This is the maximum operating frequency of the CMOS counters.

⁴AC coupling ensures AV_DD/2 bias. See Figure 35 for typical circuit.

⁵Guaranteed by design.

⁶T_A= 25°C; AV_DD= DV_DD= 3 V; RF_INfor ADF4116 = 540 MHz; RF_INfor ADF4117, ADF4118 = 900 MHz.

⁷The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN_TOT, and subtracting 20logN (where N is the N

divider value) and 10logF_PFD: PN_SYNTH= PN_TOT– 10logF_PFD– 20logN.

⁸The phase noise is measured with the EVAL-ADF411xEB and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REF_INfor the synthesizer

(f_REFOUT= 10 MHz @ 0 dBm).

⁹f_REFIN= 10 MHz; f_PFD= 200 kHz; offset frequency = 1 kHz; f_RF= 540 MHz; N = 2700; loop bandwidth = 20 kHz.

10

f

= 10 MHz; f_PFD= 200 kHz; offset frequency = 1 kHz; f_RF= 900 MHz; N = 4500; loop bandwidth = 20 kHz.

= 10 MHz; f_PFD= 30 kHz; offset frequency = 300 Hz; f_RF= 836 MHz; N = 27867; loop bandwidth = 3 kHz.

= 10 MHz; f_PFD= 200 kHz; offset frequency = 1 kHz; f_RF= 1750 MHz; N = 8750; loop bandwidth = 20 kHz.

= 10 MHz; f_PFD= 10 kHz; offset frequency = 200 Hz; f_RF= 1750 MHz; N = 175000; loop bandwidth = 1 kHz.

= 10 MHz; f_PFD= 200 kHz; offset frequency = 1 kHz; f_RF= 1960 MHz; N = 9800; loop bandwidth = 20 kHz.

REFIN

11

12

13

14

Rev. D | Page 4 of 28

ADF4116/ADF4117/ADF4118

TIMING CHARACTERISTICS

AV_DD= DV_DD= 3 V 10ꢀ, 5 V 10ꢀꢁ AV_DD≤ V_P< 6.0 Vꢁ AGND = DGND = CPGND = 0 Vꢁ T_A= T_MINto T_MAX, unless otherwise noted.

Guaranteed by design, but not production tested.

Table 2.

Parameter

Limit at T_MINto T_MAX(B, Y Version)

Unit

Test Conditions/Comments

DATA to CLK setup time

DATA to CLK hold time

CLK high duration

CLK low duration

CLK to LE setup time

LE pulse width

t₁

t₂

t₃

t₄

t₅

t₆

10

25

10

20

ns min

t₃

t₄

CLK

t₁

t₂

DB1

DB0 (LSB)

(CONTROL BIT C1)

DB20 (MSB)

DB19

DB2

DATA

LE

(CONTROL BIT C2)

t₆

t₅

LE

Figure 2. Timing Diagram

Rev. D | Page 5 of 28

ADF4116/ADF4117/ADF4118

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating onlyꢁ functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

AV_DDto GND¹

Rating

−0.3 V to +7 V

−0.3 V to +0.3 V

−0.3 V to +7 V

−0.3 V to +5.5 V

−0.3 V to V_DD+ 0.3 V

−0.3 V to V_P+ 0.3 V

−0.3 V to V_DD+ 0.3 V

320 mV

AV_DDto DV_DD

V_Pto GND¹

V_Pto AV_DD

This device is a high performance RF integrated circuit with an

ESD rating of <2 kV, and it is ESD sensitive. Proper precautions

should be taken for handling and assembly.

Digital I/O Voltage to GND¹

Analog I/O Voltage to GND¹

REF_IN, RF_INA, RF_INB to GND¹

RF_INA to RF_INB

Operating Temperature Range

Industrial (B Version)

Extended (Y Version)

Storage Temperature Range

Maximum Junction Temperature

TSSOP θ_JAThermal Impedance

Reflow Soldering

ESD CAUTION

−40°C to +85°C

−40°C to +125°C

−65°C to +150°C

150°C

112°C/W

Peak Temperature

Time at Peak Temperature

Transistor Count

260°C

40 sec

CMOS

Bipolar

6425

303

¹GND = AGND = DGND = 0 V.

Rev. D | Page 6 of 28

ADF4116/ADF4117/ADF4118

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

FL

V

O

P

CP

CPGND

AGND

DV

DD

ADF4116/

ADF4117/

ADF4118

TOP VIEW

(Not to Scale)

MUXOUT

LE

RF

B

A

DATA

CLK

IN

AV

CE

DD

REF

DGND

IN

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

FL_O

Fast Lock Switch Output. This can be used to switch an external resistor to change the loop filter bandwidth

and speed up locking the PLL.

2

CP

Charge Pump Output. When enabled, this provides the I_CPto the external loop filter, which in turn drives the

external VCO.

3

4

5

CPGND

AGND

RF_INB

Charge Pump Ground. This is the ground return path for the charge pump.

Analog Ground. This is the ground return path for the prescaler.

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small

bypass capacitor, typically 100 pF. See Figure 26.

6

7

RF_INA

AV_DD

Input to the RF Prescaler. This small signal input is ac-coupled from the VCO.

Analog Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to this pin. AV_DDmust have the same value as DV_DD.

8

REF_IN

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and an equivalent input resistance of 100 kΩ.

See Figure 25. The oscillator input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

9

10

DGND

CE

Digital Ground.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state

mode. Taking the pin high powers up the device depending on the status of the power-down bit F2.

11

12

13

14

15

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a high

impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches, the latch being selected using the control bits.

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be

accessed externally.

Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane (1 μF, 1 nF)

should be placed as close as possible to this pin. For best performance, the 1 μF capacitor should be placed within 2 mm

of the pin. The placing of the 1 nF capacitor is less critical, but should still be within 5 mm of the pin.

DV_DDmust have the same value as AV_DD.

DATA

LE

MUXOUT

DV_DD

16

V_P

Charge Pump Power Supply. This should be greater than or equal to V_DD. In systems where V_DDis 3 V, this supply can

be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.

Rev. D | Page 7 of 28

ADF4116/ADF4117/ADF4118

TYPICAL PERFORMANCE CHARACTERISTICS

10dB/DIVISION

–40

R

= –40dBc/Hz

RMS NOISE = 0.64°

L

FREQ- PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCE-

UNIT

OHMS

–50

–60

GHz

S

MA

R

50

0.64° rms

FREQ

MagS11

AngS11

FREQ MagS11 AngS11

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.89207

0.8886

–2.0571

–4.4427

–6.3212

–2.1393

–12.13

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

0.92087

0.93788

0.9512

–36.961

–39.343

–40.134

–43.747

–44.393

–46.937

–49.6

–51.884

–51.21

–53.55

–56.786

–58.781

–60.545

–61.43

–61.241

–64.051

–66.19

–70

0.89022

0.96323

0.90566

0.90307

0.89318

0.89806

0.89565

0.88538

0.89699

0.89927

0.87797

0.90765

0.88526

0.81267

0.90357

0.92954

–80

0.93458

0.94782

0.96875

0.92216

0.93755

0.96178

0.94354

0.95189

0.97647

0.98619

0.95459

0.97945

0.98864

0.97399

0.97216

–13.52

–90

–15.746

–18.056

–19.693

–22.246

–24.336

–25.948

–28.457

–29.735

–31.879

–32.681

–31.522

–34.222

–100

–110

–120

–130

–140

100Hz

FREQUENCY OFFSET FROM 900MHz CARRIER

1MHz

–63.775

Figure 4. S-Parameter Data for the ADF4118 RF Input (Up to 1.8 GHz)

Figure 7. ADF4118 Integrated Phase Noise

(900 MHz, 200 kHz, 35 kHz, Typical Lock Time: 200 μs)

0

10dB/DIVISION

–40

R

= –40dBc/Hz

RMS NOISE = 0.575°

L

–5

V

= 3V

DD

–50

–60

P

0.575° rms

–10

–15

–20

–25

–70

–80

–90

T

= –40°C

= +25°C

A

–100

–30

–35

–110

–120

–130

T

= +85°C

3.5

A

–40

–45

0

0.5

1.0

1.5

2.0

2.5

3.0

4.0

–140

100Hz

FREQUENCY OFFSET FROM 900MHz CARRIER

1MHz

RF INPUT FREQUENCY (GHz)

Figure 5. Input Sensitivity (ADF4118)

Figure 8. ADF4118 Integrated Phase Noise

(900 MHz, 200 kHz, 20 kHz, Typical Lock Time: 400 μs)

0

–10

–20

–30

–40

–50

0

REFERENCE

LEVEL = –3.8dBm

V

I

= 3V, V = 5V

P

REFERENCE

LEVEL = –4.2dBm

V

I

= 3V, V = 5V

P

DD

–10

–20

–30

–40

–50

= 1mA

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 4

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 22

–60

–70

–60

–70

–90.2dBc/Hz

–91.5dBc

–80

–90

–100

–400kHz

–200kHz

900MHz

200kHz

400kHz

–2kHz

–1kHz

900MHz

1kHz

2kHz

Figure 9. ADF4118 Reference Spurs

(900 MHz, 200 kHz, 20 kHz)

Figure 6. ADF4118 Phase Noise

(900 MHz, 200 kHz, 20 kHz)

Rev. D | Page 8 of 28

ADF4116/ADF4117/ADF4118

0

–10

–20

–30

–40

–50

V

I

= 3V, V = 5V

P

V

I

= 3V, V = 5V

P

DD

REFERENCE

LEVEL = –4.2dBm

REFERENCE

LEVEL = –7.0dBm

–10

–20

–30

–40

–50

= 5mA

= 1mA

CP

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 5kHz

RES. BANDWIDTH = 300Hz

VIDEO BANDWIDTH = 300Hz

SWEEP = 4.2ms

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 35kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 10

AVERAGES = 20

–60

–70

–60

–70

–72.3dBc

–90.67dBc

–80

–90

–80

–90

–100

–400kHz

–200kHz

900MHz

200kHz

400kHz

–60kHz

–30kHz

1750MHz

30kHz

60kHz

Figure 10. ADF4118 Reference Spurs

(900 MHz, 200 kHz, 35 kHz)

Figure 13. ADF4118 Reference Spurs

(1750 MHz, 30 kHz, 3 kHz)

0

–10

–20

–30

–40

–50

0

V

= 3V, V = 5V

P

DD

REFERENCE

LEVEL = –7.0dBm

V

= 3V, V = 5V

DD P

REFERENCE

LEVEL = –10.3dBm

I

= 1mA

CP

–10

–20

–30

–40

I

= 1mA

CP

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 5kHz

RES. BANDWIDTH = 10kHz

VIDEO BANDWIDTH = 10kHz

SWEEP = 477ms

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 26

–50

AVERAGES = 25

–60

–70

–60

–70

–85.2dBc/Hz

–71.5dBc/Hz

–80

–90

–100

–400kHz

–200kHz

1750MHz

200kHz

400kHz

–2kHz

–1kHz

1kHz

2kHz

2800MHz

Figure 11. ADF4118 Phase Noise

(1750 MHz, 30 kHz, 3 kHz)

Figure 14. ADF4118 Phase Noise

(2800 MHz, 1 MHz, 100 kHz)

10dB/DIVISION

–40

R

= –40dBc/Hz

RMS NOISE = 2.0°

10dB/DIVISION

–40

R

= –40dBc/Hz

RMS NOISE = 1.552°

L

–50

–60

–50

–60

1.55° rms

2.0° rms

–70

–80

–70

–80

–90

–100

–110

–120

–130

–110

–120

–130

–140

100Hz

–140

100Hz

FREQUENCY OFFSET FROM 1.75GHz CARRIER

1MHz

FREQUENCY OFFSET FROM 2.8GHz CARRIER

1MHz

Figure 15. ADF4118 Integrated Phase Noise

(2800 MHz, 1 MHz, 100 kHz)

Figure 12. ADF4118 Integrated Phase Noise

(1750 MHz, 30 kHz, 3 kHz)

Rev. D | Page 9 of 28

ADF4116/ADF4117/ADF4118

0

–60

–70

V

I

= 3V, V = 5V

P

DD

REFERENCE

LEVEL = –9.3dBm

–10

–20

–30

–40

–50

= 1mA

V

= 3V

CP

DD

= 5V

P

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 3kHz

VIDEO BANDWIDTH = 3kHz

SWEEP = 1.4 SECONDS

AVERAGES = 4

–80

–60

–70

–77.3dBc

–90

–80

–90

–100

–40

–20

0

20

40

60

80

100

–2MHz

–1MHz

2800MHz

1MHz

2MHz

TEMPERATURE (°C)

Figure 16. ADF4118 Reference Spurs

(2800 MHz, 1 MHz, 100 kHz)

Figure 19. ADF4118 Reference Spurs vs. Temperature

(900 MHz, 200 kHz, 20 kHz)

–130

–135

–140

–145

–150

–155

–160

–165

–170

–175

5

–5

V

= 3V

DD

= 5V

V

= 3V

DD

= 5V

P

–15

–25

–35

–45

–55

–65

–75

–85

–95

–105

0

1

2

3

4

5

1

10

100

1000

10000

PHASE DETECTOR FREQUENCY (kHz)

TUNING VOLTAGE

Figure 17. ADF4118 Phase Noise (Referred to CP Output) vs.

PFD Frequency

Figure 20. ADF4118 Reference Spurs (200 kHz) vs. V_TUNE

(900 MHz, 200 kHz, 20 kHz)

–60

–70

–80

–90

V

= 3V

DD

= 5V

V

= 3V

P

DD

= 5V

P

–70

–80

–90

–100

0

20

40

60

80

100

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 18. ADF4118 Phase Noise vs. Temperature

(900 MHz, 200 kHz, 20 kHz)

Figure 21. ADF4118 Phase Noise vs. Temperature

(836 MHz, 30 kHz, 3 kHz)

Rev. D | Page 10 of 28

ADF4116/ADF4117/ADF4118

–60

–70

1.2

1.0

0.8

0.6

V

= 3V

DD

= 5V

V

= 5V

SETTING: 1mA

P

I

CP

0.4

0.2

–80

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–90

–100

0

20

40

60

80

100

0

0.5

1.0

1.5

2.0

2.5

(V)

3.0

3.5

4.0

4.5

5.0

TEMPERATURE (°C)

V

CP

Figure 22. ADF4118 Reference Spurs vs. Temperature

(836 MHz, 30 kHz, 3 kHz)

Figure 24. Charge Pump Output Characteristics

3.0

2.5

2.0

1.5

1.0

0.5

0

50

100

150

200

PRESCALER OUTPUT FREQUENCY (MHz)

Figure 23. DI_DDvs. Prescaler Output Frequency

Rev. D | Page 11 of 28

ADF4116/ADF4117/ADF4118

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

A COUNTER AND B COUNTER

The A CMOS counter and B CMOS counter combine with the

dual-modulus prescaler to allow a wide ranging division ratio in

the PLL feedback counter. The counters are specified to work

when the prescaler output is 200 MHz or less.

The reference input stage is shown in Figure 25. SW1 and SW2

are normally closed switchesꢁ SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REF_INpin

on power-down.

Pulse Swallow Function

POWER-DOWN

CONTROL

The A counter and B counter, in conjunction with the dual-

modulus prescaler, make it possible to generate output

frequencies that are spaced only by the reference frequency

divided by R. The equation for the VCO frequency is as follows:

100kΩ

NC

SW2

TO R COUNTER

REF

IN

NC

SW1

BUFFER

f_VCO

where:

_VCOis the output frequency of external voltage controlled

=

(P×B)+ A × f_REFIN/R

[ ]

SW3

NO

Figure 25. Reference Input Stage

f

oscillator (VCO).

RF INPUT STAGE

P is the preset modulus of dual-modulus prescaler.

B is the preset divide ratio of binary 13-bit counter (3 to 8191).

A is the preset divide ratio of binary 5-bit swallow counter (0 to 31).

The RF input stage is shown in Figure 26. It is followed by a

2-stage limiting amplifier to generate the CML clock levels

needed for the prescaler.

f

_REFINis the output frequency of the external reference frequency

oscillator.

1.6V

BIAS

GENERATOR

AV

DD

R is the preset divide ratio of binary 14-bit programmable

reference counter (1 to 16,383).

500Ω

R COUNTER

RF

A

B

IN

The 14-bit R counter allows the input reference frequency to be

divided down to produce the input clock to the phase frequency

detector (PFD). Division ratios from 1 to 16,383 are allowed.

IN

AGND

N = BP + A

TO PFD

13-BIT

Figure 26. RF Input Stage

B COUNTER

FROM RF

PRESCALER (P/P + 1)

LOAD

INPUT STAGE

PRESCALER

P/P + 1

The dual-modulus prescaler (P/P + 1), along with the A counter

and B counter, enables the large division ratio, N, to be realized

(N = PB + A). The dual-modulus prescaler takes the CML clock

from the RF input stage and divides it down to a manageable

frequency for the CMOS A counter and CMOS B counter. The

prescaler is programmable. It can be set in software to 8/9 for the

ADF4116 and to 32/33 for the ADF4117 and ADF4118. It is based

on a synchronous 4/5 core.

MODULUS

CONTROL

5-BIT

A COUNTER

Figure 27. A Counter and B Counter

Rev. D | Page 12 of 28

ADF4116/ADF4117/ADF4118

PHASE FREQUENCY DETECTOR (PFD)

AND CHARGE PUMP

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF411x family allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 in the function

latch. Figure 33 shows the full truth table. Figure 29 shows the

MUXOUT section in block diagram form.

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 28 is a simplified schematic of

the PFD. The PFD includes a fixed delay element that sets the

width of the antibacklash pulse. This is typically 3 ns. This pulse

ensures that there is no dead zone in the PFD transfer function

and gives a consistent reference spur level.

DV

DD

V

P

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

CHARGE

PUMP

MUXOUT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

MUX

CONTROL

UP

HI

D1

Q1

U1

R DIVIDER

CLR1

DGND

Figure 29. MUXOUT Circuit

CP

DELAY

DOWN

U3

Lock Detect

MUXOUT can be programmed for both digital lock detect and

analog lock detect.

CLR2

U2

Digital lock detect is active high. It is set high when the phase

error on three consecutive phase detector cycles is less than

15 ns. It stays set high until a phase error greater than 25 ns is

detected on any subsequent PD cycle.

D2

Q2

HI

N DIVIDER

CPGND

The N channel, open-drain, analog lock detect should be

operated with an external pull-up resistor of 10 kΩ nominal.

When lock is detected, it is high with narrow low going pulses.

R DIVIDER

N DIVIDER

INPUT SHIFT REGISTER

CP OUTPUT

The ADF411x family digital section includes a 21-bit input shift

register, a 14-bit R counter, and an 18-bit N counter, comprising

a 5-bit A counter and a 13-bit B counter. Data is clocked into

the 21-bit shift register on each rising edge of CLK. The data is

clocked in MSB first. Data is transferred from the shift register

to one of four latches on the rising edge of LE. The destination

latch is determined by the state of the two control bits (C2, C1)

in the shift register. These are the two LSBs, DB1 and DB0, as

shown in the timing diagram in Figure 2. The truth table for

these bits is shown in Figure 34. Table 5 summarizes how the

latches are programmed.

Figure 28. PFD Simplified Schematic and Timing (In Lock)

Table 5. Programming Data Latches

Control Bits

C2

0

C1

0

Data Latch

R Counter

0

1

0

1

N Counter (A and B)

Function Latch

Initialization Latch

Rev. D | Page 13 of 28

ADF4116/ADF4117/ADF4118

LATCH SUMMARIES

REFERENCE COUNTER LATCH

TEST

MODE BITS

CONTROL

BITS

14-BIT REFERENCE COUNTER, R

DB20

LDP

DB19 DB18 DB17 DB16 DB15 DB14

T4 T3 T2 T1 R14 R13

DB13

R12

DB12 DB11 DB10

R11 R10 R9

DB9

R8

DB8

R7

DB7

R6

DB6

R5

DB5

R4

DB4

R3

DB3

R2

DB2

R1

DB1

DB0

C2 (0) C1 (0)

AB COUNTER LATCH

CONTROL

BITS

13-BIT B COUNTER

5-BIT A COUNTER

DB20 DB19 DB18

G1 B13 B12

DB17 DB16 DB15 DB14 DB13 DB12

DB11 DB10

B5 B4

DB9

B3

DB8

B2

DB7

B1

DB6

A5

DB5

DB4

A3

DB3

DB2

A1

DB1

DB0

B11

B10

B9

B8

B7

B6

A4

A2

C2 (0) C1 (1)

FUNCTION LATCH

TIMER COUNTER

CONTROL

MUXOUT

CONTROL

BITS

RESERVED

DB20 DB19

PD2

DB18 DB17 DB16 DB15 DB14

DB13 DB12

DB11 DB10

F6

DB9

F4

DB8

F3

DB7

F2

DB6

M3

DB5

M2

DB4

M1

DB3

PD1

DB2

F1

DB1

DB0

X

TC4

TC3

TC2

TC1

X

C2 (1) C1 (0)

INITIALIZATION LATCH

TIMER COUNTER

CONTROL

MUXOUT

CONTROL

BITS

RESERVED

DB20 DB19

DB18 DB17 DB16 DB15 DB14 DB13 DB12

DB11 DB10

F6

DB9

F4

DB8

F3

DB7

F2

DB6

M3

DB5

M2

DB4

M1

DB3

PD1

DB2

F1

DB1

DB0

X

PD2

TC4

TC3

TC2

TC1

X

C2 (1) C1 (1)

Figure 30. ADF411x family Latch Summary

Rev. D | Page 14 of 28

ADF4116/ADF4117/ADF4118

LATCH MAPS

TEST

MODE BITS

CONTROL

BITS

14-BIT REFERENCE COUNTER, R

DB20 DB19 DB18 DB17

LDP T4 T3 T2

DB16 DB15 DB14 DB13 DB12

T1 R14 R13 R12 R11

DB11 DB10

DB9

R8

DB8

R7

DB7

R6

DB6

R5

DB5

R4

DB4

R3

DB3

R2

DB2

R1

DB1

DB0

R10

R9

C2 (0) C1 (0)

R14

0

R13

0

R12

0

••••••••••

R3

R2

0

R1

1

DIVIDE RATIO

1

0

1

•

0

•

0

•

0

•

••••••••••

1

0

•

0

1

0

•

2

3

4

•

1

0

1

0

1

0

1

163 80

163 81

163 82

163 83

TEST MODE BITS SHOULD

BE SET TO 0000 FOR

NORMAL OPERATION

LDP

OPERATION

3 CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

5 CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

0

1

Figure 31. Reference Counter Latch Map

Rev. D | Page 15 of 28

ADF4116/ADF4117/ADF4118

CONTROL

BITS

13-BIT B COUNTER

5-BIT A COUNTER

DB20

G1

DB19 DB18

B13 B12

DB17 DB16 DB15 DB14

DB13 DB12

B7 B6

DB11 DB10

DB9

B3

DB8

B2

DB7

B1

DB6

A5

DB5

A4

DB4

A3

DB3

DB2

A1

DB1

DB0

B11

B10

B9

B8

B5

B4

A2

C2 (0) C1 (1)

A COUNTER

DIVIDE RATIO

A5

A4

X

•

A3

A2

A1

0

1

•

X

•

0

•

0

•

0

1

•

ADF4116

•

X

1

0

1

6

7

A COUNTER

DIVIDE RATIO

A5

0

•

A4

0

•

A3

0

•

A2

0

1

•

A1

0

1

0

•

0

1

ADF4117/ADF4118

2

•

1

0

1

0

1

29

30

31

••••••••••

B13

B12

0

B11

0

B3

0

B2

0

B1

1

B COUNTER DIVIDE RATIO

NOT ALLOWED

0

•

0

•

0

•

••••••••••

0

1

•

1

0

•

0

1

0

•

NOT ALLOWED

3

4

•

1

0

1

0

1

0

1

8188

8189

8190

8191

LDP CURRENT SETTINGS

250µA

1mA

0

1

N = BP + A, P IS PRESCALER VALUE. B MUST BE GREATER

THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT

2

VALUES OF N

F

, N

IS (P – P).

MIN

X

REF

Figure 32. A Counter/B Counter Latch Map

Rev. D | Page 16 of 28

ADF4116/ADF4117/ADF4118

TIMER COUNTER

CONTROL

MUXOUT

CONTROL

BITS

RESERVED

DB20

X

DB19 DB18

PD2

DB17 DB16 DB15 DB14

DB13 DB12 DB11 DB10

DB9

F4

DB8

F3

DB7

F2

DB6

M3

DB5

M2

DB4

M1

DB3

PD1

DB2

F1

DB1

DB0

X

TC4

TC3

TC2

TC1

F6

X

C2 (1) C1 (0)

COUNTER

OPERATION

F1

0

NORMAL

R, A, B COUNTERS

HELD IN RESET

1

CE PIN PD2 PD1

MODE

M3

M2

0

M1

OUTPUT

ASYNCHRONOUS POWER-DOWN

NORMAL OPERATION

0

1

X

0

1

X

0

1

0

THREE-STATE OUTPUT

DIGITAL LOCK DETECT

(ACTIVE HIGH)

ASYNCHRONOUS POWER-DOWN

SYNCHRONOUS POWER-DOWN

0

1

0

1

0

1

0

1

0

N DIVIDER OUTPUT

AV

DD

R DIVIDER OUTPUT

ANALOG LOCK DETECT

(N CHANNEL OPEN DRAIN)

1

0

1

SERIAL DATA OUTPUT

(INVERSE POLARITY OF

SERIAL DATA INPUT)

1

0

1

DGND

PHASE DETECTOR

POLARITY

F2

0

NEGATIVE

1

POSITIVE

CHARGE PUMP

OUTPUT

F3

0

NORMAL

1

THREE-STATE

F4

0

F6

X

FASTLOCK MODE

FASTLOCK DISABLED

FASTLOCK MODE 1

FASTLOCK MODE 2

TIMEOUT

1

0

1

TC4

TC3

TC2

TC1

(PFD CYCLES)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

7

11

15

19

23

27

31

35

39

43

47

51

55

59

63

Figure 33. Function Latch Map

Rev. D | Page 17 of 28

ADF4116/ADF4117/ADF4118

RESERVED

TIMER COUNTER

MUXOUT

CONTROL

BITS

CONTROL

DB20 DB19

DB18 DB17

DB16

X

DB15 DB14 DB13 DB12

DB11 DB10

F6

DB9

F4

DB8

F3

DB7

F2

DB6

M3

DB5

M2

DB4

M1

DB3

PD1

DB2

F1

DB1

DB0

X

PD2

TC4

TC3

TC2

TC1

X

C2 (1) C1 (1)

COUNTER

OPERATION

F1

0

1

NORMAL

R, A, B COUNTERS

HELD IN RESET

M3

M2

0

M1

OUTPUT

CE PIN PD2 PD1

MODE

0

THREE-STATE OUTPUT

ASYNCHRONOUS POWER-DOWN

NORMAL OPERATION

0

1

X

0

1

X

0

1

DIGITAL LOCK DETECT

(ACTIVE HIGH)

0

1

0

1

0

1

0

ASYNCHRONOUS POWER-DOWN

N DIVIDER OUTPUT

0

SYNCHRONOUS POWER-DOWN

AV

DD

0

1

R DIVIDER OUTPUT

ANALOG LOCK DETECT

(N CHANNEL OPEN DRAIN)

1

0

1

SERIAL DATA OUTPUT

(INVERSE POLARITY OF

SERIAL DATA INPUT)

1

0

1

DGND

PHASE DETECTOR

POLARITY

F2

0

NEGATIVE

1

POSITIVE

CHARGE PUMP

OUTPUT

F3

0

NORMAL

1

THREE-STATE

F4

0

F6

FASTLOCK MODE

FASTLOCK DISABLED

X

0

1

FASTLOCK MODE 1

FASTLOCK MODE 2

1

TIMEOUT

(PFD CYCLES)

TC4

TC3

TC2

TC1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

7

11

15

19

23

27

31

35

39

43

47

51

55

59

63

Figure 34. Initialization Latch Map

Rev. D | Page 18 of 28

ADF4116/ADF4117/ADF4118

FUNCTION LATCH

With C2 and C1 set to 1 and 0, respectively, the on-chip

function latch is programmed. Figure 33 shows the input data

format for programming the function latch.

CHARGE PUMP THREE-STATE

The DB8 (F3) bit puts the charge pump into three-state mode

when programmed to 1. It should be set to 0 for normal operation.

COUNTER RESET

FASTLOCK ENABLE BIT

DB2 (F1) is the counter reset bit. When this bit is set to 1, the R

counter, A counter, and B counter are reset. For normal operation,

this bit should be set to 0. On power-up, the F1 bit needs to be

disabled, for the N counter to resume counting in “close”

alignment with the R counter. (The maximum error is one

prescaler cycle.)

DB9 (F4) of the function latch is the fastlock enable bit. Fastlock

is enabled only when DB9 is set to 1.

FASTLOCK MODE BIT

DB11 (F6) of the function latch is the fastlock mode bit. When

fastlock is enabled, this bit determines which fastlock mode is

used. If the fastlock mode bit is 0, Fastlock Mode 1 is selectedꢁ if

the fastlock mode bit is 1, Fastlock Mode 2 is selected.

POWER-DOWN

DB3 (PD1) and DB19 (PD2) on the ADF411x family provide

programmable power-down modes. They are enabled by the

CE pin.

If fastlock is not enabled (DB9 = 0), DB11 (ADF4116)

determines the state of the FL_Ooutput. FL_Ostate is the same as

that programmed to DB11.

When the CE pin is low, the device is immediately disabled

regardless of the states of PD2 and PD1.

Fastlock Mode 1

In the ADF411x family, the output level of FL_Ois programmed

to a low state, and the charge pump current is switched to the

high value (1 mA). FL_Ois used to switch a resistor in the loop

filter and to ensure stability while in fastlock by altering the

loop bandwidth.

In programmed asynchronous power-down, the device powers

down immediately after latching a 1 into the PD1 bit, with the

condition that PD2 is loaded with a 0.

In programmed synchronous power-down, the device power-

down is gated by the charge pump to prevent unwanted

frequency jumps. Once power-down is enabled by writing a 1

into the PD1 bit (on condition that a 1 is also loaded to PD2),

the device goes into power-down after the first successive

charge pump event.

The device enters fastlock by having a 1 written to the CP Gain

bit in the N register. The device exits fastlock by having a 0

written to the CP Gain bit in the N register.

Fastlock Mode 2

In the ADF411x family, the output level of FL_Ois programmed

to a low state, and the charge pump current is switched to the

high value (1 mA). FL_Ois used to switch a resistor in the loop

filter and to ensure stability while in fastlock by altering the

loop bandwidth.

When a power-down is activated (either synchronous or

asynchronous mode including CE pin-activated power-down),

the following events occur:

•

All active dc current paths are removed.

The R counter, N counter, and timeout counter are forced

to their load state conditions.

The device enters fastlock by having a 1 written to the CP gain

bit in the N register. The device exits fastlock under the control

of the timer counter. After the timeout period determined by

the value in TC4 to TC1, the CP Gain bit in the N register is

automatically reset to 0, and the device reverts to normal mode

instead of fastlock.

•

The charge pump is forced into three-state mode.

The digital clock detect circuitry is reset.

The RF_INinput is debiased.

The oscillator input buffer circuitry is disabled.

TIMER COUNTER CONTROL

The input register remains active and capable of loading

and latching data.

In the ADF411x family, the user has the option of switching

between two charge pump current values to speed up locking to

a new frequency.

MUXOUT CONTROL

When using the fastlock feature with the ADF411x family, the

following should be noted:

The on-chip multiplexer is controlled by DB6 (M3), DB5 (M2),

and DB4 (M1) on the ADF411x family. Figure 33 shows the

truth table.

•

The user must make sure that fastlock is enabled. Set DB9

to 1. The user must also choose which fastlock mode to use.

PHASE DETECTOR POLARITY

DB7 (F2) of the function latch sets the phase detector polarity.

When the VCO characteristics are positive, DB7 should be set

to 1. When they are negative, it should be set to 0.

Rev. D | Page 19 of 28

ADF4116/ADF4117/ADF4118

4. Do an N load (01 in 2 LSBs).

•

Fastlock Mode 2 uses the values in the timer counter to

determine the timeout period before reverting to normal

mode operation after fastlock. Fastlock Mode 2 is chosen

by setting DB11 to 1.

When the initialization latch is loaded, the following occurs:

•

The function latch contents are loaded.

An internal pulse resets the R, N, and timeout counters to

load state conditions and also three-states the charge pump.

Note that the prescaler band gap reference and the oscillator

input buffer are unaffected by the internal reset pulse, allowing

close phase alignment when counting resumes.

•

The user must also decide how long to keep the high

current (1 mA) active before reverting to low current

(250 μA). This is controlled by the timer counter control

bits, DB14 to DB11 (TC4 to TC1), in the function latch.

The truth table is given in Figure 33.

•

Latching the first N counter data after the initialization

word activates the same internal reset pulse. Successive

N loads do not trigger the internal reset pulse unless there

is another initialization.

•

To program a new output frequency, program the A counter

and B counter latch with new values for A and B. At the

same time, set the CP Gain bit to a 1, which sets the charge

pump to 1 mA for a period of time determined by TC4 to

TC1. When this time is up, the charge pump current

reverts to 250 μA. At the same time, the CP Gain bit in the

A counter and B counter latch is reset to 0 and is ready for

the next time that the user wants to change the frequency.

CE Pin Method

1. Apply V_DD

.

2. Bring CE low to put the device into power-down. This is an

asynchronous power-down in that it happens immediately.

INITIALIZATION LATCH

3. Program the function latch (10).

When C2 and C1 are both set to 1, the initialization latch is

programmed. This is essentially the same as the function latch

that is programmed when C2, C1 = 1, 0.

4. Program the R counter latch (00).

5. Program the N counter latch (01).

6. Bring CE high to take the device out of power-down.

The R counter and N counter resume counting in close alignment.

However, when the initialization latch is programmed, an

additional internal reset pulse is applied to the R counter and

N counter. This pulse ensures that the N counter is at a load

point when the N counter data is latched and that the device

begins counting in close phase alignment.

Note that after CE goes high, a duration of 1 μs may be required

for the prescaler band gap voltage and oscillator input buffer

bias to reach a steady state.

If the latch is programmed for synchronous power-down (CE

pin is highꢁ PD1 bit is highꢁ PD2 bit is low), the internal pulse

also triggers this power-down. The prescaler reference and the

oscillator input buffer are unaffected by the internal reset pulse,

so close phase alignment is maintained when counting resumes.

CE can be used to power up and power down the device to check

for channel activity. The input register does not need to be repro-

grammed each time the device is disabled and enabled, as long

as it is programmed at least once after V_CCis initially applied.

Counter Reset Method

When the first N counter data is latched after initialization, the

internal reset pulse is again activated. However, successive

N counter loads do not trigger the internal reset pulse.

1. Apply V_DD

.

2. Do a function latch load (10 in 2 LSBs). As part of this,

load 1 to the F1 bit. This enables the counter reset.

DEVICE PROGRAMMING AFTER

INITIAL POWER-UP

3. Do an R counter load (00 in 2 LSBs).

4. Do an N counter load (01 in 2 LSBs).

After initial power-up, the device can be programmed by the

initialization latch method, the CE pin method, or the counter

reset method.

5. Do a function latch load (10 in 2 LSBs). As part of this,

load 0 to the F1 bit. This disables the counter reset.

Initialization Latch Method

This sequence provides the same close alignment as the initiali-

zation method. It offers direct control over the internal reset.

Note that counter reset holds the counters at load point and

three-states the charge pump, but it does not trigger synchro-

nous power-down. The counter reset method requires an extra

function latch load compared to the initialization latch method.

1. Apply V_DD

.

2. Program the initialization latch (11 in 2 LSBs of input

word). Make sure that F1 bit is programmed to 0.

3. Do an R load (00 in 2 LSBs).

Rev. D | Page 20 of 28

ADF4116/ADF4117/ADF4118

APPLICATIONS INFORMATION

LOCAL OSCILLATOR FOR THE

SHUTDOWN CIRCUIT

GSM BASE STATION TRANSMITTER

The attached circuit in Figure 36 shows how to shut down both

the ADF411x family and the accompanying VCO. The ADG702

switch goes open-circuit when a Logic 1 is applied to the IN

input. The low cost switch is available in both SOT-23 and

MSOP packages.

Figure 35 shows the ADF4117/ADF4118 being used with a

VCO to produce the LO for a GSM base station transmitter.

The reference input signal is applied to the circuit at F_REFINand,

in this case, is terminated in 50 Ω. A typical GSM system has a

13 MHz TCXO driving the reference input without a 50 Ω

termination. To have a channel spacing of 200 kHz (the GSM

standard), the reference input must be divided by 65, using the

on-chip reference divider of the ADF4117/ADF1118.

DIRECT CONVERSION MODULATOR

In some applications, a direct conversion architecture can be

used in base station transmitters. Figure 37 shows the

combination available from Analog Devices, Inc. to implement

this solution.

The charge pump output of the ADF4117/ADF1118 (Pin 2)

drives the loop filter. In calculating the loop filter component

values, a number of items need to be considered. In this example,

the loop filter was designed so that the overall phase margin for

the system is 45°. Other PLL system specifications include:

The circuit diagram shows the AD9761 being used with the

AD8346. The use of dual integrated DACs, such as the AD9761

with specified 0.02 dB and 0.004 dB gain and offset matching

characteristics, ensures minimum error contribution (over

temperature) from this portion of the signal chain.

K_D= 1 mA

K_V= 12 MHz/V

Loop bandwidth = 20 kHz

F_REF= 200 kHz

The local oscillator is implemented by using the ADF4117/

ADF4118. In this case, the FOX801BH-130 provides the stable

13 MHz reference frequency. The system is designed for

200 kHz channel spacing and an output center frequency of

1960 MHz. The target application is a WCDMA base station

transmitter. Typical phase noise performance from this LO is

−85 dBc/Hz at a 1 kHz offset. The LO port of the AD8346 is

driven in single-ended fashion. LOIN is ac-coupled to ground

with the 100 pF capacitor, and LOIP is driven through the ac-

coupling capacitor from a 50 Ω source. An LO drive level between

−6 dBm and −12 dBm is required. The circuit in Figure 37 gives a

typical level of −8 dBm.

N = 4500

Extra reference spur attenuation = 10 dB

All of these specifications are needed and are used to produce

the loop filter component values shown in Figure 36.

The loop filter output drives the VCO, which, in turn, is fed back

to the RF input of the PLL synthesizerꢁ it also drives the RF

output terminal. A T-circuit configuration provides 50 Ω

matching between the VCO output, the RF output, and the

RF_INterminal of the synthesizer.

The RF output is designed to drive a 50 Ω load, but it must be

ac-coupled as shown in Figure 37. If the I and Q inputs are

driven in quadrature by 2 V p-p signals, the resulting output

power is approximately −10 dBm.

In a PLL system, it is important to know when the system is in

locked mode. In Figure 35, this is accomplished by using the

MUXOUT signal from the synthesizer. The MUXOUT pin can

be programmed to monitor various internal signals in the

synthesizer. One of these is the LD or lock-detect signal.

Rev. D | Page 21 of 28

ADF4116/ADF4117/ADF4118

RF

OUT

V

DD

P

100pF

7

15 16

DV

AV

V

P

18Ω

DD

V

3.3kΩ

CC

2

1

100pF

18Ω

1000pF

8

CP

F

REF

REFIN

IN

VCO190-902T

620pF

18Ω

27kΩ

0.15nF

51Ω*

FL

O

ADF4117/

ADF4118

10kΩ

1.5nF

14

CE

LOCK

DETECT

MUXOUT

CLK

DATA

LE

100pF

6

5

RF

A

IN

51Ω**

B

IN

100pF

*TO BE USED WHEN GENERATOR SOURCE IMPEDANCE IS 50Ω.

**OPTIONAL MATCHING RESISTOR DEPENDING ON RF FREQUENCY.

3

4

9

OUT

DECOUPLING CAPACITORS ON AV , DV , AND V OF THE

DD DD

P

ADF4117/ADF4118 AND ON V OF THE VCO190-920T HAVE BEEN

CC

OMITTED FROM THE DIAGRAM FOR CLARITY.

Figure 35. Local Oscillator for GSM Base Station

V

P

POWER-DOWN CONTROL

S

V

DD

RF

OUT

IN

V

7

ADG702

GND

DD

D

100pF

15 16

18Ω

V

100pF

AV

DV

DD

V

CE

CC

18Ω

DD

P

2

1

LOOP

FILTER

8

CP

O

F

REF

REFIN

IN

VCO

FL

GND

10kΩ

ADF4116/

ADF4117/

ADF4118

100pF

6

5

RF

A

IN

51Ω

B

IN

100pF

3

4

9

DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE

BEEN OMITTED FROM THE DIAGRAM FOR CLARITY.

Figure 36. Local Oscillator Shutdown Circuit

Rev. D | Page 22 of 28

ADF4116/ADF4117/ADF4118

0.1µF

REFIO

IBBP

IOUTA

IOUTB

100pF

LOW-PASS

FILTER

RF

VOUT

OUT

MODULATED

DIGITAL

DATA

AD9761

TxDAC

AD8346

QBBP

QOUTA

QOUTB

LOW-PASS

FILTER

FS ADJ

2kΩ

LOIN

LOIP

100pF

FOX801BH-130

TCXO

18Ω

10kΩ

1kΩ

REF

IN

CP

VCO190-1960T

18pF

ADF4118

680pF

SERIAL

DIGITAL

INTERFACE

100pF

18Ω

6.8nF

18Ω

RF

B

RF A

IN

100pF

51Ω

POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS

ARE OMITTED FROM DIAGRAM FOR CLARITY.

Figure 37. Direct Conversion Transmitter Solution

Rev. D | Page 23 of 28

ADF4116/ADF4117/ADF4118

On first applying power to the ADF411x family, it requires three

writes (one each to the R counter latch, the N counter latch, and

the initialization latch) for the output to become active.

INTERFACING

The ADF411x family has a simple SPI®-compatible serial inter-

face for writing to the device. CLK, DATA, and LE control the

data transfer. When LE (latch enable) goes high, the 24 bits that

are clocked into the input register on each rising edge of CLK

are transferred to the appropriate latch. See Figure 2 for the

timing diagram and Table 5 for the latch truth table.

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and to detect lock (MUXOUT configured as

lock detect and polled by the port input).

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed is 166 kHz.

The maximum allowable serial clock rate is 20 MHz. This means

that the maximum update rate possible for the device is 833 kHz

or one update every 1.2 μs. This is more than adequate for

systems that have typical lock times in hundreds of microseconds.

ADSP-21xx Interface

Figure 39 shows the interface between the ADF411x family and

the ADSP-21xx digital signal processor. The ADF411x family

needs a 21-bit serial word for each latch write. The easiest way

to accomplish this using the ADSP-21xx family is to use the

autobuffered transmit mode of operation with alternate framing.

This provides a means for transmitting an entire block of serial

data before an interrupt is generated.

ADuC812 Interface

Figure 38 shows the interface between the ADF411x family and

the ADuC812 MicroConverter®. Since the ADuC812 is based

on an 8051 core, this interface can be used with any 8051-based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF411x family

needs a 24-bit word. This is accomplished by writing three 8-bit

bytes from the MicroConverter to the device. When the third

byte has been written, the LE input should be brought high to

complete the transfer.

CLK

SCLK

DT

DATA

ADSP-21xx

ADF4116/

ADF4117/

ADF4118

TFS

LE

CE

I/O FLAGS

CLK

DATA

LE

SCLOCK

MOSI

MUXOUT

(LOCK DETECT)

ADuC812

ADF4116/

ADF4117/

ADF4118

Figure 39. ADSP-21xx to ADF411x family Interface

I/O PORTS

Set up the word length for 8 bits and use three memory

locations for each 24-bit word. To program each 21-bit latch,

store the three 8-bit bytes, enable the autobuffered mode, and

write to the transmit register of the DSP. This last operation

initiates the autobuffer transfer.

CE

MUXOUT

(LOCK DETECT)

Figure 38. ADuC812 to ADF411x family Interface

Rev. D | Page 24 of 28

ADF4116/ADF4117/ADF4118

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153AB

Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADF4116BRU

Temperature Range

−40°C to +85°C

Package Description

Package Option

RU-16

16-Lead Thin Shrink Small Outline Package (TSSOP)

ADF4116BRU-REEL

ADF4116BRU-REEL7

ADF4116BRUZ¹

ADF4116BRUZ-REEL¹

ADF4116BRUZ-REEL7¹

RU-16

ADF4117BRU

RU-16

ADF4117BRU-REEL

ADF4117BRU-REEL7

ADF4117BRUZ¹

ADF4117BRUZ-RL¹

ADF4117BRUZ-RL7¹

ADF4118BRU

16-Lead Thin Shrink Small Outline Package (TSSOP)

Evaluation Board

RU-16

−40°C to +85°C

−40°C to +125°C

ADF4118BRU-REEL

ADF4118BRU-REEL7

ADF4118BRUZ¹

ADF4118BRUZ-RL¹

ADF4118BRUZ-RL7¹

ADF4118YRUZ¹

ADF4118YRUZ-RL¹

ADF4118YRUZ-RL7¹

EVAL-ADF4118EBZ1¹

EVAL-ADF411XEBZ1¹

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. D | Page 25 of 28

ADF4116/ADF4117/ADF4118

NOTES

Rev. D | Page 26 of 28

ADF4116/ADF4117/ADF4118

NOTES

Rev. D | Page 27 of 28

ADF4116/ADF4117/ADF4118

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D00392-0-4/07(D)

Rev. D | Page 28 of 28


型号：	ADF4116_15
厂家：	ADI
描述：	RF PLL Frequency Synthesizers
文件：	总28页 (文件大小：486K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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