ADF4117BCPZ_技术文档

a

RF PLL Frequency Synthesizers

ADF4116/ADF4117/ADF4118

GENERAL DESCRIPTION

FEATURES

The ADF4116 family of frequency synthesizers can be used

to implement local oscillators in the up-conversion and down-

conversion sections of wireless receivers and transmitters. They

consist of a low-noise digital PFD (Phase Frequency Detector),

a precision charge pump, a programmable reference divider,

programmable A and B counters and a dual-modulus prescaler

(P/P+1). The A (5-bit) and B (13-bit) counters, in conjunction

with the dual modulus prescaler (P/P+1), implement an N

divider (N = BP+A). In addition, the 14-bit reference counter

(R Counter), allows selectable REFIN frequencies at the PFD

input. A complete PLL (Phase-Locked Loop) can be imple-

mented if the synthesizer is used with an external loop ﬁlter and

VCO (Voltage Controlled Oscillator).

ADF4116: 550 MHz

ADF4117: 1.2 GHz

ADF4118: 3.0 GHz

2.7 V to 5.5 V Power Supply

Separate V_PAllows Extended Tuning Voltage in 3 V

Systems

Selected Charge Pump Currents

Dual Modulus Prescaler

ADF4116: 8/9

ADF4117/ADF4118: 32/33

3-Wire Serial Interface

Digital Lock Detect

Power-Down Mode

Fast Lock Mode

Control of all the on-chip registers is via a simple 3-wire interface.

The devices operate with a power supply ranging from 2.7 V to

5.5 V and can be powered down when not in use.

APPLICATIONS

Base Stations for Wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)

Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANS

Communications Test Equipment

CATV Equipment

FUNCTIONAL BLOCK DIAGRAM

AV

DD

DV

DD

V

P

CPGND

REFERENCE

ADF4116/ADF4117/ADF4118

14-BIT

R COUNTER

REF

IN

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

CP

14

R COUNTER

LATCH

CLK

DATA

LE

21-BIT

INPUT REGISTER

FUNCTION

LATCH

LOCK

DETECT

19

A, B COUNTER

LATCH

SD

OUT

18

HIGH Z

FROM

FUNCTION LATCH

AV

DD

13

MUX

MUXOUT

N = BP + A

13-BIT

B COUNTER

SD

OUT

RF

A

B

IN

LOAD

PRESCALER

P/P +1

IN

5-BIT

A COUNTER

M3 M2 M1

FL

SWITCH

O

FL

O

5

CE

AGND

DGND

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADF4116/ADF4117/ADF4118–SPECIFICATIONS¹

(AV_DD= DV_DD= 3 V ؎ 10%, 5 V ؎ 10%; AV_DD≤ V_P≤ 6.0 V; AGND = DGND = CPGND = 0 V; T_A= T_MINto T_MAXunless otherwise noted)

Parameter

B Version

B Chips²

Unit

Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency

ADF4116

See Figure 22 for Input Circuit

45/550

0.045/1.2

0.1/3.0

0.2/3.0

45/550

0.045/1.2

0.1/3.0

0.2/3.0

MHz min/max

GHz min/max

ADF4117

ADF4118

Input Level = –10 dBm

Maximum Allowable

Prescaler Output Frequency³

165

200

–15/0

–10/0

165

200

–15/0

–10/0

MHz max

dBm min/max

AV_DD,DV_DD= 3 V

AV_DD,DV_DD= 5 V

AV_DD= 3 V

RF Input Sensitivity

AV_DD= 5 V

REFIN CHARACTERISTICS

Reference Input Frequency

Reference Input Sensitivity⁴

0/100

–5/0

0/100

–5/0

MHz min/max

dBm min/max

AC-Coupled. When DC-Coupled:

0 to V_DDMax (CMOS Compatible)

REFIN Input Capacitance

REFIN Input Current

10

100

10

100

pF max

µA max

PHASE DETECTOR FREQUENCY⁵

55

MHz max

CHARGE PUMP

I_CPSink/Source

High Value

Low Value

Absolute Accuracy

I_CPThree-State Leakage Current

Sink and Source Current Matching

I_CPvs. V_CP

1

mA typ

µA typ

% typ

nA max

% typ

250

2.5

1

3

2

250

2.5

1

3

2

0.5 V ≤ V_CP≤ V_P– 0.5

V_CP= V_P/2

% typ

I_CPvs. Temperature

2

% typ

LOGIC INPUTS

V

_INH, Input High Voltage

_INL, Input Low Voltage

0.8 × DV_DD

0.8 × DV_DDV min

0.2 × DV_DDV max

0.2 × DV_DD

I_INH/I_INL, Input Current

C_IN, Input Capacitance

Reference Input Current

1

10

100

1

µA max

pF max

µA max

10

100

LOGIC OUTPUTS

V_OH, Output High Voltage

V_OL, Output Low Voltage

DV_DD– 0.4

0.4

DV_DD– 0.4 V min

I_OH= 500 µA

I_OL= 500 µA

0.4

V max

POWER SUPPLIES

AV_DD

DV_DD

V_P

2.7/5.5

AV_DD

AV_DD/6.0

2.7/5.5

AV_DD

AV_DD/6.0

V min/V max

AV_DD≤ V_P≤ 6.0 V

See Figure 20

4.5 mA Typical

6.5 mA Typical

T_A= 25°C

I_DD⁶(AI_DD+ DI_DD

ADF4116

ADF4117

ADF4118

I_P

)

5.5

7.5

0.4

1

4.5

6.5

0.4

1

mA max

µA typ

Low-Power Sleep Mode

REV. 0

–2–

ADF4116/ADF4117/ADF4118

Parameter

B Version

B Chips²Unit

Test Conditions/Comments

NOISE CHARACTERISTICS

ADF4118 Phase Noise Floor⁷

–170

–162

–170

–162

dBc/Hz typ @ 25 kHz PFD Frequency

dBc/Hz typ @ 200 kHz PFD Frequency

@ VCO Output

dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

dBc/Hz typ Note 15

dBc/Hz typ @ 300 Hz Offset and 30 kHz PFD Frequency

dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

dBc/Hz typ @ 200 Hz Offset and 10 kHz PFD Frequency

dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

Phase Noise Performance⁸

ADF4116⁹540 MHz Output

ADF4117¹⁰900 MHz Output

ADF4118¹⁰900 MHz Output

ADF4117¹¹836 MHz Output

–89

–87

–90

–78

–89

–87

–90

–78

–85

–65

–84

ADF4118¹²1750 MHz Output –85

ADF4118¹³1750 MHz Output –65

ADF4118¹⁴1960 MHz Output –84

Spurious Signals

ADF4116⁹540 MHz Output

ADF4117¹⁰900 MHz Output

ADF4118¹⁰900 MHz Output

ADF4117¹¹836 MHz Output

–88/–99

–90/–104 dBc typ

–91/–100 dBc typ

–80/–84

–88/–90

–65/–73

–80/–86

dBc typ

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

Note 15

@ 30 kHz/60 kHz and 30 kHz PFD Frequency

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

@ 10 kHz/20 kHz and 10 kHz PFD Frequency

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

–90/–104

–91/–100

–80/–84

dBc typ

ADF4118¹²1750 MHz Output –88/–90

ADF4118¹³1750 MHz Output –65/–73

ADF4118¹⁴1960 MHz Output –80/–86

NOTES

¹Operating temperature range is as follows: B Version: –40°C to +85°C.

²The B Chip speciﬁcations are given as typical values.

³This is the maximum operating frequency of the CMOS counters.

⁴AV_DD= DV_DD= 3 V; for AV_DD= DV_DD= 5 V, use CMOS-compatible levels.

⁵Guaranteed by design. Sample tested to ensure compliance.

⁶AV_DD= DV_DD= 3 V; RF_INfor ADF4116 = 540 MHz; RF_INfor ADF4117, ADF4118 = 900 MHz.

⁷The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider

value).

⁸The phase noise is measured with the EVAL-ADF411xEB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for

the synthesizer (f_REFOUT= 10 MHz @ 0 dBm).

⁹f_REFIN= 10 MHz; f_PFD= 200 kHz; Offset frequency = 1 kHz; f_RF= 540 MHz; N = 2700; Loop B/W = 20 kHz.

10

11

12

13

14

f

= 10 MHz; f_PFD= 200 kHz; Offset frequency = 1 kHz; f_RF= 900 MHz; N = 4500; Loop B/W = 20 kHz.

= 10 MHz; f_PFD= 30 kHz; Offset frequency = 300 Hz; f_RF= 836 MHz; N = 27867; Loop B/W = 3 kHz.

= 10 MHz; f_PFD= 200 kHz; Offset frequency = 1 kHz; f_RF= 1750 MHz; N = 8750; Loop B/W = 20 kHz.

= 10 MHz; f_PFD= 10 kHz; Offset frequency = 200 Hz; f_RF= 1750 MHz; N = 175000; Loop B/W = 1 kHz.

= 10 MHz; f_PFD= 200 kHz; Offset frequency = 1 kHz; f_RF= 1960 MHz; N = 9800; Loop B/W = 20 kHz.

REFIN

¹⁵Same conditions as above.

Speciﬁcations subject to change without notice.

(AV_DD= DV_DD= 3 V ؎ 10%, 5 V ؎ 10%; AV_DD≤ V_P< 6.0 V; AGND = DGND = CPGND = 0 V;

TIMING CHARACTERISTICS¹

T_A= T_MINto T_MAXunless otherwise noted)

Limit at T_MINto T_MAX

(B Version)

Parameter

Unit

Test Conditions/Comments

t₁

t₂

t₃

t₄

t₅

t₆

10

25

10

20

ns min

DATA to CLOCK Setup Time

DATA to CLOCK Hold Time

CLOCK High Duration

CLOCK Low Duration

CLOCK to LE Setup Time

LE Pulsewidth

NOTE

¹Guaranteed by design but not production tested.

Speciﬁcations subject to change without notice.

REV. 0

–3–

ADF4116/ADF4117/ADF4118

ABSOLUTE MAXIMUM RATINGS^{1, 2}

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

(T_A= 25°C unless otherwise noted)

AV_DDto GND³. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV_DDto DV_DD. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

V_Pto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V_Pto AV_DD. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

Digital I/O Voltage to GND . . . . . . . . –0.3 V to V_DD+ 0.3 V

Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V_P+ 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

TSSOP θ_JAThermal Impedance . . . . . . . . . . . . . 150.4°C/W

CSP θ_JAThermal Impedance

(Paddle Soldered) . . . . . . . . . . . . . . . . . . . . . . . . . 122°C/W

(Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . . 216°C/W

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this speciﬁcation is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

²This device is a high-performance RF integrated circuit with an ESD rating of

< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling

and assembly.

³GND = AGND = DGND = 0 V.

TRANSISTOR COUNT

6425 (CMOS) and 303 (Bipolar).

t₃

t₄

CLOCK

t₁

t₂

DB1

DB0 (LSB)

DB20 (MSB)

DB19

DB2

DATA

LE

(CONTROL BIT C2)

(CONTROL BIT C1)

t₆

t₅

LE

Figure 1. Timing Diagram

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu-

late on the human body and test equipment and can discharge without detection. Although the

ADF4116/ADF4117/ADF4118 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions

are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option*

ADF4116BRU

ADF4116BCP

ADF4117BRU

ADF4117BCP

ADF4118BRU

ADF4118BCP

–40°C to +85°C

Thin Shrink Small Outline Package (TSSOP)

Chip Scale Package

Thin Shrink Small Outline Package (TSSOP)

Chip Scale Package

Thin Shrink Small Outline Package (TSSOP)

Chip Scale Package

RU-16

CP-20

RU-16

CP-20

RU-16

CP-20

*Contact the factory for chip availability.

REV. 0

–4–

ADF4116/ADF4117/ADF4118

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic

Function

1

FL_O

Fast Lock Switch Output. This can be used to switch an external resistor to change the loop ﬁlter band-

width. This will speed up locking of the PLL.

2

CP

Charge Pump Output. When enabled, this provides the

the external VCO.

I_CPto the external loop ﬁlter, which in turn drives

3

4

5

CPGND

AGND

RF_INB

Charge Pump Ground. This is the ground return path for the charge pump.

Analog Ground. This is the ground return path for the prescaler.

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a

small bypass capacitor, typically 100 pF. See Figure 22.

6

7

RF_INA

AV_DD

Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.

Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground

plane should be placed as close as possible to this pin. AV_DDmust be the same value as DV_DD

.

8

REF_IN

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and an equivalent input

resistance of 100 kΩ. See Figure 21. The oscillator input can be driven from a TTL or CMOS crystal

oscillator or it can be ac-coupled.

9

10

DGND

CE

Digital Ground.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-

state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.

11

12

13

14

15

16

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

the 21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

Serial Data Input. The serial data is loaded MSB ﬁrst with the two LSBs being the control bits. This

input is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one

of the four latches, the latch being selected using the control bits.

This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency

to be accessed externally.

DATA

LE

MUXOUT

DV_DD

V_P

Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground

plane should be placed as close as possible to this pin. DV_DDmust be the same value as AV_DD

.

Charge Pump Power Supply. This should be greater than or equal to V_DD. In systems where V_DDis 3 V,

it can be set to 5 V and used to drive a VCO with a tuning range of up to 6 V.

PIN CONFIGURATIONS

TSSOP

Chip Scale Package

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

P

FL

O

DV

CP

CPGND

AGND

DD

ADF4116

ADF4117

ADF4118

TOP VIEW

(Not to Scale)

MUXOUT

LE

1

2

3

4

5

15

14

13

12

11

CPGND

AGND

MUXOUT

LE

ADF4116

ADF4117

ADF4118

DATA

CLK

RF

B

A

DATA

CLK

IN

TOP VIEW

(Not to Scale)

RF

IN

B

CE

AV

DD

RF

IN

A

CE

DGND

REF

IN

REV. 0

–5–

–Typical Performance Characteristics

ADF4116/ADF4117/ADF4118

Table I. S-Parameter Data for the ADF4118 RF Input

(Up to 1.8 GHz)

10dB/DIVISION

R

= –40dBc/Hz

RMS NOISE = 0.64؇

0.64؇ rms

L

–40

KEYWORD

FREQ-

UNIT

PARAM-

TYPE

DATA-

IMPEDANCE-

–50

–60

FORMAT

OHMS

GHZ

S

MA

R

50

FREQ MagS11 AngS11

–70

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.89207

0.8886

–2.0571

–4.4427

–6.3212

–2.1393

–12.13

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

0.92087

0.93788

0.9512

–36.961

–39.343

–40.134

–43.747

–44.393

–46.937

–49.6

–51.884

–51.21

–53.55

–56.786

–58.781

–60.545

–61.43

–61.241

–64.051

–66.19

–80

0.89022

0.96323

0.90566

0.90307

0.89318

0.89806

0.89565

0.88538

0.89699

0.89927

0.87797

0.90765

0.88526

0.81267

0.90357

0.92954

0.93458

0.94782

0.96875

0.92216

0.93755

0.96178

0.94354

0.95189

0.97647

0.98619

0.95459

0.97945

0.98864

0.97399

0.97216

–90

–13.52

–100

–110

–120

–130

–15.746

–18.056

–19.693

–22.246

–24.336

–25.948

–28.457

–29.735

–31.879

–32.681

–31.522

–34.222

–140

100Hz

FREQUENCY OFFSET FROM 900 MHz CARRIER

1MHz

Figure 4. ADF4118 Integrated Phase Noise (900 MHz,

–63.775

200 kHz, 35 kHz, Typical Lock Time: 200 µs)

10dB/DIVISION

–40

R

= –40dBc/Hz

RMS NOISE = 0.575؇

L

0

–5

V

= 3V

–50

–60

DD

V

0.575؇ rms

P

–10

–15

–20

–25

–70

–80

–90

T

= –40؇C

–100

A

–30

–35

–110

–120

–130

T

= ؉85؇C

A

–40

–45

T

= ؉25

؇

C

A

–140

100Hz

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

FREQUENCY OFFSET FROM 900 MHz CARRIER

1MHz

RF INPUT FREQUENCY – GHz

Figure 2. Input Sensitivity (ADF4118)

Figure 5. ADF4118 Integrated Phase Noise (900 MHz,

200 kHz, 20 kHz, Typical Lock Time: 400 µs)

0

REFERENCE

LEVEL = –4.2dBm

V

I

= 3V, V = 5V

P

DD

REFERENCE

LEVEL = –3.8dBm

V

= 3V, V = 5V

P

DD

= 1mA

–10

–20

–30

–40

–50

–10

–20

–30

–40

–50

= 1mA

CP

I

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 22

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 4

–60

–70

–60

–70

–90.2dBc/Hz

–91.5dBc

–80

–90

–80

–90

–100

–2kHz

–1kHz

900MHz

+1kHz

+2kHz

–400kHz

–200kHz

900MHz

+200kHz

+400kHz

Figure 3. ADF4118 Phase Noise (900 MHz, 200 kHz, 20 kHz)

Figure 6. ADF4118 Reference Spurs (900 MHz, 200 kHz,

20 kHz)

REV. 0

–6–

ADF4116/ADF4117/ADF4118

0

–10

–20

–30

–40

–50

0

V

I

= 3V, Vp = 5V

V

I

= 3V, V = 5V

P

DD

= 1mA

REFERENCE

LEVEL = –7.0dBm

REFERENCE

LEVEL = –4.2dBm

–10

–20

–30

–40

–50

= 5mA

CP

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 5kHz

RES. BANDWIDTH = 300Hz

VIDEO BANDWIDTH = 300Hz

SWEEP = 4.2ms

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 35kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 10

AVERAGES = 20

–60

–70

–60

–70

–72.3dBc

–90.67dBc

–80

–90

–100

–60kHz

–30kHz

1750MHz

+30kHz

+60kHz

–400kHz

–200kHz

900MHz

+200kHz

+400kHz

Figure 7. ADF4118 Reference Spurs (900 MHz, 200 kHz,

35 kHz)

Figure 10. ADF4118 Reference Spurs (1750 MHz,

30 kHz, 3 kHz)

0

V

I

= 3V, Vp = 5V

V

I

= 3V, Vp = 5V

DD

REFERENCE

LEVEL = –7.0dBm

REFERENCE

LEVEL = –10.3dBm

–10

–20

–30

–40

–50

= 1mA

–10

–20

–30

–40

= 1mA

CP

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 5kHz

RES. BANDWIDTH = 10kHz

VIDEO BANDWIDTH = 10kHz

SWEEP = 477ms

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 26

–50

AVERAGES = 25

–60

–70

–60

–70

–85.2dBc/Hz

–71.5dBc/Hz

–80

–90

–100

–2kHz

–1kHz

+1kHz

+2kHz

2800MHz

–400kHz

–200kHz

1750MHz

+200kHz

+400kHz

Figure 8. ADF4118 Phase Noise (1750 MHz, 30 kHz,

3 kHz)

Figure 11. ADF4118 Phase Noise (2800 MHz, 1 MHz,

100 kHz)

10dB/DIVISION

R

= –40dBc/Hz

RMS NOISE = 2.0؇

2.0؇ rms

10dB/DIVISION

R

= –40dBc/Hz

RMS NOISE = 1.552؇

1.55؇ rms

L

–40

–50

–60

–50

–60

–70

–80

–70

–80

–90

–100

–110

–120

–130

–110

–120

–130

–140

100Hz

–140

100Hz

FREQUENCY OFFSET FROM 1.75GHz CARRIER

1MHz

FREQUENCY OFFSET FROM 2.8 GHz CARRIER

1MHz

Figure 9. ADF4118 Integrated Phase Noise (1750 MHz,

30 kHz, 3 kHz)

Figure 12. ADF4118 Integrated Phase Noise (2800 MHz,

1 MHz, 100 kHz)

REV. 0

–7–

ADF4116/ADF4117/ADF4118

–60

–70

0

V

= 3V, V = 5V

P

DD

I = 1mA

CP

REFERENCE

LEVEL = –9.3dBm

–10

–20

–30

–40

–50

V

= 3V

DD

= 5V

P

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 3kHz

VIDEO BANDWIDTH = 3kHz

SWEEP = 1.4 SECONDS

AVERAGES = 4

–80

–60

–70

–77.3dBc

–90

–80

–90

–100

–40

–20

0

20

40

60

80

100

–2MHz

–1MHz

2800MHz

+1MHz

+2MHz

TEMPERATURE –

؇

C

Figure 16. ADF4118 Reference Spurs vs. Temperature

(900 MHz, 200 kHz, 20 kHz)

Figure 13. ADF4118 Reference Spurs (2800 MHz, 1 MHz,

100 kHz)

5

–130

V

= 3V

= 5V

DD

–5

–15

–25

–35

–45

–55

–65

–75

–85

–95

V

= 3V

= 5V

DD

–135

–140

–145

–150

–155

–160

–165

–170

–175

P

–105

0

1

2

3

4

5

1

10

100

1000

10000

TURNING VOLTAGE

PHASE DETECTOR FREQUENCY – kHz

Figure 17. ADF4118 Reference Spurs (200 kHz) vs.

V_TUNE(900 MHz, 200 kHz, 20 kHz)

Figure 14. ADF4118 Phase Noise (Referred to CP Out-

put) vs. PFD Frequency

–60

V

= 3V

DD

= 5V

V

= 3V

P

DD

= 5V

P

–70

–80

–70

–80

–90

–100

0

20

40

60

80

100

–40

–20

0

20

40

60

80

100

TEMPERATURE –

؇C

TEMPERATURE –

؇C

Figure 18. ADF4118 Phase Noise vs. Temperature

(836 MHz, 30 kHz, 3 kHz)

Figure 15. ADF4118 Phase Noise vs. Temperature

(900 MHz, 200 kHz, 20 kHz)

REV. 0

–8–

ADF4116/ADF4117/ADF4118

3.0

2.5

2.0

1.5

1.0

0.5

0.0

–60

–70

V

= 3V

DD

= 5V

P

–80

–90

–100

0

20

40

60

80

100

0

50

100

150

200

TEMPERATURE –

؇

C

PRESCALER OUTPUT FREQUENCY – MHz

Figure 19. ADF4118 Reference Spurs vs. Temperature

(836 MHz, 30 kHz, 3 kHz)

Figure 20. DI_DDvs. Prescaler Output Frequency

(ADF4116, ADF4117, ADF4118)

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

A AND B COUNTERS

The A and B CMOS counters combine with the dual modulus

prescaler to allow a wide ranging division ratio in the PLL

feedback counter. The counters are speciﬁed to work when the

prescaler output is 200 MHz or less.

The reference input stage is shown below in Figure 21. SW1

and SW2 are normally-closed switches. SW3 is normally-open.

When power-down is initiated, SW3 is closed and SW1 and SW2

are opened. This ensures that there is no loading of the REF_IN

pin on power-down.

Pulse Swallow Function

The A and B counters, in conjunction with the dual modulus

prescaler make it possible to generate output frequencies which

are spaced only by the Reference Frequency divided by R. The

equation for the VCO frequency is as follows:

POWER-DOWN

CONTROL

100k⍀

SW2

NC

f

_VCO= [(P × B) + A] × f_REFIN/R

TO R COUNTER

REF

IN

NC

SW1

BUFFER

f_VCO

Output Frequency of external voltage controlled oscilla-

tor (VCO).

SW3

NO

P

Preset modulus of dual modulus prescaler.

Figure 21. Reference Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 22. It is followed by a 2-

stage limiting ampliﬁer to generate the CML clock levels needed

for the prescaler.

B

A

Preset Divide Ratio of binary 13-bit counter (3 to 8191).

Preset Divide Ratio of binary 5-bit swallow counter

(0 to 31).

f_REFINOutput frequency of the external reference frequency

oscillator.

R

Preset divide ratio of binary 14-bit programmable refer-

ence counter (1 to 16383).

1.6V

BIAS

GENERATOR

AV

DD

500⍀

R COUNTER

The 14-bit R counter allows the input reference frequency to be

divided down to produce the input clock to the phase frequency

detector (PFD). Division ratios from 1 to 16,383 are allowed.

RF

A

B

IN

N = BP + A

TO PFD

AGND

13-BIT B

COUNTER

Figure 22. RF Input Stage

FROM RF

INPUT STAGE

LOAD

PRESCALER

P/P + 1

PRESCALER (P/P + 1)

The dual modulus prescale (P/P + 1), along with the A and B

counters, enables the large division ratio, N, to be realized, (N =

PB + A). The dual-modulus prescaler takes the CML clock

from the RF input stage and divides it down to a manageable

frequency for the CMOS A and B counters. The prescaler is

programmable. It can be set in software to 8/9 for the

ADF4116, and set to 32/33 for the ADF4117 and ADF4118.

It is based on a synchronous 4/5 core.

MODULUS

CONTROL

5-BIT A

COUNTER

Figure 23. A and B Counters

REV. 0

–9–

ADF4116/ADF4117/ADF4118

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE

PUMP

DV

DD

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 24 is a simpliﬁed schematic.

The PFD includes a ﬁxed delay element which sets the width of

the antibacklash pulse. This is typically 3 ns. This pulse ensures

that there is no dead zone in the PFD transfer function and

gives a consistent reference spur level.

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

MUXOUT

MUX

CONTROL

V

DGND

P

CHARGE

PUMP

Figure 25. MUXOUT Circuit

UP

HI

D1

Q1

Lock Detect

U1

MUXOUT can be programmed for two types of lock detect:

Digital Lock Detect and Analog Lock Detect.

R DIVIDER

CLR1

Digital Lock Detect is active high. It is set high when the phase

error on three consecutive phase detector cycles is less than 15 ns.

It will stay set high until a phase error of greater than 25 ns is

detected on any subsequent PD cycle.

CP

DELAY

DOWN

U3

The N-channel open-drain analog lock detect should be oper-

ated with an external pull-up resistor of 10 kΩ nominal. When

lock has been detected it is high with narrow low-going pulses.

CLR2

U2

D2

Q2

HI

INPUT SHIFT REGISTER

The ADF4116 family digital section includes a 21-bit input shift

register, a 14-bit R counter and a˙`-bit N counter, comprising

a 5-bit A counter and a 13-bit B counter. Data is clocked into

the 21-bit shift register on each rising edge of CLK. The data is

clocked in MSB ﬁrst. Data is transferred from the shift register

to one of four latches on the rising edge of LE. The destination

latch is determined by the state of the two control bits (C2, C1)

in the shift register. These are the two LSBs DB1, DB0 as

shown in the timing diagram of Figure 1. The truth table for

these bits is shown in Table VII. Table II shows a summary

of how the latches are programmed.

N DIVIDER

CP GND

R DIVIDER

N DIVIDER

CP OUTPUT

Figure 24. PFD Simpliﬁed Schematic and Timing (In Lock)

Table II. C2, C1 Truth Table

Control Bits

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4116 family allows the

user to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2 and M1 in the function

latch. Table VI shows the full truth table. Figure 25 shows the

MUXOUT section in block diagram form.

C2

C1

Data Latch

0

1

0

1

0

1

R Counter

N Counter (A and B)

Function Latch

Initialization Latch

REV. 0

–10–

ADF4116/ADF4117/ADF4118

Table III. ADF4116 Family Latch Summary

REFERENCE COUNTER LATCH

TEST

MODE BITS

CONTROL

BITS

14-BIT REFERENCE COUNTER, R

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

LDP T4 T3 T2 T1 R14 R13 R12 R11 R10 R9

DB9

R8

DB8

R7

DB7

R6

DB6

R5

DB5

R4

DB4

R3

DB3

R2

DB2

R1

DB1

DB0

C2 (0) C1 (0)

AB COUNTER LATCH

CONTROL

BITS

13-BIT B COUNTER

5-BIT A COUNTER

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9

B3

DB8

B2

DB7

B1

DB6

A5

DB5

DB4

A3

DB3

DB2

A1

DB1

DB0

G1

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

A4

A2

C2 (0) C1 (1)

FUNCTION LATCH

TIMER COUNTER

CONTROL

MUXOUT

CONTROL

BITS

RESERVED

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11

DB10

X

DB9

F4

DB8

F3

DB7

F2

DB6

M3

DB5

M2

DB4

M1

DB3

PD1

DB2

F1

DB1

DB0

X

PD2

X

TC4

TC3

TC2

TC1

F6

C2 (1) C1 (0)

INITIALIZATION LATCH

TIMER COUNTER

CONTROL

MUXOUT

CONTROL

BITS

RESERVED

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9

F4

DB8

F3

DB7

F2

DB6

M3

DB5

M2

DB4

M1

DB3

PD1

DB2

F1

DB1

DB0

X

PD2

TC4

TC3

TC2

TC1

F6

X

C2 (1) C1 (1)

REV. 0

–11–

ADF4116/ADF4117/ADF4118

Table IV. Reference Counter Latch Map

TEST

MODE BITS

CONTROL

BITS

14-BIT REFERENCE COUNTER, R

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9

R8

DB8

R7

DB7

R6

DB6

R5

DB5

R4

DB4

R3

DB3

R2

DB2

R1

DB1

DB0

LDP

T4

T3

T2

T1

R14

R13

R12

R11

R10

R9

C2 (0) C1 (0)

R14

0

R13

0

R12

0

••••••••••

R3

R2

0

R1

1

DIVIDE RATIO

1

0

1

•

0

•

0

•

0

•

••••••••••

1

0

•

0

1

0

•

2

3

4

•

1

0

1

0

1

0

1

163 80

163 81

163 82

163 83

TEST MODE BITS SHOULD

BE SET TO 0000 FOR

NORMAL OPERATION

LDP

OPERATION

3 CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

5 CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

0

1

REV. 0

–12–

ADF4116/ADF4117/ADF4118

Table V. AB Counter Latch Map

CONTROL

BITS

13-BIT B COUNTER

5-BIT A COUNTER

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9

B3

DB8

B2

DB7

B1

DB6

A5

DB5

A4

DB4

A3

DB3

A2

DB2

A1

DB1

DB0

G1

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

C2 (0) C1 (1)

A COUNTER

A5

A4

X

•

A3

A2

A1

0

1

•

DIVIDE RATIO

X

•

0

•

0

•

0

1

•

ADF4116

•

X

1

0

1

6

7

A COUNTER

A5

0

•

A4

0

•

A3

0

•

A2

0

1

•

A1

0

1

0

•

DIVIDE RATIO

0

1

ADF4117/ADF4118

2

•

1

0

1

0

1

29

30

31

••••••••••

B13

B12

B11

0

B3

0

B2

0

B1

1

B COUNTER DIVIDE RATIO

NOT ALLOWED

0

•

0

•

0

•

••••••••••

0

1

•

1

0

•

0

1

0

•

NOT ALLOWED

3

4

•

1

0

1

0

1

0

1

8188

8189

8190

8191

LDP CURRENT SETTINGS

250␮A

0

1

N = BP + A, P IS PRESCALER VALUE. B MUST BE GREATER

1mA

THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT

2

VALUES OF N

F

, N

IS (P -P).

MIN

X

REF

REV. 0

–13–

ADF4116/ADF4117/ADF4118

Table VI. Function Latch Map

TIMER COUNTER

CONTROL

MUXOUT

CONTROL

BITS

RESERVED

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11

DB10

X

DB9

F4

DB8

F3

DB7

F2

DB6

M3

DB5

M2

DB4

M1

DB3

PD1

DB2

F1

DB1

DB0

X

PD2

X

TC4

TC3

TC2

TC1

F6

C2 (1) C1 (0)

COUNTER

F1

0

OPERATION

NORMAL

R, A, B COUNTERS

HELD IN RESET

1

CE PIN PD2 PD1

MODE

M3

M2

0

M1

OUTPUT

ASYNCHRONOUS POWER-DOWN

NORMAL OPERATION

0

1

X

0

1

X

0

1

0

THREE-STATE OUTPUT

DIGITAL LOCK DETECT

(ACTIVE HIGH)

ASYNCHRONOUS POWER-DOWN

SYNCHRONOUS POWER-DOWN

0

1

0

1

0

1

0

1

0

N DIVIDER OUTPUT

AV

DD

R DIVIDER OUTPUT

ANALOG LOCK DETECT

(N CHANNEL OPEN DRAIN)

1

0

1

SERIAL DATA OUTPUT

(INVERSE POLARITY OF

SERIAL DATA INPUT)

1

0

1

DGND

F2

0

PD POLARITY

NEGATIVE

POSITIVE

1

CHARGE PUMP

OUTPUT

F3

0

NORMAL

1

3-STATE

F4

0

F6

FASTLOCK MODE

FASTLOCK DISABLED

FASTLOCK MODE 1

FASTLOCK MODE 2

X

0

1

TIMEOUT

TC4

TC3

TC2

TC1

(PFD CYCLES)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

7

11

15

19

23

27

31

35

39

43

47

51

55

59

63

REV. 0

–14–

ADF4116/ADF4117/ADF4118

Table VII. Initialization Latch Map

RESERVED

TIMER COUNTER

CONTROL

MUXOUT

CONTROL

BITS

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9

F4

DB8

F3

DB7

F2

DB6

M3

DB5

M2

DB4

M1

DB3

PD1

DB2

F1

DB1

DB0

X

PD2

TC4

TC3

TC2

TC1

F6

X

C2 (1) C1 (1)

COUNTER

OPERATION

F1

0

1

NORMAL

R, A, B COUNTERS

HELD IN RESET

M3

M2

0

M1

OUTPUT

CE PIN PD2 PD1

MODE

0

THREE-STATE OUTPUT

ASYNCHRONOUS POWER-DOWN

NORMAL OPERATION

0

1

X

0

1

X

0

1

DIGITAL LOCK DETECT

(ACTIVE HIGH)

0

1

0

1

0

1

0

ASYNCHRONOUS POWER-DOWN

N DIVIDER OUTPUT

0

SYNCHRONOUS POWER-DOWN

AV

DD

0

1

R DIVIDER OUTPUT

ANALOG LOCK DETECT

(N CHANNEL OPEN DRAIN)

1

0

1

SERIAL DATA OUTPUT

(INVERSE POLARITY OF

SERIAL DATA INPUT)

1

0

1

DGND

F2

0

PD POLARITY

NEGATIVE

POSITIVE

1

CHARGE PUMP

OUTPUT

F3

0

NORMAL

1

THREE-STATE

F4

0

F6

FASTLOCK MODE

FASTLOCK DISABLED

X

0

1

FASTLOCK MODE 1

FASTLOCK MODE 2

1

TIMEOUT

TC4

TC3

TC2

TC1

(PFD CYCLES)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

7

11

15

19

23

27

31

35

39

43

47

51

55

59

63

REV. 0

–15–

ADF4116/ADF4117/ADF4118

THE FUNCTION LATCH

Fastlock Mode Bit

With C2, C1 set to 1, 0, the on-chip function latch will be pro-

grammed. Table VI shows the input data format for programming

the Function Latch.

DB11 of the Function Latch is the Fastlock Mode bit. When

Fastlock is enabled, this bit determines which Fastlock Mode is

used. If the Fastlock Mode bit is “0” then Fastlock Mode 1 is

selected and if the Fastlock Mode bit is “1,” then Fastlock

Mode 2 is selected.

Counter Reset

DB2 (F1) is the counter reset bit. When this is “1,” the R counter

and the A, B counters are reset. For normal operation this bit

should be “0.” Upon powering up, the F1 bit needs to be disabled,

the N counter resumes counting in “close” alignment with the R counter.

(The maximum error is one prescaler cycle.)

If Fastlock is not enabled (DB9 = “0”), then DB11 (ADF4116)

determines the state of the FL_Ooutput. FL_Ostate will be the

same as that programmed to DB11.

Fastlock Mode 1

Power-Down

In the ADF4116 family, the output level of FL_Ois programmed

to a low state and the charge pump current is switched to the

high value (1 mA). FL_Ois used to switch a resistor in the loop

ﬁlter and ensure stability while in Fastlock by altering the loop

bandwidth.

DB3 (PD1) and DB19 (PD2) on the ADF4116 family, provide

programmable power-down modes. They are enabled by the

CE pin.

When the CE pin is low, the device is immediately disabled

regardless of the states of PD2, PD1.

The device enters Fastlock by having a “1” written to the CP

Gain bit in the N register. The device exits Fastlock by having a

“0” written to the CP Gain bit in the N register.

In the programmed asynchronous power-down, the device pow-

ers down immediately after latching a “1” into bit PD1, with the

condition that PD2 has been loaded with a “0.”

Fastlock Mode 2

In the ADF4116 family, the output level of FL_Ois programmed

to a low state and the charge pump current is switched to the high

value (1 mA). FL_Ois used to switch a resistor in the loop ﬁlter and

ensure stability while in Fastlock by altering the loop bandwidth.

In the programmed synchronous power-down, the device power

down is gated by the charge pump to prevent unwanted fre-

quency jumps. Once the power-down is enabled by writing a

“1” into bit PD1 (on condition that a “1” has also been loaded

to PD2), then the device will go into power-down after the ﬁrst

successive charge pump event.

The device enters Fastlock by having a “1” written to the CP

Gain bit in the N register. The device exits Fastlock under the

control of the Timer Counter. After the timeout period deter-

mined by the value in TC4–TC1, the CP Gain bit in the N

register is automatically reset to “0” and the device reverts to

normal mode instead of Fastlock.

When a power down is activated (either synchronous or asynchro-

nous mode including CE-pin-activated power down), the

following events occur:

All active dc current paths are removed.

Timer Counter Control

The R, N and timeout counters are forced to their load state

conditions.

In the ADF4116 family, the user has the option of switching

between two charge pump current values to speed up locking to

a new frequency.

The charge pump is forced into three-state mode.

The digital clock detect circuitry is reset.

The RF_INinput is debiased.

When using the Fastlock feature with the ADF4116 family, the

normal sequence of events is as follows:

The user must make sure that Fastlock is enabled. Set DB9 of the

ADF4116 family to “1.” The user must also choose which Fastlock

Mode to use. As discussed in the previous section, Fastlock

Mode 2 uses the values in the Timer Counter to determine the

timeout period before reverting to normal mode operation after

Fastlock. Fastlock Mode 2 is chosen by setting DB11 of the

ADF4116 family to “1.”

The oscillator input buffer circuitry is disabled.

The input register remains active and capable of loading and

latching data.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, M1 on the

ADF4116 family. Table VI shows the truth table.

The user must also decide how long they want the high current

(1 mA) to stay active before reverting to low current (250 µA).

This is controlled by the Timer Counter Control Bits DB14 to

DB11 (TC4–TC1) in the Function Latch. The truth table is

given in Table VI.

Phase Detector Polarity

DB7 (F2) of the function latch sets the Phase Detector Polarity.

When the VCO characteristics are positive this should be set to

“1.” When they are negative it should be set to “0.”

Charge Pump Three-State

Now, when the user wishes to program a new output frequency,

they can simply program the A, B counter latch with new values

for A and B. At the same time they can set the CP Gain bit to a

“1,” which sets the charge pump 1 mA for a period of time deter-

mined by TC4–TC1. When this time is up, the charge pump

current reverts to 250 µA. At the same time the CP Gain Bit in

the A, B Counter latch is reset to 0 and is now ready for the

next time that the user wishes to change the frequency again.

This bit puts the charge pump into three-state mode when pro-

grammed to a “1.” It should be set to “0” for normal operation.

Fastlock Enable Bit

DB9 of the Function Latch is the Fastlock Enable Bit. Only

when this is “1” is Fastlock enabled.

REV. 0

–16–

ADF4116/ADF4117/ADF4118

The Initialization Latch

The CE Pin Method

Apply V_DD

When C2, C1 = 1, 1 then the Initialization Latch is programmed.

This is essentially the same as the Function Latch (programmed

when C2, C1 = 1, 0).

.

Bring CE low to put the device into power-down. This is an

asynchronous power-down in that it happens immediately.

Program the Function Latch (10). Program the R Counter

Latch (00). Program the N Counter Latch (01). Bring CE high

to take the device out of power-down. The R and N counter will

now resume counting in close alignment.

However, when the Initialization Latch is programmed there is a

additional internal reset pulse applied to the R and N counters.

This pulse ensures that the N counter is at load point when the

N counter data is latched and the device will begin counting in

close phase alignment.

Note that after CE goes high, a duration of 1 µs may be required

for the prescaler bandgap voltage and oscillator input buffer bias

to reach steady state.

If the Latch is programmed for synchronous power-down (CE

pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse

also triggers this power-down. The prescaler reference and the

oscillator input buffer are unaffected by the internal reset pulse and

so close phase alignment is maintained when counting resumes.

CE can be used to power the device up and down in order to

check for channel activity. The input register does not need to

be reprogrammed each time the device is disabled and enabled

as long as it has been programmed at least once after V_CCwas

initially applied.

When the ﬁrst N counter data is latched after initialization, the

internal reset pulse is again activated. However, successive N

counter loads after this will not trigger the internal reset pulse.

The Counter Reset Method

Device Programming After Initial Power-Up

After initially powering up the device, there are three ways to

program the device.

Apply V_DD.

Do a Function Latch Load (“10” in 2 LSBs). As part of this,

load “1” to the F1 bit. This enables the counter reset. Do an R

Counter Load (“00” in 2 LSBs). Do an N Counter Load (“01”

in 2 LSBs). Do a Function Latch Load (“10” in 2 LSBs). As

part of this, load “0” to the F1 bit. This disables the counter reset.

Initialization Latch Method

Apply V_DD

.

Program the Initialization Latch (“11” in 2 LSBs of input word).

Make sure that F1 bit is programmed to “0.” Then do an R load

(“00” in 2 LSBs). Then do an N load (“01” in 2 LSBs). When the

Initialization Latch is loaded, the following occurs:

This sequence provides the same close alignment as the initial-

ization method. It offers direct control over the internal reset.

Note that counter reset holds the counters at load point and

three-states the charge pump, but does not trigger synchronous

power-down. The counter reset method requires an extra func-

tion latch load compared to the initialization latch method.

1. The function latch contents are loaded.

2. An internal pulse resets the R, N and timeout counters to

load state conditions and also three-states the charge pump.

Note that the prescaler bandgap reference and the oscillator

input buffer are unaffected by the internal reset pulse,

allowing close phase alignment when counting resumes.

3. Latching the ﬁrst N counter data after the initialization word

will activate the same internal reset pulse. Successive N loads

will not trigger the internal reset pulse unless there is another

initialization.

REV. 0

–17–

ADF4116/ADF4117/ADF4118

APPLICATIONS SECTION

SHUTDOWN CIRCUIT

Local Oscillator for GSM Base Station Transmitter

Figure 26 shows the ADF4117/ADF4118 being used with a

VCO to produce the LO for a GSM base station transmitter.

The attached circuit in Figure 27 shows how to shut down both

the ADF4116 family and the accompanying VCO. The ADG702

switch goes open circuit when a Logic 1 is applied to the IN

input. The low-cost switch is available in both SOT-23 and

micro SOIC packages.

The reference input signal is applied to the circuit at FREF_IN

and, in this case, is terminated in 50 Ω. Typical GSM system

would have a 13 MHz TCXO driving the Reference Input

without any 50 Ω termination. In order to have a channel

spacing of 200 kHz (the GSM standard), the reference input

must be divided by 65, using the on-chip reference divider of

the ADF4117/ADF1118.

DIRECT CONVERSION MODULATOR

In some applications a direct conversion architecture can be used

in base station transmitters. Figure 28 shows the combination

available from ADI to implement this solution.

The circuit diagram shows the AD9761 being used with the

AD8346. The use of dual integrated DACs such as the AD9761

with speciﬁed 0.02 dB and 0.004 dB gain and offset match-

ing characteristics ensures minimum error contribution (over

temperature) from this portion of the signal chain.

The charge pump output of the ADF4117/ADF1118 (Pin 2)

drives the loop ﬁlter. In calculating the loop ﬁlter component

values, a number of items need to be considered. In this example,

the loop ﬁlter was designed so that the overall phase margin for

the system would be 45 degrees. Other PLL system speciﬁca-

tions are given below:

The Local Oscillator (LO) is implemented using the ADF4117/

ADF4118. In this case, the OSC 3B1-13M0 provides the

stable 13 MHz reference frequency. The system is designed

for a 200 kHz channel spacing and an output center frequency

of 1960 MHz. The target application is a WCDMA base sta-

tion transmitter. Typical phase noise performance from this LO

is –85 dBc/Hz at a 1 kHz offset. The LO port of the AD8346 is

driven in single-ended fashion. LOIN is ac-coupled to ground

with the 100 pF capacitor and LOIP is driven through the ac-

coupling capacitor from a 50 Ω source. An LO drive level of

between –6 dBm and –12 dBm is required. The circuit of Figure

28 gives a typical level of –8 dBm.

K

_D= 1 mA

K_V= 12 MHz/V

Loop Bandwidth = 20 kHz

F

_REF= 200 kHz

N = 4500

Extra Reference Spur Attenuation = 10 dB

All of these speciﬁcations are needed and used to come up with

the loop ﬁlter components values shown in Figure 27.

The loop ﬁlter output drives the VCO, which, in turn, is fed

back to the RF input of the PLL synthesizer and also drives

the RF Output terminal. A T-circuit conﬁguration provides

50 Ω matching between the VCO output, the RF output and

the RF_INterminal of the synthesizer.

The RF output is designed to drive a 50 Ω load but must be

ac-coupled as shown in Figure 28. If the I and Q inputs are driven

in quadrature by 2 V p-p signals, the resulting output power will

be around –10 dBm.

In a PLL system, it is important to know when the system is in

lock. In Figure 26, this is accomplished by using the MUXOUT

signal from the synthesizer. The MUXOUT pin can be pro-

grammed to monitor various internal signals in the synthesizer.

One of these is the LD or lock-detect signal.

RF

OUT

V

DD

P

100pF

7

15 16

DV

AV

DD

V

P

18⍀

DD

V

3.3k⍀

CC

2

100pF

18⍀

1000pF

8

CP

FREF

IN

REF

IN

VCO190-902T

620pF

27k⍀

0.15nF

51⍀

FL

O

ADF4117/

ADF4118

10k⍀

1.5nF

14

CE

LOCK

MUXOUT

CLK

DATA

LE

DETECT

100pF

6

5

RF

IN

A

51⍀

RF

B

IN

100pF

3

4

9

DECOUPLING CAPACITORS (10␮F/10pF) ON AV , DV , V OF THE

DD DD

P

ADF4117/ADF4118 AND ON V OF THE VCO190-902T HAVE BEEN

CC

OMITTED FROM THE DIAGRAM TO AID CLARITY.

Figure 26. Local Oscillator for GSM Base Station

REV. 0

–18–

ADF4116/ADF4117/ADF4118

V

P

POWER-DOWN CONTROL

V

S

DD

RF

OUT

IN

V

ADG702

GND

DD

D

100pF

7

15 16

DV

DD

18⍀

V

100pF

AV

DD

V

CE

CP

CC

18⍀

P

2

1

LOOP

FILTER

8

FREF

IN

REF

IN

VCO

FL

O

GND

ADF4116/

ADF4117/

ADF4118

10k⍀

100pF

6

5

RF

A

IN

51⍀

RF

IN

B

100pF

3

4

9

DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE

BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

Figure 27. Local Oscillator Shutdown Circuit

0.1␮F

REFIO

IBBP

IOUTA

IOUTB

100pF

LOW-PASS

FILTER

RF

OUT

VOUT

MODULATED

DIGITAL

DATA

AD9761

T_XDAC

AD8346

QBBP

QOUTA

QOUTB

LOW-PASS

FILTER

FS ADJ

2k⍀

LOIN

LOIP

100pF

OSC 3B1-13M0

TCXO

18⍀

R

SET

10k⍀

REF

IN

CP

VCO190-1960T

1k⍀

18pF

ADF4118

680pF

SERIAL

DIGITAL

NTERFACE

100pF

18⍀

6.8nF

18⍀

RF

IN

B

RF A

IN

100pF

51⍀

POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS

ARE OMITTED FROM DIAGRAM FOR CLARITY.

Figure 28. Direct Conversion Transmitter Solution

The maximum allowable serial clock rate is 20 MHz. This means

that the maximum update rate possible for the device is 833 kHz or

one update every 1.2 microseconds. This is certainly more than

adequate for systems which will have typical lock times in hun-

dreds of microseconds.

INTERFACING

The ADF4116 family has a simple SPI-compatible serial inter-

face for writing to the device. SCLK, SDATA and LE control

the data transfer. When LE (Latch Enable) goes high, the 24 bits

which have been clocked into the input register on each rising

edge of SCLK will get transferred to the appropriate latch. See

Figure 1 for the Timing Diagram and Table II for the Latch

Truth Table.

REV. 0

–19–

ADF4116/ADF4117/ADF4118

ADuC812 Interface

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed will be 166 kHz.

Figure 29 shows the interface between the ADF4116 family and

the ADuC812 microconverter. Since the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The microconverter is set up for SPI Master

Mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4116 family

needs a 24-bit word. This is accomplished by writing three 8-bit

bytes from the microconverter to the device. When the third

byte has been written the LE input should be brought high to

complete the transfer.

ADSP-2181 Interface

Figure 30 shows the interface between the ADF4116 family and

the ADSP-21xx Digital Signal Processor. The ADF4116 family

needs a 21-bit serial word for each latch write. The easiest way

to accomplish this using the ADSP-21xx family is to use the

Autobuffered Transmit Mode of operation with Alternate Fram-

ing. This provides a means for transmitting an entire block of

serial data before an interrupt is generated.

SCLK

SDATA

LE

SCLOCK

MOSI

SCLK

DT

ADuC812

SDATA

ADSP-21xx

ADF4116/

ADF4117/

ADF4118

ADF4116/

ADF4117/

ADF4118

TFS

LE

I/O PORTS

CE

I/O FLAGS

MUXOUT

(LOCK DETECT)

MUXOUT

(LOCK DETECT)

Figure 29. ADuC812 to ADF4116 Family Interface

Figure 30. ADSP-21xx to ADF4116 Family Interface

On ﬁrst applying power to the ADF4116 family, it needs three

writes (one each to the R counter latch, the N counter latch and

the initialization latch) for the output to become active.

Set up the word length for 8 bits and use three memory loca-

tions for each 24-bit word. To program each 21-bit latch, store

the three 8-bit bytes, enable the Autobuffered mode and then

write to the transmit register of the DSP. This last operation

initiates the autobuffer transfer.

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and to detect lock (MUXOUT conﬁgured as

lock detect and polled by the port input).

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Chip Scale

(CP-20)

Thin Shrink Small Outline

(RU-16)

0.201 (5.10)

0.193 (4.90)

0.159 (4.05)

0.157 (4.00)

0.156 (3.95)

0.079 (2.0) REF

0.014 (0.35)

؋

45°

0.018 (0.45)

0.016 (0.40)

0.014 (0.35)

16

20

16

15

1

9

0.177 (4.50)

0.169 (4.30)

0.159 (4.05)

0.157 (4.00)

0.156 (3.95)

0.079

(2.0)

REF

DETAIL E

TOP VIEW

0.020 (0.5) REF

LEAD PITCH

0.256 (6.50)

0.246 (6.25)

11

10

5

6

1

8

0.039 (1.00)

0.035 (0.90)

0.031 (0.80)

0.0083 (0.211)

0.0079 (0.200)

0.0077 (0.195)

BOTTOM VIEW

(ROTATED 180؇)

PIN 1

0.006 (0.15)

0.002 (0.05)

0.0433 (1.10)

MAX

0.0079 (0.20)

REF

SEATING

PLANE

8؇

0؇

LEAD OPTION

DETAIL E

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)

0.028 (0.70)

0.020 (0.50)

0.0079 (0.20)

0.0035 (0.090)

SEATING

PLANE

BSC

0.011 (0.275)

0.010 (0.250)

0.009 (0.225)

0.018 (0.45)

0.016 (0.40)

0.014 (0.35)

0.0059

(0.15)

REF

0.0059 (0.15)

REF

CONTROLLING DIMENSIONS ARE IN MILLIMETERS

REV. 0

–20–


型号：	ADF4117BCPZ
厂家：	ADI
描述：	IC PLL FREQUENCY SYNTHESIZER, 1200 MHz, CQCC20, CSP-20, PLL or Frequency Synthesis Circuit 射频
文件：	总20页 (文件大小：227K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADF4117BCPZ [ADI]

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