ADF4150_技术文档

Fractional-N / Integer-N PLL Synthesizer

Preliminary Technical Data

ADF4150

FEATURES

GENERAL DESCRIPTION

Fractional-N synthesizer and integer-N synthesizer

Programmable divide-by-1/2/4/8 or 16 output

3.0 V to 3.6 V power supply

The ADF4150 allows implementation of fractional-N or

integer-N phase-locked loop (PLL) frequency synthesizers if

used with an external Voltage Controlled Oscillator (VCO),

loop filter and external reference frequency.

1.8 V logic compatibility

Separate charge pump supply (V

voltage in 3 V systems

P

) allows extended tuning

The ADF4150 is for use with external VCO parts and is

software compatible with the ADF4350. The VCO frequency

can be divided-by 1/2/4/8 or 16 to allow the user to generate RF

output frequencies as low as 31.25 MHz. For applications that

require isolation the RF output stage can be muted. The mute

function is both pin and software controllable.

Programmable dual-modulus prescaler of 4/5 or 8/9

Programmable output power level

RF output mute function

3-wire serial interface

Analog and digital lock detect

Switched bandwidth fast-lock mode

Cycle slip reduction

Control of all the on-chip registers is through a simple 3-wire

interface. The device operates with a power supply ranging

from 3.0 V to 3.6 V and can be powered down when not in use.

APPLICATIONS

Wireless infrastructure (WCDMA, TD-SCDMA, WiMax, GSM,

PCS, DCS, DECT)

The ADF4150 is available in a 4mm x 4mm package.

Test equipment

Wireless LANs, CATV equipment

Clock Generation

FUNCTIONAL BLOCK DIAGRAM

V

SDV

AV

DV

R

DD

P

SET

ADF4150

MUXOUT

SW

MULTIPLEXER

10-BIT R

COUNTER

÷2

DIVIDER

×2

REF

IN

DOUBLER

FL SWITCH

O

LOCK

DETECT

CLK

DATA

LE

LD

DATA REGISTER

FUNCTION

LATCH

CHARGE

PUMP

CP

OUT

PHASE

COMPARATOR

RF

+

OUT

DIVIDE BY

1/2/4/8/16

OUTPUT

STAGE

INTEGER

REG

FRACTION

REG

MODULUS

REG

–

PDB

RF

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

RF

+

–

IN

RF

INPUT

M ULTIPLEXER

IN

N COUNTER

CE

AGND

DGND

CP

SD

GND

Figure 1.

Rev. PrI

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Fax: 781.461.3113

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Preliminary Technical Data

ADF4150

TABLE OF CONTENTS

Features .............................................................................................. 1

Register 2..................................................................................... 16

Register 3..................................................................................... 17

Register 4..................................................................................... 18

Register 5..................................................................................... 18

Initialization Sequence .............................................................. 18

RF Synthesizer— A Worked Example ..................................... 19

Modulus....................................................................................... 19

Reference Doubler and Reference Divider ............................. 19

12-Bit Programmable Modulus................................................ 19

Cycle Slip Reduction for Faster Lock Times........................... 20

Spurious Optimization and Fast lock ...................................... 20

Fast-Lock Timer and Register Sequences ............................... 20

Fast Lock—An Example............................................................ 20

Fast Lock—Loop Filter Topology............................................. 20

Spur Mechanisms ....................................................................... 21

Spur Consistency and Fractional Spur Optimization ........... 21

PHASE Resync............................................................................ 21

Applications Information.............................................................. 23

Direct Conversion Modulator .................................................. 23

Interfacing ................................................................................... 24

PCB Design Guidelines for Chip Scale Package .................... 24

Output Matching........................................................................ 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

Transistor Count........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Circuit Description......................................................................... 10

Reference Input Section............................................................. 10

RF N Divider............................................................................... 10

INT, FRAC, MOD and R Counter Relationship .................... 10

INT N MODE............................................................................. 10

R Counter .................................................................................... 10

Phase Frequency Detector (PFD) and Charge Pump............ 10

MUXOUT and LOCK Detect................................................... 11

Input Shift Registers................................................................... 11

Program Modes .......................................................................... 11

Output Stage................................................................................ 11

Register Maps.................................................................................. 12

Register 0 ..................................................................................... 16

Register 1 ..................................................................................... 16

Rev. PrI | Page 2 of 27

ADF4150

Preliminary Technical Data

SPECIFICATIONS

AV_DD= DV_DD= SD_VDD= 3.3 V 10%; V_P= AV_DDto 5.5 V; AGND = DGND = 0 V; T_A= T_MINto T_MAX, unless otherwise noted. Operating

temperature range is −40°C to +85°C.

Table 1.

Parameter

B Version

Unit

Conditions/Comments

REF_INCHARACTERISTICS

Input Frequency

10 to 250

MHz min to MHz max

For f < 10 MHz ensure slew rate > 21 V/µs

Biased at AV_DD/2¹

Input Sensitivity

0.7 to AV_DDV p-p min to V p-p max

Input Capacitance

Input Current

5.0

60

pF max

µA max

RF INPUT CHARACTERISTICS

RF Input Frequency (RF_IN)

0.5/4.0

4.0/6.0

GHz min/max

−10 dBm/0 dBm minimum/maximum

−5 dBm/0 dBm minimum/maximum

For lower frequencies, ensure slew rate > 400 V/µs

PHASE DETECTOR

Phase Detector Frequency²

CHARGE PUMP

32

MHz max

I_CPSink/Source

With R_SET= 5.1 kΩ

High Value

5

mA typ

Low Value

0.312

mA typ

R_SETRange

2.7 to 10

kΩ min to kΩ max

% typ

Sink and Source Current Matching

I_CPvs. V_CP

2

0.5 V ≤ V_CP≤ V_P- 0.5 V

V_CP= 2.0 V

1.5

2

% typ

I_CPvs. Temperature

LOGIC INPUTS

% typ

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_INH/I_INL

Input Capacitance, C_IN

LOGIC OUTPUTS

1.5

0.6

1

V min

V max

µA max

pF max

3.0

Output High Voltage, V_OH

Output High Current, I_OH

Output Low Voltage, V_O

POWER SUPPLIES

AV_DD

DV_DD− 0.4 V min

CMOS output chosen

I_OL= 500 µA

500

0.4

µA max

V max

3.0 to 3.6

AV_DD

AV_DD/5.5

25

V min to V max

DV_DD, SD_VDD

V_P

,

V min/V max

mA typ

3

DI_{DD +}AI_DD

Output Dividers

6-24

32

mA typ

Each output divide by two consumes 6 mA

RF output stage is programmable

3

I_RFOUT

mA typ

Low Power Sleep Mode

7

µA typ

RF OUTPUT CHARACTERISTICS

Minimum output frequency using RF 31.25

output dividers

MHz

500 MHz VCO input and divide by 16 selected

Maximum RF_INfrequency using RF

output dividers

3500

Harmonic Content (Second)

Harmonic Content (Third)

Harmonic Content (Second)

Harmonic Content (Third)

Output Power ⁴

−19

- 13

dBc typ

Fundamental VCO output

Divided VCO output

dBc typ

−20

- 10

dBc typ

Divided VCO output

−4 to +5

1

dBm typ min to dBm typ max

dB typ

Programmable in 3 dB steps

Output Power Variation

Rev. PrI | Page 3 of 27

Preliminary Technical Data

ADF4150

Parameter

B Version

Unit

Conditions/Comments

NOISE CHARACTERISTICS

Normalized In-Band Phase Noise

Floor⁵

−219

−222

−70

dBc/Hz typ

dBc typ

Anti-backlash pulse width set to 6 ns.

Anti-backlash pulse width set to 3 ns.

Normalized In-Band Phase Noise

Floor⁶

Spurious Signals Due to PFD

Frequency

Level of Signal With RF Mute Enabled −40

dBm typ

¹AC coupling ensures AV_DD/2 bias.

²Guaranteed by design. Sample tested to ensure compliance.

³T_A= 25°C; AV_DD= DV_DD= 3.3 V; prescaler = 8/9; f_REFIN= 100 MHz; f_PFD= 25 MHz; f_RF= 2.5 GHz.

⁴Using 50 Ω resistors to V_VCO, into a 50 Ω load.

⁵This figure can be used to calculate phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output use the following formula: −213 +

10log(f_PFD) + 20 logN . The value given is the lowest noise mode. f_REFIN= 100 MHz; f_PFD= 25 MHz; offset frequency = 50 kHz; VCO frequency = 1850.1 MHz. N = 74; loop BW =

500 kHz, I_CP= 2.5 mA; low noise mode. The noise was measured with an EVAL-ADF4150EB1Z and the Agilent E5052A signal source analyzer.

⁶This figure can be used to calculate phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output use the following formula: −213 +

10log(f_PFD) + 20 logN . The value given is the lowest noise mode. f_REFIN= 100 MHz; f_PFD= 25 MHz; offset frequency = 50 kHz; VCO frequency = 1850 MHz. N = 74; loop BW =

500 kHz, I_CP= 2.5 mA; low noise mode. The noise was measured with an EVAL-ADF4150EB1Z and the Agilent E5052A signal source analyzer.

Rev. PrI | Page 4 of 27

ADF4150

Preliminary Technical Data

TIMING CHARACTERISTICS

AV_DD= DV_DD= SD_VDD= 3.3 V 10%; V_P= AV_DDto 5.5 V; AGND = DGND = 0 V; T_A= T_MINto T_MAX, unless otherwise noted. Operating

temperature range is −40°C to +85°C.

Table 2.

Parameter

Limit (B Version)

Unit

Test Conditions/Comments

LE setup time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

20

10

25

10

20

ns min

DATA to CLOCK setup time

DATA to CLOCK hold time

CLOCK high duration

CLOCK low duration

CLOCK to LE setup time

LE pulse width

t₄

t₅

CLOCK

t₂

t₃

DB2

(CONTROL BIT C3)

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

DB31 (MSB)

DB30

DATA

LE

t₇

t₁

t₆

LE

Figure 2. Timing Diagram

Rev. PrI | Page 5 of 27

ADF4150

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

AV_DDto GND¹

Rating

−0.3 V to +3.9 V

−0.3 V to +0.3 V

−0.3 V to +5.8 V

−0.3 V to V_DD+ 0.3 V

−40°C to +85°C

−65°C to +125°C

150°C

AV_DDto DV_DD

V_Pto AV_DD

Digital I/O Voltage to GND

Analog I/O Voltage to GND

REF_INto GND

TRANSISTOR COUNT

23380 (CMOS) and 809 (bipolar)

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

LFCSP θ_JAThermal Impedance

(Paddle-Soldered)

ESD CAUTION

27.3°C/W

Reflow Soldering

Peak Temperature

260°C

40 sec

Time at Peak Temperature

¹GND = AGND = DGND = 0 V

Rev. PrI | Page 6 of 27

Preliminary Technical Data

ADF4150

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

CLK 1

DATA 2

LE 3

CE 4

SW 5

18 DV

DD

PDB

17

16

RF

2

AV

DD

ADF4150

TOP VIEW

15 RF

14 RF

+

−

OUT

V

6

13 AGND

P

Figure 3. Pin Configuration, 24 lead 4mm x 4 mm

Table 4. Pin Function Descriptions

No.

Mnemonic

Function

1

CLK

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

2

3

4

DATA

LE

Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high

impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register

that is selected by the three LSBs.

CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state

mode. Taking the pin high powers up the device depending on the status of the power-down bits.

5

6

SW

V_P

Fastlock Switch. A connection should be made from the loop filter to this pin when using the fastlock mode.

Charge Pump Power Supply. This should be greater than or equal to AV_DD. In systems where AV_DDis 3 V, it can

be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

7

CP

Charge Pump Output. When enabled, this provides I_CPto the external loop filter. The output of the loop filter

is connected to V_TUNEto drive the external VCO.

8

9

CP_GND

Charge Pump Ground. This is the ground return pin for CP_OUT

.

AV_DD

1

Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are to

be placed as close as possible to this pin. AV_DDmust have the same value as DV_DD

Input to the RF Input. This small signal input is ac-coupled to the external VCO.

.

10

11

RF_IN+

RF_IN−

Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small bypass

capacitor, typically 100 pF.

12,13

14

A_GND

Analog Ground. This is a ground return pin for AV_DD1 and AV_DD2.

RF_OUT

−

Complementary RF Output. The output level is programmable. The VCO fundamental output or a divided

down version is available.

15

16

RF_OUT

+

RF Output. The output level is programmable. The VCO fundamental output or a divided down version is

available.

AV_DD

2

Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are to

be placed as close as possible to this pin. AV_DD2 must have the same value as DV_DD

.

17

18

PDB_RF

DV_DD

RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.

Digital Power Supply. Should be the same voltage as AV_DD. Decoupling capacitors to the ground plane should

be placed as close as possible to this pin.

19

20

21

REF_IN

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and a dc equivalent input resistance

of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

LD

Lock Detect output pin. This pin outputs a logic high to indicate PLL lock. A logic low output indicates loss of

PLL lock.

MUXOUT

Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.

Rev. PrI | Page 7 of 27

ADF4150

Preliminary Technical Data

No.

Mnemonic

Function

22

SDV_DD

Power Supply Pin for the Digital Σ-∆ Modulator. Should be the same voltage as AV_DD. Decoupling capacitors to

the ground plane are to be placed as close as possible to this pin.

23

24

SD_GND

R_SET

Digital Σ-∆ Modulator Ground. Ground return path for the Σ-∆ Modulator.

Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage

bias at the R_SETpin is 0.55 V. The relationship between I_CPand R_SETis

25.5

I_CP

=

R_SET

where R_SET= 5.1 kΩ, I_CP= 5 mA.

Rev. PrI | Page 8 of 27

Preliminary Technical Data

ADF4150

TYPICAL PERFORMANCE CHARACTERISTICS

–0000

TBD

–0000

–000

–0000

ALL CAPS (Initial cap)

–000

ALL CAPS (Initial cap)

Figure 4

Figure 5.

–0000

TBD

–000

ALL CAPS (Initial cap)

Figure 6.

Figure 7.

–0000

TBD

–000

ALL CAPS (Initial cap)

–000

ALL CAPS (Initial cap)

Figure 8.

Figure 9.

Rev. PrI | Page 9 of 27

ADF4150

Preliminary Technical Data

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

RF N DIVIDER

N = INT + FRAC/MOD

FROM

VCO OUTPUT/

OUTPUT DIVIDERS

The reference input stage is shown in Figure 5. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed, and SW1 and SW2 are

opened. This ensures that there is no loading of the REF_INpin

on power-down.

TO PFD

N COUNTER

THIRD ORDER

FRACTIONAL

INTERPOLATOR

POWER-DOWN

CONTROL

INT

REG

MOD

REG

FRAC

VALUE

100kΩ

SW2

NC

TO R COUNTER

REF

IN

Figure 11. RF INT Divider

NC

SW1

BUFFER

SW3

INT N MODE

NO

If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the

synthesizer operates in integer-N mode. The DB8 in Register 2

(LDF) should be set to 1 to get integer-N digital lock detect.

Figure 10. Reference Input Stage

RF N DIVIDER

R COUNTER

The RF N divider allows a division ratio in the PLL feedback

path. Division ratio is determined INT, FRAC and MOD values,

which build up this divider.

The 10–bit R counter allows the input reference frequency

(REF_IN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 1023 are allowed.

INT, FRAC, MOD AND R COUNTER RELATIONSHIP

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The INT, FRAC, and MOD values, in conjunction with the R

counter, make it possible to generate output frequencies that are

spaced by fractions of the PFD frequency. See the RF

Synthesizer—A Worked Example section for more information.

The RF VCO frequency (RF_OUT) equation is

The Phase Frequency Detector (PFD) takes inputs from the R

counter and N counter and produces an output proportional to

the phase and frequency difference between them. Figure 12 is a

simplified schematic of the phase frequency detector. The PFD

includes a programmable delay element that sets the width of

the anti-backlash pulse, which can be either 6 ns (default) or 3

ns (for integer-N mode). This pulse ensures there is no dead zone

in the PFD transfer function, and gives a consistent reference spur

level.

RF_OUT= f_PFD× (INT + (FRAC/MOD))

(1)

where RF_OUTis the output frequency of external voltage

controlled oscillator (VCO).

f_PFD= REF_IN× [(1 + D)/(R × (1 + T))]

(2)

where

REF_INis the reference input frequency.

D is the REF_INdoubler bit.

T is the REF_INdivide-by-2 bit (0 or 1).

UP

HI

D1

Q1

U1

CLR1

+IN

R is the preset divide ratio of the binary 10–bit programmable

reference counter (1 to 1023).

CHARGE

PUMP

CP

U3

DELAY

DOWN

INT is the preset divide ratio of the binary 16–bit counter

(23 to 65535 for 4/5 prescaler, 75 to 65535 for 8/9 prescaler).

MOD is the preset fractional modulus (2 to 4095).

FRAC is the numerator of the fractional division (0 to MOD − 1).

CLR2

D2 Q2

HI

U2

–IN

Figure 12. PFD Simplified Schematic

Rev. PrI | Page 10 of 27

Preliminary Technical Data

ADF4150

MUXOUT AND LOCK DETECT

Table 5. C3, C2 and C1 Truth Table

The output multiplexer on the ADF4150 allows the user to

access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 (for details, see

Figure 18). Figure 13 shows the MUXOUT section in block

diagram form.

Control Bits

C3

0

C2

0

C1

0

Register

Register 0 (R0)

Register 1 (R1)

Register 2 (R2)

Register 3 (R3)

Register 4 (R4)

Register 5 (R5)

0

1

0

1

0

DV

DD

0

1

0

1

0

1

THREE-STATE-OUTPUT

DV

DD

OUTPUT STAGE

D

GND

The RF_OUT+ and RF_OUT- pins of the ADF4150 family are

connected to the collectors of an NPN differential pair driven

by buffered outputs of the VCO, as shown in Figure 14. To allow

the user to optimize the power dissipation vs. the output power

requirements, the tail current of the differential pair is

programmable by Bit D2 and Bit D1 in Register 4 (R4). Four

current levels may be set. These levels give output power levels

of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively, using a

50 Ω resistor to VDD and ac coupling into a 50 Ω load.

Alternatively, both outputs can be combined in a 1 + 1:1

transformer or a 180° microstrip coupler (see Output Matching

Section)If the outputs are used individually, the optimum

output stage consists of a shunt inductor to VDD.

R COUNTER OUTPUT

N COUNTER OUTPUT

ANALOG LOCK DETECT

MUX

CONTROL

MUX

OUT

DIGITAL LOCK DETECT

RESERVED

D

GND

Figure 13. MUXOUT Schematic

INPUT SHIFT REGISTERS

The ADF4150 digital section includes a 10–bit RF R counter,

a 16–bit RF N counter, a 12-bit FRAC counter, and a 12–bit

modulus counter. Data is clocked into the 32–bit shift register

on each rising edge of CLK. The data is clocked in MSB first.

Data is transferred from the shift register to one of six latches

on the rising edge of LE. The destination latch is determined by

the state of the three control bits (C3, C2 and C1) in the shift

register. These are the 3 LSBs, DB2, DB1, and DB0, as shown in

Figure 2. The truth table for these bits is shown in Table 5.

Figure 19 shows a summary of how the latches are programmed.

Another feature of the ADF4150 family is that the supply

current to the RF output stage can be shut down until the part

achieves lock as measured by the digital lock detect circuitry.

This is enabled by the mute-till-lock detect (MTLD) bit in

Register 4 (R4).

RF

+

RF

-

OUT

PROGRAM MODES

Table 5 and Figure 11 through Figure 21 show how the program

modes are to be set up in the ADF4150.

BUFFER/

DIVIDE-BY

1/2/4/8/16

MUX

A number of settings in the ADF4150 are double buffered.

These include the modulus value, phase value, R counter value,

reference doubler, reference divide-by-2, and current setting.

This means that two events have to occur before the part uses a

new value of any of the double buffered settings. First, the new

value is latched into the device by writing to the appropriate

register. Second, a new write must be performed on Register R0.

For example, any time the modulus value is updated, Register 0

(R0) must be written to, to ensure the modulus value is loaded

correctly. Divider select in Register 4 (R4) is also double

buffered, but only if DB13 of Register 2 (R2) is high.

Figure 14. Output Stage

Rev. PrI | Page 11 of 27

ADF4150

Preliminary Technical Data

REGISTER MAPS

REGISTER 0

CONTROL

BITS

16-BIT INTEGER VALUE (INT)

12-BIT FRACTIONAL VALUE (FRAC)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

N16 N15 N14 N13 N12 N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

F12 F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1 C3(0) C2(0) C1(0)

REGISTER 1

CONTROL

BITS

1

DBR¹

RESERVED

12-BIT PHASE VALUE (PHASE)

12-BIT MODULUS VALUE (MOD)

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

P1

P12 P11 P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

M12 M11 M10

M9

M8

M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)

REGISTER 2

MUXOUT

NOISE

MODE

CURRENT

SETTING

DBR¹

CONTROL

BITS

DBR¹

10-BIT R COUNTER

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

L2

L1

M3

M2

M1 RD2 RD1 R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4 CP3 CP2 CP1 U6

U5

U4

U3

U2

U1 C3(0) C2(1) C1(0)

REGISTER 3

CLK

DIV

MODE

RESERVED

CONTROL

BITS

12-BIT CLOCK DIVIDER VALUE

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

F3

F2

V2

V1

F1

0

C2

C1

D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1 C3(0) C2(1) C1(1)

REGISTER 4

2

DBB

DIVIDER

SELECT

OUTPUT

POWER

RESERVED

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

D13 D12 D11 D10

0

D8

D7

D6

D5

D4

D3

D2

D1 C3(1) C2(0) C1(0)

REGISTER 5

RESERVED

LD PIN

MODE

CONTROL

BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

D15 D14 C3(1) C2(0) C1(1)

0

1

0

1

2

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

DBB = DOUBLE BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0, IF AND ONLY IF DB13 OF REGISTER 2 IS HIGH.

Figure 15. Register Summary

Rev. PrI | Page 12 of 27

Preliminary Technical Data

ADF4150

CONTROL

BITS

16-BIT INTEGER VALUE (INT)

12-BIT FRACTIONAL VALUE (FRAC)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

N16

N15

N14

N13

N12

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1 C3(0) C2(0) C1(0)

F12

0

.

F11

0

.

.......... F2

F1

FRACTIONAL VALUE (FRAC)

N16

N15

...

N5

N4

N3

N2

N1

INTEGER VALUE (INT)

..........

.........

0

1

.

0

1

0

1

.

0

.

0

.

0

.

0

.

0

.

0

1

.

0

1

0

.

NOT ALLOWED

1

NOT ALLOWED

2

NOT ALLOWED

...

3

.

0

.

0

.

1

.

0

1

.

1

0

.

1

0

.

0

1

0

.

NOT ALLOWED

.

23

24

.

...

1

0

1

0

1

0

1

4092

4093

4094

4095

1

0

1

0

1

65533

65534

65535

INTmin = 75 with prescaler = 8/9

Figure 16. Register 0 (R0)

CONTROL

BITS

RESERVED

12-BIT PHASE VALUE (PHASE)

12-BIT MODULUS VALUE (MOD)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

P1

P12

P11

P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

M12 M11 M10

M9

M8

M7 M6

M5

M4

M3

M2

M1 C3(0) C2(0) C1(1)

P1

0

PRESCALER

P12

P11

.......... P2

P1

0

1

0

1

.

PHASE VALUE (PHASE)

M12

M11

..........

M2

M1

INTERPOLATOR MODULUS (MOD)

4/5

8/9

0

.

0

.

..........

0

1

.

0

.

0

.

..........

1

.

0

1

.

2

1

3

1 (RECOMMENDED)

.

2

.

3

.

1

0

1

0

1

0

1

4092

4093

4094

4095

.

1

0

1

0

1

0

1

4092

4093

4094

4095

Figure 17. Register 1 (R1)

Rev. PrI | Page 13 of 27

ADF4150

Preliminary Technical Data

NOISE

MODE

CURRENT

SETTING

CONTROL

BITS

MUXOUT

10-BIT R COUNTER

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

L2

L1

M3

M2

M1 RD2 RD1 R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4 CP3 CP2 CP1 U6

U5

U4

U3

U2

U1 C3(0) C2(1) C1(0)

REFERENCE

RD2

COUNTER

RESET

DOUBLEBUFFER

R4 DB22-20

U1

L1

0

L2

NOISE MODE

DOUBLER

D1

U6

0

LDF

0

1

DISABLED

ENABLED

0

1

0

1

LOW NOISE MODE

RESERVED

FRAC-N

INT-N

0

1

DISABLED

ENABLED

0

1

DISABLED

ENABLED

0

1

RESERVED

RD1 REFERENCE DIVIDE BY 2

CP

1

LOW SPUR MODE

I

(mA)

CP

U2

U5

LDP

THREE-STATE

0

1

DISABLED

ENABLED

CP4

0

CP3

CP2

0

CP1

5.1kΩ

0.31

0.63

0.94

1.25

1.56

1.88

2.19

2.50

2.81

3.13

3.44

3.75

4.06

4.38

4.69

5.00

0

1

10ns

6ns

0

1

DISABLED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

ENABLED

0

1

R10

R9

..........

R2

R1

R DIVIDER (R)

0

1

U3

POWER DOWN

U4

0

PD POLARITY

NEGATIVE

POSITIVE

0

.

0

.

..........

0

1

.

1

0

.

1

0

1

DISABLED

ENABLED

0

2

1

0

1

.

0

1

.

1

0

.

1

0

1

0

1

0

1

0

1

1020

1021

1022

1023

1

0

1

0

1

M3

M2

0

M1

0

OUTPUT

0

1

THREE-STATE OUTPUT

DV_DD

0

1

0

DGND

1

R DIVIDER OUTPUT

N DIVIDER OUTPUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

RESERVED

0

1

0

1

Figure 18. Register 2 (R2)

CLK

DIV

MODE

CONTROL

BITS

RESERVED

12-BIT CLOCK DIVIDER VALUE

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

F3

F2

0

F1

0

C2

C1

D12 D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1 C3(0) C2(1) C1(1)

0

D12

D11

.......... D2

D1

CLOCK DIVIDER VALUE

CYCLE SLIP

REDUCTION

F1

0

.

0

.

..........

0

1

.

0

1

0

1

.

0

1

DISABLED

ENABLED

1

2

3

.

C2

0

C1

CLOCK DIVIDER MODE

CLOCK DIVIDER OFF

FASTLOCK ENABLE

RESYNC ENABLE

RESERVED

.

0

1

0

1

0

1

0

1

0

1

4092

4093

4094

4095

0

1

CHARGE

CANCELLATION

F2

0

1

DISABLED

ENABLED

ANTI-BACKLASH

PULSE WIDTH

F3

0

1

6 ns (FRAC-N)

3 ns (INT_N)

Figure 19. Register 3 (R3)

Rev. PrI | Page 14 of 27

Preliminary Technical Data

ADF4150

OUTPUT

POWER

CONTROL

BITS

DIVIDER

SELECT

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

D13 D12 D11 D10

0

D8

0

D3

D2

D1 C3(1) C2(0) C1(0)

FEEDBACK

SELECT

D13

D2

0

D1

0

OUTPUT POWER

0

1

-4

DIVIDED

FUNDAMENTAL

0

1

-1

1

0

+2

+5

MUTE TILL

LOCK DETECT

D12

D11

D10

RF DIVIDER SELECT

1

D8

0

1

0

1

0

1

0

1

0

/1

MUTE DISABLED

MUTE ENABLED

/2

1

/4

D3

0

RF OUT

/8

DISABLED

ENABLED

/16

1

Figure 20. Register 4 (R4)

LD PIN

MODE

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

D15

D14

0

1

0

C3(1) C2(0) C1(1)

D15

D14

LOCK DETECT PIN OPERATION

0

1

0

1

0

1

LOW

DIGITAL LOCK DETECT

LOW

HIGH

Figure 21. Register 5 (R5)

Rev. PrI | Page 15 of 27

ADF4150

Preliminary Technical Data

12-Bit PHASE Value

REGISTER 0

These bits control what is loaded as the PHASE word. The word

must be less than the MOD value programmed in Register 1.

The word is used to program the RF output phase from 0° to

360° with a resolution of 360°/MOD. See the PHASE Resync

section for more information. In most applications, the phase

relationship between the RF signal and the reference is not

important. In such applications, the PHASE value can be used

to optimize the fractional and subfractional spur levels. See the

Spur Consistency and Fractional Spur Optimization section for

more information.

Control Bits

With Bits [C3:C1] set to 0, 0, 0, Register 0 is programmed.

Figure 16 shows the input data format for programming this

register.

16-Bit INT Value

These sixteen bits set the INT value, which determines the

integer part of the feedback division factor. It is used in

Equation 1 (see the INT, FRAC, MOD and R Counter

Relationship section). All integer values from 23 to 65,535 are

allowed for 4/5 prescaler. For 8/9 prescaler, the minimum

integer value is 75.

If neither the PHASE resync nor the spurious optimization

functions are being used, it is recommended the PHASE word

be set to 1.

12-Bit FRAC Value

The 12 FRAC bits set the numerator of the fraction that is input

to the Σ-Δ modulator. This, along with INT, specifies the new

frequency channel that the synthesizer locks to, as shown in the

RF Synthesizer—A Worked Example section. FRAC values from

0 to MOD − 1 cover channels over a frequency range equal to

the PFD reference frequency.

12-Bit Interpolator MOD Value

This programmable register sets the fractional modulus. This is

the ratio of the PFD frequency to the channel step resolution on

the RF output. Please refer to the RF Synthesizer—A Worked

Example section for more information.

REGISTER 2

REGISTER 1

Control Bits

Control bits

With Bits [C3:C1] set to 0, 1, 0, Register 2 is programmed.

Figure 18 shows the input data format for programming this

register.

With Bits [C3:C1] set to 0, 0, 1, Register 1 is programmed.

Figure 17 shows the input data format for programming this

register.

Noise and Spur Modes

Prescaler Value

The noise modes on the ADF4150 are controlled by DB30 and

DB29 in Register 2 (see Figure 18). The noise modes allow the

user to optimize a design either for improved spurious

performance or for improved phase noise performance.

The dual modulus prescaler (P/P + 1), along with the INT,

FRAC, and MOD counters, determines the overall division ratio

from the VCO output to the PFD input.

Operating at CML levels, it takes the clock from the VCO

output and divides it down for the counters. It is based on a

synchronous 4/5 core. When set to 4/5, the maximum RF

frequency allowed is 3 GHz. Therefore, when operating the

ADF4150 above 3 GHz, this must be set to 8/9. The prescaler

limits the INT value, where:

When the lowest spur setting is chosen, dither is enabled. This

randomizes the fractional quantization noise so it resembles

white noise rather than spurious noise. As a result, the part is

optimized for improved spurious performance. This operation

would normally be used when the PLL closed-loop bandwidth

is wide, for fast-locking applications. (Wide loop bandwidth is

seen as a loop bandwidth greater than 1/10 of the RF_OUTchannel

step resolution (f_RES)). A wide loop filter does not attenuate the

spurs to the same level as a narrow loop bandwidth.

P = 4/5, N_MIN= 23

P = 8/9, N_MIN= 75

In the ADF4150 P1 in Register 1 sets the prescaler values.

For best noise performance, use the lowest noise setting option.

As well as disabling the dither, it also ensures that the charge

pump is operating in an optimum region for noise performance.

This setting is extremely useful where a narrow loop filter band-

width is available. The synthesizer ensures extremely low noise

and the filter attenuates the spurs. The typical performance

characteristics give the user an idea of the trade-off in a typical

WCDMA setup for the different noise and spur settings.

Rev. PrI | Page 16 of 27

Preliminary Technical Data

ADF4150

MUXOUT

Lock Detect Precision (LDP)

The on-chip multiplexer is controlled by Bits [DB28:DB26](see

Figure 18).

When DB7 is set to 0, 40 consecutive PFD cycles of 10 ns must

occur before digital lock detect is set. When this bit is

programmed to 1, 40 consecutive reference cycles of 6 ns must

occur before digital lock detect is set. When DB8 is set to 0, the

fractional-N digital lock detect is activated. When DB8 is set to

1, the integer–N digital lock detect is activated. In this case,

setting DB7 to 0 causes three consecutive cycles of 15 ns to

occur before digital lock detect is set. When this bit is set to 1,

five consecutive cycles of 15 ns must occur.

Reference Doubler

Setting DB25 to 0 feeds the REF_INsignal directly to the 10–bit R

counter, disabling the doubler. Setting this bit to 1 multiplies the

REF_INfrequency by a factor of 2 before feeding into the 10–bit R

counter. When the doubler is disabled, the REF_INfalling edge is

the active edge at the PFD input to the fractional synthesizer.

When the doubler is enabled, both the rising and falling edges

of REF_INbecome active edges at the PFD input.

Phase Detector Polarity

DB6 sets the phase detector polarity. When a passive loop filter,

or non-inverting active loop filter us used, this should be set to

1. If an active filter with an inverting characteristic is used, it

should be set to 0.

When the doubler is enabled and the lowest spur mode is

chosen, the in-band phase noise performance is sensitive to the

REF_INduty cycle. The phase noise degradation can be as much

as 5 dB for the REF_INduty cycles outside a 45% to 55% range.

The phase noise is insensitive to the REF_INduty cycle in the

lowest noise mode. The phase noise is insensitive to REF_INduty

cycle when the doubler is disabled.

Power-Down

DB5 provides the programmable power-down mode. Setting this

bit to 1 performs a power-down. Setting this bit to 0 returns the

synthesizer to normal operation. When in software power-down

mode, the part retains all information in its registers. Only if the

supply voltages are removed are the register contents lost.

The maximum allowable REF_INfrequency when the doubler is

enabled is 30 MHz.

RDIV2

Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop

between the R counter and PFD, which extends the maximum

REF_INinput rate. This function allows a 50% duty cycle signal to

appear at the PFD input, which is necessary for cycle slip

reduction.

When a power-down is activated, the following events occur:

•

The synthesizer counters are forced to their load state

conditions.

•

The charge pump is forced into three-state mode.

The digital lock detect circuitry is reset.

The RF_OUTbuffers are disabled.

10–Bit R Counter

The 10–bit R counter allows the input reference frequency

(REF_IN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 1023 are allowed.

The input register remains active and capable of loading

and latching data.

Charge Pump Three-State

Double Buffer

DB4 puts the charge pump into three-state mode when

DB13 enables or disables double buffering of Bits [DB22:DB20]

in Register 4. The Divider Select section explains how double

buffering works.

programmed to 1. It should be set to 0 for normal operation.

Counter Reset

DB3 is the R counter and N counter reset bit for the ADF4150.

When this is 1, the RF synthesizer N counter and R counter are

held in reset. For normal operation, this bit should be set to 0.

Charge Pump Current Setting

Bits [DB12:DB09] set the charge pump current setting. This

should be set to the charge pump current that the loop filter is

designed with (see Figure 18).

REGISTER 3

Control Bits

LDF

With Bits [C3:C1] set to 0, 1, 1, Register 3 is programmed.

Figure 19 shows the input data format for programming this

register.

Setting DB8 to 1 enables integer–N digital lock detect, when

FRAC part of the divider is zero; setting DB8 to 0 enables

fractional–N digital lock detect.

Rev. PrI | Page 17 of 27

ADF4150

Preliminary Technical Data

Anti-backlash pulse width

Mute-till-Lock Detect

Setting DB22 bit to 0 sets the PFD anti-backlash pulse width to

6 ns. This is the recommended mode for fractional-N use.

Setting this bit to 1, the 3 ns pulse-width is used and will result

in a phase noise and spur improvement in integer-N operation.

For fractional-N mode it is not recommended to use this

smaller setting.

If DB10 is set to 1, the supply current to the RF output stage is shut

down until the part achieves lock as measured by the digital lock

detect circuitry.

RF Output Enable

DB5 enables or disables primary RF output, depending on the

chosen value.

Charge cancellation mode pulse width

Output Power

Setting this bit to 1 enables charge pump charge cancellation.

This has the effect of reducing PFD spurs in Integer-N mode. In

fractional-N mode this should not be used and the relevant

result in a phase noise and spur improvement. For fractional-N

mode it is not recommended to use this smaller setting.

DB4 and DB3 set the value of the primary RF output power

level (see Figure 20).

REGISTER 5

Control Bits

CSR Enable

With Bits [C3:C1] set to 1, 0, 1, Register 5 is programmed.

Figure 21 shows the input data form for programming this

register.

Setting this bit to 1 enables cycle slip reduction. This is a

method for improving lock times. Note that the signal at the

phase frequency detector (PFD) must have a 50% duty cycle for

cycle slip reduction to work. The charge pump current setting

must also be set to a minimum. See the Cycle Slip Reduction for

Faster Lock Time section for more information.

Lock Detect PIN Operation

Bits [DB32:DB22] set the operation of the lock detect PIN (see

Figure 21).

INITIALIZATION SEQUENCE

Clock Divider Mode

The following sequence of registers is the correct sequence for

initial power up of the ADF4150 after the correct application of

voltages to the supply pins:

Bits [DB16:DB15] must be set to 1, 0 to activate PHASE resync

or 0, 1 to activate fast lock. Setting Bits [DB16:DB15] to 0, 0

disables the clock divider. See Figure 19.

•

Register 5

Register 4

Register 3

Register 2

Register 1

Register 0

12-Bit Clock Divider Value

The 12-bit clock divider value sets the timeout counter for

activation of PHASE resync. See the PHASE Resync section for

more information. It also sets the timeout counter for fast lock.

See the Fast-Lock Timer and Register Sequences section for

more information.

REGISTER 4

Control Bits

With Bits [C3: C1] set to 1, 0, 0, Register 4 is programmed.

Figure 20 shows the input data format for programming this

register.

Feedback Select

DB23 selects the feedback from VCO output to the N-counter.

When set to 1, the signal is taken from the VCO directly. When set

to 0, it is taken from the output of the Output dividers. The dividers

enable covering of the wide frequency band (137.5 MHz – 4.4

GHz). When the divider is enabled and the feedback signal is

taken from the output, the RF output signals of two separately

configured PLLs are in phase. This is useful in some

applications where the positive interference of signals is

required to increase the power.

Divider Select

Bits [DB22:DB20] select the value of the output divider (see

Figure 20).

Rev. PrI | Page 18 of 27

Preliminary Technical Data

ADF4150

200 kHz (13 MHz/65) necessary for GSM. With dither off, the

RF SYNTHESIZER— A WORKED EXAMPLE

fractional spur interval depends on the modulus values chosen (see

Table 6).

The following is an example how to program the ADF4150

synthesizer:

REFERENCE DOUBLER AND REFERENCE DIVIDER

RF_OUT= [INT + (FRAC/MOD)] × [f_PFD]/RFDivider

(3)

The reference doubler on-chip allows the input reference signal

to be doubled. This is useful for increasing the PFD comparison

frequency. Making the PFD frequency higher improves the

noise performance of the system. Doubling the PFD frequency

usually improves noise performance by 3 dB. It is important to

note that the PFD cannot operate above 32 MHz due to a

limitation in the speed of the Σ-Δ circuit of the N-divider.

where:

RF_OUTis the RF frequency output.

INT is the integer division factor.

FRAC is the fractionality.

MOD is the modulus.

RF Divider is the output divider that divides down the VCO

frequency.

The reference divide-by-2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency. This is necessary

for the correct operation of the cycle slip reduction (CSR)

function. See the Cycle Slip Reduction for Faster Lock Times

section for more information.

f_PFD= REF_IN× [(1 + D)/(R × (1+T))]

(4)

where:

REF_INis the reference frequency input.

D is the RF REF_INdoubler bit.

T is the reference divide-by-2 bit (0 or 1).

R is the RF reference division factor.

12-BIT PROGRAMMABLE MODULUS

Unlike most other fractional-N PLLs, the ADF4150 allows the

user to program the modulus over a 12–bit range. This means

the user can set up the part in many different configurations for

the application, when combined with the reference doubler and

the 10–bit R counter.

For example, in a UMTS system, where 2112.6 MHz RF

frequency output (RF_OUT) is required, a 10 MHz reference

frequency input (REF_IN) is available, and a 200 kHz channel

resolution (f_RESOUT) is required, on the RF output. A 2.1 GHz

VCO would be suitable, but a 4.2 GHz VCO would be suitable

also. In the second case, the RF divider of 2 should be used

(VCO frequency = 4225.2 MHz, RF_OUT= VCO frequency/RF

Divider = 4225.2 MHz/2 = 2112.6 MHz).

For example, consider an application that requires 1.75 GHz RF

and 200 kHz channel step resolution. The system has a 13 MHz

reference signal.

One possible setup is feeding the 13 MHz directly to the PFD

and programming the modulus to divide by 65. This results in

the required 200 kHz resolution.

It is also important where the loop is closed. In this example the

loop is closed as depicted in Figure 18 (from Out Divider).

f_PFD

RF

OUT

PFD

VCO

Another possible setup is using the reference doubler to create

26 MHz from the 13 MHz input signal. This 26 MHz is then fed

into the PFD programming the modulus to divide by 130. This

also results in 200 kHz resolution and offers superior phase

noise performance over the previous setup.

÷2

N

DIVIDER

Figure 22. Loop closed before output divider

The programmable modulus is also very useful for multi-

standard applications. If a dual-mode phone requires PDC

and GSM 1800 standards, the programmable modulus is a

great benefit. PDC requires 25 kHz channel step resolution,

whereas GSM 1800 requires 200 kHz channel step resolution.

200 kHz channel resolution (f_RESOUT) is required at the output of

the RF divider. Therefore, channel resolution at the output of

the VCO (f_RES) is to be twice the f_RESOUT, that is 400kHz.

MOD = REF_IN/f_RES

MOD = 10 MHz/400 kHz = 25

A 13 MHz reference signal can be fed directly to the PFD, and

the modulus can be programmed to 520 when in PDC mode

(13 MHz/520 = 25 kHz).

From Equation 4

f_PFD= [10 MHz × (1 + 0)/1] = 10 MHz

(5)

(6)

2112.6 MHz = 10 MHz × (INT + FRAC/25)/2

The modulus needs to be reprogrammed to 65 for GSM 1800

operation (13 MHz/65 = 200 kHz).

where:

INT = 422

FRAC = 13

It is important that the PFD frequency remain constant (13 MHz).

This allows the user to design one loop filter for both setups

without running into stability issues. It is important to

remember that the ratio of the RF frequency to the PFD

frequency principally affects the loop filter design, not the

actual channel spacing.

MODULUS

The choice of modulus (MOD) depends on the reference signal

(REF_IN) available and the channel resolution (f_RES) required at

the RF output. For example, a GSM system with 13 MHz REF_INsets

the modulus to 65. This means the RF output resolution (f_RES) is the

Rev. PrI | Page 19 of 27

ADF4150

Preliminary Technical Data

CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES

FAST-LOCK TIMER AND REGISTER SEQUENCES

As outlined in the Noise and Spur Mode section, the ADF4150

contains a number of features that allow optimization for noise

performance. However, in fast locking applications, the loop

bandwidth generally needs to be wide, and therefore, the filter

does not provide much attenuation of the spurs. If the cycle slip

reduction feature is enabled, the narrow loop bandwidth is

maintained for spur attenuation but faster lock times are still

possible.

If the fast-lock mode is used, a timer value is to be loaded into

the PLL to determine the duration of the wide bandwidth mode.

When Bits [DB16:DB15] in Register 3 are set to 0, 1 (fast lock

enable), the timer value is loaded by the 12–bit clock divider

value. The following sequence must be programmed to use fast

lock:

1) Initialization sequence (see the Initialization Sequence

section); occurs only once after powering up the part.

Cycle Slips

2) Load Register 3 by setting Bits [DB16:DB15] to 0, 1 and the

chosen fast-lock timer value [DB14:DB3]. Note that the

duration the PLL remains in wide bandwidth is equal to

Cycle slips occur in integer-N/fractional-N synthesizers when

the loop bandwidth is narrow compared to the PFD frequency.

The phase error at the PFD inputs accumulates too fast for the

PLL to correct, and the charge pump temporarily pumps in the

wrong direction. This slows down the lock time dramatically.

The ADF4150 contains a cycle slip reduction feature that

extends the linear range of the PFD, allowing faster lock times

without modifications to the loop filter circuitry.

the fast-lock timer/f_PFD

.

FAST LOCK—AN EXAMPLE

If a PLL has reference frequencies of 13 MHz and f_PFD= 13 MHz

and a required lock time of 50 µs, the PLL is set to wide bandwidth

for 40 µs. This example assumes a modulus of 65 for channel

spacing of 200 kHz.

When the circuitry detects that a cycle slip is about to occur, it

turns on an extra charge pump current cell. This outputs a

constant current to the loop filter, or removes a constant current

from the loop filter (depending on whether the VCO tuning

voltage needs to increase or decrease to acquire the new

frequency). The effect is that the linear range of the PFD is

increased. Loop stability is maintained because the current is

constant and is not a pulsed current.

If the time period set for the wide bandwidth is 40 µs, then

Fast-Lock Timer Value = Time in Wide Bandwidth × f_PFD

/MOD

Fast-Lock Timer Value = 40 µs × 13 MHz / 65 = 8

Therefore, 8 must be loaded into the clock divider value in

Register 3 in Step 1 of the sequence described in the Fast-Lock

Timer and Register Sequences section.

If the phase error increases again to a point where another cycle

slip is likely, the ADF4150 turns on another charge pump cell.

This continues until the ADF4150 detects the VCO frequency

has gone past the desired frequency. The extra charge pump

cells are turned off one by one until all the extra charge pump

cells have been disabled and the frequency is settled with the

original loop filter bandwidth.

FAST LOCK—LOOP FILTER TOPOLOGY

In order to use fast-lock mode, the damping resistor in the loop

filter is reduced to ¼ of its value while in wide bandwidth mode.

To achieve the wider loop filter bandwidth, the charge pump

current increases by a factor of 16, and to maintain loop

stability the damping resistor must be reduced a factor of ¼. To

enable fast lock, the SW pin is shorted to the GND pin by

settings Bits [DB16:DB15] in Register 3 to 0, 1. The following

two topologies are available:

Up to seven extra charge pump cells can be turned on. In most

applications, it is enough to eliminate cycle slips altogether,

giving much faster lock times.

Setting Bit DB18 in the Register 3 to 1 enables cycle slip

reduction. Note that the PFD requires a 45% to 55% duty cycle

for CSR to operate correctly.

•

The damping resistor (R1) is divided into two values (R1

and R1A) that have a ratio of 1:3 (see Figure 23).

•

An extra resistor (R1A) is connected directly from SW, as

shown in Figure 24. The extra resistor is calculated such

that the parallel combination of an extra resistor and the

damping resistor (R1) is reduced to ¼ of the original value

of R1 (see Figure 24).

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow loop bandwidths can filter unwanted spurious signals,

but these usually have a long lock time. A wider loop bandwidth

will achieve faster lock times, but a wider loop bandwidth may

lead to increased spurious signals inside the loop bandwidth.

The fast lock feature can achieve the same fast lock time as the

wider bandwidth, but with the advantage of a narrow final loop

bandwidth to keep spurs low.

Rev. PrI | Page 20 of 27

Preliminary Technical Data

ADF4150

Integer Boundary Spurs

R2

CP

VCO

Another mechanism for fractional spur creation is the

interactions between the RF VCO frequency and the reference

frequency. When these frequencies are not integer related (the

point of a fractional-N synthesizer) spur sidebands appear on

the VCO output spectrum at an offset frequency that

C1

C2

R1

C3

SW

R1A

corresponds to the beat note or difference frequency between an

integer multiple of the reference and the VCO frequency. These

spurs are attenuated by the loop filter and are more noticeable

on channels close to integer multiples of the reference where the

difference frequency can be inside the loop bandwidth, hence

the name integer boundary spurs.

Figure 23. Fast-Lock Loop Filter Topology—Topology 1

ADF4150

R2

CP

VCO

C1

C2

R1

C3

Reference Spurs

R1A

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feed-through mechanism

that bypasses the loop may cause a problem. Feed through of

low levels of on-chip reference switching noise, through the

RF_INpin back to the VCO, can result in reference spur levels as

high as –90 dBc. PCB layout needs to ensure adequate isolation

between VCO traces and the input reference to avoid a possible

feed through path on the board.

SW

Figure 24. Fast-Lock Loop Filter Topology—Topology 2

SPUR MECHANISMS

This section describes the three different spur mechanisms that

arise with a fractional-N synthesizer and how to minimize them

in the ADF4150.

SPUR CONSISTENCY AND FRACTIONAL SPUR

OPTIMIZATION

Fractional Spurs

The fractional interpolator in the ADF4150 is a third order Σ-Δ

modulator (SDM) with a modulus (MOD) that is programmable

to any integer value from 2 to 4095. In low spur mode (dither

enabled) the minimum allowable value of MOD is 50. The SDM

is clocked at the PFD reference rate (f_PFD) that allows PLL output

frequencies to be synthesized at a channel step resolution of

f_PFD/MOD.

With dither off, the fractional spur pattern due to the

quantization noise of the SDM also depends on the particular

PHASE word with which the modulator is seeded.

The PHASE word can be varied to optimize the fractional and

subfractional spur levels on any particular frequency. Thus, a

look-up table of PHASE values corresponding to each frequency

can be constructed for use when programming the ADF4150.

In low noise mode (dither off), the quantization noise from the

Σ-Δ modulator appears as fractional spurs. The interval between

spurs is f_PFD/L, where L is the repeat length of the code sequence

in the digital Σ-Δ modulator. For the third-order modulator

used in the ADF4150, the repeat length depends on the value of

MOD, as listed in Table 6.

If a look-up table is not used, keep the PHASE word at a constant

value to ensure consistent spur levels on any particular frequency.

PHASE RESYNC

The output of a fractional-N PLL can settle to any one of the

MOD phase offsets with respect to the input reference, where

MOD is the fractional modulus. The PHASE resync feature in

the ADF4150 produces a consistent output phase offset with

respect to the input reference. This is necessary in applications

where the output phase and frequency are important, such as

digital beam forming. See the PHASE Programmability section for

how to program a specific RF output phase when using PHASE

resync.

Table 6. Fractional Spurs with Dither Off

Repeat

Length

Condition (Dither Off)

Spur Interval

Channel step/2

Channel step/3

Channel step/6

Channel step

If MOD is divisible by 2, but not 3 2 × MOD

If MOD is divisible by 3, but not 2 3 × MOD

If MOD is divisible by 6

Otherwise

6 × MOD

MOD

PHASE resync is enabled by setting Bits [DB16:DB15] in

Register 3 to 1, 0. When PHASE resync is enabled, an internal

timer generates sync signals at intervals of t_SYNCgiven by the

following formula:

In low spur mode (dither enabled), the repeat length is

extended to 2²¹cycles, regardless of the value of MOD, which

makes the quantization error spectrum look like broadband

noise. This may degrade the in-band phase noise at the PLL

output by as much as 10 dB. For lowest noise, dither off is a

better choice, particularly when the final loop bandwidth is low

enough to attenuate even the lowest frequency fractional spur.

t_SYNC= CLK_DIV_VALUE × MOD × t_PFD

where:

t_PFDis the PFD reference period.

Rev. PrI | Page 21 of 27

ADF4150

Preliminary Technical Data

CLK_DIV_VALUE is the decimal value programmed in Bits

[DB14:DB3] of Register 3, and can be any integer in the range of

1 to 4095.

LE

t_SYNC

SYNC

(Internal)

LAST CYCLE SLIP

MOD is the modulus value programmed in Bits [DB14:DB3] of

Register 1 (R1).

FREQUENCY

When a new frequency is programmed, the second sync pulse

after the LE rising edge is used to resynchronize the output

phase to the reference. The t_SYNCtime is to be programmed to a

value that is as least as long as the worst-case lock time. This

guarantees the PHASE resync occurs after the last cycle slip in

the PLL settling transient.

PLL SETTLES TO

INCORRECT PHASE

PLL SETTLES TO

CORRECT PHASE

AFTER RESYNC

PHASE

In the example shown in Figure 25, the PFD reference is 25 MHz

and MOD = 125 for a 200 kHz channel spacing. t_SYNCis set to

400 µs by programming CLK_DIV_VALUE = 80.

–100

0

100 200 300 400 500 600 700 800 900 1000

TIME (µs)

Figure 25. PHASE Resync Example

PHASE Programmability

The PHASE word in Register 1 controls the RF output phase,.

As this word is swept from 0 to MOD, the RF output phase

sweeps over a 360^orange in steps of 360^o/MOD.

Rev. PrI | Page 22 of 27

Preliminary Technical Data

ADF4150

APPLICATIONS INFORMATION

DIRECT CONVERSION MODULATOR

The LO ports of the AD5375 can be driven differentially from

the complementary RF_OUTA and RF_OUTB outputs of the

ADF4150. This gives better performance than a single-ended

LO driver and eliminates the use of a balun to convert from a

single-ended LO input to the more desirable differential LO

inputs for the AD5375. The typical rms phase noise (100 Hz to 5

MHz) of the LO in this configuration is 0.61° rms.

Direct conversion architectures are increasingly being used to

implement base station transmitters. Figure 26 shows how Analog

Devices, Inc. parts can be used to implement such a system.

The circuit block diagram shows the AD9788 TxDAC® being

used with the ADL5375. The use of dual integrated DACs, such

as the AD9788 with its specified 0.02 dB and 0.004 dB gain

and offset matching characteristics, ensures minimum error

contribution (over temperature) from this portion of the

signal chain.

The ADL5375 accepts LO drive levels from −10 dBm to 0 dBm.

The optimum LO power can be software programmed on the

ADF4150, which allows levels from −4 dBm to +5 dBm from

each output.

The local oscillator(LO) is implemented using the ADF4150.

The low-pass filter was designed using ADIsimPLL for a channel

spacing of 200 kHz and a closed-loop bandwidth of 35 kHz.

The RF output is designed to drive a 50 Ωload but must be

ac-coupled, as shown in Figure 26. If the I and Q inputs are

driven in quadrature by 2 V p-p signals, the resulting output

power from the modulator is approximately 2 dBm.

51Ω

REFIO

IOUTA

IOUTB

LOW-PASS

FILTER

MODULATED

DIGITAL

DATA

AD9788

TxDAC

QOUTA

QOUTB

LOW-PASS

FILTER

FSADJ

51Ω

2kΩ

IBBP

LOCK

DETECT

V_DD

ADL5375

V_VCO

IBBN

9

17

21

20

18

16

4

6

22

3.9nH

MUXOUT LD

PDB_RF

SDV_DD

VP

AV_DDDV_DDAV_DDCE

1nF

LOIP

1nF 1nF

RFOUT

DSOP

QUADRATURE

PHASE

SPLITTER

RF_OUT

+

15

14

FREF_IN

REF_IN

19

51Ω

LOIN

RF_OUT

–

1

2

3

CLK

DATA

LE

V_VCO

V_CC

1nF

VCO

QBBN

QBBP

100pF

ADF4150

RF_IN

+

10

11

VCO_OUT

V_TUNE

24 R_SET

–

4.7kΩ

680Ω

CP

7

39nF

2700pF

1200pF

360Ω

SW

5

CP_GNDAGND

12

AGND SD_GND

13

8

23

Figure 26 Direct Conversion Modulator

Rev. PrI | Page 23 of 27

ADF4150

Preliminary Technical Data

INTERFACING

SCLOCK

CLK

The ADF4150 family has a simple SPI®-compatible serial

interface for writing to the device. CLK, DATA, and LE control

the data transfer. When LE goes high, the 32 bits that have been

clocked into the appropriate register on each rising edge of CLK

are transferred to the appropriate latch. See Figure 2 for the

timing diagram and Table 5 for the register address table.

MOSI

TFS

SDATA

LE

ADF4150

ADSP-21xx

CE

I/O PORTS

MUXOUT

(Lock Detect)

ADuC812 Interface

Figure 27 shows the interface between the ADF4150 family and

the ADuC812 MicroConverter®. Because the ADuC812 is based

on an 8051 core, this interface can be used with any 8051 based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4150 family

needs a 32-bit word, which is accomplished by writing four

8-bit bytes from the MicroConverter to the device. When the

fourth byte has been written, the LE input should be brought

high to complete the transfer.

Figure 28. ADSP-21xx to ADF4150 Interface

Set up the word length for 8 bits and use four memory locations for

each 32-bit word. To program each 32-bit latch, store the 8-bit

bytes, enable the autobuffered mode, and write to the transmit

register of the DSP. This last operation initiates the autobuffer

transfer.

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

The lands on the chip scale package (CP-24-3) are rectangular.

The PCB pad for these is to be 0.1 mm longer than the package

land length and 0.05 mm wider than the package land width.

The land is to be centered on the pad. This ensures the solder

joint size is maximized. The bottom of the chip scale package

has a central thermal pad.

SCLOCK

MOSI

CLK

SDATA

ADuC812

LE

ADF4150

I/O PORTS

CE

The thermal pad on the PCB is to be at least as large as the

exposed pad. On the PCB, there is to be a minimum clearance

of 0.25 mm between the thermal pad and the inner edges of the

pad pattern. This ensures that shorting is avoided.

MUXOUT

(Lock Detect)

Figure 27. ADuC812 to ADF4150 Interface

Thermal vias can be used on the PCB thermal pad to improve

the thermal performance of the package. If vias are used, they

are to be incorporated in the thermal pad at 1.2 mm pitch grid.

The via diameter is to be between 0.3 mm and 0.33 mm, and the

via barrel is to be plated with one ounce copper to plug the via.

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and detect lock (MUXOUT configured as lock

detect and polled by the port input). When operating in the

described mode, the maximum SCLOCK rate of the ADuC812

is 4 MHz. This means that the maximum rate at which the

output frequency can be changed is 125 kHz.

ADSP-21xx Interface

Figure 28 shows the interface between the ADF4150 family and

the ADSP-21xx digital signal processor. The ADF4150 family

needs a 32-bit serial word for each latch write. The easiest way

to accomplish this using the ADSP-21xx family is to use the

autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block

of serial data before an interrupt is generated.

Rev. PrI | Page 24 of 27

Preliminary Technical Data

ADF4150

OUTPUT MATCHING

There are a number of ways to match the output of the ADF4150

for optimum operation; the most basic is to use a 50 Ω resistor to

AV_DD. A dc bypass capacitor of 100 pF is connected in series as

shown in Figure 29. Because the resistor is not frequency

dependent, this provides a good broadband match. The output

power in this circuit into a 50 Ω load typically gives values

chosen by Bit D2 and Bit D1 in Register 4 (R4).

AV

DD

50Ω

100pF

RF

OUT

50Ω

Figure 29. Simple ADF4150 Output Stage

A better solution is to use a shunt inductor (acting as an RF

choke) to AV_DD. This gives a better match and, therefore, more

output power.

Experiments have shown the circuit shown in Figure 30

provides an excellent match to 50 Ω for the WCDMA UMTS

Band 1 (2110 – 2170 MHz). The maximum output power in

that case is about 7 dBm. Both single-ended architectures can be

examined using the EVAL-ADF4150EB1Z evaluation board.

AV

DD

3.9nH

1nF

RF

OUT

50Ω

Figure 30.Optimum ADF4150 Output Stage

If differential outputs are not needed, the unused output can be

terminated or combined with both outputs using a balun.

Rev. PrI | Page 25 of 27

ADF4150

Preliminary Technical Data

OUTLINE DIMENSIONS

4.10

4.00 SQ

3.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

24

19

18

0.50

BSC

1

2.65

2.50 SQ

2.45

EXPOSED

PAD

13

12

6

7

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

Figure 31. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Dimensions shown in millimeters(Package drawing subject to change).

ORDERING GUIDE

Model

ADF4150BCPZ¹

ADF4150BCPZ-RL7¹

EVAL-ADF4150EB1Z¹

Temperature Range

−40°C to +85°C

Package Description

Package Option

CP-24-7

24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board

CP-24-7

¹Z = RoHS Compliant Part.

Rev. PrI | Page 26 of 27

Preliminary Technical Data

NOTES

ADF4150

Rev. PrI | Page 27 of 27

PR08226-0-4/09(PrI)


型号：	ADF4150
厂家：	ADI
描述：	Fractional-N/Integer-N PLL Synthesizer 小数N /整数N分频PLL合成器
文件：	总27页 (文件大小：316K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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