ADF41513_V01 [ADI]
26.5 GHz, Integer N/Fractional-N, PLL Synthesizer;
| 型号： | ADF41513_V01 |
| 厂家： | 
ADI |
| 描述： | 26.5 GHz, Integer N/Fractional-N, PLL Synthesizer |
| 文件： | 总30页 (文件大小：1391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
26.5 GHz, Integer N/Fractional-N,
PLL Synthesizer
Data Sheet
ADF41513
FEATURES
GENERAL DESCRIPTION
1 GHz to 26.5 GHz bandwidth
Ultralow noise PLL
Integer N = −235 dBc/Hz, fractional-N = −231 dBc/Hz
High maximum PFD frequency
The ADF41513 is an ultralow noise frequency synthesizer that
can be used to implement local oscillators (LOs) as high as
26.5 GHz in the upconversion and downconversion sections of
wireless receivers and transmitters.
Integer N = 250 MHz, fractional-N = 125 MHz
25-bit fixed/49-bit variable fractional modulus mode
Single-ended reference input
3.3 V power supply, 3.3 V charge pump
Integrated 1.8 V logic capability
Phase resync
Programmable charge pump currents: 16× range
Digital lock detect
The ADF41513 is designed on a high performance silicon
geranium (SiGe), bipolar complementary metal-oxide
semiconductor (BiCMOS) process, achieving a normalized
phase noise floor of −235 dBc/Hz. The phase frequency
detector (PFD) operates up to 250 MHz (integer N mode)/
125 MHz (fractional-N mode) for improved phase noise and
spur performance. The variable modulus, ∑-Δ modulator allows
extremely fine resolution when using a 49-bit divide value. The
ADF41513 can be used as an integer N phase-locked loop
(PLL), or it can be used as a fractional-N PLL with either a fixed
modulus for subhertz frequency resolution or variable modulus
for subhertz exact frequency resolution.
3-wire serial interface with register readback option
Hardware and software power-down mode
Operating range from −40°C to +105°C
APPLICATIONS
Test equipment and instrumentation
Wireless infrastructure
Microwave point to point and multipoint radios
Very small aperture terminal (VSAT) radios
Aerospace and defense
A complete PLL is implemented when the synthesizer is used
with an external loop filter and voltage controlled oscillator
(VCO). The 26.5 GHz bandwidth eliminates the need for a
frequency doubler or divider stage, simplifying system
architecture and reducing cost. The ADF41513 is packaged in a
compact, 24-lead, 4 mm × 4 mm LFCSP.
FUNCTIONAL BLOCK DIAGRAM
V
AV
AV
AV
AV
AV
AV
R
SET
P
DD1
DD1
DD2
DD3
DD4
DD5
ADF41513
REFERENCE
5-BIT
R COUNTER
×2
REF
IN
DOUBLER
÷2
DIVIDER
PHASE
FREQUENCY
DETECTOR
+
–
N
CP
CHARGE
PUMP
HIGH-Z
GND
DC1
DC2
LOCK
DETECT
OUTPUT
MUX
MUXOUT
AV
R
DD
+
–
RF
RF
A
B
IN
N COUNTER
DLD
CE
DIV
IN
SD
OUT
25-BIT FIXED/49-BIT VARIABLE
FRACTIONAL INTERPOLATOR
TX
DATA
FRACTION
VALUE
INTEGER
VALUE
MODULUS
25
CLK
32-BIT
DATA
REGISTER
2
VALUE
DATA
LE
C
C
REG1
REG2
1.8V
REGULATOR
GND
Figure 1.
Rev. 0
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Technical Support
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ADF41513
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 2 (R2) Map ................................................................... 18
Register 3 (R3) Map ................................................................... 18
Register 4 (R4) Map ................................................................... 19
Register 5 (R5) Map ................................................................... 19
Register 6 (R6) Map ................................................................... 21
Register 7 (R7) Map ................................................................... 23
Register 8 (R8) Map ................................................................... 24
Register 9 (R9) Map ................................................................... 24
Register 10 (R10) Map............................................................... 25
Register 11 (R11) Map............................................................... 25
Register 12 (R12) Map............................................................... 26
Register 13 (R13) Map............................................................... 27
Applications information .............................................................. 28
Initialization Sequence .............................................................. 28
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Description .............................. 7
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 11
Reference Input........................................................................... 11
RF Input Stage............................................................................. 11
N Divider and R Counter .......................................................... 11
R Counter .................................................................................... 12
PFD and Charge Pump.............................................................. 12
MUXOUT.................................................................................... 12
Lock Detector.............................................................................. 12
Readback...................................................................................... 13
Input Shift Registers................................................................... 13
Program Modes .......................................................................... 13
Register Maps.................................................................................. 14
Register 0 (R0) Map ................................................................... 17
Register 1 (R1) Map ................................................................... 17
RF Synthesizer: A Worked Example of 25-Bit Fixed Modulus
Mode ............................................................................................ 28
RF Synthesizer: A Worked Example of Variable Modulus
Mode ............................................................................................ 28
Modulus....................................................................................... 28
Reference Doubler and Reference Divider ............................. 28
Spur Mechanisms ....................................................................... 29
Phase Resync............................................................................... 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
1/2019—Revision 0: Initial Version
Rev. 0 | Page 2 of 30
Data Sheet
ADF41513
SPECIFICATIONS
AVDDx = AVDD1 = AVDD2 = AVDD3 = AVDD4 = AVDD5 = VP = 3.3 V 5%, GND = 0 V, RSET = 1.8 kΩ, dBm referred to 50 Ω, TA = TMIN (−40°C)
to TMAX (+105°C), unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RADIO FREQUENCY (RF)
CHARACTERISTICS
8/9 Prescaler
RF Input Frequency (fRFIN) Range
1
1
26.5
24
GHz
Recommended input power of −5 dBm to
+5 dBm, operation at this frequency range is
limited to 70°C to TMIN
GHz
Operation at this frequency range is TMAX to TMIN
RF Input Sensitivity
−11
dBm
Refer to Figure 10 and Figure 11 for more
information
4/5 Prescaler
fRFIN Range
1
16
+5
GHz
For lower frequencies, ensure slew rate >
320 V/µs
Measured single-ended to RFINA via a 1 pF series
capacitor, 1 pF capacitor to GND on RFINB
RF Input Sensitivity Range
−7
dBm
INPUT REFERENCE FREQUENCY
(REFIN) CHARACTERISTICS
REFIN Input
Frequency
Voltage Range
Sensitivity Range
10
0
−10
800
1.8
8
MHz
V
dBm
Biased at 1 V (ac coupling ensures 1 V bias), use
square wave at low power and/or frequency to
ensure slew rate is > 320 V/µs; for best inband
phase noise performance, ensure slew rate >
500 V/µs
Capacitance
Current
Doubler Input Frequency
10
150
225
pF
µA
MHz
Maximum reference frequency when the
doubler is enabled
MAXIMUM PFD FREQUENCY
Integer N Mode
Fractional-N Mode
N DIVIDER RANGE
16-Bit N Divider Range
Integer N Mode
250
125
MHz
MHz
20
64
23
75
511
1023
511
4/5 prescaler
8/9 prescaler
4/5 prescaler
8/9 prescaler
Fractional-N Mode
1023
CHARGE PUMP (CP)
CP Current (ICP) Sink and Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage
Sink and Source Current Matching
ICP vs. VCP
Programmable
With RSET = 1.8 kΩ
7.2
0.45
5
2.7
2
5
5
5
mA
mA
%
kΩ
nA
%
With RSET = 1.8 kΩ
5% accuracy
VCP = 0.9 V, TA = 25°C
0.7 V ≤ CP voltage (VCP) ≤ VP − 0.7 V
0.7 V ≤ VCP ≤ VP − 0.7 V
VCP = VP/2
1.8
10
%
%
ICP vs. Temperature
Rev. 0 | Page 3 of 30
ADF41513
Data Sheet
Parameter
LOGIC INPUTS
Input Voltage
High (VIH)
Min
Typ
Max
Unit
Test Conditions/Comments
1.4
V
The serial port interface (SPI) block can accept
both 1.8 V or 3.3 V logic inputs
Low (VIL)
Input Current (IINH, IINL
Input Capacitance (CIN)
LOGIC OUTPUTS
Output Voltage
High (VOH)
0.6
1
10
V
µA
pF
)
1.4
2.6
V
V
MUXOUT voltage = 1.8 V, DLD voltage = 1.8 V
MUXOUT voltage = 3.3 V, DLD voltage = 3.3 V
Low (VOL)
0.4
V
Output High Current, Output Low
Current (IOH, IOL)
500
µA
POWER SUPPLIES
AVDD1, AVDD2, AVDD3, AVDD4, AVDD5, VP 3.135
3.3
2
63.5
2.1
1.45
20
3.465
3.2
88
3.6
2
25
7
128.8
100
V
1
IDD1
IDD2
IDD3
IDD4
mA
mA
mA
mA
mA
mA
mA
µA
Current drawn by AVDD1
Current drawn by AVDD2
Current drawn by AVDD3
Current drawn by AVDD4
Current drawn by AVDD5
Current drawn by VP
Total current drawn by AVDDx and VP
TA = 25°C, CE is low, total of all rails
1
1
1
1
IDD5
IP
ITOTAL
6
95.1
Power-Down Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PNSYNTH
)
In Integer N Mode2
−235
dBc/Hz
PLL loop bandwidth (BW) = 1 MHz (Integer N
mode)
In Fractional-N Mode3
Normalized 1∕f Noise (PN1_f)3
SPURIOUS SIGNALS
−231
−128
dBc/Hz
dBc/Hz
PLL loop BW = 1 MHz (fractional-N mode)
10 kHz offset, normalized to 1 GHz
Reference Spurious
PFD Spurious
In-Band Integer Boundary
Spurious
−90
−87
−45
dBc
dBc
dBc
At reference = 100 MHz, PLL loop BW = 40 kHz
At PFD = 50 MHz, PLL loop BW = 40 kHz
10 kHz offset, PLL loop BW = 250 kHz
1 TA = 25°C, AVDDx = 3.3 V (where x = 1, 2, 3, or 4), prescaler (P) = 8/9, fRFIN = 26.5 GHz, REFIN = 124 MHz, PFD frequency input (fPFD) = 124 MHz.
2 The synthesizer phase noise floor is estimated by measuring the inband phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value)
and 10 log fPFD. PNSYNTH is the total phase noise measured at the VCO output (PNTOT) − 10 log fPFD − 20 log N.
3 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset, f, is given by phase noise (PN) = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are
modeled in the ADIsimPLL.
Rev. 0 | Page 4 of 30
Data Sheet
ADF41513
TIMING CHARACTERISTICS
AVDDx = AVDD1 = AVDD2 = AVDD3 = AVDD4 = AVDD5 = VP = 3.3 V 5%, GND = 0 V, RSET = 1.8 kΩ, dBm referred to 50 Ω, TA = TMIN (−40°C)
to TMAX (+105°C), unless otherwise noted.
Table 2. Read and Write Timing
Parameter
Limit at TMIN to TMAX
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
t8
t9
10
5
5
12.5
12.5
5
10
20
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
LE setup time to MUXOUT when MUXOUT is configured as SPI output
CLK setup time to MUXOUT when MUXOUT is configured as SPI output
Timing Diagram
t4
t5
CLK
t2
t3
DB2
(CONTROL BIT C3)
DB1
DB0 (LSB)
(CONTRO BIT C1)
DB30
DATA
LE
DB31 (MSB)
(CONTROL BIT C2)
L
t7
t1
t6
DB31
(MSB)
MUXOUT
DB30
DB1
DB0
t8
t9
Figure 2. Read and Write Timing
Rev. 0 | Page 5 of 30
ADF41513
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
TA = 25°C, unless otherwise noted.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 3.
Parameter
AVDDx to GND1
VP to GND
Rating
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to AVDDx + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to +3.6 V
1.4 V
θ
JA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
VP to AVDDx
Digital Input/Output Voltage to GND
Analog Input/Output Voltage to GND
RFINA, RFINB to GND
RFINA to RFINB1
REFIN to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Maximum Junction Temperature
Operational
Table 4. Thermal Resistance
Package Type
θJA
θJC
Unit
CP-24-81
48
38
°C/W
−0.3 V to +2.1 V
1 The thermal resistance values are defined per the JESD51 standard.
−40°C to +105°C
−65°C to +125°C
ESD CAUTION
125°C
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Electrostatic Discharge (ESD)
Charged Device Model
Human Body Model
Transistor Count
260°C
40 sec
1250 V
1500 V
CMOS
Bipolar
215,726
1625
1 Approximately 13 dBm into a 50 Ω input.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
This device is a high performance RF IC with an electrostatic
discharge (ESD) rating of <2 kV, and the device is ESD sensitive.
Take proper precautions for handling and assembly.
Rev. 0 | Page 6 of 30
Data Sheet
ADF41513
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
18
17
16
15
14
13
GND
C
REG1
AV
MUXOUT
LE
DD1
DD1
AV
ADF41513
TOP VIEW
(Not to Scale)
DATA
CLK
RF B 4
IN
5
6
RF
AV
A
IN
CE
DD2
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST
BE CONNECTED TO GND.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
GND
Ground Pin.
2, 3
AVDD1
PFD and Up and Down Digital Driver Power Supply. Pin 2 and Pin 3 can be tied together. With Pin 2 and Pin 3 tied
together, place three parallel capacitors as close as possible to the AVDD1 pins: 10 µF, 100 nF, and 100 pF.
4
RFINB
Complementary Input to the RF Prescaler. In single-ended mode, decouple this pin to the ground plane with a
small bypass capacitor, typically 100 pF.
5
6
RFINA
AVDD2
Input to the RF Prescaler. AC-couple this signal to the external VCO.
RF Buffer and Prescaler Power Supply. Place three parallel capacitors as close as possible to the AVDD2 pin: 10 µF,
100 nF, and 100 pF.
7
AVDD3
AVDD4
AVDD5
REFIN
N Divider Power Supply. Place three parallel capacitors as close as possible to the AVDD3 pin: 10 µF, 100 nF, and
100 pF.
R Divider and Lock Detector Power Supply. Place three parallel capacitors as close as possible to the AVDD4 pin:
10 µF, 1 µF, and 100 nF. Pin 8 powers the internal low dropout (LDO) regulator for the reference divider.
Σ-Δ Modulator and SPI Power Supply. Place three parallel capacitors as close as possible to the AVDD5 pin: 10 µF,
1 µF, and 100 nF. This pin powers the internal LDO regulator for the Σ-Δ modulator.
Reference Input. The reference can accept either a single-ended CMOS (dc-coupled) or single-ended sine wave
(ac-coupled). The single-ended input has a nominal threshold of 1 V and a dc equivalent input resistance of 20 kΩ.
8
9
10
11
12
13
DLD
TXDATA
CE
Digital Lock Detect Pin. A logic high on this pin indicates PLL lock.
Transmit Data Pin. Pin 12 is not used. Connect Pin 12 to GND.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state
mode. Registers do not hold their values when CE is low. This pin only supports 3.3 V logic inputs.
14
15
16
17
18
19
CLK
Serial Clock Input. CLK clocks in the serial data to the registers. The data is latched into the 32-bit shift register on
the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded most significant bit (MSB) first with the two least significant bits (LSBs) as
the control bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches. Select the latch using the control bits.
Multiplexer Output. This multiplexer output allows the lock detect, the scaled RF, the scaled reference frequency,
logic high, logic low, or register readback data to be accessed externally.
Internal 1.8 V Regulator Output Pin. Place three parallel capacitors as close to the CREG1 pin as possible: 4.7 µF,
100 nF, and 1 nF.
Internal 1.8 V Regulator Output Pin. Place three parallel capacitors as close to the CREG2 pin as possible: 4.7 µF,
100 nF, and 1 nF.
DATA
LE
MUXOUT
CREG1
CREG2
20
21
22
23
DC1
DC2
VP
DC Bias Pin 1. Place a 1 µF capacitor in parallel with a 1 nF capacitor to ground, as close as possible to the DC1 pin.
DC Bias Pin 2. Place a 1 µF capacitor in parallel with a 1 nF capacitor to ground, as close as possible to the DC2 pin.
Charge Pump Power Supply.
Maximum Charge Pump Current Setting Resistor. Connecting a resistor between the RSET pin and GND sets the
maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship
between ICP and RSET is ICP_MAX = 12.96/RSET. For example, with RSET = 2.7 kΩ, ICP MAX = 4.8 mA. The relationship between
bleed current (IBLEED) and RSET is IBLEED_MIN = 0.0103/RSET. For example, with RSET = 2.7 kΩ, IBLEED_MIN = 3.81 µA.
RSET
Rev. 0 | Page 7 of 30
ADF41513
Data Sheet
Pin No. Mnemonic Description
24
CP
Charge Pump Output. When enabled, this pin provides ICP to the external loop filter, which in turn drives the
external VCO.
EPAD
Exposed Pad. The exposed pad must be connected to GND.
Rev. 0 | Page 8 of 30
Data Sheet
ADF41513
TYPICAL PERFORMANCE CHARACTERISTICS
–50
–60
–60
1: 100Hz –84.7799dBc/Hz
HMC733, 10GHz
2: 1kHz
–100.0772dBc/Hz
HMC733, 15GHz
3: 10kHz –106.0022dBc/Hz
4: 100kHz –107.2571dBc/Hz
HMC733, 20GHz
–70
–80
5: 1MHz
6: 5MHz
7: 5MHz
–120.4055dBc/Hz
–137.4443dBc/Hz
–137.4443dBc/Hz
–80
–90
–100
–120
–140
–160
–180
1
–100
–110
–120
–130
–140
–150
–160
–170
2
3
4
5
6
CARRIER 7.999978185GHz
10.6758dBm
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
Figure 4. Phase Noise vs. Offset Frequency at 10 GHz, 15 GHz, and 20 GHz
with the HMC733, ICP = 3.5 mA, Integer N Mode
Figure 7. 8 GHz Phase Noise vs. Offset Frequency with the HMC509,
I
CP = 3.5 mA, Fractional-N Mode
–50
–60
–70
1: 100Hz –77.5694dBc/Hz
2: 1kHz
–88.8020dBc/Hz
–60
–70
3: 10kHz –96.3815dBc/Hz
4: 100kHz –97.7809dBc/Hz
5: 1MHz
6: 5MHz
–99.0890dBc/Hz
–124.770dBc/Hz
7: 10MHz –131.8076dBc/Hz
8: 40MHz –150.4377dBc/Hz
–80
1
–80
–90
2
–100
–110
–120
–130
–140
–150
–160
–170
3
–90
4
5
–120 BLEED
–100
–110
–120
–130
6
7
8
PHASE NOISE 10.00dB/REF –60.00dBc/Hz
CARRIER 19.999935636GHz
–3.0171dBm
–136 BLEED
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
Figure 5. 20 GHz Phase Noise vs. Offset Frequency with the HMC733,
CP = 3.5 mA, Fractional-N Mode
Figure 8. Phase Noise vs. Offset Frequency for Various Bleeds
I
8.5
7.5
–30
7.5937mA UP
6.5812mA UP
5.5687mA UP
4.5562mA UP
3.5437mA UP
8dBm
4dBm
0dBm
–4dBm
–8dBm
6.5
–50
–70
5.5
4.5
3.5
2.5312mA UP
1.5187mA UP
2.5
1.5
–90
0.5062mA UP
0.5
–0.5
–1.5
–2.5
–3.5
–4.5
–5.5
–6.5
–7.5
–8.5
0.5062mA DOWN
1.5187mA DOWN
2.5312mA DOWN
3.5437mA DOWN
4.5562mA DOWN
5.5687mA DOWN
6.5812mA DOWN
7.5937mA DOWN
–100
–130
–150
–170
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1k
10k
100k
1M
10M
100M
CP VOLTAGE (V)
OFFSET FREQUENCY (Hz)
Figure 9. 15 GHz Phase Noise vs. Offset Frequency at Various REFIN Powers,
Fractional-N Mode, PFD = 100 MHz
Figure 6. Current vs. CP Voltage, Charge Pump Compliance, RSET = 1.8 kΩ
Rev. 0 | Page 9 of 30
ADF41513
Data Sheet
10
–50
–60
DEVICE A
DEVICE B
DEVICE C
DEVICE D
DEVICE E
DEVICE F
DEVICE G
DEVICE H
DEVICE I
100MHz
200MHz
300MHz
5
0
–70
–5
–10
–15
–20
–25
–30
–35
–40
–80
–90
–100
–110
–120
22.5 25.0
15.0 17.5 20.0
2.5 5.0
7.5 10.0 12.5
12.5
12.7
12.9
13.1
13.3
13.5
13.7
13.9
0
(GHz)
FREQUENCY
TARGET FREQUENCY (GHz)
Figure 12. Spur Level vs. Target Frequency with the HMC584 VCO,
REFIN = 100 MHz, PFD = 100 MHz, PLL Loop BW = 80 kHz
Figure 10. Sensitivity vs. Frequency for Multiple Soldered Devices
–50
10
5
–60
MAXIMUM SENSITIVITY –40°C
0
MAXIMUM SENSITIVITY +25°C
100MHz
200MHz
300MHz
MAXIMUM SENSITIVITY +85°C
MAXIMUM SENSITIVITY +105°C
–70
–80
–5
–10
–15
–20
–25
–30
–35
–40
–90
–100
MINIMUM SENSITIVITY –40°C
MINIMUM SENSITIVITY +25°C
MINIMUM SENSITIVITY +85°C
MINIMUM SENSITIVITY +105°C
–110
–120
22.5 25.0
15.0 17.5 20.0
2.5 5.0
7.5 10.0 12.5
0
(GHz)
FREQUENCY
TARGET FREQUENCY (GHz)
Figure 11. Sensitivity vs. Frequency at Various Temperatures for Device A
Figure 13. Spur Level vs. Target Frequency with Z-Communications
V940ME03 VCO, REFIN = 100 MHz, PFD = 100 MHz, PLL Loop BW = 80 kHz
Rev. 0 | Page 10 of 30
Data Sheet
ADF41513
THEORY OF OPERATION
The N divider value is generated by a Σ-Δ modulator. The
REFERENCE INPUT
ADF41513 contains two selectable Σ-Δ modulators. One
modulator has a 25-bit fixed modulus (see Figure 16) and one
has a variable modulus up to 49 bits (see Figure 17). Register 0,
Bit 28 selects the modulator.
The reference input stage is shown in Figure 14. The reference
input accepts an ac-coupled, single-ended signal. During
power-down, this circuit remains active and draws the same
current from AVDD4 as during normal operation. With no
reference connected, AVDD4 drops to approximately 600 μA.
20kΩ
25
RF INT DIVIDER
N = INT + FRAC/2
FROM RF
INPUT STAGE
TO PFD
N COUNTER
REF
TO R COUNTER
IN
BUFFER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
Figure 14. Reference Input Stage
INT
VALUE
FRAC
VALUE
25
2
RF INPUT STAGE
The RF input stage is shown in Figure 15. A two-stage limiting
amplifier follows the RF input stage to generate the current
mode logic (CML) clock levels needed for the prescaler. The
RFINA and RFINB inputs require dc blocking capacitors to isolate
the 1.65 V bias level from the input signal.
Figure 16. Fixed Modulus N Divider
FRAC2
MOD2
RF INT DIVIDER
N = INT +
FRAC1 +
2
TO PFD
FROM RF
INPUT STAGE
N COUNTER
1.65V
BIAS
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
GENERATOR
AV
DD2
768Ω
768Ω
EXTERNAL
AC COUPLING
FOR SE INPUT
INT
REG
FRAC1
REG
FRAC2
VALUE
MOD2
VALUE
RF
A
IN
1pF
1pF
Figure 17. Variable Modulus N Divider
RF
B
IN
25-Bit Fixed Modulus (Register 0, Bit 28 = 0)
For the 25-bit fixed modulus, the RF VCO frequency (RFOUT
equation is
)
RFOUT = fPFD × (INT + (FRAC/225))
(2)
AGND
where:
Figure 15. RF Input Stage
RFOUT is the RF VCO frequency.
N DIVIDER AND R COUNTER
INT is a 16-bit value set by Bits[19:4] in Register 0. In Integer N
mode, INT is 20 to 511 for a 4/5 prescaler and 64 to 1023 for a 8/9
prescaler, and in fractional-N mode, INT is 23 to 511 for a 4/5
prescaler and 75 to 1023 for a 8/9 prescaler.
FRAC is a 25-bit value set by Bits[28:4], FRAC1, in Register 1.
The minimum RF output resolution is set by fPFD/225. For
The N divider is used to divide the RF input signal down to the
PFD frequency (fPFD).
f
PFD = REFIN × ((1 + D)/(R × (1 + T)))
(1)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit value (0 or 1).
R is the preset divide ratio of the binary 5-bit programmable
reference counter (1 to 32).
example, if fPFD = 100 MHz, the minimum resolution is 2.98 Hz.
By default, due to the architecture of the Σ-Δ modulator, there is
a fixed (fPFD/226) offset added or subtracted from the programmed
output frequency. To remove this offset, set LSB_PI (Register 5,
Bit 24).
T is the REFIN divide by 2 bit value (0 or 1).
Rev. 0 | Page 11 of 30
ADF41513
Data Sheet
Variable Modulus (R0, DB28 = 1)
MUXOUT
For the variable modulus, the RF VCO frequency (RFOUT
equation is
RFOUT = fPFD × (INT + (FRAC1 + (FRAC2/MOD2))/225) (3)
where:
)
The output multiplexer on the ADF41513 allows the user to access
various internal nodes on the chip. The M4, M3, M2, and M1 bits
in Register 12 (see the Register 12 (R12) Map section) controls
the state of MUXOUT. Figure 19 shows the MUXOUT section in
block diagram form. Many of these access points are useful for
debugging. For example, select the N divider output to check if
the N divider is functioning correctly. Most of the access points
are self explanatory. Set the CLK1 divider output signal to access
the internal CLK1 divider signal used for phase resync. During
power-down (CE = logic low), MUXOUT is set to GND.
THREE-STATE OUTPUT
RFOUT is the output frequency of external VCO.
INT is a 16-bit value set by Bits[19:4] in Register 0. In Integer N
mode, INT is 20 to 511 for a 4/5 prescaler and 64 to 1023 for a 8/9
prescaler, and in fractional-N mode, INT is 23 to 511 for a 4/5
prescaler and 75 to 1023 for a 8/9 prescaler.
FRAC1 is a 25-bit value set by Bits[28:4] in Register 1.
FRAC2 is a 24-bit value set by Bits[27:4] in Register 3.
MOD2 is a 24-bit value set by Bits[27:4] in Register 4.
The minimum RF output resolution is set by fPFD/249. Therefore,
for fPFD = 100 MHz, the minimum resolution is 0.1776 µHz. To
achieve this resolution, MOD2 must be set to its maximum of
(224 − 1), which is 16,777,215.
AV
DD5
AV
DD5
DGND
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
CLK DIVIDER OUTPUT
R-DIVIDER/2
CONTROL
MUXOUT
MUX
N-DIVIDER/2
Integer N Mode
DGND
READBACK TO MUXOUT
When FRAC1 and FRAC2 are both equal to 0, the ADF41513
can operate in purely integer N mode, which improves the
phase noise performance of the PLL and sets the frequency
resolution to fPFD. This feature is not automatic and must be
manually set for Integer N channels. Bleed must also be
disabled when using the ADF41513 in Integer N operation. See
the Register 12 (R12) Map section for more information on
programming the ADF41513 for Integer N operation.
Figure 19. MUXOUT Schematic
LOCK DETECTOR
The lock detector compares the PFD output pulse width against
a lock detector window. Measurements are performed every
PFD comparison cycle when LD_CLK_SEL = 0 or every 32nd
cycle when LD_CLK_SEL = 1. If the pulse width falls within the
lock window, a counter is incremented. If the counter reaches
the count set by LD_COUNT without an up or down pulse
width exceeding the lock detect window and without a cycle slip
occurring, lock is then declared by the lock detector.
R COUNTER
The 5-bit R counter allows REFIN to be divided down to produce
the reference clock to the PFD. Division ratios from 1 to 32 are
allowed.
When the lock detector has declared lock, the main mechanism
to declare a loss of lock is for a cycle slip to occur. This cycle slip
is usually caused by a frequency error at the phase detector
input, causing the phase error to grow until the error exceeds
360°. The phase error then wraps around to 0°. This phase wrap
around is a cycle slip.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between these inputs. Figure 18 shows a PFD simplified
schematic. The PFD includes a fixed delay element that sets the
width of the antibacklash pulse, which is typically 1 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
and produces a consistent reference spur level.
A high level on MUXOUT indicates the PLL is in lock.
The lock detector window size, LD_COUNT, and
LD_CLK_SEL all affect the sensitivity of the lock detector.
Larger windows, smaller LD_COUNT values, and
UP
HIGH
D1
Q1
LD_CLK_SEL = 0 shorten the overall lock detect time and
increase sensitivity. Smaller windows, larger LD_COUNT
values, and LD_CLK_SEL = 1 increase the overall lock detect
time and reduce sensitivity. Excessive lock detector sensitivity
can cause multiple transitions between a locked state and out of
lock state during frequency changes. Insufficient lock detector
sensitivity can cause the detector to indicate an out of lock state
when, in fact, the PLL is locked.
U1
CLR1
+IN
CHARGE
PUMP
CP
U3
DELAY
DOWN
CLR2
D2 Q2
HIGH
U2
–IN
Figure 18. PFD Simplified Schematic
Rev. 0 | Page 12 of 30
Data Sheet
ADF41513
The window size can be adjusted between 0.9 ns and 11.5 ns
with LDP, Bits[9:8] in Register 6 and LD bias, Bits[31:30] in
Register 9. The ideal window size is halfway between the
maximum window, set by the phase comparison period, tPFD
(10 ns for 100 MHz reference and R = 1), and the minimum is
set by
PROGRAM MODES
Table 6 and Figure 23 through Figure 36 show how to set up the
program modes in the ADF41513.
Several settings in the ADF41513 are double buffered. These
settings include MOD2, FRAC1, FRAC2, R counter value,
reference doubler, CP current setting, RDIV2, phase word,
prescaler, and CLK1 divider. Two events must occur before the
device uses a new value for any of the double buffered settings.
First, the new value is latched into the device by writing to the
appropriate register. Second, a new write must be performed on
Register 0. For example, updating the FRAC1 value requires a
write to Register 1 and a write to Register 0. Write to Register 1
first, followed by the write to Register 0. The frequency change
begins after the write to Register 0. Double buffering ensures
that the bits written to Register 1 do not take effect until after
the write to Register 0.
(IBLEED/ICP) × tPFD
(4)
LD_COUNT can range from 2 counts to 8192 counts. The
fastest lock indication requires two measurement cycles (20 ns
with 100 MHz reference, R = 1, and LD_CLK_SEL = 0). In
practice, the lock indication takes much longer because of the
loop filter on the phase comparator. When LD_CLK_SEL = 1, a
minimum 64 measurements are required (640 ns).
READBACK
Register data can be read by setting MUXOUT to serial data
output. In this mode, the MUXOUT line concurrently transfers
32 bits of the previous written register value while clocking in
32 bits of write data.
Table 6. C4, C3, C2, and C1 Truth Table
Control Bits
C4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
C3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
C2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
C1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
To read back a specific register, chip revision code, or bit
pattern, write 1000b to Bits[31:28], Register 12. Bits[19:14] in
Register 12 set the data that is output from the MUXOUT pin
when in readback mode.
To prevent spurious writes, the DATA pin must be held at logic
low while a readback is taking place.
INPUT SHIFT REGISTERS
The ADF41513 contains a programmable digital block. Data is
clocked into the 32-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to the chosen register on the rising edge of LE. The
destination latch is determined by the state of the four control
bits (C4, C3, C2, and C1) in the shift register. The following are
the four LSBs: DB3, DB2, DB1, and DB0. The truth table for
these bits is shown in Table 6. Figure 20 through Figure 22 show
a summary of how the registers are programmed.
Rev. 0 | Page 13 of 30
ADF41513
Data Sheet
REGISTER MAPS
INT REGISTER (R0)
CONTROL
BITS
RESERVED
16-BIT INTEGER VALUE (INT)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
V1
0
0
0
0
0
0
0
0
N16 N15 N14 N13 N12 N11 N10 N9
N8
N7
N6
N5
N4
N3
N2 N1 C4(0) C3(0) C2(0) C1(0)
FRAC1 REGISTER (R1)
DBB
CONTROL
BITS
25-BIT FRAC1 VALUE (FRAC1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D1
0
0
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9
F8
F7
F6
F5
F4
F3
F2
F1 C4(0) C3(0) C2(0) C1(1)
PHASE REGISTER (R2)
DBB
CONTROL
BITS
RESERVED
12-BIT PHASE VALUE (PHASE)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PA1 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C4(0) C3(0) C2(1) C1(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FRAC2 REGISTER (R3)
DBB
CONTROL
BITS
24-BIT FRAC2 VALUE (FRAC2)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9
F8
F7
F6
F5
F4
F3
F2
F1 C4(0) C3(0) C2(1) C1(1)
MOD2 REGISTER (R4)
DBB
CONTROL
BITS
24-BIT MOD2 VALUE (MOD2)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M24 M23 M22 M21 M20 M19 M18 M17 M16 M15 M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C4(0) C3(1) C2(0) C1(0)
0
0
0
0
NOTES
1. DBB MEANS DOUBLE-BUFFERED BITS.
Figure 20. Register Summary for Register 0 (R0) to Register 4 (R4)
Rev. 0 | Page 14 of 30
Data Sheet
ADF41513
R DIVIDER REGISTER (R5)
DBB
DBB
DBB
DBB
CP
CURRENT
SETTING
5-BIT R COUNTER
CONTROL
BITS
12-BIT CLK DIVIDER VALUE
1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DL2 DL1
0
CPI4 CPI3 CPI2 CPI1 L1
P1
U2
U1
R5
R4
R3
R2
R1 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
C4(0) C3(1) C2(0) C1(1)
FUNCTION REGISTER (R6)
CONTROL
BITS
BLEED CURRENT
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
A1 LOL1
BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BP1
SD1 CP1
1
0
0
0
0
0
LDP2 LDP1 PP1 PD C31 CR1
C4(0) C3(1) C2(1) C1(0)
BE1
0
IM1
CLOCK 2 REGISTER (R7)
CLK
DIVIDER
MODE
CONTROL
BITS
12-BIT CLK DIVIDER VALUE
2
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C4(0) C3(1) C2(1) C1(1)
D1 CS2 CS1
0
CN1 LD1
0
CN3 CN2
0
0
ND2 ND1 PB2 PB1
C
C1 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
RESERVED REGISTER (R8)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C4(1) C3(0) C2(0) C1(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESERVED REGISTER (R9)
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C4(1) C3(0) C2(0) C1(1)
LB2 LB1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NOTES
1. DBB MEANS DOUBLE-BUFFERED BITS.
Figure 21. Register Summary for Register 5 (R5) to Register 9 (R9)
Rev. 0 | Page 15 of 30
ADF41513
Data Sheet
RESERVED REGISTER (R10)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
C4(1) C3(0) C2(1) C1(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESERVED REGISTER (R11)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PDS
0
0
0
0
0
C4(1) C3(0) C2(1) C1(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MUXOUT REGISTER (R12)
READBACK
SELECT
CONTROL
BITS
MUXOUT
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M4 M3 M2 M1 LL
0
0
0
0
MR1
0
L1
R6
R5
R4
R3
R2
R1
0
0
0
0
0
0
0
0
0
0
C4(1) C3(1) C2(0) C1(0)
RESERVED REGISTER (R13)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C4(1) C3(1) C2(0) C1(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22. Register Summary for Register 10 (R10) to Register 13 (R13)
Rev. 0 | Page 16 of 30
Data Sheet
ADF41513
REGISTER 0 (R0) MAP
REGISTER 1 (R1) MAP
DITHER2
Frequency changes occur only on a write to Register 0.
Variable Modulus
Set Register 1, Bit 31 = 1 to enable the Σ-Δ modulator dither.
Enabling DITHER2 can reduce fractional spurs.
Register 0, Bit 28 = 0 enables the 25-bit fixed modulus.
Register 0, Bit 28 = 1 enables the variable modulus. See the
N Divider and R Counter section for more information.
FRAC1
Register 1, Bits[28:4] set the FRAC1 value. See the N Divider
and R Counter section for more information. When using a
fixed modulus, Bits[28:4] are the FRAC value.
INT Value
Register 0, Bits[19:4] set the INT value. See the N Divider and
R Counter section for more information.
INT REGISTER (R0)
CONTROL
BITS
RESERVED
RESERVED
16-BIT INTEGER VALUE (INT)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
V1
0
0
0
0
0
0
0
0
N16 N15 N14 N13 N12 N11 N10 N9
N8
N7
N6
N5
N4
N3
N2 N1 C4(0) C3(0) C2(0) C1(0)
V1 VARIABLE MODULUS
...
N16 N15 N14 N13 N12 N11 N10
N5 N4
N3 N2
N1
INTEGER WORD
0
1
25-BIT FIXED MODULUS
VARIABLE MODULUS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
NOT ALLOWED
NOT ALLOWED
...
...
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
0
.
NOT ALLOWED
.
...
...
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
1
0
NOT ALLOWED
20
...
...
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
0
.
1
.
0
.
1
.
21
.
...
...
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1022
1023
...
...
...
0
.
1
.
0
.
0
.
0
.
0
.
0
.
0
.
NOT ALLOWED
.
0
.
0
.
0
.
0
.
1
1
1
1
1
1
1
...
1
1
1
1
1
NOT ALLOWED
INTEGER N MODE
PRESCALER 4/5: 20 ≤ INT ≤ 511
PRESCALER 8/9: 64 ≤ INT ≤ 1023
FRACTIONAL-N MODE
PRESCALER 4/5: 23 ≤ INT ≤ 511
PRESCALER 8/9: 75 ≤ INT ≤ 1023
Figure 23. Register 0 (R0) Map
FRAC1 REGISTER (R1)
DBB
CONTROL
BITS
25-BIT FRAC1 VALUE (FRAC1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D1
0
0
F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9
F8
F7
F6
F5
F4
F3
F2
F1 C4(0) C3(0) C2(0) C1(1)
D1
0
DITHER2
OFF
...
F25 F24
F2
F1
FRAC1 WORD
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
1
ON
1
2
3
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
33,554,428
33,554,429
33,554,430
33,554,431
NOTES
1. DBB MEANS DOUBLE-BUFFERED BITS.
Figure 24. Register 1 (R1) Map
Rev. 0 | Page 17 of 30
ADF41513
Data Sheet
REGISTER 2 (R2) MAP
REGISTER 3 (R3) MAP
Phase Adjust
FRAC2
Set Register 2, Bit 31 to 1 to enable phase adjust. Phase adjust
increases the phase of the output relative to the current phase.
The phase change occurs after a write to Register 0.
Register 3, Bits[27:4] set the FRAC2 value. See the N Divider
and R Counter section for more information. When using a
fixed modulus, FRAC2 is ignored.
Phase Shift = (Phase Value × 360°)/212
(5)
Phase Value
Register 2, Bits[15:4] set the phase value for phase adjust. For
example, setting the phase value = 512 increases the output
phase by 45°.
If phase adjust is not used, set the phase value to 0.
PHASE REGISTER (R2)
DBB
CONTROL
BITS
RESERVED
12-BIT PHASE VALUE (PHASE)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PA1 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C4(0) C3(0) C2(1) C1(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA1 PHASE ADJUST
0
1
DISABLED
ENABLED
...
P12 P11
P2
P1
PHASE VALUE
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4,092
4,093
4,094
4,095
NOTES
1. DBB MEANS DOUBLE-BUFFERED BITS.
Figure 25. Register 2 (R2) Map
FRAC2 REGISTER (R3)
DBB
CONTROL
BITS
24-BIT FRAC2 VALUE (FRAC2)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C4(0) C3(0) C2(1) C1(1)
0
0
0
0
F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9
F8
F7
F6
F5
F4
F3
F2
F1
...
F24 F23
F2
F1
FRAC2 WORD
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16,777,212
16,777,213
16,777,214
16,777,215
NOTES
1. DBB MEANS DOUBLE-BUFFERED BITS.
Figure 26. Register 3 (R3) Map
Rev. 0 | Page 18 of 30
Data Sheet
ADF41513
the fRFIN signal so that the N divider can operate correctly. The
prescaler is based on a synchronous 4/5 core. The prescaler
setting affects the RF frequency and the minimum and maximum
INT value as follows:
REGISTER 4 (R4) MAP
MOD2
Register 4, Bits[27:4] set the MOD2 value. See the N Divider
and R Counter section for more information. When using a
fixed modulus, MOD2 is ignored.
For Integer N mode,
•
•
Prescaler 4/5: 20 ≤ INT ≤ 511, fRFIN_MAX = 16 GHz
Prescaler 8/9: 64 ≤ INT ≤ 1023, fRFIN_MAX = 26.5 GHz
REGISTER 5 (R5) MAP
DLD Modes
For fractional-N mode,
Register 5, Bits[31:30] set the digital lock detect (DLD) pin
state. For normal digital lock detect, set Register 5, Bits[31:30] =
0b01. Other options tristate the pin and force a high or low
logic level, as shown in Figure 28.
•
•
Prescaler 4/5: 23 ≤ INT ≤ 511, fRFIN_MAX = 16 GHz
Prescaler 8/9: 75 ≤ INT ≤ 1023, fRFIN_MAX = 26.5 GHz
RDIV2
CP Current Setting
Register 5, Bit 22 controls the reference divide by 2 block. See
the N Divider and R Counter section for more information.
This feature can provide a 50% duty cycle signal to the PFD.
Register 5, Bits[28:25] set the charge pump current. Set these
bits to the charge pump current that the loop filter is designed
for based on the application of the user. The recommended
practice is to design the loop filter for a charge pump current of
2.4 mA or 2.7 mA and then use the programmable charge pump
current to fine tune the loop filter frequency response.
Reference Doubler
Register 5, Bit 21 controls the reference doubler block. See the
N Divider and R Counter section for more information.
LSB_P1
R Counter
Register 5, Bit 24 = 0 enables a 26th bit in the fixed modulus
MOD value. Enabling the 26th bit reduces fractional spurs but
the reduction also adds a fixed fPFD/226 frequency offset to the
output frequency. To disable this frequency offset, set Register 5,
Bit 24 = 1.
Register 5, Bits[20:16] control the R counter value. See the N
Divider and R Counter section for more information.
CLK1 Divider
Register 5, Bits[15:4] control the CLK1 divider value. See the
Phase Resync section for more information.
Prescaler
The dual modulus prescaler (4/5 and 8/9) is set by Register 5,
Bit 23. The prescaler, at the input to the N divider, divides down
MOD2 REGISTER (R4)
DBB
CONTROL
BITS
24-BIT MOD2 VALUE (MOD2)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M24 M23 M22 M21 M20 M19 M18 M17 M16 M15 M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1
0
0
0
0
C4(0) C3(1) C2(0) C1(0)
...
M24 M23
M2
M1
MOD2 WORD
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16,777,212
16,777,213
16,777,214
16,777,215
NOTES
1. DBB MEANS DOUBLE-BUFFERED BITS.
Figure 27. Register 4 (R4) Map
Rev. 0 | Page 19 of 30
ADF41513
Data Sheet
R DIVIDER REGISTER (R5)
DBB
DBB
DBB
DBB
CP
CURRENT
SETTING
5-BIT R COUNTER
CONTROL
BITS
12-BIT CLK DIVIDER VALUE
1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C4(0) C3(1) C2(0) C1(1)
DL2 DL1
0
CPI4 CPI3 CPI2 CPI1 L1
P1
U2
U1
R5
R4
R3
R2
R1 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
REFERENCE
DOUBLER
U1
DL2 DL1 DLD PIN
D12 D11 ...
D2 D1
CLK DIVIDER VALUE
1
0
0
0
1
TRISTATE
0
1
DISABLED
ENABLED
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
DIGITAL LOCK DETECT
1
1
1
0
1
LOW
HIGH
2
3
U2
R DIVIDER
DISABLED
ENABLED
.
0
1
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4,092
4,093
4,094
4,095
P1
PRESCALER
0
1
4/5
8/9
L1
0
LSB P1
R5
R4
0
0
0
0
.
R3
0
0
0
1
.
R2
R1
1
0
1
0
.
R COUNTER DIVIDE RATIO
ON: 0.5 LSB OFFSET
OFF: NO OFFSET
0
0
0
0
.
0
1
1
0
.
1
1
2
3
4
I
(mA)
CP
.
CPI4
CPI3
CPI2
CPI1
2.7kΩ 1.8kΩ
.
.
.
.
.
.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
0.45
0.90
1.35
1.80
2.25
2.70
3.15
3.60
4.05
4.50
4.95
5.40
5.85
6.30
6.75
7.20
.
.
.
.
.
.
1
1
1
0
1
1
1
0
1
1
1
0
0
1
1
0
1
0
1
0
29
30
31
32
NOTES
1. DBB MEANS DOUBLE-BUFFERED BITS.
Figure 28. Register 5 (R5) Map
Rev. 0 | Page 20 of 30
Data Sheet
ADF41513
FRAC = 0. Remove this glitch by setting Register 6, Bit 17 = 1
(recommended setting).
REGISTER 6 (R6) MAP
Bleed Current
CP Three-State, PD on
Register 6, Bits[31:24] set the bleed current. If the PD polarity is
set to positive, the optimum bleed current is set by
When Register 6, Bit 16 = 1, the charge pump is in three-state
mode but the phase detector (PD) is still operational. Set
Register 6, Bit 16 = 0 for normal operation.
Bleed Value = floor(90 × (fPFD/100 MHz) × (ICP_CODE + 1)/16) (6)
where:
Lock Detector Precision (LDP)
Bleed Value is the value programmed to Register 6, Bits[31:24].
Register 6, Bits[9:8] and Register 9, Bits[31:30] control the
sensitivity of the digital lock detector. Lock detect precision
(Register 6, Bits[9:8]) in conjunction with lock detector bias
(Register 9, Bits[31:30]) adjusts the width of the digital lock
detector window. Lock is declared when the PFD reference
arrival time and divided VCO input arrival times consistently
differ by less than the LDP value. Small LDP settings may cause
a false out of lock indication when used with large bleed
currents. See the Lock Detector section for more information.
I
CP_CODE is the charge pump current setting programmed to
Register 5, Bits[28:25].
PFD is the PFD frequency in MHz.
f
If the PD polarity is set to negative, the optimum bleed current
is set by
Bleed Value = floor(144 × (fPFD/100 MHz) × (ICP_CODE +1)/16) (7)
Bleed Polarity
Register 6, Bit 23 controls the polarity of the bleed current.
Negative polarity is the typical usage.
Phase Detector (PD) Polarity
If using a noninverting loop filter and a VCO with a positive
tuning slope, set the PD polarity to positive.
Bleed Enable
In fractional-N mode of operation, charge pump linearity (and
ultimately phase noise and spurious performance) is improved
if the VCO and reference inputs to the phase detector operate
with a phase offset. This phase offset is implemented by adding
a constant bleed current at the output of the charge pump. Use
bleed only when operating in fractional-N mode, that is,
FRAC1 or FRAC2 not equal to 0. Set Register 6, Bit 22 = 1 to
enable bleed.
If using an inverting loop filter and a VCO with a negative
tuning slope, set the PD polarity to positive.
If using a noninverting loop filter and a VCO with a negative
tuning slope, set the PD polarity to negative.
If using an inverting loop filter and a VCO with a positive
tuning slope, set the PD polarity to negative.
Power Down
INT Mode
Set Register 6, Bit 6 = 1 to perform a software power-down. All
circuit blocks are disabled, and the chip enters a low power state
drawing approximately 4 mA. Set Register 6, Bit 6 = 0 to reenable
the chip. Register values are not lost during power-down. Only
one power-down mode is available via Register 11, Bit 31. Set
Register 11, Bit 31 = 1 to leave the internal 1.8 V N divider
regulator on during power-down.
Register 6, Bit 20 completely disables the fractional-N Σ-Δ
modulator (SDM). Setting Register 6, Bit 20 = 1 disables the
SDM so the ADF41513 operates purely in integer N mode.
Disabling the SDM improves phase noise performance and
changes the frequency resolution to fPFD
.
ABP
Register 6, Bit 19 affects the antibacklash pulse (ABP) width.
The recommended setting for best figure of merit (FOM) is
narrow (Register 6, Bit 19 = 1).
Note that Register 12, Bit 20 must be set to 0 when writing this
power-down bit. Otherwise, the chip cannot be powered back
on again by setting Register 6, Bit 6 = 0.
Loss of Lock (LOL) Enable
CP Three-State
If digital lock detect is asserted when loss of lock is enabled and
the reference signal is removed, digital lock detect goes low. Set
Register 6, Bit 18 = 1 to enable loss of lock (recommended).
Setting Register 6, Bit 5 = 1 puts the charge pump into three-
state mode. Set Register 6, Bit 5 = 0 for normal operation.
Counter Reset
Sigma-Delta (SD) Reset
Setting Register 6, Bit 4 = 1 holds the N divider and R counter
in reset, which results in no signals being received at the PFD.
When Register 6, Bit 17 = 0 on a write to Register 0, the SDM is
temporarily set to a fractional value of 0. The SD reset ensures a
consistent fractional spur pattern but also results in a glitch in
the output frequency when the N divider momentarily outputs
Rev. 0 | Page 21 of 30
ADF41513
Data Sheet
FUNCTION REGISTER (R6)
CONTROL
BITS
BLEED CURRENT
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BP1 BE1
0
IM1 A1
L1 SR1 CP1
1
0
0
0
0
0
LDP2 LDP1 PP1 PD C31 CR1
C4(0) C3(1) C2(1) C1(0)
COUNTER
CR1 RESET
0
0
1
BLEED POLARITY
NEGATIVE
IM1
0
INT MODE
0
1
DISABLED
ENABLED
SD ON (FRAC-N)
SD OFF (INT-N)
CP THREE-STATE
PD ON
POSITIVE
CP1
1
0
1
DISABLED
ENABLED
CP
C31 THREE-STATE
A1 ABP
0
0
1
BLEED ENABLE
DISABLED
WIDE
0
1
0
1
DISABLED
ENABLED
NARROW
ENABLED
PD
POWER DOWN
L1
LOL
0
1
NORMAL OPERATION
POWER-DOWN DEVICE
0
1
DISABLED
ENABLED
PP1 PD POLARITY
SR1
0
SD RESET
0
1
NEGATIVE
POSITIVE
RESET ON R0 WRITE
NO RESET
1
LDP2 LDP1 R9[31] R9[30]
LDP
...
BC8 BC7
BC2 BC1 BLEED CURRENT (µA)
2.7kΩ 1.8kΩ
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
4.3ns
2.8ns
1.7ns
0.9ns
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
0
3.81
7.63
11.44
.
5.72
11.44
17.17
.
0
0
1
1
0
1
0
1
5.2ns
3.5ns
2.1ns
1.2ns
0
0
0
0
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
961.33
965.15
968.96
972.78
1442
1447.72
1453.44
1459.17
0
0
1
1
0
1
0
1
7.0ns
4.7ns
2.9ns
1.6ns
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
11.5ns
7.9ns
4.9ns
2.8ns
Figure 29. Register 6 (R6) Map
Rev. 0 | Page 22 of 30
Data Sheet
ADF41513
Prescaler (PS) Bias
Set these bits to 0b10.
CLK Divider Mode
REGISTER 7 (R7) MAP
Lock Detector Count (LD_COUNT)
LD_COUNT sets the initial value of the lock detect counter. See
the Lock Detector section for more information about the
operation of the lock detector.
Setting Register 7, Bits[19:18] = 0b10 enables a phase resync.
See the Phase Resync section for more information.
Lock Detect Clock Select (LD_CLK_SEL)
When not using phase resync, set Register 7, Bits[19:18] = 0b00.
The lock detector checks for lock on every phase comparison
cycle when LD CLK SEL = 1. Otherwise, the lock detector
checks for lock on every 32nd cycle. Use LD CLK SEL = 1 to
speed up declaration of lock at the cost of reduced lock
indication stability during frequency changes.
CLK2 Divider Value
Register 7, Bits[17:6] control the CLK2 divider value. The CLK2
divider value controls the timing of the phase resync pulse. See
the Phase Resync section for more information.
SDM to N Divider Timing Adjustment (N Delay)
This control adjusts the timing between the SDM output and
the N divider. Set these bits to 0b01.
CLOCK 2 REGISTER (R7)
CLK
DIVIDER
MODE
CONTROL
BITS
12-BIT CLK DIVIDER VALUE
2
N DELAY PS BIAS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LC3 LC2 LC1 C4(0) C3(1) C2(1) C1(1)
0
0
0
0
LS1
0
0
ND2 ND1 PB2 PB1 C2 C1 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
...
DB17 DB16
DB7 DB6
CLK DIVIDER VALUE
2
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
0
1
2
3
.
.
.
PB2 PB1 PRESCALER BIAS
0
0
1
1
0
1
0
1
RESERVED
RESERVED
PROGRAM THIS VALUE
RESERVED
LC2 LC1 LOCK DETECTOR COUNT
LC3
4,092
4,093
4,094
4,095
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
2
4
ND2 ND1 SDM TO N DELAY
8
0
0
1
1
0
1
0
1
PROGRAM THIS VALUE
RESERVED
16
32
64
128
256
C2
C1
CLK DIV MODE
RESERVED
0
0
1
1
0
1
0
1
CLK DIVIDER OFF
RESERVED
RESERVED
PHASE RESYNC
RESERVED
LS1 LOCK DETECTOR CLOCK SELECT
0
1
fPFD ÷ 32
fPFD
Figure 30. Register 7 (R7) Map
Rev. 0 | Page 23 of 30
ADF41513
Data Sheet
REGISTER 8 (R8) MAP
REGISTER 9 (R9) MAP
Lock Detector Bias
Set all reserved bits to zero.
The lock detector window size is set by adjusting the lock
detector bias in conjunction with the lock detector precision
bits (Register 6, Bits[9:8]). See the Lock Detector section.
RESERVED REGISTER (R8)
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C4(1) C3(0) C2(0) C1(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 31. Register 8 (R8) Map
LOCK DETECTOR BIAS REGISTER (R9)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C4(1) C3(0) C2(0) C1(1)
LB2 LB1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LB2 LB1 LOCK DETECTOR BIAS
0
0
1
1
0
1
0
1
40µA
30µA
20µA
10µA
Figure 32. Register 9 (R9) Map
Rev. 0 | Page 24 of 30
Data Sheet
ADF41513
REGISTER 10 (R10) MAP
REGISTER 11 (R11) MAP
Power-Down Select
Set all reserved bits to zero.
Only one power-down option is available. Program Register 11,
Bit 31 = 1. Set Register 6, Bit 6 = 1 to power down the device.
RESERVED REGISTER (R10)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C4(1) C3(0) C2(1) C1(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 33. Register 10 (R10) Map
POWER-DOWN SELECT REGISTER (R11)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PDS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C4(1) C3(0) C2(1) C1(1)
POWER-DOWN SELECT
RESERVED
PDS
0
PROGRAM THIS VALUE
1
Figure 34. Register 11 (R11) Map
Rev. 0 | Page 25 of 30
ADF41513
Data Sheet
Master Reset
REGISTER 12 (R12) MAP
Register 12, Bit 22 = 1 resets all registers to all zeros.
MUXOUT
Register 12, Bits[31:28] select the MUXOUT signal. Register
data can be read either by selecting the serial data output or via
a readback. Serial data output sends the 32 bits of register data
that was written in the previous access. A readback sends the
data as defined by the readback select bits, Register 12,
Bits[19:14].
LE Select
Register 12, Bit 20 = 1 synchronizes the rising edge of LE on an
SPI write with the falling edge of the reference signal. This recom-
mended setting ensures there is no glitch from asynchronous
loading. Set Register 12, Bit 20 = 0 if it is necessary to write data
into the ADF41513 when no reference is present.
Logic Level
Readback Select
Register 12, Bit 27 selects the DLD and MUXOUT logic level.
Register 12, Bits[19:14] select the value to be read back. For
more information, see the Readback section.
MUXOUT REGISTER (R12)
READBACK
SELECT
CONTROL
BITS
MUXOUT
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M4 M3 M2 M1
LL
0
0
0
0
MR1
0
L1
R6
R5
R4
R3
R2
R1
0
0
0
0
0
0
0
0
0
0
C4(1) C3(1) C2(0) C1(0)
R6 R5 R4 R3 R2 R1
READBACK SELECT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
32 ZEROS
L1 LE SEL
LL DLD AND MUXOUT LEVEL
R0
0
1
LE FROM PIN
0
1
1.8V LOGIC HIGH
3.3V LOGIC HIGH
R1
LE SYNCHRONIZED WITH
RISING EDGE OF
R2
R3
R DIVIDER OUTPUT
R4
MR1 MASTER RESET
R5
0
1
NORMAL OPERATION
R6
RESETS ALL REGISTERS
R7
R8
R9
R10
R11
R12
R13
M4 M3 M2 M1 OUTPUT
INT (16-BIT R0[19:4] VALUE)
FRAC (7-BIT R1[10:4] VALUE)
32 ZEROS
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
THREE-STATE OUTPUT
DV
DD
DGND
RESERVED
R DIVIDER OUTPUT
N DIVIDER OUTPUT
RESERVED
REVISION CODE
RESERVED
RESERVED
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
READBACK
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CLK1 DIVIDER OUTPUT
RESERVED
RESERVED
R DIVIDER/2
N DIVIDER/2
RESERVED
RESERVED
RESERVED
Figure 35. Register 12 (R12) Map
Rev. 0 | Page 26 of 30
Data Sheet
ADF41513
REGISTER 13 (R13) MAP
Set all reserved bits to zero.
RESERVED REGISTER (R13)
CONTROL
BITS
RESERVED
DB3
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
DB2 DB1 DB0
C4(1) C3(1) C2(0) C1(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 36. Register 13 (R13) Map
Rev. 0 | Page 27 of 30
ADF41513
Data Sheet
APPLICATIONS INFORMATION
Note that 671088.64 is rounded to 671,089, resulting in a small
frequency error. For exact frequency, use the variable
modulus mode.
INITIALIZATION SEQUENCE
The following sequence of registers is the correct sequence for
initial power-up of the ADF41513 after the correct application
of voltages to the supply pins:
RF SYNTHESIZER: A WORKED EXAMPLE OF
VARIABLE MODULUS MODE
1. Register 13
2. Register 12
3. Register 11
4. Register 10
5. Register 9
6. Register 8
7. Register 7
8. Register 6
9. Register 5
10. Register 4
11. Register 3
12. Register 2
13. Register 1
14. Register 0
The following is an example how to program the ADF41513
synthesizer:
RFOUT = fPFD × (INT + (FRAC1 + (FRAC2/MOD2))/225)
(8)
where:
RFOUT is the output frequency of the external VCO.
INT is a 16-bit value set by Bits[19:4] in Register 0. In Integer N
mode, INT is 20 to 511 for a 4/5 prescaler and 64 to 1023 for a 8/9
prescaler, and in fractional-N mode, INT is 23 to 511 for a 4/5
prescaler and 75 to 1023 for a 8/9 prescaler.
FRAC1 is a 25-bit value set by Bits[28:4] in Register 1.
FRAC2 is a 24-bit value set by Bits[27:4] in Register 3.
MOD2 is a 24-bit value set by Bits[27:4] in Register 4.
f
PFD is the PFD frequency.
RF SYNTHESIZER: A WORKED EXAMPLE OF 25-BIT
FIXED MODULUS MODE
For example, in a system where a 12.102 GHz RFOUT is required
and a 100 MHz fPFD is available,
The following equation governs how to program the
synthesizer:
INT = int(RFOUT/fPFD) = 121
FRAC1 = int(((RFOUT/fPFD) – INT) × 225) = 671,088
RFOUT = (INT + (FRAC1/225)) × fPFD
(7)
where:
int() makes an integer of the argument in parentheses.
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC1 is the fractional numerator.
Remainder = FRAC2/MOD2 = 0.64
where:
FRAC2 = 64.
MOD2 = 100.
fPFD is the PFD frequency.
For example, in a system where a 12.102 GHz RF frequency
output (RFOUT) is required and a 100 MHz reference frequency
input (REFIN) is available, the frequency resolution, fRES, is
MODULUS
The choice of modulus (MOD) depends on the reference signal
(REFIN) available and the channel resolution (fRES) required at
the RF output.
f
f
RES = REFIN/225
RES = 100 MHz/225
= 2.98 Hz
REFERENCE DOUBLER AND REFERENCE DIVIDER
The on-chip reference doubler allows the input reference signal
to be doubled. Doubling is useful for increasing the PFD
comparison frequency. Setting the PFD frequency higher
improves the noise performance of the system. Doubling the
PFD frequency usually improves noise performance by 3 dB. It
is important to note that the reference input cannot operate
above 225 MHz when the reference doubler is on. The PFD
maximum operating frequency is 250 MHz (integer N mode) or
125 MHz (fractional-N mode) due to a limitation in the speed
of the Σ-Δ circuit.
From Equation 1 and Equation 2,
f
PFD = (100 MHz × (1 + 0)/1) = 100 MHz
12.102 GHz = 100 MHz × (N + FRAC/225)
Calculating the INT and FRAC values,
INT = int(RFOUT/fPFD) = 121
FRAC1 = (int(RFOUT/fPFD) − INT) × 225 = 671088.64 ≈
671089
where:
The reference divide by 2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency.
INT is the 16-bit INT value in Register 0.
FRAC1 is the 25-bit FRAC1 value in Register 1.
int() makes an integer of the argument in parentheses.
Rev. 0 | Page 28 of 30
Data Sheet
ADF41513
Phase resync is enabled by setting Register 7, Bits[19:18] =
0b10. When phase resync is enabled, an internal timer generates
sync signals at intervals of tSYNC given by the following formula:
SPUR MECHANISMS
This section describes the two different spur mechanisms that
arise with a PLL, and how to minimize them in the ADF41513.
tSYNC = CLK1 × CLK2 × tPFD
where:
CLK1 is the decimal value programmed in Register 5, Bits[15:4].
CLK2 is the decimal value programmed in Register 7, Bits[17:6].
(9)
Integer Boundary Spurs
Interactions between the RF VCO frequency and the reference
frequency cause integer boundary spurs. When these
frequencies are not integer related (the point of a fractional-N
synthesizer), spur sidebands appear on the VCO output
spectrum at an offset frequency that corresponds to the beat
note or difference frequency between an integer multiple of the
reference and the VCO frequency. These spurs are attenuated by
the loop filter and are more noticeable on channels close to
integer multiples of the reference where the difference
frequency can be inside the loop bandwidth.
tPFD is the PFD reference period (1/fPFD).
When a new frequency is programmed, the second sync pulse
after the LE rising edge resynchronizes the output phase to the
reference. Program the tSYNC time to a value that is at least as
long as the worst case lock time to guarantee that the phase
resync occurs after the last cycle slip in the PLL settling
transient.
Reference Spurs
In the example shown in Figure 37, tSYNC is set to 550 µs. The
second sync pulse and any later sync pulses are ignored.
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. Feedthrough of low
levels of on-chip reference switching noise, through the RFINA
pin or the RFINB pin back to the VCO, can result in reference
spur levels as high as −90 dBc. PCB layout must ensure
adequate isolation between VCO traces and the input reference
to avoid a possible feedthrough path on the board.
LE
SYNC
(INTERNAL)
LAST CYCLE SLIP
FREQUENCY
PLL SETTLES TO
INCORRECT PHASE
PLL SETTLES TO
CORRECT PHASE
AFTER RESYNC
PHASE RESYNC
PHASE
The output of a 25-bit fractional-N PLL can settle to any of the
225 phase offsets with respect to the input reference. The phase
resync feature in the ADF41513 produces a consistent output
phase offset with respect to the input reference. This consistent
output phase offset with respect to the input reference is neces-
sary in applications where the output phase and frequency are
important, such as digital beamforming. See the Phase
Programmability section to program a specific RF output phase
when using phase resync.
300 400 500 600 700 800 900
TIME (µs)
–100
0
100 200
1000
Figure 37. Phase Resync Example
Phase Programmability
The phase word in Register 2 controls the RF output phase. As
this word is changed from 0 to 212, the RF output phase changes
over a 360° range in steps of phase value × 360°/212.
Rev. 0 | Page 29 of 30
ADF41513
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
AREA
PIN 1
IONS
INDICATOR AR EA OP T
(SEE DETAIL A)
24
19
18
1
0.50
BSC
2.85
2.70 SQ
2.45
EXPOSED
PAD
13
12
6
7
0.50
0.40
0.30
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8
Figure 38. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-8)
Dimensions shown in millimeters
ORDERING GUIDE
Parameter1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
CP-24-8
CP-24-8
ADF41513BCPZ
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board Without VCO
ADF41513BCPZ-RL7
EV-ADF41513SD1Z
EV-ADF41513SD2Z
Evaluation Board with On-Board VCO
1 Z = RoHS Compliant Part.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16805-0-1/19(0)
Rev. 0 | Page 30 of 30
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