ADF4153_技术文档

Fractional-N Frequency Synthesizer

ADF4153

FEATURES

GENERAL DESCRIPTION

RF bandwidth 500 MHz to 4 GHz

2.7 V to 3.3 V power supply

The ADF4153 is a fractional-N frequency synthesizer that

implements local oscillators in the upconversion and

downconversion sections of wireless receivers and transmitters.

It consists of a low noise digital phase frequency detector

(PFD), a precision charge pump, and a programmable reference

divider. There is a Σ-Δ based fractional interpolator to allow

programmable fractional-N division. The INT, FRAC, and

MOD registers define an overall N divider (N = (INT +

(FRAC/MOD))). In addition, the 4-bit reference counter (R

counter) allows selectable REFIN frequencies at the PFD input.

A complete phase-locked loop (PLL) can be implemented if the

synthesizer is used with an external loop filter and a voltage

controlled oscillator (VCO).

Separate V_Pallows extended tuning voltage

Programmable dual-modulus prescaler 4/5, 8/9

Programmable charge pump currents

3-wire serial interface

Analog and digital lock detect

Power-down mode

Pin compatible with the

ADF4110/ADF4111/ADF4112/ADF4113 and ADF4106

Programmable modulus on fractional-N synthesizer

Trade-off noise versus spurious performance

APPLICATIONS

CATV equipment

Base stations for mobile radio (GSM, PCS, DCS,

CDMA, WCDMA)

Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANs

Control of all on-chip registers is via a simple 3-wire interface.

The device operate with a power supply ranging from 2.7 V to

3.3 V and can be powered down when not in use.

Communications test equipment

FUNCTIONAL BLOCK DIAGRAM

AV

DV

V

SDV

R

SET

DD

P

DD

ADF4153

REFERENCE

4-BIT

R COUNTER

×2

REF

IN

DOUBLER

+

PHASE

CP

CHARGE

PUMP

FREQUENCY

DETECTOR

V

DD

–

HIGH Z

DGND

LOCK

DETECT

CURRENT

SETTING

OUTPUT

MUX

MUXOUT

V

R

N

DD

DIV

RFCP3 RFCP2 RFCP1

DIV

RF

A

B

IN

N-COUNTER

IN

THIRD ORDER

FRACTIONAL

INTERPOLATOR

CLOCK

DATA

LE

FRACTION

REG

MODULUS

REG

INTEGER

REG

24-BIT

DATA

REGISTER

AGND

DGND

CPGND

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

ADF4153

TABLE OF CONTENTS

Specifications..................................................................................... 3

R Divider Register, R1................................................................ 17

Control Register, R2 ................................................................... 17

Noise and Spur Register, R3...................................................... 18

Reserved Bits............................................................................... 18

RF Synthesizer: A Worked Example ........................................ 18

Modulus....................................................................................... 19

Reference Doubler and Reference Divider ............................. 19

12-Bit Programmable Modulus................................................ 19

Spurious Optimization and Fastlock ....................................... 19

Phase Resync and Spur Consistency ....................................... 19

Spurious Signals—Predicting Where They Will Appear....... 20

Filter Design—ADIsimPLL....................................................... 20

Interfacing ................................................................................... 20

PCB Design Guidelines for Chip Scale Package .................... 21

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Pin Function Descriptions...................... 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 10

Reference Input Section............................................................. 10

RF Input Stage............................................................................. 10

RF INT Divider........................................................................... 10

INT, FRAC, MOD, and R Relationship.................................... 10

RF R COUNTER ........................................................................ 10

Phase Frequency Detector (PFD) and Charge Pump............ 11

MUXOUT and LOCK Detect................................................... 11

Input Shift Registers................................................................... 11

Program Modes .......................................................................... 11

N Divider Register, R0 ............................................................... 17

REVISION HISTORY

1/04—Data Sheet Changed from a REV. 0 to a REV. A

Renumbered Figures and Tables.............................. UNIVERSAL

Changes to Specifications............................................................... 3

Changes to Pin Function Description .......................................... 7

Changes to RF Power-Down section ..........................................17

Changes to PCB Design Guidelines for Chip Scale

Package section ..............................................................................21

Updated Outline Dimensions......................................................22

Updated Ordering Guide..............................................................22

7/03—Revision 0: Initial Version

Rev. A | Page 2 of 24

ADF4153

SPECIFICATIONS¹

AV_DD= DV_DD= SDV_DD= 2.7 V to 3.3 V; V_P= AV_DDto 5.5 V; AGND = DGND = 0 V; T_A= T_MINto T_MAX, unless otherwise noted; dBm

referred to 50 Ω.

Table 1.

Parameter

B Version

Unit

Test Conditions/Comments

RF CHARACTERISTICS (3 V)

RF Input Frequency (RF_IN)²

See Figure 17 for input circuit.

−8 dBm/0 dBm min/max. For lower frequencies,

ensure slew rate (SR) > 396 V/µs.

0.5/4.0

1.0/4.0

GHz min/max

−10 dBm/0 dBm min/max.

REFERENCE CHARACTERISTICS

REF_INInput Frequency²

See Figure 16 for input circuit.

For f < 10 MHz, use a dc-coupled CMOS compatible

square wave, slew rate > 21 V/µs.

10/250

MHz min/max

REF_INInput Sensitivity

0.7/AV_DD

0 to AV_DD

10

V p-p min/max

V max

pF max

AC-coupled.

CMOS compatible.

REF_INInput Capacitance

REF_INInput Current

PHASE DETECTOR

Phase Detector Frequency³

CHARGE PUMP

100

µA max

32

MHz max

I_CPSink/Source

High Value

Low Value

Absolute Accuracy

R_SETRange

I_CPThree-State Leakage Current

Matching

I_CPvs. V_CP

I_CPvs. Temperature

LOGIC INPUTS

Programmable. See Table 5.

With R_SET= 5.1 kΩ.

5

mA typ

µA typ

% typ

kΩ min/max

nA typ

% typ

312.5

2.5

1.5/10

1

2

With R_SET= 5.1 kΩ.

Sink and source current.

0.5 V < V_CP< V_P– 0.5.

V_CP= V_P/2.

% typ

V_INH, Input High Voltage

V_INL, Input Low Voltage

I_INH/I_INL, Input Current

C_IN, Input Capacitance

LOGIC OUTPUTS

V_OH, Output High Voltage

V_OL, Output Low Voltage

POWER SUPPLIES

AV_DD

1.4

0.6

1

V min

V max

µA max

pF max

10

1.4

0.4

V min

V max

Open-drain 1 kΩ pull-up to 1.8 V.

I_OL= 500 µA.

2.7/3.3

AV_DD

AV_DD/5.5

24

V min/V max

DV_DD, SDV_DD

V_P

I_DD

V min/V max

mA max

4

20 mA typical.

Low Power Sleep Mode

NOISE CHARACTERISTICS

Phase Noise Figure of Merit⁵

ADF4153 Phase Noise Floor⁶

1

µA typ

−217

−147

−143

dBc/Hz typ

@ 10 MHz PFD frequency.

@ 26 MHz PFD frequency.

@ VCO output.

Phase Noise Performance⁷

1750 MHz Output⁸

−106

dBc/Hz typ

@ 1 kHz offset, 26 MHz PFD frequency.

See footnotes on next page.

Rev. A | Page 3 of 24

ADF4153

¹Operating temperature is B version: −40°C to +80°C.

²Use a square wave for frequencies below f_MIN

.

³Guaranteed by design. Sample tested to ensure compliance.

⁴AC coupling ensures AV_DD/2 bias. See Figure 16 for typical circuit.

⁵This figure can be used to calculate phase noise for any application. Use the formula –217 + 10log(f_PFD) + 20logN to calculate in-band phase noise performance as seen

at the VCO output. The value given is the lowest noise mode.

⁶The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

The value given is the lowest noise mode.

⁷The phase noise is measured with the EVAL-ADF4153EB1 evaluation board and the HP8562E spectrum analyzer.

⁸f_REFIN= 26 MHz; f_PFD= 10 MHz; offset frequency = 1 kHz; RF_OUT= 1750 MHz; N = 175; loop B/W = 20 kHz; lowest noise mode.

Rev. A | Page 4 of 24

ADF4153

TIMING CHARACTERISTICS¹

AV_DD= DV_DD= SDV_DD= 2.7 V to 3.3 V; V_P= AV_DDto 5.5 V; AGND = DGND = 0 V; T_A= T_MINto T_MAX, unless otherwise noted; dBm

referred to 50 Ω.

Table 2.

Parameter

Limit at T_MINto T_MAX(B Version)

Unit

Test Conditions/Comments

LE Setup Time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

20

10

25

10

20

ns min

DATA to CLOCK Setup Time

DATA to CLOCK Hold Time

CLOCK High Duration

CLOCK Low Duration

CLOCK to LE Setup Time

LE Pulse Width

¹Guaranteed by design but not production tested.

t₄

t₅

CLOCK

t₂

t₃

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

DB23 (MSB)

DB22

DB2

DATA

LE

t₇

t₁

t₆

LE

Figure 2. Timing Diagram

Rev. A | Page 5 of 24

ADF4153

ABSOLUTE MAXIMUM RATINGS^{1, 2, 3, 4}

T_A= 25°C, unless otherwise noted.

Table 3.

Parameter

Rating

V_DDto GND

−0.3 V to +4 V

V_DDto V_DD

V_Pto GND

V_Pto V_DD

Digital I/O Voltage to GND

Analog I/O Voltage to GND

REF_IN, RF_INto GND

−0.3 V to +0.3 V

−0.3 V to +5.8 V

−0.3 V to V_DD+ 0.3 V

Operating Temperature Range

Industrial (B Version)

−40°C to +85°C

−65°C to +150°C

150°C

150.4°C/W

122°C/W

Storage Temperature Range

Maximum Junction Temperature

TSSOP θ_JAThermal Impedance

LFCSP θ_JAThermal Impedance (Paddle Soldered)

LFCSP θ_JAThermal Impedance (Paddle Not Soldered)

Lead Temperature, Soldering

Vapor Phase (60 sec)

216°C/W

215°C

220°C

Infrared

¹Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

²This device is a high performance RF integrated circuit with an ESD rating of < 2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and

assembly.

³GND = AGND = DGND = 0 V.

⁴V_DD= AV_DD= DV_DD= SDV_DD

.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page 6 of 24

ADF4153

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

R

1

2

3

4

5

6

7

8

16

V

P

SET

CP

15 DV

DD

PIN 1

15 MUXOUT

14 LE

13 DATA

12 CLK

11 SDV

DD

CPGND

AGND

1

2

3

4

5

INDICATOR

CPGND

AGND

14 MUXOUT

13 LE

ADF4153

TOP VIEW

ADF4153

RF

B

A

TOP VIEW

IN

RF

B

A

12 DATA

11 CLK

IN

(Not to Scale)

RFI

AV

DD

10 SDV

DD

REF

IN

9 DGND

Figure 3. TSSOP Pin Configuration

Figure 4. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

TSSOP

LFCSP

Mnemonic Description

1

19

R_SET

Connecting a resistor between this pin and ground sets the maximum charge pump output current.

The relation ship between I_CPand R_SETis

25.5

R_SET

I_{CP max}

=

With R_SET= 5.1 kΩ, I_CPmax= 5 mA.

2

20

CP

Charge Pump Output. When enabled, this provides I_CPto the external loop filter, which in turn drives

the external VCO.

3

4

5

1

2, 3

4

CPGND

AGND

RF_INB

Charge Pump Ground. This is the ground return path for the charge pump.

Analog Ground. This is the ground return path of the prescaler.

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a

small bypass capacitor, typically 100 pF (see Figure 17).

6

7

5

6, 7

RF_INA

AV_DD

Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.

Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be

placed as close as possible to this pin. AV_DDhas a value of 3 V 10%. AV_DDmust have the same voltage

as DV_DD

.

8

REF_IN

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and an equivalent input

resistance of 100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it

can be ac-coupled.

9

10

9, 10

11

DGND

SDV_DD

Digital Ground.

∑-∆ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to

this pin. SDV_DDhas a value of 3 V 10%. SDV_DDmust have the same voltage as DV_DD

.

11

12

13

14

15

12

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the shift register on the CLK rising edge. This input is a high impedance CMOS input.

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input

is a high impedance CMOS input.

Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of

the four latches, the latch being selected using the control bits.

This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.

13

DATA

LE

14

15

MUXOUT

DV_DD

16, 17

Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should

be placed as close as possible to this pin. DV_DDhas a value of 3 V 10%. DV_DDmust have the same

voltage as AV_DD

.

16

18

V_P

Charge Pump Power Supply. This should be greater than or equal to V_DD. In systems where V_DDis 3 V, it

can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

Rev. A | Page 7 of 24

ADF4153

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5 to Figure 10: RF_OUT= 1.722 GHz, PFD Freq = 26 MHz, INT = 66, Channel Spacing = 200 kHz, Modulus = 130, Fraction = 1/130,

and I_CP= 5 mA.

Loop Bandwidth = 20 kHz, Reference = Fox 10 MHz TCXO, VCO = Vari-L VCO190-1750T, Eval Board = Eval-ADF4153EB1,

measurements taken on HP8562E spectrum analyzer.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

V

= 3V, V = 5V

P

DD

= 5mA

V

= 3V, V = 5V

P

DD

I = 5mA

CP

I

CP

REFERENCE

LEVEL = –4.2dBm

REFERENCE

LEVEL = –4dBm

PFD FREQUENCY = 26MHz

CHANNEL STEP = 200kHz

LOOP BANDWIDTH = 20kHz

LOWEST NOISE MODE

N = 66 1/130

PFD FREQUENCY = 26MHz

CHANNEL STEP = 200kHz

LOOP BANDWIDTH = 20kHz

LOWEST NOISE MODE

N = 66 1/130

RBW = 10Hz

–71dBc@200kHz

–102dBc/Hz

–400kHz

–200kHz

1.722GHz

200kHz

400kHz

–2kHz

–1kHz

1.722GHz

1kHz

2kHz

Figure 5. Phase Noise (Lowest Noise Mode)

Figure 8. Spurs (Lowest Noise Mode)

0

–10

–20

–30

–40

–50

–60

–70

–80

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

V

= 3V, V = 5V

P

DD

= 5mA

V

I

= 3V, V = 5V

P

DD

= 5mA

I

CP

REFERENCE

LEVEL = –4.2dBm

REFERENCE

LEVEL = –4.2dBm

CP

PFD FREQUENCY = 26MHz

CHANNEL STEP = 200kHz

LOOP BANDWIDTH = 20kHz

LOW NOISE AND

PFD FREQUENCY = 26MHz

CHANNEL STEP = 200kHz

LOOP BANDWIDTH = 20kHz

LOW NOISE AND

SPUR MODE

N = 66 1/130

RBW = 10Hz

N = 66 1/130

RBW = 10Hz

–74dBc@200kHz

–95dBc/Hz

–90

–100

–2kHz

–1kHz

1.722GHz

1kHz

2kHz

–400kHz

–200kHz

1.722GHz

200kHz

400kHz

Figure 6. Phase Noise (Low Noise Mode and Spur Mode)

Figure 9. Spurs (Low Noise and Spur Mode)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

V

= 3V, V = 5V

P

DD

I = 5mA

CP

V

I

= 3V, V = 5V

P

DD

= 5mA

REFERENCE

LEVEL = –4.2dBm

REFERENCE

LEVEL = –4.2dBm

CP

PFD FREQUENCY = 26MHz

CHANNEL STEP = 200kHz

LOOP BANDWIDTH = 20kHz

LOWEST SPUR NOISE

N = 66 1/130

PFD FREQUENCY = 26MHz

CHANNEL STEP = 200kHz

LOOP BANDWIDTH = 20kHz

LOWEST SPUR MODE

N = 66 1/130

RBW = 10Hz

–90dBc/Hz

–2kHz

–1kHz

1.722GHz

1kHz

2kHz

–400kHz

–200kHz

1.722GHz

200kHz

400kHz

Figure 7. Phase Noise (Lowest Spur Mode)

Figure 10. Spurs (Lowest Spur Mode)

Rev. A | Page 8 of 24

ADF4153

–130

–140

–150

–160

–170

–80

–85

–90

–95

–100

–105

–110

0

5

10

15

20

25

30

35

100

1000

10000

100000

R

VALUE (kΩ)

SET

PHASE DETECTOR FREQUENCY (kHz)

Figure 11. PFD Noise Floor vs. PFD Frequency (Lowest Noise Mode)

Figure 14. Phase Noise vs. R_SET

5

–90

–92

–94

–96

0

–5

–10

–15

–20

–25

–30

–35

P = 4/5

–98

–100

P = 8/9

–102

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

–104

–60

–40

–20

0

20

40

60

80

100

FREQUENCY (GHz)

TEMPERATURE(°C)

Figure 12. RF Input Sensitivity

Figure 15. Phase Noise vs. Temperature

6

5

4

3

2

1

0

–1

–2

–3

–4

–5

–6

0

1

2

3

4

5

V

(V)

CP

Figure 13. Charge Pump Output Characteristics

Rev. A | Page 9 of 24

ADF4153

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

INT, FRAC, MOD, AND R RELATIONSHIP

The reference input stage is shown in Figure 16. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REF_INpin

on power-down.

The INT, FRAC, and MOD values, in conjunction with the

R counter, make it possible to generate output frequencies that

are spaced by fractions of the phase frequency detector (PFD).

See the RF Synthesizer: A Worked Example section for more

information. The RF VCO frequency (RF_OUT) equation is

POWER-DOWN

CONTROL

RF_OUT= F_PFD

×

(

INT +

(

FRAC MOD

))

(1)

100kΩ

where RF_OUTis the output frequency of external voltage

NC

SW2

controlled oscillator (VCO).

TO R COUNTER

REF

IN

NC

SW1

BUFFER

F_PFD= REF_IN

where:

×

(

1 + D R

)

(2)

SW3

NO

Figure 16. Reference Input Stage

REF_INis the reference input frequency.

D is the REF_INdoubler bit.

RF INPUT STAGE

The RF input stage is shown in Figure 17. It is followed by a

2-stage limiting amplifier to generate the current mode logic

(CML) clock levels needed for the prescaler.

R is the preset divide ratio of binary 4-bit programmable

reference counter (1 to 15).

1.6V

INT is the preset divide ratio of binary 9-bit counter (31 to 511).

BIAS

GENERATOR

AV

DD

MOD is the preset modulus ratio of binary 12-bit

programmable FRAC counter (2 to 4095).

2kΩ

FRAC is the preset fractional ratio of binary 12-bit

programmable FRAC counter (0 to MOD).

RF

A

B

IN

RF R COUNTER

The 4-bit RF R counter allows the input reference frequency

(REF_IN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 15 are allowed.

IN

RF N DIVIDER

N = INT + FRAC/MOD

AGND

FROM RF

TO PFD

INPUT STAGE

N-COUNTER

Figure 17. RF Input Stage

THIRD ORDER

FRACTIONAL

INTERPOLATOR

RF INT DIVIDER

The RF INT CMOS counter allows a division ratio in the PLL

feedback counter. Division ratios from 31 to 511 are allowed.

INT

REG

MOD

REG

FRAC

VALUE

Figure 18. A and B Counters

Rev. A | Page 10 of 24

ADF4153

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

INPUT SHIFT REGISTERS

The ADF4153 digital section includes a 4-bit RF R counter, a 9-

bit RF N counter, a 12-bit FRAC counter, and a 12-bit modulus

counter. Data is clocked into the 24-bit shift register on each

rising edge of CLK. The data is clocked in MSB first. Data is

transferred from the shift register to one of four latches on the

rising edge of LE. The destination latch is determined by the

state of the two control bits (C2 and C1) in the shift register.

These are the 2 LSBs, DB1 and DB0, as shown in Figure 2. The

truth table for these bits is shown in Table 5. Table 6 shows a

summary of how the latches are programmed.

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 19 is a simplified schematic.

The PFD includes a fixed delay element that sets the width of

the antibacklash pulse, which is typically 3 ns. This pulse

ensures that there is no dead zone in the PFD transfer function,

and gives a consistent reference spur level.

UP

HI

D1

Q1

U1

CLR1

+IN

PROGRAM MODES

Table 5 through Table 10 show how to set up the program

modes in the ADF4153.

CHARGE

PUMP

CP

U3

DELAY

DOWN

The ADF4153 programmable modulus is double buffered. This

means that two events have to occur before the part uses a new

modulus value. First, the new modulus value is latched into the

device by writing to the R divider register. Second, a new write

must be performed on the N divider register. Therefore, any

time that the modulus value has been updated, the N divider

register must be written to after this, to ensure that the modulus

value is loaded correctly.

CLR2

D2 Q2

HI

U2

–IN

Figure 19. PFD Simplified Schematic

MUXOUT AND LOCK DETECT

Table 5. C2 and C1 Truth Table

Control Bits

The output multiplexer on the ADF4153 allows the user to

access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 (see Table 8).

Figure 20 shows the MUXOUT section in block diagram form.

C2

0

1

C1

0

1

0

1

Register

N Divider Register

R Divider Register

Control Register

Noise and Spur Register

The N-channel open-drain analog lock detect should be

operated with an external pull-up resistor of 10 kΩ nominal.

When lock has been detected, it is high with narrow low-going

pulses.

DV

DD

THREE-STATE OUTPUT

LOGIC LOW

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

ANALOG LOCK DETECT

LOGIC HIGH

MUXOUT

MUX

CONTROL

DGND

Figure 20. MUXOUT Schematic

Rev. A | Page 11 of 24

ADF4153

Table 6. Register Summary

N DIVIDER REG

CONTROL

BITS

9-BIT INTEGER VALUE (INT)

12-BIT FRACTIONAL VALUE (FRAC)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9 DB8

F8 F7

DB7

F6

DB6

F5

DB5

F4

DB4 DB3 DB2

F3 F2 F1

DB1

DB0

FL1

N9

N8

N7

N6

N5

N4

N3

N2

N1

F12

F11

F10

F9

C2 (0) C1 (0)

R DIVIDER REG

4-BIT

R COUNTER

CONTROL

BITS

MUXOUT

12-BIT INTERPOLATOR MODULUS VALUE (MOD)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

P3 M3 M2 M1 P2 P1 R4 R3 R2 R1 M12 M11 M10 M9 M8

DB8

M7

DB7

M6

DB6

M5

DB5

M4

DB4 DB3 DB2

DB1 DB0

M3

M2

M1

C2 (0) C1 (1)

CONTROL REG

CP CURRENT

SETTING

CONTROL

BITS

RESYNC

DB15 DB14 DB13 DB12 DB11 DB10

DB9

CP2

DB8

CP1

DB7

CP0

DB6

U5

DB5

U4

DB4

U3

DB3

U2

DB2

U1

DB1

DB0

S4

S3

S2

S1

U6

CP3

C2 (1) C1 (0)

NOISE AND SPUR REG

CONTROL

BITS

NOISE AND SPUR

MODE

RESERVED

DB10

T9

DB9

T8

DB8

T7

DB7 DB6 DB5

T6 T5 T4

DB4

T3

DB3

T2

DB2

T1

DB1 DB0

C2 (1) C1 (1)

Rev. A | Page 12 of 24

ADF4153

Table 7. N Divider Register Map

CONTROL

BITS

9-BIT INTEGER VALUE (INT)

12-BIT FRACTIONAL VALUE (FRAC)

DB23 DB22

N9

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

F7

DB7

F6

DB6

F5

DB5

F4

DB4 DB3 DB2

F3 F2 F1

DB1

DB0

N8

N7

N6

N5

N4

N3

N2

N1

C2 (0) C1 (0)

FL1

F8

F12

F11

F10

F9

F12

F11

F10

F3

F2

F1

FRACTIONAL VALUE (FRAC)

0

.

1

0

.

1

0

.

1

..........

0

.

1

0

1

.

0

1

0

1

.

0

1

2

3

.

4092

1

..........

1

0

1

0

1

4093

4094

4095

N9

N8

N7

N6

N5

N4

N3

N2

N1

INTEGER VALUE (INT)

0

1

0

1

0

1

0

1

0

1

0

31

32

0

.

0

.

0

.

1

.

0

.

0

.

0

.

0

1

.

1

0

.

33

34

.

1

.

1

.

1

.

1

.

1

...

1

.

1

.

0

.

1

.

509

1

0

1

510

511

FL1

FASTLOCK

0

1

NORMAL OPERATION

FAST LOCK ENABLED

Rev. A | Page 13 of 24

ADF4153

Table 8. R Divider Register Map

CONTROL

BITS

MUXOUT

4-BIT R COUNTER

12-BIT INTERPOLATOR MODULUS VALUE (MOD)

DB23 DB22 DB21

DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

DB20 DB19

M1 P2

M3

M2

P1

R4

R3

R2

R1

M12

M11

M10

M9

M8

M7

M6

M5

M4

M3

M2

M1

P3

C2 (0) C1 (1)

P3 LOAD CONTROL

P1

PRESCALER

INTERPOLATOR

M12

M11

M10

M3

0

M2

1

M1

0

MODULUS VALUE (MOD)

0

1

NORMAL OPERATION

LOAD RESYNC

0

1

4/5

8/9

0

..........

2

0

.

0

.

0

.

..........

0

1

.

1

0

.

1

0

.

3

4

.

1

0

4092

1

..........

1

0

1

0

1

4093

4094

4095

RF R COUNTER

DIVIDE RATIO

R4

R3

R2

R1

0

.

0

1

.

0

1

0

.

1

0

1

0

.

1

2

3

4

.

1

0

12

1

0

1

0

1

13

14

15

M3

M2

M1

MUXOUT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

THREE-STATE OUTPUT

DIGITAL LOCK DETECT

N DIVIDER OUTPUT

LOGIC HIGH

R DIVIDER OUTPUT

ANALOG LOCK DETECT

FASTLOCK SWITCH

LOGIC LOW

Rev. A | Page 14 of 24

ADF4153

Table 9. Control Register Map

CP CURRENT

SETTING

CONTROL

BITS

RESYNC

DB15 DB14 DB13 DB12 DB11 DB10 DB9

S4 S3 S2 S1 U6 CP3 CP2

DB8

CP1

DB7

CP0

DB6

U5

DB5

U4

DB4

U3

DB3 DB2

U2 U1

DB1

DB0

C2 (1) C1 (0)

REFERENCE

DOUBLER

U6

0

1

DISABLED

ENABLED

U1

COUNTER RESET

0

1

DISABLED

ENABLED

S4

S3

S2

S1

RESYNC

0

.

0

.

0

1

.

1

0

1

.

1

2

3

U2

CP THREE-STATE

.

0

1

DISABLED

THREE-STATE

.

1

0

1

0

1

13

14

15

U3

POWER-DOWN

0

1

NORMAL OPERATION

POWER-DOWN

I

(mA)

CP

CP3

CP2

CP1

CP0

2.7kΩ

5.1kΩ

10kΩ

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.09

2.18

3.26

4.35

5.44

6.53

7.62

8.70

0.63

1.25

1.88

2.50

3.13

3.75

4.38

5.00

0.29

0.59

0.88

1.15

1.47

1.76

2.06

2.35

U4

LDP

0

1

3

5

U5

PD POLARITY

0

1

NEGATIVE

POSITIVE

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.54

1.10

1.64

2.18

2.73

3.27

3.81

4.35

0.31

0.63

0.94

1.25

1.57

1.88

2.19

2.50

0.15

0.30

0.44

0.588

0.74

0.88

1.03

1.18

Rev. A | Page 15 of 24

ADF4153

Table 10. Noise and Spur Register

NOISE AND SPUR

MODE

CONTROL

BITS

RESERVED

DB10

T9

DB9

T8

DB8

T7

DB7

T6

DB6

T5

DB5

T4

DB4

T3

DB3

T2

DB2

T1

DB1

DB0

C2 (1) C1 (1)

DB10, DB5, DB4, DB3

0

RESERVED

THESE BITS MUST BE SET TO 0

FOR NORMAL OPERATION.

DB9, DB8, DB7, DB6, DB2 NOISE AND SPUR SETTING

00000

11100

11111

LOWEST SPUR MODE

LOW NOISE AND SPUR MODE

LOWEST NOISE MODE

Rev. A | Page 16 of 24

ADF4153

takes the clock from the RF input stage and divides it down for

the counters. It is based on a synchronous 4/5 core. When set to

4/5, the maximum RF frequency allowed is 2 GHz. Therefore,

when operating the ADF4153 above 2 GHz, this must be set to

8/9. The prescaler limits the INT value.

N DIVIDER REGISTER, R0

With R0[1, 0] set to [0, 0], the on-chip N divider register is

programmed. Table 7 shows the input data format for

programming this register.

9-Bit INT Value

With P = 4/5, N_MIN= 31.

With P = 8/9, N_MIN= 91.

These nine bits control what is loaded as the INT value. This is

used to determine the overall feedback division factor. It is used

in Equation 1.

The prescaler can also influence the phase noise performance. If

INT < 91, a prescaler of 4/5 should be used. For applications

where INT > 91, P = 8/9 should be used for optimum noise

performance (see Table 8).

12-Bit FRAC Value

These 12 bits control what is loaded as the FRAC value into the

fractional interpolator. This is part of what determines the

overall feedback division factor. It is used in Equation 1. The

FRAC value must be less than or equal to the value loaded into

the MOD register.

4-Bit RF R Counter

The 4-bit RF R counter allows the input reference frequency

(REF_IN) to be divided down to produce the reference clock to

the phase frequency detector (PFD). Division ratios from 1 to

15 are allowed.

Fastlock

When set to logic high, this enables the fastlock. This sets the

charge pump current to its maximum value. When set to logic

low, the charge pump current is equal to the value programmed

in the function register.

12-Bit Interpolator Modulus

This programmable register sets the fractional modulus. This is

the ratio of the PFD frequency to the channel step resolution on

the RF output. Refer to the RF Synthesizer: A Worked Example

section for more information.

R DIVIDER REGISTER, R1

With R1[1, 0] set to [0, 1], the on-chip R divider register is

programmed. Table 8 shows the input data format for

programming this register.

The ADF4153 programmable modulus is double buffered. This

means that two events have to occur before the part uses a new

modulus value. First, the new modulus value is latched into the

device by writing to the R divider register. Second, a new write

must be performed on the N divider register. Therefore, any

time that the modulus value has been updated, the N divider

register must be written to after this, to ensure that the modulus

value is loaded correctly.

Load Control

When set to logic high, the value being programmed in the

modulus is not loaded into the modulus. Instead, it sets the

resync delay of the Σ-Δ. This is done to ensure phase resync

when changing frequencies. See the Phase Resync and Spur

Consistency section for more information and a worked

example.

CONTROL REGISTER, R2

MUXOUT

With R2[1, 0] set to [0, 1], the on-chip control register is

programmed. Table 9 shows the input data format for

programming this register.

The on-chip multiplexer is controlled by R1[22 ... 20] on the

ADF4153. Table 8 shows the truth table.

Digital Lock Detect

RF Counter Reset

The digital lock detect output goes high if there are 40

successive PFD cycles with an input error of less than 15 ns. It

stays high until a new channel is programmed or until the error

at the PFD input exceeds 30 ns for one or more cycles. If the

loop bandwidth is narrow compared to the PFD frequency, the

error at the PFD inputs may drop below 15 ns for 40 cycles

around a cycle slip. Therefore, the digital lock detect may go

falsely high for a short period until the error again exceeds

30 ns. In this case, the digital lock detect is reliable only as a

loss-of-lock detector.

DB3 is the RF counter reset bit for the ADF4153. When this is 1,

the RF synthesizer counters are held in reset. For normal

operation, this bit should be 0.

RF Charge Pump Three-State

This bit puts the charge pump into three-state mode when

programmed to 1. It should be set to 0 for normal operation.

RF Power-Down

DB4 on the ADF4153 provides the programmable power-down

mode. Setting this bit to 1 performs a power-down. Setting this

bit to 0 returns the synthesizer to normal operation. While in

software power-down mode, the part retains all information in

its registers. Only when supplies are removed are the register

contents lost.

Prescaler (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the INT,

FRAC, and MOD counters, determines the overall division ratio

from the RF_INto the PFD input. Operating at CML levels, it

Rev. A | Page 17 of 24

ADF4153

When a power-down is activated, the following events occur:

1. All active dc current paths are removed.

dither is enabled. This randomizes the fractional quantization

noise so that it looks more like white noise rather than spurious

noise. This means that the part is optimized for improved

spurious performance. This operation would normally be used

when the PLL closed-loop bandwidth is wide, for fast-locking

applications. (Wide-loop bandwidth is seen as a loop bandwidth

greater than 1/10 of the RF_OUTchannel step resolution (f_RES)). A

wide-loop filter does not attenuate the spurs to a level that a

narrow-loop bandwidth would. When the low noise and spur

setting is enabled, dither is disabled. This optimizes the

synthesizer to operate with improved noise performance.

However, the spurious performance is degraded in this mode

compared to the lowest spurs setting. To further improve noise

performance, the lowest noise setting option can be used, which

reduces the phase noise. As well as disabling the dither, it also

ensures that the charge pump is operating in an optimum

region for noise performance. This setting is extremely useful

where a narrow-loop filter bandwidth is available. The

synthesizer ensures extremely low noise and the filter attenuates

the spurs. The typical performance characteristics give the user

an idea of the trade-off in a typical WCDMA setup for the

different noise and spur settings.

2. The synthesizer counters are forced to their load state

conditions.

3. The charge pump is forced into three-state mode.

4. The digital lock detect circuitry is reset.

5. The RF_INinput is debiased.

6. The input register remains active and capable of loading

and latching data.

Lock Detect Precision (LDP)

When this bit is programmed to 0, three consecutive reference

cycles of 15 ns must occur before digital lock detect is set. When

this bit is programmed to 1, five consecutive reference cycles of

15 ns must occur before digital lock detect is set.

Phase Detector Polarity

DB6 in the ADF4153 sets the phase detector polarity. When the

VCO characteristics are positive, this should be set to 1. When

they are negative, it should be set to 0.

Charge Pump Current Setting

RESERVED BITS

DB7, DB8, and DB9 set the charge pump current setting. This

should be set to the charge pump current that the loop filter is

designed with (see Table 9).

These bits should be set to 0 for normal operation.

RF SYNTHESIZER: A WORKED EXAMPLE

This equation governs how the synthesizer should be

programmed.

REF_INDoubler

Setting this bit to 0 feeds the REF_INsignal directly to the 4-bit

RF R counter, disabling the doubler. Setting this bit to 1

multiplies the REF_INfrequency by a factor of 2 before feeding

into the 4-bit R counter. When the doubler is disabled, the REF_IN

falling edge is the active edge at the PFD input to the fractional

synthesizer. When the doubler is enabled, both the rising and

falling edges of REF_INbecome active edges at the PFD input.

RF_OUT

where:

=

[

INT +

(

FRAC MOD

)

]

×

[

F_PFD

]

(3)

RF_OUTis the RF frequency output.

INT is the integer division factor.

FRAC is the fractionality.

When the doubler is enabled and the lowest spur mode is

chosen, the in-band phase noise performance is sensitive to the

REF_INduty cycle. The phase noise degradation can be as much

as 5 dB for the REF_INduty cycles outside a 45% to 55% range.

The phase noise is insensitive to the REF_INduty cycle in the

lowest noise mode and in the lowest noise and spur mode. The

phase noise is insensitive to REF_INduty cycle when the doubler

is disabled.

MOD is the modulus.

F_PFD

where:

=

[

REF_IN

×

(

1 + D

)

R

]

(4)

REF_INis the reference frequency input.

D is the RF REF_INdoubler bit.

NOISE AND SPUR REGISTER, R3

With R3[1, 0] set to 1, 1, the on-chip noise and spur register is

programmed. Table 10 shows the input data format for

programming this register.

R is the RF reference division factor.

Noise and Spur Mode

Noise and spur mode allows the user to optimize a design either

for improved spurious performance or for improved phase

noise performance. When the lowest spur setting is chosen,

Rev. A | Page 18 of 24

ADF4153

Example: In a GSM 1800 system, where 1.8 GHz RF frequency

output (RF_OUT) is required, a 13 MHz reference frequency input

(REF_IN) is available and a 200 kHz channel resolution (f_RES) is

required on the RF output.

benefit. PDC requires 25 kHz channel step resolution, whereas

GSM 1800 requires 200 kHz channel step resolution. A 13 MHz

reference signal could be fed directly to the PFD. The modulus

would be programmed to 520 when in PDC mode (13 MHz/

520 = 25 kHz). The modulus would be reprogrammed to 65 for

GSM 1800 operation (13 MHz/65 = 200 kHz). It is important

that the PFD frequency remains constant (13 MHz). This allows

the user to design one loop filter that can be used in both setups

without running into stability issues. It is the ratio of the RF

frequency to the PFD frequency that affects the loop design.

Keeping this relationship constant, instead of changing the

modulus factor, results in a stable filter.

MOD = REF_INf_RES

MOD =13 MHz 200 kHz = 65

From Equation 4:

F_PFD

=

[

13 MHz ×

(

1 + 0

)

1

]

=13 MHz

(5)

(6)

1.8 G =13 MHz ×

(

INT + FRAC 65 ≥

)

INT =138; ≥ FRAC = 30

SPURIOUS OPTIMIZATION AND FASTLOCK

As mentioned earlier, the part can be optimized for spurious

performance. However, in fast locking applications, the loop

bandwidth needs to be wide, and therefore the filter does not

provide much attenuation of the spurs. The programmable

charge pump can be used to get around this issue. The filter is

designed for a narrow-loop bandwidth so that steady-state

spurious specifications are met. This is designed using the

lowest charge pump current setting. To implement fastlock

during a frequency jump, the charge pump current is set to the

maximum setting for the duration of the jump. This has the

effect of widening the loop bandwidth, which improves lock

time. When the PLL has locked to the new frequency, the charge

pump is again programmed to the lowest charge pump current

setting. This narrows the loop bandwidth to its original cutoff

frequency to allow better attenuation of the spurs than the

wide-loop bandwidth.

MODULUS

The choice of modulus (MOD) depends on the reference signal

(REF_IN) available and the channel resolution (f_RES) required at

the RF output. For example, a GSM system with 13 MHz REF_IN

would set the modulus to 65. This means that the RF output

resolution (f_RES) is the 200 kHz (13 MHz/65) necessary for GSM.

REFERENCE DOUBLER AND REFERENCE DIVIDER

The reference doubler on-chip allows the input reference signal

to be doubled. This is useful for increasing the PFD comparison

frequency. Making the PFD frequency higher improves the

noise performance of the system. Doubling the PFD frequency

usually results in an improvement in noise performance of 3 dB.

It is important to note that the PFD cannot be operated above

32 MHz due to a limitation in the speed of the Σ-Δ circuit of

the N divider.

PHASE RESYNC AND SPUR CONSISTENCY

12-BIT PROGRAMMABLE MODULUS

Setting the RESYNC bits [S4 ,S3, S2, and S1] enables the phase

RESYNC feature. With a fractional denominator of MOD, a

fractional-N PLL can settle with any one of (2 × π)/MOD valid

phase offsets with respect to the reference input. This is

different from integer-N where the RF output always settles to

the same static phase offset with respect to the input reference,

which is zero ideally. This is not an issue in applications that

require only a consistent frequency lock. When RESYNC is

enabled, it also ensures that spur levels remain consistent when

the PLL returns to a certain frequency. This is due to the fact

that the RESYNC function resets the Σ-Δ modulator. RESYNC

is enabled by setting the S4 to S1 bits in R2 to a nonzero value.

When the S4 to S1 bits are 0, 0, 0, and 0, RESYNC is disabled.

Unlike most other fractional-N PLLs, the ADF4153 allows the

user to program the modulus over a 12-bit range. This means

that the user can set up the part in many different

configurations for the application, when combined with the

reference doubler and the 4-bit R counter.

For example, here is an application that requires 1.75 GHz RF

and 200 kHz channel step resolution. The system has a 13 MHz

reference signal.

One possible setup is feeding the 13 MHz directly to the PFD

and programming the modulus to divide by 65. This would

result in the required 200 kHz resolution.

For applications where a consistent phase relationship between

the output and reference is required (i.e., digital beam forming),

the ADF4153 can be used with the phase resync feature enabled.

This ensures that if the user programs the PLL to jump from

Frequency (and Phase) A to Frequency (and Phase) B and back

again to Frequency A, the PLL returns to the original phase

(Phase A).

Another possible setup is using the reference doubler to create

26 MHz from the 13 MHz input signal. This 26 MHz is then fed

into the PFD. The modulus is now programmed to divide by

130. This also results in 200 kHz resolution and offers superior

phase noise performance over the previous setup.

The programmable modulus is also very useful for multi-

standard applications. If a dual-mode phone requires PDC and

GSM 1800 standards, the programmable modulus is a huge

Rev. A | Page 19 of 24

ADF4153

When enabled, it activates every time the user programs

Register R0 to set a new output frequency. However, if a cycle

slip occurs in the settling transient after the phase RESYNC

operation, the phase RESYNC is lost. This can be avoided by

delaying the RESYNC activation until the locking transient is

close to its final frequency. This is done by rewriting to R1 after

R1 has been set up as normal. Setting load control [DB23]

allows this. When set, instead of determining the fractional

denominator, the MOD bits [M12 to M1] are used to set a time

interval from when the new channel is programmed to the time

the RESYNC is activated. This is called the delay. Its value

should be programmed to set a time interval that is at least as

long as the RF PLL lock time.

INTERFACING

The ADF4153 has a simple SPI® compatible serial interface for

writing to the device. SCLK, SDATA, and LE control the data

transfer. When LE (latch enable) is high, the 22 bits that have

been clocked into the input register on each rising edge of

SCLK are transferred to the appropriate latch. See Figure 2 for

the timing diagram and Table 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

909 kHz or one update every 1.1 µs. This is more than adequate

for systems that have typical lock times in the hundreds of

microseconds.

ADuC812 Interface

For example, if REF_IN= 26 MHz and MOD = 130 to give

200 kHz output steps (f_RES), and the RF loop has a settling

time of 150 µs, then delay should be programmed to 3,900,

as 26 MHz × 150 µs = 3,900.

Figure 21 shows the interface between the ADF4153 and the

ADuC812 MicroConverter®. Since the ADuC812 is based on an

8051 core, this interface can be used with any 8051-based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4153 needs a

24-bit word, which is accomplished by writing three 8-bit bytes

from the MicroConverter to the device. After the third byte is

written, the LE input should be brought high to complete the

transfer.

If the application requires the delay to be greater than 4095, the

RESYNC bits should be increased. For example, if the lock time

above is 1.5 ms, the delay should be programmed to 26 MHz ×

1.5 ms = 39,000. In this case, program M12 to M1 to 3,900 and

program S4 to S1 to 10. The delay is 3,900 × 10 = 39,000.

SPURIOUS SIGNALS—PREDICTING WHERE THEY

WILL APPEAR

When operating in the mode described, the maximum

SCLOCK rate of the ADuC812 is 4 MHz. This means that the

maximum rate at which the output frequency can be changed is

180 kHz.

Just as in integer-N PLLs, spurs appear at PFD frequency offsets

from the carrier. In a fractional-N PLL, spurs also appear at

frequencies equal to the RF_OUTchannel step resolution (f_RES).

The third-order fractional interpolator engine of the ADF4153

may also introduce subfractional spurs. If the fractional

denominator (MOD) is divisible by 2, spurs appear at 1/2 f_RES.If

the fractional denominator (MOD) is divisible by 3, spurs

appear at 1/3 f_RES.Harmonics of all spurs mentioned will also

appear. With the lowest spur mode enabled, the fractional and

subfractional spurs is attenuated dramatically. The worst-case

spurs appear when the fraction is programmed to (1/MOD).

For example, in a GSM 900 MHz system with a 26 MHz PFD

frequency and an RF_OUTchannel step resolution (f_RES) of 200

kHz, the MOD = 130. PFD spurs appear at 26 MHz offset, and

fractional spurs appear at 200 kHz offset. Since MOD is

divisible by 2, subfractional spurs are also present at 100 kHz

offset.

ADuC812

ADF4153

SCLOCK

SCLK

MOSI

SDATA

LE

I/O PORTS

MUXOUT

(LOCK DETECT)

Figure 21. ADuC812 to ADF4153 Interface

FILTER DESIGN—ADISIMPLL

A filter design and analysis program is available to help the user

to implement PLL design. Visit www.analog.com/pll for a free

download of the ADIsimPLL software. The software designs,

simulates, and analyzes the entire PLL frequency domain and

time domain response. Various passive and active filter

architectures are allowed. REV. #2 of ADIsimPLL allows analysis

of the ADF4153.

Rev. A | Page 20 of 24

ADF4153

ADSP-2181 Interface

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

Figure 22 shows the interface between the ADF4153 and the

ADSP-21xx digital signal processor. As discussed previously, the

ADF4153 needs a 24-bit serial word for each latch write. The

easiest way to accomplish this using the ADSP-21xx family is to

use the autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block

of serial data before an interrupt is generated. Set up the word

length for eight bits and use three memory locations for each

24-bit word. To program each 24-bit latch, store the three 8-bit

bytes, enable the autobuffered mode, and write to the transmit

register of the DSP. This last operation initiates the autobuffer

transfer.

The lands on the chip scale package (CP-20) are rectangular.

The printed circuit board pad for these should be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. The land should be centered on the pad.

This ensures that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be a clearance of at least 0.25 mm between the thermal

pad and the inner edges of the pad pattern. This ensures that

shorting is avoided.

Thermal vias may be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias are

used, they should be incorporated in the thermal pad at 1.2 mm

pitch grid. The via diameter should be between 0.3 mm and

0.33 mm, and the via barrel should be plated with 1 oz. copper

to plug the via.

ADSP-21xx

ADF4153

SCLK

SCLOCK

SDATA

LE

DT

TFS

The user should connect the printed circuit board thermal pad

to AGND.

MUXOUT

(LOCK DETECT)

I/O FLAGS

Figure 22. ADSP-21xx to ADF4153 Interface

Rev. A | Page 21 of 24

ADF4153

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20 MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153AB

Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.60

MAX

4.0

BSC SQ

0.60

MAX

16

15

20

1

PIN 1

INDICATOR

2.25

2.10 SQ

1.95

3.75

BSC SQ

TOP

VIEW

BOTTOM

VIEW

11

10

5

0.75

0.55

0.35

6

0.25 MIN

0.80 MAX

0.65 TYP

0.30

0.23

0.18

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

0.20

REF

COPLANARITY

0.08

SEATING

PLANE

0.50

BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

Figure 24. 20-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body

(CP-20)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADF4153BRU

ADF4153BRU-REEL

ADF4153BRU-REEL7

ADF4153BCP

ADF4153BCP-REEL

ADF4153BCP-REEL7

EVAL-ADF4153EB1

Description

Temperature Range

−40°C to +85°C

Package Option

RU-16

CP-20

Thin Shrink Small Outline Package (TSSOP)

Lead Frame Chip Scale Package (LFCSP)

Evaluation Board

CP-20

Rev. A | Page 22 of 24

ADF4153

NOTES

Rev. A | Page 23 of 24

ADF4153

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

©

registered trademarks are the property of their respective owners.

C03685–0–1/04(A)

Rev. A | Page 24 of 24


型号：	ADF4153
厂家：	ADI
描述：	Fractional-N Frequency Synthesizer 小数N分频合成器
文件：	总24页 (文件大小：257K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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