ADF4211BRCHIPS_技术文档

a

PreliminaryTechnicalData

DualFrequencySynthesizer

ADF4210/ADF4211/ADF4212/ADF4213

G E NE R AL D E S C R IP T IO N

FEATURES

T he AD F4210/AD F4211/AD F4212/AD F4213 is a

dual frequency synthesizer which can be used to

implement local oscillators in the up-conversion and

down-conversion sections of wireless receivers and

transmitters. T hey can provide the LO for both the

RF and IF sections. T hey consist of a low-noise digi-

tal PFD (Phase Frequency Detector), a precision

charge pump, a programmable reference divider,

programmable A and B counters and a dual-modulus

prescaler (P/P+1). T he A (6-bit) and B (12-bit)

counters, in conjunction with the dual modulus

prescaler (P/P+1), implement an N divider (N=

BP+A). In addition, the 15-bit reference counter (R

Counter), allows selectable REFIN frequencies at the

PFD input. A complete PLL (Phase-Locked Loop)

can be implemented if the synthesizers are used with

an external loop filter and VCO's (Voltage Controlled

Oscillators)Control of all the on-chip registers is via

a simple 3-wire interface. T he devices operate with a

3V ( ± 10%) or 5V( ± 10%) power supply and can be

powered down when not in use.

ADF4210:

ADF4211:

ADF4212:

ADF4213:

550MHz/ 1.2GHz

550MHz/ 2.0GHz

550MHz/ 3.0GHz

1.0GHz/ 2.5GHz

+2.7 V to +5.5 V Pow er Supply

Program m able Dual Modulus Prescaler

Program m able Charge Pum p Currents

3-Wire Serial Interface

Digital Lock Detect

Pow er Dow n Mode

APPLICATIONS

Portable Wireless Com m unications (PCS/ PCN,

Cordless)

phone System s

w orks (WLANs)

Cordless and Cellular Tele-

Wireless Local Area Net-

FUNCTIO NAL BLO CK D IAGRAM

V

1

V

2

V

1

V 2

R_{S ET}

CC

P

AD F 4210/AD F 4211/

AD F 4212/AD F 4213

ADF4210/ADF4211/ADF4212

SWALLOW

CO NTROL

15 -BIT IF

IF_IN

+

-

IF

N-COUNTER

PRESCALER

CHARGE

PUMP

CP

IF

15-BI IF

R-COUNTER

PH ASE

C OM PAR ATOR

IF

LOCK

DETECT

OS CILLATOR

REF_IN

OUTPUT

M UX

MUXOUT

FAST

CH ARGE

CLOCK

DATA

LE

24-BIT

DAT A

PUMP

REGISTER

FL_O

RF

LOCK

DE TECT

18 -BIT RF

N-COUNTE R

+

RF

RF_IN

PRESCALER

-

CHARGE

PUMP

CP

RF

15-BIT RF

R-COUNTER

PH ASE

C OM PAR ATOR

SWALLOW

CONTRO L

REV.PrD 07/99

DGND

AGND

DGND

AGND

IF

RF

IF

Inform ation furnished by Analog Devices is believed to be accurate and reliable. However,

no responsibility is assum ed by Analog Devices for its use, nor for any infringem ents of

patents or other rights of third parties which m ay result from its use. No license is granted

by im plication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 781-329-4700 Fax: 781-326-8703

(V = +3 V ± 10%, +5 V ± 10%; V = V +5 V ± 10%;

DD

P

DD,

1

GND = 0 V; R = 4.7kΩ; T = T_MINto T_MAXunless otherwise

SET

A

ADF4210/11/12/13 – SPECIFICATIONS

noted)

P ar am eter

B Version

BChips

Units

Test Conditions/Com m ents

RF C H ARAC T ERIST IC S

RF Input Frequency (RF_INA, RF_INB)

AD F 4210

25/550

0.1/1.2

0.1/3.0

0.1/2.5

25/550

0.1/1.2

0.1/3.0

0.1/2.5

M H z min/max

G H z min/max

AD F 4211

AD F 4212

AD F 4213

IF Input Frequency (IF_INA, IF_INB)

AD F 4210

AD F 4211

AD F 4212

AD F 4213

25/550

0.1/1.0

25/550

0.1/1.0

M H z min/max

G H z min/max

Reference Input Frequency

Phase Detector Frequency

RF Input Sensitivity

5/40

10

-15/0

-10/0

-5

5/40

10

-15/0

-10/0

-5

M H z min/max

M H z max

dBm min/max 3V Power Supply

dBm min/max 5V Power Supply

dBm min

Reference Input Sensitivity

C H ARG E PU M P

I_{C P}sink/source

H igh Value

Low Value

I_{C P}T hree State Current

Sink and Source Current Matching

I_{C P}vs. V_{C P}

5

625

1

2

5

625

1

2

mA typ

µA typ

nA max

% typ

See T able 11

0.5V < V_{C P}< V_P- 0.5

V_{C P}= V_P/2

I_{C P}vs. T emperature

2

LO G IC IN PU T S

V_INH, Input High Voltage

0.8*V_{D D}

0.2*V_{D D}

± 1

10

± 100

0.8*V_{D D}

0.2*V_{D D}

± 1

10

± 100

V min

V max

µA max

pF max

µA max

V

I

C

_INL, Input Low Voltage

_INH/I_INL, Input Current

_IN, Input Capacitance

Oscillator Input Current

LO G IC O U T P U T S

V_OH, Output High Voltage

V_OL, Output Low Voltage

V_CC- 0.4

0.4

V_CC- 0.4

0.4

V min

V max

I_OH= 1mA

I_OL= 1mA

PO WER SU PPLIES

AV_DD

DV_DD

2.7/5.5

AV_DD

AV_{D D}/5.5

2.7/5.5

AV_DD

AV_{D D}/5.5

V min/V max

V_P1,V_P2

I_DD

(RF + IF)

AD F 4210

AD F 4211

AD F 4212

AD F 4213

RF Only

3.0

4.0

5.0

3.0

4.0

5.0

mA max

AD F 4210

AD F 4211

AD F 4212

AD F 4213

IF Only

2.0

3.0

4.0

2.0

3.0

4.0

mA max

AD F 4213

Low Power Sleep Mode

1.0

1

1.0

1

mA max

µA typ

REV.PrD 07/99

–2–

Preliminary TechnicalData

ADF4210/ADF4211/ADF4212/ADF4213

P ar am eter

B Version

BChips

Units

Test Conditions/Com m ents

N O ISE C H ARAC T ERIST IC S

Phase N oise Floor

-173

-165

-173

-165

dBc/H z typ

@ 25kH z PFD Frequency

@ 200kH z PFD Frequency

@ VCO Output

Phase Noise Performance²

AD F 4210³

-96

-92

-82

-85

-66

-85

-96

-92

-82

-85

-66

-85

dBc/H z typ

AD F 4211⁴

AD F 4211⁵

AD F 4212⁶

AD F 4212⁷

AD F 4213⁷

AD F 4213⁸

Spurious Signals

Measured at offset of f_PFD/2f_PFD

AD F 4210³

tbd/tbd

dB typ

AD F 4211⁴

AD F 4211⁵

AD F 4212⁶

AD F 4212⁷

AD F 4212⁸

AD F 4213⁸

NOTES

1

2

Operatingtemperaturerangeisasfollows:BVersion: –40°C to +85°C.

ThephasenoiseismeasuredwiththeEVAL-ADF421XEBEvaluationBoardandtheHP8562ESpectrumAnalyzer. ThespectrumanalyzerprovidestheREFIN forthesynthesizer.(f_REFOUT=10MHz@

0dBm)

3.

4.

5.

6.

7.

8.

f _REFIN= 10MHz; f_PFD= 200kHz; Offsetfrequency= 1kHz; f_RF= 540MHz; N = 2700; Loop B/W= 20kHz

f

_REFIN= 10MHz; f_PFD= 200kHz; Offsetfrequency= 1kHz; f_RF= 900MHz; N = 4500; Loop B/W= 12kHz

_REFIN= 10MHz; f_PFD= 30kHz; Offsetfrequency= 1kHz; f_RF= 836MHz; N = 27867; Loop B/W= 3kHz

_REFIN= 10MHz; f_PFD= 200kHz; Offsetfrequency= 1kHz; f_RF= 1880MHz; N = 9400; LoopB/W= 20kHz

f _REFIN= 10MHz; f_PFD= 10kHz; Offsetfrequency= 250Hz; f_RF= 1880MHz; N = 188000; LoopB/W= 1kHz

_REFIN= 10MHz; f_PFD= 200kHz; Offsetfrequency= 1kHz; f_RF= 1960MHz; N = 9800; LoopB/W= 20kHz

f

Specificationssubjecttochangewithoutnotice.

C H IP LAYO U T

REV.PrD 07/99

–3 –

Preliminary TechnicalData

TIMINGCHARACTERISTICS

ADF4210/ADF4211/ADF4212/ADF4213

(V = +5 V 10%, +3 V ± 10%; GND = 0 V, unless otherwise noted)

Lim it at

DD

T_MINto T_MAX

P aram eter

(B Version)

Units

Test Conditions/Com m ents

t₁

t₂

t₃

t₄

t₅

t₆

50

10

50

ns min

DAT A to CLOCK Set Up T ime

DAT A to CLOCK Hold T ime

CLOCK High Duration

CLOCK Low Duration

CLOCK to LE Set Up T ime

LE Pulse Width

NOT E

Guaranteed by Design but not Production T ested.

t₃

t₄

CLOCK

t₁

t₂

DB23

DATA

DB22

DB2

DB1

DB0 (LSB)

(CONTROL BIT C1)

(MSB)

(CONTROL BIT C2)

t₆

LE

t₅

Figure 1. Tim ing Diagram

Lead T emperature, Soldering

2

ABSO LUT E MAXIMUM RAT INGS^1,

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

(

T_A= +25°C unless otherwise noted)

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V

V_Pto GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V

V_Pto V_DD^{. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .}.–0.3 V to +3.5 V

Digital I/O Voltage to GND . . . . . . . . –0.3 V to V_DD+ 0.3 V

Analog I/O Voltage to GND . . . . . . . . –0.3 V to V_P+ 0.3 V

Operating T emperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C

Storage T emperature Range . . . . . . . . . . . –65°C to +150°C

Maximum Junction T emperature . . . . . . . . . . . . . . . +150°C

T SSOP θ_JAT hermal Impedance . . . . . . . . . . . . . T BD °C/W

1. Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T his is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2. T his device is a high-performance RF integrated circuit with an ESD rating of

< 2kV and it is ESD sensitive. Proper precautions should be taken for handling

and assembly.

C A U T I O N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although this device features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

O R D E R ING G U ID E

Model

Tem perature Range P ackage O ption*

AD F 4210BRU

–40°C to +85°C

RU -16

AD F 4210BC H IP S –40°C to +85°C

AD F 4211BRU –40°C to +85°C

AD F 4211BRC H IP S –40°C to +85°C

AD F 4212BRU –40°C to +85°C

AD F 4212BC H IP S –40°C to +85°C

AD F 4213BRU –40°C to +85°C

AD F 4213BRC H IP S –40°C to +85°C

REV.PrD 07/99

*RU = T hin Shrink Small Outline Package (T SSOP).

–4 –

Preliminary TechnicalData

ADF4210/ADF4211/ADF4212/ADF4213

T YP IC AL P E RF O RM ANC E C H ARAC T E RIST IC S

Figure 2. ADF4210 Phase Noise

Figure 3. ADF4210 Reference Spurs

Figure 4. ADF4211 Phase Noise (GSM902)

Figure 5. ADF4211 Reference Spurs (GSM902)

Figure 6. ADF4211 Phase Noise (CDMA836)

Figure 7. ADF4211 Reference Spurs (CDMA836)

REV.PrD 07/99

–5 –

Preliminary TechnicalData

ADF4210/ADF4211/ADF4212/ADF4213

T YP IC AL P E RF O RM ANC E C H ARAC T E RIST IC S (con tin -

u ed )

Figure 8. ADF4212 Phase Noise (GSM1880)

Figure 9. ADF4212 Reference Spurs (GSM1880)

Figure 10. ADF4212 Phase Noise (CDMA1880)

Figure 11. ADF4212 Reference Spurs (CDMA1880)

Figure 12. ADF4212 Phase Noise (WCDMA1960)

Figure 13. ADF4212 Reference Spurs (WCDMA1960)

REV.PrD 07/99

–6 –

Preliminary TechnicalData

ADF4210/ADF4211/ADF4212/ADF4213

T YP IC AL P E RF O RM ANC E C H ARAC T E RIST IC S (con tin -

u ed )

Figure 14. ADF4210 Phase Noise Floor vs PFD Fre-

quency

Figure 15. ADF4211 Phase Noise Floor vs PFD Fre-

quency

Figure 16. ADF4212 Phase Noise Floor vs PFD Fre-

quency

Figure 17.ADF4213 Phase Noise Floor vs PFD Fre-

quency

Figure 18.

Figure 19.

REV.PrD 07/99

–7 –

Preliminary TechnicalData

ADF4210/ADF4211/ADF4212/ADF4213

P IN D E S C R IP T IO N

Mnem onic

Function

Vcc1

Positive power supply for the RF section. A 0.1uF capacitor should be connected between this pin and

GND. Vcc1 has a value +5V 10% or 3V 10%. Vcc1 must have the same potential as Vcc2.

Vp1

RF Charge Pump Power Supply. T his should be greater than or equal to V_cc1.

CP_RF

RF Charge Pump Output. T his is normally connected to a loop filter which drives the input to an ex-

ternal VC O.

D G N D _RF

RF_IN

Digital Ground for the RF digital circuitry.

Input to the RF Prescaler. T his small signal input is normally taken from the VCO.

Analog Ground for the RF analog circuitry.

AG N D _RF

F L_o

Multiplexed output of RF/IF programmable or reference dividers, RF/IF fastlock mode. CMOS output.

REF _IN

Reference Input. T his is a CMOS input with a nominal threshold of V_DD/2 and an equivalent input

resistance of 100kΩ. T his input can be driven from a T T L or CMOS crystal oscillator.

D G N D _IF

Digital Ground for the IF digital,interface and control circuitry

M U X O U T

T his multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled

Reference Frequency to be accessed externally.

C L K

Serial Clock Input. T his serial clock is used to clock in the serial data to the registers. T he data is

latched into the 22-bit shift register on the CLK rising edge. T his input is a high impedance CMOS

input.

D AT A

L E

Serial Data Input. T he serial data is loaded MSB first with the two LSBs being the control bits. T his

input is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into

one of the four latches, the latch being selected using the control bits.

R_SET

Connecting a resistor to this pin sets the maximum charge pump output current. With R_SET= 4.7kΩ,

I_CPmax= 5mA.

AG N D _IF

IF_IN

Analog Ground for the IF analog circuitry.

Input to the RF Prescaler. T his small signal input is normally taken from the VCO.

Digital Ground for the IF digital,interface and control circuitry

D G N D _IF

C P_IF

IF Charge Pump Output. T his is normally connected to a loop filter which drives the input to an exter-

nal VC O.

Vp2

IF Charge Pump Power Supply. T his should be greater than or equal to V_cc2.

Vcc2

Positive power supply for the IF section. A 0.1uF capacitor should be connected between this pin and

GND. Vcc1 has a value +5V ±10% or 3V ±10%. Vcc1 must have the same potential as Vcc1.

P IN C O NF IG U R AT IO N

V_CC

1

V_CC

V_P2

2

V_P1

CP_RF

CP_IF

DGND_RF

RF_IN

DGND_IF

IF_IN

ADF4210

ADF4211

ADF4212

ADF4213

AGND_IF

AGND_RF

R

FL

O

SET

REF_IN

LE

DGND_IF

DATA

CLK

MUXOUT

REV.PrD 07/99

–8 –

Preliminary TechnicalData

ADF4210/ADF4211/ADF4212/ADF4213

C IR C U IT D E S C R IP T IO N

INP UT SH IFT RE GISTE R

P RO G RAM M AB LE RE F E RE NC E (R) C O UNT E R

If control bits C2, C1 are 0,0 then the data is transferred

from the input shift register to the 14 Bit IFR counter. If

the control bits 1,0 then the data is transferred to the 14 Bit

RFR counter T ables 2a and 2b shows the input shift regis-

ter data format for the IF and RF R conters and T able 3

shows the divide ratios possible.

T he functional block diagram for the ADF4210 family is

shown on page 1. T he main blocks include a 22-bit input

shift register, two 15-bit R counters and two N counters

(15 bit resloution for the IF and 18 bit resolution for the

RF). Data is clocked into the 24-bit shift register on each

rising edge of CLK. T he data is clocked in MSB first.

Data is transferred from the shift register to one of four

latches on the rising edge of LE. T he destination latch is

determined by the state of the two control bits (C2, C1) in

the shift register. T hese are the two lsb's DB1, DB0 as

shown in the timing diagram of Figure 1. T he truth table

for these bits is shown in T able 1.

Table 1. C2, C1 Tr uth Table

C on tr ol Bits

C 2

C 1

D a ta La tch

0

1

0

1

0

1

IF R Counter

IF N Counter (A and B)

RF R Counter

RF N Counter

Table 2a. IF R Counter

IF CP Current

Setting

14-Bit Reference Counter

Control

Bits

IF F

O

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

R7

DB7

R6

DB6

R5

DB5

R4

DB4

R3

DB3

R2

DB2

R1

DB1

DB0

IF CPI 2 IF CPI 1 IF CPI 0

P4

P3

P2

P1

R14

R13 R12

R11

R10

R9

R8

C2(0) C1(0)

Table 2b. RF R Counter

RF CP

Cu rrent

Setting

14-Bit Reference Counter

Control

Bits

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

R7

DB7

R6

DB6

R5

DB5

R4

DB4

R3

DB3

R2

DB2

R1

DB1

DB0

RF CPI 2 RF CPI 1 RF CPI 0

P12

P11

P10

R15

P9

R14

R13 R12

R11

R10

R9

R8

C2(1) C1(0)

Table 3.

IF/RF R Counter D ivide Ratios

D ivide Ratio

R14 R13 R12 R11 R10

R9

0

*

R8 R7

R6

0

*

R5

0

*

R4

R3

R2

R1

1

0

1

2

*

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

1

*

1

*

1

*

0

1

16382

16383

1

NOTES

1. Divideratio: 1to16383

REV.PrD 07/99

–9 –

Preliminary TechnicalData

ADF4210/ADF4211/ADF4212/ADF4213

P RO G RAM M AB LE N C O U NT E R

P u lse Swallow F u n ction

If control bits C2, C1 are 0, 1 then the data in the input

register is used to program the IFN (A + B) counter. If

the control bits 1,1 then the data is transferred to the RFN

counter. T he N counter consists of a 6-bit swallow counter

(A counter) and 12-bit programmable counter (B counter).

T able 4 shows the input register data format for program-

ming the N counters. T able 5 and 6 show the truth table

for the RF and IF A counters. T able 7 is the truth table

for the RF/IF B counter.

T he A and B counters, in conjunction with the dual modu-

lus prescaler make it possible to generate output frequen-

cies which are spaced only by the Reference Frequency

divided by R . T he equation for the VCO frequency is as

follows:

f_VCO= [(P x B) + A] x f_REFIN/R

f_VCO

:

Ouput Frequency of external voltage controlled

oscillator (VC O).

P :

B:

A:

Preset modulus of dual modulus prescaler.

Preset Divide Ratio of binary 12-bit counter (3

Preset Divide Ratio of binary 6-bit swallow

counter.

f_REFIN: Ouput frequency of the external reference

frequency oscillator.

R :

Preset divide ratio of binary 14-bit

programmable reference counter (3 to 16383).

Table 4a. IF N Counter

Control

Bits

6-Bit A Counter

12-Bit B Counter

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2

DB8

B1

DB7

A6

DB6

A5

DB5

A4

DB4

A3

DB3

A2

DB2

A1

DB1

DB0

C2(0) C1(1)

P8

P7

B12

Table 4b. RF N Counter

Control

Bits

6-Bit A Counter

12-Bit B Counter

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

P14 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2

DB8

B1

DB7

A6

DB6

A5

DB5

A4

DB4

A3

DB3

A2

DB2

A1

DB1

DB0

C2(1) C1(1)

P16

B12

P15

Table 6. IF Swallow Counter (A Counter )

Table 5. RF Swallow Counter (A Counter )

Divide Ratio

A6 A5 A4 A3

A2 A1

A6 A5 A4 A3 A2 A1

0

1

*

X

*

X

*

0

*

0

*

0

*

1

0

1

*

1

0

1

*

0

*

0

*

0

*

0

*

0

*

0

1

*

15

X

1

127

1

NOTES

1. Divideratio: 0to127.

2.BisgreaterthanorequaltoA

NOTES

1. Divideratio: 0to15

2.BisgreaterthanorequaltoA

3.Xequalsdontcarecondition.

Table 7. B Counter D ivide Ratio

D ivide Ratio

N17 N16 N15 N14 N13 N12 N11 N10 N9

N8

0

1

*

N7

1

0

*

N6

1

0

*

3

4

*

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

*

4095

1

NOTES

1.Divide ratios less than 3 are prohibited.

2.Divide ratio: 3 to 4095.

3.B is must be greater than or equal to A.

REV.PrD 07/99

–1 0 –

Preliminary TechnicalData

ADF4210/ADF4211/ADF4212/ADF4213

M U XO U T C on t r ol

IF P ower D own

T he on-chip multiplexer is controlled by P12, P11, P4,

P3 on the ADF4210 Family.

If P8 has been set to a "1" and P2 has been set to “0”

(normal operation), then a synchronous power down is

conducted in the IF section. T he device will automati-

cally put the IF charge pump into 3-state and then com-

plete the IF power down. See table 8.

Table 9. MUXO UT Control

If P8 has been set to a "1" and P2 has been set to “1”

(normal operation), then an asynchronous power down is

conducted in the IF section. T he IF stage of the device

will go into powerdown on the rising edge of LE which

latches the "1" to the IF powerdown bit. See table 8.

P12 P11

P4

P3

Muxout

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Logic low state

IF Analog Lock Detect

IF Reference Divider Output

IF N Divider Output

RF Analog Lock Detect

RF/IF Analog Lock Detect

IF Digital Lock Detect

Logic high state

RF Reference Divider

RF N Divider

3-State Output

IF Counter Reset

RF Digital Lock Detect

RF/IF Digital Lock Detect

RF Counter Reset

Activation of either synchronous or asynchronous

powerdown forces the IF loop's R and N dividers to their

load state conditions and the IF_INsection is debiased to a

high impedance state

T he REF oscillator circuit is only disabled if both the IF

and RF Powerdowns are set.

T he IF section of the devicewill return to normal pow-

ered-up operation immediately on LE latching a "0" to the

IF powerdown bit (P8). See table 8.

IF and RF Counter Reset

RF P ower D own

If P16 has been set to a "1" and P10 has been set to “0”

(normal operation), then a synchronous power down is

conducted in the RF section. T he device will automati-

cally put the RF charge pump into 3-state and then com-

plete the RF power down. See table 8.

IF P h ase D etector P olar ity

P1 sets the IF Phase Detector Polarity. When the IF VCO

characteristics are positive this should be set to “1”.

When they are negative it should be set to “0”.

If P16 has been set to a "1" and P10 has been set to “1”

(normal operation), then an asynchronous power down is

conducted in the RF section. T he RF stage of the device

will go into powerdown on the rising edge of LE which

latches the "1" to the RF powerdown bit. See table 8.

RF P h ase D etector P olar ity

P9 sets the IF Phase Detector Polarity. When the RF

VCO characteristics are positive this should be set to “1”.

When they are negative it should be set to “0”.

Activation of either synchronous or asynchronous

powerdown forces the RF loop's R and N dividers to their

load state conditions and the RF_INsection is debiased to a

high impedance state

IF C har ge P um p 3-State

P2 puts the IF charge pump into 3-state mode when pro-

grammed to a “1”. It should be set to “0” for normal

operation.

T he REF oscillator circuit is only disabled if both the IF

and RF Powerdowns are set.

T he RF section of the devicewill return to normal pow-

ered-up operation immediately on LE latching a "0" to the

RF powerdown bit (P16). See table 8.

RF C har ge P um p 3-State

P10 puts the RF charge pump into 3-state mode when

programmed to a “1”. It should be set to “0” for normal

operation.

IF P r escaler Value

Table 8. P ower-D own Modes

P7 and P6 in the IF A,B Counter Latch set the IF

prescaler values. See T able 10.

P 10

P 2

P 16

P 8

RF Mode

IF Mode

RF P r escaler Value

P15 and P14 in the RF A,B Counter Latch set the RF

prescaler values. See T able 10.

NOTES

1. The prescaler value should be chosen so that the

prescaler output frequency is always less than or

equal to 125MHz. Thus, with an RF frequency of

2GHz, a prescaler value of 16/17 is valid but a value

of 8/9 is not valid.

X

0

1

0

1

Normal Operation

Synchronous Power-Down

Asynchronous Power-Down

REV.PrD 07/99

–1 1 –

Preliminary TechnicalData

ADF4210/ADF4211/ADF4212/ADF4213

maximum value. Also an extra loop filter damping

resistor to ground is switched in using the FL_Opin.

thus compensating for the change in loop characteris-

tics while in Fastlock. Since the RF CP Gain bit is

contained in the RF N Counter, only one write is

needed to both program a new output frequency and

also initiate Fastlock. T o come out of fastlock, the

RF CP Gain bit on the RF N register must be set to

"0".

Table 10. P r escaler Values

P15

P7

0

1

P14

P6

0

Prescaler Value¹

8/9

1

0

1

16/17

32/33

64/65

1

IF C h ar ge P u m p C u r r en ts

IFCP2, IFCP1, IFCP0 program Current Setting for the

IF charge pump. See T able 11.

RF C har ge P um p C ur r ents

RFCP2, RFCP1, RFCP0 program Current Setting for the

RF charge pump. See T able 11.

Table 11. Char ge P um p Cur r ents

RFCP2 RFCP1 RFCP0

IFCP2 IFCP1 IFCP0 Output

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.625 mA

1.25 mA

1.875 mA

2.5 mA

3.125 mA

3.75 mA

4.375 mA

5.0 mA

D evice P r ogr am m in g After In itial P ower - Up.

After initially powering up the device, there are three ways

to program the device.

IF F astlock

T he IF CP Gain bit of the IF N register in the

ADF4210 family is the Fastlock Enable Bit. Only

when this is “1” is IF Fastlock enabled. When

Fastlock is enabled, the IF CP current is set to it's

maximum value. Also an extra loop filter damping

resistor to ground is switched in using the FL_Opin.

thus compensating for the change in loop characteris-

tics while in Fastlock. Since the IF CP Gain bit is

contained in the IF N Counter, only one write is

needed to both program a new output frequency and

also initiate Fastlock. T o come out of fastlock, the IF

CP Gain bit on the IF N register must be set to "0".

RF F astlock

T he RF CP Gain bit of the RF N register in the

ADF4210 family is the Fastlock Enable Bit. Only

when this is “1” is RF Fastlock enabled. When

Fastlock is enabled, the RF CP current is set to it's

REV.PrD 07/99

–1 2 –


型号：	ADF4211BRCHIPS
厂家：	ADI
描述：	IC PHASE DETECTOR, 1200 MHz, UUC, DIE, PLL or Frequency Synthesis Circuit
文件：	总12页 (文件大小：87K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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