ADF4212LBCP-REEL [ADI]

IC PLL FREQUENCY SYNTHESIZER, 2400 MHz, QCC20, 4 X 4 MM, MO-220VGGD-1, LFCSP-20, PLL or Frequency Synthesis Circuit;
ADF4212LBCP-REEL
型号: ADF4212LBCP-REEL
厂家: ADI    ADI
描述:

IC PLL FREQUENCY SYNTHESIZER, 2400 MHz, QCC20, 4 X 4 MM, MO-220VGGD-1, LFCSP-20, PLL or Frequency Synthesis Circuit

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Dual Low Power PLL  
Frequency Synthesizer  
ADF4212L  
FEATURES  
GENERAL DESCRIPTION  
IDD Total, 7.5 mA  
The ADF4212L is a dual frequency synthesizer that can be used  
to implement local oscillators (LO) in the up-conversion and  
down-conversion sections of wireless receivers and transmitters.  
It can provide the LO for both the RF and IF sections. It con-  
sists of a low noise digital PFD (Phase Frequency Detector), a  
precision charge pump, a programmable reference divider,  
programmable A and B counters, and a dual modulus prescaler  
(P/P + 1). The A (6-bit) and B (12-bit) counters, in conjunction  
with the dual modulus prescaler (P/P + 1), implement an N  
divider (N = BP + A). In addition, the 14-bit reference counter  
(R counter) allows selectable REFIN frequencies at the PFD  
input. A complete PLL (Phase-Locked Loop) can be implemented  
if the synthesizer is used with external loop filters and VCOs  
(Voltage Controlled Oscillators).  
Bandwidth RF/IF, 2.4 GHz/1.0 GHz  
2.7 V to 3.3 V Power Supply  
Separate VP Allows Extended Tuning Voltage  
Programmable Dual Modulus Prescaler  
RF and IF: 8/9, 16/17, 32/33, 64/65  
Programmable Charge Pump Currents  
3-Wire Serial Interface  
Analog and Digital Lock Detect  
Fastlock Mode  
Power-Down Mode  
20-Lead TSSOP and 20-Lead MLF Chip Scale Package  
APPLICATIONS  
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)  
Base Stations for Wireless Radio (GSM, PCS, DCS,  
CDMA, WCDMA)  
Wireless LANS  
Cable TV Tuners (CATV)  
Control of all the on-chip registers is via a simple 3-wire inter-  
face with 1.8 V compatibility. The devices operate with a power  
supply ranging from 2.7 V to 3.3 V and can be powered down  
when not in use.  
Communications Test Equipment  
FUNCTIONAL BLOCK DIAGRAM  
V
1
V
2
V 1  
V 2  
P
R
SET  
DD  
DD  
P
ADF4212L  
IF PHASE  
FREQUENCY  
DETECTOR  
REFERENCE  
12-BIT IF  
B-COUNTER  
CHARGE  
PUMP  
CP  
IF  
IF  
IN  
IF  
PRESCALER  
6-BIT IF  
A-COUNTER  
IF CURRENT  
SETTING  
IF  
LOCK  
IFCP3 IFCP2 IFCP1  
DETECT  
REF  
OSCILLATOR  
IN  
14-BIT IF  
R-COUNTER  
OUTPUT  
MUX  
MUXOUT  
CLOCK  
DATA  
LE  
22-BIT  
DATA  
REGISTER  
SDOUT  
RFCP3 RFCP2 RFCP1  
REFERENCE  
RF  
14-BIT RF  
R-COUNTER  
LOCK  
DETECT  
12-BIT RF  
B-COUNTER  
CHARGE  
PUMP  
CP  
RF  
RF  
IN  
RF  
PRESCALER  
RF PHASE  
FREQUENCY  
DETECTOR  
REFERENCE  
6-BIT RF  
A-COUNTER  
R
SET  
FL SWITCH  
FL  
O
O
DGND  
RF  
AGND  
RF  
DGND  
IF  
AGND  
IF  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  
ADF4212L–SPECIFICATIONS1  
(VDD1 = VDD2 = 2.7 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF =  
AGNDIF = DGNDIF = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 .)  
B Chips2  
Parameter  
B Version Typical  
Unit  
Test Conditions/Comments  
RF/IF CHARACTERISTICS  
RF Input Frequency (RFIN  
RF Input Sensitivity  
)
0.2/2.4  
–10/0  
100/1000  
–10/0  
0.2/2.4  
–10/0  
100/1000  
–10/0  
GHz min/max  
dBm min/max  
MHz min/max  
dBm min/max  
For Operation below FMIN, Use a Square Wave  
VDD = 3 V  
IF Input Frequency (IFIN  
)
IF Input Sensitivity  
VDD = 3 V  
MAXIMUM ALLOWABLE  
Prescaler Output Frequency3  
200  
200  
MHz max  
REFIN CHARACTERISTICS  
REFIN Input Frequency  
REFIN Input Sensitivity  
See Figure 2 for Input Circuit  
10/150  
10/150  
MHz min/max  
500 mV/VDD 500 mV/VDD V p-p min/max AC-Coupled. When DC-Coupled,  
0 to VDD Max (CMOS Compatible)  
REFIN Input Capacitance  
REFIN Input Current  
10  
100  
10  
100  
pF max  
µA max  
PHASE DETECTOR  
Phase Detector Frequency4  
75  
75  
MHz max  
CHARGE PUMP  
ICP Sink/Source  
Programmable, See Table V  
High Value  
Low Value  
5
625  
2
5
625  
2
mA typ  
µA typ  
% typ  
kmin/max  
nA max  
% typ  
With RSET = 2.7 kΩ  
Absolute Accuracy  
RSET Range  
ICP Three-State Leakage Current  
Sink and Source Current Matching  
ICP vs. VCP  
With RSET = 2.7 kΩ  
1.5/5.6  
1.5/5.6  
1
6
2
2
1
6
2
2
0.5 V < VCP < VP – 0.5 V, 2% typ  
0.5 V < VCP < VP – 0.5 V  
VCP = VP/2  
% typ  
% typ  
ICP vs. Temperature  
LOGIC INPUTS  
V
INH, Input High Voltage  
1.4  
0.6  
1
1.4  
0.6  
1
V min  
VINL, Input Low Voltage  
IINH/IINL, Input Current  
CIN, Input Capacitance  
V max  
µA max  
pF max  
10  
10  
LOGIC OUTPUTS  
VOH, Output High Voltage  
VOL, Output Low Voltage  
1.4  
0.4  
1.4  
0.4  
V min  
V max  
Open-Drain 1 kPull-Up to 1.8 V  
IOL = 500 µA  
POWER SUPPLIES  
VDD  
VDD  
VP1, VP2  
1
2
2.7/3.3  
2.7/3.3  
VDD1  
VDD1/5.5  
V min/V max  
V min/V max  
VDD1  
VDD1/5.5  
IDD (RF and IF)5  
RF Only  
IF Only  
IP (IP1 + IP2)  
Low Power Sleep Mode  
10  
6
4
0.6  
1
10  
6
4
0.6  
1
mA max  
mA max  
mA max  
mA typ  
µA typ  
7.5 mA Typical  
5.0 mA Typical  
2.5 mA Typical  
NOTES  
1Operating temperature range is as follows: B Version: –40°C to +85°C.  
2The B Chip specifications are given as typical values.  
3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency  
less than this value.  
4Guaranteed by design. Sample tested to ensure compliance.  
5TA = 25°C. RF = 1 GHz. Prescaler = 32/33. IF = 500 MHz. Prescaler = 16/17.  
Specifications subject to change without notice.  
–2–  
REV. A  
ADF4212L  
SPECIFICATIONS1  
(VDD1 = VDD2 = 2.7 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; TA =  
TMIN to TMAX, unless otherwise noted; dBm referred to 50 V.)  
Parameter  
B Version B Chips2  
Unit  
Test Conditions/Comments  
NOISE CHARACTERISTICS  
RF Phase Noise Floor3  
–170  
–162  
–170  
–162  
dBc/Hz typ  
dBc/Hz typ  
@ 25 kHz PFD Frequency  
@ 200 kHz PFD Frequency  
@ VCO Output  
@ 1 kHz Offset and 200 kHz PFD Frequency  
See Note 7  
Phase Noise Performance4  
IF: 540 MHz Output5  
IF: 900 MHz Output6  
RF: 900 MHz Output6  
RF: 1750 MHz Output8  
RF: 2400 MHz Output9  
Spurious Signals  
–89  
–87  
–89  
–84  
–87  
–89  
–87  
–89  
–84  
–87  
dBc/Hz typ  
dBc/Hz typ  
dBc/Hz typ  
dBc/Hz typ  
dBc/Hz typ  
See Note 7  
See Note 7  
@ 1 kHz Offset and 1 MHz PFD Frequency  
IF: 540 MHz Output5  
IF: 900 MHz Output6  
RF: 900 MHz Output6  
RF: 1750 MHz Output8  
RF: 2400 MHz Output9  
–88/–90  
–90/–94  
–90/–94  
–80/–82  
–80/–82  
–88/–90  
–90/–94  
–90/–94  
–80/–82  
–80/–82  
dB typ  
dB typ  
dB typ  
dB typ  
dB typ  
@ 200 kHz/400 kHz and 200 kHz PFD Frequency  
See Note 7  
See Note 7  
See Note 7  
@ 200 kHz/400 kHz and 200 kHz PFD Frequency  
NOTES  
1Operating temperature range is as follows: B Version: –40°C to +85°C  
2The B Chip specifications are given as typical values.  
3The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider  
value). See TPC 14.  
4The phase noise is measured with the EVAL-ADF4210/12/13EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the  
REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm).  
5fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fIF = 540 MHz; N = 2700; Loop B/W = 20 kHz  
6fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz  
7Same conditions as listed on the preceding line.  
8fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz  
9fREFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; fRF = 2400 MHz; N = 9800; Loop B/W = 20 kHz  
Specifications subject to change without notice.  
(VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V;  
T = TMIN to TMAX, unless otherwise noted; dBm referred to 50 .)  
A
TIMING CHARACTERISTICS*  
Limit at  
T
MIN to TMAX  
Parameter  
(B Version)  
Unit  
Test Conditions/Comments  
t1  
t2  
t3  
t4  
t5  
t6  
10  
10  
25  
25  
10  
20  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
DATA to CLOCK Setup Time  
DATA to CLOCK Hold Time  
CLOCK High Duration  
CLOCK Low Duration  
CLOCK to LE Setup Time  
LE Pulsewidth  
*Guaranteed by design but not production tested.  
Specifications subject to change without notice.  
t3  
t4  
CLOCK  
t1  
t2  
DB1  
(CONTROL BIT C2)  
DB0 (LSB)  
(CONTROL BIT C1)  
DATA DB20 (MSB)  
DB19  
DB2  
t6  
LE  
LE  
t5  
Figure 1. Timing Diagram  
–3–  
REV. A  
ADF4212L  
ABSOLUTE MAXIMUM RATINGS1, 2, 3  
(TA = 25°C, unless otherwise noted.)  
NOTES  
1Stresses above those listed under Absolute Maximum Ratings may cause perma-  
nent damage to the device. This is a stress rating only; functional operation of the  
device at these or any other conditions above those listed in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
2This device is a high performance RF integrated circuit with an ESD rating of  
<2 kV, and is ESD sensitive. Proper precautions should be taken for handling and  
assembly.  
VDD1 to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V  
V
DD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V  
VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V  
VP1, VP2 to VDD1, VDD2 . . . . . . . . . . . . . . . . –0.3 V to +3.6 V  
Digital I/O Voltage to GND . . . . . . . –0.3 V to DVDD + 0.3 V  
Analog I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V  
REFIN, RFIN, IFIN to GND . . . . . . . –0.3 V to VDD + 0.3 V  
Operating Temperature Range  
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C  
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C  
TSSOP JA Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W  
LFCSP JA Thermal Impedance (Paddle Soldered) . . 122°C/W  
LFCSP JA Thermal Impedance (Paddle Not Soldered) 216°C/W  
Lead Temperature, Soldering  
3GND = AGND = DGND = 0 V  
ORDERING GUIDE  
Model  
ADF4212LBRU –40°C to +85°C  
ADF4212LBCP –40°C to +85°C  
Temperature Range Package Option*  
RU-20  
CP-20  
*RU = Thin Shrink Small Outline Package (TSSOP)  
CP = Chip Scale Package (LFCSP)  
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C  
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C  
Contact the factory for chip availability.  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection. Although the  
ADF4212L features proprietary ESD protection circuitry, permanent damage may occur on devices  
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended  
to avoid performance degradation or loss of functionality.  
–4–  
REV. A  
ADF4212L  
PIN CONFIGURATIONS  
TSSOP  
LFCSP  
1
2
20  
19  
18  
17  
VDD  
1
VDD  
2
VP1  
VP2  
20 19 18 17 16  
1
2
3
4
5
15  
14  
13  
CPRF  
DGNDRF  
RFIN  
DGNDIF  
3
CPRF  
CPIF  
IFIN  
ADF4212L  
TOP VIEW  
(NOT TO SCALE) 12  
4
DGNDIF  
IFIN  
DGNDRF  
RFIN  
AGNDIF  
RSET  
LE  
5
ADF4212L 16  
AGNDRF  
FLO  
TOP VIEW  
6
15  
14  
13  
12  
11  
AGNDRF  
FLO  
AGNDIF  
RSET  
LE  
11  
(Not To Scale)  
6
7
8
9
10  
7
REFIN  
8
DGNDIF  
9
DATA  
CLK  
10  
MUXOUT  
PIN FUNCTION DESCRIPTION  
Mnemonic  
Description  
CPRF  
RF Charge Pump Output. When enabled, this provides ICP to the external RF loop filter, which in turn drives the  
external RF VCO.  
DGNDRF  
RFIN  
Digital Ground Pin for the RF Digital Circuitry.  
Input to the RF Prescaler. This small signal input is normally ac-coupled from the RF VCO.  
Ground Pin for the RF Analog Circuitry.  
AGNDRF  
FLO  
Multiplexed Output of RF/IF Programmable or Reference Dividers, RF/IF Fastlock Mode. CMOS output.  
REFIN  
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of  
100 k. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled.  
DGNDIF  
Digital Ground Pin for the IF Digital, Interface, and Control Circuitry.  
MUXOUT  
This multiplexer output allows either the IF/RF lock detect, the scaled RF, the scaled IF, or the scaled reference  
frequency to be accessed externally.  
CLK  
DATA  
LE  
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the  
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.  
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a  
high impedance CMOS input.  
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four  
latches, the latch being selected using the control bits.  
RSET  
Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output current. The  
nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is  
13.5  
RSET  
ICP MAX  
=
therefore, with RSET = 2.7 k, ICP MAX = 5 mA for both the RF and IF charge pumps.  
Ground Pin for the IF Analog Circuitry.  
AGNDIF  
IFIN  
Input to the IF Prescaler. This small signal input is normally ac-coupled from the IF VCO.  
Output from the IF Charge Pump. This is normally connected to a loop filter that drives the input to an external VCO.  
CPIF  
VP2  
Power Supply for the IF Charge Pump. This should be greater than or equal to VDD2. In systems where VDD2 is 3 V, it  
can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.  
V
V
DD2  
Power Supply for the IF, Digital, and Interface Section. Decoupling capacitors to the ground plane should be  
placed as close as possible to this pin. VDD2 should have a value of between 2.6 V and 3.3 V. VDD2 must have the  
same potential as VDD1.  
DD1  
Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as close as possible  
to this pin. VDD1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same potential as VDD2.  
VP1  
Power Supply for the RF Charge Pump. This should be greater than or equal to VDD1. In systems where VDD1 is 3 V, it  
can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.  
REV. A  
–5–  
ADF4212L–Typical Performance Characteristics  
0
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
V
V
= 3V  
V
= 3V, V = 5V  
= 5mA  
DD  
= 5V  
REFERENCE  
LEVEL = –3.0dBm  
DD P  
I
CP  
P
–5  
–10  
–15  
–20  
PFD FREQUENCY =  
200kHz  
LOOP BANDWIDTH =  
20kHz  
RES. BANDWIDTH = 1Hz  
VIDEO BANDWIDTH = 1Hz  
SWEEP = 2.5 SECONDS  
AVERAGES = 20  
–85.9dB  
–25  
–30  
0
500  
1000  
1500  
2000  
2500  
3000  
–400k  
–200k  
1.75G  
FREQUENCY – Hz  
200k  
400k  
FREQUENCY – MHz  
TPC 1. Input Sensitivity (RF Input)  
TPC 4. Reference Spurs, RF Side (1750 MHz,  
200 kHz, 20 kHz)  
rms NOISE =  
1.38 DEGREES  
10dB/DIV  
R
= –50dBc/Hz  
L
0
–50  
–60  
V
= 3V  
DD  
= 5V  
1.38rms  
V
P
–5  
–10  
–15  
–20  
–25  
–30  
–35  
–70  
–80  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
0
500  
1000  
1500  
100Hz  
1MHz  
FREQUENCY – MHz  
FREQUENCY OFFSET  
FROM 1.75GHz CARRIER  
TPC 5. Integrated Phase Noise (1750 MHz, 200 kHz/20 kHz)  
TPC 2. Input Sensitivity (IF Input)  
0
0
–10  
REFERENCE  
LEVEL = –4.3dBm  
V
= 3V,V = 5V  
P
= 5mA  
DD  
REFERENCE  
V
= 3V,V = 5V  
P
= 5mA  
DD  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
I
CP  
LEVEL = –3.2dBm  
I
CP  
PFD FREQUENCY = 200kHz  
LOOP BANDWIDTH = 20kHz  
RES. BANDWIDTH = 10Hz  
VIDEO BANDWIDTH = 10Hz  
SWEEP = 1.9 SECONDS  
AVERAGES = 22  
PFD FREQUENCY = 200kHz  
LOOP BANDWIDTH = 20kHz  
RES. BANDWIDTH = 10Hz  
VIDEO BANDWIDTH = 10Hz  
SWEEP = 1.9 SECONDS  
AVERAGES = 22  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–84.2dBc/Hz  
1k 2k  
–88.8dBc/Hz  
–2k  
–1k  
1.75G  
FREQUENCY – Hz  
–2k  
–1k  
540M  
FREQUENCY – Hz  
1k  
2k  
TPC 6. Phase Noise, IF Side (540 MHz, 200 kHz/20 kHz)  
TPC 3. Phase Noise, RF Side (1750 MHz, 200 kHz, 20 kHz)  
–6–  
REV. A  
ADF4212L  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–130  
–140  
–150  
V
= 3V,V = 5V  
= 5mA  
REFERENCE  
DD P  
V
= 3V  
DD  
= 5V  
LEVEL = –7.0dBm  
I
CP  
V
P
PFD FREQUENCY = 200kHz  
LOOP BANDWIDTH = 20kHz  
RES. BANDWIDTH = 1Hz  
VIDEO BANDWIDTH = 1Hz  
SWEEP = 2.5 SECONDS  
AVERAGES = 20  
–160  
–170  
–180  
–89.3dBc  
–400k  
–200k  
200k  
400k  
540M  
FREQUENCY – Hz  
10  
100  
1000  
10000  
PHASE DETECTOR FREQUENCY – kHz  
TPC 10. Phase Noise Referred to CP Output vs.  
PFD Frequency, IF Side  
TPC 7. Reference Spurs, IF Side (540 MHz,  
200 kHz, 20 kHz)  
rms NOISE =  
0.83 DEGREES  
10dB/DIV  
R
= –50dBc/Hz  
L
6
4
–50  
–60  
0.83rms  
–70  
–80  
2
–90  
0
–100  
–110  
–120  
–130  
–140  
–150  
–2  
–4  
–6  
0
1
2
3
4
5
100Hz  
1MHz  
V
–V  
FREQUENCY OFFSET  
FROM 540MHz CARRIER  
CP  
TPC 11. RF Charge Pump Output Characteristics  
TPC 8. Integrated Phase Noise (540 MHz, 200 kHz/20 kHz)  
6
4
–130  
V
= 3V  
= 5V  
DD  
V
P
–140  
–150  
V
P
= 3V  
DD  
V 2 = 5.5V  
2
0
–160  
–170  
–180  
–2  
–4  
–6  
0
1
2
3
4
5
10  
100  
1000  
10000  
V
–V  
CP  
PHASE DETECTOR FREQUENCY – kHz  
TPC 12. IF Charge Pump Output Characteristics  
TPC 9. Phase Noise Referred to CP Output vs.  
PFD Frequency, RF Side  
REV. A  
–7–  
ADF4212L  
0
0
–10  
–20  
–30  
–40  
–50  
–20  
–40  
–60  
–80  
–60  
–70  
–80  
–90  
–100  
0
–100  
2
1
3
4
5
–40  
–20  
0
20  
40  
60  
80  
100  
TUNINGVOLTAGE V  
TEMPERATURE –  
C
TPC 13. RF Reference Spurs (200 kHz) vs. VTUNE  
(1750 MHz, 200 kHz, 20 kHz)  
TPC 16. IF Phase Noise vs. Temperature  
(540 MHz, 200 kHz, 20 kHz)  
0
–20  
–40  
–60  
–80  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–100  
–120  
–90  
–100  
0
1
2
3
4
5
0
1
2
3
4
5
TUNINGVOLTAGE V  
TUNINGVOLTAGE V  
TPC 14. IF Reference Spurs (200 kHz) vs. VTUNE  
(1750 MHz, 200 kHz, 20 kHz)  
TPC 17. RF Noise vs. VTUNE  
0
0
–10  
–20  
–30  
–40  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–50  
–60  
–70  
–80  
–90  
–90  
–100  
–100  
–40  
–20  
0
20  
40  
60  
80  
100  
0
1
2
3
4
5
TEMPERATURE –  
C
TUNINGVOLTAGE V  
TPC 15. RF Phase Noise vs. Temperature  
(1750 MHz, 200 kHz, 20 kHz)  
TPC 18. IF Noise vs. VTUNE  
–8–  
REV. A  
ADF4212L  
0
–20  
–40  
–60  
–80  
FREQ  
(MHz)  
FREQ  
s11.IMAG  
(MHz) s11.REAL s11.IMAG  
s11.REAL  
50  
0.97692  
–0.021077 1550  
0.561872  
0.529742  
0.514244  
0.405754  
0.379354  
0.312959  
0.322646  
0.288881  
0.199294  
0.206914  
0.168344  
0.092764  
0.036125  
0.037007  
–0.648879  
–0.668172  
–0.702192  
–0.714541  
–0.703593  
–0.802878  
–0.803970  
–0.807055  
–0.758619  
–0.725029  
–0.770837  
–0.778619  
–0.706197  
–0.716939  
150  
250  
350  
450  
550  
650  
750  
850  
950  
1050  
1150  
1250  
1350  
1450  
0.942115 –0.110459  
0.961217 –0.085802  
0.920667 –0.185830  
0.897441 –0.245482  
0.888164 –0.282399  
0.850012 –0.305457  
0.760189 –0.358884  
0.767363 –0.541032  
0.779511 –0.585687  
0.761034 –0.482539  
0.624825 –0.530108  
0.635364 –0.590526  
0.630242 –0.592498  
0.634506 –0.655932  
1650  
1750  
1850  
1950  
2050  
2150  
2250  
2350  
2450  
2550  
2650  
2750  
2850  
2950  
–100  
–120  
–0.053842 –0.736527  
–40  
–20  
0
20  
40  
60  
80  
100  
TEMPERATURE –  
C
TPC 19. RF Spurs vs. Temperature  
TPC 21. S Parameter Data for the RF Input  
0
–20  
–40  
–60  
–80  
–100  
–120  
–40  
–20  
0
20  
40  
60  
80  
100  
TEMPERATURE –  
C
TPC 20. IF Spurs vs. Temperature  
CIRCUIT DESCRIPTION  
Reference Input Section  
RF/IF Input Stage  
The RF/IF Input Stage is shown in Figure 3. It is followed by a  
two-stage limiting amplifier to generate the CML (Current  
Mode Logic) clock levels needed for the prescaler.  
The Reference Input Stage is shown in Figure 2. SW1 and SW2  
are normally closed switches. SW3 is normally open. When  
power-down is initiated, SW3 is closed and SW1 and SW2 are  
opened. This ensures that there is no loading of the REFIN pin  
on power-down.  
1.6V  
BIAS  
GENERATOR  
AV  
DD  
POWER-DOWN  
CONTROL  
2kꢀ  
2kꢀ  
RF  
RF  
A
B
IN  
100kꢀ  
NC  
SW2  
REF  
IN  
TO R COUNTER  
IN  
NC  
BUFFER  
SW1  
SW3  
AGND  
NC = NO CONNECT  
NO  
Figure 3. RF/IF Input Stage  
Figure 2. Reference Input Stage  
REV. A  
–9–  
ADF4212L  
Prescaler (P/P + 1)  
Phase Frequency Detector (PFD) and Charge Pump  
The PFD takes inputs from the R counter and N counter and  
produces an output proportional to the phase and frequency  
difference between them. Figure 5 is a simplified schematic.  
The PFD includes a fixed delay element that sets the width of  
the antibacklash pulse. This is typically 3 ns. This pulse ensures  
that there is no dead zone in the PFD transfer function and  
gives a consistent reference spur level.  
The dual-modulus prescaler (P/P + 1), along with the A and B  
counters, enables the large division ratio, N, to be realized  
(N = PB + A). The dual modulus prescaler, operating at CML  
levels, takes the clock from the RF/IF input stage and divides it  
down to a manageable frequency for the CMOS A and B  
counters in the RF and IF sections. The prescaler in both sec-  
tions is programmable. It can be set in software to 8/9, 16/17,  
32/33, or 64/65. See Table IV and Table VI. It is based on a  
synchronous 4/5 core.  
UP  
HI  
D1  
Q1  
RF/IF A and B Counters  
U1  
The A and B CMOS counters combine with the dual modulus  
prescaler to allow a wide ranging division ratio in the PLL feed-  
back counter. The counters are specified to work when the  
prescaler output is 200 MHz or less. Typically, they will work  
with 250 MHz output from the prescaler. Thus, with an RF  
input frequency of 2.5 GHz, a prescaler value of 16/17 is valid,  
but a value of 8/9 is not valid.  
+IN  
CLR1  
CHARGE  
PUMP  
CP  
U3  
DELAY  
DOWN  
CLR2  
D2 Q2  
HI  
Pulse Swallow Function  
The A and B counters, in conjunction with the dual modulus  
prescaler, make it possible to generate output frequencies that  
are spaced only by the Reference Frequency divided by R. The  
equation for the VCO frequency is as follows:  
U2  
–IN  
Figure 5. RF/IF PFD Simplified Schematic  
MUXOUT and Lock Detect  
The output multiplexer on the ADF4212L allows the user to  
access various internal points on the chip. The state of MUXOUT  
is controlled by P3, P4, P11, and P12. See Table III and Table V.  
Figure 6 shows the MUXOUT section in block diagram form.  
fVCO = P × B + A × fREFIN /R  
(
)
[
]
fVCO = Output frequency of external voltage controlled oscillator  
(VCO)  
P
= Preset modulus of dual modulus prescaler (8/9, 16/17,  
and so on)  
Lock Detect  
MUXOUT can be programmed for two types of lock detect:  
Digital Lock Detect and Analog Lock Detect. Digital Lock  
Detect is active high. It is set high when the phase error on three  
consecutive Phase Detector cycles is less than 15 ns. It will stay  
set high until a phase error of greater than 25 ns is detected on  
any subsequent PD cycle.  
B
A
= Preset divide ratio of binary 13-bit counter (3 to 8191)  
= Preset divide ratio of binary 6-bit swallow counter (0 to 63)  
f
REFIN = External reference oscillator frequency  
R
= Preset divide ratio of binary 14-bit programmable reference  
counter (1 to 16383)  
The N-channel open-drain Analog Lock Detect should be oper-  
ated with an external pull-up resistor of 10 knominal. When  
lock has been detected, it is high with narrow, low-going pulses.  
N = BP + A  
12-BIT B  
TO PFD  
COUNTER  
LOAD  
LOAD  
FROM RF  
INPUT STAGE  
PRESCALER  
P/P+1  
DV  
DD  
6-BIT A  
COUNTER  
MODULUS  
CONTROL  
IF ANALOG LOCK DETECT  
IF R COUNTER OUTPUT  
IF N COUNTER OUTPUT  
Figure 4. RF/IF A and B Counters  
MUXOUT  
MUX  
CONTROL  
IF/RF ANALOG LOCK DETECT  
RF R COUNTER OUTPUT  
RF N COUNTER OUTPUT  
RF ANALOG LOCK DETECT  
RF/IF R Counter  
The 14-bit RF/IF R counter allows the input reference fre-  
quency to be divided down to produce the input clock to the  
phase frequency detector (PFD). Division ratios from 1 to  
16,383 are allowed.  
DGND  
Figure 6. MUXOUT Schematic  
–10–  
REV. A  
ADF4212L  
RF/IF Input Shift Register  
Table I. C2, C1 Truth Table  
The ADF4212L digital section includes a 24-bit input shift  
register, a 14-bit IF R counter, and an 18-bit IF N counter  
(comprising a 6-bit IF A counter and a 12-bit IF B counter).  
Also present is a 14-bit RF R counter and an 18-bit RF N  
counter (comprising a 6-bit RF A counter and a 12-bit RF B  
counter). Data is clocked into the 24-bit shift register on each  
rising edge of CLK. The data is clocked in MSB first. Data is  
transferred from the shift register to one of four latches on the  
rising edge of LE. The destination latch is determined by the  
state of the two control bits (C2, C1) in the shift register. These  
are the two LSBs, DB1 and DB0, as shown in the timing dia-  
gram of Figure 1. The truth table for these bits is shown in  
Table I. Table II shows a summary of how the latches are  
programmed.  
Control Bits  
C2  
C1  
Data Latch  
0
0
1
1
0
1
0
1
IF R Counter  
IF N Counter (A and B)  
RF R Counter  
RF N Counter (A and B)  
Table II. Latch Summary  
IF R COUNTER LATCH  
IF CP CURRENT  
SETTING  
CONTROL  
BITS  
15-BIT REFERENCE COUNTER  
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1  
DB0  
IFCP2 IFCP1 IFCP0  
P4  
P3  
P2  
P1  
R15  
R14  
R13  
R12  
R11  
R10  
R9  
R8  
R7  
R6  
R5  
R4  
R3  
R2  
R1 C2 (0) C1 (0)  
IF N COUNTER LATCH  
IF  
PRESCALER  
CONTROL  
BITS  
12-BIT B COUNTER  
6-BIT A COUNTER  
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1  
DB0  
P8  
P7  
P6  
P5  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
A6  
A5  
A4  
A3  
A2  
A1 C2 (0) C1 (1)  
RF R COUNTER LATCH  
RF CP CURRENT  
SETTING  
CONTROL  
BITS  
15-BIT RF REFERENCE COUNTER  
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1  
DB0  
RFCP2 RFCP1 RFCP0 P12  
P11  
P10  
P9  
R15  
R14  
R13  
R12  
R11  
R10  
R9  
R8  
R7  
R6  
R5  
R4  
R3  
R2  
R1 C2 (1) C1 (0)  
RF N COUNTER LATCH  
RF  
CONTROL  
BITS  
12-BIT B COUNTER  
6-BIT A COUNTER  
PRESCALER  
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1  
DB0  
P17  
P16  
P15  
P14  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
A6  
A5  
A4  
A3  
A2  
A1 C2 (1) C1 (1)  
REV. A  
–11–  
ADF4212L  
IF R COUNTER LATCH  
Table III. IF R Counter Latch Map  
IF CP CURRENT  
SETTING  
CONTROL  
BITS  
15-BIT IF REFERENCE COUNTER  
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1  
DB0  
IFCP2 IFCP1 IFCP0  
P4  
P3  
P2  
P1  
R15  
R14  
R13  
R12  
R11  
R10  
R9  
R8  
R7  
R6  
R5  
R4  
R3  
R2  
R1 C2 (0) C1 (0)  
R15  
R14  
R13  
..........  
R3  
R2  
R1  
DIVIDE RATIO  
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
..........  
..........  
..........  
..........  
..........  
0
0
0
1
.
0
1
1
0
.
1
0
1
0
.
1
2
3
4
.
.
.
.
..........  
..........  
..........  
.
.
.
.
.
1
.
1
.
1
.
1
.
0
.
0
.
32764  
1
1
1
1
1
1
1
1
1
..........  
..........  
..........  
1
1
1
0
1
1
1
0
1
32765  
32766  
32767  
P1  
IF PD POLARITY  
0
1
NEGATIVE  
POSITIVE  
CHARGE PUMP  
OUTPUT  
P2  
0
1
NORMAL  
THREE-STATE  
P12  
P11  
P4  
P3  
MUXOUT  
FROM RF R LATCH  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LOGIC LOW STATE  
IF ANALOG LOCK DETECT  
IF REFERENCE DIVIDER OUTPUT  
IF N DIVIDER OUTPUT  
RF ANALOG LOCK DETECT  
RF/IF ANALOG LOCK DETECT  
IF DIGITAL LOCK DETECT  
LOGIC HIGH STATE  
RF REFERENCE DIVIDER OUTPUT  
RF N DIVIDER OUTPUT  
THREE-STATE OUTPUT  
IF COUNTER RESET  
RF DIGITAL LOCK DETECT  
RF/IF DIGITAL LOCK DETECT  
RF COUNTER RESET  
IF AND RF COUNTER RESET  
I
(mA)  
CP  
IFCP2  
IFCP1  
IFCP0  
1.5kꢀ  
1.1250  
2.2500  
3.3750  
4.5000  
5.6250  
6.7500  
7.7875  
9.0000  
2.7kꢀ  
5.6kꢀ  
0.301  
0.602  
0.904  
1.205  
1.506  
1.808  
2.109  
2.411  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.625  
1.250  
1.875  
2.500  
3.125  
3.750  
4.375  
5.000  
–12–  
REV. A  
ADF4212L  
IF N COUNTER LATCH  
Table IV. IF N Counter Latch Map  
IF  
CONTROL  
BITS  
12-BIT B COUNTER  
6-BIT A COUNTER  
PRESCALER  
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1  
DB0  
P8  
P7  
P6  
P5  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
A6  
A5  
A4  
A3  
A2  
A1 C2 (0) C1 (1)  
A6  
A5  
..........  
A2  
A1  
A COUNTER  
DIVIDE RATIO  
P6 P5 PRESCALERVALUE  
0
0
0
0
.
0
0
0
0
.
..........  
..........  
..........  
..........  
..........  
0
0
1
0
.
0
1
0
1
.
0
1
2
3
.
0
0
1
1
0
1
0
1
8/9  
16/17  
32/33  
64/65  
P7 IF POWER-DOWN  
0
1
DISABLED  
ENABLED  
.
.
..........  
..........  
..........  
.
.
.
.
1
.
1
.
0
.
0
.
60  
1
1
1
1
1
1
..........  
..........  
..........  
0
1
1
1
0
1
61  
62  
63  
P8 IF CP GAIN  
0
1
DISABLED  
ENABLED  
B12  
B11  
B10  
B3  
B2  
B1  
B COUNTER DIVIDE RATIO  
0
0
.
0
0
.
0
0
.
..........  
..........  
..........  
0
1
.
1
0
.
1
0
.
3
4
.
.
.
.
..........  
..........  
..........  
.
.
.
.
.
1
.
1
.
1
.
1
.
0
.
0
.
4092  
1
1
1
1
1
1
1
1
1
..........  
..........  
..........  
1
1
1
0
1
1
1
0
1
4093  
4094  
4095  
N = BP+A, P IS PRESCALERVALUE SET INTHE FUNCTION LATCH  
B MUST BE GREATERTHAN OR EQUALTO A  
2
FOR CONTIGUOUSVALUES OF N, N  
IS (P – P)  
MIN  
REV. A  
–13–  
ADF4212L  
RF R COUNTER LATCH  
Table V. RF R Counter Latch Map  
RF CP CURRENT  
SETTING  
CONTROL  
BITS  
15-BIT RF REFERENCE COUNTER  
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1  
DB0  
RFCP2 RFCP1 RFCP0 P12  
P11  
P10  
P9  
R15  
R14  
R13  
R12  
R11  
R10  
R9  
R8  
R7  
R6  
R5  
R4  
R3  
R2  
R1 C2 (1) C1 (0)  
R15  
R14  
R13  
..........  
R3  
R2  
R1  
DIVIDE RATIO  
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
..........  
..........  
..........  
..........  
..........  
0
0
0
1
.
0
1
1
0
.
1
0
1
0
.
1
2
3
4
.
.
.
.
..........  
..........  
..........  
.
.
.
.
.
1
.
1
.
1
.
1
.
0
.
0
.
32764  
1
1
1
1
1
1
1
1
1
..........  
..........  
..........  
1
1
1
0
1
1
1
0
1
32765  
32766  
32767  
P9  
RF PD POLARITY  
0
1
NEGATIVE  
POSITIVE  
RF CHARGE  
PUMP OUTPUT  
P10  
0
1
NORMAL  
THREE-STATE  
P12  
P11  
P4  
P3  
MUXOUT  
FROM IF R LATCH  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LOGIC LOW STATE  
IF ANALOG LOCK DETECT  
IF REFERENCE DIVIDER OUTPUT  
IF N DIVIDER OUTPUT  
RF ANALOG LOCK DETECT  
RF/IF ANALOG LOCK DETECT  
IF DIGITAL LOCK DETECT  
LOGIC HIGH STATE  
RF REFERENCE DIVIDER OUTPUT  
RF N DIVIDER OUTPUT  
THREE-STATE OUTPUT  
IF COUNTER RESET  
RF DIGITAL LOCK DETECT  
RF/IF DIGITAL LOCK DETECT  
RF COUNTER RESET  
IF AND RF COUNTER RESET  
I
(mA)  
CP  
RFCP2 RFCP1 RFCP0  
1.5kꢀ  
2.7kꢀ  
5.6kꢀ  
0.301  
0.602  
0.904  
1.205  
1.506  
1.808  
2.109  
2.411  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.1250  
2.2500  
3.3750  
4.5000  
5.6250  
6.7500  
7.7875  
9.0000  
0.625  
1.250  
1.875  
2.500  
3.125  
3.750  
4.375  
5.000  
–14–  
REV. A  
ADF4212L  
RF N COUNTER LATCH  
Table VI. RF N Counter Latch Map  
RF  
CONTROL  
BITS  
12-BIT B COUNTER  
6-BIT A COUNTER  
PRESCALER  
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1  
DB0  
P17  
P16  
P15  
P14  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
A6  
A5  
A4  
A3  
A2  
A1 C2 (1) C1 (1)  
A6  
A5  
..........  
A2  
A1  
A COUNTER  
DIVIDE RATIO  
P15 P14 PRESCALERVALUE  
0
0
0
0
.
0
0
0
0
.
..........  
..........  
..........  
..........  
..........  
0
0
1
0
.
0
1
0
1
.
0
1
2
3
.
0
0
1
1
0
1
0
1
8/9  
16/17  
32/33  
64/65  
P16 RF POWER-DOWN  
0
1
DISABLED  
ENABLED  
.
.
..........  
..........  
..........  
.
.
.
.
1
.
1
.
0
.
0
.
60  
1
1
1
1
1
1
..........  
..........  
..........  
0
1
1
1
0
1
61  
62  
63  
P17 RF CP GAIN  
B12  
B11  
B10  
B3  
B2  
B1  
B COUNTER DIVIDE RATIO  
0
1
DISABLED  
ENABLED  
0
0
.
0
0
.
0
0
.
..........  
0
1
.
1
0
.
1
0
.
3
4
.
..........  
..........  
.
.
.
..........  
..........  
..........  
.
.
.
.
.
1
.
1
.
1
.
1
.
0
.
0
.
4092  
1
1
1
1
1
1
1
1
1
..........  
..........  
..........  
1
1
1
0
1
1
1
0
1
4093  
4094  
4095  
N = BP+A, P IS PRESCALERVALUE SET INTHE FUNCTION LATCH  
B MUST BE GREATERTHAN OR EQUALTO A  
2
FOR CONTIGUOUSVALUES OF N, N  
IS (P – P)  
MIN  
REV. A  
–15–  
ADF4212L  
PROGRAM MODES  
Table III and Table V show how to set up the Program Modes  
in the ADF4212L. The following should be noted:  
The REFIN oscillator circuit is only disabled if both the IF and  
RF power-downs are set.  
The input register and latches remain active and are capable of  
loading and latching data during all power-down modes.  
1. IF and RF Analog Lock Detect indicate when the PLL is in  
lock. When the loop is locked and either IF or RF Analog  
Lock Detect is selected, then the MUXOUT pin will show a  
logic high with narrow, low-going pulses. When the IF/RF  
Analog Lock Detect is chosen, then the locked condition is  
indicated only when both IF and RF loops are locked.  
The IF/RF section of the device will return to normal powered-up  
operation immediately upon LE latching a “0” to the appropri-  
ate Power-Down Bit.  
IF SECTION  
2. The IF Counter Reset Mode resets the R and AB counters in  
the IF section and also puts the IF charge pump into three-  
state. The RF Counter Reset Mode resets the R and AB  
counters in the RF section and also puts the RF charge  
pump into three-state. The IF and RF Counter Reset Mode  
does both of the above. Upon removal of the reset bits, the  
AB counter resumes counting in close alignment with the R  
counter. (Maximum error is one prescaler output cycle.)  
Programmable if Reference (R) Counter  
If control bits C2, C1 are 0, 0, the data is transferred from the  
input shift register to the 14-bit IFR counter. Table III shows  
the input shift register data format for the IFR counter and the  
divide ratios possible.  
IF Phase Detector Polarity  
P1 sets the IF Phase Detector Polarity. When the IF VCO char-  
acteristics are positive, this should be set to “1.” When they are  
negative, it should be set to “0.” See Table III.  
3. The Fastlock Mode uses MUXOUT to switch a second loop  
filter damping resistor to ground during Fastlock operation.  
Activation of Fastlock occurs whenever RF CP Gain in the  
RF Reference counter is set to “1.”  
IF Charge Pump Three-State  
P2 puts the IF charge pump into three-state mode when pro-  
grammed to a “1.” It should be set to “0” for normal operation.  
See Table III.  
IF and RF Power-Down  
It is possible to program the ADF4210 family for either synchro-  
nous or asynchronous power-down on either the IF or RF side.  
IF Program Modes  
Table III and Table V show how to set up the Program Modes  
in the ADF4212L.  
Synchronous IF Power-Down  
Programming a “1” to P7 of the ADF4212L will initiate a  
power-down. If P2 of the ADF4212L has been set to “0” (nor-  
mal operation), a synchronous power-down is conducted. The  
device will automatically put the charge pump into three-state  
and complete the power-down.  
IF Charge Pump Currents  
IFCP2, IFCP1, IFCP0 program Current Setting for the IF charge  
pump. See Table III.  
Programmable IF AB Counter  
If control bits C2, C1 are 0, 1, the data in the input register is  
used to program the IF AB counter. The N counter consists of a  
6-bit swallow counter (A counter) and 12-bit programmable  
counter (B counter). Table IV shows the input register data  
format for programming the IF AB counter and the divide ratios  
possible.  
Asynchronous IF Power-Down  
If P2 of the ADF4212L has been set to “1” (three-state the IF  
charge pump) and P7 is subsequently set to “1,” an asynchronous  
power-down is conducted. The device will go into power-down  
on the rising edge of LE, which latches the “1” to the IF Power-  
Down Bit (P7).  
IF Prescaler Value  
P5 and P6 in the IF A, B Counter Latch set the IF prescaler  
values. See Table IV.  
Synchronous RF Power-Down  
Programming a “1” to P16 of the ADF4212L will initiate a  
power-down. If P10 of the ADF4212L has been set to “0”  
(normal operation), a synchronous power-down is conducted.  
The device will automatically put the charge pump into three-  
state and then complete the power-down.  
IF Power-Down  
Table III and Table V show the power-down bits in the  
ADF4212L.  
IF Fastlock  
Asynchronous RF Power-Down  
The IF CP Gain Bit (P8) of the IF N Register in the ADF4212L  
is the Fastlock Enable Bit. Only when this is “1” is IF Fastlock  
enabled. When Fastlock is enabled, the IF CP current is set to  
maximum value. Also, an extra loop filter damping resistor to  
ground is switched in using the FLO pin, thus compensating for  
the change in loop characteristics while in Fastlock. Since the IF  
CP Gain Bit is contained in the IF N Counter, only one write is  
needed to both program a new output frequency and initiate  
Fastlock. To come out of fastlock, the IF CP Gain Bit on the IF  
N Register must be set to “0.” See Table IV.  
If P10 of the ADF4212L has been set to “1” (three-state the RF  
charge pump) and P16 is subsequently set to “1,” an asynchronous  
power-down is conducted. The device will go into power-down  
on the rising edge of LE, which latches the “1” to the RF Power-  
Down Bit (P16).  
Activation of either synchronous or asynchronous power-down  
forces the IF/RF loop’s R and AB dividers to their load state  
conditions and the IF/RF input section is debiased to a high  
impedance state.  
–16–  
REV. A  
ADF4212L  
RF SECTION  
RF Power-Down  
Programmable RF Reference (R) Counter  
If control bits C2, C1 are 1, 0, the data is transferred from the  
input shift register to the 14-bit RFR counter. Table V shows  
the input shift register data format for the RFR counter and the  
divide ratios possible.  
Table III and Table V show the power-down bits in the  
ADF4210 family.  
RF Fastlock  
The RF CP Gain Bit (P17) of the RF N Register in the  
ADF4212L is the Fastlock Enable Bit. Only when this is “1” is  
IF Fastlock enabled. When Fastlock is enabled, the RF CP  
current is set to maximum value. Also, an extra loop filter  
damping resistor to ground is switched in using the FLO pin,  
thus compensating for the change in loop characteristics while  
in Fastlock. Since the RF CP Gain Bit is contained in the RF N  
counter, only one write is needed to both program a new output  
frequency and initiate Fastlock. To come out of Fastlock, the RF  
CP Gain Bit on the RF N Register must be set to “0.” See  
Table VI.  
RF Phase Detector Polarity  
P9 sets the IF Phase Detector Polarity. When the RF VCO  
characteristics are positive, this should be set to “1.” When they  
are negative, it should be set to “0.” See Table V.  
RF Charge Pump Three-State  
P10 puts the RF charge pump into three-state mode when pro-  
grammed to a “1.” It should be set to “0” for normal operation.  
See Table V.  
RF Program Modes  
Table III and Table V show how to set up the Program Modes  
in the ADF4212L.  
APPLICATIONS  
Local Oscillator for GSM Handset Receiver  
Figure 7 shows the ADF4212L being used with a VCO to pro-  
duce the required LOs for a GSM base station transmitter or  
receiver. The reference input signal is applied to the circuit at  
FREFIN and, in this case, is terminated in 50 . Typical GSM  
systems would have a 13 MHz TCXO driving the Reference  
Input without any 50 termination. In order to have a channel  
spacing of 200 kHz (the GSM standard), the reference input  
must be divided by 65, using the on-chip reference.  
RF Charge Pump Currents  
RFCP2, RFCP1, and RFCP0 program Current Setting for the  
RF charge pump. See Table V.  
Programmable RF N Counter  
If control bits C2, C1 are 1, 1, the data in the input register is  
used to program the RF N (A + B) counter. The N counter  
consists of a 6-bit swallow counter (A counter) and 12-bit pro-  
grammable counter (B counter). Table IV shows the input  
register data format for programming the RF N counter and the  
divide ratios possible. See Table VI.  
The RF output frequency range is 880 MHz to 915 MHz. The  
loop filter is designed to give a 20 kHz loop bandwidth. The  
filter is set up for a 5 mA charge pump current, and the VCO  
sensitivity is 12 MHz/V. The IF output is fixed at 540 MHz.  
The filter is again designed to have a bandwidth of 20 kHz, and  
the system is programmed to give channel steps of 200 kHz.  
RF Prescaler Value  
P14 and P15 in the RF A, B Counter Latch set the RF prescaler  
values. See Table VI.  
RF  
IF  
OUT  
OUT  
V
V
V
P
P
DD  
100pF  
100pF  
18ꢀ  
18ꢀ  
18ꢀ  
V 2  
V
2
V 1  
DD  
V 1  
P
100pF  
100pF  
P
DD  
3.3kꢀ  
3.3kꢀ  
18ꢀ  
18ꢀ  
V
V
CC  
CC  
CP  
CP  
RF  
IF  
VCO190-540T  
VCO190-902U  
18ꢀ  
620pF  
1.3nF  
620pF  
1nF  
1.7kꢀ  
5.6kꢀ  
ADF4212L  
8.2nF  
13nF  
R
SET  
2.7kꢀ  
LOCK  
DETECT  
MUXOUT  
100pF  
100pF  
RF  
IN  
IF  
IN  
51ꢀ  
51ꢀ  
CLK  
DATA  
LE  
100pF 100pF  
SPI COMPATIBLE SERIAL BUS  
FREF  
REF  
IN  
IN  
51ꢀ  
DECOUPLING CAPACITORS (22F/10pF) ONV , V OFTHE ADF4212L AND ONV OFTHE VCOs  
CC  
DD  
P
HAVE BEEN OMITTED FROMTHE DIAGRAMTO AID CLARITY.  
Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4212L  
REV. A  
–17–  
ADF4212L  
Wideband PLL  
multiplied by the gain factor of 4), VCO KD of 80 MHz/V  
(sensitivity of the M3500-1324 at an output of 2100 MHz), and  
a phase margin of 45 degrees.  
Many of the wireless applications for synthesizers and VCOs in  
PLLs are narrow-band in nature. These applications include the  
various wireless standards such as GSM, DSC1800, CDMA,  
or WCDMA. In each of these cases, the total tuning range for  
the local oscillator is less than 100 MHz. However, there are  
also wideband applications where the local oscillator could have  
up to an octave tuning range. For example, cable television  
tuners have a total range of about 400 MHz. Figure 8 shows an  
application where the ADF4212L is used to control and program  
the Micronetics M3500-1324. The loop filter was designed for an  
RF output of 2100 MHz, a loop bandwidth of 40 kHz, a PFD  
frequency of 1 MHz, ICP of 10 mA (2.5 mA synthesizer ICP  
In narrow-band applications, there is generally a small variation  
in output frequency (generally less than 10%) and also a small  
variation in VCO sensitivity over the range (typically <10%).  
However, in wideband applications both of these parameters have  
a much greater variation, which will change the loop bandwidth.  
This in turn can affect stability and lock time. By changing the  
programmable ICP, it is possible to get compensation for these  
varying loop conditions and to ensure that the loop is always  
operating close to optimal conditions.  
RF  
OUT  
V
V
DD  
20V  
12V  
P
100pF  
V
CC  
3kꢀ  
AD820  
1kꢀ  
100pF  
18ꢀ  
18ꢀ  
18ꢀ  
V
1
V
2
V 1 V 2  
DD  
DD  
P
P
V_TUNE  
M3500-1324  
GND  
OUT  
20kꢀ  
CP  
RF  
1000pF 1000pF  
FREF  
REF  
IN  
IN  
3.9nF  
27nF  
130pF  
R
SET  
51ꢀ  
2.7kꢀ  
470ꢀ  
ADF4212L  
CLK  
LOCK  
DETECT  
SPI COMPATIBLE SERIAL BUS DATA  
LE  
MUXOUT  
100pF  
RF  
IN  
51ꢀ  
DECOUPLING CAPACITORS ONV , V OFTHE ADF4212L, ONV  
DD  
OFTHE AD820 AND ON  
P
CC  
V
OFTHE M3500-2250 HAVE BEEN OMITTED FROMTHE DIAGRAMTO AID CLARITY.  
CC  
THE IF SECTION OFTHE CIRCUIT HAS ALSO BEEN OMITTEDTO SIMPLIFYTHE SCHEMATIC.  
Figure 8. Wideband PLL Circuit  
–18–  
REV. A  
ADF4212L  
Interfacing  
ADSP-2181 Interface  
The ADF4212L has a simple SPI compatible serial interface for  
writing to the device. SCLK, SDATA, and LE control the data  
transfer. When LE (Latch Enable) goes high, the 22 bits that  
have been clocked into the input register on each rising edge of  
SCLK will get transferred to the appropriate latch. See Figure 1  
for the Timing Diagram and Table I for the Latch Truth Table.  
Figure 10 shows the interface between the ADF4212L and the  
ADSP-21xx Digital Signal Processor. As previously discussed,  
the ADF4212L needs a 24-bit serial word for each latch write.  
The easiest way to accomplish this using the ADSP-21xx family  
is to use the Autobuffered Transmit Mode of operation with  
Alternate Framing. This provides a means for transmitting an  
entire block of serial data before an interrupt is generated. Set  
up the word length for eight bits and use three memory loca-  
tions for each 24-bit word. To program each 24-bit latch, store  
the three 8-bit bytes, enable the Autobuffered Mode, and then  
write to the transmit register of the DSP. This last operation  
initiates the autobuffer transfer.  
The maximum allowable serial clock rate is 20 MHz. This  
means that the maximum update rate possible for the device is  
909 kHz or one update every 1.1 µs. This is certainly more than  
adequate for systems that will have typical lock times in hun-  
dreds of microseconds.  
ADuC812 Interface  
Figure 9 shows the interface between the ADF4212L and the  
ADuC812 microconverter. Since the ADuC812 is based on an  
8051 core, this interface can be used with any 8051-based  
microcontroller. The microconverter is set up for SPI Master  
Mode with CPHA = 0. To initiate the operation, the I/O port  
driving LE is brought low. Each latch of the ADF4212L needs a  
24-bit word. This is accomplished by writing three 8-bit bytes  
from the microconverter to the device. When the third byte has  
been written, the LE input should be brought high to complete  
the transfer.  
ADuC812  
ADF4212L  
SCLK  
MOSI  
SCLK  
SDATA  
LE  
CE  
I/O PORTS  
MUXOUT  
(LOCK DETECT)  
Figure 9. ADuC812 to ADF4212L Interface  
On first applying power to the ADF4212L, four writes (one  
each to the R counter latch and the AB counter latch for both  
IF and RF side) are required for the output to become active.  
ADSP-21xx  
ADF4212L  
SCLK  
DT  
SCLK  
SDATA  
When operating in the mode described, the maximum SCLOCK  
rate of the ADuC812 is 4 MHz. This means that the maxi-  
mum rate at which the output frequency can be changed will  
be 180 kHz.  
TFS  
LE  
CE  
I/O FLAGS  
MUXOUT  
(LOCK DETECT)  
Figure 10. ADSP-21xx to ADF4212L Interface  
REV. A  
–19–  
ADF4212L  
OUTLINE DIMENSIONS  
20-Lead Thin Shrink Small Outline Package [TSSOP]  
(RU-20)  
Dimensions shown in millimeters  
6.60  
6.50  
6.40  
20  
11  
10  
4.50  
4.40  
4.30  
6.40 BSC  
1
PIN 1  
0.65  
BSC  
1.20  
MAX  
0.15  
0.05  
0.20  
0.09  
0.75  
0.60  
0.45  
8ꢁ  
0ꢁ  
0.30  
0.19  
SEATING  
PLANE  
COPLANARITY  
0.10  
COMPLIANT TO JEDEC STANDARDS MO-153AC  
20-Lead Frame Chip Scale Package [LFCSP]  
4 mm × 4 mm Body  
(CP-20)  
Dimensions shown in millimeters  
0.60  
MAX  
4.0  
BSC SQ  
0.60  
MAX  
16  
15  
20  
1
5
PIN 1  
INDICATOR  
2.25  
2.10 SQ  
1.95  
3.75  
BSC SQ  
TOP  
VIEW  
BOTTOM  
VIEW  
11  
10  
0.75  
0.55  
0.35  
6
1.00 MAX  
0.65 NOM  
0.30  
0.23  
0.18  
12MAX  
1.00  
0.90  
0.80  
0.05  
0.02  
0.00  
SEATING  
PLANE  
COPLANARITY  
0.08  
0.50  
BSC  
0.20  
REF  
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1  
Revision History  
Location  
Page  
3/03—Data Sheet changed from REV. 0 to REV. A.  
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Changes to Table IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Changes to Table VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Changes to Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
–20–  
REV. A  

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