ADF4217LBRUZ [ADI]
IC PLL FREQUENCY SYNTHESIZER, 3000 MHz, PDSO20, MO-153AC, TSSOP-20, PLL or Frequency Synthesis Circuit;
| 型号： | ADF4217LBRUZ |
| 厂家： | 
ADI |
| 描述： | IC PLL FREQUENCY SYNTHESIZER, 3000 MHz, PDSO20, MO-153AC, TSSOP-20, PLL or Frequency Synthesis Circuit 光电二极管 |
| 文件： | 总24页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Low Power
Frequency Synthesizers
a
ADF4217L/ADF4218L/ADF4219L
FEATURES
GENERAL DESCRIPTION
Total IDD: 7.1 mA
Bandwidth/RF 3.0 GHz
ADF4217L/ADF4218L, IF 1.1 GHz
ADF4219L, IF 1.0 GHz
2.6 V to 3.3 V Power Supply
1.8 V Logic Compatibility
Separate VP Allows Extended Tuning Voltage
Selectable Dual Modulus Prescaler
Selectable Charge Pump Currents
Charge Pump Current Matching of 1%
3-Wire Serial Interface
The ADF4217L/ADF4218L/ADF4219L are low power dual
frequency synthesizers that can be used to implement local
oscillators in the up-conversion and down-conversion sections
of wireless receivers and transmitters. They can provide the LO
for both the RF and IF sections. They consist of a low noise
digital PFD (phase frequency detector), a precision charge pump,
programmable reference divider, programmable A and B counters,
a
and a dual modulus prescaler (P/P + 1). The A and B counters,
in conjunction with the dual modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R Counter) allows selectable REFIN fre-
quencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizers are used with an
external loop filter and VCOs (voltage controlled oscillators).
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS, WCDMA)
Wireless LANs
Communications Test Equipment
Cable TV Tuners (CATV)
Control of all the on-chip registers is via a simple 3-wire interface
with 1.8 V compatibility. The devices operate with a power supply
ranging from 2.6 V to 3.3 V and can be powered down when
not in use.
FUNCTIONAL BLOCK DIAGRAM
ADF4219L ONLY
NC
V
1
V
2
V 1
V 2
P
DD
DD
P
ADF4217L/
ADF4218L/
ADF4219L
N = BP + A
IF
11(13)-BIT IF
B COUNTER
PHASE
COMPARATOR
IF
A
IN
CHARGE
PUMP
PRESCALER
CP
IF
IF
B
IN
6(5)-BIT IF
A COUNTER
ADF4217L
ADF4218L
ONLY
IF
LOCK
DETECT
REF
BUFFER
IN
14(15)-BIT IF
R COUNTER
OUTPUT
MUX
MUXOUT
CLOCK
DATA
LE
22-BIT
DATA
REGISTER
SDOUT
RF
14(15)-BIT RF
R COUNTER
LOCK
DETECT
N = BP + A
CHARGE
PUMP
11(13)-BIT RF
B COUNTER
CP
RF
RF
RF
A
B
IN
RF
PHASE
COMPARATOR
PRESCALER
IN
6(5)-BIT RF
A COUNTER
DGND
AGND
DGND
AGND
IF
FEATURES IN ( ) REFERTO ADF4219L
NC = NO CONNECT
RF
RF
IF
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
ADF4217L/ADF4218L/ADF4219L–SPECIFICATIONS1
(VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.)
BChips2
(Typical)
Parameter
B Version1
Unit
Test Conditions/Comments
RF CHARACTERISTICS
Use a square wave for operation
below minimum frequency spec.
RF Input Frequency (RFIN)
ADF4217L, ADF4218L
ADF4217L, ADF4218L
ADF4219L
0.15/3.0
0.15/2.5
0.8/2.2
0.15/3.0
0.15/2.5
0.8/2.2
GHz min/max
GHz min/max
GHz min/max
–10 dBm minimum input signal
–15 dBm minimum input signal
–20 dBm minimum input signal
RF Input Sensitivity
ADF4217L, ADF4218L
ADF4219L
–15/0
–20/0
–15/0
–20/0
dBm min/max
dBm min/max
IF Input Frequency (IFIN)
ADF4217L/ADF4218L
ADF4219L P = 16/17
ADF4219L P = 8/9
0.045/1.1
0.045/1.0
0.045/0.55
–15/0
0.045/1.1
0.045/1.0
0.045/0.55
–15/0
GHz min/max
GHz min/max
GHz min/max
dBm min/max
–15 dBm minimum input signal
–10 dBm minimum input signal
–10 dBm minimum input signal
IF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency3
188
188
MHz max
REFIN CHARACTERISTICS
Reference Input Frequency
10/110
0.5
10/110
0.5
MHz min/max
V p-p min
For f < 10 MHz, use dc-coupled
square wave, (0 to VDD).
AC-coupled. When dc-coupled,
0 to VDD max.
Reference Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
10
100
10
100
pF max
µA max
(CMOS compatible)
PHASE DETECTOR
Phase Detector Frequency4
56
56
MHz max
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
4
1
1
1
6
5
2
4
1
1
1
6
5
2
mA typ
mA typ
% typ
nA typ
% max
% max
% typ
0.5 V < VCP < VP – 0.5, 1% typ
0.5 V < VCP < VP – 0.5, 0.1% typ
VCP = VP/2
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
1.4
0.6
1
10
100
1.4
0.6
1
10
100
V min
V max
µA max
pF max
µA max
I
INH/IINL, Input Current
CIN, Input Capacitance
Reference Input Current
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
VDD – 0.4
0.4
VDD – 0.4
0.4
V min
V max
IOH = 1 mA
IOL = 1 mA
POWER SUPPLIES
VDD
1
2.6/3.3
2.6/3.3
V min/V max
V
DD2
VDD
VDD1/5.5 V
10
7
5
1
VDD1
VDD1/5.5 V
10
7
5
VP1, VP2
V min/V max
mA max
mA
IDD (RF + IF)5
(RF only)5
7.1 mA typ
4.7 mA typ
3.4 mA typ
TA = 25°C
(IF only)5
mA
IP (IP1 + IP2)
Low Power Sleep Mode
0.6
1
0.6
1
mA typ
µA typ
–2–
REV. C
ADF4217L/ADF4218L/ADF4219L
BChips2
(Typical)
Parameter
B Version1
Unit
Test Conditions/Comments
NOISE CHARACTERISTICS6
RF Phase Noise Floor7
–171
–163
–167
–159
–171
–163
–167
–159
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 30 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 30 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
1.95 GHz Output; 30 kHz PFD
900 MHz Output; 200 kHz PFD
900 MHz Output; 30 kHz PFD
900 MHz Output; 200 kHz PFD
Measured at Offset of fPFD/2fPFD
IF Phase Noise Floor7
Phase Noise Performance8
RF9
–75
–90
–77
–86
–75
–90
–77
–86
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
RF10
IF11
IF12
Spurious Signals
RF9
RF10
IF11
IF12
–78/–85
–80/–84
–79/–86
–80/–84
–78/–85
–80/–84
–79/–86
–80/–84
dBc typ
dBc typ
dBc typ
dBc typ
NOTES
1Operating temperature range is as follows: B Version: –40°C to +85°C.
2The BChip specifications are given as typical values.
3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
that is less than this value.
4Guaranteed by design. Sample tested to ensure compliance.
5This includes relevant IP.
6VDD = 3 V; P = 16/32; IFIN /RFIN for ADF4218L, ADF4219L = 540 MHz/900 MHz.
7The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
8The phase noise is measured with the EVAL-ADF421xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN
for the synthesizer. (fREFOUT = 10 MHz @ 0 dBm.)
9fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 1 kHz; fRF = 1.95 GHz; N = 65000; Loop B/W = 3 kHz
10
11
12
f
f
f
= 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz
= 10 MHz; fPFD = 30 kHz; Offset frequency = 1 kHz; fIF = 900 MHz; N = 30000; Loop B/W = 3 kHz
= 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fIF = 900 MHz; N = 4500; Loop B/W = 20 kHz
REFIN
REFIN
REFIN
Specifications subject to change without notice.
(VDD1 = VDD2 = 3 V ؎ 10%, 5 V ؎ 10%; VDD1, VDD2 ≤ VP1,
TIMING CHARACTERISTICS
VP2 ≤ 6.0 V ; AGNDRF1 = DGNDRF1 = AGNDRF2 = DGNDRF2 = 0 V; TA = TMIN to TMAX, unless otherwise noted.)
Limit at
TMIN to TMAX
(B Version)
Parameter
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
10
10
25
25
10
50
ns min
ns min
ns min
ns min
ns min
ns min
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
Guaranteed by design but not production tested.
t3
t4
CLOCK
t1
t2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
DATA
LE
DB21 (MSB)
DB20
DB2
t6
t5
LE
Figure 1. Timing Diagram
–3–
REV. C
ADF4217L/ADF4218L/ADF4219L
ABSOLUTE MAXIMUM RATINGS1, 2
TSSOP JA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
(
TA = 25°C, unless otherwise noted.)
LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W
JA
Lead Temperature, Soldering
VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V
VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V
TSSOP, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . 215°C
TSSOP, Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . 220°C
LGA, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . 240°C
LGA, Infrared (20 sec) . . . . . . . . . . . . . . . . . . . . . . . 240°C
VP1, VP2 to VDD
1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
REFIN, RF1IN (A, B), IFIN (A, B)
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
RFINA to RFINB . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 mV
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operationalsections
of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2This device is a high performance RF integrated circuit with an ESD rating of
< 2 kV and is ESD sensitive. Proper precautions should be taken for handling and
assembly.
3GND = AGND = DGND = 0 V.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
*
ADF4217L/ADF4218L/ADF4219LBRU
ADF4217L/ADF4218L/ADF4219LBCC
–40°C to +85°C
–40°C to +85°C
Thin Shrink Small Outline Package (TSSOP) RU-20
Chip Array CASON (LGA) CC-24
*Contact the factory for chip availability.
CAUTION
ESD(electrostaticdischarge)sensitivedevice.Electrostaticchargesashighas4000 Vreadilyaccumulate
on the human body and test equipment and can discharge without detection. Although the ADF4217L/
ADF4218L/ADF4219L feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. C
ADF4217L/ADF4218L/ADF4219L
PIN CONFIGURATIONS
TSSOP
TSSOP
VDD
1
VDD1
1
2
20
19
1
2
20
19
18
17
16
15
14
13
12
11
VDD
2
V
DD2
VP1
CPRF
VP1
CPRF
VP2
VP2
3
18 CPIF
17
3
CPIF
DGNDRF
DGNDRF
4
4
DGNDIF
DGNDIF
IFIN
RFIN
A
B
5
ADF4217L/
ADF4218L
16
15
14
13
12
11
RFIN
A
B
5
IFINA
IFINB
AGNDIF
LE
ADF4219L
RFIN
RFIN
6
6
AGNDIF
AGNDRF
REFIN
AGNDRF
REFIN
7
7
NC
8
8
LE
DGNDIF
DGNDIF
9
DATA
CLK
9
DATA
CLK
10
10
MUXOUT
MUXOUT
CHIP SCALE
CHIP SCALE
24
23
22
1
2
3
4
5
6
7
8
9
NC
VP1
21
NC
24
23
22
20
19
18
17
16
15
14
13
CPIF
1
2
3
4
5
6
7
8
9
21
NC
VP1
NC
CPRF
DGNDIF
IFIN
20
19
18
17
16
15
14
13
CPIF
DGNDRF
CPRF
DGNDIF
ADF4219L
RFIN
A
B
AGNDIF
NC
DGNDRF
RFINA
IFIN
IFIN
A
B
ADF4217L/
ADF4218L
RFIN
AGNDRF
REFIN
LE
RFIN
B
AGNDIF
LE
DATA
NC
AGNDRF
REFIN
NC
NC
DATA
NC
10
11 12
10
11 12
NC = NO INTERNAL CONNECT
NC = NO INTERNAL CONNECT
REV. C
–5–
ADF4217L/ADF4218L/ADF4219L
PIN FUNCTION DESCRIPTIONS
Mnemonic
DD1
Function
V
Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as
close as possible to this pin. VDD1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same
potential as VDD2.
VP1
Power Supply for the RF Charge Pump. This should be greater than or equal to VDD.
CPRF
Output from the RF Charge Pump. When enabled, this provides ICP to the external loop filter, which in turn
drives the external VCO.
DGNDRF
RFINA
Ground Pin for the RF Digital Circuitry
Input to the RF Prescaler. This low level input signal is normally ac-coupled to the external VCO.
RFINB
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.
AGNDRF
REFIN
Ground Pin for the RF Analog Circuitry
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of
100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled.
DGNDIF
Ground Pin for the IF Digital, Interface, and Control Circuitry
MUXOUT
This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, or the scaled Reference Frequency to
be accessed externally (Table V).
CLK
DATA
LE
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches; the latch is selected using the control bits.
AGNDIF
NC
Ground Pin for the IF Analog Circuitry
This pin is not connected internally (ADF4219L only).
IFINB
Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF (ADF4217L/ADF4218L only).
IFINA
DGNDIF
CPIF
Input to the IF Prescaler. This low level input signal is normally ac-coupled to the external VCO.
Ground Pin for the IF Digital, Interface, and Control Circuitry
Output from the IF Charge Pump. When enabled, this provides ICP to the external loop filter, which in turn drives
the external VCO.
VP2
Power Supply for the IF Charge Pump. This should be greater than or equal to VDD.
V
DD2
Positive Power Supply for the IF Interface and Oscillator Sections. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. VDD2 should have a value of between 2.6 V and 3.3 V.
VDD2 must have the same potential as VDD1.
–6–
REV. C
Typical Performance Characteristics–ADF4217L/ADF4218L/ADF4219L
0
0
–5
V
= 3V
V
= 3V, V = 5V
P
= 4mA
DD
= 3V
DD
REFERENCE
LEVEL = –11.2dBm
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
I
P
CP
PFD FREQUENCY = 200kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 10
–10
–15
–20
–25
–30
–35
–40
–78dBc
T
= 25؇C
A
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
–400kHz
–200kHz
1960MHz
FREQUENCY
200kHz
400kHz
RF INPUT FREQUENCY – GHz
TPC 1. Input Sensitivity, RF Input
TPC 4. Reference Spurs, RF Side
(1960 MHz, 200 kHz, 20 kHz)
10dB/DIVISION
–40
R
= –40dBc/Hz
rms NOISE = 1.2؇
L
0
–5
V
= 3V
= 3V
DD
–50
–60
V
P
–10
–15
–20
–25
–30
–35
–40
1.2؇ rms
–70
–80
–90
–100
–110
–120
–130
–140
100Hz
0.1
0.6
1.1
1.6
FREQUENCY OFFSET FROM 1960MHz CARRIER
1MHz
IF INPUT FREQUENCY – GHz
TPC 2. Input Sensitivity, IF Input
TPC 5. Integrated Phase Noise, RF Side
(1960 MHz, 200 kHz, 20 kHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= 3V, V = 5V
P
= 4mA
V
= 3V, V = 5V
P
= 4.0mA
DD
DD
REFERENCE
LEVEL = –11.2dBm
REFERENCE
I
I
CP
CP
LEVEL = –4.2dBm
PFD FREQUENCY = 200kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 20
PFD FREQUENCY = 200kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 20
–83dBc/Hz
–87dBc/Hz
–2kHz
–1kHz
1960MHz
FREQUENCY
1kHz
2kHz
–2kHz
–1kHz
900MHz
FREQUENCY
1kHz
2kHz
TPC 3. Phase Noise, RF Side (1960 MHz, 200 kHz, 20 kHz)
TPC 6. Phase Noise, IF Side (900 MHz, 200 kHz, 20 kHz)
REV. C
–7–
ADF4217L/ADF4218L/ADF4219L
0
–120
–130
–140
–150
–160
–170
–180
V
= 3V
V
= 3V, V = 5V
P
= 4.0mA
DD
REFERENCE
DD
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= 5V
LEVEL = –4.2dBm
I
P
CP
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10kHz
VIDEO BANDWIDTH = 10kHz
SWEEP = 1.9 SECONDS
AVERAGES = 20
–83dBc
–400kHz
–200kHz
900MHz
FREQUENCY
200kHz
400kHz
1
10
100
1000
10000
PHASE DETECTOR FREQUENCY – kHz
TPC 7. Reference Spurs, IF Side
(900 MHz, 200 kHz, 20 kHz)
TPC 10. Phase Noise Referred to CP Output vs.
PFD Frequency, IF Side
10dB/DIVISION
–40
R
= –40dBc/Hz
rms NOISE = 0.9؇
L
–60
V
= 3V
= 5V
DD
–50
–60
V
P
–70
–80
–70
–80
–90
–100
–110
–120
–130
–90
–140
100Hz
–100
–40
–20
0
20
40
60
80
100
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
TEMPERATURE – ؇C
TPC 8. Integrated Phase Noise, IF Side
(900 MHz, 200 kHz, 20 kHz)
TPC 11. Phase Noise vs. Temperature, RF Side
(1960 MHz, 200 kHz, 20 kHz)
–120
–60
V
= 3V
DD
V
= 3V
DD
= 5V
V
= 5V
P
V
P
–130
–140
–150
–160
–170
–180
–70
–80
–90
–100
1
10
100
1000
10000
–40
–20
0
20
40
60
80
100
PHASE DETECTOR FREQUENCY – kHz
TEMPERATURE – ؇C
TPC 9. Phase Noise Referred to CP Output vs.
PFD Frequency, RF Side
TPC 12. Phase Noise vs. Temperature, IF Side
(900 MHz, 200 kHz, 20 kHz)
–8–
REV. C
ADF4217L/ADF4218L/ADF4219L
6
4
V
= 5V
P
I
= 4mA
CP
2
0
–2
–4
–6
0
0.5
1.0
1.5
2.0
2.5
– V
3.0
3.5
4.0
4.5
5.0
V
CP
TPC 13. Charge Pump Output Characteristics
CIRCUIT DESCRIPTION
Reference Input Section
Prescaler
The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). This prescaler, operating at CML levels, takes
the clock from the IF/RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. It is
based on a synchronous 4/5 core.
The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches; SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
The prescaler is selectable. On the IF side, it can be set to either 8/9
(DB20 of the IF AB Counter Latch set to 0) or 16/17 (DB20 set
to 1). On the RF side of the ADF4217L/ADF4218L, it can be set
to 64/65 or 32/33. On the ADF4219L, the RF prescaler can be
set to 16/17 or 32/33. See Tables V, VI, VIII, and IX.
POWER-DOWN
CONTROL
50k⍀
NC
SW2
REF
IN
NC
TO R
COUNTER
BUFFER
A AND B COUNTERS
SW1
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The devices are guaranteed to work when the
prescaler output is 188 MHz or less. Typically they will work
with 250 MHz output from the prescaler.
SW3
NO
NC = NORMALLY CLOSED
NO = NORMALLY OPEN
Figure 2. Reference Input Stage
IF/RF Input Stage
The IF/RF input stage is shown in Figure 3. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
N = BP + A
TO PFD
11(13)-BIT
B COUNTER
LOAD
LOAD
1.6V
PRESCALER
P/P+1
BIAS
GENERATOR
FROM IF/RF
INPUT STAGE
AV
DD
6(5)-BIT
A COUNTER
MODULUS
CONTROL
500⍀
500⍀
RF
RF
A
B
IN
Figure 4. Reference Input Stage, A and B Counters
IN
AGND
Figure 3. IF/RF Input Stage
REV. C
–9–
ADF4217L/ADF4218L/ADF4219L
MUXOUT AND LOCK DETECT
The A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
The output multiplexer on the ADF4217L family allows the user
to access various internal points on the chip. The state of MUXOUT
is controlled by P3, P4, P11, and P12. See Tables IV and VII.
Figure 6 shows the MUXOUT section in block diagram form.
fVCO
=
P × B + A × f
/ R
(
)
[
]
REFIN
DV
DD
fVCO = Output frequency of external voltage controlled oscillator
(VCO).
P
= Preset modulus of dual modulus prescaler (8/9, 16/17, and
so on).
IF ANALOG LOCK DETECT
IF R COUNTER OUTPUT
B
A
= Preset divide ratio of binary 11-bit counter (ADF4217L/
ADF4218L), binary 13-bit counter (ADF4219L).
IF N COUNTER OUTPUT
MUXOUT
MUX
CONTROL
IF/RF ANALOG LOCK DETECT
RF R COUNTER OUTPUT
RF N COUNTER OUTPUT
RF ANALOG LOCK DETECT
= Preset divide ratio of binary 6-bit A counter (ADF4217L/
ADF4218L), binary 5-bit counter (ADF4219L).
fREF = Output frequency of the external reference frequency
IN
oscillator.
R
= Preset divide ratio of binary 14-bit programmable reference
counter (1 to 16383). The ADF4219L has an R divide
of 15 bits.
DGND
Figure 6. MUXOUT Circuit
Lock Detect
R COUNTER
MUXOUT can be programmed for analog lock detect. The
N-channel open-drain analog lock detect should be operated
with an external pull-up resistor of 10 kΩ nominal. When lock
has been detected, it is high with narrow low going pulses.
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed. The
extra R15 bit on the ADF4219L allows ratios from 1 to 32767.
INPUT SHIFT REGISTER
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic.
The functional block diagram for the ADF4217L family is shown
on page 1. The main blocks include a 22-bit input shift register,
a 14-bit R counter, and an N counter. The N counter is comprised
of a 6-bit A counter and an 11-bit B counter for the ADF4217L
and the ADF4218L. The 18-bit N counter on the ADF4219L
is comprised of a 13-bit B counter and a 5-bit A counter. Data
is clocked into the 22-bit shift register on each rising edge of
CLK. The data is clocked in MSB first. Data is transferred from
the shift register to one of four latches on the rising edge of LE.
The destination latch is determined by the state of the two con-
trol bits (C2, C1) in the shift register. These are the two LSBs,
DB1 and DB0, as shown in the timing diagram of Figure 1. The
truth table for these bits is shown in Table I.
V
P
CHARGE
PUMP
UP
HI
D1
Q1
U1
CLR1
R DIVIDER
DELAY
ELEMENT
CP
U3
Table I. C2, C1 Truth Table
Control Bits
C2 C1
Data Latch
CLR2
D2 Q2
0
0
1
1
0
1
0
1
IF R Counter
IF AB Counter (and Prescaler Select)
RF R Counter
DOWN
HI
N DIVIDER
U2
CPGND
RF AB Counter (and Prescaler Select)
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 5. PFD Simplified Schematic
–10–
REV. C
ADF4217L/ADF4218L/ADF4219L
Table II. ADF4217L/ADF4218L Family Latch Summary
IF REFERENCE COUNTER LATCH
CONTROL
BITS
14-BIT REFERENCE COUNTER, R
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P4
P3
P2
P5
P1
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1 C2 (0) C1 (0)
IF AB COUNTER LATCH
CONTROL
BITS
NOT
USED
11-BIT B COUNTER
6-BIT A COUNTER
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P7
P6
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A6
A5
A4
A3
A2
A1 C2 (0) C1 (1)
RF REFERENCE COUNTER LATCH
CONTROL
BITS
14-BIT REFERENCE COUNTER, R
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P12
P11
P10
P13
P9
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1 C2 (1) C1 (0)
RF AB COUNTER LATCH
CONTROL
BITS
NOT
USED
11-BIT B COUNTER
6-BIT A COUNTER
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P16 P14 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (1) C1 (1)
REV. C
–11–
ADF4217L/ADF4218L/ADF4219L
Table III. ADF4219L Family Latch Summary
IF REFERENCE COUNTER LATCH
CONTROL
BITS
15-BIT REFERENCE COUNTER, R
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R15
P4
P3
P2
P5
P1
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1 C2 (0) C1 (0)
IF AB COUNTER LATCH
CONTROL
BITS
13-BIT B COUNTER
5-BIT A COUNTER
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P7
P6
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A5
A4
A3
A2
A1 C2 (0) C1 (1)
RF REFERENCE COUNTER LATCH
CONTROL
BITS
15-BIT REFERENCE COUNTER, R
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P13
P12
P11
P10
P9
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1 C2 (1) C1 (0)
RF AB COUNTER LATCH
CONTROL
BITS
13-BIT B COUNTER
5-BIT A COUNTER
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P16 P14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A5 A4 A3 A2 A1 C2 (1) C1 (1)
–12–
REV. C
ADF4217L/ADF4218L/ADF4219L
Table IV. ADF4217L/ADF4218L/ADF4219L IF Reference Counter Latch Map
IF REFERENCE COUNTER LATCH
CONTROL
BITS
14-BIT REFERENCE COUNTER, R
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P4
P3
P2
P5
P1
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1 C2 (0) C1 (0)
R15
R14
R13
R12
..........
R3
R2
R1
DIVIDE RATIO
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
0
0
0
1
.
0
1
1
0
.
1
0
1
0
.
1
2
3
4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
0
0
0
.
1
1
1
1
.
1
1
1
1
.
1
1
1
1
.
1
1
1
1
.
0
0
1
1
.
0
1
0
1
.
16380
16381
16382
16383
.
1
1
1
1
1
1
1
32767
P1
PD POLARITY
0
1
NEGATIVE
POSITIVE
I
P5
CP
0
1
1.0mA
4.0mA
CHARGE PUMP
OUTPUT
P2
0
1
NORMAL
THREE-STATE
P12
P11
FROM RF R LATCH
P4
0
P3
0
MUXOUT
LOGIC LOW STATE
IF ANALOG LOCK DETECT
0
0
0
0
0
0
1
1
1
0
0
X
X
1
1
X
X
0
0
1
1
0
IF REFERENCE DIVIDER OUTPUT
IF N DIVIDER OUTPUT
1
1
0
0
RF ANALOG LOCK DETECT
RF/IF ANALOG LOCK DETECT
RF REFERENCE DIVIDER
RF N DIVIDER
0
1
0
0
0
1
1
0
FAST LOCK OUTPUT SWITCH ON
AND CONNECTEDTO MUXOUT
1
1
1
0
1
1
1
1
1
1
0
1
IF COUNTER RESET
RF COUNTER RESET
IF AND RF COUNTER RESET
REV. C
–13–
ADF4217L/ADF4218L/ADF4219L
Table V. ADF4217L/ADF4218L IF AB Counter Latch Map
IF AB COUNTER LATCH
CONTROL
BITS
NOT
USED
11-BIT B COUNTER
6-BIT A COUNTER
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1)
A6
0
0
0
0
.
A5
0
0
0
0
.
A4
0
0
0
0
.
A3
0
0
0
0
.
A2
A1
A COUNTER DIVIDE RATIO
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
0
1
62
63
B11
B10
B9
..........
B3
B2
B1
B COUNTER DIVIDE RATIO
..........
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
1
1
.
1
0
1
.
NOT ALLOWED
..........
..........
..........
..........
..........
..........
..........
..........
..........
NOT ALLOWED
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
2044
2045
2046
2047
P6
IF PRESCALER
0
1
8/9
16/17
P7
IF SECTION
0
1
NORMAL OPERATION
POWER-DOWN
N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE
GREATERTHAN OR EQUALTO A. TO ENSURE CONTINUOUSLY
2
ADJACENT VALUES OF N, N
IS (P – P).
MIN
–14–
REV. C
ADF4217L/ADF4218L/ADF4219L
Table VI. ADF4219L IF AB Counter Latch Map
IF AB COUNTER LATCH
CONTROL
BITS
13-BIT B COUNTER
5-BIT A COUNTER
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P7 P6 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A5 A4 A3 A2 A1 C2 (0) C1 (1)
A5
A4
A3
0
A2
A1
A COUNTER DIVIDE RATIO
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
0
0
0
.
1
.
1
.
1
.
1
.
0
.
30
1
1
1
1
1
31
B13
B12
B11
..........
B3
B2
B1
B COUNTER DIVIDE RATIO
..........
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
1
1
.
1
0
1
.
NOT ALLOWED
..........
..........
..........
..........
..........
..........
..........
..........
..........
NOT ALLOWED
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8188
8189
8190
8191
P6
IF PRESCALER
0
1
8/9
16/17
P7
IF SECTION
0
1
NORMAL OPERATION
POWER-DOWN
N = BP + A, P IS PRESCALER VALUE SET BY P6.
B MUST BE GREATERTHAN OR EQUALTO A.
2
FOR CONTIGUOUSVALUES OF N, N
IS (P – P).
MIN
REV. C
–15–
ADF4217L/ADF4218L/ADF4219L
Table VII. RF Reference Counter Latch Map
RF REFERENCE COUNTER LATCH
CONTROL
BITS
14-BIT REFERENCE COUNTER, R
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P12
P11
P10
P13
P9
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1 C2 (1) C1 (0)
R15
R14
R13
R12
..........
R3
R2
R1
DIVIDE RATIO
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
0
0
0
1
.
0
1
1
0
.
1
0
1
0
.
1
2
3
4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
0
0
0
.
1
1
1
1
.
1
1
1
1
.
1
1
1
1
.
1
1
1
1
.
0
0
1
1
.
0
1
0
1
.
16380
16381
16382
16383
.
P9
PD POLARITY
0
1
NEGATIVE
POSITIVE
1
1
1
1
1
1
1
32767
I
P13
CP
0
1
1.0mA
4.0mA
CHARGE PUMP
OUTPUT
P10
0
1
NORMAL
THREE-STATE
P4
P3
FROM RF R LATCH
P12
P11
MUXOUT
LOGIC LOW STATE
IF ANALOG LOCK DETECT
0
0
0
0
0
0
1
1
1
0
0
X
X
1
1
X
X
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
IF REFERENCE DIVIDER OUTPUT
IF N DIVIDER OUTPUT
RF ANALOG LOCK DETECT
RF/IF ANALOG LOCK DETECT
RF REFERENCE DIVIDER
RF N DIVIDER
FAST LOCK OUTPUT SWITCH ON
AND CONNECTEDTO MUXOUT
1
1
1
0
1
1
1
1
1
1
0
1
IF COUNTER RESET
RF COUNTER RESET
IF AND RF COUNTER RESET
–16–
REV. C
ADF4217L/ADF4218L/ADF4219L
Table VIII. ADF4217L/ADF4218L RF AB Counter Latch Map
RF AB COUNTER LATCH
CONTROL
BITS
NOT
USED
11-BIT B COUNTER
6-BIT A COUNTER
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P16 P14 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (1) C1 (1)
A6
0
0
0
0
.
A5
0
0
0
0
.
A4
0
0
0
0
.
A3
0
0
0
0
.
A2
A1
A COUNTER DIVIDE RATIO
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
0
1
62
63
B11
B10
B9
..........
B3
B2
B1
B COUNTER DIVIDE RATIO
..........
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
0
0
0
1
.
0
1
1
0
.
1
0
1
0
.
NOT ALLOWED
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
NOT ALLOWED
3
4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
2044
2045
2046
2047
RF PRESCALER
ADF4217L
RF PRESCALER
ADF4218L
P14
0
1
64/65
32/33
32/33
64/65
P16
RF SECTION
0
1
NORMAL OPERATION
POWER-DOWN
N = BP + A, P IS PRESCALERVALUE SET BY P6, B MUST BE
GREATER THAN OR EQUALTO A. TO ENSURE CONTINUOUSLY
2
ADJACENT VALUES OF N
؋
F , N
IS (P – P).
MIN
REF
REV. C
–17–
ADF4217L/ADF4218L/ADF4219L
Table IX. ADF4219L RF AB Counter Latch Map
RF AB COUNTER LATCH
CONTROL
BITS
13-BIT B COUNTER
5-BIT A COUNTER
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P16
P14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A5
A4
A3
A2
A1 C2 (1) C1 (1)
A5
A4
0
0
0
0
.
A3
A2
0
0
1
1
.
A1
A COUNTER DIVIDE RATIO
0
0
0
0
.
0
0
0
0
.
0
1
0
1
.
0
1
2
3
.
1
1
1
1
1
1
1
1
0
1
30
31
B13
B12
B11
..........
B3
B2
B1
B COUNTER DIVIDE RATIO
..........
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
0
0
0
1
.
0
1
1
0
.
1
0
1
0
.
NOT ALLOWED
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
NOT ALLOWED
3
4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8188
8189
8190
8191
P14
IF PRESCALER
0
1
16/17
32/33
P16
IF SECTION
0
1
NORMAL OPERATION
POWER-DOWN
N = BP + A, P IS PRESCALERVALUE SET BY P14.
B MUST BE GREATERTHAN OR EQUALTO A.
2
FOR CONTIGUOUSVALUES OF N, N
A MUST BE LESSTHAN P.
IS (P –P).
MIN
–18–
REV. C
ADF4217L/ADF4218L/ADF4219L
PROGRAM MODES
Tables IV and VII show how to set up the program modes in the
ADF4217L family. The following should be noted:
The REFIN oscillator circuit is only disabled if both the IF and
RF power-downs are set.
The input register and latches remain active and are capable of
loading and latching data during all the power-down modes.
1. IF and RF Analog Lock Detect indicate when the PLL is in
lock. When the loop is locked, and either IF or RF Analog
Lock Detect is selected, the MUXOUT pin will show a logic
high with narrow low-going pulses. When the IF/RF Analog
Lock Detect is chosen, the locked condition is indicated only
when both IF and RF loops are locked.
The IF/RF section of the devices will return to normal powered-up
operation immediately upon LE latching a “0” to the appropriate
power-down bit.
IF SECTION
2. The IF Counter Reset Mode resets the R and N counters in
the IF section and also puts the IF charge pump into three-
state. The RF Counter Reset Mode resets the R and N counters
in the RF section and also puts the RF charge pump into
three-state. The IF and RF Counter Reset Mode does both
of the above.
Programmable IF Reference (R) Counter
If control bits C2, C1 are 0, 0, then the data is transferred from
the input shift register to the 14-bit IF R counter. Table IV shows
the input shift register data format for the IF R counter and the
possible divide ratios.
IF Phase Detector Polarity
Upon removal of the reset bits, the N counter resumes counting
in close alignment with the R counter (maximum error is one
prescaler output cycle).
P1 sets the IF phase detector polarity. When the IF VCO char-
acteristics are positive, this should be set to “1.” When they are
negative, it should be set to “0.” See Table IV.
3. The Fastlock Mode uses MUXOUT to switch a second loop
filter damping resistor to ground during Fastlock operation.
Activation of Fastlock occurs whenever RF CP Gain in the
RF Reference counter is set to 1.
IF Charge Pump Three-State
P2 puts the IF charge pump into three-state mode when programmed
to a “1.” It should be set to “0” for normal operation. See Table IV.
IF Charge Pump Currents
P5 sets the IF charge pump current. With P5 set to “0,” ICP is
1.0 mA. With P5 set to “1,” ICP is 4.0 mA. See Table IV.
POWER-DOWN
It is possible to program the ADF4217L family for either synchro-
nous or asynchronous power-down on either the IF or RF side.
Programmable IF AB Counter
If control bits C2, C1 are 0, 1, the data in the input register is
used to program the IF AB counter. For the ADF4217L/ADF4218L,
the AB counter consists of a 6-bit swallow counter (A counter)
and 11-bit programmable counter (B counter). Table V shows
the input register data format for programming the IF AB counter
and the possible divide ratios. The ADF4219L N counter consists
of an 13-bit B counter and 5-bit A counter. Table VI shows the
input register data format for programming the ADF4219L.
Synchronous IF Power-Down
Programming a “1” to P7 of the ADF4217L family will initiate a
power-down. If P2 of the ADF4217L family has been set to “0”
(normal operation), then a synchronous power-down is conducted.
The device will automatically put the charge pump into three-
state and then complete the power-down.
Asynchronous IF Power-Down
If P2 of the ADF4217L family has been set to “1” (three-state the
IF charge pump) and P7 is subsequently set to “1,” an asynchro-
nous power-down is conducted. The device will go into power-down
on the rising edge of LE, which latches the “1” to the IF Power-
Down Bit (P7).
IF Prescaler Value
P6 in the IF AB counter latch sets the IF prescaler value. For
the ADF4217L family, 8/9 or 16/17 prescalers are available. See
Table V and Table VI.
IF Power-Down
Tables IV, V, and VI show the power-down bits in the ADF4217L
family. See the Power-Down section for a functional description.
Synchronous RF Power-Down
Programming a “1” to P16 of the ADF4217L family will initiate a
power-down. If P10 of the ADF4217L family has been set to “0”
(normal operation), a synchronous power-down is conducted. The
device will automatically put the charge pump into three-state
and then complete the power-down.
RF SECTION
Programmable RF Reference (R) Counter
If control bits C2, C1 are 1, 0, the data is transferred from the
input shift register to the 14-bit RF R counter. Table VII shows the
input shift register data format for the RF R counter and the
possible divide ratios.
Asynchronous RF Power-Down
If P10 of the ADF4217L family has been set to “1” (three-state
the RF charge pump) and P16 is subsequently set to “1,” an
asynchronous power-down is conducted. The device will go into
power-down on the rising edge of LE, which latches the “1” to
the RF Power-Down Bit (P16).
RF Phase Detector Polarity
P9 sets the RF phase detector polarity. When the RF VCO
characteristics are positive, this should be set to “1.” When they
are negative, it should be set to “0.” See Table VII.
Activation of either synchronous or asynchronous power-down
forces the IF/RF loop’s R and N dividers to their load state
conditions, and the IF/RF input section is debiased to a high
impedance state.
RF Charge Pump Three-State
P10 puts the RF charge pump into three-state mode when programmed
to a “1.” It should be set to “0” for normal operation. See Table VII.
REV. C
–19–
ADF4217L/ADF4218L/ADF4219L
RF Program Modes
Tables IV and VII show how to set up the RF program modes.
program the new frequency and to initiate Fastlock. To come
out of Fastlock, the RF CP Gain Bit should be returned to “0”
and the extra damping resistor switched out.
RF Charge Pump Currents
P13 sets the RF charge pump current. With P13 set to “0,” ICP is
1.0 mA. With P13 set to “1,” ICP is 4.0 mA. See Table VII.
APPLICATIONS SECTION
Local Oscillator for GSM Handset Receiver
The diagram in Figure 7 shows the ADF4217L/ADF4218L/
ADF4219L being used in a classic superheterodyne receiver to
provide the required LOs (local oscillators). In this circuit, the
Programmable RF AB Counter
If control bits C2, C1 are 1, 1, the data in the input register is used
to program the RF AB counter. For the ADF4217L/ADF4218L,
the AB counter consists of a 6-bit swallow counter (A counter)
and 11-bit programmable counter (B counter). Table VIII shows
the input register data format for programming the RF AB counter
and the possible divide ratios. The ADF4219L N counter consists
of a 13-bit B counter and 5-bit A counter. Table IX shows the
input register data format for programming the ADF4219L.
reference input signal is applied to the circuit at fREF and is
IN
being generated by a 13 MHz temperature controlled crystal
oscillator. In order to have a channel spacing of 200 kHz (the GSM
standard), the reference input must be divided by 65, using the
on-chip reference counter.
The RF output frequency range is 1050 MHz to 1085 MHz.
Loop filter component values are chosen so that the loop band-
width is 20 kHz. The synthesizer is set up for a charge pump
current of 4.0 mA, and the VCO sensitivity is 15.6 MHz/V.
The IF output is fixed at 125 MHz. The IF loop bandwidth is
chosen to be 20 kHz with a channel spacing of 200 kHz. Loop
filter component values are chosen accordingly.
RF Prescaler Value
P14 in the RF AB counter latch sets the RF prescaler value. For
the ADF4217L and ADF4218L family, 32/33 or 64/65 prescalers
are available. See Table VIII. For the ADF4219L, the prescaler
may be 16/17 or 32/33. See Table IX.
RF Power-Down
Tables VII, VIII, and IX show the power-down bits (Charge
Pump Bit used for asynchronous in the ADF4217L family). See
the Power-Down section for a functional description.
Local Oscillator for WCDMA Receiver
Figure 8 shows the ADF4217L/ADF4218L/ADF4219L being
used to generate the local oscillator frequencies in a wideband
CDMA (WCDMA) system.
RF Fastlock
The RF CP Gain Bit (P13) of the RF N Register in the ADF4217L
family is the Fastlock Enable Bit. The loop filter should be
designed for the lower current setting. When Fastlock is enabled,
the RF CP current is set to maximum value. Also, an extra loop
filter damping resistor to ground is switched in using the
MUXOUT pin, thus compensating for the change of loop
dynamics when in Fastlock Mode. Since the RF CP Gain Bit is
contained in the RF N counter, only one write is needed to
The RF output range needed is 1720 MHz to 1780 MHz. The
VCO190-1750T from Varil-L will accomplish that. Channel spacing
is 200 kHz, the loop bandwidth of the loop filter is 20 kHz, and the
VCO sensitivity is 32 MHz/V. A charge pump current of 4.0 mA
is used and the desired phase margin for the loop is 45 degrees.
The IF output is fixed at 200 MHz. The VCO190-200T is used.
It has a sensitivity of 11.5 MHz/V. Channel spacing and loop
bandwidth are chosen the same as the RF side.
RF
IF
OUT
OUT
V
V
V
P
P
DD
100pF
100pF
18⍀
18⍀
18⍀
V 2
V
2
V 1
DD
V 1
P
100pF
100pF
P
DD
3.3k⍀
3.3k⍀
18⍀
18⍀
V
V
CC
CC
CP
CP
RF
IF
VCO190-125T
VCO190-1068U
18⍀
620pF
400pF
620pF
620pF
9k⍀
5.8k⍀
ADF4217L/
ADF4218L/
ADF4219L
3.9nF
6nF
LOCK
DETECT
MUXOUT
100pF
100pF
RF
IN
IF
IN
V
DD
REF
51⍀
IN
51⍀
CLK
DATA
LE
SPI COMPATIBLE SERIAL BUS
10MHz
TCXO
DECOUPLING CAPACITORS (22F/10pF) ONV , V OF THE ADF4217L/ADF4218L/ADF4219L.
DD
P
THE TCXO AND ONV
OFTHE VCOs HAVE BEEN OMITTED FROMTHE DIAGRAMTO AID CLARITY.
CC
Figure 7. Local Oscillator Design for GSM Receiver
–20–
REV. C
ADF4217L/ADF4218L/ADF4219L
RF
IF
OUT
OUT
V
V
V
P
P
DD
100pF
100pF
18⍀
18⍀
18⍀
18⍀
V 2
V
2
V 1
DD
V 1
P
100pF
100pF
P
DD
3.3k⍀
3.3k⍀
18⍀
18⍀
V
V
CC
CC
CP
CP
IF
RF
VCO190-200T
VCO190-1750T
450pF
2.4pF
760pF
690pF
1.5k⍀
4.7k⍀
ADF4217L/
ADF4218L/
ADF4219L
7.5nF
24nF
LOCK
DETECT
MUXOUT
100pF
100pF
RF
IN
IF
IN
REF
IN
51⍀
51⍀
CLK
DATA
LE
SPI COMPATIBLE SERIAL BUS
10MHz
TCXO
DECOUPLING CAPACITORS (22F/10pF) ONV , V OF THE ADF4217L/ADF4218L/ADF4219L.
DD
P
THETCXO AND ONV
OFTHE VCOs HAVE BEEN OMITTED FROMTHE DIAGRAMTO AID CLARITY.
CC
Figure 8. Local Oscillator Design for WCDMA System
In this circuit, the reference input signal is applied to the circuit
at REFIN by a 10 MHz TCXO (temperature controlled crystal
oscillator).
SCLK
MOSI
CLK
DATA
LE
ADF4217L/
ADF4218L/
ADF4219L
ADuC812
INTERFACING
I/O PORTS
The ADF4217L/ADF4218L/ADF4219L family has a simple
SPI® compatible serial interface for writing to the device. SCLK,
SDATA, and LE control the data transfer. When LE (latch
enable) goes high, the 22 bits that have been clocked into the
input register on each rising edge of SCLK will get transferred
to the appropriate latch. See Figure 1 for the timing diagram
and Table I for the latch truth table.
MUXOUT
(LOCK DETECT)
Figure 9. ADuC812 to ADF421xL Interface
ADSP2181 Interface
Figure 10 shows the interface between the ADF4217L family and
the ADSP-21xx digital signal processor. As previously discussed,
the ADF4217L family needs a 22-bit serial word for each latch
write. The easiest way to accomplish this using the ADSP-21xx
family is to use the autobuffered transmit mode of operation
with alternate framing. This provides a means for transmitting
an entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use three memory loca-
tions for each 22-bit word. To program each 22-bit latch, store
the three 8-bit bytes, enable the Autobuffered Mode, and then
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 909 kHz
or one update every 1.1 µs. This is certainly more than adequate
for systems that will have typical lock times in hundreds of
microseconds.
ADuC812 Interface
Figure 9 shows the interface to the ADuC812 MicroConverter®.
Since the ADuC812 is based on an 8051 core, this interface can
be used with any 8051 based microcontroller. The MicroConverter
is set up for SPI Master Mode with CPHA = 0. To initiate the
operation, the I/O port driving LE is brought low. Each latch of
the ADF421xL family needs a 22-bit word. This is accomplished
by writing three 8-bit bytes from the MicroConverter to the
device. When the third byte has been written, the LE input should
be brought high to complete the transfer.
SCLK
DT
CLK
DATA
LE
TFS
ADF4217L/
ADF4218L/
ADF4219L
ADSP-21xx
On first applying power to the ADF4217L family, it needs four
writes (one each to the R counter latch and the AB counter latch
for both RF1 and RF2 side) for the output to become active.
MUXOUT
(LOCK DETECT)
I/O FLAG
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be about
180 kHz.
Figure 10. ADSP-21xx to ADF421xL Interface
REV. C
–21–
ADF4217L/ADF4218L/ADF4219L
OUTLINE DIMENSIONS
20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8؇
0؇
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AC
24-Leadless Chip Array CASON [LGA]
(CC-24)
Dimensions shown in millimeters
SEATING PLANE
1.20 MAX
4.50 BSC
VIEW A
3.50 BSC
TOP VIEW
PIN 1
INDEX AREA
1.15
0.90
0.05 MAX
0.50 BSC
TYP
0.10 TYP
1
0.60
0.40
24
0.33
0.30
0.25
VIEW A
BOTTOMVIEW
COMPLIANTTO JEDEC STANDARDS MO-208, ECEA-1
–22–
REV. C
ADF4217L/ADF4218L/ADF4219L
Revision History
Location
Page
5/03—Data Sheet changed from REV. B to REV. C.
Change to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Change to TPC 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Change to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7/02—Data Sheet changed from REV. A to REV. B.
Change to ADF4219L SENSITIVITY SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6/02—Data Sheet changed from REV. 0 to REV. A.
Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to CASON package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REV. C
–23–
–24–
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